| // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals all --include-generated-funcs --version 4 |
| // RUN: %clang_cc1 -triple riscv64-linux-gnu -target-feature +i -emit-llvm -o - %s | FileCheck %s |
| |
| __attribute__((target_clones("default", "arch=+m"))) int foo1(void) { |
| return 1; |
| } |
| __attribute__((target_clones("default", "arch=+zbb", "arch=+m"))) int foo2(void) { return 2; } |
| __attribute__((target_clones("default", "arch=+zbb,+c"))) int foo3(void) { return 3; } |
| __attribute__((target_clones("default", "arch=+zbb,+v"))) int |
| foo4(void) { |
| return 4; |
| } |
| __attribute__((target_clones("default"))) int foo5(void) { return 5; } |
| __attribute__((target_clones("default", "arch=+zvkt"))) int foo6(void) { return 2; } |
| |
| __attribute__((target_clones("default", "arch=+zbb", "arch=+zba", "arch=+zbb,+zba"))) int foo7(void) { return 2; } |
| __attribute__((target_clones("default", "arch=+zbb;priority=2", "arch=+zba;priority=1", "arch=+zbb,+zba;priority=3"))) int foo8(void) { return 2; } |
| __attribute__((target_clones("default", "arch=+zbb;priority=1", "priority=2;arch=+zba", "priority=3;arch=+zbb,+zba"))) int foo9(void) { return 2; } |
| |
| |
| int bar() { return foo1() + foo2() + foo3() + foo4() + foo5() + foo6() + foo7() + foo8() + foo9(); } |
| |
| //. |
| // CHECK: @__riscv_feature_bits = external dso_local global { i32, [2 x i64] } |
| // CHECK: @foo1.ifunc = weak_odr alias i32 (), ptr @foo1 |
| // CHECK: @foo2.ifunc = weak_odr alias i32 (), ptr @foo2 |
| // CHECK: @foo3.ifunc = weak_odr alias i32 (), ptr @foo3 |
| // CHECK: @foo4.ifunc = weak_odr alias i32 (), ptr @foo4 |
| // CHECK: @foo5.ifunc = weak_odr alias i32 (), ptr @foo5 |
| // CHECK: @foo6.ifunc = weak_odr alias i32 (), ptr @foo6 |
| // CHECK: @foo7.ifunc = weak_odr alias i32 (), ptr @foo7 |
| // CHECK: @foo8.ifunc = weak_odr alias i32 (), ptr @foo8 |
| // CHECK: @foo9.ifunc = weak_odr alias i32 (), ptr @foo9 |
| // CHECK: @foo1 = weak_odr ifunc i32 (), ptr @foo1.resolver |
| // CHECK: @foo2 = weak_odr ifunc i32 (), ptr @foo2.resolver |
| // CHECK: @foo3 = weak_odr ifunc i32 (), ptr @foo3.resolver |
| // CHECK: @foo4 = weak_odr ifunc i32 (), ptr @foo4.resolver |
| // CHECK: @foo5 = weak_odr ifunc i32 (), ptr @foo5.resolver |
| // CHECK: @foo6 = weak_odr ifunc i32 (), ptr @foo6.resolver |
| // CHECK: @foo7 = weak_odr ifunc i32 (), ptr @foo7.resolver |
| // CHECK: @foo8 = weak_odr ifunc i32 (), ptr @foo8.resolver |
| // CHECK: @foo9 = weak_odr ifunc i32 (), ptr @foo9.resolver |
| //. |
| // CHECK-LABEL: define dso_local signext i32 @foo1.default( |
| // CHECK-SAME: ) #[[ATTR0:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 1 |
| // |
| // |
| // CHECK-LABEL: define dso_local signext i32 @foo1._m( |
| // CHECK-SAME: ) #[[ATTR1:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 1 |
| // |
| // |
| // CHECK-LABEL: define weak_odr ptr @foo1.resolver() comdat { |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) |
| // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 |
| // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 4096 |
| // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 4096 |
| // CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] |
| // CHECK: resolver_return: |
| // CHECK-NEXT: ret ptr @foo1._m |
| // CHECK: resolver_else: |
| // CHECK-NEXT: ret ptr @foo1.default |
| // |
| // |
| // CHECK-LABEL: define dso_local signext i32 @foo2.default( |
| // CHECK-SAME: ) #[[ATTR0]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK-LABEL: define dso_local signext i32 @foo2._zbb( |
| // CHECK-SAME: ) #[[ATTR2:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK-LABEL: define dso_local signext i32 @foo2._m( |
| // CHECK-SAME: ) #[[ATTR1]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK-LABEL: define weak_odr ptr @foo2.resolver() comdat { |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) |
| // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 |
| // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 268435456 |
| // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 268435456 |
| // CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] |
| // CHECK: resolver_return: |
| // CHECK-NEXT: ret ptr @foo2._zbb |
| // CHECK: resolver_else: |
| // CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 |
| // CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 4096 |
| // CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 4096 |
| // CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] |
| // CHECK: resolver_return1: |
| // CHECK-NEXT: ret ptr @foo2._m |
| // CHECK: resolver_else2: |
| // CHECK-NEXT: ret ptr @foo2.default |
| // |
| // |
| // CHECK-LABEL: define dso_local signext i32 @foo3.default( |
| // CHECK-SAME: ) #[[ATTR0]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 3 |
| // |
| // |
| // CHECK-LABEL: define dso_local signext i32 @foo3._c_zbb( |
| // CHECK-SAME: ) #[[ATTR3:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 3 |
| // |
| // |
| // CHECK-LABEL: define weak_odr ptr @foo3.resolver() comdat { |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) |
| // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 |
| // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 268435460 |
| // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 268435460 |
| // CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] |
| // CHECK: resolver_return: |
| // CHECK-NEXT: ret ptr @foo3._c_zbb |
| // CHECK: resolver_else: |
| // CHECK-NEXT: ret ptr @foo3.default |
| // |
| // |
| // CHECK-LABEL: define dso_local signext i32 @foo4.default( |
| // CHECK-SAME: ) #[[ATTR0]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 4 |
| // |
| // |
| // CHECK-LABEL: define dso_local signext i32 @foo4._v_zbb( |
| // CHECK-SAME: ) #[[ATTR4:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 4 |
| // |
| // |
| // CHECK-LABEL: define weak_odr ptr @foo4.resolver() comdat { |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) |
| // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 |
| // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 270532608 |
| // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 270532608 |
| // CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] |
| // CHECK: resolver_return: |
| // CHECK-NEXT: ret ptr @foo4._v_zbb |
| // CHECK: resolver_else: |
| // CHECK-NEXT: ret ptr @foo4.default |
| // |
| // |
| // CHECK-LABEL: define dso_local signext i32 @foo5.default( |
| // CHECK-SAME: ) #[[ATTR0]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 5 |
| // |
| // |
| // CHECK-LABEL: define weak_odr ptr @foo5.resolver() comdat { |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) |
| // CHECK-NEXT: ret ptr @foo5.default |
| // |
| // |
| // CHECK-LABEL: define dso_local signext i32 @foo6.default( |
| // CHECK-SAME: ) #[[ATTR0]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK-LABEL: define dso_local signext i32 @foo6._zvkt( |
| // CHECK-SAME: ) #[[ATTR5:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK-LABEL: define weak_odr ptr @foo6.resolver() comdat { |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) |
| // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 |
| // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 576460752303423488 |
| // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 576460752303423488 |
| // CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] |
| // CHECK: resolver_return: |
| // CHECK-NEXT: ret ptr @foo6._zvkt |
| // CHECK: resolver_else: |
| // CHECK-NEXT: ret ptr @foo6.default |
| // |
| // |
| // CHECK-LABEL: define dso_local signext i32 @foo7.default( |
| // CHECK-SAME: ) #[[ATTR0]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK-LABEL: define dso_local signext i32 @foo7._zbb( |
| // CHECK-SAME: ) #[[ATTR2]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK-LABEL: define dso_local signext i32 @foo7._zba( |
| // CHECK-SAME: ) #[[ATTR6:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK-LABEL: define dso_local signext i32 @foo7._zba_zbb( |
| // CHECK-SAME: ) #[[ATTR7:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK-LABEL: define weak_odr ptr @foo7.resolver() comdat { |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) |
| // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 |
| // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 268435456 |
| // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 268435456 |
| // CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] |
| // CHECK: resolver_return: |
| // CHECK-NEXT: ret ptr @foo7._zbb |
| // CHECK: resolver_else: |
| // CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 |
| // CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 134217728 |
| // CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 134217728 |
| // CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] |
| // CHECK: resolver_return1: |
| // CHECK-NEXT: ret ptr @foo7._zba |
| // CHECK: resolver_else2: |
| // CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 |
| // CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], 402653184 |
| // CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 402653184 |
| // CHECK-NEXT: br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]] |
| // CHECK: resolver_return3: |
| // CHECK-NEXT: ret ptr @foo7._zba_zbb |
| // CHECK: resolver_else4: |
| // CHECK-NEXT: ret ptr @foo7.default |
| // |
| // |
| // CHECK-LABEL: define dso_local signext i32 @foo8.default( |
| // CHECK-SAME: ) #[[ATTR0]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK-LABEL: define dso_local signext i32 @foo8._zbb( |
| // CHECK-SAME: ) #[[ATTR2]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK-LABEL: define dso_local signext i32 @foo8._zba( |
| // CHECK-SAME: ) #[[ATTR6]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK-LABEL: define dso_local signext i32 @foo8._zba_zbb( |
| // CHECK-SAME: ) #[[ATTR7]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK-LABEL: define weak_odr ptr @foo8.resolver() comdat { |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) |
| // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 |
| // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 402653184 |
| // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 402653184 |
| // CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] |
| // CHECK: resolver_return: |
| // CHECK-NEXT: ret ptr @foo8._zba_zbb |
| // CHECK: resolver_else: |
| // CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 |
| // CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 268435456 |
| // CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 268435456 |
| // CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] |
| // CHECK: resolver_return1: |
| // CHECK-NEXT: ret ptr @foo8._zbb |
| // CHECK: resolver_else2: |
| // CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 |
| // CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], 134217728 |
| // CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 134217728 |
| // CHECK-NEXT: br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]] |
| // CHECK: resolver_return3: |
| // CHECK-NEXT: ret ptr @foo8._zba |
| // CHECK: resolver_else4: |
| // CHECK-NEXT: ret ptr @foo8.default |
| // |
| // |
| // CHECK-LABEL: define dso_local signext i32 @foo9.default( |
| // CHECK-SAME: ) #[[ATTR0]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK-LABEL: define dso_local signext i32 @foo9._zbb( |
| // CHECK-SAME: ) #[[ATTR2]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK-LABEL: define dso_local signext i32 @foo9._zba( |
| // CHECK-SAME: ) #[[ATTR6]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK-LABEL: define dso_local signext i32 @foo9._zba_zbb( |
| // CHECK-SAME: ) #[[ATTR7]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK-LABEL: define weak_odr ptr @foo9.resolver() comdat { |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) |
| // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 |
| // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 402653184 |
| // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 402653184 |
| // CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] |
| // CHECK: resolver_return: |
| // CHECK-NEXT: ret ptr @foo9._zba_zbb |
| // CHECK: resolver_else: |
| // CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 |
| // CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 134217728 |
| // CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 134217728 |
| // CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] |
| // CHECK: resolver_return1: |
| // CHECK-NEXT: ret ptr @foo9._zba |
| // CHECK: resolver_else2: |
| // CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 |
| // CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], 268435456 |
| // CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 268435456 |
| // CHECK-NEXT: br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]] |
| // CHECK: resolver_return3: |
| // CHECK-NEXT: ret ptr @foo9._zbb |
| // CHECK: resolver_else4: |
| // CHECK-NEXT: ret ptr @foo9.default |
| // |
| // |
| // CHECK-LABEL: define dso_local signext i32 @bar( |
| // CHECK-SAME: ) #[[ATTR0]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[CALL:%.*]] = call signext i32 @foo1() |
| // CHECK-NEXT: [[CALL1:%.*]] = call signext i32 @foo2() |
| // CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] |
| // CHECK-NEXT: [[CALL2:%.*]] = call signext i32 @foo3() |
| // CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]] |
| // CHECK-NEXT: [[CALL4:%.*]] = call signext i32 @foo4() |
| // CHECK-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CALL4]] |
| // CHECK-NEXT: [[CALL6:%.*]] = call signext i32 @foo5() |
| // CHECK-NEXT: [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CALL6]] |
| // CHECK-NEXT: [[CALL8:%.*]] = call signext i32 @foo6() |
| // CHECK-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD7]], [[CALL8]] |
| // CHECK-NEXT: [[CALL10:%.*]] = call signext i32 @foo7() |
| // CHECK-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CALL10]] |
| // CHECK-NEXT: [[CALL12:%.*]] = call signext i32 @foo8() |
| // CHECK-NEXT: [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CALL12]] |
| // CHECK-NEXT: [[CALL14:%.*]] = call signext i32 @foo9() |
| // CHECK-NEXT: [[ADD15:%.*]] = add nsw i32 [[ADD13]], [[CALL14]] |
| // CHECK-NEXT: ret i32 [[ADD15]] |
| // |
| //. |
| // CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i" } |
| // CHECK: attributes #[[ATTR1]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zmmul" } |
| // CHECK: attributes #[[ATTR2]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zbb" } |
| // CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+c,+i,+zbb,+zca" } |
| // CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zbb,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } |
| // CHECK: attributes #[[ATTR5]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zvkt" } |
| // CHECK: attributes #[[ATTR6]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zba" } |
| // CHECK: attributes #[[ATTR7]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zba,+zbb" } |
| //. |
| // CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} |
| // CHECK: [[META1:![0-9]+]] = !{i32 1, !"target-abi", !"lp64"} |
| // CHECK: [[META2:![0-9]+]] = !{i32 6, !"riscv-isa", [[META3:![0-9]+]]} |
| // CHECK: [[META3]] = !{!"rv64i2p1"} |
| // CHECK: [[META4:![0-9]+]] = !{i32 8, !"SmallDataLimit", i32 0} |
| // CHECK: [[META5:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} |
| //. |
