| // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py |
| // REQUIRES: aarch64-registered-target |
| // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s |
| // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK |
| // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -o /dev/null %s |
| // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s |
| // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK |
| #include <arm_neon_sve_bridge.h> |
| |
| #ifdef SVE_OVERLOADED_FORMS |
| // A simple used,unused... macro, long enough to represent any SVE builtin. |
| #define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3 |
| #else |
| #define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4 |
| #endif |
| |
| // CHECK-LABEL: @test_svdup_neonq_s8( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef, <16 x i8> [[N:%.*]], i64 0) |
| // CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> [[TMP0]], i64 0) |
| // CHECK-NEXT: ret <vscale x 16 x i8> [[TMP1]] |
| // |
| // CPP-CHECK-LABEL: @_Z19test_svdup_neonq_s811__Int8x16_t( |
| // CPP-CHECK-NEXT: entry: |
| // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef, <16 x i8> [[N:%.*]], i64 0) |
| // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> [[TMP0]], i64 0) |
| // CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP1]] |
| // |
| svint8_t test_svdup_neonq_s8(int8x16_t n) { |
| return SVE_ACLE_FUNC(svdup_neonq, _s8, , )(n); |
| } |
| |
| // CHECK-LABEL: @test_svdup_neonq_s16( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> undef, <8 x i16> [[N:%.*]], i64 0) |
| // CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> [[TMP0]], i64 0) |
| // CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]] |
| // |
| // CPP-CHECK-LABEL: @_Z20test_svdup_neonq_s1611__Int16x8_t( |
| // CPP-CHECK-NEXT: entry: |
| // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> undef, <8 x i16> [[N:%.*]], i64 0) |
| // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> [[TMP0]], i64 0) |
| // CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]] |
| // |
| svint16_t test_svdup_neonq_s16(int16x8_t n) { |
| return SVE_ACLE_FUNC(svdup_neonq, _s16, , )(n); |
| } |
| |
| // CHECK-LABEL: @test_svdup_neonq_s32( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, <4 x i32> [[N:%.*]], i64 0) |
| // CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> [[TMP0]], i64 0) |
| // CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]] |
| // |
| // CPP-CHECK-LABEL: @_Z20test_svdup_neonq_s3211__Int32x4_t( |
| // CPP-CHECK-NEXT: entry: |
| // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, <4 x i32> [[N:%.*]], i64 0) |
| // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> [[TMP0]], i64 0) |
| // CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]] |
| // |
| svint32_t test_svdup_neonq_s32(int32x4_t n) { |
| return SVE_ACLE_FUNC(svdup_neonq, _s32, , )(n); |
| } |
| |
| // CHECK-LABEL: @test_svdup_neonq_s64( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, <2 x i64> [[N:%.*]], i64 0) |
| // CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> [[TMP0]], i64 0) |
| // CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]] |
| // |
| // CPP-CHECK-LABEL: @_Z20test_svdup_neonq_s6411__Int64x2_t( |
| // CPP-CHECK-NEXT: entry: |
| // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, <2 x i64> [[N:%.*]], i64 0) |
| // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> [[TMP0]], i64 0) |
| // CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]] |
| // |
| svint64_t test_svdup_neonq_s64(int64x2_t n) { |
| return SVE_ACLE_FUNC(svdup_neonq, _s64, , )(n); |
| } |
| |
| // CHECK-LABEL: @test_svdup_neonq_u8( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef, <16 x i8> [[N:%.*]], i64 0) |
| // CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> [[TMP0]], i64 0) |
| // CHECK-NEXT: ret <vscale x 16 x i8> [[TMP1]] |
| // |
| // CPP-CHECK-LABEL: @_Z19test_svdup_neonq_u812__Uint8x16_t( |
| // CPP-CHECK-NEXT: entry: |
| // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef, <16 x i8> [[N:%.*]], i64 0) |
| // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> [[TMP0]], i64 0) |
| // CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP1]] |
| // |
| svuint8_t test_svdup_neonq_u8(uint8x16_t n) { |
| return SVE_ACLE_FUNC(svdup_neonq, _u8, , )(n); |
| } |
| |
| // CHECK-LABEL: @test_svdup_neonq_u16( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> undef, <8 x i16> [[N:%.*]], i64 0) |
| // CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> [[TMP0]], i64 0) |
| // CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]] |
| // |
| // CPP-CHECK-LABEL: @_Z20test_svdup_neonq_u1612__Uint16x8_t( |
| // CPP-CHECK-NEXT: entry: |
| // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> undef, <8 x i16> [[N:%.*]], i64 0) |
| // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> [[TMP0]], i64 0) |
| // CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]] |
| // |
| svuint16_t test_svdup_neonq_u16(uint16x8_t n) { |
| return SVE_ACLE_FUNC(svdup_neonq, _u16, , )(n); |
| } |
| |
| // CHECK-LABEL: @test_svdup_neonq_u32( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, <4 x i32> [[N:%.*]], i64 0) |
| // CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> [[TMP0]], i64 0) |
| // CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]] |
| // |
| // CPP-CHECK-LABEL: @_Z20test_svdup_neonq_u3212__Uint32x4_t( |
| // CPP-CHECK-NEXT: entry: |
| // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, <4 x i32> [[N:%.*]], i64 0) |
| // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> [[TMP0]], i64 0) |
| // CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]] |
| // |
| svuint32_t test_svdup_neonq_u32(uint32x4_t n) { |
| return SVE_ACLE_FUNC(svdup_neonq, _u32, , )(n); |
| } |
| |
| // CHECK-LABEL: @test_svdup_neonq_u64( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, <2 x i64> [[N:%.*]], i64 0) |
| // CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> [[TMP0]], i64 0) |
| // CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]] |
| // |
| // CPP-CHECK-LABEL: @_Z20test_svdup_neonq_u6412__Uint64x2_t( |
| // CPP-CHECK-NEXT: entry: |
| // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, <2 x i64> [[N:%.*]], i64 0) |
| // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> [[TMP0]], i64 0) |
| // CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]] |
| // |
| svuint64_t test_svdup_neonq_u64(uint64x2_t n) { |
| return SVE_ACLE_FUNC(svdup_neonq, _u64, , )(n); |
| } |
| |
| // CHECK-LABEL: @test_svdup_neonq_f16( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.v8f16(<vscale x 8 x half> undef, <8 x half> [[N:%.*]], i64 0) |
| // CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.dupq.lane.nxv8f16(<vscale x 8 x half> [[TMP0]], i64 0) |
| // CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]] |
| // |
| // CPP-CHECK-LABEL: @_Z20test_svdup_neonq_f1613__Float16x8_t( |
| // CPP-CHECK-NEXT: entry: |
| // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.v8f16(<vscale x 8 x half> undef, <8 x half> [[N:%.*]], i64 0) |
| // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.dupq.lane.nxv8f16(<vscale x 8 x half> [[TMP0]], i64 0) |
| // CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]] |
| // |
| svfloat16_t test_svdup_neonq_f16(float16x8_t n) { |
| return SVE_ACLE_FUNC(svdup_neonq, _f16, , )(n); |
| } |
| |
| // CHECK-NEXT %0 = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v4f32(<vscale x 4 x float> undef, <4 x float> %n, i64 0) |
| // CHECK-NEXT %1 = call <vscale x 4 x float> @llvm.aarch64.sve.dupq.lane.nxv4f32(<vscale x 4 x float> %0, i64 0) |
| // CHECK-NEXT ret <vscale x 4 x float> %1 |
| // CHECK-LABEL: @test_svdup_neonq_f32( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v4f32(<vscale x 4 x float> undef, <4 x float> [[N:%.*]], i64 0) |
| // CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.dupq.lane.nxv4f32(<vscale x 4 x float> [[TMP0]], i64 0) |
| // CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]] |
| // |
| // CPP-CHECK-LABEL: @_Z20test_svdup_neonq_f3213__Float32x4_t( |
| // CPP-CHECK-NEXT: entry: |
| // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v4f32(<vscale x 4 x float> undef, <4 x float> [[N:%.*]], i64 0) |
| // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.dupq.lane.nxv4f32(<vscale x 4 x float> [[TMP0]], i64 0) |
| // CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]] |
| // |
| svfloat32_t test_svdup_neonq_f32(float32x4_t n) { |
| return SVE_ACLE_FUNC(svdup_neonq, _f32, , )(n); |
| } |
| |
| // CHECK-LABEL: @test_svdup_neonq_f64( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v2f64(<vscale x 2 x double> undef, <2 x double> [[N:%.*]], i64 0) |
| // CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.dupq.lane.nxv2f64(<vscale x 2 x double> [[TMP0]], i64 0) |
| // CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]] |
| // |
| // CPP-CHECK-LABEL: @_Z20test_svdup_neonq_f6413__Float64x2_t( |
| // CPP-CHECK-NEXT: entry: |
| // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v2f64(<vscale x 2 x double> undef, <2 x double> [[N:%.*]], i64 0) |
| // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.dupq.lane.nxv2f64(<vscale x 2 x double> [[TMP0]], i64 0) |
| // CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]] |
| // |
| svfloat64_t test_svdup_neonq_f64(float64x2_t n) { |
| return SVE_ACLE_FUNC(svdup_neonq, _f64, , )(n); |
| } |
| |
| // CHECK-LABEL: @test_svdup_neonq_bf16( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.v8bf16(<vscale x 8 x bfloat> undef, <8 x bfloat> [[N:%.*]], i64 0) |
| // CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.dupq.lane.nxv8bf16(<vscale x 8 x bfloat> [[TMP0]], i64 0) |
| // CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP1]] |
| // |
| // CPP-CHECK-LABEL: @_Z21test_svdup_neonq_bf1614__Bfloat16x8_t( |
| // CPP-CHECK-NEXT: entry: |
| // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.v8bf16(<vscale x 8 x bfloat> undef, <8 x bfloat> [[N:%.*]], i64 0) |
| // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.dupq.lane.nxv8bf16(<vscale x 8 x bfloat> [[TMP0]], i64 0) |
| // CPP-CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP1]] |
| // |
| svbfloat16_t test_svdup_neonq_bf16(bfloat16x8_t n) { |
| return SVE_ACLE_FUNC(svdup_neonq, _bf16, , )(n); |
| } |
