| // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py |
| // RUN: %clang_cc1 -no-opaque-pointers -triple riscv32 -target-feature +zbkx -emit-llvm %s -o - \ |
| // RUN: | FileCheck %s -check-prefix=RV32ZBKX |
| |
| // RV32ZBKX-LABEL: @xperm8( |
| // RV32ZBKX-NEXT: entry: |
| // RV32ZBKX-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4 |
| // RV32ZBKX-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4 |
| // RV32ZBKX-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4 |
| // RV32ZBKX-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4 |
| // RV32ZBKX-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4 |
| // RV32ZBKX-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4 |
| // RV32ZBKX-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.xperm8.i32(i32 [[TMP0]], i32 [[TMP1]]) |
| // RV32ZBKX-NEXT: ret i32 [[TMP2]] |
| // |
| long xperm8(long rs1, long rs2) |
| { |
| return __builtin_riscv_xperm8(rs1, rs2); |
| } |
| |
| // RV32ZBKX-LABEL: @xperm4( |
| // RV32ZBKX-NEXT: entry: |
| // RV32ZBKX-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4 |
| // RV32ZBKX-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4 |
| // RV32ZBKX-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4 |
| // RV32ZBKX-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4 |
| // RV32ZBKX-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4 |
| // RV32ZBKX-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4 |
| // RV32ZBKX-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.xperm4.i32(i32 [[TMP0]], i32 [[TMP1]]) |
| // RV32ZBKX-NEXT: ret i32 [[TMP2]] |
| // |
| long xperm4(long rs1, long rs2) |
| { |
| return __builtin_riscv_xperm4(rs1, rs2); |
| } |
