blob: 5b03240e3dc496cabdae737c143f54045d1bb63e [file] [log] [blame]
Fraser Cormackffa6d2a2020-10-26 12:22:55 +00001; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=amdgcn-amd-amdhsa < %s | FileCheck %s
3
Fraser Cormackf99580c2020-04-21 16:23:11 +01004; FIXME: Inefficient codegen which skips an optimization of load +
5; extractelement when the vector element type is not byte-sized.
Nikita Popovbdf2fbb2022-12-19 12:39:01 +01006define i1 @extractloadi1(ptr %ptr, i32 %idx) {
Fraser Cormackffa6d2a2020-10-26 12:22:55 +00007; CHECK-LABEL: extractloadi1:
8; CHECK: ; %bb.0:
9; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
Fraser Cormackffa6d2a2020-10-26 12:22:55 +000010; CHECK-NEXT: flat_load_ubyte v0, v[0:1]
Fraser Cormackffa6d2a2020-10-26 12:22:55 +000011; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
Björn Pettersson445973c2024-06-13 11:09:18 +020012; CHECK-NEXT: v_lshrrev_b32_e32 v1, 2, v0
13; CHECK-NEXT: v_lshlrev_b32_e32 v3, 5, v0
14; CHECK-NEXT: v_and_b32_e32 v4, 2, v0
15; CHECK-NEXT: v_lshrrev_b32_e32 v5, 6, v0
16; CHECK-NEXT: v_lshrrev_b32_e32 v6, 4, v0
17; CHECK-NEXT: v_lshlrev_b32_e32 v7, 3, v0
18; CHECK-NEXT: v_lshlrev_b32_e32 v8, 1, v0
19; CHECK-NEXT: v_or_b32_e32 v1, v1, v3
20; CHECK-NEXT: v_and_b32_e32 v3, 0x100, v7
21; CHECK-NEXT: v_and_b32_e32 v7, 0x100, v8
22; CHECK-NEXT: v_lshlrev_b32_e32 v4, 7, v4
23; CHECK-NEXT: v_or_b32_e32 v3, v6, v3
24; CHECK-NEXT: v_or_b32_e32 v5, v5, v7
25; CHECK-NEXT: v_or_b32_e32 v0, v0, v4
26; CHECK-NEXT: v_and_b32_e32 v1, 0x103, v1
27; CHECK-NEXT: v_lshlrev_b32_e32 v4, 16, v5
28; CHECK-NEXT: v_lshlrev_b32_e32 v5, 16, v1
29; CHECK-NEXT: v_or_b32_e32 v1, v3, v4
30; CHECK-NEXT: v_or_b32_e32 v0, v0, v5
31; CHECK-NEXT: v_lshlrev_b32_e32 v2, 3, v2
32; CHECK-NEXT: v_lshr_b64 v[0:1], v[0:1], v2
Fraser Cormackffa6d2a2020-10-26 12:22:55 +000033; CHECK-NEXT: s_setpc_b64 s[30:31]
Nikita Popovbdf2fbb2022-12-19 12:39:01 +010034 %val = load <8 x i1>, ptr %ptr
Fraser Cormackffa6d2a2020-10-26 12:22:55 +000035 %ret = extractelement <8 x i1> %val, i32 %idx
36 ret i1 %ret
37}