Shilei Tian | 3570908 | 2025-04-28 09:25:05 -0400 | [diff] [blame] | 1 | ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --prefix-filecheck-ir-name _ --version 5 |
Matt Arsenault | 5651af8 | 2022-11-27 20:24:34 -0500 | [diff] [blame] | 2 | ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=infer-address-spaces %s | FileCheck %s |
Eric Christopher | cee313d | 2019-04-17 04:52:47 +0000 | [diff] [blame] | 3 | |
| 4 | ; Trivial optimization of generic addressing |
| 5 | |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 6 | define float @load_global_from_flat(ptr %generic_scalar) #0 { |
Shilei Tian | 3570908 | 2025-04-28 09:25:05 -0400 | [diff] [blame] | 7 | ; CHECK-LABEL: define float @load_global_from_flat( |
| 8 | ; CHECK-SAME: ptr [[GENERIC_SCALAR:%.*]]) #[[ATTR0:[0-9]+]] { |
| 9 | ; CHECK-NEXT: [[_TMP0:%.*]] = addrspacecast ptr [[GENERIC_SCALAR]] to ptr addrspace(1) |
| 10 | ; CHECK-NEXT: [[_TMP1:%.*]] = load float, ptr addrspace(1) [[_TMP0]], align 4 |
| 11 | ; CHECK-NEXT: ret float [[_TMP1]] |
| 12 | ; |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 13 | %tmp0 = addrspacecast ptr %generic_scalar to ptr addrspace(1) |
| 14 | %tmp1 = load float, ptr addrspace(1) %tmp0 |
Eric Christopher | cee313d | 2019-04-17 04:52:47 +0000 | [diff] [blame] | 15 | ret float %tmp1 |
| 16 | } |
| 17 | |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 18 | define float @load_constant_from_flat(ptr %generic_scalar) #0 { |
Shilei Tian | 3570908 | 2025-04-28 09:25:05 -0400 | [diff] [blame] | 19 | ; CHECK-LABEL: define float @load_constant_from_flat( |
| 20 | ; CHECK-SAME: ptr [[GENERIC_SCALAR:%.*]]) #[[ATTR0]] { |
| 21 | ; CHECK-NEXT: [[_TMP0:%.*]] = addrspacecast ptr [[GENERIC_SCALAR]] to ptr addrspace(4) |
| 22 | ; CHECK-NEXT: [[_TMP1:%.*]] = load float, ptr addrspace(4) [[_TMP0]], align 4 |
| 23 | ; CHECK-NEXT: ret float [[_TMP1]] |
| 24 | ; |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 25 | %tmp0 = addrspacecast ptr %generic_scalar to ptr addrspace(4) |
| 26 | %tmp1 = load float, ptr addrspace(4) %tmp0 |
Eric Christopher | cee313d | 2019-04-17 04:52:47 +0000 | [diff] [blame] | 27 | ret float %tmp1 |
| 28 | } |
| 29 | |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 30 | define float @load_group_from_flat(ptr %generic_scalar) #0 { |
Shilei Tian | 3570908 | 2025-04-28 09:25:05 -0400 | [diff] [blame] | 31 | ; CHECK-LABEL: define float @load_group_from_flat( |
| 32 | ; CHECK-SAME: ptr [[GENERIC_SCALAR:%.*]]) #[[ATTR0]] { |
| 33 | ; CHECK-NEXT: [[_TMP0:%.*]] = addrspacecast ptr [[GENERIC_SCALAR]] to ptr addrspace(3) |
| 34 | ; CHECK-NEXT: [[_TMP1:%.*]] = load float, ptr addrspace(3) [[_TMP0]], align 4 |
| 35 | ; CHECK-NEXT: ret float [[_TMP1]] |
| 36 | ; |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 37 | %tmp0 = addrspacecast ptr %generic_scalar to ptr addrspace(3) |
| 38 | %tmp1 = load float, ptr addrspace(3) %tmp0 |
Eric Christopher | cee313d | 2019-04-17 04:52:47 +0000 | [diff] [blame] | 39 | ret float %tmp1 |
| 40 | } |
| 41 | |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 42 | define float @load_private_from_flat(ptr %generic_scalar) #0 { |
Shilei Tian | 3570908 | 2025-04-28 09:25:05 -0400 | [diff] [blame] | 43 | ; CHECK-LABEL: define float @load_private_from_flat( |
| 44 | ; CHECK-SAME: ptr [[GENERIC_SCALAR:%.*]]) #[[ATTR0]] { |
| 45 | ; CHECK-NEXT: [[_TMP0:%.*]] = addrspacecast ptr [[GENERIC_SCALAR]] to ptr addrspace(5) |
| 46 | ; CHECK-NEXT: [[_TMP1:%.*]] = load float, ptr addrspace(5) [[_TMP0]], align 4 |
| 47 | ; CHECK-NEXT: ret float [[_TMP1]] |
| 48 | ; |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 49 | %tmp0 = addrspacecast ptr %generic_scalar to ptr addrspace(5) |
| 50 | %tmp1 = load float, ptr addrspace(5) %tmp0 |
Eric Christopher | cee313d | 2019-04-17 04:52:47 +0000 | [diff] [blame] | 51 | ret float %tmp1 |
| 52 | } |
| 53 | |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 54 | define amdgpu_kernel void @store_global_from_flat(ptr %generic_scalar) #0 { |
Shilei Tian | 3570908 | 2025-04-28 09:25:05 -0400 | [diff] [blame] | 55 | ; CHECK-LABEL: define amdgpu_kernel void @store_global_from_flat( |
| 56 | ; CHECK-SAME: ptr [[GENERIC_SCALAR:%.*]]) #[[ATTR0]] { |
| 57 | ; CHECK-NEXT: [[_TMP0:%.*]] = addrspacecast ptr [[GENERIC_SCALAR]] to ptr addrspace(1) |
| 58 | ; CHECK-NEXT: store float 0.000000e+00, ptr addrspace(1) [[_TMP0]], align 4 |
| 59 | ; CHECK-NEXT: ret void |
| 60 | ; |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 61 | %tmp0 = addrspacecast ptr %generic_scalar to ptr addrspace(1) |
| 62 | store float 0.0, ptr addrspace(1) %tmp0 |
Eric Christopher | cee313d | 2019-04-17 04:52:47 +0000 | [diff] [blame] | 63 | ret void |
| 64 | } |
| 65 | |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 66 | define amdgpu_kernel void @store_group_from_flat(ptr %generic_scalar) #0 { |
Shilei Tian | 3570908 | 2025-04-28 09:25:05 -0400 | [diff] [blame] | 67 | ; CHECK-LABEL: define amdgpu_kernel void @store_group_from_flat( |
| 68 | ; CHECK-SAME: ptr [[GENERIC_SCALAR:%.*]]) #[[ATTR0]] { |
Shilei Tian | 9bf6b2a | 2025-05-30 17:30:42 -0400 | [diff] [blame^] | 69 | ; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[GENERIC_SCALAR]] to ptr addrspace(1) |
| 70 | ; CHECK-NEXT: [[TMP2:%.*]] = addrspacecast ptr addrspace(1) [[TMP1]] to ptr |
| 71 | ; CHECK-NEXT: [[_TMP0:%.*]] = addrspacecast ptr [[TMP2]] to ptr addrspace(3) |
Shilei Tian | 3570908 | 2025-04-28 09:25:05 -0400 | [diff] [blame] | 72 | ; CHECK-NEXT: store float 0.000000e+00, ptr addrspace(3) [[_TMP0]], align 4 |
| 73 | ; CHECK-NEXT: ret void |
| 74 | ; |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 75 | %tmp0 = addrspacecast ptr %generic_scalar to ptr addrspace(3) |
| 76 | store float 0.0, ptr addrspace(3) %tmp0 |
Eric Christopher | cee313d | 2019-04-17 04:52:47 +0000 | [diff] [blame] | 77 | ret void |
| 78 | } |
| 79 | |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 80 | define amdgpu_kernel void @store_private_from_flat(ptr %generic_scalar) #0 { |
Shilei Tian | 3570908 | 2025-04-28 09:25:05 -0400 | [diff] [blame] | 81 | ; CHECK-LABEL: define amdgpu_kernel void @store_private_from_flat( |
| 82 | ; CHECK-SAME: ptr [[GENERIC_SCALAR:%.*]]) #[[ATTR0]] { |
Shilei Tian | 9bf6b2a | 2025-05-30 17:30:42 -0400 | [diff] [blame^] | 83 | ; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[GENERIC_SCALAR]] to ptr addrspace(1) |
| 84 | ; CHECK-NEXT: [[TMP2:%.*]] = addrspacecast ptr addrspace(1) [[TMP1]] to ptr |
| 85 | ; CHECK-NEXT: [[_TMP0:%.*]] = addrspacecast ptr [[TMP2]] to ptr addrspace(5) |
Shilei Tian | 3570908 | 2025-04-28 09:25:05 -0400 | [diff] [blame] | 86 | ; CHECK-NEXT: store float 0.000000e+00, ptr addrspace(5) [[_TMP0]], align 4 |
| 87 | ; CHECK-NEXT: ret void |
| 88 | ; |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 89 | %tmp0 = addrspacecast ptr %generic_scalar to ptr addrspace(5) |
| 90 | store float 0.0, ptr addrspace(5) %tmp0 |
Eric Christopher | cee313d | 2019-04-17 04:52:47 +0000 | [diff] [blame] | 91 | ret void |
| 92 | } |
| 93 | |
| 94 | ; optimized to global load/store. |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 95 | define amdgpu_kernel void @load_store_global(ptr addrspace(1) nocapture %input, ptr addrspace(1) nocapture %output) #0 { |
Shilei Tian | 3570908 | 2025-04-28 09:25:05 -0400 | [diff] [blame] | 96 | ; CHECK-LABEL: define amdgpu_kernel void @load_store_global( |
| 97 | ; CHECK-SAME: ptr addrspace(1) captures(none) [[INPUT:%.*]], ptr addrspace(1) captures(none) [[OUTPUT:%.*]]) #[[ATTR0]] { |
| 98 | ; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr addrspace(1) [[INPUT]], align 4 |
| 99 | ; CHECK-NEXT: store i32 [[VAL]], ptr addrspace(1) [[OUTPUT]], align 4 |
| 100 | ; CHECK-NEXT: ret void |
| 101 | ; |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 102 | %tmp0 = addrspacecast ptr addrspace(1) %input to ptr |
| 103 | %tmp1 = addrspacecast ptr addrspace(1) %output to ptr |
| 104 | %val = load i32, ptr %tmp0, align 4 |
| 105 | store i32 %val, ptr %tmp1, align 4 |
Eric Christopher | cee313d | 2019-04-17 04:52:47 +0000 | [diff] [blame] | 106 | ret void |
| 107 | } |
| 108 | |
| 109 | ; Optimized to group load/store. |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 110 | define amdgpu_kernel void @load_store_group(ptr addrspace(3) nocapture %input, ptr addrspace(3) nocapture %output) #0 { |
Shilei Tian | 3570908 | 2025-04-28 09:25:05 -0400 | [diff] [blame] | 111 | ; CHECK-LABEL: define amdgpu_kernel void @load_store_group( |
| 112 | ; CHECK-SAME: ptr addrspace(3) captures(none) [[INPUT:%.*]], ptr addrspace(3) captures(none) [[OUTPUT:%.*]]) #[[ATTR0]] { |
| 113 | ; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr addrspace(3) [[INPUT]], align 4 |
| 114 | ; CHECK-NEXT: store i32 [[VAL]], ptr addrspace(3) [[OUTPUT]], align 4 |
| 115 | ; CHECK-NEXT: ret void |
| 116 | ; |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 117 | %tmp0 = addrspacecast ptr addrspace(3) %input to ptr |
| 118 | %tmp1 = addrspacecast ptr addrspace(3) %output to ptr |
| 119 | %val = load i32, ptr %tmp0, align 4 |
| 120 | store i32 %val, ptr %tmp1, align 4 |
Eric Christopher | cee313d | 2019-04-17 04:52:47 +0000 | [diff] [blame] | 121 | ret void |
| 122 | } |
| 123 | |
| 124 | ; Optimized to private load/store. |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 125 | define amdgpu_kernel void @load_store_private(ptr addrspace(5) nocapture %input, ptr addrspace(5) nocapture %output) #0 { |
Shilei Tian | 3570908 | 2025-04-28 09:25:05 -0400 | [diff] [blame] | 126 | ; CHECK-LABEL: define amdgpu_kernel void @load_store_private( |
| 127 | ; CHECK-SAME: ptr addrspace(5) captures(none) [[INPUT:%.*]], ptr addrspace(5) captures(none) [[OUTPUT:%.*]]) #[[ATTR0]] { |
| 128 | ; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr addrspace(5) [[INPUT]], align 4 |
| 129 | ; CHECK-NEXT: store i32 [[VAL]], ptr addrspace(5) [[OUTPUT]], align 4 |
| 130 | ; CHECK-NEXT: ret void |
| 131 | ; |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 132 | %tmp0 = addrspacecast ptr addrspace(5) %input to ptr |
| 133 | %tmp1 = addrspacecast ptr addrspace(5) %output to ptr |
| 134 | %val = load i32, ptr %tmp0, align 4 |
| 135 | store i32 %val, ptr %tmp1, align 4 |
Eric Christopher | cee313d | 2019-04-17 04:52:47 +0000 | [diff] [blame] | 136 | ret void |
| 137 | } |
| 138 | |
| 139 | ; No optimization. flat load/store. |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 140 | define amdgpu_kernel void @load_store_flat(ptr nocapture %input, ptr nocapture %output) #0 { |
Shilei Tian | 3570908 | 2025-04-28 09:25:05 -0400 | [diff] [blame] | 141 | ; CHECK-LABEL: define amdgpu_kernel void @load_store_flat( |
| 142 | ; CHECK-SAME: ptr captures(none) [[INPUT:%.*]], ptr captures(none) [[OUTPUT:%.*]]) #[[ATTR0]] { |
Shilei Tian | 9bf6b2a | 2025-05-30 17:30:42 -0400 | [diff] [blame^] | 143 | ; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[INPUT]] to ptr addrspace(1) |
| 144 | ; CHECK-NEXT: [[TMP2:%.*]] = addrspacecast ptr [[OUTPUT]] to ptr addrspace(1) |
| 145 | ; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr addrspace(1) [[TMP1]], align 4 |
| 146 | ; CHECK-NEXT: store i32 [[VAL]], ptr addrspace(1) [[TMP2]], align 4 |
Shilei Tian | 3570908 | 2025-04-28 09:25:05 -0400 | [diff] [blame] | 147 | ; CHECK-NEXT: ret void |
| 148 | ; |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 149 | %val = load i32, ptr %input, align 4 |
| 150 | store i32 %val, ptr %output, align 4 |
Eric Christopher | cee313d | 2019-04-17 04:52:47 +0000 | [diff] [blame] | 151 | ret void |
| 152 | } |
| 153 | |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 154 | define amdgpu_kernel void @store_addrspacecast_ptr_value(ptr addrspace(1) nocapture %input, ptr addrspace(1) nocapture %output) #0 { |
Shilei Tian | 3570908 | 2025-04-28 09:25:05 -0400 | [diff] [blame] | 155 | ; CHECK-LABEL: define amdgpu_kernel void @store_addrspacecast_ptr_value( |
| 156 | ; CHECK-SAME: ptr addrspace(1) captures(none) [[INPUT:%.*]], ptr addrspace(1) captures(none) [[OUTPUT:%.*]]) #[[ATTR0]] { |
| 157 | ; CHECK-NEXT: [[CAST:%.*]] = addrspacecast ptr addrspace(1) [[INPUT]] to ptr |
| 158 | ; CHECK-NEXT: store ptr [[CAST]], ptr addrspace(1) [[OUTPUT]], align 4 |
| 159 | ; CHECK-NEXT: ret void |
| 160 | ; |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 161 | %cast = addrspacecast ptr addrspace(1) %input to ptr |
| 162 | store ptr %cast, ptr addrspace(1) %output, align 4 |
Eric Christopher | cee313d | 2019-04-17 04:52:47 +0000 | [diff] [blame] | 163 | ret void |
| 164 | } |
| 165 | |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 166 | define i32 @atomicrmw_add_global_to_flat(ptr addrspace(1) %global.ptr, i32 %y) #0 { |
Shilei Tian | 3570908 | 2025-04-28 09:25:05 -0400 | [diff] [blame] | 167 | ; CHECK-LABEL: define i32 @atomicrmw_add_global_to_flat( |
| 168 | ; CHECK-SAME: ptr addrspace(1) [[GLOBAL_PTR:%.*]], i32 [[Y:%.*]]) #[[ATTR0]] { |
| 169 | ; CHECK-NEXT: [[RET:%.*]] = atomicrmw add ptr addrspace(1) [[GLOBAL_PTR]], i32 [[Y]] seq_cst, align 4 |
| 170 | ; CHECK-NEXT: ret i32 [[RET]] |
| 171 | ; |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 172 | %cast = addrspacecast ptr addrspace(1) %global.ptr to ptr |
| 173 | %ret = atomicrmw add ptr %cast, i32 %y seq_cst |
Eric Christopher | cee313d | 2019-04-17 04:52:47 +0000 | [diff] [blame] | 174 | ret i32 %ret |
| 175 | } |
| 176 | |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 177 | define i32 @atomicrmw_add_group_to_flat(ptr addrspace(3) %group.ptr, i32 %y) #0 { |
Shilei Tian | 3570908 | 2025-04-28 09:25:05 -0400 | [diff] [blame] | 178 | ; CHECK-LABEL: define i32 @atomicrmw_add_group_to_flat( |
| 179 | ; CHECK-SAME: ptr addrspace(3) [[GROUP_PTR:%.*]], i32 [[Y:%.*]]) #[[ATTR0]] { |
| 180 | ; CHECK-NEXT: [[RET:%.*]] = atomicrmw add ptr addrspace(3) [[GROUP_PTR]], i32 [[Y]] seq_cst, align 4 |
| 181 | ; CHECK-NEXT: ret i32 [[RET]] |
| 182 | ; |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 183 | %cast = addrspacecast ptr addrspace(3) %group.ptr to ptr |
| 184 | %ret = atomicrmw add ptr %cast, i32 %y seq_cst |
Eric Christopher | cee313d | 2019-04-17 04:52:47 +0000 | [diff] [blame] | 185 | ret i32 %ret |
| 186 | } |
| 187 | |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 188 | define { i32, i1 } @cmpxchg_global_to_flat(ptr addrspace(1) %global.ptr, i32 %cmp, i32 %val) #0 { |
Shilei Tian | 3570908 | 2025-04-28 09:25:05 -0400 | [diff] [blame] | 189 | ; CHECK-LABEL: define { i32, i1 } @cmpxchg_global_to_flat( |
| 190 | ; CHECK-SAME: ptr addrspace(1) [[GLOBAL_PTR:%.*]], i32 [[CMP:%.*]], i32 [[VAL:%.*]]) #[[ATTR0]] { |
| 191 | ; CHECK-NEXT: [[RET:%.*]] = cmpxchg ptr addrspace(1) [[GLOBAL_PTR]], i32 [[CMP]], i32 [[VAL]] seq_cst monotonic, align 4 |
| 192 | ; CHECK-NEXT: ret { i32, i1 } [[RET]] |
| 193 | ; |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 194 | %cast = addrspacecast ptr addrspace(1) %global.ptr to ptr |
| 195 | %ret = cmpxchg ptr %cast, i32 %cmp, i32 %val seq_cst monotonic |
Eric Christopher | cee313d | 2019-04-17 04:52:47 +0000 | [diff] [blame] | 196 | ret { i32, i1 } %ret |
| 197 | } |
| 198 | |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 199 | define { i32, i1 } @cmpxchg_group_to_flat(ptr addrspace(3) %group.ptr, i32 %cmp, i32 %val) #0 { |
Shilei Tian | 3570908 | 2025-04-28 09:25:05 -0400 | [diff] [blame] | 200 | ; CHECK-LABEL: define { i32, i1 } @cmpxchg_group_to_flat( |
| 201 | ; CHECK-SAME: ptr addrspace(3) [[GROUP_PTR:%.*]], i32 [[CMP:%.*]], i32 [[VAL:%.*]]) #[[ATTR0]] { |
| 202 | ; CHECK-NEXT: [[RET:%.*]] = cmpxchg ptr addrspace(3) [[GROUP_PTR]], i32 [[CMP]], i32 [[VAL]] seq_cst monotonic, align 4 |
| 203 | ; CHECK-NEXT: ret { i32, i1 } [[RET]] |
| 204 | ; |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 205 | %cast = addrspacecast ptr addrspace(3) %group.ptr to ptr |
| 206 | %ret = cmpxchg ptr %cast, i32 %cmp, i32 %val seq_cst monotonic |
Eric Christopher | cee313d | 2019-04-17 04:52:47 +0000 | [diff] [blame] | 207 | ret { i32, i1 } %ret |
| 208 | } |
| 209 | |
| 210 | ; Not pointer operand |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 211 | define { ptr, i1 } @cmpxchg_group_to_flat_wrong_operand(ptr addrspace(3) %cas.ptr, ptr addrspace(3) %cmp.ptr, ptr %val) #0 { |
Shilei Tian | 3570908 | 2025-04-28 09:25:05 -0400 | [diff] [blame] | 212 | ; CHECK-LABEL: define { ptr, i1 } @cmpxchg_group_to_flat_wrong_operand( |
| 213 | ; CHECK-SAME: ptr addrspace(3) [[CAS_PTR:%.*]], ptr addrspace(3) [[CMP_PTR:%.*]], ptr [[VAL:%.*]]) #[[ATTR0]] { |
| 214 | ; CHECK-NEXT: [[CAST_CMP:%.*]] = addrspacecast ptr addrspace(3) [[CMP_PTR]] to ptr |
| 215 | ; CHECK-NEXT: [[RET:%.*]] = cmpxchg ptr addrspace(3) [[CAS_PTR]], ptr [[CAST_CMP]], ptr [[VAL]] seq_cst monotonic, align 8 |
| 216 | ; CHECK-NEXT: ret { ptr, i1 } [[RET]] |
| 217 | ; |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 218 | %cast.cmp = addrspacecast ptr addrspace(3) %cmp.ptr to ptr |
| 219 | %ret = cmpxchg ptr addrspace(3) %cas.ptr, ptr %cast.cmp, ptr %val seq_cst monotonic |
| 220 | ret { ptr, i1 } %ret |
Eric Christopher | cee313d | 2019-04-17 04:52:47 +0000 | [diff] [blame] | 221 | } |
| 222 | |
| 223 | ; Null pointer in local addr space |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 224 | define void @local_nullptr(ptr addrspace(1) nocapture %results, ptr addrspace(3) %a) { |
Shilei Tian | 3570908 | 2025-04-28 09:25:05 -0400 | [diff] [blame] | 225 | ; CHECK-LABEL: define void @local_nullptr( |
| 226 | ; CHECK-SAME: ptr addrspace(1) captures(none) [[RESULTS:%.*]], ptr addrspace(3) [[A:%.*]]) { |
| 227 | ; CHECK-NEXT: [[ENTRY:.*:]] |
| 228 | ; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne ptr addrspace(3) [[A]], addrspacecast (ptr addrspace(5) null to ptr addrspace(3)) |
| 229 | ; CHECK-NEXT: [[CONV:%.*]] = zext i1 [[TOBOOL]] to i32 |
| 230 | ; CHECK-NEXT: store i32 [[CONV]], ptr addrspace(1) [[RESULTS]], align 4 |
| 231 | ; CHECK-NEXT: ret void |
| 232 | ; |
Eric Christopher | cee313d | 2019-04-17 04:52:47 +0000 | [diff] [blame] | 233 | entry: |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 234 | %tobool = icmp ne ptr addrspace(3) %a, addrspacecast (ptr addrspace(5) null to ptr addrspace(3)) |
Eric Christopher | cee313d | 2019-04-17 04:52:47 +0000 | [diff] [blame] | 235 | %conv = zext i1 %tobool to i32 |
Matt Arsenault | a982f09 | 2022-11-27 20:11:40 -0500 | [diff] [blame] | 236 | store i32 %conv, ptr addrspace(1) %results, align 4 |
Eric Christopher | cee313d | 2019-04-17 04:52:47 +0000 | [diff] [blame] | 237 | ret void |
| 238 | } |
| 239 | |
Matt Arsenault | f433c3b | 2024-04-20 00:43:36 +0200 | [diff] [blame] | 240 | define i32 @atomicrmw_add_global_to_flat_preserve_amdgpu_md(ptr addrspace(1) %global.ptr, i32 %y) #0 { |
Shilei Tian | 3570908 | 2025-04-28 09:25:05 -0400 | [diff] [blame] | 241 | ; CHECK-LABEL: define i32 @atomicrmw_add_global_to_flat_preserve_amdgpu_md( |
| 242 | ; CHECK-SAME: ptr addrspace(1) [[GLOBAL_PTR:%.*]], i32 [[Y:%.*]]) #[[ATTR0]] { |
| 243 | ; CHECK-NEXT: [[RET:%.*]] = atomicrmw add ptr addrspace(1) [[GLOBAL_PTR]], i32 [[Y]] seq_cst, align 4, !amdgpu.no.fine.grained.memory [[META0:![0-9]+]], !amdgpu.no.remote.memory [[META0]] |
| 244 | ; CHECK-NEXT: ret i32 [[RET]] |
| 245 | ; |
Matt Arsenault | f433c3b | 2024-04-20 00:43:36 +0200 | [diff] [blame] | 246 | %cast = addrspacecast ptr addrspace(1) %global.ptr to ptr |
Matt Arsenault | 9f9856d | 2024-04-22 11:40:35 +0200 | [diff] [blame] | 247 | %ret = atomicrmw add ptr %cast, i32 %y seq_cst, align 4, !amdgpu.no.fine.grained.memory !0, !amdgpu.no.remote.memory !0 |
Matt Arsenault | f433c3b | 2024-04-20 00:43:36 +0200 | [diff] [blame] | 248 | ret i32 %ret |
| 249 | } |
| 250 | |
Matt Arsenault | 2ccbf92 | 2024-08-15 15:53:55 +0400 | [diff] [blame] | 251 | ; Make sure there's no assert |
Matt Arsenault | 2ccbf92 | 2024-08-15 15:53:55 +0400 | [diff] [blame] | 252 | define ptr @try_infer_getelementptr_constant_null() { |
Shilei Tian | 3570908 | 2025-04-28 09:25:05 -0400 | [diff] [blame] | 253 | ; CHECK-LABEL: define ptr @try_infer_getelementptr_constant_null() { |
| 254 | ; CHECK-NEXT: [[CE:%.*]] = getelementptr i8, ptr getelementptr inbounds (i8, ptr null, i64 8), i64 0 |
| 255 | ; CHECK-NEXT: ret ptr [[CE]] |
| 256 | ; |
Matt Arsenault | 2ccbf92 | 2024-08-15 15:53:55 +0400 | [diff] [blame] | 257 | %ce = getelementptr i8, ptr getelementptr inbounds (i8, ptr null, i64 8), i64 0 |
| 258 | ret ptr %ce |
| 259 | } |
| 260 | |
Eric Christopher | cee313d | 2019-04-17 04:52:47 +0000 | [diff] [blame] | 261 | attributes #0 = { nounwind } |
Matt Arsenault | f433c3b | 2024-04-20 00:43:36 +0200 | [diff] [blame] | 262 | |
| 263 | !0 = !{} |
Shilei Tian | 3570908 | 2025-04-28 09:25:05 -0400 | [diff] [blame] | 264 | ;. |
| 265 | ; CHECK: [[META0]] = !{} |
| 266 | ;. |