blob: ae99ef1630647d5fa500795f0d30d2e8d368d77a [file] [log] [blame]
Ilia Diachkovec259032022-04-14 01:10:25 +03001//===-- SPIRVAsmPrinter.cpp - SPIR-V LLVM assembly writer ------*- C++ -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a printer that converts from our internal representation
10// of machine-dependent LLVM code to the SPIR-V assembly language.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MCTargetDesc/SPIRVInstPrinter.h"
15#include "SPIRV.h"
16#include "SPIRVInstrInfo.h"
17#include "SPIRVMCInstLower.h"
Ilia Diachkov153dee32022-04-14 03:46:45 +030018#include "SPIRVModuleAnalysis.h"
19#include "SPIRVSubtarget.h"
Ilia Diachkovec259032022-04-14 01:10:25 +030020#include "SPIRVTargetMachine.h"
Ilia Diachkov153dee32022-04-14 03:46:45 +030021#include "SPIRVUtils.h"
Ilia Diachkovec259032022-04-14 01:10:25 +030022#include "TargetInfo/SPIRVTargetInfo.h"
Ilia Diachkov153dee32022-04-14 03:46:45 +030023#include "llvm/ADT/DenseMap.h"
Ilia Diachkovb8e15442022-07-20 18:48:16 +030024#include "llvm/Analysis/ValueTracking.h"
Ilia Diachkovec259032022-04-14 01:10:25 +030025#include "llvm/CodeGen/AsmPrinter.h"
26#include "llvm/CodeGen/MachineConstantPool.h"
27#include "llvm/CodeGen/MachineFunctionPass.h"
28#include "llvm/CodeGen/MachineInstr.h"
29#include "llvm/CodeGen/MachineModuleInfo.h"
30#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
31#include "llvm/MC/MCAsmInfo.h"
Vyacheslav Levytskyy59f34e82024-03-18 11:42:44 +010032#include "llvm/MC/MCAssembler.h"
Ilia Diachkovec259032022-04-14 01:10:25 +030033#include "llvm/MC/MCInst.h"
Vyacheslav Levytskyy59f34e82024-03-18 11:42:44 +010034#include "llvm/MC/MCObjectStreamer.h"
Fangrui Songffcd7e92024-07-21 12:48:09 -070035#include "llvm/MC/MCSPIRVObjectWriter.h"
Ilia Diachkovec259032022-04-14 01:10:25 +030036#include "llvm/MC/MCStreamer.h"
37#include "llvm/MC/MCSymbol.h"
38#include "llvm/MC/TargetRegistry.h"
39#include "llvm/Support/raw_ostream.h"
Ilia Diachkov153dee32022-04-14 03:46:45 +030040
Ilia Diachkovec259032022-04-14 01:10:25 +030041using namespace llvm;
42
43#define DEBUG_TYPE "asm-printer"
44
45namespace {
46class SPIRVAsmPrinter : public AsmPrinter {
Vyacheslav Levytskyy23b058c2024-04-09 16:15:44 +020047 unsigned NLabels = 0;
Vyacheslav Levytskyy874b4fb2024-12-03 16:18:06 +010048 SmallPtrSet<const MachineBasicBlock *, 8> LabeledMBB;
Vyacheslav Levytskyy23b058c2024-04-09 16:15:44 +020049
Ilia Diachkovec259032022-04-14 01:10:25 +030050public:
51 explicit SPIRVAsmPrinter(TargetMachine &TM,
52 std::unique_ptr<MCStreamer> Streamer)
Ilia Diachkov153dee32022-04-14 03:46:45 +030053 : AsmPrinter(TM, std::move(Streamer)), ST(nullptr), TII(nullptr) {}
54 bool ModuleSectionsEmitted;
55 const SPIRVSubtarget *ST;
56 const SPIRVInstrInfo *TII;
Ilia Diachkovec259032022-04-14 01:10:25 +030057
58 StringRef getPassName() const override { return "SPIRV Assembly Printer"; }
59 void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O);
Ilia Diachkovec259032022-04-14 01:10:25 +030060 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
61 const char *ExtraCode, raw_ostream &O) override;
62
Ilia Diachkov153dee32022-04-14 03:46:45 +030063 void outputMCInst(MCInst &Inst);
64 void outputInstruction(const MachineInstr *MI);
65 void outputModuleSection(SPIRV::ModuleSectionType MSType);
Ilia Diachkovdf871302022-08-11 00:37:46 +030066 void outputGlobalRequirements();
Ilia Diachkov153dee32022-04-14 03:46:45 +030067 void outputEntryPoints();
68 void outputDebugSourceAndStrings(const Module &M);
Ilia Diachkovb8e15442022-07-20 18:48:16 +030069 void outputOpExtInstImports(const Module &M);
Ilia Diachkov153dee32022-04-14 03:46:45 +030070 void outputOpMemoryModel();
71 void outputOpFunctionEnd();
72 void outputExtFuncDecls();
Craig Topper20120892025-03-03 08:43:02 -080073 void outputExecutionModeFromMDNode(MCRegister Reg, MDNode *Node,
Vyacheslav Levytskyy0047df92024-05-20 19:05:25 +020074 SPIRV::ExecutionMode::ExecutionMode EM,
75 unsigned ExpectMDOps, int64_t DefVal);
Nathan Gauër56396b22023-07-24 13:28:09 +020076 void outputExecutionModeFromNumthreadsAttribute(
Craig Topper20120892025-03-03 08:43:02 -080077 const MCRegister &Reg, const Attribute &Attr,
Nathan Gauër56396b22023-07-24 13:28:09 +020078 SPIRV::ExecutionMode::ExecutionMode EM);
Ilia Diachkovb8e15442022-07-20 18:48:16 +030079 void outputExecutionMode(const Module &M);
80 void outputAnnotations(const Module &M);
Ilia Diachkov153dee32022-04-14 03:46:45 +030081 void outputModuleSections();
Vyacheslav Levytskyy8d8996d2024-10-15 18:42:51 +020082 bool isHidden() {
83 return MF->getFunction()
84 .getFnAttribute(SPIRV_BACKEND_SERVICE_FUN_NAME)
85 .isValid();
86 }
Ilia Diachkovec259032022-04-14 01:10:25 +030087
Ilia Diachkov153dee32022-04-14 03:46:45 +030088 void emitInstruction(const MachineInstr *MI) override;
Ilia Diachkovec259032022-04-14 01:10:25 +030089 void emitFunctionEntryLabel() override {}
90 void emitFunctionHeader() override;
91 void emitFunctionBodyStart() override {}
Ilia Diachkov153dee32022-04-14 03:46:45 +030092 void emitFunctionBodyEnd() override;
93 void emitBasicBlockStart(const MachineBasicBlock &MBB) override;
Ilia Diachkovec259032022-04-14 01:10:25 +030094 void emitBasicBlockEnd(const MachineBasicBlock &MBB) override {}
95 void emitGlobalVariable(const GlobalVariable *GV) override {}
Ilia Diachkov153dee32022-04-14 03:46:45 +030096 void emitOpLabel(const MachineBasicBlock &MBB);
97 void emitEndOfAsmFile(Module &M) override;
98 bool doInitialization(Module &M) override;
99
100 void getAnalysisUsage(AnalysisUsage &AU) const override;
101 SPIRV::ModuleAnalysisInfo *MAI;
Vyacheslav Levytskyy9ba27ca2025-01-14 17:45:10 +0100102
103protected:
104 void cleanUp(Module &M);
Ilia Diachkovec259032022-04-14 01:10:25 +0300105};
106} // namespace
107
Ilia Diachkov153dee32022-04-14 03:46:45 +0300108void SPIRVAsmPrinter::getAnalysisUsage(AnalysisUsage &AU) const {
109 AU.addRequired<SPIRVModuleAnalysis>();
110 AU.addPreserved<SPIRVModuleAnalysis>();
111 AsmPrinter::getAnalysisUsage(AU);
112}
113
114// If the module has no functions, we need output global info anyway.
115void SPIRVAsmPrinter::emitEndOfAsmFile(Module &M) {
116 if (ModuleSectionsEmitted == false) {
117 outputModuleSections();
118 ModuleSectionsEmitted = true;
119 }
Vyacheslav Levytskyyc2483ed2024-03-20 19:28:29 +0100120
121 ST = static_cast<const SPIRVTargetMachine &>(TM).getSubtargetImpl();
Michal Paszkowskif352ce32024-04-22 10:47:46 -0700122 VersionTuple SPIRVVersion = ST->getSPIRVVersion();
123 uint32_t Major = SPIRVVersion.getMajor();
124 uint32_t Minor = SPIRVVersion.getMinor().value_or(0);
Vyacheslav Levytskyy23b058c2024-04-09 16:15:44 +0200125 // Bound is an approximation that accounts for the maximum used register
126 // number and number of generated OpLabels
127 unsigned Bound = 2 * (ST->getBound() + 1) + NLabels;
Vyacheslav Levytskyyc2483ed2024-03-20 19:28:29 +0100128 if (MCAssembler *Asm = OutStreamer->getAssemblerPtr())
Fangrui Songffcd7e92024-07-21 12:48:09 -0700129 static_cast<SPIRVObjectWriter &>(Asm->getWriter())
130 .setBuildVersion(Major, Minor, Bound);
Vyacheslav Levytskyy9ba27ca2025-01-14 17:45:10 +0100131
132 cleanUp(M);
133}
134
135// Any cleanup actions with the Module after we don't care about its content
136// anymore.
137void SPIRVAsmPrinter::cleanUp(Module &M) {
138 // Verifier disallows uses of intrinsic global variables.
139 for (StringRef GVName : {"llvm.global_ctors", "llvm.global_dtors",
140 "llvm.used", "llvm.compiler.used"}) {
141 if (GlobalVariable *GV = M.getNamedGlobal(GVName))
142 GV->setName("");
143 }
Ilia Diachkov153dee32022-04-14 03:46:45 +0300144}
145
Ilia Diachkovec259032022-04-14 01:10:25 +0300146void SPIRVAsmPrinter::emitFunctionHeader() {
Ilia Diachkov153dee32022-04-14 03:46:45 +0300147 if (ModuleSectionsEmitted == false) {
148 outputModuleSections();
149 ModuleSectionsEmitted = true;
150 }
151 // Get the subtarget from the current MachineFunction.
152 ST = &MF->getSubtarget<SPIRVSubtarget>();
153 TII = ST->getInstrInfo();
Ilia Diachkovec259032022-04-14 01:10:25 +0300154 const Function &F = MF->getFunction();
155
Vyacheslav Levytskyy8d8996d2024-10-15 18:42:51 +0200156 if (isVerbose() && !isHidden()) {
Fangrui Song15d82c62022-06-07 00:31:02 -0700157 OutStreamer->getCommentOS()
Ilia Diachkovec259032022-04-14 01:10:25 +0300158 << "-- Begin function "
159 << GlobalValue::dropLLVMManglingEscape(F.getName()) << '\n';
160 }
161
162 auto Section = getObjFileLowering().SectionForGlobal(&F, TM);
163 MF->setSection(Section);
164}
165
Ilia Diachkov153dee32022-04-14 03:46:45 +0300166void SPIRVAsmPrinter::outputOpFunctionEnd() {
167 MCInst FunctionEndInst;
168 FunctionEndInst.setOpcode(SPIRV::OpFunctionEnd);
169 outputMCInst(FunctionEndInst);
170}
171
Ilia Diachkov153dee32022-04-14 03:46:45 +0300172void SPIRVAsmPrinter::emitFunctionBodyEnd() {
Vyacheslav Levytskyy874b4fb2024-12-03 16:18:06 +0100173 if (!isHidden())
174 outputOpFunctionEnd();
Ilia Diachkov153dee32022-04-14 03:46:45 +0300175}
176
177void SPIRVAsmPrinter::emitOpLabel(const MachineBasicBlock &MBB) {
Vyacheslav Levytskyy8d8996d2024-10-15 18:42:51 +0200178 // Do not emit anything if it's an internal service function.
179 if (isHidden())
180 return;
181
Ilia Diachkov153dee32022-04-14 03:46:45 +0300182 MCInst LabelInst;
183 LabelInst.setOpcode(SPIRV::OpLabel);
184 LabelInst.addOperand(MCOperand::createReg(MAI->getOrCreateMBBRegister(MBB)));
185 outputMCInst(LabelInst);
Vyacheslav Levytskyy23b058c2024-04-09 16:15:44 +0200186 ++NLabels;
Vyacheslav Levytskyy874b4fb2024-12-03 16:18:06 +0100187 LabeledMBB.insert(&MBB);
Ilia Diachkov153dee32022-04-14 03:46:45 +0300188}
189
190void SPIRVAsmPrinter::emitBasicBlockStart(const MachineBasicBlock &MBB) {
Vyacheslav Levytskyy8d8996d2024-10-15 18:42:51 +0200191 // Do not emit anything if it's an internal service function.
192 if (MBB.empty())
193 return;
Michal Paszkowski8bfb2b62023-03-26 20:07:11 +0200194
Ilia Diachkov153dee32022-04-14 03:46:45 +0300195 // If it's the first MBB in MF, it has OpFunction and OpFunctionParameter, so
196 // OpLabel should be output after them.
197 if (MBB.getNumber() == MF->front().getNumber()) {
198 for (const MachineInstr &MI : MBB)
199 if (MI.getOpcode() == SPIRV::OpFunction)
200 return;
201 // TODO: this case should be checked by the verifier.
202 report_fatal_error("OpFunction is expected in the front MBB of MF");
203 }
204 emitOpLabel(MBB);
205}
206
Ilia Diachkovec259032022-04-14 01:10:25 +0300207void SPIRVAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
208 raw_ostream &O) {
209 const MachineOperand &MO = MI->getOperand(OpNum);
210
211 switch (MO.getType()) {
212 case MachineOperand::MO_Register:
213 O << SPIRVInstPrinter::getRegisterName(MO.getReg());
214 break;
215
216 case MachineOperand::MO_Immediate:
217 O << MO.getImm();
218 break;
219
220 case MachineOperand::MO_FPImmediate:
221 O << MO.getFPImm();
222 break;
223
224 case MachineOperand::MO_MachineBasicBlock:
225 O << *MO.getMBB()->getSymbol();
226 break;
227
228 case MachineOperand::MO_GlobalAddress:
229 O << *getSymbol(MO.getGlobal());
230 break;
231
232 case MachineOperand::MO_BlockAddress: {
233 MCSymbol *BA = GetBlockAddressSymbol(MO.getBlockAddress());
234 O << BA->getName();
235 break;
236 }
237
238 case MachineOperand::MO_ExternalSymbol:
239 O << *GetExternalSymbolSymbol(MO.getSymbolName());
240 break;
241
242 case MachineOperand::MO_JumpTableIndex:
243 case MachineOperand::MO_ConstantPoolIndex:
244 default:
245 llvm_unreachable("<unknown operand type>");
246 }
247}
248
249bool SPIRVAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
250 const char *ExtraCode, raw_ostream &O) {
251 if (ExtraCode && ExtraCode[0])
252 return true; // Invalid instruction - SPIR-V does not have special modifiers
253
254 printOperand(MI, OpNo, O);
255 return false;
256}
257
Ilia Diachkov153dee32022-04-14 03:46:45 +0300258static bool isFuncOrHeaderInstr(const MachineInstr *MI,
259 const SPIRVInstrInfo *TII) {
260 return TII->isHeaderInstr(*MI) || MI->getOpcode() == SPIRV::OpFunction ||
261 MI->getOpcode() == SPIRV::OpFunctionParameter;
262}
Ilia Diachkovec259032022-04-14 01:10:25 +0300263
Ilia Diachkov153dee32022-04-14 03:46:45 +0300264void SPIRVAsmPrinter::outputMCInst(MCInst &Inst) {
265 OutStreamer->emitInstruction(Inst, *OutContext.getSubtargetInfo());
266}
267
268void SPIRVAsmPrinter::outputInstruction(const MachineInstr *MI) {
Ilia Diachkovec259032022-04-14 01:10:25 +0300269 SPIRVMCInstLower MCInstLowering;
270 MCInst TmpInst;
Ilia Diachkov153dee32022-04-14 03:46:45 +0300271 MCInstLowering.lower(MI, TmpInst, MAI);
272 outputMCInst(TmpInst);
273}
274
275void SPIRVAsmPrinter::emitInstruction(const MachineInstr *MI) {
David Green3e0bf1c2022-07-14 09:33:28 +0100276 SPIRV_MC::verifyInstructionPredicates(MI->getOpcode(),
277 getSubtargetInfo().getFeatureBits());
278
Ilia Diachkov153dee32022-04-14 03:46:45 +0300279 if (!MAI->getSkipEmission(MI))
280 outputInstruction(MI);
281
282 // Output OpLabel after OpFunction and OpFunctionParameter in the first MBB.
283 const MachineInstr *NextMI = MI->getNextNode();
Vyacheslav Levytskyy874b4fb2024-12-03 16:18:06 +0100284 if (!LabeledMBB.contains(MI->getParent()) && isFuncOrHeaderInstr(MI, TII) &&
Ilia Diachkov153dee32022-04-14 03:46:45 +0300285 (!NextMI || !isFuncOrHeaderInstr(NextMI, TII))) {
286 assert(MI->getParent()->getNumber() == MF->front().getNumber() &&
287 "OpFunction is not in the front MBB of MF");
288 emitOpLabel(*MI->getParent());
289 }
290}
291
292void SPIRVAsmPrinter::outputModuleSection(SPIRV::ModuleSectionType MSType) {
Vyacheslav Levytskyy83c1d002025-01-07 10:42:23 +0100293 for (const MachineInstr *MI : MAI->getMSInstrs(MSType))
Ilia Diachkov153dee32022-04-14 03:46:45 +0300294 outputInstruction(MI);
295}
296
297void SPIRVAsmPrinter::outputDebugSourceAndStrings(const Module &M) {
Ilia Diachkovb8e15442022-07-20 18:48:16 +0300298 // Output OpSourceExtensions.
299 for (auto &Str : MAI->SrcExt) {
300 MCInst Inst;
301 Inst.setOpcode(SPIRV::OpSourceExtension);
302 addStringImm(Str.first(), Inst);
303 outputMCInst(Inst);
304 }
bwlodarcz62da3592024-08-23 05:27:36 +0200305 // Output OpString.
306 outputModuleSection(SPIRV::MB_DebugStrings);
Ilia Diachkov153dee32022-04-14 03:46:45 +0300307 // Output OpSource.
308 MCInst Inst;
309 Inst.setOpcode(SPIRV::OpSource);
310 Inst.addOperand(MCOperand::createImm(static_cast<unsigned>(MAI->SrcLang)));
311 Inst.addOperand(
312 MCOperand::createImm(static_cast<unsigned>(MAI->SrcLangVersion)));
313 outputMCInst(Inst);
314}
315
Ilia Diachkovb8e15442022-07-20 18:48:16 +0300316void SPIRVAsmPrinter::outputOpExtInstImports(const Module &M) {
317 for (auto &CU : MAI->ExtInstSetMap) {
318 unsigned Set = CU.first;
Craig Topper20120892025-03-03 08:43:02 -0800319 MCRegister Reg = CU.second;
Ilia Diachkovb8e15442022-07-20 18:48:16 +0300320 MCInst Inst;
321 Inst.setOpcode(SPIRV::OpExtInstImport);
322 Inst.addOperand(MCOperand::createReg(Reg));
Ilia Diachkovf61eb412022-08-24 02:13:19 +0300323 addStringImm(getExtInstSetName(
324 static_cast<SPIRV::InstructionSet::InstructionSet>(Set)),
Ilia Diachkovb8e15442022-07-20 18:48:16 +0300325 Inst);
326 outputMCInst(Inst);
327 }
328}
329
Ilia Diachkov153dee32022-04-14 03:46:45 +0300330void SPIRVAsmPrinter::outputOpMemoryModel() {
331 MCInst Inst;
332 Inst.setOpcode(SPIRV::OpMemoryModel);
333 Inst.addOperand(MCOperand::createImm(static_cast<unsigned>(MAI->Addr)));
334 Inst.addOperand(MCOperand::createImm(static_cast<unsigned>(MAI->Mem)));
335 outputMCInst(Inst);
336}
337
338// Before the OpEntryPoints' output, we need to add the entry point's
339// interfaces. The interface is a list of IDs of global OpVariable instructions.
340// These declare the set of global variables from a module that form
341// the interface of this entry point.
342void SPIRVAsmPrinter::outputEntryPoints() {
343 // Find all OpVariable IDs with required StorageClass.
Craig Topper20120892025-03-03 08:43:02 -0800344 DenseSet<MCRegister> InterfaceIDs;
Vyacheslav Levytskyy83c1d002025-01-07 10:42:23 +0100345 for (const MachineInstr *MI : MAI->GlobalVarList) {
Ilia Diachkov153dee32022-04-14 03:46:45 +0300346 assert(MI->getOpcode() == SPIRV::OpVariable);
Ilia Diachkovb25b5072022-08-01 22:56:31 +0300347 auto SC = static_cast<SPIRV::StorageClass::StorageClass>(
348 MI->getOperand(2).getImm());
Ilia Diachkov153dee32022-04-14 03:46:45 +0300349 // Before version 1.4, the interface's storage classes are limited to
350 // the Input and Output storage classes. Starting with version 1.4,
351 // the interface's storage classes are all storage classes used in
352 // declaring all global variables referenced by the entry point call tree.
Michal Paszkowskif352ce32024-04-22 10:47:46 -0700353 if (ST->isAtLeastSPIRVVer(VersionTuple(1, 4)) ||
354 SC == SPIRV::StorageClass::Input || SC == SPIRV::StorageClass::Output) {
Vyacheslav Levytskyy83c1d002025-01-07 10:42:23 +0100355 const MachineFunction *MF = MI->getMF();
Craig Topper20120892025-03-03 08:43:02 -0800356 MCRegister Reg = MAI->getRegisterAlias(MF, MI->getOperand(0).getReg());
Ilia Diachkov153dee32022-04-14 03:46:45 +0300357 InterfaceIDs.insert(Reg);
358 }
359 }
360
361 // Output OpEntryPoints adding interface args to all of them.
Vyacheslav Levytskyy83c1d002025-01-07 10:42:23 +0100362 for (const MachineInstr *MI : MAI->getMSInstrs(SPIRV::MB_EntryPoints)) {
Ilia Diachkov153dee32022-04-14 03:46:45 +0300363 SPIRVMCInstLower MCInstLowering;
364 MCInst TmpInst;
365 MCInstLowering.lower(MI, TmpInst, MAI);
Craig Topper20120892025-03-03 08:43:02 -0800366 for (MCRegister Reg : InterfaceIDs) {
Ilia Diachkov153dee32022-04-14 03:46:45 +0300367 assert(Reg.isValid());
368 TmpInst.addOperand(MCOperand::createReg(Reg));
369 }
370 outputMCInst(TmpInst);
371 }
372}
373
Ilia Diachkovdf871302022-08-11 00:37:46 +0300374// Create global OpCapability instructions for the required capabilities.
375void SPIRVAsmPrinter::outputGlobalRequirements() {
376 // Abort here if not all requirements can be satisfied.
377 MAI->Reqs.checkSatisfiable(*ST);
378
379 for (const auto &Cap : MAI->Reqs.getMinimalCapabilities()) {
380 MCInst Inst;
381 Inst.setOpcode(SPIRV::OpCapability);
382 Inst.addOperand(MCOperand::createImm(Cap));
383 outputMCInst(Inst);
384 }
385
386 // Generate the final OpExtensions with strings instead of enums.
387 for (const auto &Ext : MAI->Reqs.getExtensions()) {
388 MCInst Inst;
389 Inst.setOpcode(SPIRV::OpExtension);
390 addStringImm(getSymbolicOperandMnemonic(
391 SPIRV::OperandCategory::ExtensionOperand, Ext),
392 Inst);
393 outputMCInst(Inst);
394 }
395 // TODO add a pseudo instr for version number.
396}
397
Ilia Diachkov153dee32022-04-14 03:46:45 +0300398void SPIRVAsmPrinter::outputExtFuncDecls() {
399 // Insert OpFunctionEnd after each declaration.
Vyacheslav Levytskyy83c1d002025-01-07 10:42:23 +0100400 auto I = MAI->getMSInstrs(SPIRV::MB_ExtFuncDecls).begin(),
401 E = MAI->getMSInstrs(SPIRV::MB_ExtFuncDecls).end();
Ilia Diachkov153dee32022-04-14 03:46:45 +0300402 for (; I != E; ++I) {
403 outputInstruction(*I);
404 if ((I + 1) == E || (*(I + 1))->getOpcode() == SPIRV::OpFunction)
405 outputOpFunctionEnd();
406 }
407}
408
Ilia Diachkovb8e15442022-07-20 18:48:16 +0300409// Encode LLVM type by SPIR-V execution mode VecTypeHint.
410static unsigned encodeVecTypeHint(Type *Ty) {
411 if (Ty->isHalfTy())
412 return 4;
413 if (Ty->isFloatTy())
414 return 5;
415 if (Ty->isDoubleTy())
416 return 6;
417 if (IntegerType *IntTy = dyn_cast<IntegerType>(Ty)) {
418 switch (IntTy->getIntegerBitWidth()) {
419 case 8:
420 return 0;
421 case 16:
422 return 1;
423 case 32:
424 return 2;
425 case 64:
426 return 3;
427 default:
428 llvm_unreachable("invalid integer type");
429 }
430 }
431 if (FixedVectorType *VecTy = dyn_cast<FixedVectorType>(Ty)) {
432 Type *EleTy = VecTy->getElementType();
433 unsigned Size = VecTy->getNumElements();
434 return Size << 16 | encodeVecTypeHint(EleTy);
435 }
436 llvm_unreachable("invalid type");
437}
438
439static void addOpsFromMDNode(MDNode *MDN, MCInst &Inst,
440 SPIRV::ModuleAnalysisInfo *MAI) {
441 for (const MDOperand &MDOp : MDN->operands()) {
442 if (auto *CMeta = dyn_cast<ConstantAsMetadata>(MDOp)) {
443 Constant *C = CMeta->getValue();
444 if (ConstantInt *Const = dyn_cast<ConstantInt>(C)) {
445 Inst.addOperand(MCOperand::createImm(Const->getZExtValue()));
446 } else if (auto *CE = dyn_cast<Function>(C)) {
Craig Topper20120892025-03-03 08:43:02 -0800447 MCRegister FuncReg = MAI->getFuncReg(CE);
Ilia Diachkovb8e15442022-07-20 18:48:16 +0300448 assert(FuncReg.isValid());
449 Inst.addOperand(MCOperand::createReg(FuncReg));
450 }
451 }
452 }
453}
454
Ilia Diachkovb25b5072022-08-01 22:56:31 +0300455void SPIRVAsmPrinter::outputExecutionModeFromMDNode(
Craig Topper20120892025-03-03 08:43:02 -0800456 MCRegister Reg, MDNode *Node, SPIRV::ExecutionMode::ExecutionMode EM,
Vyacheslav Levytskyy0047df92024-05-20 19:05:25 +0200457 unsigned ExpectMDOps, int64_t DefVal) {
Ilia Diachkovb8e15442022-07-20 18:48:16 +0300458 MCInst Inst;
459 Inst.setOpcode(SPIRV::OpExecutionMode);
460 Inst.addOperand(MCOperand::createReg(Reg));
461 Inst.addOperand(MCOperand::createImm(static_cast<unsigned>(EM)));
462 addOpsFromMDNode(Node, Inst, MAI);
Vyacheslav Levytskyy0047df92024-05-20 19:05:25 +0200463 // reqd_work_group_size and work_group_size_hint require 3 operands,
464 // if metadata contains less operands, just add a default value
465 unsigned NodeSz = Node->getNumOperands();
466 if (ExpectMDOps > 0 && NodeSz < ExpectMDOps)
467 for (unsigned i = NodeSz; i < ExpectMDOps; ++i)
468 Inst.addOperand(MCOperand::createImm(DefVal));
Ilia Diachkovb8e15442022-07-20 18:48:16 +0300469 outputMCInst(Inst);
470}
471
Nathan Gauër56396b22023-07-24 13:28:09 +0200472void SPIRVAsmPrinter::outputExecutionModeFromNumthreadsAttribute(
Craig Topper20120892025-03-03 08:43:02 -0800473 const MCRegister &Reg, const Attribute &Attr,
Nathan Gauër56396b22023-07-24 13:28:09 +0200474 SPIRV::ExecutionMode::ExecutionMode EM) {
475 assert(Attr.isValid() && "Function called with an invalid attribute.");
476
477 MCInst Inst;
478 Inst.setOpcode(SPIRV::OpExecutionMode);
479 Inst.addOperand(MCOperand::createReg(Reg));
480 Inst.addOperand(MCOperand::createImm(static_cast<unsigned>(EM)));
481
482 SmallVector<StringRef> NumThreads;
483 Attr.getValueAsString().split(NumThreads, ',');
484 assert(NumThreads.size() == 3 && "invalid numthreads");
485 for (uint32_t i = 0; i < 3; ++i) {
486 uint32_t V;
487 [[maybe_unused]] bool Result = NumThreads[i].getAsInteger(10, V);
488 assert(!Result && "Failed to parse numthreads");
489 Inst.addOperand(MCOperand::createImm(V));
490 }
491
492 outputMCInst(Inst);
493}
494
Ilia Diachkovb8e15442022-07-20 18:48:16 +0300495void SPIRVAsmPrinter::outputExecutionMode(const Module &M) {
496 NamedMDNode *Node = M.getNamedMetadata("spirv.ExecutionMode");
497 if (Node) {
498 for (unsigned i = 0; i < Node->getNumOperands(); i++) {
499 MCInst Inst;
500 Inst.setOpcode(SPIRV::OpExecutionMode);
501 addOpsFromMDNode(cast<MDNode>(Node->getOperand(i)), Inst, MAI);
502 outputMCInst(Inst);
503 }
504 }
505 for (auto FI = M.begin(), E = M.end(); FI != E; ++FI) {
506 const Function &F = *FI;
Vyacheslav Levytskyy8e8f9c02024-02-19 20:51:32 +0100507 // Only operands of OpEntryPoint instructions are allowed to be
508 // <Entry Point> operands of OpExecutionMode
509 if (F.isDeclaration() || !isEntryPoint(F))
Ilia Diachkovb8e15442022-07-20 18:48:16 +0300510 continue;
Craig Topper20120892025-03-03 08:43:02 -0800511 MCRegister FReg = MAI->getFuncReg(&F);
Ilia Diachkovb8e15442022-07-20 18:48:16 +0300512 assert(FReg.isValid());
513 if (MDNode *Node = F.getMetadata("reqd_work_group_size"))
Vyacheslav Levytskyy0047df92024-05-20 19:05:25 +0200514 outputExecutionModeFromMDNode(FReg, Node, SPIRV::ExecutionMode::LocalSize,
515 3, 1);
Nathan Gauër56396b22023-07-24 13:28:09 +0200516 if (Attribute Attr = F.getFnAttribute("hlsl.numthreads"); Attr.isValid())
517 outputExecutionModeFromNumthreadsAttribute(
518 FReg, Attr, SPIRV::ExecutionMode::LocalSize);
Ilia Diachkovb8e15442022-07-20 18:48:16 +0300519 if (MDNode *Node = F.getMetadata("work_group_size_hint"))
520 outputExecutionModeFromMDNode(FReg, Node,
Vyacheslav Levytskyy0047df92024-05-20 19:05:25 +0200521 SPIRV::ExecutionMode::LocalSizeHint, 3, 1);
Ilia Diachkovb8e15442022-07-20 18:48:16 +0300522 if (MDNode *Node = F.getMetadata("intel_reqd_sub_group_size"))
523 outputExecutionModeFromMDNode(FReg, Node,
Vyacheslav Levytskyy0047df92024-05-20 19:05:25 +0200524 SPIRV::ExecutionMode::SubgroupSize, 0, 0);
Ilia Diachkovb8e15442022-07-20 18:48:16 +0300525 if (MDNode *Node = F.getMetadata("vec_type_hint")) {
526 MCInst Inst;
527 Inst.setOpcode(SPIRV::OpExecutionMode);
528 Inst.addOperand(MCOperand::createReg(FReg));
529 unsigned EM = static_cast<unsigned>(SPIRV::ExecutionMode::VecTypeHint);
530 Inst.addOperand(MCOperand::createImm(EM));
531 unsigned TypeCode = encodeVecTypeHint(getMDOperandAsType(Node, 0));
532 Inst.addOperand(MCOperand::createImm(TypeCode));
533 outputMCInst(Inst);
534 }
Nathan Gauër56396b22023-07-24 13:28:09 +0200535 if (ST->isOpenCLEnv() && !M.getNamedMetadata("spirv.ExecutionMode") &&
Michal Paszkowski2bcedd42023-01-18 22:23:11 +0100536 !M.getNamedMetadata("opencl.enable.FP_CONTRACT")) {
537 MCInst Inst;
538 Inst.setOpcode(SPIRV::OpExecutionMode);
539 Inst.addOperand(MCOperand::createReg(FReg));
540 unsigned EM = static_cast<unsigned>(SPIRV::ExecutionMode::ContractionOff);
541 Inst.addOperand(MCOperand::createImm(EM));
542 outputMCInst(Inst);
543 }
Ilia Diachkovb8e15442022-07-20 18:48:16 +0300544 }
545}
546
547void SPIRVAsmPrinter::outputAnnotations(const Module &M) {
548 outputModuleSection(SPIRV::MB_Annotations);
549 // Process llvm.global.annotations special global variable.
550 for (auto F = M.global_begin(), E = M.global_end(); F != E; ++F) {
551 if ((*F).getName() != "llvm.global.annotations")
552 continue;
553 const GlobalVariable *V = &(*F);
554 const ConstantArray *CA = cast<ConstantArray>(V->getOperand(0));
555 for (Value *Op : CA->operands()) {
556 ConstantStruct *CS = cast<ConstantStruct>(Op);
557 // The first field of the struct contains a pointer to
558 // the annotated variable.
559 Value *AnnotatedVar = CS->getOperand(0)->stripPointerCasts();
560 if (!isa<Function>(AnnotatedVar))
Michal Paszkowski7a3c9a82022-10-06 21:35:41 +0200561 report_fatal_error("Unsupported value in llvm.global.annotations");
Ilia Diachkovb8e15442022-07-20 18:48:16 +0300562 Function *Func = cast<Function>(AnnotatedVar);
Craig Topper20120892025-03-03 08:43:02 -0800563 MCRegister Reg = MAI->getFuncReg(Func);
Vyacheslav Levytskyy59f34e82024-03-18 11:42:44 +0100564 if (!Reg.isValid()) {
565 std::string DiagMsg;
566 raw_string_ostream OS(DiagMsg);
567 AnnotatedVar->print(OS);
568 DiagMsg = "Unknown function in llvm.global.annotations: " + DiagMsg;
569 report_fatal_error(DiagMsg.c_str());
570 }
Ilia Diachkovb8e15442022-07-20 18:48:16 +0300571
572 // The second field contains a pointer to a global annotation string.
573 GlobalVariable *GV =
574 cast<GlobalVariable>(CS->getOperand(1)->stripPointerCasts());
575
576 StringRef AnnotationString;
577 getConstantStringInfo(GV, AnnotationString);
578 MCInst Inst;
579 Inst.setOpcode(SPIRV::OpDecorate);
580 Inst.addOperand(MCOperand::createReg(Reg));
581 unsigned Dec = static_cast<unsigned>(SPIRV::Decoration::UserSemantic);
582 Inst.addOperand(MCOperand::createImm(Dec));
583 addStringImm(AnnotationString, Inst);
584 outputMCInst(Inst);
585 }
586 }
587}
588
Ilia Diachkov153dee32022-04-14 03:46:45 +0300589void SPIRVAsmPrinter::outputModuleSections() {
590 const Module *M = MMI->getModule();
591 // Get the global subtarget to output module-level info.
592 ST = static_cast<const SPIRVTargetMachine &>(TM).getSubtargetImpl();
593 TII = ST->getInstrInfo();
594 MAI = &SPIRVModuleAnalysis::MAI;
595 assert(ST && TII && MAI && M && "Module analysis is required");
596 // Output instructions according to the Logical Layout of a Module:
Ilia Diachkovdf871302022-08-11 00:37:46 +0300597 // 1,2. All OpCapability instructions, then optional OpExtension instructions.
598 outputGlobalRequirements();
Ilia Diachkovb8e15442022-07-20 18:48:16 +0300599 // 3. Optional OpExtInstImport instructions.
600 outputOpExtInstImports(*M);
Ilia Diachkov153dee32022-04-14 03:46:45 +0300601 // 4. The single required OpMemoryModel instruction.
602 outputOpMemoryModel();
603 // 5. All entry point declarations, using OpEntryPoint.
604 outputEntryPoints();
605 // 6. Execution-mode declarations, using OpExecutionMode or OpExecutionModeId.
Ilia Diachkovb8e15442022-07-20 18:48:16 +0300606 outputExecutionMode(*M);
Ilia Diachkov153dee32022-04-14 03:46:45 +0300607 // 7a. Debug: all OpString, OpSourceExtension, OpSource, and
608 // OpSourceContinued, without forward references.
609 outputDebugSourceAndStrings(*M);
610 // 7b. Debug: all OpName and all OpMemberName.
611 outputModuleSection(SPIRV::MB_DebugNames);
612 // 7c. Debug: all OpModuleProcessed instructions.
613 outputModuleSection(SPIRV::MB_DebugModuleProcessed);
614 // 8. All annotation instructions (all decorations).
Ilia Diachkovb8e15442022-07-20 18:48:16 +0300615 outputAnnotations(*M);
Ilia Diachkov153dee32022-04-14 03:46:45 +0300616 // 9. All type declarations (OpTypeXXX instructions), all constant
617 // instructions, and all global variable declarations. This section is
618 // the first section to allow use of: OpLine and OpNoLine debug information;
619 // non-semantic instructions with OpExtInst.
620 outputModuleSection(SPIRV::MB_TypeConstVars);
bwlodarcz62da3592024-08-23 05:27:36 +0200621 // 10. All global NonSemantic.Shader.DebugInfo.100 instructions.
622 outputModuleSection(SPIRV::MB_NonSemanticGlobalDI);
623 // 11. All function declarations (functions without a body).
Ilia Diachkov153dee32022-04-14 03:46:45 +0300624 outputExtFuncDecls();
bwlodarcz62da3592024-08-23 05:27:36 +0200625 // 12. All function definitions (functions with a body).
Ilia Diachkov153dee32022-04-14 03:46:45 +0300626 // This is done in regular function output.
627}
628
629bool SPIRVAsmPrinter::doInitialization(Module &M) {
630 ModuleSectionsEmitted = false;
631 // We need to call the parent's one explicitly.
632 return AsmPrinter::doInitialization(M);
Ilia Diachkovec259032022-04-14 01:10:25 +0300633}
634
635// Force static initialization.
636extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSPIRVAsmPrinter() {
637 RegisterAsmPrinter<SPIRVAsmPrinter> X(getTheSPIRV32Target());
638 RegisterAsmPrinter<SPIRVAsmPrinter> Y(getTheSPIRV64Target());
Nathan Gauër56396b22023-07-24 13:28:09 +0200639 RegisterAsmPrinter<SPIRVAsmPrinter> Z(getTheSPIRVLogicalTarget());
Ilia Diachkovec259032022-04-14 01:10:25 +0300640}