| # REQUIRES: amdgpu-registered-target |
| # RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=none -o /dev/null %s 2>&1 | FileCheck %s |
| |
| --- |
| name: invalid_reg_sequence |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| %0:vgpr_32 = IMPLICIT_DEF |
| %1:vgpr_32 = IMPLICIT_DEF |
| |
| ; No operands |
| ; CHECK: *** Bad machine code: Too few operands *** |
| REG_SEQUENCE |
| |
| ; Only dest operand |
| ; CHECK: *** Bad machine code: Too few operands *** |
| %2:vreg_64 = REG_SEQUENCE |
| |
| ; Missing destination |
| ; CHECK: *** Bad machine code: Explicit definition marked as use *** |
| REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1 |
| |
| ; Missing subreg operand |
| ; CHECK: *** Bad machine code: Invalid number of operands for REG_SEQUENCE *** |
| %3:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, %1 |
| |
| ; Missing register operand |
| ; CHECK: *** Bad machine code: Invalid number of operands for REG_SEQUENCE *** |
| %4:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, %subreg.sub1 |
| |
| ; Physreg destination |
| ; CHECK: *** Bad machine code: REG_SEQUENCE does not support physical register results *** |
| $vgpr0_vgpr1 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1 |
| |
| ; Subreg in destination |
| ; CHECK: *** Bad machine code: Invalid subreg result for REG_SEQUENCE *** |
| %5.sub0_sub1:vreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1 |
| |
| ; All operands are registers |
| ; CHECK: *** Bad machine code: Invalid subregister index operand for REG_SEQUENCE *** |
| %6:vreg_64 = REG_SEQUENCE %0, %1 |
| |
| ; Register and subreg index operand order swapped |
| ; CHECK: *** Bad machine code: Invalid register operand for REG_SEQUENCE *** |
| ; CHECK: *** Bad machine code: Invalid subregister index operand for REG_SEQUENCE *** |
| %7:vreg_64 = REG_SEQUENCE %subreg.sub0, %0, %subreg.sub1, %1 |
| |
| ; Invalid subreg index constants |
| ; CHECK: *** Bad machine code: Invalid subregister index operand for REG_SEQUENCE *** |
| ; CHECK: - instruction: %8:vreg_64 = REG_SEQUENCE %0:vgpr_32, %subreg.0, %1:vgpr_32, %subreg.99999 |
| ; CHECK-NEXT: operand 2: 0 |
| |
| ; CHECK: *** Bad machine code: Invalid subregister index operand for REG_SEQUENCE *** |
| ; CHECK: instruction: %8:vreg_64 = REG_SEQUENCE %0:vgpr_32, %subreg.0, %1:vgpr_32, %subreg.99999 |
| ; CHECK-NEXT: operand 4: 99999 |
| %8:vreg_64 = REG_SEQUENCE %0, 0, %1, 99999 |
| |
| ... |