llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN:   | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
; RUN:   < %s | FileCheck -check-prefix=RV32IZFH %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN:   | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
; RUN:   < %s | FileCheck -check-prefix=RV64IZFH %s
; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
; RUN:   < %s | FileCheck -check-prefix=RV32IZFHMIN %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN:   | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
; RUN:   < %s | FileCheck -check-prefix=RV64IZFHMIN %s

; This file tests cases where simple floating point operations can be
; profitably handled though bit manipulation if a soft-float ABI is being used
; (e.g. fneg implemented by XORing the sign bit). This is typically handled in
; DAGCombiner::visitBITCAST, but this target-independent code may not trigger
; in cases where we perform custom legalisation (e.g. RV64F).

define half @fneg(half %a) nounwind {
; RV32I-LABEL: fneg:
; RV32I:       # %bb.0:
; RV32I-NEXT:    lui a1, 1048568
; RV32I-NEXT:    xor a0, a0, a1
; RV32I-NEXT:    ret
;
; RV32IZFH-LABEL: fneg:
; RV32IZFH:       # %bb.0:
; RV32IZFH-NEXT:    lui a1, 1048568
; RV32IZFH-NEXT:    xor a0, a0, a1
; RV32IZFH-NEXT:    ret
;
; RV64I-LABEL: fneg:
; RV64I:       # %bb.0:
; RV64I-NEXT:    lui a1, 1048568
; RV64I-NEXT:    xor a0, a0, a1
; RV64I-NEXT:    ret
;
; RV64IZFH-LABEL: fneg:
; RV64IZFH:       # %bb.0:
; RV64IZFH-NEXT:    lui a1, 1048568
; RV64IZFH-NEXT:    xor a0, a0, a1
; RV64IZFH-NEXT:    ret
;
; RV32IZFHMIN-LABEL: fneg:
; RV32IZFHMIN:       # %bb.0:
; RV32IZFHMIN-NEXT:    lui a1, 1048568
; RV32IZFHMIN-NEXT:    xor a0, a0, a1
; RV32IZFHMIN-NEXT:    ret
;
; RV64IZFHMIN-LABEL: fneg:
; RV64IZFHMIN:       # %bb.0:
; RV64IZFHMIN-NEXT:    lui a1, 1048568
; RV64IZFHMIN-NEXT:    xor a0, a0, a1
; RV64IZFHMIN-NEXT:    ret
  %1 = fneg half %a
  ret half %1
}

declare half @llvm.fabs.f16(half)

define half @fabs(half %a) nounwind {
; RV32I-LABEL: fabs:
; RV32I:       # %bb.0:
; RV32I-NEXT:    slli a0, a0, 17
; RV32I-NEXT:    srli a0, a0, 17
; RV32I-NEXT:    ret
;
; RV32IZFH-LABEL: fabs:
; RV32IZFH:       # %bb.0:
; RV32IZFH-NEXT:    slli a0, a0, 17
; RV32IZFH-NEXT:    srli a0, a0, 17
; RV32IZFH-NEXT:    ret
;
; RV64I-LABEL: fabs:
; RV64I:       # %bb.0:
; RV64I-NEXT:    slli a0, a0, 49
; RV64I-NEXT:    srli a0, a0, 49
; RV64I-NEXT:    ret
;
; RV64IZFH-LABEL: fabs:
; RV64IZFH:       # %bb.0:
; RV64IZFH-NEXT:    slli a0, a0, 49
; RV64IZFH-NEXT:    srli a0, a0, 49
; RV64IZFH-NEXT:    ret
;
; RV32IZFHMIN-LABEL: fabs:
; RV32IZFHMIN:       # %bb.0:
; RV32IZFHMIN-NEXT:    slli a0, a0, 17
; RV32IZFHMIN-NEXT:    srli a0, a0, 17
; RV32IZFHMIN-NEXT:    ret
;
; RV64IZFHMIN-LABEL: fabs:
; RV64IZFHMIN:       # %bb.0:
; RV64IZFHMIN-NEXT:    slli a0, a0, 49
; RV64IZFHMIN-NEXT:    srli a0, a0, 49
; RV64IZFHMIN-NEXT:    ret
  %1 = call half @llvm.fabs.f16(half %a)
  ret half %1
}

declare half @llvm.copysign.f16(half, half)

; DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN will convert to bitwise
; operations if half precision floating point isn't supported. A combine could
; be written to do the same even when f16 is legal.

define half @fcopysign_fneg(half %a, half %b) nounwind {
; RV32I-LABEL: fcopysign_fneg:
; RV32I:       # %bb.0:
; RV32I-NEXT:    not a1, a1
; RV32I-NEXT:    lui a2, 1048568
; RV32I-NEXT:    and a1, a1, a2
; RV32I-NEXT:    slli a0, a0, 17
; RV32I-NEXT:    srli a0, a0, 17
; RV32I-NEXT:    or a0, a0, a1
; RV32I-NEXT:    ret
;
; RV32IZFH-LABEL: fcopysign_fneg:
; RV32IZFH:       # %bb.0:
; RV32IZFH-NEXT:    fmv.h.x ft0, a1
; RV32IZFH-NEXT:    fmv.h.x ft1, a0
; RV32IZFH-NEXT:    fsgnjn.h ft0, ft1, ft0
; RV32IZFH-NEXT:    fmv.x.h a0, ft0
; RV32IZFH-NEXT:    ret
;
; RV64I-LABEL: fcopysign_fneg:
; RV64I:       # %bb.0:
; RV64I-NEXT:    not a1, a1
; RV64I-NEXT:    lui a2, 1048568
; RV64I-NEXT:    and a1, a1, a2
; RV64I-NEXT:    slli a0, a0, 49
; RV64I-NEXT:    srli a0, a0, 49
; RV64I-NEXT:    or a0, a0, a1
; RV64I-NEXT:    ret
;
; RV64IZFH-LABEL: fcopysign_fneg:
; RV64IZFH:       # %bb.0:
; RV64IZFH-NEXT:    fmv.h.x ft0, a1
; RV64IZFH-NEXT:    fmv.h.x ft1, a0
; RV64IZFH-NEXT:    fsgnjn.h ft0, ft1, ft0
; RV64IZFH-NEXT:    fmv.x.h a0, ft0
; RV64IZFH-NEXT:    ret
;
; RV32IZFHMIN-LABEL: fcopysign_fneg:
; RV32IZFHMIN:       # %bb.0:
; RV32IZFHMIN-NEXT:    addi sp, sp, -16
; RV32IZFHMIN-NEXT:    fmv.h.x ft0, a0
; RV32IZFHMIN-NEXT:    fmv.h.x ft1, a1
; RV32IZFHMIN-NEXT:    fcvt.s.h ft1, ft1
; RV32IZFHMIN-NEXT:    fneg.s ft1, ft1
; RV32IZFHMIN-NEXT:    fcvt.h.s ft1, ft1
; RV32IZFHMIN-NEXT:    fsh ft0, 8(sp)
; RV32IZFHMIN-NEXT:    fsh ft1, 12(sp)
; RV32IZFHMIN-NEXT:    lbu a0, 9(sp)
; RV32IZFHMIN-NEXT:    lbu a1, 13(sp)
; RV32IZFHMIN-NEXT:    andi a0, a0, 127
; RV32IZFHMIN-NEXT:    andi a1, a1, 128
; RV32IZFHMIN-NEXT:    or a0, a0, a1
; RV32IZFHMIN-NEXT:    sb a0, 9(sp)
; RV32IZFHMIN-NEXT:    flh ft0, 8(sp)
; RV32IZFHMIN-NEXT:    fmv.x.h a0, ft0
; RV32IZFHMIN-NEXT:    addi sp, sp, 16
; RV32IZFHMIN-NEXT:    ret
;
; RV64IZFHMIN-LABEL: fcopysign_fneg:
; RV64IZFHMIN:       # %bb.0:
; RV64IZFHMIN-NEXT:    addi sp, sp, -16
; RV64IZFHMIN-NEXT:    fmv.h.x ft0, a0
; RV64IZFHMIN-NEXT:    fmv.h.x ft1, a1
; RV64IZFHMIN-NEXT:    fcvt.s.h ft1, ft1
; RV64IZFHMIN-NEXT:    fneg.s ft1, ft1
; RV64IZFHMIN-NEXT:    fcvt.h.s ft1, ft1
; RV64IZFHMIN-NEXT:    fsh ft0, 0(sp)
; RV64IZFHMIN-NEXT:    fsh ft1, 8(sp)
; RV64IZFHMIN-NEXT:    lbu a0, 1(sp)
; RV64IZFHMIN-NEXT:    lbu a1, 9(sp)
; RV64IZFHMIN-NEXT:    andi a0, a0, 127
; RV64IZFHMIN-NEXT:    andi a1, a1, 128
; RV64IZFHMIN-NEXT:    or a0, a0, a1
; RV64IZFHMIN-NEXT:    sb a0, 1(sp)
; RV64IZFHMIN-NEXT:    flh ft0, 0(sp)
; RV64IZFHMIN-NEXT:    fmv.x.h a0, ft0
; RV64IZFHMIN-NEXT:    addi sp, sp, 16
; RV64IZFHMIN-NEXT:    ret
  %1 = fneg half %b
  %2 = call half @llvm.copysign.f16(half %a, half %1)
  ret half %2
}