llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-hoist-same-hands.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s

...
---
name:            or_combine_sext
tracksRegLiveness: true
legalized: true
body:             |
  bb.0:
    liveins: $w0, $w1
    ; or (sext X), (sext Y) --> sext (or X, Y)
    ; CHECK-LABEL: name: or_combine_sext
    ; CHECK: liveins: $w0, $w1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %x:_(s32) = COPY $w0
    ; CHECK-NEXT: %y:_(s32) = COPY $w1
    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR %x, %y
    ; CHECK-NEXT: %logic_op:_(s64) = G_SEXT [[OR]](s32)
    ; CHECK-NEXT: $x0 = COPY %logic_op(s64)
    ; CHECK-NEXT: RET_ReallyLR implicit $x0
    %x:_(s32) = COPY $w0
    %y:_(s32) = COPY $w1
    %hand1:_(s64) = G_SEXT %x(s32)
    %hand2:_(s64) = G_SEXT %y(s32)
    %logic_op:_(s64) = G_OR %hand1, %hand2
    $x0 = COPY %logic_op(s64)
    RET_ReallyLR implicit $x0

...
---
name:            illegal_ty
tracksRegLiveness: true
legalized: true
body:             |
  bb.0:
    liveins: $w0, $w1
    ; Post-legalization, we should not perform the optimization here, since
    ; it would create an illegal G_OR.
    ; CHECK-LABEL: name: illegal_ty
    ; CHECK: liveins: $w0, $w1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %x_wide:_(s32) = COPY $w0
    ; CHECK-NEXT: %y_wide:_(s32) = COPY $w1
    ; CHECK-NEXT: %x:_(s1) = G_TRUNC %x_wide(s32)
    ; CHECK-NEXT: %y:_(s1) = G_TRUNC %y_wide(s32)
    ; CHECK-NEXT: %hand1:_(s64) = G_SEXT %x(s1)
    ; CHECK-NEXT: %hand2:_(s64) = G_SEXT %y(s1)
    ; CHECK-NEXT: %logic_op:_(s64) = G_OR %hand1, %hand2
    ; CHECK-NEXT: $x0 = COPY %logic_op(s64)
    ; CHECK-NEXT: RET_ReallyLR implicit $x0
    %x_wide:_(s32) = COPY $w0
    %y_wide:_(s32) = COPY $w1
    %x:_(s1) = G_TRUNC %x_wide
    %y:_(s1) = G_TRUNC %y_wide
    %hand1:_(s64) = G_SEXT %x(s1)
    %hand2:_(s64) = G_SEXT %y(s1)
    %logic_op:_(s64) = G_OR %hand1, %hand2
    $x0 = COPY %logic_op(s64)
    RET_ReallyLR implicit $x0

...
---
name:            dont_combine_physreg
tracksRegLiveness: true
legalized: true
body:             |
  bb.0:
    liveins: $w0, $w1
    ; Post-legalization, we must not crash here.
    ; CHECK-LABEL: name: dont_combine_physreg
    ; CHECK: liveins: $w0, $w1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %x:_(s32) = COPY $w0
    ; CHECK-NEXT: %y:_(s32) = COPY $w1
    ; CHECK-NEXT: %logic_op:_(s32) = G_OR %x, %y
    ; CHECK-NEXT: $w0 = COPY %logic_op(s32)
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %x:_(s32) = COPY $w0
    %y:_(s32) = COPY $w1
    %logic_op:_(s32) = G_OR %x, %y
    $w0 = COPY %logic_op(s32)
    RET_ReallyLR implicit $w0