| ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 | |
| ; RUN: opt < %s -passes=loop-interchange -loop-interchange-profitabilities=ignore -S | FileCheck %s | |
| ; The outer loop preheader contains an indirectbr instruction, so we cannot | |
| ; interchange the loops. | |
| ; | |
| define void @outer_ph_indirectbr(ptr %A) { | |
| ; CHECK-LABEL: define void @outer_ph_indirectbr( | |
| ; CHECK-SAME: ptr [[A:%.*]]) { | |
| ; CHECK-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-NEXT: indirectbr ptr blockaddress(@outer_ph_indirectbr, %[[OUTER_HEADER:.*]]), [label %[[OUTER_HEADER]]] | |
| ; CHECK: [[OUTER_HEADER]]: | |
| ; CHECK-NEXT: [[I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[I_INC:%.*]], %[[OUTER_LATCH:.*]] ] | |
| ; CHECK-NEXT: br label %[[INNER:.*]] | |
| ; CHECK: [[INNER]]: | |
| ; CHECK-NEXT: [[J:%.*]] = phi i64 [ 0, %[[OUTER_HEADER]] ], [ [[J_INC:%.*]], %[[INNER]] ] | |
| ; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds [4 x i8], ptr [[A]], i64 [[J]], i64 [[I]] | |
| ; CHECK-NEXT: store i8 0, ptr [[GEP]], align 1 | |
| ; CHECK-NEXT: [[J_INC]] = add i64 [[J]], 1 | |
| ; CHECK-NEXT: [[EC_J:%.*]] = icmp eq i64 [[J_INC]], 4 | |
| ; CHECK-NEXT: br i1 [[EC_J]], label %[[OUTER_LATCH]], label %[[INNER]] | |
| ; CHECK: [[OUTER_LATCH]]: | |
| ; CHECK-NEXT: [[I_INC]] = add i64 [[I]], 1 | |
| ; CHECK-NEXT: [[EC_I:%.*]] = icmp eq i64 [[I_INC]], 4 | |
| ; CHECK-NEXT: br i1 [[EC_I]], label %[[EXIT:.*]], label %[[OUTER_HEADER]] | |
| ; CHECK: [[EXIT]]: | |
| ; CHECK-NEXT: ret void | |
| ; | |
| entry: | |
| indirectbr ptr blockaddress(@outer_ph_indirectbr, %outer.header), [ label %outer.header ] | |
| outer.header: | |
| %i = phi i64 [ 0, %entry ], [ %i.inc, %outer.latch ] | |
| br label %inner | |
| inner: | |
| %j = phi i64 [ 0, %outer.header ], [ %j.inc, %inner ] | |
| %gep = getelementptr inbounds [4 x i8], ptr %A, i64 %j, i64 %i | |
| store i8 0, ptr %gep | |
| %j.inc = add i64 %j, 1 | |
| %ec.j = icmp eq i64 %j.inc, 4 | |
| br i1 %ec.j, label %outer.latch, label %inner | |
| outer.latch: | |
| %i.inc = add i64 %i, 1 | |
| %ec.i = icmp eq i64 %i.inc, 4 | |
| br i1 %ec.i, label %exit, label %outer.header | |
| exit: | |
| ret void | |
| } | |
| ; The inner loop preheader contains an indirectbr instruction, so we cannot | |
| ; interchange the loops. | |
| ; | |
| define void @inner_ph_indirectbr(ptr %A) { | |
| ; CHECK-LABEL: define void @inner_ph_indirectbr( | |
| ; CHECK-SAME: ptr [[A:%.*]]) { | |
| ; CHECK-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-NEXT: br label %[[OUTER_HEADER:.*]] | |
| ; CHECK: [[OUTER_HEADER]]: | |
| ; CHECK-NEXT: [[I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[I_INC:%.*]], %[[OUTER_LATCH:.*]] ] | |
| ; CHECK-NEXT: indirectbr ptr blockaddress(@inner_ph_indirectbr, %[[INNER:.*]]), [label %[[INNER]]] | |
| ; CHECK: [[INNER]]: | |
| ; CHECK-NEXT: [[J:%.*]] = phi i64 [ 0, %[[OUTER_HEADER]] ], [ [[J_INC:%.*]], %[[INNER]] ] | |
| ; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds [4 x i8], ptr [[A]], i64 [[J]], i64 [[I]] | |
| ; CHECK-NEXT: store i8 0, ptr [[GEP]], align 1 | |
| ; CHECK-NEXT: [[J_INC]] = add i64 [[J]], 1 | |
| ; CHECK-NEXT: [[EC_J:%.*]] = icmp eq i64 [[J_INC]], 4 | |
| ; CHECK-NEXT: br i1 [[EC_J]], label %[[OUTER_LATCH]], label %[[INNER]] | |
| ; CHECK: [[OUTER_LATCH]]: | |
| ; CHECK-NEXT: [[I_INC]] = add i64 [[I]], 1 | |
| ; CHECK-NEXT: [[EC_I:%.*]] = icmp eq i64 [[I_INC]], 4 | |
| ; CHECK-NEXT: br i1 [[EC_I]], label %[[EXIT:.*]], label %[[OUTER_HEADER]] | |
| ; CHECK: [[EXIT]]: | |
| ; CHECK-NEXT: ret void | |
| ; | |
| entry: | |
| br label %outer.header | |
| outer.header: | |
| %i = phi i64 [ 0, %entry ], [ %i.inc, %outer.latch ] | |
| indirectbr ptr blockaddress(@inner_ph_indirectbr, %inner), [ label %inner ] | |
| inner: | |
| %j = phi i64 [ 0, %outer.header ], [ %j.inc, %inner ] | |
| %gep = getelementptr inbounds [4 x i8], ptr %A, i64 %j, i64 %i | |
| store i8 0, ptr %gep | |
| %j.inc = add i64 %j, 1 | |
| %ec.j = icmp eq i64 %j.inc, 4 | |
| br i1 %ec.j, label %outer.latch, label %inner | |
| outer.latch: | |
| %i.inc = add i64 %i, 1 | |
| %ec.i = icmp eq i64 %i.inc, 4 | |
| br i1 %ec.i, label %exit, label %outer.header | |
| exit: | |
| ret void | |
| } | |
| ; We only support outer loop header PHIs if they are induction variables or if | |
| ; they have exactly two incoming values. In common cases, we can reduce the | |
| ; number of incoming values to two by inserting a preheader block, but in this | |
| ; case we cannot do that because one of the predecessors branches to the outer | |
| ; loop header via an indirectbr instruction. Previously, this test case caused | |
| ; an assertion failure. | |
| ; | |
| define void @indirectbr_to_outer_header(i1 %c, i32 %x, i32 %y, ptr %A) { | |
| ; CHECK-LABEL: define void @indirectbr_to_outer_header( | |
| ; CHECK-SAME: i1 [[C:%.*]], i32 [[X:%.*]], i32 [[Y:%.*]], ptr [[A:%.*]]) { | |
| ; CHECK-NEXT: [[ENTRY:.*:]] | |
| ; CHECK-NEXT: br i1 [[C]], label %[[ENTRY_0:.*]], label %[[ENTRY_1:.*]] | |
| ; CHECK: [[ENTRY_0]]: | |
| ; CHECK-NEXT: br label %[[OUTER_HEADER:.*]] | |
| ; CHECK: [[ENTRY_1]]: | |
| ; CHECK-NEXT: indirectbr ptr blockaddress(@indirectbr_to_outer_header, %[[OUTER_HEADER]]), [label %[[OUTER_HEADER]]] | |
| ; CHECK: [[OUTER_HEADER]]: | |
| ; CHECK-NEXT: [[I:%.*]] = phi i64 [ 0, %[[ENTRY_0]] ], [ 0, %[[ENTRY_1]] ], [ [[I_NEXT:%.*]], %[[OUTER_LATCH:.*]] ] | |
| ; CHECK-NEXT: [[SEL:%.*]] = phi i32 [ [[X]], %[[ENTRY_0]] ], [ [[Y]], %[[ENTRY_1]] ], [ [[SEL]], %[[OUTER_LATCH]] ] | |
| ; CHECK-NEXT: br label %[[INNER:.*]] | |
| ; CHECK: [[INNER]]: | |
| ; CHECK-NEXT: [[J:%.*]] = phi i64 [ 0, %[[OUTER_HEADER]] ], [ [[J_NEXT:%.*]], %[[INNER]] ] | |
| ; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds [256 x i32], ptr [[A]], i64 [[J]], i64 [[I]] | |
| ; CHECK-NEXT: store i32 [[SEL]], ptr [[GEP]], align 4 | |
| ; CHECK-NEXT: [[J_NEXT]] = add i64 [[J]], 1 | |
| ; CHECK-NEXT: [[EC_J:%.*]] = icmp eq i64 [[J_NEXT]], 256 | |
| ; CHECK-NEXT: br i1 [[EC_J]], label %[[OUTER_LATCH]], label %[[INNER]] | |
| ; CHECK: [[OUTER_LATCH]]: | |
| ; CHECK-NEXT: [[I_NEXT]] = add i64 [[I]], 1 | |
| ; CHECK-NEXT: [[EC_I:%.*]] = icmp eq i64 [[I_NEXT]], 256 | |
| ; CHECK-NEXT: br i1 [[EC_I]], label %[[EXIT:.*]], label %[[OUTER_HEADER]] | |
| ; CHECK: [[EXIT]]: | |
| ; CHECK-NEXT: ret void | |
| ; | |
| entry: | |
| br i1 %c, label %entry.0, label %entry.1 | |
| entry.0: | |
| br label %outer.header | |
| entry.1: | |
| indirectbr ptr blockaddress(@indirectbr_to_outer_header, %outer.header), [ label %outer.header ] | |
| outer.header: | |
| %i = phi i64 [ 0, %entry.0 ], [ 0, %entry.1 ], [ %i.next, %outer.latch ] | |
| %sel = phi i32 [ %x, %entry.0 ], [ %y, %entry.1 ], [ %sel, %outer.latch ] | |
| br label %inner | |
| inner: | |
| %j = phi i64 [ 0, %outer.header ], [ %j.next, %inner ] | |
| %gep = getelementptr inbounds [256 x i32], ptr %A, i64 %j, i64 %i | |
| store i32 %sel, ptr %gep | |
| %j.next = add i64 %j, 1 | |
| %ec.j = icmp eq i64 %j.next, 256 | |
| br i1 %ec.j, label %outer.latch, label %inner | |
| outer.latch: | |
| %i.next = add i64 %i, 1 | |
| %ec.i = icmp eq i64 %i.next, 256 | |
| br i1 %ec.i, label %exit, label %outer.header | |
| exit: | |
| ret void | |
| } |