llvm/test/Transforms/IndVarSimplify/pr66986.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
; RUN: opt -S -passes=indvars < %s | FileCheck %s

target datalayout = "n8:16:32:64"

; The udiv should not get hoisted into the preheader (past a conditional).
define i32 @test(i1 %c, i32 %arg1, i32 %arg2) {
; CHECK-LABEL: define i32 @test(
; CHECK-SAME: i1 [[C:%.*]], i32 [[ARG1:%.*]], i32 [[ARG2:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    br label [[LOOP:%.*]]
; CHECK:       loop:
; CHECK-NEXT:    [[PHI:%.*]] = phi i32 [ [[ADD9:%.*]], [[LOOP_LATCH:%.*]] ], [ 0, [[ENTRY:%.*]] ]
; CHECK-NEXT:    br i1 [[C]], label [[IF:%.*]], label [[LOOP_LATCH]]
; CHECK:       if:
; CHECK-NEXT:    [[UDIV:%.*]] = udiv i32 [[ARG1]], [[ARG2]]
; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[UDIV]], [[PHI]]
; CHECK-NEXT:    [[ZEXT:%.*]] = zext i32 [[ADD]] to i64
; CHECK-NEXT:    br label [[LOOP2:%.*]]
; CHECK:       loop2:
; CHECK-NEXT:    [[PHI6:%.*]] = phi i64 [ [[ADD7:%.*]], [[LOOP2]] ], [ 0, [[IF]] ]
; CHECK-NEXT:    [[ADD7]] = add nuw nsw i64 [[PHI6]], 1
; CHECK-NEXT:    [[ICMP:%.*]] = icmp samesign ult i64 [[PHI6]], [[ZEXT]]
; CHECK-NEXT:    br i1 [[ICMP]], label [[LOOP2]], label [[LOOP_LATCH_LOOPEXIT:%.*]]
; CHECK:       loop.latch.loopexit:
; CHECK-NEXT:    br label [[LOOP_LATCH]]
; CHECK:       loop.latch:
; CHECK-NEXT:    [[ADD9]] = add i32 [[PHI]], 1
; CHECK-NEXT:    br label [[LOOP]]
;
entry:
  br label %loop

loop:
  %phi = phi i32 [ %add9, %loop.latch ], [ 0, %entry ]
  br i1 %c, label %if, label %loop.latch

if:
  %udiv = udiv i32 %arg1, %arg2
  %add = add i32 %udiv, %phi
  %zext = zext i32 %add to i64
  br label %loop2

loop2:
  %phi6 = phi i64 [ %add7, %loop2 ], [ 0, %if ]
  %add7 = add i64 %phi6, 1
  %icmp = icmp slt i64 %phi6, %zext
  br i1 %icmp, label %loop2, label %loop.latch

loop.latch:
  %add9 = add i32 %phi, 1
  br label %loop
}