llvm/test/CodeGen/X86/vmaskmov-offset.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=core-avx2 -stop-after finalize-isel -o - %s | FileCheck %s

declare void @llvm.masked.store.v16f32.p0(<16 x float>, ptr, i32, <16 x i1>)
declare <16 x float> @llvm.masked.load.v16f32.p0(ptr, i32, <16 x i1>, <16 x float>)

define void @test_v16f(<16 x i32> %x) {
  ; CHECK-LABEL: name: test_v16f
  ; CHECK: bb.0.bb:
  ; CHECK-NEXT:   liveins: $ymm0, $ymm1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
  ; CHECK-NEXT:   [[V_SET0_:%[0-9]+]]:vr128 = V_SET0
  ; CHECK-NEXT:   [[SUBREG_TO_REG:%[0-9]+]]:vr256 = SUBREG_TO_REG [[V_SET0_]], %subreg.sub_xmm
  ; CHECK-NEXT:   [[VPCMPEQDYrr:%[0-9]+]]:vr256 = VPCMPEQDYrr [[COPY]], [[SUBREG_TO_REG]]
  ; CHECK-NEXT:   [[VPCMPEQDYrr1:%[0-9]+]]:vr256 = VPCMPEQDYrr [[COPY1]], [[SUBREG_TO_REG]]
  ; CHECK-NEXT:   [[VMASKMOVPSYrm:%[0-9]+]]:vr256 = VMASKMOVPSYrm [[VPCMPEQDYrr1]], %stack.0.stack_input_vec, 1, $noreg, 0, $noreg :: (load unknown-size from %ir.stack_input_vec, align 4)
  ; CHECK-NEXT:   [[VMASKMOVPSYrm1:%[0-9]+]]:vr256 = VMASKMOVPSYrm [[VPCMPEQDYrr]], %stack.0.stack_input_vec, 1, $noreg, 32, $noreg :: (load unknown-size from %ir.stack_input_vec + 32, align 4)
  ; CHECK-NEXT:   VMASKMOVPSYmr %stack.1.stack_output_vec, 1, $noreg, 32, $noreg, [[VPCMPEQDYrr]], [[VMASKMOVPSYrm1]] :: (store unknown-size into %ir.stack_output_vec + 32, align 4)
  ; CHECK-NEXT:   VMASKMOVPSYmr %stack.1.stack_output_vec, 1, $noreg, 0, $noreg, [[VPCMPEQDYrr1]], [[VMASKMOVPSYrm]] :: (store unknown-size into %ir.stack_output_vec, align 4)
  ; CHECK-NEXT:   RET 0
bb:
  %stack_input_vec = alloca <16 x float>, align 64
  %stack_output_vec = alloca <16 x float>, align 64
  %mask = icmp eq <16 x i32> %x, zeroinitializer
  %masked_loaded_vec = call <16 x float> @llvm.masked.load.v16f32.p0(ptr nonnull %stack_input_vec, i32 4, <16 x i1> %mask, <16 x float> undef)
  call void @llvm.masked.store.v16f32.p0(<16 x float> %masked_loaded_vec, ptr nonnull %stack_output_vec, i32 4, <16 x i1> %mask)
  ret void
}

declare void @llvm.masked.store.v8f64.p0(<8 x double>, ptr, i32, <8 x i1>)
declare <8 x double> @llvm.masked.load.v8f64.p0(ptr, i32, <8 x i1>, <8 x double>)

define void @test_v8d(<8 x i64> %x) {
  ; CHECK-LABEL: name: test_v8d
  ; CHECK: bb.0.bb:
  ; CHECK-NEXT:   liveins: $ymm0, $ymm1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
  ; CHECK-NEXT:   [[V_SET0_:%[0-9]+]]:vr128 = V_SET0
  ; CHECK-NEXT:   [[SUBREG_TO_REG:%[0-9]+]]:vr256 = SUBREG_TO_REG [[V_SET0_]], %subreg.sub_xmm
  ; CHECK-NEXT:   [[VPCMPEQQYrr:%[0-9]+]]:vr256 = VPCMPEQQYrr [[COPY]], [[SUBREG_TO_REG]]
  ; CHECK-NEXT:   [[VPCMPEQQYrr1:%[0-9]+]]:vr256 = VPCMPEQQYrr [[COPY1]], [[SUBREG_TO_REG]]
  ; CHECK-NEXT:   [[VMASKMOVPDYrm:%[0-9]+]]:vr256 = VMASKMOVPDYrm [[VPCMPEQQYrr1]], %stack.0.stack_input_vec, 1, $noreg, 0, $noreg :: (load unknown-size from %ir.stack_input_vec, align 4)
  ; CHECK-NEXT:   [[VMASKMOVPDYrm1:%[0-9]+]]:vr256 = VMASKMOVPDYrm [[VPCMPEQQYrr]], %stack.0.stack_input_vec, 1, $noreg, 32, $noreg :: (load unknown-size from %ir.stack_input_vec + 32, align 4)
  ; CHECK-NEXT:   VMASKMOVPDYmr %stack.1.stack_output_vec, 1, $noreg, 32, $noreg, [[VPCMPEQQYrr]], [[VMASKMOVPDYrm1]] :: (store unknown-size into %ir.stack_output_vec + 32, align 4)
  ; CHECK-NEXT:   VMASKMOVPDYmr %stack.1.stack_output_vec, 1, $noreg, 0, $noreg, [[VPCMPEQQYrr1]], [[VMASKMOVPDYrm]] :: (store unknown-size into %ir.stack_output_vec, align 4)
  ; CHECK-NEXT:   RET 0
bb:
  %stack_input_vec = alloca <8 x double>, align 64
  %stack_output_vec = alloca <8 x double>, align 64
  %mask = icmp eq <8 x i64> %x, zeroinitializer
  %masked_loaded_vec = call <8 x double> @llvm.masked.load.v8f64.p0(ptr nonnull %stack_input_vec, i32 4, <8 x i1> %mask, <8 x double> undef)
  call void @llvm.masked.store.v8f64.p0(<8 x double> %masked_loaded_vec, ptr nonnull %stack_output_vec, i32 4, <8 x i1> %mask)
  ret void
}

define <2 x double> @mload_constmask_v2f64(ptr %addr, <2 x double> %dst) {
  ; CHECK-LABEL: name: mload_constmask_v2f64
  ; CHECK: bb.0 (%ir-block.0):
  ; CHECK-NEXT:   liveins: $rdi, $xmm0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
  ; CHECK-NEXT:   [[VMOVHPDrm:%[0-9]+]]:vr128 = VMOVHPDrm [[COPY]], [[COPY1]], 1, $noreg, 8, $noreg :: (load (s64) from %ir.addr + 8, align 4)
  ; CHECK-NEXT:   $xmm0 = COPY [[VMOVHPDrm]]
  ; CHECK-NEXT:   RET 0, $xmm0
  %res = call <2 x double> @llvm.masked.load.v2f64.p0(ptr %addr, i32 4, <2 x i1> <i1 0, i1 1>, <2 x double> %dst)
  ret <2 x double> %res
}

define void @one_mask_bit_set2(ptr %addr, <4 x float> %val) {
  ; CHECK-LABEL: name: one_mask_bit_set2
  ; CHECK: bb.0 (%ir-block.0):
  ; CHECK-NEXT:   liveins: $rdi, $xmm0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
  ; CHECK-NEXT:   VEXTRACTPSmri [[COPY1]], 1, $noreg, 8, $noreg, [[COPY]], 2 :: (store (s32) into %ir.addr + 8)
  ; CHECK-NEXT:   RET 0
  call void @llvm.masked.store.v4f32.p0(<4 x float> %val, ptr %addr, i32 4, <4 x i1><i1 false, i1 false, i1 true, i1 false>)
  ret void
}

declare <2 x double> @llvm.masked.load.v2f64.p0(ptr, i32, <2 x i1>, <2 x double>)
declare void @llvm.masked.store.v4f32.p0(<4 x float>, ptr, i32, <4 x i1>)