llvm/test/CodeGen/X86/vec_insert-7.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=+mmx,+sse4.2 | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=+mmx,+sse4.2 | FileCheck %s --check-prefix=X64

; MMX insertelement is not available; these are promoted to xmm.
; (Without SSE they are split to two ints, and the code is much better.)

define <1 x i64> @mmx_movzl(<1 x i64> %x) nounwind {
; X86-LABEL: mmx_movzl:
; X86:       ## %bb.0:
; X86-NEXT:    movl $32, %eax
; X86-NEXT:    xorl %edx, %edx
; X86-NEXT:    retl
;
; X64-LABEL: mmx_movzl:
; X64:       ## %bb.0:
; X64-NEXT:    movl $32, %eax
; X64-NEXT:    retq
  %tmp = bitcast <1 x i64> %x to <2 x i32>
  %tmp3 = insertelement <2 x i32> %tmp, i32 32, i32 0
  %tmp8 = insertelement <2 x i32> %tmp3, i32 0, i32 1
  %tmp9 = bitcast <2 x i32> %tmp8 to <1 x i64>
  ret <1 x i64> %tmp9
}