llvm/test/CodeGen/X86/memset.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mcpu=pentium2 -mtriple=i686-apple-darwin8.8.0 | FileCheck %s --check-prefixes=X86
; RUN: llc < %s -mcpu=pentium3 -mtriple=i686-apple-darwin8.8.0 | FileCheck %s --check-prefixes=SSE
; RUN: llc < %s -mcpu=bdver1   -mtriple=i686-apple-darwin8.8.0 | FileCheck %s --check-prefixes=AVX,AVX1
; RUN: llc < %s -mcpu=haswell  -mtriple=i686-apple-darwin8.8.0 | FileCheck %s --check-prefixes=AVX,AVX2

%struct.x = type { i16, i16 }

define void @t() nounwind  {
; X86-LABEL: t:
; X86:       ## %bb.0: ## %entry
; X86-NEXT:    subl $44, %esp
; X86-NEXT:    movl $0, {{[0-9]+}}(%esp)
; X86-NEXT:    movl $0, {{[0-9]+}}(%esp)
; X86-NEXT:    movl $0, {{[0-9]+}}(%esp)
; X86-NEXT:    movl $0, {{[0-9]+}}(%esp)
; X86-NEXT:    movl $0, {{[0-9]+}}(%esp)
; X86-NEXT:    movl $0, {{[0-9]+}}(%esp)
; X86-NEXT:    movl $0, {{[0-9]+}}(%esp)
; X86-NEXT:    movl $0, {{[0-9]+}}(%esp)
; X86-NEXT:    leal {{[0-9]+}}(%esp), %eax
; X86-NEXT:    movl %eax, (%esp)
; X86-NEXT:    calll _foo
; X86-NEXT:    addl $44, %esp
; X86-NEXT:    retl
;
; SSE-LABEL: t:
; SSE:       ## %bb.0: ## %entry
; SSE-NEXT:    subl $60, %esp
; SSE-NEXT:    xorps %xmm0, %xmm0
; SSE-NEXT:    movaps %xmm0, {{[0-9]+}}(%esp)
; SSE-NEXT:    movaps %xmm0, {{[0-9]+}}(%esp)
; SSE-NEXT:    leal {{[0-9]+}}(%esp), %eax
; SSE-NEXT:    movl %eax, (%esp)
; SSE-NEXT:    calll _foo
; SSE-NEXT:    addl $60, %esp
; SSE-NEXT:    retl
;
; AVX1-LABEL: t:
; AVX1:       ## %bb.0: ## %entry
; AVX1-NEXT:    subl $60, %esp
; AVX1-NEXT:    leal {{[0-9]+}}(%esp), %eax
; AVX1-NEXT:    vxorps %xmm0, %xmm0, %xmm0
; AVX1-NEXT:    vmovups %ymm0, {{[0-9]+}}(%esp)
; AVX1-NEXT:    movl %eax, (%esp)
; AVX1-NEXT:    vzeroupper
; AVX1-NEXT:    calll _foo
; AVX1-NEXT:    addl $60, %esp
; AVX1-NEXT:    retl
;
; AVX2-LABEL: t:
; AVX2:       ## %bb.0: ## %entry
; AVX2-NEXT:    subl $60, %esp
; AVX2-NEXT:    vxorps %xmm0, %xmm0, %xmm0
; AVX2-NEXT:    vmovups %ymm0, {{[0-9]+}}(%esp)
; AVX2-NEXT:    leal {{[0-9]+}}(%esp), %eax
; AVX2-NEXT:    movl %eax, (%esp)
; AVX2-NEXT:    vzeroupper
; AVX2-NEXT:    calll _foo
; AVX2-NEXT:    addl $60, %esp
; AVX2-NEXT:    retl
entry:
	%up_mvd = alloca [8 x %struct.x]		; <ptr> [#uses=2]
	%up_mvd116 = getelementptr [8 x %struct.x], ptr %up_mvd, i32 0, i32 0		; <ptr> [#uses=1]

	call void @llvm.memset.p0.i64(ptr align 8 %up_mvd, i8 0, i64 32, i1 false)
	call void @foo( ptr %up_mvd116 ) nounwind
	ret void
}

declare void @foo(ptr)

declare void @llvm.memset.p0.i64(ptr nocapture, i8, i64, i1) nounwind

; Ensure that alignment of '0' in an @llvm.memset intrinsic results in
; unaligned loads and stores.
define void @PR15348(ptr %a) {
; X86-LABEL: PR15348:
; X86:       ## %bb.0:
; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
; X86-NEXT:    movb $0, 16(%eax)
; X86-NEXT:    movl $0, 12(%eax)
; X86-NEXT:    movl $0, 8(%eax)
; X86-NEXT:    movl $0, 4(%eax)
; X86-NEXT:    movl $0, (%eax)
; X86-NEXT:    retl
;
; SSE-LABEL: PR15348:
; SSE:       ## %bb.0:
; SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
; SSE-NEXT:    movb $0, 16(%eax)
; SSE-NEXT:    movl $0, 12(%eax)
; SSE-NEXT:    movl $0, 8(%eax)
; SSE-NEXT:    movl $0, 4(%eax)
; SSE-NEXT:    movl $0, (%eax)
; SSE-NEXT:    retl
;
; AVX-LABEL: PR15348:
; AVX:       ## %bb.0:
; AVX-NEXT:    movl {{[0-9]+}}(%esp), %eax
; AVX-NEXT:    vxorps %xmm0, %xmm0, %xmm0
; AVX-NEXT:    vmovups %xmm0, (%eax)
; AVX-NEXT:    movb $0, 16(%eax)
; AVX-NEXT:    retl
  call void @llvm.memset.p0.i64(ptr %a, i8 0, i64 17, i1 false)
  ret void
}

declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1 immarg)

define void @PR83077(ptr %a) {
; X86-LABEL: PR83077:
; X86:       ## %bb.0:
; X86-NEXT:    pushl %edi
; X86-NEXT:    .cfi_def_cfa_offset 8
; X86-NEXT:    .cfi_offset %edi, -8
; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
; X86-NEXT:    movl $-1, %eax
; X86-NEXT:    movl $22, %ecx
; X86-NEXT:    movl %edx, %edi
; X86-NEXT:    rep;stosl %eax, %es:(%edi)
; X86-NEXT:    movw $-1, 88(%edx)
; X86-NEXT:    popl %edi
; X86-NEXT:    retl
;
; SSE-LABEL: PR83077:
; SSE:       ## %bb.0:
; SSE-NEXT:    pushl %edi
; SSE-NEXT:    .cfi_def_cfa_offset 8
; SSE-NEXT:    .cfi_offset %edi, -8
; SSE-NEXT:    movl {{[0-9]+}}(%esp), %edx
; SSE-NEXT:    movl $-1, %eax
; SSE-NEXT:    movl $22, %ecx
; SSE-NEXT:    movl %edx, %edi
; SSE-NEXT:    rep;stosl %eax, %es:(%edi)
; SSE-NEXT:    movw $-1, 88(%edx)
; SSE-NEXT:    popl %edi
; SSE-NEXT:    retl
;
; AVX1-LABEL: PR83077:
; AVX1:       ## %bb.0:
; AVX1-NEXT:    movl {{[0-9]+}}(%esp), %eax
; AVX1-NEXT:    vxorps %xmm0, %xmm0, %xmm0
; AVX1-NEXT:    vcmptrueps %ymm0, %ymm0, %ymm0
; AVX1-NEXT:    vmovups %ymm0, 58(%eax)
; AVX1-NEXT:    vmovups %ymm0, 32(%eax)
; AVX1-NEXT:    vmovups %ymm0, (%eax)
; AVX1-NEXT:    vzeroupper
; AVX1-NEXT:    retl
;
; AVX2-LABEL: PR83077:
; AVX2:       ## %bb.0:
; AVX2-NEXT:    movl {{[0-9]+}}(%esp), %eax
; AVX2-NEXT:    vpcmpeqd %ymm0, %ymm0, %ymm0
; AVX2-NEXT:    vmovdqu %ymm0, 58(%eax)
; AVX2-NEXT:    vmovdqu %ymm0, 32(%eax)
; AVX2-NEXT:    vmovdqu %ymm0, (%eax)
; AVX2-NEXT:    vzeroupper
; AVX2-NEXT:    retl
  call void @llvm.memset.p0.i32(ptr noundef nonnull align 4 dereferenceable(90) %a, i8 -1, i32 90, i1 false)
  ret void
}