llvm/test/CodeGen/SystemZ/copy-physreg-vr16.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z16 -regalloc=fast -verify-machineinstrs \
; RUN:   | FileCheck %s

; Test COPY to $f0 from $f24.
define half @fun0(<4 x half> %0) {
; CHECK-LABEL: fun0:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vlr %v0, %v24
; CHECK-NEXT:    br %r14
entry:
  %Res = extractelement <4 x half> %0, i32 0
  ret half %Res
}

; Test COPY from $f0 to $f24.
define <4 x half>  @fun1(half %0) {
; CHECK-LABEL: fun1:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    stmg %r14, %r15, 112(%r15)
; CHECK-NEXT:    .cfi_offset %r14, -48
; CHECK-NEXT:    .cfi_offset %r15, -40
; CHECK-NEXT:    aghi %r15, -160
; CHECK-NEXT:    .cfi_def_cfa_offset 320
; CHECK-NEXT:    brasl %r14, __extendhfsf2@PLT
; CHECK-NEXT:    aebr %f0, %f0
; CHECK-NEXT:    brasl %r14, __truncsfhf2@PLT
; CHECK-NEXT:    # implicit-def: $v24
; CHECK-NEXT:    vlr %v24, %v0
; CHECK-NEXT:    lmg %r14, %r15, 272(%r15)
; CHECK-NEXT:    br %r14
entry:
  %Add = fadd half %0, %0
  %Res = insertelement <4 x half> poison, half %Add, i32 0
  ret <4 x half> %Res
}