llvm/test/CodeGen/SPARC/vector-extract-elt.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=sparc < %s | FileCheck %s


; If computeKnownSignBits (in SelectionDAG) can do a simple
; look-thru for extractelement then we know that the add will yield a
; non-negative result.
define i1 @test1(ptr %in) nounwind {
; CHECK-LABEL: test1:
; CHECK:       ! %bb.0:
; CHECK-NEXT:    retl
; CHECK-NEXT:    mov %g0, %o0
  %vec2 = load <4 x i16>, ptr %in, align 1
  %vec3 = lshr <4 x i16> %vec2, <i16 2, i16 2, i16 2, i16 2>
  %vec4 = sext <4 x i16> %vec3 to <4 x i32>
  %elt0 = extractelement <4 x i32> %vec4, i32 0
  %elt1 = extractelement <4 x i32> %vec4, i32 1
  %sum = add i32 %elt0, %elt1
  %bool = icmp slt i32 %sum, 0
  ret i1 %bool
}

; v2i32 is legal on 32-bit SPARC to represent 64-bit integer register pairs.
; Make sure a dynamic extract does not reach instruction selection, which
; only handles constant indices.
define i32 @extract_v2i32(<2 x i32> %v, i32 %idx) nounwind {
; CHECK-LABEL: extract_v2i32:
; CHECK:       ! %bb.0:
; CHECK-NEXT:    cmp %o2, 0
; CHECK-NEXT:    be .LBB1_2
; CHECK-NEXT:    nop
; CHECK-NEXT:  ! %bb.1:
; CHECK-NEXT:    mov %o1, %o0
; CHECK-NEXT:  .LBB1_2:
; CHECK-NEXT:    retl
; CHECK-NEXT:    nop
  %elt = extractelement <2 x i32> %v, i32 %idx
  ret i32 %elt
}