llvm/test/CodeGen/SPARC/fshl.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=sparcv9 | FileCheck %s

define <2 x i64> @fshl_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %z) {
; CHECK-LABEL: fshl_v2i64:
; CHECK:         .cfi_startproc
; CHECK-NEXT:    .register %g2, #scratch
; CHECK-NEXT:    .register %g3, #scratch
; CHECK-NEXT:  ! %bb.0: ! %bb
; CHECK-NEXT:    mov 63, %g2
; CHECK-NEXT:    andn %g2, %o4, %g3
; CHECK-NEXT:    srlx %o2, 1, %o2
; CHECK-NEXT:    srlx %o2, %g3, %o2
; CHECK-NEXT:    and %o4, 63, %o4
; CHECK-NEXT:    sllx %o0, %o4, %o0
; CHECK-NEXT:    or %o0, %o2, %o0
; CHECK-NEXT:    andn %g2, %o5, %o2
; CHECK-NEXT:    srlx %o3, 1, %o3
; CHECK-NEXT:    srlx %o3, %o2, %o2
; CHECK-NEXT:    and %o5, 63, %o3
; CHECK-NEXT:    sllx %o1, %o3, %o1
; CHECK-NEXT:    retl
; CHECK-NEXT:    or %o1, %o2, %o1
bb:
  %i = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %z)
  ret <2 x i64> %i
}

define i32 @PR47303() {
; CHECK-LABEL: PR47303:
; CHECK:         .cfi_startproc
; CHECK-NEXT:  ! %bb.0: ! %bb
; CHECK-NEXT:    retl
; CHECK-NEXT:    mov %g0, %o0
bb:
  %i = call <4 x i64> @llvm.fshl.v4i64(<4 x i64> undef, <4 x i64> undef, <4 x i64> <i64 57, i64 27, i64 12, i64 33>)
  %i1 = add <4 x i64> %i, zeroinitializer
  %i2 = add <4 x i64> %i1, zeroinitializer
  %i3 = extractelement <4 x i64> %i2, i32 0
  %i4 = add i64 0, %i3
  %i5 = xor i64 0, %i4
  %i6 = trunc i64 %i5 to i32
  %i7 = mul i32 %i6, 797982799
  ret i32 %i7
}

declare <2 x i64> @llvm.fshl.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)
declare <4 x i64> @llvm.fshl.v4i64(<4 x i64>, <4 x i64>, <4 x i64>)