llvm/test/CodeGen/SPARC/64cond.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=sparc64-pc-openbsd -disable-sparc-leaf-proc | FileCheck %s
; Testing 64-bit conditionals. The sparc64 triple is an alias for sparcv9.

define void @cmpri(ptr %p, i64 %x) nounwind {
; CHECK-LABEL: cmpri:
; CHECK:       ! %bb.0: ! %entry
; CHECK-NEXT:    save %sp, -128, %sp
; CHECK-NEXT:    cmp %i1, 1
; CHECK-NEXT:    be %xcc, .LBB0_2
; CHECK-NEXT:    nop
; CHECK-NEXT:  ! %bb.1: ! %if.then
; CHECK-NEXT:    stx %i1, [%i0]
; CHECK-NEXT:  .LBB0_2: ! %if.end
; CHECK-NEXT:    ret
; CHECK-NEXT:    restore
entry:
  %tobool = icmp eq i64 %x, 1
  br i1 %tobool, label %if.end, label %if.then

if.then:
  store i64 %x, ptr %p, align 8
  br label %if.end

if.end:
  ret void
}

define void @cmprr(ptr %p, i64 %x, i64 %y) nounwind {
; CHECK-LABEL: cmprr:
; CHECK:       ! %bb.0: ! %entry
; CHECK-NEXT:    save %sp, -128, %sp
; CHECK-NEXT:    cmp %i1, %i2
; CHECK-NEXT:    bgu %xcc, .LBB1_2
; CHECK-NEXT:    nop
; CHECK-NEXT:  ! %bb.1: ! %if.then
; CHECK-NEXT:    stx %i1, [%i0]
; CHECK-NEXT:  .LBB1_2: ! %if.end
; CHECK-NEXT:    ret
; CHECK-NEXT:    restore
entry:
  %tobool = icmp ugt i64 %x, %y
  br i1 %tobool, label %if.end, label %if.then

if.then:
  store i64 %x, ptr %p, align 8
  br label %if.end

if.end:
  ret void
}

define i32 @selecti32_xcc(i64 %x, i64 %y, i32 %a, i32 %b) nounwind {
; CHECK-LABEL: selecti32_xcc:
; CHECK:       ! %bb.0: ! %entry
; CHECK-NEXT:    save %sp, -128, %sp
; CHECK-NEXT:    cmp %i0, %i1
; CHECK-NEXT:    movg %xcc, %i2, %i3
; CHECK-NEXT:    ret
; CHECK-NEXT:    restore %g0, %i3, %o0
entry:
  %tobool = icmp sgt i64 %x, %y
  %rv = select i1 %tobool, i32 %a, i32 %b
  ret i32 %rv
}

define i64 @selecti64_xcc(i64 %x, i64 %y, i64 %a, i64 %b) nounwind {
; CHECK-LABEL: selecti64_xcc:
; CHECK:       ! %bb.0: ! %entry
; CHECK-NEXT:    save %sp, -128, %sp
; CHECK-NEXT:    cmp %i0, %i1
; CHECK-NEXT:    movg %xcc, %i2, %i3
; CHECK-NEXT:    ret
; CHECK-NEXT:    restore %g0, %i3, %o0
entry:
  %tobool = icmp sgt i64 %x, %y
  %rv = select i1 %tobool, i64 %a, i64 %b
  ret i64 %rv
}

define i64 @selecti64_icc(i32 %x, i32 %y, i64 %a, i64 %b) nounwind {
; CHECK-LABEL: selecti64_icc:
; CHECK:       ! %bb.0: ! %entry
; CHECK-NEXT:    save %sp, -128, %sp
; CHECK-NEXT:    cmp %i0, %i1
; CHECK-NEXT:    movg %icc, %i2, %i3
; CHECK-NEXT:    ret
; CHECK-NEXT:    restore %g0, %i3, %o0
entry:
  %tobool = icmp sgt i32 %x, %y
  %rv = select i1 %tobool, i64 %a, i64 %b
  ret i64 %rv
}

define i64 @selecti64_fcc(float %x, float %y, i64 %a, i64 %b) nounwind {
; CHECK-LABEL: selecti64_fcc:
; CHECK:       ! %bb.0: ! %entry
; CHECK-NEXT:    save %sp, -128, %sp
; CHECK-NEXT:    mov %i3, %i0
; CHECK-NEXT:    fcmps %fcc0, %f1, %f3
; CHECK-NEXT:    movul %fcc0, %i2, %i0
; CHECK-NEXT:    ret
; CHECK-NEXT:    restore
entry:
  %tobool = fcmp ult float %x, %y
  %rv = select i1 %tobool, i64 %a, i64 %b
  ret i64 %rv
}

define float @selectf32_xcc(i64 %x, i64 %y, float %a, float %b) nounwind {
; CHECK-LABEL: selectf32_xcc:
; CHECK:       ! %bb.0: ! %entry
; CHECK-NEXT:    save %sp, -128, %sp
; CHECK-NEXT:    fmovs %f7, %f0
; CHECK-NEXT:    cmp %i0, %i1
; CHECK-NEXT:    fmovsg %xcc, %f5, %f0
; CHECK-NEXT:    ret
; CHECK-NEXT:    restore
entry:
  %tobool = icmp sgt i64 %x, %y
  %rv = select i1 %tobool, float %a, float %b
  ret float %rv
}

define double @selectf64_xcc(i64 %x, i64 %y, double %a, double %b) nounwind {
; CHECK-LABEL: selectf64_xcc:
; CHECK:       ! %bb.0: ! %entry
; CHECK-NEXT:    save %sp, -128, %sp
; CHECK-NEXT:    fmovd %f6, %f0
; CHECK-NEXT:    cmp %i0, %i1
; CHECK-NEXT:    fmovdg %xcc, %f4, %f0
; CHECK-NEXT:    ret
; CHECK-NEXT:    restore
entry:
  %tobool = icmp sgt i64 %x, %y
  %rv = select i1 %tobool, double %a, double %b
  ret double %rv
}

; The MOVXCC instruction can't use %g0 for its tied operand.
define i64 @select_consti64_xcc(i64 %x, i64 %y) nounwind {
; CHECK-LABEL: select_consti64_xcc:
; CHECK:       ! %bb.0: ! %entry
; CHECK-NEXT:    save %sp, -128, %sp
; CHECK-NEXT:    mov %g0, %i2
; CHECK-NEXT:    cmp %i0, %i1
; CHECK-NEXT:    movg %xcc, 123, %i2
; CHECK-NEXT:    ret
; CHECK-NEXT:    restore %g0, %i2, %o0
entry:
  %tobool = icmp sgt i64 %x, %y
  %rv = select i1 %tobool, i64 123, i64 0
  ret i64 %rv
}

define i1 @setcc_resultty(i64 %a, i1 %b) nounwind {
; CHECK-LABEL: setcc_resultty:
; CHECK:       ! %bb.0:
; CHECK-NEXT:    save %sp, -128, %sp
; CHECK-NEXT:    mov %g0, %i2
; CHECK-NEXT:    sethi 4194303, %i3
; CHECK-NEXT:    or %i3, 1023, %i3
; CHECK-NEXT:    sethi 131071, %i4
; CHECK-NEXT:    or %i4, 1023, %i4
; CHECK-NEXT:    sllx %i4, 32, %i4
; CHECK-NEXT:    or %i4, %i3, %i3
; CHECK-NEXT:    and %i0, %i3, %i3
; CHECK-NEXT:    cmp %i3, %i0
; CHECK-NEXT:    movne %xcc, 1, %i2
; CHECK-NEXT:    or %i2, %i1, %i0
; CHECK-NEXT:    ret
; CHECK-NEXT:    restore
  %a0 = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 32)
  %a1 = extractvalue { i64, i1 } %a0, 1
  %a4 = or i1 %a1, %b
  ret i1 %a4
}

declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64)