llvm/test/CodeGen/RISCV/xcvmac.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+m -mattr=+xcvmac -verify-machineinstrs < %s \
; RUN:   | FileCheck %s

define i32 @test.mac(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: test.mac:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cv.mac a2, a0, a1
; CHECK-NEXT:    mv a0, a2
; CHECK-NEXT:    ret
  %1 = call i32 @llvm.riscv.cv.mac.mac(i32 %a, i32 %b, i32 %c)
  ret i32 %1
}

define i32 @test.msu(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: test.msu:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cv.msu a2, a0, a1
; CHECK-NEXT:    mv a0, a2
; CHECK-NEXT:    ret
  %1 = call i32 @llvm.riscv.cv.mac.msu(i32 %a, i32 %b, i32 %c)
  ret i32 %1
}

define i32 @test.muluN(i32 %a, i32 %b) {
; CHECK-LABEL: test.muluN:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cv.mulun a0, a0, a1, 5
; CHECK-NEXT:    ret
  %1 = call i32 @llvm.riscv.cv.mac.muluN(i32 %a, i32 %b, i32 5)
  ret i32 %1
}

define i32 @test.mulhhuN(i32 %a, i32 %b) {
; CHECK-LABEL: test.mulhhuN:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cv.mulhhun a0, a0, a1, 5
; CHECK-NEXT:    ret
  %1 = call i32 @llvm.riscv.cv.mac.mulhhuN(i32 %a, i32 %b, i32 5)
  ret i32 %1
}

define i32 @test.mulsN(i32 %a, i32 %b) {
; CHECK-LABEL: test.mulsN:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cv.mulsn a0, a0, a1, 5
; CHECK-NEXT:    ret
  %1 = call i32 @llvm.riscv.cv.mac.mulsN(i32 %a, i32 %b, i32 5)
  ret i32 %1
}

define i32 @test.mulhhsN(i32 %a, i32 %b) {
; CHECK-LABEL: test.mulhhsN:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cv.mulhhsn a0, a0, a1, 5
; CHECK-NEXT:    ret
  %1 = call i32 @llvm.riscv.cv.mac.mulhhsN(i32 %a, i32 %b, i32 5)
  ret i32 %1
}

define i32 @test.muluRN(i32 %a, i32 %b) {
; CHECK-LABEL: test.muluRN:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cv.mulurn a0, a0, a1, 5
; CHECK-NEXT:    ret
  %1 = call i32 @llvm.riscv.cv.mac.muluRN(i32 %a, i32 %b, i32 5)
  ret i32 %1
}

define i32 @test.mulhhuRN(i32 %a, i32 %b) {
; CHECK-LABEL: test.mulhhuRN:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cv.mulhhurn a0, a0, a1, 5
; CHECK-NEXT:    ret
  %1 = call i32 @llvm.riscv.cv.mac.mulhhuRN(i32 %a, i32 %b, i32 5)
  ret i32 %1
}

define i32 @test.mulsRN(i32 %a, i32 %b) {
; CHECK-LABEL: test.mulsRN:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cv.mulsrn a0, a0, a1, 5
; CHECK-NEXT:    ret
  %1 = call i32 @llvm.riscv.cv.mac.mulsRN(i32 %a, i32 %b, i32 5)
  ret i32 %1
}

define i32 @test.mulhhsRN(i32 %a, i32 %b) {
; CHECK-LABEL: test.mulhhsRN:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cv.mulhhsrn a0, a0, a1, 5
; CHECK-NEXT:    ret
  %1 = call i32 @llvm.riscv.cv.mac.mulhhsRN(i32 %a, i32 %b, i32 5)
  ret i32 %1
}

define i32 @test.macuN(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: test.macuN:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cv.macun a2, a0, a1, 5
; CHECK-NEXT:    mv a0, a2
; CHECK-NEXT:    ret
  %1 = call i32 @llvm.riscv.cv.mac.macuN(i32 %a, i32 %b, i32 %c, i32 5)
  ret i32 %1
}

define i32 @test.machhuN(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: test.machhuN:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cv.machhun a2, a0, a1, 5
; CHECK-NEXT:    mv a0, a2
; CHECK-NEXT:    ret
  %1 = call i32 @llvm.riscv.cv.mac.machhuN(i32 %a, i32 %b, i32 %c, i32 5)
  ret i32 %1
}

define i32 @test.macsN(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: test.macsN:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cv.macsn a2, a0, a1, 5
; CHECK-NEXT:    mv a0, a2
; CHECK-NEXT:    ret
  %1 = call i32 @llvm.riscv.cv.mac.macsN(i32 %a, i32 %b, i32 %c, i32 5)
  ret i32 %1
}

define i32 @test.machhsN(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: test.machhsN:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cv.machhsn a2, a0, a1, 5
; CHECK-NEXT:    mv a0, a2
; CHECK-NEXT:    ret
  %1 = call i32 @llvm.riscv.cv.mac.machhsN(i32 %a, i32 %b, i32 %c, i32 5)
  ret i32 %1
}

define i32 @test.macuRN(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: test.macuRN:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cv.macurn a2, a0, a1, 5
; CHECK-NEXT:    mv a0, a2
; CHECK-NEXT:    ret
  %1 = call i32 @llvm.riscv.cv.mac.macuRN(i32 %a, i32 %b, i32 %c, i32 5)
  ret i32 %1
}

define i32 @test.machhuRN(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: test.machhuRN:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cv.machhurn a2, a0, a1, 5
; CHECK-NEXT:    mv a0, a2
; CHECK-NEXT:    ret
  %1 = call i32 @llvm.riscv.cv.mac.machhuRN(i32 %a, i32 %b, i32 %c, i32 5)
  ret i32 %1
}

define i32 @test.macsRN(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: test.macsRN:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cv.macsrn a2, a0, a1, 5
; CHECK-NEXT:    mv a0, a2
; CHECK-NEXT:    ret
  %1 = call i32 @llvm.riscv.cv.mac.macsRN(i32 %a, i32 %b, i32 %c, i32 5)
  ret i32 %1
}

define i32 @test.machhsRN(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: test.machhsRN:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cv.machhsrn a2, a0, a1, 5
; CHECK-NEXT:    mv a0, a2
; CHECK-NEXT:    ret
  %1 = call i32 @llvm.riscv.cv.mac.machhsRN(i32 %a, i32 %b, i32 %c, i32 5)
  ret i32 %1
}