llvm/test/CodeGen/RISCV/twoaddr-insert-subreg-subrange.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=riscv64 -mattr=+v -verify-coalescing -run-pass=liveintervals,two-address-instruction,register-coalescer -o - %s | FileCheck %s

# The subrange for the lanes above sub_vrm1_0 straddles sub_vrm4_0, so
# it is only partially redefined when the INSERT_SUBREG becomes a
# subregister COPY. The upper half of $v8m8 must survive.

---
name:            insert_subreg_straddling_subrange
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $v8m8, $v16m4

    ; CHECK-LABEL: name: insert_subreg_straddling_subrange
    ; CHECK: liveins: $v8m8, $v16m4
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8
    ; CHECK-NEXT: [[COPY:%[0-9]+]].sub_vrm4_0:vrm8 = COPY $v16m4
    ; CHECK-NEXT: $v8m8 = COPY [[COPY]]
    ; CHECK-NEXT: PseudoRET implicit $v8m8
    %0:vrm8 = COPY $v8m8
    %1:vrm4 = COPY $v16m4
    %2:vrm8 = INSERT_SUBREG %0, %1, %subreg.sub_vrm4_0
    %3:vr = COPY %2.sub_vrm1_0
    %4:vrm8 = INSERT_SUBREG %2, %3, %subreg.sub_vrm1_0
    $v8m8 = COPY %4
    PseudoRET implicit $v8m8
...