llvm/test/CodeGen/RISCV/rv32e.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=riscv32 -mattr=+e -verify-machineinstrs < %s \
; RUN:   | FileCheck %s

; TODO: Add more tests.

define i32 @exhausted(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g) {
; CHECK-LABEL: exhausted:
; CHECK:       # %bb.0:
; CHECK-NEXT:    lw t0, 0(sp)
; CHECK-NEXT:    add a0, a0, a1
; CHECK-NEXT:    add a2, a3, a2
; CHECK-NEXT:    add a0, a2, a0
; CHECK-NEXT:    add a4, a5, a4
; CHECK-NEXT:    add a0, a4, a0
; CHECK-NEXT:    add a0, t0, a0
; CHECK-NEXT:    ret
  %1 = add i32 %a, %b
  %2 = add i32 %c, %1
  %3 = add i32 %d, %2
  %4 = add i32 %e, %3
  %5 = add i32 %f, %4
  %6 = add i32 %g, %5
  ret i32 %6
}