llvm/test/CodeGen/RISCV/fp128.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN:   | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN:   | FileCheck -check-prefix=RV64I %s

@x = local_unnamed_addr global fp128 0xL00000000000000007FFF000000000000, align 16
@y = local_unnamed_addr global fp128 0xL00000000000000007FFF000000000000, align 16

; Besides anything else, these tests help verify that libcall ABI lowering
; works correctly

define i32 @test_load_and_cmp() nounwind {
; RV32I-LABEL: test_load_and_cmp:
; RV32I:       # %bb.0:
; RV32I-NEXT:    addi sp, sp, -48
; RV32I-NEXT:    sw ra, 44(sp) # 4-byte Folded Spill
; RV32I-NEXT:    lui a0, %hi(x)
; RV32I-NEXT:    lw a2, %lo(x)(a0)
; RV32I-NEXT:    lw a3, %lo(x+4)(a0)
; RV32I-NEXT:    lw a4, %lo(x+8)(a0)
; RV32I-NEXT:    lw a5, %lo(x+12)(a0)
; RV32I-NEXT:    lui a0, %hi(y)
; RV32I-NEXT:    lw a1, %lo(y)(a0)
; RV32I-NEXT:    lw a6, %lo(y+4)(a0)
; RV32I-NEXT:    lw a7, %lo(y+8)(a0)
; RV32I-NEXT:    lw a0, %lo(y+12)(a0)
; RV32I-NEXT:    sw a1, 8(sp)
; RV32I-NEXT:    sw a6, 12(sp)
; RV32I-NEXT:    sw a7, 16(sp)
; RV32I-NEXT:    sw a0, 20(sp)
; RV32I-NEXT:    addi a0, sp, 24
; RV32I-NEXT:    addi a1, sp, 8
; RV32I-NEXT:    sw a2, 24(sp)
; RV32I-NEXT:    sw a3, 28(sp)
; RV32I-NEXT:    sw a4, 32(sp)
; RV32I-NEXT:    sw a5, 36(sp)
; RV32I-NEXT:    call __netf2
; RV32I-NEXT:    snez a0, a0
; RV32I-NEXT:    lw ra, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT:    addi sp, sp, 48
; RV32I-NEXT:    ret
;
; RV64I-LABEL: test_load_and_cmp:
; RV64I:       # %bb.0:
; RV64I-NEXT:    addi sp, sp, -16
; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT:    lui a1, %hi(x)
; RV64I-NEXT:    lui a3, %hi(y)
; RV64I-NEXT:    ld a0, %lo(x)(a1)
; RV64I-NEXT:    ld a1, %lo(x+8)(a1)
; RV64I-NEXT:    ld a2, %lo(y)(a3)
; RV64I-NEXT:    ld a3, %lo(y+8)(a3)
; RV64I-NEXT:    call __netf2
; RV64I-NEXT:    snez a0, a0
; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT:    addi sp, sp, 16
; RV64I-NEXT:    ret
  %1 = load fp128, ptr @x, align 16
  %2 = load fp128, ptr @y, align 16
  %cmp = fcmp une fp128 %1, %2
  %3 = zext i1 %cmp to i32
  ret i32 %3
}

define i32 @test_add_and_fptosi() nounwind {
; RV32I-LABEL: test_add_and_fptosi:
; RV32I:       # %bb.0:
; RV32I-NEXT:    addi sp, sp, -80
; RV32I-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill
; RV32I-NEXT:    lui a0, %hi(x)
; RV32I-NEXT:    lw a3, %lo(x)(a0)
; RV32I-NEXT:    lw a4, %lo(x+4)(a0)
; RV32I-NEXT:    lw a5, %lo(x+8)(a0)
; RV32I-NEXT:    lw a6, %lo(x+12)(a0)
; RV32I-NEXT:    lui a0, %hi(y)
; RV32I-NEXT:    lw a1, %lo(y)(a0)
; RV32I-NEXT:    lw a2, %lo(y+4)(a0)
; RV32I-NEXT:    lw a7, %lo(y+8)(a0)
; RV32I-NEXT:    lw a0, %lo(y+12)(a0)
; RV32I-NEXT:    sw a1, 24(sp)
; RV32I-NEXT:    sw a2, 28(sp)
; RV32I-NEXT:    sw a7, 32(sp)
; RV32I-NEXT:    sw a0, 36(sp)
; RV32I-NEXT:    addi a0, sp, 56
; RV32I-NEXT:    addi a1, sp, 40
; RV32I-NEXT:    addi a2, sp, 24
; RV32I-NEXT:    sw a3, 40(sp)
; RV32I-NEXT:    sw a4, 44(sp)
; RV32I-NEXT:    sw a5, 48(sp)
; RV32I-NEXT:    sw a6, 52(sp)
; RV32I-NEXT:    call __addtf3
; RV32I-NEXT:    lw a1, 56(sp)
; RV32I-NEXT:    lw a2, 60(sp)
; RV32I-NEXT:    lw a3, 64(sp)
; RV32I-NEXT:    lw a4, 68(sp)
; RV32I-NEXT:    addi a0, sp, 8
; RV32I-NEXT:    sw a1, 8(sp)
; RV32I-NEXT:    sw a2, 12(sp)
; RV32I-NEXT:    sw a3, 16(sp)
; RV32I-NEXT:    sw a4, 20(sp)
; RV32I-NEXT:    call __fixtfsi
; RV32I-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload
; RV32I-NEXT:    addi sp, sp, 80
; RV32I-NEXT:    ret
;
; RV64I-LABEL: test_add_and_fptosi:
; RV64I:       # %bb.0:
; RV64I-NEXT:    addi sp, sp, -16
; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT:    lui a1, %hi(x)
; RV64I-NEXT:    lui a3, %hi(y)
; RV64I-NEXT:    ld a0, %lo(x)(a1)
; RV64I-NEXT:    ld a1, %lo(x+8)(a1)
; RV64I-NEXT:    ld a2, %lo(y)(a3)
; RV64I-NEXT:    ld a3, %lo(y+8)(a3)
; RV64I-NEXT:    call __addtf3
; RV64I-NEXT:    call __fixtfsi
; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT:    addi sp, sp, 16
; RV64I-NEXT:    ret
  %1 = load fp128, ptr @x, align 16
  %2 = load fp128, ptr @y, align 16
  %3 = fadd fp128 %1, %2
  %4 = fptosi fp128 %3 to i32
  ret i32 %4
}

define fp128 @fmaximum(fp128 %x, fp128 %y) {
; RV32I-LABEL: fmaximum:
; RV32I:       # %bb.0:
; RV32I-NEXT:    addi sp, sp, -64
; RV32I-NEXT:    .cfi_def_cfa_offset 64
; RV32I-NEXT:    sw ra, 60(sp) # 4-byte Folded Spill
; RV32I-NEXT:    sw s0, 56(sp) # 4-byte Folded Spill
; RV32I-NEXT:    .cfi_offset ra, -4
; RV32I-NEXT:    .cfi_offset s0, -8
; RV32I-NEXT:    lw a3, 0(a1)
; RV32I-NEXT:    lw a4, 4(a1)
; RV32I-NEXT:    lw a5, 8(a1)
; RV32I-NEXT:    lw a6, 12(a1)
; RV32I-NEXT:    lw a1, 0(a2)
; RV32I-NEXT:    lw a7, 4(a2)
; RV32I-NEXT:    lw t0, 8(a2)
; RV32I-NEXT:    lw a2, 12(a2)
; RV32I-NEXT:    mv s0, a0
; RV32I-NEXT:    sw a1, 8(sp)
; RV32I-NEXT:    sw a7, 12(sp)
; RV32I-NEXT:    sw t0, 16(sp)
; RV32I-NEXT:    sw a2, 20(sp)
; RV32I-NEXT:    addi a0, sp, 40
; RV32I-NEXT:    addi a1, sp, 24
; RV32I-NEXT:    addi a2, sp, 8
; RV32I-NEXT:    sw a3, 24(sp)
; RV32I-NEXT:    sw a4, 28(sp)
; RV32I-NEXT:    sw a5, 32(sp)
; RV32I-NEXT:    sw a6, 36(sp)
; RV32I-NEXT:    call fmaximuml
; RV32I-NEXT:    lw a0, 40(sp)
; RV32I-NEXT:    lw a1, 44(sp)
; RV32I-NEXT:    lw a2, 48(sp)
; RV32I-NEXT:    lw a3, 52(sp)
; RV32I-NEXT:    sw a0, 0(s0)
; RV32I-NEXT:    sw a1, 4(s0)
; RV32I-NEXT:    sw a2, 8(s0)
; RV32I-NEXT:    sw a3, 12(s0)
; RV32I-NEXT:    lw ra, 60(sp) # 4-byte Folded Reload
; RV32I-NEXT:    lw s0, 56(sp) # 4-byte Folded Reload
; RV32I-NEXT:    .cfi_restore ra
; RV32I-NEXT:    .cfi_restore s0
; RV32I-NEXT:    addi sp, sp, 64
; RV32I-NEXT:    .cfi_def_cfa_offset 0
; RV32I-NEXT:    ret
;
; RV64I-LABEL: fmaximum:
; RV64I:       # %bb.0:
; RV64I-NEXT:    addi sp, sp, -16
; RV64I-NEXT:    .cfi_def_cfa_offset 16
; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT:    .cfi_offset ra, -8
; RV64I-NEXT:    call fmaximuml
; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT:    .cfi_restore ra
; RV64I-NEXT:    addi sp, sp, 16
; RV64I-NEXT:    .cfi_def_cfa_offset 0
; RV64I-NEXT:    ret
  %a = call fp128 @llvm.maximum.fp128(fp128 %x, fp128 %y)
  ret fp128 %a
}

define fp128 @fminimum(fp128 %x, fp128 %y) {
; RV32I-LABEL: fminimum:
; RV32I:       # %bb.0:
; RV32I-NEXT:    addi sp, sp, -64
; RV32I-NEXT:    .cfi_def_cfa_offset 64
; RV32I-NEXT:    sw ra, 60(sp) # 4-byte Folded Spill
; RV32I-NEXT:    sw s0, 56(sp) # 4-byte Folded Spill
; RV32I-NEXT:    .cfi_offset ra, -4
; RV32I-NEXT:    .cfi_offset s0, -8
; RV32I-NEXT:    lw a3, 0(a1)
; RV32I-NEXT:    lw a4, 4(a1)
; RV32I-NEXT:    lw a5, 8(a1)
; RV32I-NEXT:    lw a6, 12(a1)
; RV32I-NEXT:    lw a1, 0(a2)
; RV32I-NEXT:    lw a7, 4(a2)
; RV32I-NEXT:    lw t0, 8(a2)
; RV32I-NEXT:    lw a2, 12(a2)
; RV32I-NEXT:    mv s0, a0
; RV32I-NEXT:    sw a1, 8(sp)
; RV32I-NEXT:    sw a7, 12(sp)
; RV32I-NEXT:    sw t0, 16(sp)
; RV32I-NEXT:    sw a2, 20(sp)
; RV32I-NEXT:    addi a0, sp, 40
; RV32I-NEXT:    addi a1, sp, 24
; RV32I-NEXT:    addi a2, sp, 8
; RV32I-NEXT:    sw a3, 24(sp)
; RV32I-NEXT:    sw a4, 28(sp)
; RV32I-NEXT:    sw a5, 32(sp)
; RV32I-NEXT:    sw a6, 36(sp)
; RV32I-NEXT:    call fminimuml
; RV32I-NEXT:    lw a0, 40(sp)
; RV32I-NEXT:    lw a1, 44(sp)
; RV32I-NEXT:    lw a2, 48(sp)
; RV32I-NEXT:    lw a3, 52(sp)
; RV32I-NEXT:    sw a0, 0(s0)
; RV32I-NEXT:    sw a1, 4(s0)
; RV32I-NEXT:    sw a2, 8(s0)
; RV32I-NEXT:    sw a3, 12(s0)
; RV32I-NEXT:    lw ra, 60(sp) # 4-byte Folded Reload
; RV32I-NEXT:    lw s0, 56(sp) # 4-byte Folded Reload
; RV32I-NEXT:    .cfi_restore ra
; RV32I-NEXT:    .cfi_restore s0
; RV32I-NEXT:    addi sp, sp, 64
; RV32I-NEXT:    .cfi_def_cfa_offset 0
; RV32I-NEXT:    ret
;
; RV64I-LABEL: fminimum:
; RV64I:       # %bb.0:
; RV64I-NEXT:    addi sp, sp, -16
; RV64I-NEXT:    .cfi_def_cfa_offset 16
; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT:    .cfi_offset ra, -8
; RV64I-NEXT:    call fminimuml
; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT:    .cfi_restore ra
; RV64I-NEXT:    addi sp, sp, 16
; RV64I-NEXT:    .cfi_def_cfa_offset 0
; RV64I-NEXT:    ret
  %a = call fp128 @llvm.minimum.fp128(fp128 %x, fp128 %y)
  ret fp128 %a
}

define { fp128, fp128 } @modf(fp128 %a) nounwind {
; RV32I-LABEL: modf:
; RV32I:       # %bb.0:
; RV32I-NEXT:    addi sp, sp, -64
; RV32I-NEXT:    sw ra, 60(sp) # 4-byte Folded Spill
; RV32I-NEXT:    sw s0, 56(sp) # 4-byte Folded Spill
; RV32I-NEXT:    lw a3, 0(a1)
; RV32I-NEXT:    lw a4, 4(a1)
; RV32I-NEXT:    lw a5, 8(a1)
; RV32I-NEXT:    lw a6, 12(a1)
; RV32I-NEXT:    mv s0, a0
; RV32I-NEXT:    addi a0, sp, 24
; RV32I-NEXT:    addi a1, sp, 8
; RV32I-NEXT:    addi a2, sp, 40
; RV32I-NEXT:    sw a3, 8(sp)
; RV32I-NEXT:    sw a4, 12(sp)
; RV32I-NEXT:    sw a5, 16(sp)
; RV32I-NEXT:    sw a6, 20(sp)
; RV32I-NEXT:    call modfl
; RV32I-NEXT:    lw a0, 40(sp)
; RV32I-NEXT:    lw a1, 44(sp)
; RV32I-NEXT:    lw a2, 48(sp)
; RV32I-NEXT:    lw a3, 52(sp)
; RV32I-NEXT:    lw a4, 24(sp)
; RV32I-NEXT:    lw a5, 28(sp)
; RV32I-NEXT:    lw a6, 32(sp)
; RV32I-NEXT:    lw a7, 36(sp)
; RV32I-NEXT:    sw a0, 16(s0)
; RV32I-NEXT:    sw a1, 20(s0)
; RV32I-NEXT:    sw a2, 24(s0)
; RV32I-NEXT:    sw a3, 28(s0)
; RV32I-NEXT:    sw a4, 0(s0)
; RV32I-NEXT:    sw a5, 4(s0)
; RV32I-NEXT:    sw a6, 8(s0)
; RV32I-NEXT:    sw a7, 12(s0)
; RV32I-NEXT:    lw ra, 60(sp) # 4-byte Folded Reload
; RV32I-NEXT:    lw s0, 56(sp) # 4-byte Folded Reload
; RV32I-NEXT:    addi sp, sp, 64
; RV32I-NEXT:    ret
;
; RV64I-LABEL: modf:
; RV64I:       # %bb.0:
; RV64I-NEXT:    addi sp, sp, -32
; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT:    mv a3, a2
; RV64I-NEXT:    mv s0, a0
; RV64I-NEXT:    mv a2, sp
; RV64I-NEXT:    mv a0, a1
; RV64I-NEXT:    mv a1, a3
; RV64I-NEXT:    call modfl
; RV64I-NEXT:    ld a2, 0(sp)
; RV64I-NEXT:    ld a3, 8(sp)
; RV64I-NEXT:    sd a0, 0(s0)
; RV64I-NEXT:    sd a1, 8(s0)
; RV64I-NEXT:    sd a2, 16(s0)
; RV64I-NEXT:    sd a3, 24(s0)
; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT:    addi sp, sp, 32
; RV64I-NEXT:    ret
  %result = call { fp128, fp128 } @llvm.modf.f128(fp128 %a)
  ret { fp128, fp128 } %result
}

define i96 @fptosi_fp128_to_i96(fp128 %a) nounwind {
; RV32I-LABEL: fptosi_fp128_to_i96:
; RV32I:       # %bb.0: # %fp-to-i-entry
; RV32I-NEXT:    addi sp, sp, -112
; RV32I-NEXT:    sw ra, 108(sp) # 4-byte Folded Spill
; RV32I-NEXT:    sw s0, 104(sp) # 4-byte Folded Spill
; RV32I-NEXT:    sw s1, 100(sp) # 4-byte Folded Spill
; RV32I-NEXT:    sw s2, 96(sp) # 4-byte Folded Spill
; RV32I-NEXT:    sw s3, 92(sp) # 4-byte Folded Spill
; RV32I-NEXT:    sw s4, 88(sp) # 4-byte Folded Spill
; RV32I-NEXT:    sw s5, 84(sp) # 4-byte Folded Spill
; RV32I-NEXT:    sw s6, 80(sp) # 4-byte Folded Spill
; RV32I-NEXT:    sw s7, 76(sp) # 4-byte Folded Spill
; RV32I-NEXT:    sw s8, 72(sp) # 4-byte Folded Spill
; RV32I-NEXT:    sw s9, 68(sp) # 4-byte Folded Spill
; RV32I-NEXT:    sw s10, 64(sp) # 4-byte Folded Spill
; RV32I-NEXT:    lui a6, 4
; RV32I-NEXT:    lw a5, 12(a1)
; RV32I-NEXT:    slli a4, a5, 1
; RV32I-NEXT:    srli a4, a4, 17
; RV32I-NEXT:    addi a2, a6, -1
; RV32I-NEXT:    mv s0, a0
; RV32I-NEXT:    bgeu a4, a2, .LBB5_2
; RV32I-NEXT:  # %bb.1:
; RV32I-NEXT:    li s3, 0
; RV32I-NEXT:    li s8, 0
; RV32I-NEXT:    li a0, 0
; RV32I-NEXT:    j .LBB5_5
; RV32I-NEXT:  .LBB5_2: # %fp-to-i-if-check.exp.size
; RV32I-NEXT:    lw a3, 0(a1)
; RV32I-NEXT:    lw a2, 4(a1)
; RV32I-NEXT:    lw a0, 8(a1)
; RV32I-NEXT:    srai s1, a5, 31
; RV32I-NEXT:    addi a1, a6, 110
; RV32I-NEXT:    ori s2, s1, 1
; RV32I-NEXT:    bltu a1, a4, .LBB5_4
; RV32I-NEXT:  # %bb.3: # %fp-to-i-if-exp.small
; RV32I-NEXT:    slli a5, a5, 16
; RV32I-NEXT:    lui a1, 16
; RV32I-NEXT:    srli a5, a5, 16
; RV32I-NEXT:    addi a6, a6, 111
; RV32I-NEXT:    or a1, a5, a1
; RV32I-NEXT:    sub a4, a6, a4
; RV32I-NEXT:    srli a5, a4, 3
; RV32I-NEXT:    sw zero, 16(sp)
; RV32I-NEXT:    sw zero, 20(sp)
; RV32I-NEXT:    sw zero, 24(sp)
; RV32I-NEXT:    sw zero, 28(sp)
; RV32I-NEXT:    andi a5, a5, 12
; RV32I-NEXT:    mv a6, sp
; RV32I-NEXT:    sw a3, 0(sp)
; RV32I-NEXT:    sw a2, 4(sp)
; RV32I-NEXT:    sw a0, 8(sp)
; RV32I-NEXT:    sw a1, 12(sp)
; RV32I-NEXT:    add a5, a6, a5
; RV32I-NEXT:    lw a0, 12(a5)
; RV32I-NEXT:    lw a1, 8(a5)
; RV32I-NEXT:    lw a2, 4(a5)
; RV32I-NEXT:    lw a3, 0(a5)
; RV32I-NEXT:    andi a5, a4, 31
; RV32I-NEXT:    xori a5, a5, 31
; RV32I-NEXT:    slli a6, a0, 1
; RV32I-NEXT:    srl a7, a1, a4
; RV32I-NEXT:    sll a6, a6, a5
; RV32I-NEXT:    or s4, a7, a6
; RV32I-NEXT:    slli a1, a1, 1
; RV32I-NEXT:    srl a6, a2, a4
; RV32I-NEXT:    sll a1, a1, a5
; RV32I-NEXT:    or s5, a6, a1
; RV32I-NEXT:    slli a2, a2, 1
; RV32I-NEXT:    srl a1, a3, a4
; RV32I-NEXT:    sll a2, a2, a5
; RV32I-NEXT:    or s6, a1, a2
; RV32I-NEXT:    srl s7, a0, a4
; RV32I-NEXT:    mv a0, s6
; RV32I-NEXT:    li a1, 0
; RV32I-NEXT:    mv a2, s2
; RV32I-NEXT:    li a3, 0
; RV32I-NEXT:    call __muldi3
; RV32I-NEXT:    mv s3, a0
; RV32I-NEXT:    mv s8, a1
; RV32I-NEXT:    mv a0, s5
; RV32I-NEXT:    li a1, 0
; RV32I-NEXT:    mv a2, s2
; RV32I-NEXT:    li a3, 0
; RV32I-NEXT:    call __muldi3
; RV32I-NEXT:    add s8, a0, s8
; RV32I-NEXT:    sltu a0, s8, a0
; RV32I-NEXT:    add s9, a1, a0
; RV32I-NEXT:    mv a0, s6
; RV32I-NEXT:    li a1, 0
; RV32I-NEXT:    mv a2, s1
; RV32I-NEXT:    li a3, 0
; RV32I-NEXT:    call __muldi3
; RV32I-NEXT:    add s8, a0, s8
; RV32I-NEXT:    sltu a0, s8, a0
; RV32I-NEXT:    add s10, a1, a0
; RV32I-NEXT:    mv a0, s5
; RV32I-NEXT:    li a1, 0
; RV32I-NEXT:    mv a2, s1
; RV32I-NEXT:    li a3, 0
; RV32I-NEXT:    call __muldi3
; RV32I-NEXT:    add a0, a0, s9
; RV32I-NEXT:    add s10, a0, s10
; RV32I-NEXT:    mv a0, s1
; RV32I-NEXT:    mv a2, s6
; RV32I-NEXT:    mv a3, s5
; RV32I-NEXT:    call __muldi3
; RV32I-NEXT:    mv s5, a0
; RV32I-NEXT:    mv a0, s2
; RV32I-NEXT:    mv a1, s1
; RV32I-NEXT:    mv a2, s4
; RV32I-NEXT:    mv a3, s7
; RV32I-NEXT:    call __muldi3
; RV32I-NEXT:    add a0, s5, a0
; RV32I-NEXT:    add a0, s10, a0
; RV32I-NEXT:    j .LBB5_5
; RV32I-NEXT:  .LBB5_4: # %fp-to-i-if-exp.large
; RV32I-NEXT:    lui a1, 1048572
; RV32I-NEXT:    addi a1, a1, -111
; RV32I-NEXT:    add a1, a4, a1
; RV32I-NEXT:    sw zero, 32(sp)
; RV32I-NEXT:    sw zero, 36(sp)
; RV32I-NEXT:    sw zero, 40(sp)
; RV32I-NEXT:    sw zero, 44(sp)
; RV32I-NEXT:    srli a4, a1, 3
; RV32I-NEXT:    addi a5, sp, 48
; RV32I-NEXT:    andi a4, a4, 12
; RV32I-NEXT:    sw a3, 48(sp)
; RV32I-NEXT:    sw a2, 52(sp)
; RV32I-NEXT:    sw a0, 56(sp)
; RV32I-NEXT:    sub a5, a5, a4
; RV32I-NEXT:    lw a0, 0(a5)
; RV32I-NEXT:    lw a2, 4(a5)
; RV32I-NEXT:    andi a3, a1, 31
; RV32I-NEXT:    xori a3, a3, 31
; RV32I-NEXT:    lw a4, 8(a5)
; RV32I-NEXT:    lw a5, 12(a5)
; RV32I-NEXT:    srli a6, a0, 1
; RV32I-NEXT:    sll a7, a2, a1
; RV32I-NEXT:    srl a6, a6, a3
; RV32I-NEXT:    srli a2, a2, 1
; RV32I-NEXT:    or s4, a7, a6
; RV32I-NEXT:    sll a6, a4, a1
; RV32I-NEXT:    srl a2, a2, a3
; RV32I-NEXT:    or a2, a6, a2
; RV32I-NEXT:    srli a4, a4, 1
; RV32I-NEXT:    sll a5, a5, a1
; RV32I-NEXT:    srl a3, a4, a3
; RV32I-NEXT:    or a3, a5, a3
; RV32I-NEXT:    sll s5, a0, a1
; RV32I-NEXT:    mv a0, s2
; RV32I-NEXT:    mv a1, s1
; RV32I-NEXT:    call __muldi3
; RV32I-NEXT:    mv s3, a0
; RV32I-NEXT:    mv a0, s1
; RV32I-NEXT:    mv a2, s5
; RV32I-NEXT:    mv a3, s4
; RV32I-NEXT:    call __muldi3
; RV32I-NEXT:    add s9, a0, s3
; RV32I-NEXT:    mv a0, s4
; RV32I-NEXT:    li a1, 0
; RV32I-NEXT:    mv a2, s2
; RV32I-NEXT:    li a3, 0
; RV32I-NEXT:    call __muldi3
; RV32I-NEXT:    mv s6, a0
; RV32I-NEXT:    mv s7, a1
; RV32I-NEXT:    mv a0, s5
; RV32I-NEXT:    li a1, 0
; RV32I-NEXT:    mv a2, s2
; RV32I-NEXT:    li a3, 0
; RV32I-NEXT:    call __muldi3
; RV32I-NEXT:    mv s3, a0
; RV32I-NEXT:    add s8, s6, a1
; RV32I-NEXT:    sltu a0, s8, s6
; RV32I-NEXT:    add s7, s7, a0
; RV32I-NEXT:    mv a0, s5
; RV32I-NEXT:    li a1, 0
; RV32I-NEXT:    mv a2, s1
; RV32I-NEXT:    li a3, 0
; RV32I-NEXT:    call __muldi3
; RV32I-NEXT:    add s8, a0, s8
; RV32I-NEXT:    sltu a0, s8, a0
; RV32I-NEXT:    add s2, a1, a0
; RV32I-NEXT:    mv a0, s4
; RV32I-NEXT:    li a1, 0
; RV32I-NEXT:    mv a2, s1
; RV32I-NEXT:    li a3, 0
; RV32I-NEXT:    call __muldi3
; RV32I-NEXT:    add a0, a0, s7
; RV32I-NEXT:    add a0, a0, s2
; RV32I-NEXT:    add a0, a0, s9
; RV32I-NEXT:  .LBB5_5: # %fp-to-i-cleanup
; RV32I-NEXT:    sw s3, 0(s0)
; RV32I-NEXT:    sw s8, 4(s0)
; RV32I-NEXT:    sw a0, 8(s0)
; RV32I-NEXT:    lw ra, 108(sp) # 4-byte Folded Reload
; RV32I-NEXT:    lw s0, 104(sp) # 4-byte Folded Reload
; RV32I-NEXT:    lw s1, 100(sp) # 4-byte Folded Reload
; RV32I-NEXT:    lw s2, 96(sp) # 4-byte Folded Reload
; RV32I-NEXT:    lw s3, 92(sp) # 4-byte Folded Reload
; RV32I-NEXT:    lw s4, 88(sp) # 4-byte Folded Reload
; RV32I-NEXT:    lw s5, 84(sp) # 4-byte Folded Reload
; RV32I-NEXT:    lw s6, 80(sp) # 4-byte Folded Reload
; RV32I-NEXT:    lw s7, 76(sp) # 4-byte Folded Reload
; RV32I-NEXT:    lw s8, 72(sp) # 4-byte Folded Reload
; RV32I-NEXT:    lw s9, 68(sp) # 4-byte Folded Reload
; RV32I-NEXT:    lw s10, 64(sp) # 4-byte Folded Reload
; RV32I-NEXT:    addi sp, sp, 112
; RV32I-NEXT:    ret
;
; RV64I-LABEL: fptosi_fp128_to_i96:
; RV64I:       # %bb.0:
; RV64I-NEXT:    addi sp, sp, -16
; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT:    call __fixtfti
; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT:    addi sp, sp, 16
; RV64I-NEXT:    ret
  %result = fptosi fp128 %a to i96
  ret i96 %result
}

define i32 @lround_f128() nounwind {
; RV32I-LABEL: lround_f128:
; RV32I:       # %bb.0:
; RV32I-NEXT:    addi sp, sp, -32
; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT:    lui a0, %hi(x)
; RV32I-NEXT:    lw a1, %lo(x)(a0)
; RV32I-NEXT:    lw a2, %lo(x+4)(a0)
; RV32I-NEXT:    lw a3, %lo(x+8)(a0)
; RV32I-NEXT:    lw a4, %lo(x+12)(a0)
; RV32I-NEXT:    addi a0, sp, 8
; RV32I-NEXT:    sw a1, 8(sp)
; RV32I-NEXT:    sw a2, 12(sp)
; RV32I-NEXT:    sw a3, 16(sp)
; RV32I-NEXT:    sw a4, 20(sp)
; RV32I-NEXT:    call lroundl
; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT:    addi sp, sp, 32
; RV32I-NEXT:    ret
;
; RV64I-LABEL: lround_f128:
; RV64I:       # %bb.0:
; RV64I-NEXT:    addi sp, sp, -16
; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT:    lui a1, %hi(x)
; RV64I-NEXT:    ld a0, %lo(x)(a1)
; RV64I-NEXT:    ld a1, %lo(x+8)(a1)
; RV64I-NEXT:    call lroundl
; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT:    addi sp, sp, 16
; RV64I-NEXT:    ret
  %1 = load fp128, ptr @x, align 16
  %r = call i32 @llvm.lround.f128(fp128 %1)
  ret i32 %r
}

; fp128 ldexp lowers to ldexpl (long double is fp128).
define fp128 @ldexp_f128(fp128 %x, i32 %y) nounwind {
; RV32I-LABEL: ldexp_f128:
; RV32I:       # %bb.0:
; RV32I-NEXT:    addi sp, sp, -48
; RV32I-NEXT:    sw ra, 44(sp) # 4-byte Folded Spill
; RV32I-NEXT:    sw s0, 40(sp) # 4-byte Folded Spill
; RV32I-NEXT:    lw a3, 0(a1)
; RV32I-NEXT:    lw a4, 4(a1)
; RV32I-NEXT:    lw a5, 8(a1)
; RV32I-NEXT:    lw a6, 12(a1)
; RV32I-NEXT:    mv s0, a0
; RV32I-NEXT:    sw a3, 8(sp)
; RV32I-NEXT:    sw a4, 12(sp)
; RV32I-NEXT:    addi a0, sp, 24
; RV32I-NEXT:    addi a1, sp, 8
; RV32I-NEXT:    sw a5, 16(sp)
; RV32I-NEXT:    sw a6, 20(sp)
; RV32I-NEXT:    call ldexpl
; RV32I-NEXT:    lw a0, 24(sp)
; RV32I-NEXT:    lw a1, 28(sp)
; RV32I-NEXT:    lw a2, 32(sp)
; RV32I-NEXT:    lw a3, 36(sp)
; RV32I-NEXT:    sw a0, 0(s0)
; RV32I-NEXT:    sw a1, 4(s0)
; RV32I-NEXT:    sw a2, 8(s0)
; RV32I-NEXT:    sw a3, 12(s0)
; RV32I-NEXT:    lw ra, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT:    lw s0, 40(sp) # 4-byte Folded Reload
; RV32I-NEXT:    addi sp, sp, 48
; RV32I-NEXT:    ret
;
; RV64I-LABEL: ldexp_f128:
; RV64I:       # %bb.0:
; RV64I-NEXT:    addi sp, sp, -16
; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT:    sext.w a2, a2
; RV64I-NEXT:    call ldexpl
; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT:    addi sp, sp, 16
; RV64I-NEXT:    ret
  %z = call fp128 @llvm.ldexp.f128.i32(fp128 %x, i32 %y)
  ret fp128 %z
}