llvm/test/CodeGen/RISCV/bitinsert-bitextract-common-offsets.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=riscv32 < %s | FileCheck %s --check-prefix=RV32
; RUN: llc -mtriple=riscv32 -mattr=+zbb < %s | FileCheck %s --check-prefix=RV32ZBB
; RUN: llc -mtriple=riscv64 < %s | FileCheck %s --check-prefix=RV64
; RUN: llc -mtriple=riscv64 -mattr=+zbb < %s | FileCheck %s --check-prefix=RV64ZBB

; bitextract
define i1 @test_bitextract_b8_off0(b8 %src) {
; RV32-LABEL: test_bitextract_b8_off0:
; RV32:       # %bb.0:
; RV32-NEXT:    ret
;
; RV32ZBB-LABEL: test_bitextract_b8_off0:
; RV32ZBB:       # %bb.0:
; RV32ZBB-NEXT:    ret
;
; RV64-LABEL: test_bitextract_b8_off0:
; RV64:       # %bb.0:
; RV64-NEXT:    ret
;
; RV64ZBB-LABEL: test_bitextract_b8_off0:
; RV64ZBB:       # %bb.0:
; RV64ZBB-NEXT:    ret
  %result = bitextract i1, b8 %src, i32 0
  ret i1 %result
}

define i4 @test_bitextract_b8_nibble_hi(b8 %src) {
; RV32-LABEL: test_bitextract_b8_nibble_hi:
; RV32:       # %bb.0:
; RV32-NEXT:    slli a0, a0, 24
; RV32-NEXT:    srli a0, a0, 28
; RV32-NEXT:    ret
;
; RV32ZBB-LABEL: test_bitextract_b8_nibble_hi:
; RV32ZBB:       # %bb.0:
; RV32ZBB-NEXT:    slli a0, a0, 24
; RV32ZBB-NEXT:    srli a0, a0, 28
; RV32ZBB-NEXT:    ret
;
; RV64-LABEL: test_bitextract_b8_nibble_hi:
; RV64:       # %bb.0:
; RV64-NEXT:    slli a0, a0, 56
; RV64-NEXT:    srli a0, a0, 60
; RV64-NEXT:    ret
;
; RV64ZBB-LABEL: test_bitextract_b8_nibble_hi:
; RV64ZBB:       # %bb.0:
; RV64ZBB-NEXT:    slli a0, a0, 56
; RV64ZBB-NEXT:    srli a0, a0, 60
; RV64ZBB-NEXT:    ret
  %result = bitextract i4, b8 %src, i32 4
  ret i4 %result
}

define i1 @test_bitextract_b8_off_top(b8 %src) {
; RV32-LABEL: test_bitextract_b8_off_top:
; RV32:       # %bb.0:
; RV32-NEXT:    slli a0, a0, 24
; RV32-NEXT:    srli a0, a0, 31
; RV32-NEXT:    ret
;
; RV32ZBB-LABEL: test_bitextract_b8_off_top:
; RV32ZBB:       # %bb.0:
; RV32ZBB-NEXT:    slli a0, a0, 24
; RV32ZBB-NEXT:    srli a0, a0, 31
; RV32ZBB-NEXT:    ret
;
; RV64-LABEL: test_bitextract_b8_off_top:
; RV64:       # %bb.0:
; RV64-NEXT:    slli a0, a0, 56
; RV64-NEXT:    srli a0, a0, 63
; RV64-NEXT:    ret
;
; RV64ZBB-LABEL: test_bitextract_b8_off_top:
; RV64ZBB:       # %bb.0:
; RV64ZBB-NEXT:    slli a0, a0, 56
; RV64ZBB-NEXT:    srli a0, a0, 63
; RV64ZBB-NEXT:    ret
  %result = bitextract i1, b8 %src, i32 7
  ret i1 %result
}

define i8 @test_bitextract_b16_byte_hi(b16 %src) {
; RV32-LABEL: test_bitextract_b16_byte_hi:
; RV32:       # %bb.0:
; RV32-NEXT:    slli a0, a0, 16
; RV32-NEXT:    srli a0, a0, 24
; RV32-NEXT:    ret
;
; RV32ZBB-LABEL: test_bitextract_b16_byte_hi:
; RV32ZBB:       # %bb.0:
; RV32ZBB-NEXT:    slli a0, a0, 16
; RV32ZBB-NEXT:    srli a0, a0, 24
; RV32ZBB-NEXT:    ret
;
; RV64-LABEL: test_bitextract_b16_byte_hi:
; RV64:       # %bb.0:
; RV64-NEXT:    slli a0, a0, 48
; RV64-NEXT:    srli a0, a0, 56
; RV64-NEXT:    ret
;
; RV64ZBB-LABEL: test_bitextract_b16_byte_hi:
; RV64ZBB:       # %bb.0:
; RV64ZBB-NEXT:    slli a0, a0, 48
; RV64ZBB-NEXT:    srli a0, a0, 56
; RV64ZBB-NEXT:    ret
  %result = bitextract i8, b16 %src, i32 8
  ret i8 %result
}

define i32 @test_bitextract_b64_dword_hi(b64 %src) {
; RV32-LABEL: test_bitextract_b64_dword_hi:
; RV32:       # %bb.0:
; RV32-NEXT:    mv a0, a1
; RV32-NEXT:    ret
;
; RV32ZBB-LABEL: test_bitextract_b64_dword_hi:
; RV32ZBB:       # %bb.0:
; RV32ZBB-NEXT:    mv a0, a1
; RV32ZBB-NEXT:    ret
;
; RV64-LABEL: test_bitextract_b64_dword_hi:
; RV64:       # %bb.0:
; RV64-NEXT:    srli a0, a0, 32
; RV64-NEXT:    ret
;
; RV64ZBB-LABEL: test_bitextract_b64_dword_hi:
; RV64ZBB:       # %bb.0:
; RV64ZBB-NEXT:    srli a0, a0, 32
; RV64ZBB-NEXT:    ret
  %result = bitextract i32, b64 %src, i32 32
  ret i32 %result
}

define i64 @test_bitextract_b128_lo64(b128 %src) {
; RV32-LABEL: test_bitextract_b128_lo64:
; RV32:       # %bb.0:
; RV32-NEXT:    lw a2, 0(a0)
; RV32-NEXT:    lw a1, 4(a0)
; RV32-NEXT:    mv a0, a2
; RV32-NEXT:    ret
;
; RV32ZBB-LABEL: test_bitextract_b128_lo64:
; RV32ZBB:       # %bb.0:
; RV32ZBB-NEXT:    lw a2, 0(a0)
; RV32ZBB-NEXT:    lw a1, 4(a0)
; RV32ZBB-NEXT:    mv a0, a2
; RV32ZBB-NEXT:    ret
;
; RV64-LABEL: test_bitextract_b128_lo64:
; RV64:       # %bb.0:
; RV64-NEXT:    ret
;
; RV64ZBB-LABEL: test_bitextract_b128_lo64:
; RV64ZBB:       # %bb.0:
; RV64ZBB-NEXT:    ret
  %result = bitextract i64, b128 %src, i32 0
  ret i64 %result
}

define b8 @test_bitinsert_b8_off1(b8 %base, i1 %val) {
; RV32-LABEL: test_bitinsert_b8_off1:
; RV32:       # %bb.0:
; RV32-NEXT:    andi a1, a1, 1
; RV32-NEXT:    andi a0, a0, -3
; RV32-NEXT:    slli a1, a1, 1
; RV32-NEXT:    or a0, a0, a1
; RV32-NEXT:    ret
;
; RV32ZBB-LABEL: test_bitinsert_b8_off1:
; RV32ZBB:       # %bb.0:
; RV32ZBB-NEXT:    andi a1, a1, 1
; RV32ZBB-NEXT:    andi a0, a0, -3
; RV32ZBB-NEXT:    slli a1, a1, 1
; RV32ZBB-NEXT:    or a0, a0, a1
; RV32ZBB-NEXT:    ret
;
; RV64-LABEL: test_bitinsert_b8_off1:
; RV64:       # %bb.0:
; RV64-NEXT:    andi a1, a1, 1
; RV64-NEXT:    andi a0, a0, -3
; RV64-NEXT:    slli a1, a1, 1
; RV64-NEXT:    or a0, a0, a1
; RV64-NEXT:    ret
;
; RV64ZBB-LABEL: test_bitinsert_b8_off1:
; RV64ZBB:       # %bb.0:
; RV64ZBB-NEXT:    andi a1, a1, 1
; RV64ZBB-NEXT:    andi a0, a0, -3
; RV64ZBB-NEXT:    slli a1, a1, 1
; RV64ZBB-NEXT:    or a0, a0, a1
; RV64ZBB-NEXT:    ret
  %result = bitinsert b8 %base, i1 %val, i32 1
  ret b8 %result
}

define b16 @test_bitinsert_b16_off8(b16 %base, i8 %val) {
; RV32-LABEL: test_bitinsert_b16_off8:
; RV32:       # %bb.0:
; RV32-NEXT:    slli a1, a1, 8
; RV32-NEXT:    zext.b a0, a0
; RV32-NEXT:    or a0, a0, a1
; RV32-NEXT:    ret
;
; RV32ZBB-LABEL: test_bitinsert_b16_off8:
; RV32ZBB:       # %bb.0:
; RV32ZBB-NEXT:    slli a1, a1, 8
; RV32ZBB-NEXT:    zext.b a0, a0
; RV32ZBB-NEXT:    or a0, a0, a1
; RV32ZBB-NEXT:    ret
;
; RV64-LABEL: test_bitinsert_b16_off8:
; RV64:       # %bb.0:
; RV64-NEXT:    slli a1, a1, 8
; RV64-NEXT:    zext.b a0, a0
; RV64-NEXT:    or a0, a0, a1
; RV64-NEXT:    ret
;
; RV64ZBB-LABEL: test_bitinsert_b16_off8:
; RV64ZBB:       # %bb.0:
; RV64ZBB-NEXT:    slli a1, a1, 8
; RV64ZBB-NEXT:    zext.b a0, a0
; RV64ZBB-NEXT:    or a0, a0, a1
; RV64ZBB-NEXT:    ret
  %result = bitinsert b16 %base, i8 %val, i32 8
  ret b16 %result
}

; b32 container: offsets 1, 2, 4, 8, 16

define b32 @test_bitinsert_b32_off8(b32 %base, i8 %val) {
; RV32-LABEL: test_bitinsert_b32_off8:
; RV32:       # %bb.0:
; RV32-NEXT:    lui a2, 1048560
; RV32-NEXT:    addi a2, a2, 255
; RV32-NEXT:    zext.b a1, a1
; RV32-NEXT:    and a0, a0, a2
; RV32-NEXT:    slli a1, a1, 8
; RV32-NEXT:    or a0, a0, a1
; RV32-NEXT:    ret
;
; RV32ZBB-LABEL: test_bitinsert_b32_off8:
; RV32ZBB:       # %bb.0:
; RV32ZBB-NEXT:    lui a2, 1048560
; RV32ZBB-NEXT:    addi a2, a2, 255
; RV32ZBB-NEXT:    zext.b a1, a1
; RV32ZBB-NEXT:    and a0, a0, a2
; RV32ZBB-NEXT:    slli a1, a1, 8
; RV32ZBB-NEXT:    or a0, a0, a1
; RV32ZBB-NEXT:    ret
;
; RV64-LABEL: test_bitinsert_b32_off8:
; RV64:       # %bb.0:
; RV64-NEXT:    lui a2, 1048560
; RV64-NEXT:    addi a2, a2, 255
; RV64-NEXT:    zext.b a1, a1
; RV64-NEXT:    and a0, a0, a2
; RV64-NEXT:    slli a1, a1, 8
; RV64-NEXT:    or a0, a0, a1
; RV64-NEXT:    ret
;
; RV64ZBB-LABEL: test_bitinsert_b32_off8:
; RV64ZBB:       # %bb.0:
; RV64ZBB-NEXT:    lui a2, 1048560
; RV64ZBB-NEXT:    addi a2, a2, 255
; RV64ZBB-NEXT:    zext.b a1, a1
; RV64ZBB-NEXT:    and a0, a0, a2
; RV64ZBB-NEXT:    slli a1, a1, 8
; RV64ZBB-NEXT:    or a0, a0, a1
; RV64ZBB-NEXT:    ret
  %result = bitinsert b32 %base, i8 %val, i32 8
  ret b32 %result
}

define b64 @test_bitinsert_b64_off32(b64 %base, i32 %val) {
; RV32-LABEL: test_bitinsert_b64_off32:
; RV32:       # %bb.0:
; RV32-NEXT:    mv a1, a2
; RV32-NEXT:    ret
;
; RV32ZBB-LABEL: test_bitinsert_b64_off32:
; RV32ZBB:       # %bb.0:
; RV32ZBB-NEXT:    mv a1, a2
; RV32ZBB-NEXT:    ret
;
; RV64-LABEL: test_bitinsert_b64_off32:
; RV64:       # %bb.0:
; RV64-NEXT:    slli a0, a0, 32
; RV64-NEXT:    slli a1, a1, 32
; RV64-NEXT:    srli a0, a0, 32
; RV64-NEXT:    or a0, a0, a1
; RV64-NEXT:    ret
;
; RV64ZBB-LABEL: test_bitinsert_b64_off32:
; RV64ZBB:       # %bb.0:
; RV64ZBB-NEXT:    slli a0, a0, 32
; RV64ZBB-NEXT:    slli a1, a1, 32
; RV64ZBB-NEXT:    srli a0, a0, 32
; RV64ZBB-NEXT:    or a0, a0, a1
; RV64ZBB-NEXT:    ret
  %result = bitinsert b64 %base, i32 %val, i32 32
  ret b64 %result
}


; b128 container: offsets 1, 2, 4, 8, 16, 32, 64

define b128 @test_bitinsert_b128_off64(b128 %base, i64 %val) {
; RV32-LABEL: test_bitinsert_b128_off64:
; RV32:       # %bb.0:
; RV32-NEXT:    lw a4, 0(a1)
; RV32-NEXT:    lw a1, 4(a1)
; RV32-NEXT:    sw a4, 0(a0)
; RV32-NEXT:    sw a1, 4(a0)
; RV32-NEXT:    sw a2, 8(a0)
; RV32-NEXT:    sw a3, 12(a0)
; RV32-NEXT:    ret
;
; RV32ZBB-LABEL: test_bitinsert_b128_off64:
; RV32ZBB:       # %bb.0:
; RV32ZBB-NEXT:    lw a4, 0(a1)
; RV32ZBB-NEXT:    lw a1, 4(a1)
; RV32ZBB-NEXT:    sw a4, 0(a0)
; RV32ZBB-NEXT:    sw a1, 4(a0)
; RV32ZBB-NEXT:    sw a2, 8(a0)
; RV32ZBB-NEXT:    sw a3, 12(a0)
; RV32ZBB-NEXT:    ret
;
; RV64-LABEL: test_bitinsert_b128_off64:
; RV64:       # %bb.0:
; RV64-NEXT:    mv a1, a2
; RV64-NEXT:    ret
;
; RV64ZBB-LABEL: test_bitinsert_b128_off64:
; RV64ZBB:       # %bb.0:
; RV64ZBB-NEXT:    mv a1, a2
; RV64ZBB-NEXT:    ret
  %result = bitinsert b128 %base, i64 %val, i32 64
  ret b128 %result
}