llvm/test/CodeGen/PowerPC/nofpexcept.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s \
; RUN:   -stop-after=finalize-isel -verify-machineinstrs | FileCheck %s

; Verify if the mayRaiseFPException is set for FCMPD/FCMPS
define i32 @fcmpu(double %a, double %b) {
  ; CHECK-LABEL: name: fcmpu
  ; CHECK: bb.0.entry:
  ; CHECK-NEXT:   liveins: $f1, $f2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:f8rc = COPY $f2
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:f8rc = COPY $f1
  ; CHECK-NEXT:   [[FCMPUD:%[0-9]+]]:crrc = nofpexcept FCMPUD [[COPY1]], [[COPY]]
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:crbitrc = COPY [[FCMPUD]].sub_gt
  ; CHECK-NEXT:   [[LI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = LI8 0
  ; CHECK-NEXT:   [[LI8_1:%[0-9]+]]:g8rc_and_g8rc_nox0 = LI8 1
  ; CHECK-NEXT:   [[ISEL8_:%[0-9]+]]:g8rc = ISEL8 [[LI8_1]], [[LI8_]], [[COPY2]]
  ; CHECK-NEXT:   $x3 = COPY [[ISEL8_]]
  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm, implicit $x3
entry:
  %r = fcmp ogt double %a, %b
  %g = zext i1 %r to i32
  ret i32 %g
}

define double @max_typec(double %a, double %b) {
  ; CHECK-LABEL: name: max_typec
  ; CHECK: bb.0.entry:
  ; CHECK-NEXT:   liveins: $f1, $f2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vsfrc = COPY $f2
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:vsfrc = COPY $f1
  ; CHECK-NEXT:   [[XSMAXCDP:%[0-9]+]]:vsfrc = nofpexcept XSMAXCDP [[COPY1]], [[COPY]]
  ; CHECK-NEXT:   $f1 = COPY [[XSMAXCDP]]
  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm, implicit $f1
entry:
  %cmp = fcmp ogt double %a, %b
  %sel = select i1 %cmp, double %a, double %b
  ret double %sel
}

; Verify no mayRaiseFPException bit set on fneg & fabs
define double @fneg(double %a) {
  ; CHECK-LABEL: name: fneg
  ; CHECK: bb.0.entry:
  ; CHECK-NEXT:   liveins: $f1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vsfrc = COPY $f1
  ; CHECK-NEXT:   [[XSNEGDP:%[0-9]+]]:vsfrc = XSNEGDP [[COPY]], implicit $rm
  ; CHECK-NEXT:   $f1 = COPY [[XSNEGDP]]
  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm, implicit $f1
entry:
  %neg = fneg double %a
  ret double %neg
}

define double @fabs(double %a) {
  ; CHECK-LABEL: name: fabs
  ; CHECK: bb.0.entry:
  ; CHECK-NEXT:   liveins: $f1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vsfrc = COPY $f1
  ; CHECK-NEXT:   [[XSABSDP:%[0-9]+]]:vsfrc = XSABSDP [[COPY]], implicit $rm
  ; CHECK-NEXT:   $f1 = COPY [[XSABSDP]]
  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm, implicit $f1
entry:
  %abs = call double @llvm.fabs.f64(double %a)
  ret double %abs
}

; Verify nofpexcept is set to constrained conversions when ignoring exceptions
define void @fptoint_nofpexcept(ppc_fp128 %p, fp128 %m, ptr %addr1, ptr %addr2) #0 {
  ; CHECK-LABEL: name: fptoint_nofpexcept
  ; CHECK: bb.0.entry:
  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; CHECK-NEXT:   liveins: $f1, $f2, $v2, $x7, $x8
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x8
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x7
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:vrrc = COPY $v2
  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:f8rc = COPY $f2
  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:f8rc = COPY $f1
  ; CHECK-NEXT:   [[XSCVQPSWZ:%[0-9]+]]:vrrc = nofpexcept XSCVQPSWZ [[COPY2]]
  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:vslrc = COPY [[XSCVQPSWZ]]
  ; CHECK-NEXT:   [[COPY6:%[0-9]+]]:vsfrc = COPY [[COPY5]].sub_64
  ; CHECK-NEXT:   STIWX [[COPY6]], $zero8, [[COPY1]] :: (volatile store (s32) into %ir.addr1)
  ; CHECK-NEXT:   [[XSCVQPUWZ:%[0-9]+]]:vrrc = nofpexcept XSCVQPUWZ [[COPY2]]
  ; CHECK-NEXT:   [[COPY7:%[0-9]+]]:vslrc = COPY [[XSCVQPUWZ]]
  ; CHECK-NEXT:   [[COPY8:%[0-9]+]]:vsfrc = COPY [[COPY7]].sub_64
  ; CHECK-NEXT:   STIWX [[COPY8]], $zero8, [[COPY1]] :: (volatile store (s32) into %ir.addr1)
  ; CHECK-NEXT:   [[XSCVQPSDZ:%[0-9]+]]:vrrc = nofpexcept XSCVQPSDZ [[COPY2]]
  ; CHECK-NEXT:   [[MFVRD:%[0-9]+]]:g8rc = nofpexcept MFVRD [[XSCVQPSDZ]]
  ; CHECK-NEXT:   [[XSCVQPSDZ1:%[0-9]+]]:vrrc = nofpexcept XSCVQPSDZ [[COPY2]]
  ; CHECK-NEXT:   [[COPY9:%[0-9]+]]:vslrc = COPY [[XSCVQPSDZ1]]
  ; CHECK-NEXT:   [[COPY10:%[0-9]+]]:vfrc = COPY [[COPY9]].sub_64
  ; CHECK-NEXT:   STXSD [[COPY10]], 0, [[COPY]] :: (volatile store (s64) into %ir.addr2)
  ; CHECK-NEXT:   [[XSCVQPUDZ:%[0-9]+]]:vrrc = nofpexcept XSCVQPUDZ [[COPY2]]
  ; CHECK-NEXT:   [[MFVRD1:%[0-9]+]]:g8rc = nofpexcept MFVRD [[XSCVQPUDZ]]
  ; CHECK-NEXT:   [[XSCVQPUDZ1:%[0-9]+]]:vrrc = nofpexcept XSCVQPUDZ [[COPY2]]
  ; CHECK-NEXT:   [[COPY11:%[0-9]+]]:vslrc = COPY [[XSCVQPUDZ1]]
  ; CHECK-NEXT:   [[COPY12:%[0-9]+]]:vfrc = COPY [[COPY11]].sub_64
  ; CHECK-NEXT:   STXSD [[COPY12]], 0, [[COPY]] :: (volatile store (s64) into %ir.addr2)
  ; CHECK-NEXT:   [[MFFS:%[0-9]+]]:f8rc = MFFS implicit $rm
  ; CHECK-NEXT:   MTFSB1 31, implicit-def $rm, implicit-def $rm
  ; CHECK-NEXT:   MTFSB0 30, implicit-def $rm, implicit-def $rm
  ; CHECK-NEXT:   [[FADD:%[0-9]+]]:f8rc = nofpexcept FADD [[COPY3]], [[COPY4]], implicit $rm
  ; CHECK-NEXT:   MTFSFb 1, [[MFFS]], implicit-def $rm
  ; CHECK-NEXT:   [[XSCVDPSXWS:%[0-9]+]]:vsfrc = nofpexcept XSCVDPSXWS [[FADD]], implicit $rm
  ; CHECK-NEXT:   STIWX [[XSCVDPSXWS]], $zero8, [[COPY1]] :: (volatile store (s32) into %ir.addr1)
  ; CHECK-NEXT:   [[ADDIStocHA8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, %const.0
  ; CHECK-NEXT:   [[DFLOADf32_:%[0-9]+]]:vssrc = DFLOADf32 target-flags(ppc-toc-lo) %const.0, [[ADDIStocHA8_]] :: (load (s32) from constant-pool)
  ; CHECK-NEXT:   [[COPY13:%[0-9]+]]:f8rc = COPY [[DFLOADf32_]]
  ; CHECK-NEXT:   [[FCMPOD:%[0-9]+]]:crrc = FCMPOD [[COPY4]], [[COPY13]]
  ; CHECK-NEXT:   [[COPY14:%[0-9]+]]:crbitrc = COPY [[FCMPOD]].sub_eq
  ; CHECK-NEXT:   [[XXLXORdpz:%[0-9]+]]:f8rc = XXLXORdpz
  ; CHECK-NEXT:   [[FCMPOD1:%[0-9]+]]:crrc = FCMPOD [[COPY3]], [[XXLXORdpz]]
  ; CHECK-NEXT:   [[COPY15:%[0-9]+]]:crbitrc = COPY [[FCMPOD1]].sub_lt
  ; CHECK-NEXT:   [[CRAND:%[0-9]+]]:crbitrc = CRAND [[COPY14]], [[COPY15]]
  ; CHECK-NEXT:   [[COPY16:%[0-9]+]]:crbitrc = COPY [[FCMPOD]].sub_eq
  ; CHECK-NEXT:   [[COPY17:%[0-9]+]]:crbitrc = COPY [[FCMPOD]].sub_lt
  ; CHECK-NEXT:   [[CRANDC:%[0-9]+]]:crbitrc = CRANDC [[COPY17]], [[COPY16]]
  ; CHECK-NEXT:   [[CROR:%[0-9]+]]:crbitrc = CROR [[CRANDC]], [[CRAND]]
  ; CHECK-NEXT:   [[LIS:%[0-9]+]]:gprc_and_gprc_nor0 = LIS 32768
  ; CHECK-NEXT:   [[LI:%[0-9]+]]:gprc_and_gprc_nor0 = LI 0
  ; CHECK-NEXT:   [[ISEL:%[0-9]+]]:gprc = ISEL [[LI]], [[LIS]], [[CROR]]
  ; CHECK-NEXT:   BC [[CROR]], %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1.entry:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2.entry:
  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:f8rc = PHI [[COPY13]], %bb.1, [[XXLXORdpz]], %bb.0
  ; CHECK-NEXT:   ADJCALLSTACKDOWN 32, 0, implicit-def dead $r1, implicit $r1
  ; CHECK-NEXT:   $f1 = COPY [[COPY4]]
  ; CHECK-NEXT:   $f2 = COPY [[COPY3]]
  ; CHECK-NEXT:   $f3 = COPY [[PHI]]
  ; CHECK-NEXT:   $f4 = COPY [[XXLXORdpz]]
  ; CHECK-NEXT:   BL8_NOP &__gcc_qsub, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $x2, implicit-def $r1, implicit-def $f1, implicit-def $f2
  ; CHECK-NEXT:   ADJCALLSTACKUP 32, 0, implicit-def dead $r1, implicit $r1
  ; CHECK-NEXT:   [[COPY18:%[0-9]+]]:f8rc = COPY $f1
  ; CHECK-NEXT:   [[COPY19:%[0-9]+]]:f8rc = COPY $f2
  ; CHECK-NEXT:   [[MFFS1:%[0-9]+]]:f8rc = MFFS implicit $rm
  ; CHECK-NEXT:   MTFSB1 31, implicit-def $rm, implicit-def $rm
  ; CHECK-NEXT:   MTFSB0 30, implicit-def $rm, implicit-def $rm
  ; CHECK-NEXT:   [[FADD1:%[0-9]+]]:f8rc = nofpexcept FADD [[COPY19]], [[COPY18]], implicit $rm
  ; CHECK-NEXT:   MTFSFb 1, [[MFFS1]], implicit-def $rm
  ; CHECK-NEXT:   [[XSCVDPSXWS1:%[0-9]+]]:vsfrc = nofpexcept XSCVDPSXWS [[FADD1]], implicit $rm
  ; CHECK-NEXT:   [[MFVSRWZ:%[0-9]+]]:gprc = MFVSRWZ [[XSCVDPSXWS1]]
  ; CHECK-NEXT:   [[XOR:%[0-9]+]]:gprc = XOR [[MFVSRWZ]], [[ISEL]]
  ; CHECK-NEXT:   STW [[XOR]], 0, [[COPY1]] :: (volatile store (s32) into %ir.addr1)
  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm
entry:
  %conv1 = tail call i32 @llvm.experimental.constrained.fptosi.i32.f128(fp128 %m, metadata !"fpexcept.ignore")
  store volatile i32 %conv1, ptr %addr1, align 4
  %conv2 = tail call i32 @llvm.experimental.constrained.fptoui.i32.f128(fp128 %m, metadata !"fpexcept.ignore")
  store volatile i32 %conv2, ptr %addr1, align 4
  %conv3 = tail call i64 @llvm.experimental.constrained.fptosi.i64.f128(fp128 %m, metadata !"fpexcept.ignore")
  store volatile i64 %conv3, ptr %addr2, align 8
  %conv4 = tail call i64 @llvm.experimental.constrained.fptoui.i64.f128(fp128 %m, metadata !"fpexcept.ignore")
  store volatile i64 %conv4, ptr %addr2, align 8

  %conv5 = tail call i32 @llvm.experimental.constrained.fptosi.i32.ppcf128(ppc_fp128 %p, metadata !"fpexcept.ignore")
  store volatile i32 %conv5, ptr %addr1, align 4
  %conv6 = tail call i32 @llvm.experimental.constrained.fptoui.i32.ppcf128(ppc_fp128 %p, metadata !"fpexcept.ignore")
  store volatile i32 %conv6, ptr %addr1, align 4
  ret void
}

; Verify nofpexcept is NOT set to constrained conversions
define signext i32 @q_to_i32(fp128 %m) #0 {
  ; CHECK-LABEL: name: q_to_i32
  ; CHECK: bb.0.entry:
  ; CHECK-NEXT:   liveins: $v2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vrrc = COPY $v2
  ; CHECK-NEXT:   [[XSCVQPSWZ:%[0-9]+]]:vrrc = XSCVQPSWZ [[COPY]]
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:vslrc = COPY [[XSCVQPSWZ]]
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:vfrc = COPY [[COPY1]].sub_64
  ; CHECK-NEXT:   [[MFVSRWZ:%[0-9]+]]:gprc = MFVSRWZ [[COPY2]]
  ; CHECK-NEXT:   [[EXTSW_32_64_:%[0-9]+]]:g8rc = EXTSW_32_64 [[MFVSRWZ]]
  ; CHECK-NEXT:   $x3 = COPY [[EXTSW_32_64_]]
  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm, implicit $x3
entry:
  %conv = tail call i32 @llvm.experimental.constrained.fptosi.i32.f128(fp128 %m, metadata !"fpexcept.strict")
  ret i32 %conv
}

define i64 @q_to_i64(fp128 %m) #0 {
  ; CHECK-LABEL: name: q_to_i64
  ; CHECK: bb.0.entry:
  ; CHECK-NEXT:   liveins: $v2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vrrc = COPY $v2
  ; CHECK-NEXT:   [[XSCVQPSDZ:%[0-9]+]]:vrrc = XSCVQPSDZ [[COPY]]
  ; CHECK-NEXT:   [[MFVRD:%[0-9]+]]:g8rc = MFVRD [[XSCVQPSDZ]]
  ; CHECK-NEXT:   $x3 = COPY [[MFVRD]]
  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm, implicit $x3
entry:
  %conv = tail call i64 @llvm.experimental.constrained.fptosi.i64.f128(fp128 %m, metadata !"fpexcept.strict")
  ret i64 %conv
}

define i64 @q_to_u64(fp128 %m) #0 {
  ; CHECK-LABEL: name: q_to_u64
  ; CHECK: bb.0.entry:
  ; CHECK-NEXT:   liveins: $v2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vrrc = COPY $v2
  ; CHECK-NEXT:   [[XSCVQPUDZ:%[0-9]+]]:vrrc = XSCVQPUDZ [[COPY]]
  ; CHECK-NEXT:   [[MFVRD:%[0-9]+]]:g8rc = MFVRD [[XSCVQPUDZ]]
  ; CHECK-NEXT:   $x3 = COPY [[MFVRD]]
  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm, implicit $x3
entry:
  %conv = tail call i64 @llvm.experimental.constrained.fptoui.i64.f128(fp128 %m, metadata !"fpexcept.strict")
  ret i64 %conv
}

define zeroext i32 @q_to_u32(fp128 %m) #0 {
  ; CHECK-LABEL: name: q_to_u32
  ; CHECK: bb.0.entry:
  ; CHECK-NEXT:   liveins: $v2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vrrc = COPY $v2
  ; CHECK-NEXT:   [[XSCVQPUWZ:%[0-9]+]]:vrrc = XSCVQPUWZ [[COPY]]
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:vslrc = COPY [[XSCVQPUWZ]]
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:vfrc = COPY [[COPY1]].sub_64
  ; CHECK-NEXT:   [[MFVSRWZ:%[0-9]+]]:gprc = MFVSRWZ [[COPY2]]
  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:g8rc = IMPLICIT_DEF
  ; CHECK-NEXT:   [[INSERT_SUBREG:%[0-9]+]]:g8rc = INSERT_SUBREG [[DEF]], [[MFVSRWZ]], %subreg.sub_32
  ; CHECK-NEXT:   [[RLDICL:%[0-9]+]]:g8rc = RLDICL [[INSERT_SUBREG]], 0, 32
  ; CHECK-NEXT:   $x3 = COPY [[RLDICL]]
  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm, implicit $x3
entry:
  %conv = tail call i32 @llvm.experimental.constrained.fptoui.i32.f128(fp128 %m, metadata !"fpexcept.strict")
  ret i32 %conv
}

declare double @llvm.fabs.f64(double)

declare i32 @llvm.experimental.constrained.fptosi.i32.f128(fp128, metadata)
declare i64 @llvm.experimental.constrained.fptosi.i64.f128(fp128, metadata)
declare i64 @llvm.experimental.constrained.fptoui.i64.f128(fp128, metadata)
declare i32 @llvm.experimental.constrained.fptoui.i32.f128(fp128, metadata)
declare i32 @llvm.experimental.constrained.fptosi.i32.ppcf128(ppc_fp128, metadata)
declare i32 @llvm.experimental.constrained.fptoui.i32.ppcf128(ppc_fp128, metadata)

attributes #0 = { strictfp }