llvm/test/CodeGen/NVPTX/switch-loop-header.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -o - %s -passes="require<machine-loops>,require<live-vars>,phi-node-elimination" | FileCheck %s

--- |
  target datalayout = "e-p6:32:32-i64:64-i128:128-i256:256-v16:16-v32:32-n16:32:64"
  target triple = "nvptx64-unknown-nvidiacl"

  define void @func_26(i32 %BS_COND_16.0.BS_COND_16.0.BS_COND_16.0.BS_COND_16.0.) {
  entry:
    br label %for.cond

  for.cond:                                         ; preds = %BS_LABEL_1, %BS_LABEL_1, %entry
    %p_2218_0.1 = phi i32 [ 0, %entry ], [ %p_2218_0.3, %BS_LABEL_1 ], [ %p_2218_0.3, %BS_LABEL_1 ]
    br label %BS_LABEL_1

  BS_LABEL_2:                                       ; preds = %BS_LABEL_1
    %sub = or i32 %p_2218_0.3, 1
    br label %for.cond4

  for.cond4:                                        ; preds = %BS_LABEL_1, %BS_LABEL_2
    %p_2218_0.2 = phi i32 [ %BS_COND_16.0.BS_COND_16.0.BS_COND_16.0.BS_COND_16.0., %BS_LABEL_1 ], [ %sub, %BS_LABEL_2 ]
    br label %BS_LABEL_1

  BS_LABEL_1:                                       ; preds = %for.cond4, %for.cond
    %p_2218_0.3 = phi i32 [ %p_2218_0.2, %for.cond4 ], [ %p_2218_0.1, %for.cond ]
    switch i32 %BS_COND_16.0.BS_COND_16.0.BS_COND_16.0.BS_COND_16.0., label %unreachable [
      i32 0, label %for.cond4
      i32 4, label %BS_LABEL_2
      i32 1, label %for.cond
      i32 6, label %for.cond
    ]

  unreachable:                                      ; preds = %BS_LABEL_1
    call void asm sideeffect "exit;", ""()
    unreachable
  }
...
---
name:            func_26
alignment:       1
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
hasWinCFI:       false
noPhis:          false
isSSA:           true
noVRegs:         false
hasFakeUses:     false
callsEHReturn:   false
callsUnwindInit: false
hasEHContTarget: false
hasEHScopes:     false
hasEHFunclets:   false
isOutlined:      false
debugInstrRef:   false
failsVerification: false
tracksDebugUserValues: false
registers:
  - { id: 0, class: b32, preferred-register: '', flags: [  ] }
  - { id: 1, class: b32, preferred-register: '', flags: [  ] }
  - { id: 2, class: b32, preferred-register: '', flags: [  ] }
  - { id: 3, class: b32, preferred-register: '', flags: [  ] }
  - { id: 4, class: b32, preferred-register: '', flags: [  ] }
  - { id: 5, class: b32, preferred-register: '', flags: [  ] }
  - { id: 6, class: b32, preferred-register: '', flags: [  ] }
  - { id: 7, class: b1, preferred-register: '', flags: [  ] }
  - { id: 8, class: b32, preferred-register: '', flags: [  ] }
  - { id: 9, class: b1, preferred-register: '', flags: [  ] }
  - { id: 10, class: b32, preferred-register: '', flags: [  ] }
  - { id: 11, class: b1, preferred-register: '', flags: [  ] }
liveins:         []
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    1
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  functionContext: ''
  maxCallFrameSize: 4294967295
  cvBytesOfCalleeSavedRegisters: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  hasTailCall:     false
  isCalleeSavedInfoValid: false
  localFrameSize:  0
fixedStack:      []
stack:           []
entry_values:    []
callSites:       []
debugValueSubstitutions: []
constants:       []
machineFunctionInfo: {}
jumpTable:
  kind:            inline
  entries:
    - id:              0
      blocks:          [ '%bb.3', '%bb.1', '%bb.6', '%bb.6', '%bb.2', '%bb.6',
                         '%bb.1' ]
body:             |
  ; CHECK-LABEL: name: func_26
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   dead [[DEF:%[0-9]+]]:b32 = IMPLICIT_DEF
  ; CHECK-NEXT:   dead [[DEF1:%[0-9]+]]:b1 = IMPLICIT_DEF
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.4(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[DEF2:%[0-9]+]]:b32 = IMPLICIT_DEF
  ; CHECK-NEXT:   GOTO %bb.4
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3:
  ; CHECK-NEXT:   successors: %bb.4(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.4:
  ; CHECK-NEXT:   successors: %bb.6(0x00000000), %bb.5(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   CBranch undef [[DEF1]], %bb.6, 0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.5:
  ; CHECK-NEXT:   successors: %bb.3(0x3e000000), %bb.1(0x04000000), %bb.6(0x00000000), %bb.2(0x3e000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   BRX_IDX undef [[DEF]], %jump-table.0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.6:
  bb.0:
    successors: %bb.1(0x80000000)

    %10:b32 = IMPLICIT_DEF
    %11:b1 = IMPLICIT_DEF

  bb.1:
    successors: %bb.4(0x80000000)

    %0:b32 = PHI undef %10, %bb.0, undef %0, %bb.5
    GOTO %bb.4

  bb.2:
    successors: %bb.3(0x80000000)

  bb.3:
    successors: %bb.4(0x80000000)

  bb.4:
    successors: %bb.6(0x00000000), %bb.5(0x80000000)

    CBranch undef %11, %bb.6, 0

  bb.5:
    successors: %bb.3(0x3e000000), %bb.1(0x04000000), %bb.6(0x00000000), %bb.2(0x3e000000)

    BRX_IDX undef %10, %jump-table.0

  bb.6:
...