llvm/test/CodeGen/Mips/pr49200.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=mipsel-unknown-linux-musl-gnu < %s | FileCheck %s

; Check that in microMIPSr5 with a 64 bit fpu configuration, the following
; code can be compiled. This previously failed due to missing load/store
; patterns and instructions to handle the 64 bit FPU case for microMIPS.

%union.anon = type { { double, double } }

define dso_local void @foo() #0 {
; CHECK-LABEL: foo:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    addiusp -24
; CHECK-NEXT:    mtc1 $zero, $f0
; CHECK-NEXT:    mthc1 $zero, $f0
; CHECK-NEXT:    sdc1 $f0, 0($sp)
; CHECK-NEXT:    sdc1 $f0, 8($sp)
; CHECK-NEXT:    ldc1 $f0, 0($sp)
; CHECK-NEXT:    sdc1 $f0, 16($sp)
; CHECK-NEXT:    addiusp 24
; CHECK-NEXT:    jrc $ra
entry:
  %bleh = alloca double, align 8
  %.compoundliteral = alloca %union.anon, align 8
  %arrayinit.begin = getelementptr inbounds [2 x double], ptr %.compoundliteral, i32 0, i32 0
  store double 0.000000e+00, ptr %arrayinit.begin, align 8
  %arrayinit.element = getelementptr inbounds double, ptr %arrayinit.begin, i32 1
  store double 0.000000e+00, ptr %arrayinit.element, align 8
  %.compoundliteral.realp = getelementptr inbounds { double, double }, ptr %.compoundliteral, i32 0, i32 0
  %.compoundliteral.real = load double, ptr %.compoundliteral.realp, align 8
  store double %.compoundliteral.real, ptr %bleh, align 8
  ret void
}
attributes #0 = { noinline nounwind optnone "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="mips32r5" "target-features"="+dspr2,+fp64,+mips32r5,-noabicalls,+micromips" }