llvm/test/CodeGen/AVR/llround-conv.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=avr -mcpu=atmega328p | FileCheck %s

define signext i32 @testmsws(float %x) {
; CHECK-LABEL: testmsws:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    call llroundf
; CHECK-NEXT:    movw r22, r18
; CHECK-NEXT:    movw r24, r20
; CHECK-NEXT:    ret
entry:
  %0 = tail call i64 @llvm.llround.i64.f32(float %x)
  %conv = trunc i64 %0 to i32
  ret i32 %conv
}

define i64 @testmsxs(float %x) {
; CHECK-LABEL: testmsxs:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    call llroundf
; CHECK-NEXT:    ret
entry:
  %0 = tail call i64 @llvm.llround.i64.f32(float %x)
  ret i64 %0
}

define signext i32 @testmswd(double %x) {
; CHECK-LABEL: testmswd:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    call llround
; CHECK-NEXT:    movw r22, r18
; CHECK-NEXT:    movw r24, r20
; CHECK-NEXT:    ret
entry:
  %0 = tail call i64 @llvm.llround.i64.f64(double %x)
  %conv = trunc i64 %0 to i32
  ret i32 %conv
}

define i64 @testmsxd(double %x) {
; CHECK-LABEL: testmsxd:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    call llround
; CHECK-NEXT:    ret
entry:
  %0 = tail call i64 @llvm.llround.i64.f64(double %x)
  ret i64 %0
}

declare i64 @llvm.llround.i64.f32(float) nounwind readnone
declare i64 @llvm.llround.i64.f64(double) nounwind readnone