llvm/test/CodeGen/ARM/peephole-phi.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - %s -mtriple=armv7-- -verify-machineinstrs -run-pass=peephole-opt | FileCheck %s
#
# Make sure we do not crash on this input.
# Note that this input could in principle be optimized, but right now we don't
# have this case implemented so the output should simply be unchanged.

---
name: func0
tracksRegLiveness: true
body: |
  ; CHECK-LABEL: name: func0
  ; CHECK: bb.0:
  ; CHECK:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK:   Bcc %bb.2, 1 /* CC::ne */, undef $cpsr
  ; CHECK: bb.1:
  ; CHECK:   successors: %bb.3(0x80000000)
  ; CHECK:   [[DEF:%[0-9]+]]:dpr = IMPLICIT_DEF
  ; CHECK:   [[VMOVRRD:%[0-9]+]]:gpr, [[VMOVRRD1:%[0-9]+]]:gpr = VMOVRRD [[DEF]], 14 /* CC::al */, $noreg
  ; CHECK:   B %bb.3
  ; CHECK: bb.2:
  ; CHECK:   successors: %bb.3(0x80000000)
  ; CHECK:   [[DEF1:%[0-9]+]]:spr = IMPLICIT_DEF
  ; CHECK:   [[VMOVRS:%[0-9]+]]:gpr = VMOVRS [[DEF1]], 14 /* CC::al */, $noreg
  ; CHECK: bb.3:
  ; CHECK:   [[PHI:%[0-9]+]]:gpr = PHI [[VMOVRRD]], %bb.1, [[VMOVRS]], %bb.2
  ; CHECK:   [[VMOVSR:%[0-9]+]]:spr = VMOVSR [[PHI]], 14 /* CC::al */, $noreg
  bb.0:
    Bcc %bb.2, 1, undef $cpsr

  bb.1:
    %0:dpr = IMPLICIT_DEF
    %1:gpr, %2:gpr = VMOVRRD %0:dpr, 14, $noreg
    B %bb.3

  bb.2:
    %3:spr = IMPLICIT_DEF
    %4:gpr = VMOVRS %3:spr, 14, $noreg

  bb.3:
    %5:gpr = PHI %1, %bb.1, %4, %bb.2
    %6:spr = VMOVSR %5, 14, $noreg
...

---
name: func1
tracksRegLiveness: true
body: |
  ; CHECK-LABEL: name: func1
  ; CHECK: bb.0:
  ; CHECK:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK:   Bcc %bb.2, 1 /* CC::ne */, undef $cpsr
  ; CHECK: bb.1:
  ; CHECK:   successors: %bb.3(0x80000000)
  ; CHECK:   [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF
  ; CHECK:   [[VMOVRS:%[0-9]+]]:gpr = VMOVRS [[DEF]], 14 /* CC::al */, $noreg
  ; CHECK:   B %bb.3
  ; CHECK: bb.2:
  ; CHECK:   successors: %bb.3(0x80000000)
  ; CHECK:   [[DEF1:%[0-9]+]]:spr = IMPLICIT_DEF
  ; CHECK:   [[VMOVRS1:%[0-9]+]]:gpr = VMOVRS [[DEF1]], 14 /* CC::al */, $noreg
  ; CHECK: bb.3:
  ; CHECK:   [[PHI:%[0-9]+]]:spr = PHI [[DEF]], %bb.1, [[DEF1]], %bb.2
  ; CHECK:   [[PHI1:%[0-9]+]]:gpr = PHI [[VMOVRS]], %bb.1, [[VMOVRS1]], %bb.2
  ; CHECK:   [[COPY:%[0-9]+]]:spr = COPY [[PHI]]
  bb.0:
    Bcc %bb.2, 1, undef $cpsr

  bb.1:
    %1:spr = IMPLICIT_DEF
    %0:gpr = VMOVRS %1, 14, $noreg
    B %bb.3

  bb.2:
    %3:spr = IMPLICIT_DEF
    %2:gpr = VMOVRS %3:spr, 14, $noreg

  bb.3:
    %4:gpr = PHI %0, %bb.1, %2, %bb.2
    %5:spr = VMOVSR %4, 14, $noreg
...

# The current implementation doesn't perform any transformations if undef
# operands are involved.

---
name: func-undefops
tracksRegLiveness: true
body: |
  ; CHECK-LABEL: name: func-undefops
  ; CHECK: bb.0:
  ; CHECK:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK:   Bcc %bb.2, 1 /* CC::ne */, undef $cpsr
  ; CHECK: bb.1:
  ; CHECK:   successors: %bb.3(0x80000000)
  ; CHECK:   [[VMOVRS:%[0-9]+]]:gpr = VMOVRS undef %1:spr, 14 /* CC::al */, $noreg
  ; CHECK:   B %bb.3
  ; CHECK: bb.2:
  ; CHECK:   successors: %bb.3(0x80000000)
  ; CHECK:   [[VMOVRS1:%[0-9]+]]:gpr = VMOVRS undef %3:spr, 14 /* CC::al */, $noreg
  ; CHECK: bb.3:
  ; CHECK:   [[PHI:%[0-9]+]]:gpr = PHI [[VMOVRS]], %bb.1, [[VMOVRS1]], %bb.2
  ; CHECK:   [[VMOVSR:%[0-9]+]]:spr = VMOVSR [[PHI]], 14 /* CC::al */, $noreg
  bb.0:
    Bcc %bb.2, 1, undef $cpsr

  bb.1:
    %0:gpr = VMOVRS undef %1:spr, 14, $noreg
    B %bb.3

  bb.2:
    %2:gpr = VMOVRS undef %3:spr, 14, $noreg

  bb.3:
    %4:gpr = PHI %0, %bb.1, %2, %bb.2
    %5:spr = VMOVSR %4, 14, $noreg
...