llvm/test/CodeGen/AMDGPU/xor.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgpu6.01 < %s | FileCheck -enable-var-scope -check-prefixes=SI %s
; RUN: llc -mtriple=amdgpu8.02 < %s | FileCheck -enable-var-scope -check-prefixes=VI %s

define amdgpu_ps <2 x i32> @s_xor_v2i32(<2 x i32> inreg %num, <2 x i32> inreg %den) {
; SI-LABEL: s_xor_v2i32:
; SI:       ; %bb.0:
; SI-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]
; SI-NEXT:    ; return to shader part epilog
;
; VI-LABEL: s_xor_v2i32:
; VI:       ; %bb.0:
; VI-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]
; VI-NEXT:    ; return to shader part epilog
  %result = xor <2 x i32> %num, %den
  ret <2 x i32> %result
}

define <2 x i32> @v_xor_v2i32(<2 x i32> %num, <2 x i32> %den) {
; SI-LABEL: v_xor_v2i32:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_xor_b32_e32 v1, v1, v3
; SI-NEXT:    v_xor_b32_e32 v0, v0, v2
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: v_xor_v2i32:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_xor_b32_e32 v1, v1, v3
; VI-NEXT:    v_xor_b32_e32 v0, v0, v2
; VI-NEXT:    s_setpc_b64 s[30:31]
  %result = xor <2 x i32> %num, %den
  ret <2 x i32> %result
}

define <2 x i32> @xor_v2i32(<2 x i32> %in0, <2 x i32> %in1) {
; SI-LABEL: xor_v2i32:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_xor_b32_e32 v1, v1, v3
; SI-NEXT:    v_xor_b32_e32 v0, v0, v2
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: xor_v2i32:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_xor_b32_e32 v1, v1, v3
; VI-NEXT:    v_xor_b32_e32 v0, v0, v2
; VI-NEXT:    s_setpc_b64 s[30:31]
  %result = xor <2 x i32> %in0, %in1
  ret <2 x i32> %result
}

define <4 x i32> @xor_v4i32(<4 x i32> %in0, <4 x i32> %in1) {
; SI-LABEL: xor_v4i32:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_xor_b32_e32 v0, v0, v4
; SI-NEXT:    v_xor_b32_e32 v1, v1, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v6
; SI-NEXT:    v_xor_b32_e32 v3, v3, v7
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: xor_v4i32:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_xor_b32_e32 v0, v0, v4
; VI-NEXT:    v_xor_b32_e32 v1, v1, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v6
; VI-NEXT:    v_xor_b32_e32 v3, v3, v7
; VI-NEXT:    s_setpc_b64 s[30:31]
  %result = xor <4 x i32> %in0, %in1
  ret <4 x i32> %result
}

define float @xor_i1(float %in0, float %in1) {
; SI-LABEL: xor_i1:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cmp_le_f32_e32 vcc, 0, v0
; SI-NEXT:    v_cmp_le_f32_e64 s[4:5], 1.0, v1
; SI-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
; SI-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: xor_i1:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_le_f32_e32 vcc, 0, v0
; VI-NEXT:    v_cmp_le_f32_e64 s[4:5], 1.0, v1
; VI-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
; VI-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; VI-NEXT:    s_setpc_b64 s[30:31]
  %acmp = fcmp oge float %in0, 0.000000e+00
  %bcmp = fcmp oge float %in1, 1.000000e+00
  %xor = xor i1 %acmp, %bcmp
  %result = select i1 %xor, float %in0, float %in1
  ret float %result
}

define i1 @v_xor_i1(i1 %in0, i1 %in1) {
; SI-LABEL: v_xor_i1:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_xor_b32_e32 v0, v0, v1
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: v_xor_i1:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_xor_b32_e32 v0, v0, v1
; VI-NEXT:    s_setpc_b64 s[30:31]
  %xor = xor i1 %in0, %in1
  ret i1 %xor
}

define i32 @vector_xor_i32(i32 %in0, i32 %in1) {
; SI-LABEL: vector_xor_i32:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_xor_b32_e32 v0, v0, v1
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: vector_xor_i32:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_xor_b32_e32 v0, v0, v1
; VI-NEXT:    s_setpc_b64 s[30:31]
  %result = xor i32 %in0, %in1
  ret i32 %result
}

define amdgpu_kernel void @scalar_xor_i32(ptr addrspace(1) %out, i32 %a, i32 %b) {
; SI-LABEL: scalar_xor_i32:
; SI:       ; %bb.0:
; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    s_mov_b64 s[4:5], s[2:3]
; SI-NEXT:    s_xor_b32 s4, s4, s5
; SI-NEXT:    s_mov_b32 s3, 0xf000
; SI-NEXT:    s_mov_b32 s2, -1
; SI-NEXT:    v_mov_b32_e32 v0, s4
; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT:    s_endpgm
;
; VI-LABEL: scalar_xor_i32:
; VI:       ; %bb.0:
; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT:    s_waitcnt lgkmcnt(0)
; VI-NEXT:    s_xor_b32 s2, s2, s3
; VI-NEXT:    v_mov_b32_e32 v0, s0
; VI-NEXT:    v_mov_b32_e32 v1, s1
; VI-NEXT:    v_mov_b32_e32 v2, s2
; VI-NEXT:    flat_store_dword v[0:1], v2
; VI-NEXT:    s_endpgm
  %result = xor i32 %a, %b
  store i32 %result, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @scalar_not_i32(ptr addrspace(1) %out, i32 %a) {
; SI-LABEL: scalar_not_i32:
; SI:       ; %bb.0:
; SI-NEXT:    s_load_dword s6, s[4:5], 0xb
; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-NEXT:    s_mov_b32 s3, 0xf000
; SI-NEXT:    s_mov_b32 s2, -1
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    s_not_b32 s4, s6
; SI-NEXT:    v_mov_b32_e32 v0, s4
; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT:    s_endpgm
;
; VI-LABEL: scalar_not_i32:
; VI:       ; %bb.0:
; VI-NEXT:    s_load_dword s2, s[4:5], 0x2c
; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-NEXT:    s_waitcnt lgkmcnt(0)
; VI-NEXT:    s_not_b32 s2, s2
; VI-NEXT:    v_mov_b32_e32 v0, s0
; VI-NEXT:    v_mov_b32_e32 v1, s1
; VI-NEXT:    v_mov_b32_e32 v2, s2
; VI-NEXT:    flat_store_dword v[0:1], v2
; VI-NEXT:    s_endpgm
  %result = xor i32 %a, -1
  store i32 %result, ptr addrspace(1) %out
  ret void
}

define i32 @vector_not_i32(i32 %in0, i32 %in1) {
; SI-LABEL: vector_not_i32:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_not_b32_e32 v0, v0
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: vector_not_i32:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_not_b32_e32 v0, v0
; VI-NEXT:    s_setpc_b64 s[30:31]
  %result = xor i32 %in0, -1
  ret i32 %result
}

define i64 @vector_xor_i64(i64 %in0, i64 %in1) {
; SI-LABEL: vector_xor_i64:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_xor_b32_e32 v1, v1, v3
; SI-NEXT:    v_xor_b32_e32 v0, v0, v2
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: vector_xor_i64:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_xor_b32_e32 v1, v1, v3
; VI-NEXT:    v_xor_b32_e32 v0, v0, v2
; VI-NEXT:    s_setpc_b64 s[30:31]
  %result = xor i64 %in0, %in1
  ret i64 %result
}

define amdgpu_kernel void @scalar_xor_i64(ptr addrspace(1) %out, i64 %a, i64 %b) {
; SI-LABEL: scalar_xor_i64:
; SI:       ; %bb.0:
; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT:    s_load_dwordx2 s[8:9], s[4:5], 0xd
; SI-NEXT:    s_mov_b32 s7, 0xf000
; SI-NEXT:    s_mov_b32 s6, -1
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    s_mov_b32 s4, s0
; SI-NEXT:    s_mov_b32 s5, s1
; SI-NEXT:    s_xor_b64 s[0:1], s[2:3], s[8:9]
; SI-NEXT:    v_mov_b32_e32 v0, s0
; SI-NEXT:    v_mov_b32_e32 v1, s1
; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; SI-NEXT:    s_endpgm
;
; VI-LABEL: scalar_xor_i64:
; VI:       ; %bb.0:
; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x34
; VI-NEXT:    s_waitcnt lgkmcnt(0)
; VI-NEXT:    v_mov_b32_e32 v0, s0
; VI-NEXT:    v_mov_b32_e32 v1, s1
; VI-NEXT:    s_xor_b64 s[0:1], s[2:3], s[4:5]
; VI-NEXT:    v_mov_b32_e32 v3, s1
; VI-NEXT:    v_mov_b32_e32 v2, s0
; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
; VI-NEXT:    s_endpgm
  %result = xor i64 %a, %b
  store i64 %result, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @scalar_not_i64(ptr addrspace(1) %out, i64 %a) {
; SI-LABEL: scalar_not_i64:
; SI:       ; %bb.0:
; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT:    s_mov_b32 s7, 0xf000
; SI-NEXT:    s_mov_b32 s6, -1
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    s_mov_b32 s4, s0
; SI-NEXT:    s_mov_b32 s5, s1
; SI-NEXT:    s_not_b64 s[0:1], s[2:3]
; SI-NEXT:    v_mov_b32_e32 v0, s0
; SI-NEXT:    v_mov_b32_e32 v1, s1
; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; SI-NEXT:    s_endpgm
;
; VI-LABEL: scalar_not_i64:
; VI:       ; %bb.0:
; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT:    s_waitcnt lgkmcnt(0)
; VI-NEXT:    v_mov_b32_e32 v0, s0
; VI-NEXT:    v_mov_b32_e32 v1, s1
; VI-NEXT:    s_not_b64 s[0:1], s[2:3]
; VI-NEXT:    v_mov_b32_e32 v3, s1
; VI-NEXT:    v_mov_b32_e32 v2, s0
; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
; VI-NEXT:    s_endpgm
  %result = xor i64 %a, -1
  store i64 %result, ptr addrspace(1) %out
  ret void
}

define i64 @vector_not_i64(i64 %in0, i64 %in1) {
; SI-LABEL: vector_not_i64:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_not_b32_e32 v1, v1
; SI-NEXT:    v_not_b32_e32 v0, v0
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: vector_not_i64:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_not_b32_e32 v1, v1
; VI-NEXT:    v_not_b32_e32 v0, v0
; VI-NEXT:    s_setpc_b64 s[30:31]
  %result = xor i64 %in0, -1
  ret i64 %result
}

define amdgpu_kernel void @xor_cf(ptr addrspace(1) %out, ptr addrspace(1) %in, i64 %a, i64 %b) {
; SI-LABEL: xor_cf:
; SI:       ; %bb.0: ; %entry
; SI-NEXT:    s_load_dwordx8 s[0:7], s[4:5], 0x9
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    v_cmp_ne_u64_e64 vcc, s[4:5], 0
; SI-NEXT:    s_cbranch_vccz .LBB14_2
; SI-NEXT:  ; %bb.1: ; %else
; SI-NEXT:    s_mov_b32 s7, 0xf000
; SI-NEXT:    s_mov_b32 s6, 0
; SI-NEXT:    s_mov_b64 s[4:5], s[2:3]
; SI-NEXT:    v_lshlrev_b32_e32 v0, 3, v0
; SI-NEXT:    v_mov_b32_e32 v1, 0
; SI-NEXT:    buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64
; SI-NEXT:    s_branch .LBB14_3
; SI-NEXT:  .LBB14_2: ; %if
; SI-NEXT:    s_xor_b64 s[2:3], s[4:5], s[6:7]
; SI-NEXT:    v_mov_b32_e32 v0, s2
; SI-NEXT:    v_mov_b32_e32 v1, s3
; SI-NEXT:  .LBB14_3: ; %endif
; SI-NEXT:    s_mov_b32 s3, 0xf000
; SI-NEXT:    s_mov_b32 s2, -1
; SI-NEXT:    s_waitcnt vmcnt(0)
; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT:    s_endpgm
;
; VI-LABEL: xor_cf:
; VI:       ; %bb.0: ; %entry
; VI-NEXT:    s_load_dwordx8 s[0:7], s[4:5], 0x24
; VI-NEXT:    s_waitcnt lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u64 s[4:5], 0
; VI-NEXT:    s_cbranch_scc0 .LBB14_2
; VI-NEXT:  ; %bb.1: ; %else
; VI-NEXT:    v_lshlrev_b32_e32 v0, 3, v0
; VI-NEXT:    v_mov_b32_e32 v1, s3
; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v0
; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT:    flat_load_dwordx2 v[0:1], v[0:1]
; VI-NEXT:    s_branch .LBB14_3
; VI-NEXT:  .LBB14_2: ; %if
; VI-NEXT:    s_xor_b64 s[2:3], s[4:5], s[6:7]
; VI-NEXT:    v_mov_b32_e32 v0, s2
; VI-NEXT:    v_mov_b32_e32 v1, s3
; VI-NEXT:  .LBB14_3: ; %endif
; VI-NEXT:    v_mov_b32_e32 v2, s0
; VI-NEXT:    v_mov_b32_e32 v3, s1
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT:    s_endpgm
entry:
  %tid = call i32 @llvm.amdgcn.workitem.id.x()
  %0 = icmp eq i64 %a, 0
  br i1 %0, label %if, label %else

if:
  %1 = xor i64 %a, %b
  br label %endif

else:
  %in.gep = getelementptr inbounds i64, ptr addrspace(1) %in, i32 %tid
  %2 = load i64, ptr addrspace(1) %in.gep
  br label %endif

endif:
  %3 = phi i64 [%1, %if], [%2, %else]
  store i64 %3, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @scalar_xor_literal_i64(ptr addrspace(1) %out, [8 x i32], i64 %a) {
; SI-LABEL: scalar_xor_literal_i64:
; SI:       ; %bb.0:
; SI-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x13
; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-NEXT:    s_mov_b32 s3, 0xf000
; SI-NEXT:    s_mov_b32 s2, -1
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    s_xor_b32 s4, s7, 0xf237b
; SI-NEXT:    s_xor_b32 s5, s6, 0x3039
; SI-NEXT:    v_mov_b32_e32 v0, s5
; SI-NEXT:    v_mov_b32_e32 v1, s4
; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT:    s_endpgm
;
; VI-LABEL: scalar_xor_literal_i64:
; VI:       ; %bb.0:
; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x4c
; VI-NEXT:    s_load_dwordx2 s[2:3], s[4:5], 0x24
; VI-NEXT:    s_waitcnt lgkmcnt(0)
; VI-NEXT:    s_xor_b32 s1, s1, 0xf237b
; VI-NEXT:    s_xor_b32 s0, s0, 0x3039
; VI-NEXT:    v_mov_b32_e32 v0, s0
; VI-NEXT:    v_mov_b32_e32 v1, s1
; VI-NEXT:    v_mov_b32_e32 v2, s2
; VI-NEXT:    v_mov_b32_e32 v3, s3
; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT:    s_endpgm
  %or = xor i64 %a, 4261135838621753
  store i64 %or, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @scalar_xor_literal_multi_use_i64(ptr addrspace(1) %out, [8 x i32], i64 %a, i64 %b) {
; SI-LABEL: scalar_xor_literal_multi_use_i64:
; SI:       ; %bb.0:
; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x13
; SI-NEXT:    s_movk_i32 s8, 0x3039
; SI-NEXT:    s_mov_b32 s9, 0xf237b
; SI-NEXT:    s_mov_b32 s3, 0xf000
; SI-NEXT:    s_mov_b32 s2, -1
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    s_xor_b64 s[4:5], s[4:5], s[8:9]
; SI-NEXT:    v_mov_b32_e32 v0, s4
; SI-NEXT:    v_mov_b32_e32 v1, s5
; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT:    s_add_u32 s0, s6, 0x3039
; SI-NEXT:    s_addc_u32 s1, s7, 0xf237b
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_mov_b32_e32 v0, s0
; SI-NEXT:    v_mov_b32_e32 v1, s1
; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT:    s_waitcnt vmcnt(0)
; SI-NEXT:    s_endpgm
;
; VI-LABEL: scalar_xor_literal_multi_use_i64:
; VI:       ; %bb.0:
; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x4c
; VI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x24
; VI-NEXT:    s_movk_i32 s6, 0x3039
; VI-NEXT:    s_mov_b32 s7, 0xf237b
; VI-NEXT:    s_waitcnt lgkmcnt(0)
; VI-NEXT:    s_xor_b64 s[0:1], s[0:1], s[6:7]
; VI-NEXT:    v_mov_b32_e32 v3, s1
; VI-NEXT:    v_mov_b32_e32 v2, s0
; VI-NEXT:    s_add_u32 s0, s2, 0x3039
; VI-NEXT:    v_mov_b32_e32 v0, s4
; VI-NEXT:    v_mov_b32_e32 v1, s5
; VI-NEXT:    s_addc_u32 s1, s3, 0xf237b
; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
; VI-NEXT:    v_mov_b32_e32 v0, s0
; VI-NEXT:    v_mov_b32_e32 v1, s1
; VI-NEXT:    flat_store_dwordx2 v[0:1], v[0:1]
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    s_endpgm
  %or = xor i64 %a, 4261135838621753
  store i64 %or, ptr addrspace(1) %out

  %foo = add i64 %b, 4261135838621753
  store volatile i64 %foo, ptr addrspace(1) poison
  ret void
}

define amdgpu_kernel void @scalar_xor_inline_imm_i64(ptr addrspace(1) %out, [8 x i32], i64 %a) {
; SI-LABEL: scalar_xor_inline_imm_i64:
; SI:       ; %bb.0:
; SI-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x13
; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-NEXT:    s_mov_b32 s3, 0xf000
; SI-NEXT:    s_mov_b32 s2, -1
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    s_xor_b32 s4, s6, 63
; SI-NEXT:    v_mov_b32_e32 v0, s4
; SI-NEXT:    v_mov_b32_e32 v1, s7
; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT:    s_endpgm
;
; VI-LABEL: scalar_xor_inline_imm_i64:
; VI:       ; %bb.0:
; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x4c
; VI-NEXT:    s_load_dwordx2 s[2:3], s[4:5], 0x24
; VI-NEXT:    s_waitcnt lgkmcnt(0)
; VI-NEXT:    s_xor_b32 s0, s0, 63
; VI-NEXT:    v_mov_b32_e32 v1, s1
; VI-NEXT:    v_mov_b32_e32 v0, s0
; VI-NEXT:    v_mov_b32_e32 v2, s2
; VI-NEXT:    v_mov_b32_e32 v3, s3
; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT:    s_endpgm
  %or = xor i64 %a, 63
  store i64 %or, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @scalar_xor_neg_inline_imm_i64(ptr addrspace(1) %out, [8 x i32], i64 %a) {
; SI-LABEL: scalar_xor_neg_inline_imm_i64:
; SI:       ; %bb.0:
; SI-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x13
; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-NEXT:    s_mov_b32 s3, 0xf000
; SI-NEXT:    s_mov_b32 s2, -1
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    s_xor_b64 s[4:5], s[6:7], -8
; SI-NEXT:    v_mov_b32_e32 v0, s4
; SI-NEXT:    v_mov_b32_e32 v1, s5
; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT:    s_endpgm
;
; VI-LABEL: scalar_xor_neg_inline_imm_i64:
; VI:       ; %bb.0:
; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x4c
; VI-NEXT:    s_load_dwordx2 s[2:3], s[4:5], 0x24
; VI-NEXT:    s_waitcnt lgkmcnt(0)
; VI-NEXT:    s_xor_b64 s[0:1], s[0:1], -8
; VI-NEXT:    v_mov_b32_e32 v0, s2
; VI-NEXT:    v_mov_b32_e32 v1, s3
; VI-NEXT:    v_mov_b32_e32 v3, s1
; VI-NEXT:    v_mov_b32_e32 v2, s0
; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
; VI-NEXT:    s_endpgm

  %or = xor i64 %a, -8
  store i64 %or, ptr addrspace(1) %out
  ret void
}

define i64 @vector_xor_i64_neg_inline_imm(i64 %a) {
; SI-LABEL: vector_xor_i64_neg_inline_imm:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_xor_b32_e32 v1, -1, v1
; SI-NEXT:    v_xor_b32_e32 v0, -8, v0
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: vector_xor_i64_neg_inline_imm:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_xor_b32_e32 v1, -1, v1
; VI-NEXT:    v_xor_b32_e32 v0, -8, v0
; VI-NEXT:    s_setpc_b64 s[30:31]
  %or = xor i64 %a, -8
  ret i64 %or
}

define i64 @vector_xor_literal_i64(i64 %a) {
; SI-LABEL: vector_xor_literal_i64:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_xor_b32_e32 v0, 0xdf77987f, v0
; SI-NEXT:    v_xor_b32_e32 v1, 0x146f, v1
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: vector_xor_literal_i64:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_xor_b32_e32 v0, 0xdf77987f, v0
; VI-NEXT:    v_xor_b32_e32 v1, 0x146f, v1
; VI-NEXT:    s_setpc_b64 s[30:31]
  %or = xor i64 %a, 22470723082367
  ret i64 %or
}