llvm/test/CodeGen/AMDGPU/uniform-i16-load-bug.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgpu12.00 < %s | FileCheck -check-prefix=GFX12 %s

; Test bug where LowerLOAD converts uniform load i16 to: i16 = trunc (zextload i32).
; isTypeDesirableForOp did not block conversion back to load i16 creating an infinite loop;

define amdgpu_kernel void @test_uniform_i16_memcpy(ptr addrspace(4) align 2 %in, ptr addrspace(1) align 2 %out) {
; GFX12-LABEL: test_uniform_i16_memcpy:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    s_clause 0x2
; GFX12-NEXT:    s_load_u16 s4, s[0:1], 0x4
; GFX12-NEXT:    s_load_u16 s5, s[0:1], 0x2
; GFX12-NEXT:    s_load_u16 s0, s[0:1], 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
; GFX12-NEXT:    v_dual_mov_b32 v2, s5 :: v_dual_mov_b32 v3, s0
; GFX12-NEXT:    s_clause 0x2
; GFX12-NEXT:    global_store_b16 v0, v1, s[2:3] offset:4
; GFX12-NEXT:    global_store_b16 v0, v2, s[2:3] offset:2
; GFX12-NEXT:    global_store_b16 v0, v3, s[2:3]
; GFX12-NEXT:    s_endpgm
  call void @llvm.memcpy.p1.p4.i64(ptr addrspace(1) align 2 %out, ptr addrspace(4) align 2 %in, i64 6, i1 false)
  ret void
}