llvm/test/CodeGen/AMDGPU/twoaddr-insert-subreg-subrange.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=amdgpu9.42 -verify-coalescing -run-pass=liveintervals,two-address-instruction,register-coalescer -o - %s | FileCheck %s

# The subrange for the lanes above sub0 straddles sub0_sub1_sub2_sub3,
# so it is only partially redefined when the INSERT_SUBREG becomes a
# subregister COPY. The upper half of the tuple must survive.

---
name:            insert_subreg_straddling_subrange
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11

    ; CHECK-LABEL: name: insert_subreg_straddling_subrange
    ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:av_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
    ; CHECK-NEXT: [[COPY:%[0-9]+]].sub0_sub1_sub2_sub3:av_256 = COPY $vgpr8_vgpr9_vgpr10_vgpr11
    ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[COPY]]
    ; CHECK-NEXT: SI_RETURN implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
    %0:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
    %1:vreg_128 = COPY $vgpr8_vgpr9_vgpr10_vgpr11
    %2:vreg_256 = INSERT_SUBREG %0, %1, %subreg.sub0_sub1_sub2_sub3
    %3:vgpr_32 = COPY %2.sub0
    %4:vreg_256 = INSERT_SUBREG %2, %3, %subreg.sub0
    $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %4
    SI_RETURN implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
...