llvm/test/CodeGen/AMDGPU/trunc-store.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgpu6.01 < %s | FileCheck -check-prefixes=GCN,SI %s
; RUN: llc -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=GCN,VI %s

define amdgpu_kernel void @truncstore_arg_v16i32_to_v16i8(ptr addrspace(1) %out, <16 x i32> %in) {
; SI-LABEL: truncstore_arg_v16i32_to_v16i8:
; SI:       ; %bb.0:
; SI-NEXT:    s_load_dwordx16 s[8:23], s[4:5], 0x19
; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-NEXT:    s_mov_b32 s3, 0xf000
; SI-NEXT:    s_mov_b32 s2, -1
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    s_and_b32 s5, s22, 0xff
; SI-NEXT:    s_lshl_b32 s4, s23, 24
; SI-NEXT:    s_lshl_b32 s5, s5, 16
; SI-NEXT:    s_or_b32 s4, s4, s5
; SI-NEXT:    s_lshl_b32 s5, s21, 8
; SI-NEXT:    s_and_b32 s6, s20, 0xff
; SI-NEXT:    s_or_b32 s5, s6, s5
; SI-NEXT:    s_and_b32 s5, s5, 0xffff
; SI-NEXT:    s_and_b32 s6, s18, 0xff
; SI-NEXT:    s_or_b32 s4, s5, s4
; SI-NEXT:    s_lshl_b32 s5, s19, 24
; SI-NEXT:    s_lshl_b32 s6, s6, 16
; SI-NEXT:    s_or_b32 s5, s5, s6
; SI-NEXT:    s_lshl_b32 s6, s17, 8
; SI-NEXT:    s_and_b32 s7, s16, 0xff
; SI-NEXT:    s_or_b32 s6, s7, s6
; SI-NEXT:    s_and_b32 s6, s6, 0xffff
; SI-NEXT:    s_and_b32 s7, s14, 0xff
; SI-NEXT:    s_or_b32 s5, s6, s5
; SI-NEXT:    s_lshl_b32 s6, s15, 24
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_or_b32 s6, s6, s7
; SI-NEXT:    s_lshl_b32 s7, s13, 8
; SI-NEXT:    s_and_b32 s12, s12, 0xff
; SI-NEXT:    s_or_b32 s7, s12, s7
; SI-NEXT:    s_and_b32 s7, s7, 0xffff
; SI-NEXT:    s_and_b32 s10, s10, 0xff
; SI-NEXT:    s_lshl_b32 s9, s9, 8
; SI-NEXT:    s_and_b32 s8, s8, 0xff
; SI-NEXT:    s_or_b32 s6, s7, s6
; SI-NEXT:    s_lshl_b32 s7, s11, 24
; SI-NEXT:    s_lshl_b32 s10, s10, 16
; SI-NEXT:    s_or_b32 s8, s8, s9
; SI-NEXT:    s_or_b32 s7, s7, s10
; SI-NEXT:    s_and_b32 s8, s8, 0xffff
; SI-NEXT:    s_or_b32 s7, s8, s7
; SI-NEXT:    v_mov_b32_e32 v0, s7
; SI-NEXT:    v_mov_b32_e32 v1, s6
; SI-NEXT:    v_mov_b32_e32 v2, s5
; SI-NEXT:    v_mov_b32_e32 v3, s4
; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT:    s_endpgm
;
; VI-LABEL: truncstore_arg_v16i32_to_v16i8:
; VI:       ; %bb.0:
; VI-NEXT:    s_load_dwordx16 s[8:23], s[4:5], 0x64
; VI-NEXT:    v_mov_b32_e32 v0, 0xc0c0004
; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-NEXT:    s_waitcnt lgkmcnt(0)
; VI-NEXT:    v_mov_b32_e32 v2, s23
; VI-NEXT:    v_mov_b32_e32 v1, s21
; VI-NEXT:    v_perm_b32 v2, s22, v2, v0
; VI-NEXT:    v_perm_b32 v1, s20, v1, v0
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v3, v1, v2
; VI-NEXT:    v_mov_b32_e32 v2, s19
; VI-NEXT:    v_mov_b32_e32 v1, s17
; VI-NEXT:    v_perm_b32 v2, s18, v2, v0
; VI-NEXT:    v_perm_b32 v1, s16, v1, v0
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_mov_b32_e32 v4, s15
; VI-NEXT:    v_or_b32_e32 v2, v1, v2
; VI-NEXT:    v_mov_b32_e32 v1, s13
; VI-NEXT:    v_perm_b32 v4, s14, v4, v0
; VI-NEXT:    v_perm_b32 v1, s12, v1, v0
; VI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT:    v_or_b32_e32 v1, v1, v4
; VI-NEXT:    v_mov_b32_e32 v4, s9
; VI-NEXT:    v_mov_b32_e32 v5, s11
; VI-NEXT:    v_perm_b32 v4, s8, v4, v0
; VI-NEXT:    v_perm_b32 v0, s10, v5, v0
; VI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
; VI-NEXT:    v_or_b32_e32 v0, v4, v0
; VI-NEXT:    v_mov_b32_e32 v5, s1
; VI-NEXT:    v_mov_b32_e32 v4, s0
; VI-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT:    s_endpgm
  %trunc = trunc <16 x i32> %in to <16 x i8>
  store <16 x i8> %trunc, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @truncstore_arg_v16i64_to_v16i8(ptr addrspace(1) %out, <16 x i64> %in) {
; SI-LABEL: truncstore_arg_v16i64_to_v16i8:
; SI:       ; %bb.0:
; SI-NEXT:    s_load_dwordx16 s[16:31], s[4:5], 0x39
; SI-NEXT:    s_load_dwordx2 s[36:37], s[4:5], 0x9
; SI-NEXT:    s_load_dwordx16 s[0:15], s[4:5], 0x29
; SI-NEXT:    s_mov_b32 s39, 0xf000
; SI-NEXT:    s_mov_b32 s38, -1
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    s_and_b32 s3, s28, 0xff
; SI-NEXT:    s_lshl_b32 s1, s30, 24
; SI-NEXT:    s_lshl_b32 s3, s3, 16
; SI-NEXT:    s_or_b32 s1, s1, s3
; SI-NEXT:    s_lshl_b32 s3, s26, 8
; SI-NEXT:    s_and_b32 s5, s24, 0xff
; SI-NEXT:    s_or_b32 s3, s5, s3
; SI-NEXT:    s_and_b32 s3, s3, 0xffff
; SI-NEXT:    s_and_b32 s5, s20, 0xff
; SI-NEXT:    s_or_b32 s1, s3, s1
; SI-NEXT:    s_lshl_b32 s3, s22, 24
; SI-NEXT:    s_lshl_b32 s5, s5, 16
; SI-NEXT:    s_or_b32 s3, s3, s5
; SI-NEXT:    s_lshl_b32 s5, s18, 8
; SI-NEXT:    s_and_b32 s7, s16, 0xff
; SI-NEXT:    s_or_b32 s5, s7, s5
; SI-NEXT:    s_and_b32 s5, s5, 0xffff
; SI-NEXT:    s_and_b32 s7, s12, 0xff
; SI-NEXT:    s_or_b32 s3, s5, s3
; SI-NEXT:    s_lshl_b32 s5, s14, 24
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_or_b32 s5, s5, s7
; SI-NEXT:    s_lshl_b32 s7, s10, 8
; SI-NEXT:    s_and_b32 s8, s8, 0xff
; SI-NEXT:    s_and_b32 s4, s4, 0xff
; SI-NEXT:    s_lshl_b32 s2, s2, 8
; SI-NEXT:    s_and_b32 s0, s0, 0xff
; SI-NEXT:    s_or_b32 s7, s8, s7
; SI-NEXT:    s_lshl_b32 s6, s6, 24
; SI-NEXT:    s_lshl_b32 s4, s4, 16
; SI-NEXT:    s_or_b32 s0, s0, s2
; SI-NEXT:    s_and_b32 s7, s7, 0xffff
; SI-NEXT:    s_or_b32 s4, s6, s4
; SI-NEXT:    s_and_b32 s0, s0, 0xffff
; SI-NEXT:    s_or_b32 s5, s7, s5
; SI-NEXT:    s_or_b32 s0, s0, s4
; SI-NEXT:    v_mov_b32_e32 v0, s0
; SI-NEXT:    v_mov_b32_e32 v1, s5
; SI-NEXT:    v_mov_b32_e32 v2, s3
; SI-NEXT:    v_mov_b32_e32 v3, s1
; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[36:39], 0
; SI-NEXT:    s_endpgm
;
; VI-LABEL: truncstore_arg_v16i64_to_v16i8:
; VI:       ; %bb.0:
; VI-NEXT:    s_load_dwordx16 s[16:31], s[4:5], 0xe4
; VI-NEXT:    v_mov_b32_e32 v0, 0xc0c0004
; VI-NEXT:    s_load_dwordx2 s[34:35], s[4:5], 0x24
; VI-NEXT:    s_load_dwordx16 s[0:15], s[4:5], 0xa4
; VI-NEXT:    s_waitcnt lgkmcnt(0)
; VI-NEXT:    v_mov_b32_e32 v2, s30
; VI-NEXT:    v_mov_b32_e32 v1, s26
; VI-NEXT:    v_perm_b32 v2, s28, v2, v0
; VI-NEXT:    v_perm_b32 v1, s24, v1, v0
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v3, v1, v2
; VI-NEXT:    v_mov_b32_e32 v2, s22
; VI-NEXT:    v_mov_b32_e32 v1, s18
; VI-NEXT:    v_perm_b32 v2, s20, v2, v0
; VI-NEXT:    v_perm_b32 v1, s16, v1, v0
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_mov_b32_e32 v4, s14
; VI-NEXT:    v_or_b32_e32 v2, v1, v2
; VI-NEXT:    v_mov_b32_e32 v1, s10
; VI-NEXT:    v_perm_b32 v4, s12, v4, v0
; VI-NEXT:    v_perm_b32 v1, s8, v1, v0
; VI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT:    v_or_b32_e32 v1, v1, v4
; VI-NEXT:    v_mov_b32_e32 v4, s2
; VI-NEXT:    v_mov_b32_e32 v5, s6
; VI-NEXT:    v_perm_b32 v4, s0, v4, v0
; VI-NEXT:    v_perm_b32 v0, s4, v5, v0
; VI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
; VI-NEXT:    v_or_b32_e32 v0, v4, v0
; VI-NEXT:    v_mov_b32_e32 v4, s34
; VI-NEXT:    v_mov_b32_e32 v5, s35
; VI-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT:    s_endpgm
  %trunc = trunc <16 x i64> %in to <16 x i8>
  store <16 x i8> %trunc, ptr addrspace(1) %out
  ret void
}

define void @truncstore_v5i32_to_v5i1(ptr addrspace(1) %out, <5 x i32> %val) {
; SI-LABEL: truncstore_v5i32_to_v5i1:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_and_b32_e32 v3, 1, v3
; SI-NEXT:    v_and_b32_e32 v2, 1, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 1, v3
; SI-NEXT:    v_or_b32_e32 v2, v2, v3
; SI-NEXT:    v_and_b32_e32 v3, 1, v4
; SI-NEXT:    v_lshlrev_b32_e32 v3, 2, v3
; SI-NEXT:    v_or_b32_e32 v2, v2, v3
; SI-NEXT:    v_and_b32_e32 v3, 1, v5
; SI-NEXT:    v_lshlrev_b32_e32 v3, 3, v3
; SI-NEXT:    v_or_b32_e32 v2, v2, v3
; SI-NEXT:    v_lshlrev_b32_e32 v3, 4, v6
; SI-NEXT:    s_mov_b32 s6, 0
; SI-NEXT:    v_or_b32_e32 v2, v2, v3
; SI-NEXT:    s_mov_b32 s7, 0xf000
; SI-NEXT:    s_mov_b32 s4, s6
; SI-NEXT:    s_mov_b32 s5, s6
; SI-NEXT:    v_and_b32_e32 v2, 31, v2
; SI-NEXT:    buffer_store_byte v2, v[0:1], s[4:7], 0 addr64
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: truncstore_v5i32_to_v5i1:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_and_b32_e32 v3, 1, v3
; VI-NEXT:    v_and_b32_e32 v2, 1, v2
; VI-NEXT:    v_lshlrev_b16_e32 v3, 1, v3
; VI-NEXT:    v_or_b32_e32 v2, v2, v3
; VI-NEXT:    v_and_b32_e32 v3, 1, v4
; VI-NEXT:    v_lshlrev_b16_e32 v3, 2, v3
; VI-NEXT:    v_or_b32_e32 v2, v2, v3
; VI-NEXT:    v_and_b32_e32 v3, 1, v5
; VI-NEXT:    v_lshlrev_b16_e32 v3, 3, v3
; VI-NEXT:    v_or_b32_e32 v2, v2, v3
; VI-NEXT:    v_lshlrev_b16_e32 v3, 4, v6
; VI-NEXT:    v_or_b32_e32 v2, v2, v3
; VI-NEXT:    v_and_b32_e32 v2, 31, v2
; VI-NEXT:    flat_store_byte v[0:1], v2
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    s_setpc_b64 s[30:31]
  %trunc = trunc <5 x i32> %val to <5 x i1>
  store <5 x i1> %trunc, ptr addrspace(1) %out
  ret void
}

define void @truncstore_v5i32_to_v5i8(ptr addrspace(1) %out, <5 x i32> %val) {
; SI-LABEL: truncstore_v5i32_to_v5i8:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_and_b32_e32 v4, 0xff, v4
; SI-NEXT:    v_lshlrev_b32_e32 v3, 8, v3
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v2
; SI-NEXT:    s_mov_b32 s6, 0
; SI-NEXT:    v_lshlrev_b32_e32 v5, 24, v5
; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT:    v_or_b32_e32 v2, v2, v3
; SI-NEXT:    s_mov_b32 s7, 0xf000
; SI-NEXT:    s_mov_b32 s4, s6
; SI-NEXT:    s_mov_b32 s5, s6
; SI-NEXT:    v_or_b32_e32 v4, v5, v4
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    v_or_b32_e32 v2, v2, v4
; SI-NEXT:    buffer_store_byte v6, v[0:1], s[4:7], 0 addr64 offset:4
; SI-NEXT:    buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: truncstore_v5i32_to_v5i8:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_mov_b32 s4, 0xc0c0004
; VI-NEXT:    v_perm_b32 v2, v2, v3, s4
; VI-NEXT:    v_perm_b32 v3, v4, v5, s4
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_e32 v4, v2, v3
; VI-NEXT:    v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
; VI-NEXT:    flat_store_byte v[2:3], v6
; VI-NEXT:    flat_store_dword v[0:1], v4
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    s_setpc_b64 s[30:31]
  %trunc = trunc <5 x i32> %val to <5 x i8>
  store <5 x i8> %trunc, ptr addrspace(1) %out
  ret void
}

define void @truncstore_v6i32_to_v6i1(ptr addrspace(1) %out, <6 x i32> %val) {
; SI-LABEL: truncstore_v6i32_to_v6i1:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_and_b32_e32 v3, 1, v3
; SI-NEXT:    v_and_b32_e32 v2, 1, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 1, v3
; SI-NEXT:    v_or_b32_e32 v2, v2, v3
; SI-NEXT:    v_and_b32_e32 v3, 1, v4
; SI-NEXT:    v_lshlrev_b32_e32 v3, 2, v3
; SI-NEXT:    v_or_b32_e32 v2, v2, v3
; SI-NEXT:    v_and_b32_e32 v3, 1, v5
; SI-NEXT:    v_lshlrev_b32_e32 v3, 3, v3
; SI-NEXT:    v_or_b32_e32 v2, v2, v3
; SI-NEXT:    v_and_b32_e32 v3, 1, v6
; SI-NEXT:    v_lshlrev_b32_e32 v3, 4, v3
; SI-NEXT:    v_or_b32_e32 v2, v2, v3
; SI-NEXT:    v_lshlrev_b32_e32 v3, 5, v7
; SI-NEXT:    s_mov_b32 s6, 0
; SI-NEXT:    v_or_b32_e32 v2, v2, v3
; SI-NEXT:    s_mov_b32 s7, 0xf000
; SI-NEXT:    s_mov_b32 s4, s6
; SI-NEXT:    s_mov_b32 s5, s6
; SI-NEXT:    v_and_b32_e32 v2, 63, v2
; SI-NEXT:    buffer_store_byte v2, v[0:1], s[4:7], 0 addr64
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: truncstore_v6i32_to_v6i1:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_and_b32_e32 v3, 1, v3
; VI-NEXT:    v_and_b32_e32 v2, 1, v2
; VI-NEXT:    v_lshlrev_b16_e32 v3, 1, v3
; VI-NEXT:    v_or_b32_e32 v2, v2, v3
; VI-NEXT:    v_and_b32_e32 v3, 1, v4
; VI-NEXT:    v_lshlrev_b16_e32 v3, 2, v3
; VI-NEXT:    v_or_b32_e32 v2, v2, v3
; VI-NEXT:    v_and_b32_e32 v3, 1, v5
; VI-NEXT:    v_lshlrev_b16_e32 v3, 3, v3
; VI-NEXT:    v_or_b32_e32 v2, v2, v3
; VI-NEXT:    v_and_b32_e32 v3, 1, v6
; VI-NEXT:    v_lshlrev_b16_e32 v3, 4, v3
; VI-NEXT:    v_or_b32_e32 v2, v2, v3
; VI-NEXT:    v_lshlrev_b16_e32 v3, 5, v7
; VI-NEXT:    v_or_b32_e32 v2, v2, v3
; VI-NEXT:    v_and_b32_e32 v2, 63, v2
; VI-NEXT:    flat_store_byte v[0:1], v2
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    s_setpc_b64 s[30:31]
  %trunc = trunc <6 x i32> %val to <6 x i1>
  store <6 x i1> %trunc, ptr addrspace(1) %out
  ret void
}

define void @truncstore_v6i32_to_v6i8(ptr addrspace(1) %out, <6 x i32> %val) {
; SI-LABEL: truncstore_v6i32_to_v6i8:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_and_b32_e32 v4, 0xff, v4
; SI-NEXT:    v_lshlrev_b32_e32 v3, 8, v3
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v2
; SI-NEXT:    v_lshlrev_b32_e32 v5, 24, v5
; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT:    v_or_b32_e32 v2, v2, v3
; SI-NEXT:    v_or_b32_e32 v4, v5, v4
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    s_mov_b32 s6, 0
; SI-NEXT:    v_or_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshlrev_b32_e32 v3, 8, v7
; SI-NEXT:    v_and_b32_e32 v4, 0xff, v6
; SI-NEXT:    s_mov_b32 s7, 0xf000
; SI-NEXT:    s_mov_b32 s4, s6
; SI-NEXT:    s_mov_b32 s5, s6
; SI-NEXT:    v_or_b32_e32 v3, v4, v3
; SI-NEXT:    buffer_store_short v3, v[0:1], s[4:7], 0 addr64 offset:4
; SI-NEXT:    buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: truncstore_v6i32_to_v6i8:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_mov_b32 s4, 0xc0c0004
; VI-NEXT:    v_perm_b32 v2, v2, v3, s4
; VI-NEXT:    v_perm_b32 v3, v4, v5, s4
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_e32 v4, v2, v3
; VI-NEXT:    v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT:    v_perm_b32 v5, v6, v7, s4
; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
; VI-NEXT:    flat_store_short v[2:3], v5
; VI-NEXT:    flat_store_dword v[0:1], v4
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    s_setpc_b64 s[30:31]
  %trunc = trunc <6 x i32> %val to <6 x i8>
  store <6 x i8> %trunc, ptr addrspace(1) %out
  ret void
}

define void @truncstore_v6i32_to_v6i16(ptr addrspace(1) %out, <6 x i32> %val) {
; SI-LABEL: truncstore_v6i32_to_v6i16:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    s_mov_b32 s6, 0
; SI-NEXT:    v_or_b32_e32 v4, v4, v5
; SI-NEXT:    v_or_b32_e32 v3, v2, v3
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v7
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v6
; SI-NEXT:    s_mov_b32 s7, 0xf000
; SI-NEXT:    s_mov_b32 s4, s6
; SI-NEXT:    s_mov_b32 s5, s6
; SI-NEXT:    v_or_b32_e32 v2, v5, v2
; SI-NEXT:    buffer_store_dword v2, v[0:1], s[4:7], 0 addr64 offset:8
; SI-NEXT:    buffer_store_dwordx2 v[3:4], v[0:1], s[4:7], 0 addr64
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: truncstore_v6i32_to_v6i16:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_mov_b32 s4, 0x1000504
; VI-NEXT:    v_perm_b32 v6, v6, v7, s4
; VI-NEXT:    v_perm_b32 v5, v4, v5, s4
; VI-NEXT:    v_perm_b32 v4, v2, v3, s4
; VI-NEXT:    flat_store_dwordx3 v[0:1], v[4:6]
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    s_setpc_b64 s[30:31]
  %trunc = trunc <6 x i32> %val to <6 x i16>
  store <6 x i16> %trunc, ptr addrspace(1) %out
  ret void
}

define void @global_fp_truncstore_v6f32_to_v6bf16(ptr addrspace(1) %ptr, <6 x float> %src) {
; SI-LABEL: global_fp_truncstore_v6f32_to_v6bf16:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_mul_f32_e32 v3, 1.0, v3
; SI-NEXT:    v_mul_f32_e32 v5, 1.0, v5
; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_mul_f32_e32 v2, 1.0, v2
; SI-NEXT:    v_lshrrev_b32_e32 v5, 16, v5
; SI-NEXT:    v_mul_f32_e32 v4, 1.0, v4
; SI-NEXT:    v_alignbit_b32 v3, v3, v2, 16
; SI-NEXT:    v_mul_f32_e32 v2, 1.0, v7
; SI-NEXT:    s_mov_b32 s6, 0
; SI-NEXT:    v_alignbit_b32 v4, v5, v4, 16
; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_mul_f32_e32 v5, 1.0, v6
; SI-NEXT:    s_mov_b32 s7, 0xf000
; SI-NEXT:    s_mov_b32 s4, s6
; SI-NEXT:    s_mov_b32 s5, s6
; SI-NEXT:    v_alignbit_b32 v2, v2, v5, 16
; SI-NEXT:    buffer_store_dword v2, v[0:1], s[4:7], 0 addr64 offset:8
; SI-NEXT:    buffer_store_dwordx2 v[3:4], v[0:1], s[4:7], 0 addr64
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: global_fp_truncstore_v6f32_to_v6bf16:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_bfe_u32 v9, v6, 16, 1
; VI-NEXT:    v_add_u32_e32 v9, vcc, v9, v6
; VI-NEXT:    v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT:    v_or_b32_e32 v8, 0x400000, v6
; VI-NEXT:    v_cmp_u_f32_e32 vcc, v6, v6
; VI-NEXT:    v_cndmask_b32_e32 v6, v9, v8, vcc
; VI-NEXT:    v_bfe_u32 v9, v7, 16, 1
; VI-NEXT:    v_add_u32_e32 v9, vcc, v9, v7
; VI-NEXT:    v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT:    v_or_b32_e32 v8, 0x400000, v7
; VI-NEXT:    v_cmp_u_f32_e32 vcc, v7, v7
; VI-NEXT:    v_cndmask_b32_e32 v7, v9, v8, vcc
; VI-NEXT:    v_bfe_u32 v8, v4, 16, 1
; VI-NEXT:    v_add_u32_e32 v8, vcc, v8, v4
; VI-NEXT:    v_lshrrev_b32_e32 v7, 16, v7
; VI-NEXT:    v_add_u32_e32 v8, vcc, 0x7fff, v8
; VI-NEXT:    v_alignbit_b32 v6, v7, v6, 16
; VI-NEXT:    v_or_b32_e32 v7, 0x400000, v4
; VI-NEXT:    v_cmp_u_f32_e32 vcc, v4, v4
; VI-NEXT:    v_cndmask_b32_e32 v4, v8, v7, vcc
; VI-NEXT:    v_bfe_u32 v8, v5, 16, 1
; VI-NEXT:    v_add_u32_e32 v8, vcc, v8, v5
; VI-NEXT:    v_add_u32_e32 v8, vcc, 0x7fff, v8
; VI-NEXT:    v_or_b32_e32 v7, 0x400000, v5
; VI-NEXT:    v_cmp_u_f32_e32 vcc, v5, v5
; VI-NEXT:    v_cndmask_b32_e32 v5, v8, v7, vcc
; VI-NEXT:    v_bfe_u32 v7, v2, 16, 1
; VI-NEXT:    v_add_u32_e32 v7, vcc, v7, v2
; VI-NEXT:    v_lshrrev_b32_e32 v5, 16, v5
; VI-NEXT:    v_add_u32_e32 v7, vcc, 0x7fff, v7
; VI-NEXT:    v_alignbit_b32 v5, v5, v4, 16
; VI-NEXT:    v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT:    v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT:    v_cndmask_b32_e32 v2, v7, v4, vcc
; VI-NEXT:    v_bfe_u32 v7, v3, 16, 1
; VI-NEXT:    v_add_u32_e32 v7, vcc, v7, v3
; VI-NEXT:    v_add_u32_e32 v7, vcc, 0x7fff, v7
; VI-NEXT:    v_or_b32_e32 v4, 0x400000, v3
; VI-NEXT:    v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT:    v_cndmask_b32_e32 v3, v7, v4, vcc
; VI-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_alignbit_b32 v4, v3, v2, 16
; VI-NEXT:    flat_store_dwordx3 v[0:1], v[4:6]
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    s_setpc_b64 s[30:31]
  %trunc = fptrunc <6 x float> %src to <6 x bfloat>
  store <6 x bfloat> %trunc, ptr addrspace(1) %ptr
  ret void
}


define void @global_fp_truncstore_v6f32_to_v6f16(ptr addrspace(1) %ptr, <6 x float> %src) {
; SI-LABEL: global_fp_truncstore_v6f32_to_v6f16:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cvt_f16_f32_e32 v5, v5
; SI-NEXT:    v_cvt_f16_f32_e32 v4, v4
; SI-NEXT:    v_cvt_f16_f32_e32 v3, v3
; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT:    v_or_b32_e32 v4, v4, v5
; SI-NEXT:    v_cvt_f16_f32_e32 v5, v7
; SI-NEXT:    v_cvt_f16_f32_e32 v6, v6
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    s_mov_b32 s6, 0
; SI-NEXT:    v_or_b32_e32 v3, v2, v3
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v5
; SI-NEXT:    s_mov_b32 s7, 0xf000
; SI-NEXT:    s_mov_b32 s4, s6
; SI-NEXT:    s_mov_b32 s5, s6
; SI-NEXT:    v_or_b32_e32 v2, v6, v2
; SI-NEXT:    buffer_store_dword v2, v[0:1], s[4:7], 0 addr64 offset:8
; SI-NEXT:    buffer_store_dwordx2 v[3:4], v[0:1], s[4:7], 0 addr64
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: global_fp_truncstore_v6f32_to_v6f16:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cvt_f16_f32_sdwa v7, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
; VI-NEXT:    v_cvt_f16_f32_e32 v6, v6
; VI-NEXT:    v_cvt_f16_f32_sdwa v5, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
; VI-NEXT:    v_cvt_f16_f32_e32 v8, v4
; VI-NEXT:    v_cvt_f16_f32_sdwa v9, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
; VI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; VI-NEXT:    v_or_b32_e32 v4, v6, v7
; VI-NEXT:    v_or_b32_e32 v3, v8, v5
; VI-NEXT:    v_or_b32_e32 v2, v2, v9
; VI-NEXT:    flat_store_dwordx3 v[0:1], v[2:4]
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    s_setpc_b64 s[30:31]
  %trunc = fptrunc <6 x float> %src to <6 x half>
  store <6 x half> %trunc, ptr addrspace(1) %ptr
  ret void
}

;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GCN: {{.*}}