llvm/test/CodeGen/AMDGPU/trunc-bitcast-vector.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -enable-var-scope -check-prefixes=SI %s
; RUN: llc -mtriple=amdgpu8.02 < %s | FileCheck -enable-var-scope -check-prefixes=VI %s

define i32 @trunc_i64_bitcast_v2i32(<2 x i32> %in) {
; SI-LABEL: trunc_i64_bitcast_v2i32:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: trunc_i64_bitcast_v2i32:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_setpc_b64 s[30:31]
  %bc = bitcast <2 x i32> %in to i64
  %trunc = trunc i64 %bc to i32
  ret i32 %trunc
}

define i32 @trunc_i96_bitcast_v3i32(<3 x i32> %in) {
; SI-LABEL: trunc_i96_bitcast_v3i32:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: trunc_i96_bitcast_v3i32:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_setpc_b64 s[30:31]
  %bc = bitcast <3 x i32> %in to i96
  %trunc = trunc i96 %bc to i32
  ret i32 %trunc
}

define i32 @trunc_i128_bitcast_v4i32(<4 x i32> %in) {
; SI-LABEL: trunc_i128_bitcast_v4i32:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: trunc_i128_bitcast_v4i32:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_setpc_b64 s[30:31]
  %bc = bitcast <4 x i32> %in to i128
  %trunc = trunc i128 %bc to i32
  ret i32 %trunc
}

; Don't want load width reduced in this case.
define i16 @trunc_i16_bitcast_v2i16(<2 x i16> %in) {
; SI-LABEL: trunc_i16_bitcast_v2i16:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: trunc_i16_bitcast_v2i16:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_setpc_b64 s[30:31]
  %bc = bitcast <2 x i16> %in to i32
  %trunc = trunc i32 %bc to i16
  ret i16 %trunc
}

; FIXME We need to teach the dagcombiner to reduce load width for:
;   t21: v2i32,ch = load<LD8[%in(addrspace=1)]> t12, t10, undef:i64
;        t23: i64 = bitcast t21
;      t30: i16 = truncate t23
define i16 @trunc_i16_bitcast_v4i16(<4 x i16> %in) {
; SI-LABEL: trunc_i16_bitcast_v4i16:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: trunc_i16_bitcast_v4i16:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_setpc_b64 s[30:31]
  %bc = bitcast <4 x i16> %in to i64
  %trunc = trunc i64 %bc to i16
  ret i16 %trunc
}

; FIXME: Consistently shrink or not here
define i8 @trunc_i8_bitcast_v2i8(<2 x i8> %in) {
; SI-LABEL: trunc_i8_bitcast_v2i8:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_lshlrev_b32_e32 v1, 8, v1
; SI-NEXT:    v_and_b32_e32 v0, 0xff, v0
; SI-NEXT:    v_or_b32_e32 v0, v0, v1
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: trunc_i8_bitcast_v2i8:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v1
; VI-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT:    s_setpc_b64 s[30:31]
  %bc = bitcast <2 x i8> %in to i16
  %trunc = trunc i16 %bc to i8
  ret i8 %trunc
}

define i8 @trunc_i32_bitcast_v4i8(<4 x i8> %in) {
; SI-LABEL: trunc_i32_bitcast_v4i8:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v2
; SI-NEXT:    v_lshlrev_b32_e32 v1, 8, v1
; SI-NEXT:    v_and_b32_e32 v0, 0xff, v0
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v3
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_or_b32_e32 v0, v0, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_or_b32_e32 v0, v0, v2
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: trunc_i32_bitcast_v4i8:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_mov_b32 s4, 0xc0c0004
; VI-NEXT:    v_perm_b32 v0, v0, v1, s4
; VI-NEXT:    s_setpc_b64 s[30:31]
  %bc = bitcast <4 x i8> %in to i32
  %trunc = trunc i32 %bc to i8
  ret i8 %trunc
}

define i8 @trunc_i24_bitcast_v3i8(<3 x i8> %in) {
; SI-LABEL: trunc_i24_bitcast_v3i8:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_lshlrev_b32_e32 v1, 8, v1
; SI-NEXT:    v_and_b32_e32 v0, 0xff, v0
; SI-NEXT:    v_or_b32_e32 v0, v0, v1
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v2
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT:    v_or_b32_e32 v0, v0, v1
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: trunc_i24_bitcast_v3i8:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_mov_b32 s4, 0xc0c0004
; VI-NEXT:    v_perm_b32 v0, v0, v1, s4
; VI-NEXT:    s_setpc_b64 s[30:31]
  %bc = bitcast <3 x i8> %in to i24
  %trunc = trunc i24 %bc to i8
  ret i8 %trunc
}