llvm/test/CodeGen/AMDGPU/subreg-implicit-def.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6

# Ensure processing an IMPLICIT_DEF of a physreg handles subreg definitions
# and super-reg uses correctly.


# RUN: llc -mtriple=amdgpu8.02  -run-pass process-implicit-defs -asm-verbose=0 -verify-machineinstrs %s -o - | FileCheck %s

# Must not add undef to use of implicit-def because def is partially redefined.
---
name: impdef_subreg_def
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: impdef_subreg_def
    ; CHECK: $sgpr0_sgpr1 = IMPLICIT_DEF
    ; CHECK-NEXT: $sgpr0 = S_MOV_B32 0
    ; CHECK-NEXT: $sgpr2_sgpr3 = COPY $sgpr0_sgpr1
    ; CHECK-NEXT: S_ENDPGM 0
    $sgpr0_sgpr1 = IMPLICIT_DEF
    $sgpr0 = S_MOV_B32 0
    $sgpr2_sgpr3 = COPY $sgpr0_sgpr1
    S_ENDPGM 0
...

# Must not add undef to use of implicit-def because use is larger than implicit definition.
---
name: impdef_superreg_use
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: impdef_superreg_use
    ; CHECK: $sgpr0 = IMPLICIT_DEF
    ; CHECK-NEXT: $sgpr1 = S_MOV_B32 0
    ; CHECK-NEXT: $sgpr2_sgpr3 = COPY $sgpr0_sgpr1
    ; CHECK-NEXT: S_ENDPGM 0
    $sgpr0 = IMPLICIT_DEF
    $sgpr1 = S_MOV_B32 0
    $sgpr2_sgpr3 = COPY $sgpr0_sgpr1
    S_ENDPGM 0
...