llvm/test/CodeGen/AMDGPU/rsq.f32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=amdgpu6.00 -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=GCN-DAZ,GCN-DAZ-UNSAFE,SI-DAZ-UNSAFE %s
; RUN: llc -mtriple=amdgpu6.00 -denormal-fp-math-f32=ieee < %s          | FileCheck -check-prefixes=GCN-IEEE,GCN-IEEE-UNSAFE,SI-IEEE-UNSAFE %s


; RUN: llc -mtriple=amdgpu7.01 -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=GCN-DAZ,GCN-DAZ-UNSAFE,CI-DAZ-UNSAFE %s
; RUN: llc -mtriple=amdgpu7.01 -denormal-fp-math-f32=ieee < %s          | FileCheck -check-prefixes=GCN-IEEE,GCN-IEEE-UNSAFE,CI-IEEE-UNSAFE %s


declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
declare float @llvm.sqrt.f32(float) nounwind readnone
declare <2 x float> @llvm.sqrt.v2f32(<2 x float>) nounwind readnone

define float @rsq_f32(float %in) {
; GCN-DAZ-LABEL: rsq_f32:
; GCN-DAZ:       ; %bb.0:
; GCN-DAZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-DAZ-NEXT:    v_rsq_f32_e32 v0, v0
; GCN-DAZ-NEXT:    s_setpc_b64 s[30:31]
;
; GCN-IEEE-LABEL: rsq_f32:
; GCN-IEEE:       ; %bb.0:
; GCN-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IEEE-NEXT:    v_rsq_f32_e32 v0, v0
; GCN-IEEE-NEXT:    s_setpc_b64 s[30:31]
; GCN-UNSAFE-LABEL: rsq_f32:
; GCN-UNSAFE:       ; %bb.0:
; GCN-UNSAFE-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-UNSAFE-NEXT:    s_mov_b32 s7, 0xf000
; GCN-UNSAFE-NEXT:    s_mov_b32 s6, -1
; GCN-UNSAFE-NEXT:    s_mov_b32 s10, s6
; GCN-UNSAFE-NEXT:    s_mov_b32 s11, s7
; GCN-UNSAFE-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-UNSAFE-NEXT:    s_mov_b32 s8, s2
; GCN-UNSAFE-NEXT:    s_mov_b32 s9, s3
; GCN-UNSAFE-NEXT:    buffer_load_dword v0, off, s[8:11], 0
; GCN-UNSAFE-NEXT:    s_mov_b32 s4, s0
; GCN-UNSAFE-NEXT:    s_mov_b32 s5, s1
; GCN-UNSAFE-NEXT:    s_waitcnt vmcnt(0)
; GCN-UNSAFE-NEXT:    v_rsq_f32_e32 v0, v0
; GCN-UNSAFE-NEXT:    buffer_store_dword v0, off, s[4:7], 0
; GCN-UNSAFE-NEXT:    s_endpgm
  %sqrt = call afn contract float @llvm.sqrt.f32(float %in) nounwind readnone
  %div = fdiv afn contract float 1.0, %sqrt, !fpmath !0
  ret float %div
}

define amdgpu_kernel void @rsq_f32_sgpr(ptr addrspace(1) noalias %out, float %val) {
; GCN-DAZ-LABEL: rsq_f32_sgpr:
; GCN-DAZ:       ; %bb.0:
; GCN-DAZ-NEXT:    s_load_dword s2, s[4:5], 0xb
; GCN-DAZ-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; GCN-DAZ-NEXT:    s_mov_b32 s3, 0xf000
; GCN-DAZ-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-DAZ-NEXT:    v_rsq_f32_e32 v0, s2
; GCN-DAZ-NEXT:    s_mov_b32 s2, -1
; GCN-DAZ-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; GCN-DAZ-NEXT:    s_endpgm
;
; GCN-IEEE-LABEL: rsq_f32_sgpr:
; GCN-IEEE:       ; %bb.0:
; GCN-IEEE-NEXT:    s_load_dword s2, s[4:5], 0xb
; GCN-IEEE-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; GCN-IEEE-NEXT:    s_mov_b32 s3, 0xf000
; GCN-IEEE-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-IEEE-NEXT:    v_rsq_f32_e32 v0, s2
; GCN-IEEE-NEXT:    s_mov_b32 s2, -1
; GCN-IEEE-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; GCN-IEEE-NEXT:    s_endpgm
; GCN-UNSAFE-LABEL: rsq_f32_sgpr:
; GCN-UNSAFE:       ; %bb.0:
; GCN-UNSAFE-NEXT:    s_load_dword s2, s[0:1], 0xb
; GCN-UNSAFE-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
; GCN-UNSAFE-NEXT:    s_mov_b32 s3, 0xf000
; GCN-UNSAFE-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-UNSAFE-NEXT:    v_rsq_f32_e32 v0, s2
; GCN-UNSAFE-NEXT:    s_mov_b32 s2, -1
; GCN-UNSAFE-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; GCN-UNSAFE-NEXT:    s_endpgm
  %sqrt = call afn contract float @llvm.sqrt.f32(float %val) nounwind readnone
  %div = fdiv afn contract float 1.0, %sqrt, !fpmath !0
  store float %div, ptr addrspace(1) %out, align 4
  ret void
}

; Recognize that this is rsqrt(a) * rcp(b) * c,
; not 1 / ( 1 / sqrt(a)) * rcp(b) * c.

; NOTE: c * rcp( sqrt(a) * b ) is generated when we move rcp generation to AMGGPUCogenPrepare.
define amdgpu_kernel void @rsqrt_fmul(ptr addrspace(1) %out, ptr addrspace(1) %in) {
; GCN-UNSAFE-LABEL: rsqrt_fmul:
; GCN-UNSAFE:       ; %bb.0:
; GCN-UNSAFE-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-UNSAFE-NEXT:    s_mov_b32 s7, 0xf000
; GCN-UNSAFE-NEXT:    s_mov_b32 s6, 0
; GCN-UNSAFE-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GCN-UNSAFE-NEXT:    v_mov_b32_e32 v1, 0
; GCN-UNSAFE-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-UNSAFE-NEXT:    s_mov_b64 s[8:9], s[2:3]
; GCN-UNSAFE-NEXT:    s_mov_b64 s[10:11], s[6:7]
; GCN-UNSAFE-NEXT:    buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 glc
; GCN-UNSAFE-NEXT:    s_waitcnt vmcnt(0)
; GCN-UNSAFE-NEXT:    buffer_load_dword v3, v[0:1], s[8:11], 0 addr64 offset:4 glc
; GCN-UNSAFE-NEXT:    s_waitcnt vmcnt(0)
; GCN-UNSAFE-NEXT:    buffer_load_dword v4, v[0:1], s[8:11], 0 addr64 offset:8 glc
; GCN-UNSAFE-NEXT:    s_waitcnt vmcnt(0)
; GCN-UNSAFE-NEXT:    s_mov_b64 s[4:5], s[0:1]
; GCN-UNSAFE-NEXT:    v_sqrt_f32_e32 v2, v2
; GCN-UNSAFE-NEXT:    v_mul_f32_e32 v2, v2, v3
; GCN-UNSAFE-NEXT:    v_rcp_f32_e32 v2, v2
; GCN-UNSAFE-NEXT:    v_mul_f32_e32 v2, v4, v2
; GCN-UNSAFE-NEXT:    buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
; GCN-UNSAFE-NEXT:    s_endpgm
; GCN-DAZ-LABEL: rsqrt_fmul:
; GCN-DAZ:       ; %bb.0:
; GCN-DAZ-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
; GCN-DAZ-NEXT:    s_mov_b32 s7, 0xf000
; GCN-DAZ-NEXT:    s_mov_b32 s6, 0
; GCN-DAZ-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GCN-DAZ-NEXT:    v_mov_b32_e32 v1, 0
; GCN-DAZ-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-DAZ-NEXT:    s_mov_b64 s[8:9], s[2:3]
; GCN-DAZ-NEXT:    s_mov_b64 s[10:11], s[6:7]
; GCN-DAZ-NEXT:    buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 glc
; GCN-DAZ-NEXT:    s_waitcnt vmcnt(0)
; GCN-DAZ-NEXT:    buffer_load_dword v3, v[0:1], s[8:11], 0 addr64 offset:4 glc
; GCN-DAZ-NEXT:    s_waitcnt vmcnt(0)
; GCN-DAZ-NEXT:    buffer_load_dword v4, v[0:1], s[8:11], 0 addr64 offset:8 glc
; GCN-DAZ-NEXT:    s_waitcnt vmcnt(0)
; GCN-DAZ-NEXT:    s_mov_b64 s[4:5], s[0:1]
; GCN-DAZ-NEXT:    v_rsq_f32_e32 v2, v2
; GCN-DAZ-NEXT:    v_rcp_f32_e32 v3, v3
; GCN-DAZ-NEXT:    v_mul_f32_e32 v2, v2, v3
; GCN-DAZ-NEXT:    v_mul_f32_e32 v2, v4, v2
; GCN-DAZ-NEXT:    buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
; GCN-DAZ-NEXT:    s_endpgm
;
; GCN-IEEE-LABEL: rsqrt_fmul:
; GCN-IEEE:       ; %bb.0:
; GCN-IEEE-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
; GCN-IEEE-NEXT:    s_mov_b32 s7, 0xf000
; GCN-IEEE-NEXT:    s_mov_b32 s6, 0
; GCN-IEEE-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GCN-IEEE-NEXT:    v_mov_b32_e32 v1, 0
; GCN-IEEE-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-IEEE-NEXT:    s_mov_b64 s[8:9], s[2:3]
; GCN-IEEE-NEXT:    s_mov_b64 s[10:11], s[6:7]
; GCN-IEEE-NEXT:    buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 glc
; GCN-IEEE-NEXT:    s_waitcnt vmcnt(0)
; GCN-IEEE-NEXT:    buffer_load_dword v3, v[0:1], s[8:11], 0 addr64 offset:4 glc
; GCN-IEEE-NEXT:    s_waitcnt vmcnt(0)
; GCN-IEEE-NEXT:    buffer_load_dword v4, v[0:1], s[8:11], 0 addr64 offset:8 glc
; GCN-IEEE-NEXT:    s_waitcnt vmcnt(0)
; GCN-IEEE-NEXT:    s_mov_b64 s[4:5], s[0:1]
; GCN-IEEE-NEXT:    v_rsq_f32_e32 v2, v2
; GCN-IEEE-NEXT:    v_rcp_f32_e32 v3, v3
; GCN-IEEE-NEXT:    v_mul_f32_e32 v2, v2, v3
; GCN-IEEE-NEXT:    v_mul_f32_e32 v2, v4, v2
; GCN-IEEE-NEXT:    buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
; GCN-IEEE-NEXT:    s_endpgm
  %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
  %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
  %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
  %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1
  %gep.2 = getelementptr float, ptr addrspace(1) %gep.0, i32 2

  %a = load volatile float, ptr addrspace(1) %gep.0
  %b = load volatile float, ptr addrspace(1) %gep.1
  %c = load volatile float, ptr addrspace(1) %gep.2

  %x = call contract float @llvm.sqrt.f32(float %a)
  %y = fmul contract float %x, %b
  %z = fdiv arcp afn contract float %c, %y
  store float %z, ptr addrspace(1) %out.gep
  ret void
}

define float @neg_rsq_f32(float %in) {
; GCN-DAZ-LABEL: neg_rsq_f32:
; GCN-DAZ:       ; %bb.0:
; GCN-DAZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-DAZ-NEXT:    v_rsq_f32_e32 v0, v0
; GCN-DAZ-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0
; GCN-DAZ-NEXT:    s_setpc_b64 s[30:31]
;
; GCN-IEEE-LABEL: neg_rsq_f32:
; GCN-IEEE:       ; %bb.0:
; GCN-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IEEE-NEXT:    v_rsq_f32_e32 v0, v0
; GCN-IEEE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0
; GCN-IEEE-NEXT:    s_setpc_b64 s[30:31]
; GCN-UNSAFE-LABEL: neg_rsq_f32:
; GCN-UNSAFE:       ; %bb.0:
; GCN-UNSAFE-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-UNSAFE-NEXT:    s_mov_b32 s7, 0xf000
; GCN-UNSAFE-NEXT:    s_mov_b32 s6, -1
; GCN-UNSAFE-NEXT:    s_mov_b32 s10, s6
; GCN-UNSAFE-NEXT:    s_mov_b32 s11, s7
; GCN-UNSAFE-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-UNSAFE-NEXT:    s_mov_b32 s8, s2
; GCN-UNSAFE-NEXT:    s_mov_b32 s9, s3
; GCN-UNSAFE-NEXT:    buffer_load_dword v0, off, s[8:11], 0
; GCN-UNSAFE-NEXT:    s_mov_b32 s4, s0
; GCN-UNSAFE-NEXT:    s_mov_b32 s5, s1
; GCN-UNSAFE-NEXT:    s_waitcnt vmcnt(0)
; GCN-UNSAFE-NEXT:    v_sqrt_f32_e32 v0, v0
; GCN-UNSAFE-NEXT:    v_rcp_f32_e64 v0, -v0
; GCN-UNSAFE-NEXT:    buffer_store_dword v0, off, s[4:7], 0
; GCN-UNSAFE-NEXT:    s_endpgm
  %sqrt = call afn contract float @llvm.sqrt.f32(float %in)
  %div = fdiv afn contract float -1.0, %sqrt, !fpmath !0
  ret float %div
}

define float @neg_rsq_neg_f32(float %in) {
; GCN-DAZ-LABEL: neg_rsq_neg_f32:
; GCN-DAZ:       ; %bb.0:
; GCN-DAZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-DAZ-NEXT:    v_rsq_f32_e64 v0, -v0
; GCN-DAZ-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0
; GCN-DAZ-NEXT:    s_setpc_b64 s[30:31]
;
; GCN-IEEE-LABEL: neg_rsq_neg_f32:
; GCN-IEEE:       ; %bb.0:
; GCN-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IEEE-NEXT:    v_rsq_f32_e64 v0, -v0
; GCN-IEEE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0
; GCN-IEEE-NEXT:    s_setpc_b64 s[30:31]
; GCN-UNSAFE-LABEL: neg_rsq_neg_f32:
; GCN-UNSAFE:       ; %bb.0:
; GCN-UNSAFE-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-UNSAFE-NEXT:    s_mov_b32 s7, 0xf000
; GCN-UNSAFE-NEXT:    s_mov_b32 s6, -1
; GCN-UNSAFE-NEXT:    s_mov_b32 s10, s6
; GCN-UNSAFE-NEXT:    s_mov_b32 s11, s7
; GCN-UNSAFE-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-UNSAFE-NEXT:    s_mov_b32 s8, s2
; GCN-UNSAFE-NEXT:    s_mov_b32 s9, s3
; GCN-UNSAFE-NEXT:    buffer_load_dword v0, off, s[8:11], 0
; GCN-UNSAFE-NEXT:    s_mov_b32 s4, s0
; GCN-UNSAFE-NEXT:    s_mov_b32 s5, s1
; GCN-UNSAFE-NEXT:    s_waitcnt vmcnt(0)
; GCN-UNSAFE-NEXT:    v_sqrt_f32_e64 v0, -v0
; GCN-UNSAFE-NEXT:    v_rcp_f32_e64 v0, -v0
; GCN-UNSAFE-NEXT:    buffer_store_dword v0, off, s[4:7], 0
; GCN-UNSAFE-NEXT:    s_endpgm
  %val.fneg = fneg float %in
  %sqrt = call afn contract float @llvm.sqrt.f32(float %val.fneg)
  %div = fdiv afn contract float -1.0, %sqrt, !fpmath !0
  ret float %div
}

define float @v_neg_rsq_neg_f32(float %val) {
; GCN-DAZ-LABEL: v_neg_rsq_neg_f32:
; GCN-DAZ:       ; %bb.0:
; GCN-DAZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-DAZ-NEXT:    v_rsq_f32_e64 v0, -v0
; GCN-DAZ-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0
; GCN-DAZ-NEXT:    s_setpc_b64 s[30:31]
;
; GCN-IEEE-LABEL: v_neg_rsq_neg_f32:
; GCN-IEEE:       ; %bb.0:
; GCN-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IEEE-NEXT:    v_rsq_f32_e64 v0, -v0
; GCN-IEEE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0
; GCN-IEEE-NEXT:    s_setpc_b64 s[30:31]
  %val.fneg = fneg float %val
  %sqrt = call afn contract float @llvm.sqrt.f32(float %val.fneg)
  %div = fdiv afn contract float -1.0, %sqrt, !fpmath !0
  ret float %div
}

define <2 x float> @v_neg_rsq_neg_v2f32(<2 x float> %val) {
; GCN-DAZ-LABEL: v_neg_rsq_neg_v2f32:
; GCN-DAZ:       ; %bb.0:
; GCN-DAZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-DAZ-NEXT:    v_rsq_f32_e64 v0, -v0
; GCN-DAZ-NEXT:    v_rsq_f32_e64 v1, -v1
; GCN-DAZ-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0
; GCN-DAZ-NEXT:    v_xor_b32_e32 v1, 0x80000000, v1
; GCN-DAZ-NEXT:    s_setpc_b64 s[30:31]
;
; GCN-IEEE-LABEL: v_neg_rsq_neg_v2f32:
; GCN-IEEE:       ; %bb.0:
; GCN-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IEEE-NEXT:    v_rsq_f32_e64 v0, -v0
; GCN-IEEE-NEXT:    v_rsq_f32_e64 v1, -v1
; GCN-IEEE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0
; GCN-IEEE-NEXT:    v_xor_b32_e32 v1, 0x80000000, v1
; GCN-IEEE-NEXT:    s_setpc_b64 s[30:31]
  %val.fneg = fneg <2 x float> %val
  %sqrt = call afn contract <2 x float> @llvm.sqrt.v2f32(<2 x float> %val.fneg)
  %div = fdiv afn contract <2 x float> <float -1.0, float -1.0>, %sqrt, !fpmath !0
  ret <2 x float> %div
}

define float @v_neg_rsq_neg_f32_foldable_user(float %val0, float %val1) {
; GCN-DAZ-LABEL: v_neg_rsq_neg_f32_foldable_user:
; GCN-DAZ:       ; %bb.0:
; GCN-DAZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-DAZ-NEXT:    v_rsq_f32_e64 v0, -v0
; GCN-DAZ-NEXT:    v_mul_f32_e64 v0, -v0, v1
; GCN-DAZ-NEXT:    s_setpc_b64 s[30:31]
;
; GCN-IEEE-LABEL: v_neg_rsq_neg_f32_foldable_user:
; GCN-IEEE:       ; %bb.0:
; GCN-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IEEE-NEXT:    v_rsq_f32_e64 v0, -v0
; GCN-IEEE-NEXT:    v_mul_f32_e64 v0, -v0, v1
; GCN-IEEE-NEXT:    s_setpc_b64 s[30:31]
  %val0.neg = fneg float %val0
  %sqrt = call afn contract float @llvm.sqrt.f32(float %val0.neg)
  %div = fdiv afn contract float -1.0, %sqrt, !fpmath !0
  %user = fmul contract float %div, %val1
  ret float %user
}

define <2 x float> @v_neg_rsq_neg_v2f32_foldable_user(<2 x float> %val0, <2 x float> %val1) {
; GCN-DAZ-LABEL: v_neg_rsq_neg_v2f32_foldable_user:
; GCN-DAZ:       ; %bb.0:
; GCN-DAZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-DAZ-NEXT:    v_rsq_f32_e64 v0, -v0
; GCN-DAZ-NEXT:    v_rsq_f32_e64 v1, -v1
; GCN-DAZ-NEXT:    v_mul_f32_e64 v0, -v0, v2
; GCN-DAZ-NEXT:    v_mul_f32_e64 v1, -v1, v3
; GCN-DAZ-NEXT:    s_setpc_b64 s[30:31]
;
; GCN-IEEE-LABEL: v_neg_rsq_neg_v2f32_foldable_user:
; GCN-IEEE:       ; %bb.0:
; GCN-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IEEE-NEXT:    v_rsq_f32_e64 v0, -v0
; GCN-IEEE-NEXT:    v_rsq_f32_e64 v1, -v1
; GCN-IEEE-NEXT:    v_mul_f32_e64 v0, -v0, v2
; GCN-IEEE-NEXT:    v_mul_f32_e64 v1, -v1, v3
; GCN-IEEE-NEXT:    s_setpc_b64 s[30:31]
  %val0.fneg = fneg <2 x float> %val0
  %sqrt = call afn contract <2 x float> @llvm.sqrt.v2f32(<2 x float> %val0.fneg)
  %div = fdiv afn contract <2 x float> <float -1.0, float -1.0>, %sqrt, !fpmath !0
  %user = fmul contract <2 x float> %div, %val1
  ret <2 x float> %user
}

define float @v_neg_rsq_f32(float %val) {
; GCN-DAZ-LABEL: v_neg_rsq_f32:
; GCN-DAZ:       ; %bb.0:
; GCN-DAZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-DAZ-NEXT:    v_rsq_f32_e32 v0, v0
; GCN-DAZ-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0
; GCN-DAZ-NEXT:    s_setpc_b64 s[30:31]
;
; GCN-IEEE-LABEL: v_neg_rsq_f32:
; GCN-IEEE:       ; %bb.0:
; GCN-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IEEE-NEXT:    v_rsq_f32_e32 v0, v0
; GCN-IEEE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0
; GCN-IEEE-NEXT:    s_setpc_b64 s[30:31]
  %sqrt = call afn contract float @llvm.sqrt.f32(float %val)
  %div = fdiv afn contract float -1.0, %sqrt, !fpmath !0
  ret float %div
}

define <2 x float> @v_neg_rsq_v2f32(<2 x float> %val) {
; GCN-DAZ-LABEL: v_neg_rsq_v2f32:
; GCN-DAZ:       ; %bb.0:
; GCN-DAZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-DAZ-NEXT:    v_rsq_f32_e32 v0, v0
; GCN-DAZ-NEXT:    v_rsq_f32_e32 v1, v1
; GCN-DAZ-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0
; GCN-DAZ-NEXT:    v_xor_b32_e32 v1, 0x80000000, v1
; GCN-DAZ-NEXT:    s_setpc_b64 s[30:31]
;
; GCN-IEEE-LABEL: v_neg_rsq_v2f32:
; GCN-IEEE:       ; %bb.0:
; GCN-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IEEE-NEXT:    v_rsq_f32_e32 v0, v0
; GCN-IEEE-NEXT:    v_rsq_f32_e32 v1, v1
; GCN-IEEE-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0
; GCN-IEEE-NEXT:    v_xor_b32_e32 v1, 0x80000000, v1
; GCN-IEEE-NEXT:    s_setpc_b64 s[30:31]
  %sqrt = call afn contract <2 x float> @llvm.sqrt.v2f32(<2 x float> %val)
  %div = fdiv afn contract <2 x float> <float -1.0, float -1.0>, %sqrt, !fpmath !0
  ret <2 x float> %div
}

define float @v_neg_rsq_f32_foldable_user(float %val0, float %val1) {
; GCN-DAZ-LABEL: v_neg_rsq_f32_foldable_user:
; GCN-DAZ:       ; %bb.0:
; GCN-DAZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-DAZ-NEXT:    v_rsq_f32_e32 v0, v0
; GCN-DAZ-NEXT:    v_mul_f32_e64 v0, -v0, v1
; GCN-DAZ-NEXT:    s_setpc_b64 s[30:31]
;
; GCN-IEEE-LABEL: v_neg_rsq_f32_foldable_user:
; GCN-IEEE:       ; %bb.0:
; GCN-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IEEE-NEXT:    v_rsq_f32_e32 v0, v0
; GCN-IEEE-NEXT:    v_mul_f32_e64 v0, -v0, v1
; GCN-IEEE-NEXT:    s_setpc_b64 s[30:31]
  %sqrt = call afn contract float @llvm.sqrt.f32(float %val0)
  %div = fdiv afn contract float -1.0, %sqrt, !fpmath !0
  %user = fmul contract float %div, %val1
  ret float %user
}

define <2 x float> @v_neg_rsq_v2f32_foldable_user(<2 x float> %val0, <2 x float> %val1) {
; GCN-DAZ-LABEL: v_neg_rsq_v2f32_foldable_user:
; GCN-DAZ:       ; %bb.0:
; GCN-DAZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-DAZ-NEXT:    v_rsq_f32_e32 v0, v0
; GCN-DAZ-NEXT:    v_rsq_f32_e32 v1, v1
; GCN-DAZ-NEXT:    v_mul_f32_e64 v0, -v0, v2
; GCN-DAZ-NEXT:    v_mul_f32_e64 v1, -v1, v3
; GCN-DAZ-NEXT:    s_setpc_b64 s[30:31]
;
; GCN-IEEE-LABEL: v_neg_rsq_v2f32_foldable_user:
; GCN-IEEE:       ; %bb.0:
; GCN-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IEEE-NEXT:    v_rsq_f32_e32 v0, v0
; GCN-IEEE-NEXT:    v_rsq_f32_e32 v1, v1
; GCN-IEEE-NEXT:    v_mul_f32_e64 v0, -v0, v2
; GCN-IEEE-NEXT:    v_mul_f32_e64 v1, -v1, v3
; GCN-IEEE-NEXT:    s_setpc_b64 s[30:31]
; GCN-DAZ-SAFE-LABEL: v_neg_rsq_v2f32_foldable_user:
; GCN-DAZ-SAFE:       ; %bb.0:
; GCN-DAZ-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-DAZ-SAFE-NEXT:    s_mov_b32 s4, 0xf800000
; GCN-DAZ-SAFE-NEXT:    v_mul_f32_e32 v4, 0x4f800000, v1
; GCN-DAZ-SAFE-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v1
; GCN-DAZ-SAFE-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
; GCN-DAZ-SAFE-NEXT:    v_rsq_f32_e32 v4, v1
; GCN-DAZ-SAFE-NEXT:    v_mul_f32_e32 v5, v1, v4
; GCN-DAZ-SAFE-NEXT:    v_mul_f32_e32 v4, 0.5, v4
; GCN-DAZ-SAFE-NEXT:    v_fma_f32 v6, -v4, v5, 0.5
; GCN-DAZ-SAFE-NEXT:    v_fma_f32 v5, v5, v6, v5
; GCN-DAZ-SAFE-NEXT:    v_fma_f32 v7, -v5, v5, v1
; GCN-DAZ-SAFE-NEXT:    v_fma_f32 v4, v4, v6, v4
; GCN-DAZ-SAFE-NEXT:    v_fma_f32 v4, v7, v4, v5
; GCN-DAZ-SAFE-NEXT:    v_mul_f32_e32 v5, 0x37800000, v4
; GCN-DAZ-SAFE-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc
; GCN-DAZ-SAFE-NEXT:    v_mul_f32_e32 v5, 0x4f800000, v0
; GCN-DAZ-SAFE-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
; GCN-DAZ-SAFE-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
; GCN-DAZ-SAFE-NEXT:    v_rsq_f32_e32 v5, v0
; GCN-DAZ-SAFE-NEXT:    v_mov_b32_e32 v6, 0x260
; GCN-DAZ-SAFE-NEXT:    v_cmp_class_f32_e64 s[4:5], v1, v6
; GCN-DAZ-SAFE-NEXT:    v_cndmask_b32_e64 v1, v4, v1, s[4:5]
; GCN-DAZ-SAFE-NEXT:    v_mul_f32_e32 v4, v0, v5
; GCN-DAZ-SAFE-NEXT:    v_mul_f32_e32 v5, 0.5, v5
; GCN-DAZ-SAFE-NEXT:    v_fma_f32 v7, -v5, v4, 0.5
; GCN-DAZ-SAFE-NEXT:    v_fma_f32 v4, v4, v7, v4
; GCN-DAZ-SAFE-NEXT:    v_fma_f32 v8, -v4, v4, v0
; GCN-DAZ-SAFE-NEXT:    v_fma_f32 v5, v5, v7, v5
; GCN-DAZ-SAFE-NEXT:    v_fma_f32 v4, v8, v5, v4
; GCN-DAZ-SAFE-NEXT:    v_mul_f32_e32 v5, 0x37800000, v4
; GCN-DAZ-SAFE-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc
; GCN-DAZ-SAFE-NEXT:    v_cmp_class_f32_e32 vcc, v0, v6
; GCN-DAZ-SAFE-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
; GCN-DAZ-SAFE-NEXT:    v_rcp_f32_e64 v0, -v0
; GCN-DAZ-SAFE-NEXT:    v_rcp_f32_e64 v1, -v1
; GCN-DAZ-SAFE-NEXT:    v_mul_f32_e32 v0, v0, v2
; GCN-DAZ-SAFE-NEXT:    v_mul_f32_e32 v1, v1, v3
; GCN-DAZ-SAFE-NEXT:    s_setpc_b64 s[30:31]
; SI-IEEE-SAFE-LABEL: v_neg_rsq_v2f32_foldable_user:
; SI-IEEE-SAFE:       ; %bb.0:
; SI-IEEE-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-IEEE-SAFE-NEXT:    s_mov_b32 s6, 0xf800000
; SI-IEEE-SAFE-NEXT:    v_mul_f32_e32 v4, 0x4f800000, v1
; SI-IEEE-SAFE-NEXT:    v_cmp_gt_f32_e32 vcc, s6, v1
; SI-IEEE-SAFE-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
; SI-IEEE-SAFE-NEXT:    v_sqrt_f32_e32 v4, v1
; SI-IEEE-SAFE-NEXT:    v_add_i32_e64 v5, s[4:5], -1, v4
; SI-IEEE-SAFE-NEXT:    v_fma_f32 v6, -v5, v4, v1
; SI-IEEE-SAFE-NEXT:    v_cmp_ge_f32_e64 s[4:5], 0, v6
; SI-IEEE-SAFE-NEXT:    v_cndmask_b32_e64 v5, v4, v5, s[4:5]
; SI-IEEE-SAFE-NEXT:    v_add_i32_e64 v6, s[4:5], 1, v4
; SI-IEEE-SAFE-NEXT:    v_fma_f32 v4, -v6, v4, v1
; SI-IEEE-SAFE-NEXT:    v_cmp_lt_f32_e64 s[4:5], 0, v4
; SI-IEEE-SAFE-NEXT:    v_cndmask_b32_e64 v4, v5, v6, s[4:5]
; SI-IEEE-SAFE-NEXT:    v_mul_f32_e32 v5, 0x37800000, v4
; SI-IEEE-SAFE-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc
; SI-IEEE-SAFE-NEXT:    v_mul_f32_e32 v6, 0x4f800000, v0
; SI-IEEE-SAFE-NEXT:    v_cmp_gt_f32_e32 vcc, s6, v0
; SI-IEEE-SAFE-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
; SI-IEEE-SAFE-NEXT:    v_sqrt_f32_e32 v6, v0
; SI-IEEE-SAFE-NEXT:    v_mov_b32_e32 v5, 0x260
; SI-IEEE-SAFE-NEXT:    v_cmp_class_f32_e64 s[4:5], v1, v5
; SI-IEEE-SAFE-NEXT:    v_cndmask_b32_e64 v1, v4, v1, s[4:5]
; SI-IEEE-SAFE-NEXT:    v_add_i32_e64 v4, s[4:5], -1, v6
; SI-IEEE-SAFE-NEXT:    v_fma_f32 v7, -v4, v6, v0
; SI-IEEE-SAFE-NEXT:    v_cmp_ge_f32_e64 s[4:5], 0, v7
; SI-IEEE-SAFE-NEXT:    v_cndmask_b32_e64 v4, v6, v4, s[4:5]
; SI-IEEE-SAFE-NEXT:    v_add_i32_e64 v7, s[4:5], 1, v6
; SI-IEEE-SAFE-NEXT:    v_fma_f32 v6, -v7, v6, v0
; SI-IEEE-SAFE-NEXT:    v_cmp_lt_f32_e64 s[4:5], 0, v6
; SI-IEEE-SAFE-NEXT:    v_cndmask_b32_e64 v4, v4, v7, s[4:5]
; SI-IEEE-SAFE-NEXT:    v_mul_f32_e32 v6, 0x37800000, v4
; SI-IEEE-SAFE-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
; SI-IEEE-SAFE-NEXT:    v_cmp_class_f32_e32 vcc, v0, v5
; SI-IEEE-SAFE-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
; SI-IEEE-SAFE-NEXT:    s_mov_b32 s6, 0x7f800000
; SI-IEEE-SAFE-NEXT:    v_frexp_mant_f32_e64 v4, -v0
; SI-IEEE-SAFE-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, s6
; SI-IEEE-SAFE-NEXT:    v_cndmask_b32_e64 v4, -v0, v4, s[4:5]
; SI-IEEE-SAFE-NEXT:    v_rcp_f32_e32 v4, v4
; SI-IEEE-SAFE-NEXT:    v_frexp_exp_i32_f32_e32 v0, v0
; SI-IEEE-SAFE-NEXT:    v_sub_i32_e32 v0, vcc, 0, v0
; SI-IEEE-SAFE-NEXT:    v_ldexp_f32_e32 v0, v4, v0
; SI-IEEE-SAFE-NEXT:    v_frexp_mant_f32_e64 v4, -v1
; SI-IEEE-SAFE-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v1|, s6
; SI-IEEE-SAFE-NEXT:    v_cndmask_b32_e64 v4, -v1, v4, s[4:5]
; SI-IEEE-SAFE-NEXT:    v_rcp_f32_e32 v4, v4
; SI-IEEE-SAFE-NEXT:    v_frexp_exp_i32_f32_e32 v1, v1
; SI-IEEE-SAFE-NEXT:    v_sub_i32_e32 v1, vcc, 0, v1
; SI-IEEE-SAFE-NEXT:    v_ldexp_f32_e32 v1, v4, v1
; SI-IEEE-SAFE-NEXT:    v_mul_f32_e32 v0, v0, v2
; SI-IEEE-SAFE-NEXT:    v_mul_f32_e32 v1, v1, v3
; SI-IEEE-SAFE-NEXT:    s_setpc_b64 s[30:31]
; CI-IEEE-SAFE-LABEL: v_neg_rsq_v2f32_foldable_user:
; CI-IEEE-SAFE:       ; %bb.0:
; CI-IEEE-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-IEEE-SAFE-NEXT:    s_mov_b32 s6, 0xf800000
; CI-IEEE-SAFE-NEXT:    v_mul_f32_e32 v4, 0x4f800000, v1
; CI-IEEE-SAFE-NEXT:    v_cmp_gt_f32_e32 vcc, s6, v1
; CI-IEEE-SAFE-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
; CI-IEEE-SAFE-NEXT:    v_sqrt_f32_e32 v4, v1
; CI-IEEE-SAFE-NEXT:    v_add_i32_e64 v5, s[4:5], -1, v4
; CI-IEEE-SAFE-NEXT:    v_fma_f32 v6, -v5, v4, v1
; CI-IEEE-SAFE-NEXT:    v_cmp_ge_f32_e64 s[4:5], 0, v6
; CI-IEEE-SAFE-NEXT:    v_cndmask_b32_e64 v5, v4, v5, s[4:5]
; CI-IEEE-SAFE-NEXT:    v_add_i32_e64 v6, s[4:5], 1, v4
; CI-IEEE-SAFE-NEXT:    v_fma_f32 v4, -v6, v4, v1
; CI-IEEE-SAFE-NEXT:    v_cmp_lt_f32_e64 s[4:5], 0, v4
; CI-IEEE-SAFE-NEXT:    v_cndmask_b32_e64 v4, v5, v6, s[4:5]
; CI-IEEE-SAFE-NEXT:    v_mul_f32_e32 v5, 0x37800000, v4
; CI-IEEE-SAFE-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc
; CI-IEEE-SAFE-NEXT:    v_mul_f32_e32 v6, 0x4f800000, v0
; CI-IEEE-SAFE-NEXT:    v_cmp_gt_f32_e32 vcc, s6, v0
; CI-IEEE-SAFE-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
; CI-IEEE-SAFE-NEXT:    v_sqrt_f32_e32 v6, v0
; CI-IEEE-SAFE-NEXT:    v_mov_b32_e32 v5, 0x260
; CI-IEEE-SAFE-NEXT:    v_cmp_class_f32_e64 s[4:5], v1, v5
; CI-IEEE-SAFE-NEXT:    v_cndmask_b32_e64 v1, v4, v1, s[4:5]
; CI-IEEE-SAFE-NEXT:    v_add_i32_e64 v4, s[4:5], -1, v6
; CI-IEEE-SAFE-NEXT:    v_fma_f32 v7, -v4, v6, v0
; CI-IEEE-SAFE-NEXT:    v_cmp_ge_f32_e64 s[4:5], 0, v7
; CI-IEEE-SAFE-NEXT:    v_cndmask_b32_e64 v4, v6, v4, s[4:5]
; CI-IEEE-SAFE-NEXT:    v_add_i32_e64 v7, s[4:5], 1, v6
; CI-IEEE-SAFE-NEXT:    v_fma_f32 v6, -v7, v6, v0
; CI-IEEE-SAFE-NEXT:    v_cmp_lt_f32_e64 s[4:5], 0, v6
; CI-IEEE-SAFE-NEXT:    v_cndmask_b32_e64 v4, v4, v7, s[4:5]
; CI-IEEE-SAFE-NEXT:    v_mul_f32_e32 v6, 0x37800000, v4
; CI-IEEE-SAFE-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
; CI-IEEE-SAFE-NEXT:    v_cmp_class_f32_e32 vcc, v0, v5
; CI-IEEE-SAFE-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
; CI-IEEE-SAFE-NEXT:    v_frexp_mant_f32_e64 v4, -v0
; CI-IEEE-SAFE-NEXT:    v_rcp_f32_e32 v4, v4
; CI-IEEE-SAFE-NEXT:    v_frexp_exp_i32_f32_e32 v0, v0
; CI-IEEE-SAFE-NEXT:    v_sub_i32_e32 v0, vcc, 0, v0
; CI-IEEE-SAFE-NEXT:    v_ldexp_f32_e32 v0, v4, v0
; CI-IEEE-SAFE-NEXT:    v_frexp_mant_f32_e64 v4, -v1
; CI-IEEE-SAFE-NEXT:    v_rcp_f32_e32 v4, v4
; CI-IEEE-SAFE-NEXT:    v_frexp_exp_i32_f32_e32 v1, v1
; CI-IEEE-SAFE-NEXT:    v_sub_i32_e32 v1, vcc, 0, v1
; CI-IEEE-SAFE-NEXT:    v_ldexp_f32_e32 v1, v4, v1
; CI-IEEE-SAFE-NEXT:    v_mul_f32_e32 v0, v0, v2
; CI-IEEE-SAFE-NEXT:    v_mul_f32_e32 v1, v1, v3
; CI-IEEE-SAFE-NEXT:    s_setpc_b64 s[30:31]
  %sqrt = call afn contract <2 x float> @llvm.sqrt.v2f32(<2 x float> %val0)
  %div = fdiv afn contract <2 x float> <float -1.0, float -1.0>, %sqrt, !fpmath !0
  %user = fmul contract <2 x float> %div, %val1
  ret <2 x float> %user
}

define float @v_rsq_f32(float %val) {
; GCN-DAZ-LABEL: v_rsq_f32:
; GCN-DAZ:       ; %bb.0:
; GCN-DAZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-DAZ-NEXT:    v_rsq_f32_e32 v0, v0
; GCN-DAZ-NEXT:    s_setpc_b64 s[30:31]
;
; GCN-IEEE-LABEL: v_rsq_f32:
; GCN-IEEE:       ; %bb.0:
; GCN-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IEEE-NEXT:    v_rsq_f32_e32 v0, v0
; GCN-IEEE-NEXT:    s_setpc_b64 s[30:31]
; GCN-IEEE-SAFE-LABEL: v_rsq_f32:
; GCN-IEEE-SAFE:       ; %bb.0:
; GCN-IEEE-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IEEE-SAFE-NEXT:    s_mov_b32 s4, 0x800000
; GCN-IEEE-SAFE-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
; GCN-IEEE-SAFE-NEXT:    v_cndmask_b32_e64 v1, 0, 24, vcc
; GCN-IEEE-SAFE-NEXT:    v_ldexp_f32_e32 v0, v0, v1
; GCN-IEEE-SAFE-NEXT:    v_rsq_f32_e32 v0, v0
; GCN-IEEE-SAFE-NEXT:    v_cndmask_b32_e64 v1, 0, 12, vcc
; GCN-IEEE-SAFE-NEXT:    v_ldexp_f32_e32 v0, v0, v1
; GCN-IEEE-SAFE-NEXT:    s_setpc_b64 s[30:31]
  %sqrt = call afn contract float @llvm.sqrt.f32(float %val), !fpmath !1
  %div = fdiv afn contract float 1.0, %sqrt, !fpmath !1
  ret float %div
}

define { float, float } @v_rsq_f32_multi_use(float %val) {
; GCN-DAZ-LABEL: v_rsq_f32_multi_use:
; GCN-DAZ:       ; %bb.0:
; GCN-DAZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-DAZ-NEXT:    v_sqrt_f32_e32 v2, v0
; GCN-DAZ-NEXT:    v_rsq_f32_e32 v1, v0
; GCN-DAZ-NEXT:    v_mov_b32_e32 v0, v2
; GCN-DAZ-NEXT:    s_setpc_b64 s[30:31]
;
; GCN-IEEE-LABEL: v_rsq_f32_multi_use:
; GCN-IEEE:       ; %bb.0:
; GCN-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IEEE-NEXT:    v_sqrt_f32_e32 v2, v0
; GCN-IEEE-NEXT:    v_rsq_f32_e32 v1, v0
; GCN-IEEE-NEXT:    v_mov_b32_e32 v0, v2
; GCN-IEEE-NEXT:    s_setpc_b64 s[30:31]
; GCN-DAZ-SAFE-LABEL: v_rsq_f32_multi_use:
; GCN-DAZ-SAFE:       ; %bb.0:
; GCN-DAZ-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-DAZ-SAFE-NEXT:    v_sqrt_f32_e32 v0, v0
; GCN-DAZ-SAFE-NEXT:    v_rcp_f32_e32 v1, v0
; GCN-DAZ-SAFE-NEXT:    s_setpc_b64 s[30:31]
; SI-IEEE-SAFE-LABEL: v_rsq_f32_multi_use:
; SI-IEEE-SAFE:       ; %bb.0:
; SI-IEEE-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-IEEE-SAFE-NEXT:    s_mov_b32 s4, 0xf800000
; SI-IEEE-SAFE-NEXT:    v_mul_f32_e32 v1, 0x4f800000, v0
; SI-IEEE-SAFE-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
; SI-IEEE-SAFE-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-IEEE-SAFE-NEXT:    v_sqrt_f32_e32 v1, v0
; SI-IEEE-SAFE-NEXT:    v_add_i32_e64 v2, s[4:5], -1, v1
; SI-IEEE-SAFE-NEXT:    v_fma_f32 v3, -v2, v1, v0
; SI-IEEE-SAFE-NEXT:    v_cmp_ge_f32_e64 s[4:5], 0, v3
; SI-IEEE-SAFE-NEXT:    v_cndmask_b32_e64 v2, v1, v2, s[4:5]
; SI-IEEE-SAFE-NEXT:    v_add_i32_e64 v3, s[4:5], 1, v1
; SI-IEEE-SAFE-NEXT:    v_fma_f32 v1, -v3, v1, v0
; SI-IEEE-SAFE-NEXT:    v_cmp_lt_f32_e64 s[4:5], 0, v1
; SI-IEEE-SAFE-NEXT:    v_cndmask_b32_e64 v1, v2, v3, s[4:5]
; SI-IEEE-SAFE-NEXT:    v_mul_f32_e32 v2, 0x37800000, v1
; SI-IEEE-SAFE-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
; SI-IEEE-SAFE-NEXT:    v_mov_b32_e32 v2, 0x260
; SI-IEEE-SAFE-NEXT:    v_cmp_class_f32_e32 vcc, v0, v2
; SI-IEEE-SAFE-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; SI-IEEE-SAFE-NEXT:    s_mov_b32 s4, 0x7f800000
; SI-IEEE-SAFE-NEXT:    v_frexp_mant_f32_e32 v1, v0
; SI-IEEE-SAFE-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, s4
; SI-IEEE-SAFE-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
; SI-IEEE-SAFE-NEXT:    v_rcp_f32_e32 v1, v1
; SI-IEEE-SAFE-NEXT:    v_frexp_exp_i32_f32_e32 v2, v0
; SI-IEEE-SAFE-NEXT:    v_sub_i32_e32 v2, vcc, 0, v2
; SI-IEEE-SAFE-NEXT:    v_ldexp_f32_e32 v1, v1, v2
; SI-IEEE-SAFE-NEXT:    s_setpc_b64 s[30:31]
; CI-IEEE-SAFE-LABEL: v_rsq_f32_multi_use:
; CI-IEEE-SAFE:       ; %bb.0:
; CI-IEEE-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-IEEE-SAFE-NEXT:    s_mov_b32 s4, 0xf800000
; CI-IEEE-SAFE-NEXT:    v_mul_f32_e32 v1, 0x4f800000, v0
; CI-IEEE-SAFE-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
; CI-IEEE-SAFE-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
; CI-IEEE-SAFE-NEXT:    v_sqrt_f32_e32 v1, v0
; CI-IEEE-SAFE-NEXT:    v_add_i32_e64 v2, s[4:5], -1, v1
; CI-IEEE-SAFE-NEXT:    v_fma_f32 v3, -v2, v1, v0
; CI-IEEE-SAFE-NEXT:    v_cmp_ge_f32_e64 s[4:5], 0, v3
; CI-IEEE-SAFE-NEXT:    v_cndmask_b32_e64 v2, v1, v2, s[4:5]
; CI-IEEE-SAFE-NEXT:    v_add_i32_e64 v3, s[4:5], 1, v1
; CI-IEEE-SAFE-NEXT:    v_fma_f32 v1, -v3, v1, v0
; CI-IEEE-SAFE-NEXT:    v_cmp_lt_f32_e64 s[4:5], 0, v1
; CI-IEEE-SAFE-NEXT:    v_cndmask_b32_e64 v1, v2, v3, s[4:5]
; CI-IEEE-SAFE-NEXT:    v_mul_f32_e32 v2, 0x37800000, v1
; CI-IEEE-SAFE-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
; CI-IEEE-SAFE-NEXT:    v_mov_b32_e32 v2, 0x260
; CI-IEEE-SAFE-NEXT:    v_cmp_class_f32_e32 vcc, v0, v2
; CI-IEEE-SAFE-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; CI-IEEE-SAFE-NEXT:    v_frexp_mant_f32_e32 v1, v0
; CI-IEEE-SAFE-NEXT:    v_rcp_f32_e32 v1, v1
; CI-IEEE-SAFE-NEXT:    v_frexp_exp_i32_f32_e32 v2, v0
; CI-IEEE-SAFE-NEXT:    v_sub_i32_e32 v2, vcc, 0, v2
; CI-IEEE-SAFE-NEXT:    v_ldexp_f32_e32 v1, v1, v2
; CI-IEEE-SAFE-NEXT:    s_setpc_b64 s[30:31]
  %sqrt = call afn contract float @llvm.sqrt.f32(float %val), !fpmath !1
  %insert.0 = insertvalue { float, float } poison, float %sqrt, 0
  %div = fdiv arcp afn contract float 1.0, %sqrt, !fpmath !1
  %insert.1 = insertvalue { float, float } %insert.0, float %div, 1
  ret { float, float } %insert.1
}

define float @v_rsq_f32_missing_contract0(float %val) {
; GCN-DAZ-LABEL: v_rsq_f32_missing_contract0:
; GCN-DAZ:       ; %bb.0:
; GCN-DAZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-DAZ-NEXT:    v_rsq_f32_e32 v0, v0
; GCN-DAZ-NEXT:    s_setpc_b64 s[30:31]
;
; GCN-IEEE-LABEL: v_rsq_f32_missing_contract0:
; GCN-IEEE:       ; %bb.0:
; GCN-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IEEE-NEXT:    v_rsq_f32_e32 v0, v0
; GCN-IEEE-NEXT:    s_setpc_b64 s[30:31]
; GCN-DAZ-SAFE-LABEL: v_rsq_f32_missing_contract0:
; GCN-DAZ-SAFE:       ; %bb.0:
; GCN-DAZ-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-DAZ-SAFE-NEXT:    v_sqrt_f32_e32 v0, v0
; GCN-DAZ-SAFE-NEXT:    v_rcp_f32_e32 v0, v0
; GCN-DAZ-SAFE-NEXT:    s_setpc_b64 s[30:31]
; SI-IEEE-SAFE-LABEL: v_rsq_f32_missing_contract0:
; SI-IEEE-SAFE:       ; %bb.0:
; SI-IEEE-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-IEEE-SAFE-NEXT:    s_mov_b32 s4, 0xf800000
; SI-IEEE-SAFE-NEXT:    v_mul_f32_e32 v1, 0x4f800000, v0
; SI-IEEE-SAFE-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
; SI-IEEE-SAFE-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-IEEE-SAFE-NEXT:    v_sqrt_f32_e32 v1, v0
; SI-IEEE-SAFE-NEXT:    v_add_i32_e64 v2, s[4:5], -1, v1
; SI-IEEE-SAFE-NEXT:    v_fma_f32 v3, -v2, v1, v0
; SI-IEEE-SAFE-NEXT:    v_cmp_ge_f32_e64 s[4:5], 0, v3
; SI-IEEE-SAFE-NEXT:    v_cndmask_b32_e64 v2, v1, v2, s[4:5]
; SI-IEEE-SAFE-NEXT:    v_add_i32_e64 v3, s[4:5], 1, v1
; SI-IEEE-SAFE-NEXT:    v_fma_f32 v1, -v3, v1, v0
; SI-IEEE-SAFE-NEXT:    v_cmp_lt_f32_e64 s[4:5], 0, v1
; SI-IEEE-SAFE-NEXT:    v_cndmask_b32_e64 v1, v2, v3, s[4:5]
; SI-IEEE-SAFE-NEXT:    v_mul_f32_e32 v2, 0x37800000, v1
; SI-IEEE-SAFE-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
; SI-IEEE-SAFE-NEXT:    v_mov_b32_e32 v2, 0x260
; SI-IEEE-SAFE-NEXT:    v_cmp_class_f32_e32 vcc, v0, v2
; SI-IEEE-SAFE-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; SI-IEEE-SAFE-NEXT:    s_mov_b32 s4, 0x7f800000
; SI-IEEE-SAFE-NEXT:    v_frexp_mant_f32_e32 v1, v0
; SI-IEEE-SAFE-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, s4
; SI-IEEE-SAFE-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
; SI-IEEE-SAFE-NEXT:    v_rcp_f32_e32 v1, v1
; SI-IEEE-SAFE-NEXT:    v_frexp_exp_i32_f32_e32 v0, v0
; SI-IEEE-SAFE-NEXT:    v_sub_i32_e32 v0, vcc, 0, v0
; SI-IEEE-SAFE-NEXT:    v_ldexp_f32_e32 v0, v1, v0
; SI-IEEE-SAFE-NEXT:    s_setpc_b64 s[30:31]
; CI-IEEE-SAFE-LABEL: v_rsq_f32_missing_contract0:
; CI-IEEE-SAFE:       ; %bb.0:
; CI-IEEE-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-IEEE-SAFE-NEXT:    s_mov_b32 s4, 0xf800000
; CI-IEEE-SAFE-NEXT:    v_mul_f32_e32 v1, 0x4f800000, v0
; CI-IEEE-SAFE-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
; CI-IEEE-SAFE-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
; CI-IEEE-SAFE-NEXT:    v_sqrt_f32_e32 v1, v0
; CI-IEEE-SAFE-NEXT:    v_add_i32_e64 v2, s[4:5], -1, v1
; CI-IEEE-SAFE-NEXT:    v_fma_f32 v3, -v2, v1, v0
; CI-IEEE-SAFE-NEXT:    v_cmp_ge_f32_e64 s[4:5], 0, v3
; CI-IEEE-SAFE-NEXT:    v_cndmask_b32_e64 v2, v1, v2, s[4:5]
; CI-IEEE-SAFE-NEXT:    v_add_i32_e64 v3, s[4:5], 1, v1
; CI-IEEE-SAFE-NEXT:    v_fma_f32 v1, -v3, v1, v0
; CI-IEEE-SAFE-NEXT:    v_cmp_lt_f32_e64 s[4:5], 0, v1
; CI-IEEE-SAFE-NEXT:    v_cndmask_b32_e64 v1, v2, v3, s[4:5]
; CI-IEEE-SAFE-NEXT:    v_mul_f32_e32 v2, 0x37800000, v1
; CI-IEEE-SAFE-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
; CI-IEEE-SAFE-NEXT:    v_mov_b32_e32 v2, 0x260
; CI-IEEE-SAFE-NEXT:    v_cmp_class_f32_e32 vcc, v0, v2
; CI-IEEE-SAFE-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; CI-IEEE-SAFE-NEXT:    v_frexp_mant_f32_e32 v1, v0
; CI-IEEE-SAFE-NEXT:    v_rcp_f32_e32 v1, v1
; CI-IEEE-SAFE-NEXT:    v_frexp_exp_i32_f32_e32 v0, v0
; CI-IEEE-SAFE-NEXT:    v_sub_i32_e32 v0, vcc, 0, v0
; CI-IEEE-SAFE-NEXT:    v_ldexp_f32_e32 v0, v1, v0
; CI-IEEE-SAFE-NEXT:    s_setpc_b64 s[30:31]
  %sqrt = call afn float @llvm.sqrt.f32(float %val), !fpmath !1
  %div = fdiv arcp afn contract float 1.0, %sqrt, !fpmath !1
  ret float %div
}

define float @v_rsq_f32_missing_contract1(float %val) {
; GCN-DAZ-LABEL: v_rsq_f32_missing_contract1:
; GCN-DAZ:       ; %bb.0:
; GCN-DAZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-DAZ-NEXT:    v_rsq_f32_e32 v0, v0
; GCN-DAZ-NEXT:    s_setpc_b64 s[30:31]
;
; GCN-IEEE-LABEL: v_rsq_f32_missing_contract1:
; GCN-IEEE:       ; %bb.0:
; GCN-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IEEE-NEXT:    v_rsq_f32_e32 v0, v0
; GCN-IEEE-NEXT:    s_setpc_b64 s[30:31]
  %sqrt = call afn contract float @llvm.sqrt.f32(float %val), !fpmath !1
  %div = fdiv arcp afn float 1.0, %sqrt, !fpmath !1
  ret float %div
}

; Test that we contract into FMA for an fadd user after introducing
; the fmul.
define float @v_rsq_f32_contractable_user(float %val0, float %val1) {
; GCN-DAZ-LABEL: v_rsq_f32_contractable_user:
; GCN-DAZ:       ; %bb.0:
; GCN-DAZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-DAZ-NEXT:    v_rsq_f32_e32 v0, v0
; GCN-DAZ-NEXT:    v_add_f32_e32 v0, v0, v1
; GCN-DAZ-NEXT:    s_setpc_b64 s[30:31]
;
; GCN-IEEE-LABEL: v_rsq_f32_contractable_user:
; GCN-IEEE:       ; %bb.0:
; GCN-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IEEE-NEXT:    v_rsq_f32_e32 v0, v0
; GCN-IEEE-NEXT:    v_add_f32_e32 v0, v0, v1
; GCN-IEEE-NEXT:    s_setpc_b64 s[30:31]
  %sqrt = call afn contract float @llvm.sqrt.f32(float %val0), !fpmath !1
  %div = fdiv afn contract float 1.0, %sqrt, !fpmath !1
  %add = fadd contract float %div, %val1
  ret float %add
}

; Missing contract on the fdiv
define float @v_rsq_f32_contractable_user_missing_contract0(float %val0, float %val1) {
; GCN-DAZ-LABEL: v_rsq_f32_contractable_user_missing_contract0:
; GCN-DAZ:       ; %bb.0:
; GCN-DAZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-DAZ-NEXT:    v_rsq_f32_e32 v0, v0
; GCN-DAZ-NEXT:    v_add_f32_e32 v0, v0, v1
; GCN-DAZ-NEXT:    s_setpc_b64 s[30:31]
;
; GCN-IEEE-LABEL: v_rsq_f32_contractable_user_missing_contract0:
; GCN-IEEE:       ; %bb.0:
; GCN-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IEEE-NEXT:    v_rsq_f32_e32 v0, v0
; GCN-IEEE-NEXT:    v_add_f32_e32 v0, v0, v1
; GCN-IEEE-NEXT:    s_setpc_b64 s[30:31]
  %sqrt = call afn contract float @llvm.sqrt.f32(float %val0), !fpmath !1
  %div = fdiv afn contract float 1.0, %sqrt, !fpmath !1
  %add = fadd contract float %div, %val1
  ret float %add
}

; Missing contract on the fadd
define float @v_rsq_f32_contractable_user_missing_contract1(float %val0, float %val1) {
; GCN-DAZ-LABEL: v_rsq_f32_contractable_user_missing_contract1:
; GCN-DAZ:       ; %bb.0:
; GCN-DAZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-DAZ-NEXT:    v_rsq_f32_e32 v0, v0
; GCN-DAZ-NEXT:    v_add_f32_e32 v0, v0, v1
; GCN-DAZ-NEXT:    s_setpc_b64 s[30:31]
;
; GCN-IEEE-LABEL: v_rsq_f32_contractable_user_missing_contract1:
; GCN-IEEE:       ; %bb.0:
; GCN-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IEEE-NEXT:    v_rsq_f32_e32 v0, v0
; GCN-IEEE-NEXT:    v_add_f32_e32 v0, v0, v1
; GCN-IEEE-NEXT:    s_setpc_b64 s[30:31]
  %sqrt = call afn contract float @llvm.sqrt.f32(float %val0), !fpmath !1
  %div = fdiv afn contract float 1.0, %sqrt, !fpmath !1
  %add = fadd float %div, %val1
  ret float %add
}

define float @v_rsq_f32_known_never_denormal(float nofpclass(sub) %val) {
; GCN-DAZ-LABEL: v_rsq_f32_known_never_denormal:
; GCN-DAZ:       ; %bb.0:
; GCN-DAZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-DAZ-NEXT:    v_rsq_f32_e32 v0, v0
; GCN-DAZ-NEXT:    s_setpc_b64 s[30:31]
;
; GCN-IEEE-LABEL: v_rsq_f32_known_never_denormal:
; GCN-IEEE:       ; %bb.0:
; GCN-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IEEE-NEXT:    v_rsq_f32_e32 v0, v0
; GCN-IEEE-NEXT:    s_setpc_b64 s[30:31]
  %sqrt = call contract float @llvm.sqrt.f32(float %val), !fpmath !1
  %div = fdiv contract float 1.0, %sqrt, !fpmath !1
  ret float %div
}

define float @v_rsq_f32_known_never_posdenormal(float nofpclass(psub) %val) {
; GCN-DAZ-LABEL: v_rsq_f32_known_never_posdenormal:
; GCN-DAZ:       ; %bb.0:
; GCN-DAZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-DAZ-NEXT:    v_rsq_f32_e32 v0, v0
; GCN-DAZ-NEXT:    s_setpc_b64 s[30:31]
;
; GCN-IEEE-LABEL: v_rsq_f32_known_never_posdenormal:
; GCN-IEEE:       ; %bb.0:
; GCN-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IEEE-NEXT:    v_rsq_f32_e32 v0, v0
; GCN-IEEE-NEXT:    s_setpc_b64 s[30:31]
  %sqrt = call afn contract float @llvm.sqrt.f32(float %val), !fpmath !1
  %div = fdiv afn contract float 1.0, %sqrt, !fpmath !1
  ret float %div
}

!0 = !{float 2.500000e+00}
!1 = !{float 1.000000e+00}

attributes #0 = { nounwind denormal_fpenv(float: preservesign) }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CI-DAZ-UNSAFE: {{.*}}
; CI-IEEE-UNSAFE: {{.*}}
; GCN-DAZ-UNSAFE: {{.*}}
; GCN-IEEE-UNSAFE: {{.*}}
; SI-DAZ-UNSAFE: {{.*}}
; SI-IEEE-UNSAFE: {{.*}}