llvm/test/CodeGen/AMDGPU/or.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN:  llc  -mtriple=amdgpu6.01 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX6 %s
; RUN:  llc  -mtriple=amdgpu8.02 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8 %s

define amdgpu_ps <2 x i32> @s_or_v2i32(<2 x i32> inreg %num, <2 x i32> inreg %den) {
; GFX6-LABEL: s_or_v2i32:
; GFX6:       ; %bb.0:
; GFX6-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]
; GFX6-NEXT:    ; return to shader part epilog
;
; GFX8-LABEL: s_or_v2i32:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]
; GFX8-NEXT:    ; return to shader part epilog
  %result = or <2 x i32> %num, %den
  ret <2 x i32> %result
}

define <2 x i32> @v_or_v2i32(<2 x i32> %num, <2 x i32> %den) {
; GFX6-LABEL: v_or_v2i32:
; GFX6:       ; %bb.0:
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    v_or_b32_e32 v1, v1, v3
; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
; GFX6-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_or_v2i32:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_or_b32_e32 v1, v1, v3
; GFX8-NEXT:    v_or_b32_e32 v0, v0, v2
; GFX8-NEXT:    s_setpc_b64 s[30:31]
  %result = or <2 x i32> %num, %den
  ret <2 x i32> %result
}

define <2 x i32> @or_v2i32(<2 x i32> %a, <2 x i32> %b) {
; GFX6-LABEL: or_v2i32:
; GFX6:       ; %bb.0:
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    v_or_b32_e32 v1, v1, v3
; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
; GFX6-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: or_v2i32:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_or_b32_e32 v1, v1, v3
; GFX8-NEXT:    v_or_b32_e32 v0, v0, v2
; GFX8-NEXT:    s_setpc_b64 s[30:31]
  %result = or <2 x i32> %a, %b
  ret <2 x i32> %result
}

define <4 x i32> @or_v4i32(<4 x i32> %a, <4 x i32> %b) {
; GFX6-LABEL: or_v4i32:
; GFX6:       ; %bb.0:
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    v_or_b32_e32 v0, v0, v4
; GFX6-NEXT:    v_or_b32_e32 v1, v1, v5
; GFX6-NEXT:    v_or_b32_e32 v2, v2, v6
; GFX6-NEXT:    v_or_b32_e32 v3, v3, v7
; GFX6-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: or_v4i32:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_or_b32_e32 v0, v0, v4
; GFX8-NEXT:    v_or_b32_e32 v1, v1, v5
; GFX8-NEXT:    v_or_b32_e32 v2, v2, v6
; GFX8-NEXT:    v_or_b32_e32 v3, v3, v7
; GFX8-NEXT:    s_setpc_b64 s[30:31]
  %result = or <4 x i32> %a, %b
  ret <4 x i32> %result
}

define amdgpu_kernel void @scalar_or_i32(ptr addrspace(1) %out, i32 %a, i32 %b) {
; GFX6-LABEL: scalar_or_i32:
; GFX6:       ; %bb.0:
; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
; GFX6-NEXT:    s_mov_b64 s[4:5], s[2:3]
; GFX6-NEXT:    s_or_b32 s4, s4, s5
; GFX6-NEXT:    s_mov_b32 s3, 0xf000
; GFX6-NEXT:    s_mov_b32 s2, -1
; GFX6-NEXT:    v_mov_b32_e32 v0, s4
; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT:    s_endpgm
;
; GFX8-LABEL: scalar_or_i32:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
; GFX8-NEXT:    s_mov_b64 s[4:5], s[2:3]
; GFX8-NEXT:    s_or_b32 s4, s4, s5
; GFX8-NEXT:    s_mov_b32 s3, 0xf000
; GFX8-NEXT:    s_mov_b32 s2, -1
; GFX8-NEXT:    v_mov_b32_e32 v0, s4
; GFX8-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; GFX8-NEXT:    s_endpgm
  %or = or i32 %a, %b
  store i32 %or, ptr addrspace(1) %out
  ret void
}

define i32 @vector_or_i32(i32 %a, i32 inreg %b) {
; GFX6-LABEL: vector_or_i32:
; GFX6:       ; %bb.0:
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    v_or_b32_e32 v0, s16, v0
; GFX6-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: vector_or_i32:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_or_b32_e32 v0, s16, v0
; GFX8-NEXT:    s_setpc_b64 s[30:31]
  %or = or i32 %a, %b
  ret i32 %or
}

define amdgpu_kernel void @scalar_or_literal_i32(ptr addrspace(1) %out, i32 %a) {
; GFX6-LABEL: scalar_or_literal_i32:
; GFX6:       ; %bb.0:
; GFX6-NEXT:    s_load_dword s6, s[4:5], 0xb
; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; GFX6-NEXT:    s_mov_b32 s3, 0xf000
; GFX6-NEXT:    s_mov_b32 s2, -1
; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
; GFX6-NEXT:    s_or_b32 s4, s6, 0x1869f
; GFX6-NEXT:    v_mov_b32_e32 v0, s4
; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT:    s_endpgm
;
; GFX8-LABEL: scalar_or_literal_i32:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_load_dword s6, s[4:5], 0x2c
; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX8-NEXT:    s_mov_b32 s3, 0xf000
; GFX8-NEXT:    s_mov_b32 s2, -1
; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
; GFX8-NEXT:    s_or_b32 s4, s6, 0x1869f
; GFX8-NEXT:    v_mov_b32_e32 v0, s4
; GFX8-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; GFX8-NEXT:    s_endpgm
  %or = or i32 %a, 99999
  store i32 %or, ptr addrspace(1) %out, align 4
  ret void
}

define amdgpu_kernel void @scalar_or_literal_i64(ptr addrspace(1) %out, [8 x i32], i64 %a) {
; GFX6-LABEL: scalar_or_literal_i64:
; GFX6:       ; %bb.0:
; GFX6-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x13
; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; GFX6-NEXT:    s_mov_b32 s3, 0xf000
; GFX6-NEXT:    s_mov_b32 s2, -1
; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
; GFX6-NEXT:    s_or_b32 s4, s7, 0xf237b
; GFX6-NEXT:    s_or_b32 s5, s6, 0x3039
; GFX6-NEXT:    v_mov_b32_e32 v0, s5
; GFX6-NEXT:    v_mov_b32_e32 v1, s4
; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX6-NEXT:    s_endpgm
;
; GFX8-LABEL: scalar_or_literal_i64:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x4c
; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX8-NEXT:    s_mov_b32 s3, 0xf000
; GFX8-NEXT:    s_mov_b32 s2, -1
; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
; GFX8-NEXT:    s_or_b32 s4, s7, 0xf237b
; GFX8-NEXT:    s_or_b32 s5, s6, 0x3039
; GFX8-NEXT:    v_mov_b32_e32 v0, s5
; GFX8-NEXT:    v_mov_b32_e32 v1, s4
; GFX8-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX8-NEXT:    s_endpgm
  %or = or i64 %a, 4261135838621753
  store i64 %or, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @scalar_or_literal_multi_use_i64(ptr addrspace(1) %out, [8 x i32], i64 %a, [8 x i32], i64 %b) {
; GFX6-LABEL: scalar_or_literal_multi_use_i64:
; GFX6:       ; %bb.0:
; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; GFX6-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x13
; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x1d
; GFX6-NEXT:    s_movk_i32 s8, 0x3039
; GFX6-NEXT:    s_mov_b32 s9, 0xf237b
; GFX6-NEXT:    s_mov_b32 s3, 0xf000
; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
; GFX6-NEXT:    s_or_b64 s[6:7], s[6:7], s[8:9]
; GFX6-NEXT:    s_mov_b32 s2, -1
; GFX6-NEXT:    v_mov_b32_e32 v0, s6
; GFX6-NEXT:    v_mov_b32_e32 v1, s7
; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX6-NEXT:    s_add_u32 s0, s4, 0x3039
; GFX6-NEXT:    s_addc_u32 s1, s5, 0xf237b
; GFX6-NEXT:    s_waitcnt expcnt(0)
; GFX6-NEXT:    v_mov_b32_e32 v0, s0
; GFX6-NEXT:    v_mov_b32_e32 v1, s1
; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX6-NEXT:    s_waitcnt vmcnt(0)
; GFX6-NEXT:    s_endpgm
;
; GFX8-LABEL: scalar_or_literal_multi_use_i64:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x4c
; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX8-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x74
; GFX8-NEXT:    s_movk_i32 s8, 0x3039
; GFX8-NEXT:    s_mov_b32 s9, 0xf237b
; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
; GFX8-NEXT:    s_or_b64 s[6:7], s[6:7], s[8:9]
; GFX8-NEXT:    s_mov_b32 s3, 0xf000
; GFX8-NEXT:    s_mov_b32 s2, -1
; GFX8-NEXT:    v_mov_b32_e32 v0, s6
; GFX8-NEXT:    v_mov_b32_e32 v1, s7
; GFX8-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX8-NEXT:    s_add_u32 s0, s4, 0x3039
; GFX8-NEXT:    s_addc_u32 s1, s5, 0xf237b
; GFX8-NEXT:    v_mov_b32_e32 v0, s0
; GFX8-NEXT:    v_mov_b32_e32 v1, s1
; GFX8-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX8-NEXT:    s_waitcnt vmcnt(0)
; GFX8-NEXT:    s_endpgm
  %or = or i64 %a, 4261135838621753
  store i64 %or, ptr addrspace(1) %out

  %foo = add i64 %b, 4261135838621753
  store volatile i64 %foo, ptr addrspace(1) poison
  ret void
}

define amdgpu_kernel void @scalar_or_inline_imm_i64(ptr addrspace(1) %out, [8 x i32], i64 %a) {
; GFX6-LABEL: scalar_or_inline_imm_i64:
; GFX6:       ; %bb.0:
; GFX6-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x13
; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; GFX6-NEXT:    s_mov_b32 s3, 0xf000
; GFX6-NEXT:    s_mov_b32 s2, -1
; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
; GFX6-NEXT:    s_or_b32 s4, s6, 63
; GFX6-NEXT:    v_mov_b32_e32 v0, s4
; GFX6-NEXT:    v_mov_b32_e32 v1, s7
; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX6-NEXT:    s_endpgm
;
; GFX8-LABEL: scalar_or_inline_imm_i64:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x4c
; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX8-NEXT:    s_mov_b32 s3, 0xf000
; GFX8-NEXT:    s_mov_b32 s2, -1
; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
; GFX8-NEXT:    s_or_b32 s4, s6, 63
; GFX8-NEXT:    v_mov_b32_e32 v0, s4
; GFX8-NEXT:    v_mov_b32_e32 v1, s7
; GFX8-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX8-NEXT:    s_endpgm
  %or = or i64 %a, 63
  store i64 %or, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @scalar_or_inline_imm_multi_use_i64(ptr addrspace(1) %out, i64 %a, i64 %b) {
; GFX6-LABEL: scalar_or_inline_imm_multi_use_i64:
; GFX6:       ; %bb.0:
; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
; GFX6-NEXT:    s_load_dwordx2 s[8:9], s[4:5], 0xd
; GFX6-NEXT:    s_mov_b32 s7, 0xf000
; GFX6-NEXT:    s_mov_b32 s6, -1
; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
; GFX6-NEXT:    s_mov_b32 s4, s0
; GFX6-NEXT:    s_or_b32 s0, s2, 63
; GFX6-NEXT:    v_mov_b32_e32 v0, s0
; GFX6-NEXT:    s_add_u32 s0, s8, 63
; GFX6-NEXT:    s_mov_b32 s5, s1
; GFX6-NEXT:    v_mov_b32_e32 v1, s3
; GFX6-NEXT:    s_addc_u32 s1, s9, 0
; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX6-NEXT:    s_waitcnt expcnt(0)
; GFX6-NEXT:    v_mov_b32_e32 v0, s0
; GFX6-NEXT:    v_mov_b32_e32 v1, s1
; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX6-NEXT:    s_waitcnt vmcnt(0)
; GFX6-NEXT:    s_endpgm
;
; GFX8-LABEL: scalar_or_inline_imm_multi_use_i64:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8-NEXT:    s_load_dwordx2 s[8:9], s[4:5], 0x34
; GFX8-NEXT:    s_mov_b32 s7, 0xf000
; GFX8-NEXT:    s_mov_b32 s6, -1
; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
; GFX8-NEXT:    s_mov_b32 s4, s0
; GFX8-NEXT:    s_or_b32 s0, s2, 63
; GFX8-NEXT:    v_mov_b32_e32 v0, s0
; GFX8-NEXT:    s_add_u32 s0, s8, 63
; GFX8-NEXT:    s_mov_b32 s5, s1
; GFX8-NEXT:    v_mov_b32_e32 v1, s3
; GFX8-NEXT:    s_addc_u32 s1, s9, 0
; GFX8-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX8-NEXT:    v_mov_b32_e32 v0, s0
; GFX8-NEXT:    v_mov_b32_e32 v1, s1
; GFX8-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX8-NEXT:    s_waitcnt vmcnt(0)
; GFX8-NEXT:    s_endpgm
  %or = or i64 %a, 63
  store i64 %or, ptr addrspace(1) %out
  %foo = add i64 %b, 63
  store volatile i64 %foo, ptr addrspace(1) poison
  ret void
}

define amdgpu_kernel void @scalar_or_neg_inline_imm_i64(ptr addrspace(1) %out, [8 x i32], i64 %a) {
; GFX6-LABEL: scalar_or_neg_inline_imm_i64:
; GFX6:       ; %bb.0:
; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x13
; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; GFX6-NEXT:    s_mov_b32 s3, 0xf000
; GFX6-NEXT:    s_mov_b32 s2, -1
; GFX6-NEXT:    v_mov_b32_e32 v1, -1
; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
; GFX6-NEXT:    s_or_b32 s4, s6, -8
; GFX6-NEXT:    v_mov_b32_e32 v0, s4
; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX6-NEXT:    s_endpgm
;
; GFX8-LABEL: scalar_or_neg_inline_imm_i64:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_load_dword s6, s[4:5], 0x4c
; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX8-NEXT:    s_mov_b32 s3, 0xf000
; GFX8-NEXT:    s_mov_b32 s2, -1
; GFX8-NEXT:    v_mov_b32_e32 v1, -1
; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
; GFX8-NEXT:    s_or_b32 s4, s6, -8
; GFX8-NEXT:    v_mov_b32_e32 v0, s4
; GFX8-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX8-NEXT:    s_endpgm
  %or = or i64 %a, -8
  store i64 %or, ptr addrspace(1) %out
  ret void
}

define i32 @vector_or_literal_i32(i32 %a) {
; GFX6-LABEL: vector_or_literal_i32:
; GFX6:       ; %bb.0:
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    v_or_b32_e32 v0, 0xffff, v0
; GFX6-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: vector_or_literal_i32:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_or_b32_e32 v0, 0xffff, v0
; GFX8-NEXT:    s_setpc_b64 s[30:31]
  %or = or i32 %a, 65535
  ret i32 %or
}

define i32 @vector_or_inline_immediate_i32(i32 %a) {
; GFX6-LABEL: vector_or_inline_immediate_i32:
; GFX6:       ; %bb.0:
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    v_or_b32_e32 v0, 4, v0
; GFX6-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: vector_or_inline_immediate_i32:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_or_b32_e32 v0, 4, v0
; GFX8-NEXT:    s_setpc_b64 s[30:31]
  %or = or i32 %a, 4
  ret i32 %or
}

define amdgpu_kernel void @scalar_or_i64(ptr addrspace(1) %out, i64 %a, i64 %b) {
; GFX6-LABEL: scalar_or_i64:
; GFX6:       ; %bb.0:
; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
; GFX6-NEXT:    s_load_dwordx2 s[8:9], s[4:5], 0xd
; GFX6-NEXT:    s_mov_b32 s7, 0xf000
; GFX6-NEXT:    s_mov_b32 s6, -1
; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
; GFX6-NEXT:    s_mov_b32 s4, s0
; GFX6-NEXT:    s_mov_b32 s5, s1
; GFX6-NEXT:    s_or_b64 s[0:1], s[2:3], s[8:9]
; GFX6-NEXT:    v_mov_b32_e32 v0, s0
; GFX6-NEXT:    v_mov_b32_e32 v1, s1
; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX6-NEXT:    s_endpgm
;
; GFX8-LABEL: scalar_or_i64:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8-NEXT:    s_load_dwordx2 s[8:9], s[4:5], 0x34
; GFX8-NEXT:    s_mov_b32 s7, 0xf000
; GFX8-NEXT:    s_mov_b32 s6, -1
; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
; GFX8-NEXT:    s_mov_b32 s4, s0
; GFX8-NEXT:    s_mov_b32 s5, s1
; GFX8-NEXT:    s_or_b64 s[0:1], s[2:3], s[8:9]
; GFX8-NEXT:    v_mov_b32_e32 v0, s0
; GFX8-NEXT:    v_mov_b32_e32 v1, s1
; GFX8-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX8-NEXT:    s_endpgm
  %or = or i64 %a, %b
  store i64 %or, ptr addrspace(1) %out
  ret void
}

define i64 @vector_or_i64(i64 %a, i64 %b) {
; GFX6-LABEL: vector_or_i64:
; GFX6:       ; %bb.0:
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    v_or_b32_e32 v1, v1, v3
; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
; GFX6-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: vector_or_i64:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_or_b32_e32 v1, v1, v3
; GFX8-NEXT:    v_or_b32_e32 v0, v0, v2
; GFX8-NEXT:    s_setpc_b64 s[30:31]
  %or = or i64 %a, %b
  ret i64 %or
}

define i64 @scalar_vector_or_i64(i64 %a, i64 inreg %b) {
; GFX6-LABEL: scalar_vector_or_i64:
; GFX6:       ; %bb.0:
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    v_or_b32_e32 v1, s17, v1
; GFX6-NEXT:    v_or_b32_e32 v0, s16, v0
; GFX6-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: scalar_vector_or_i64:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_or_b32_e32 v1, s17, v1
; GFX8-NEXT:    v_or_b32_e32 v0, s16, v0
; GFX8-NEXT:    s_setpc_b64 s[30:31]
  %or = or i64 %a, %b
  ret i64 %or
}

define i64 @vector_or_i64_loadimm(i64 %a) {
; GFX6-LABEL: vector_or_i64_loadimm:
; GFX6:       ; %bb.0:
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    v_or_b32_e32 v0, 0xdf77987f, v0
; GFX6-NEXT:    v_or_b32_e32 v1, 0x146f, v1
; GFX6-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: vector_or_i64_loadimm:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_or_b32_e32 v0, 0xdf77987f, v0
; GFX8-NEXT:    v_or_b32_e32 v1, 0x146f, v1
; GFX8-NEXT:    s_setpc_b64 s[30:31]
  %or = or i64 %a, 22470723082367
  ret i64 %or
}

; FIXME: The or 0 should really be removed.
define i64 @vector_or_i64_imm(i64 %a) {
; GFX6-LABEL: vector_or_i64_imm:
; GFX6:       ; %bb.0:
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    v_or_b32_e32 v0, 8, v0
; GFX6-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: vector_or_i64_imm:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_or_b32_e32 v0, 8, v0
; GFX8-NEXT:    s_setpc_b64 s[30:31]
  %or = or i64 %a, 8
  ret i64 %or
}

define i64 @vector_or_i64_neg_inline_imm(i64 %a) {
; GFX6-LABEL: vector_or_i64_neg_inline_imm:
; GFX6:       ; %bb.0:
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    v_or_b32_e32 v0, -8, v0
; GFX6-NEXT:    v_mov_b32_e32 v1, -1
; GFX6-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: vector_or_i64_neg_inline_imm:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_or_b32_e32 v0, -8, v0
; GFX8-NEXT:    v_mov_b32_e32 v1, -1
; GFX8-NEXT:    s_setpc_b64 s[30:31]
  %or = or i64 %a, -8
  ret i64 %or
}

define i64 @vector_or_i64_neg_literal(i64 %a) {
; GFX6-LABEL: vector_or_i64_neg_literal:
; GFX6:       ; %bb.0:
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    v_or_b32_e32 v0, 0xffffff38, v0
; GFX6-NEXT:    v_mov_b32_e32 v1, -1
; GFX6-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: vector_or_i64_neg_literal:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_or_b32_e32 v0, 0xffffff38, v0
; GFX8-NEXT:    v_mov_b32_e32 v1, -1
; GFX8-NEXT:    s_setpc_b64 s[30:31]
  %or = or i64 %a, -200
  ret i64 %or
}

define amdgpu_kernel void @trunc_i64_or_to_i32(ptr addrspace(1) %out, [8 x i32], i64 %a, [8 x i32], i64 %b) {
; GFX6-LABEL: trunc_i64_or_to_i32:
; GFX6:       ; %bb.0:
; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x13
; GFX6-NEXT:    s_load_dword s7, s[4:5], 0x1d
; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; GFX6-NEXT:    s_mov_b32 s3, 0xf000
; GFX6-NEXT:    s_mov_b32 s2, -1
; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
; GFX6-NEXT:    s_or_b32 s4, s7, s6
; GFX6-NEXT:    v_mov_b32_e32 v0, s4
; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT:    s_endpgm
;
; GFX8-LABEL: trunc_i64_or_to_i32:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_load_dword s6, s[4:5], 0x4c
; GFX8-NEXT:    s_load_dword s7, s[4:5], 0x74
; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX8-NEXT:    s_mov_b32 s3, 0xf000
; GFX8-NEXT:    s_mov_b32 s2, -1
; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
; GFX8-NEXT:    s_or_b32 s4, s7, s6
; GFX8-NEXT:    v_mov_b32_e32 v0, s4
; GFX8-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; GFX8-NEXT:    s_endpgm
  %add = or i64 %b, %a
  %trunc = trunc i64 %add to i32
  store i32 %trunc, ptr addrspace(1) %out, align 8
  ret void
}

define i32 @or_i1(float %in0, float %in1) {
; GFX6-LABEL: or_i1:
; GFX6:       ; %bb.0:
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    v_mul_f32_e32 v1, 1.0, v1
; GFX6-NEXT:    v_mul_f32_e32 v0, 1.0, v0
; GFX6-NEXT:    v_max_f32_e32 v0, v0, v1
; GFX6-NEXT:    v_cmp_le_f32_e32 vcc, 0, v0
; GFX6-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX6-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: or_i1:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_mul_f32_e32 v1, 1.0, v1
; GFX8-NEXT:    v_mul_f32_e32 v0, 1.0, v0
; GFX8-NEXT:    v_max_f32_e32 v0, v0, v1
; GFX8-NEXT:    v_cmp_le_f32_e32 vcc, 0, v0
; GFX8-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX8-NEXT:    s_setpc_b64 s[30:31]
  %acmp = fcmp oge float %in0, 0.000000e+00
  %bcmp = fcmp oge float %in1, 0.000000e+00
  %or = or i1 %acmp, %bcmp
  %result = zext i1 %or to i32
  ret i32 %result
}

define amdgpu_kernel void @s_or_i1(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c, i32 %d) {
; GFX6-LABEL: s_or_i1:
; GFX6:       ; %bb.0:
; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0xb
; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x9
; GFX6-NEXT:    s_mov_b32 s7, 0xf000
; GFX6-NEXT:    s_mov_b32 s6, -1
; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
; GFX6-NEXT:    s_cmp_eq_u32 s0, s1
; GFX6-NEXT:    s_cselect_b64 s[0:1], -1, 0
; GFX6-NEXT:    s_cmp_eq_u32 s2, s3
; GFX6-NEXT:    s_cselect_b64 s[2:3], -1, 0
; GFX6-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]
; GFX6-NEXT:    s_and_b64 s[0:1], s[0:1], exec
; GFX6-NEXT:    s_cselect_b32 s0, 1, 0
; GFX6-NEXT:    v_mov_b32_e32 v0, s0
; GFX6-NEXT:    buffer_store_byte v0, off, s[4:7], 0
; GFX6-NEXT:    s_endpgm
;
; GFX8-LABEL: s_or_i1:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x2c
; GFX8-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x24
; GFX8-NEXT:    s_mov_b32 s7, 0xf000
; GFX8-NEXT:    s_mov_b32 s6, -1
; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
; GFX8-NEXT:    s_cmp_eq_u32 s0, s1
; GFX8-NEXT:    s_cselect_b64 s[0:1], -1, 0
; GFX8-NEXT:    s_cmp_eq_u32 s2, s3
; GFX8-NEXT:    s_cselect_b64 s[2:3], -1, 0
; GFX8-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]
; GFX8-NEXT:    s_and_b64 s[0:1], s[0:1], exec
; GFX8-NEXT:    s_cselect_b32 s0, 1, 0
; GFX8-NEXT:    v_mov_b32_e32 v0, s0
; GFX8-NEXT:    buffer_store_byte v0, off, s[4:7], 0
; GFX8-NEXT:    s_endpgm
  %cmp0 = icmp eq i32 %a, %b
  %cmp1 = icmp eq i32 %c, %d
  %or = or i1 %cmp0, %cmp1
  store i1 %or, ptr addrspace(1) %out
  ret void
}

; Propagate demanded bits from the LHS to simplify the RHS.

define i32 @s_or_hidden_bits_rhs(i32 inreg %x, i32 inreg %y) {
; GFX6-LABEL: s_or_hidden_bits_rhs:
; GFX6:       ; %bb.0:
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    s_lshr_b32 s4, s17, 24
; GFX6-NEXT:    s_orn2_b32 s4, s16, s4
; GFX6-NEXT:    v_mov_b32_e32 v0, s4
; GFX6-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: s_or_hidden_bits_rhs:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    s_lshr_b32 s4, s17, 24
; GFX8-NEXT:    s_orn2_b32 s4, s16, s4
; GFX8-NEXT:    v_mov_b32_e32 v0, s4
; GFX8-NEXT:    s_setpc_b64 s[30:31]
  %shift = lshr i32 %y, 24
  %bounded = xor i32 %shift, -1
  %inner = and i32 %x, 255
  %result = or i32 %bounded, %inner
  ret i32 %result
}

define i32 @v_or_hidden_bits_rhs(i32 %x, i32 %y) {
; GFX6-LABEL: v_or_hidden_bits_rhs:
; GFX6:       ; %bb.0:
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 24, v1
; GFX6-NEXT:    v_bfi_b32 v0, v1, v0, -1
; GFX6-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_or_hidden_bits_rhs:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_lshrrev_b32_e32 v1, 24, v1
; GFX8-NEXT:    v_bfi_b32 v0, v1, v0, -1
; GFX8-NEXT:    s_setpc_b64 s[30:31]
  %shift = lshr i32 %y, 24
  %bounded = xor i32 %shift, -1
  %inner = and i32 %x, 255
  %result = or i32 %bounded, %inner
  ret i32 %result
}