llvm/test/CodeGen/AMDGPU/optimize-compare-cselect.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=amdgpu9.00 -run-pass=peephole-opt -o - %s | FileCheck %s

# Compares of (S_CSELECT* A, B) against A or B, where A != B, recompute SCC or
# its inverse.

# sel == 1 iff SCC, so s_cmp_lg sel, 1 is !SCC.
---
name:            cselect_b32_1_0_cmp_lg_1
body:             |
  ; CHECK-LABEL: name: cselect_b32_1_0_cmp_lg_1
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT:   liveins: $sgpr0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  ; CHECK-NEXT:   S_CMP_LG_U32 [[COPY]], 0, implicit-def $scc
  ; CHECK-NEXT:   [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 1, 0, implicit $scc
  ; CHECK-NEXT:   S_CBRANCH_SCC1 %bb.2, implicit $scc
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   S_ENDPGM 0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    liveins: $sgpr0

    %0:sreg_32 = COPY $sgpr0
    S_CMP_LG_U32 %0, 0, implicit-def $scc
    %1:sreg_32 = S_CSELECT_B32 1, 0, implicit $scc
    S_CMP_LG_U32 %1, 1, implicit-def $scc
    S_CBRANCH_SCC0 %bb.2, implicit $scc
    S_BRANCH %bb.1

  bb.1:
    S_ENDPGM 0

  bb.2:
    S_ENDPGM 0
...

# sel == 1 iff SCC, so s_cmp_eq sel, 1 is SCC.
---
name:            cselect_b32_1_0_cmp_eq_1
body:             |
  ; CHECK-LABEL: name: cselect_b32_1_0_cmp_eq_1
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT:   liveins: $sgpr0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  ; CHECK-NEXT:   S_CMP_LG_U32 [[COPY]], 0, implicit-def $scc
  ; CHECK-NEXT:   [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 1, 0, implicit $scc
  ; CHECK-NEXT:   S_CBRANCH_SCC0 %bb.2, implicit $scc
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   S_ENDPGM 0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    liveins: $sgpr0

    %0:sreg_32 = COPY $sgpr0
    S_CMP_LG_U32 %0, 0, implicit-def $scc
    %1:sreg_32 = S_CSELECT_B32 1, 0, implicit $scc
    S_CMP_EQ_U32 %1, 1, implicit-def $scc
    S_CBRANCH_SCC0 %bb.2, implicit $scc
    S_BRANCH %bb.1

  bb.1:
    S_ENDPGM 0

  bb.2:
    S_ENDPGM 0
...

# Neither constant is zero. s_cmp_eq sel, 7 is !SCC.
---
name:            cselect_b32_5_7_cmp_eq_7
body:             |
  ; CHECK-LABEL: name: cselect_b32_5_7_cmp_eq_7
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT:   liveins: $sgpr0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  ; CHECK-NEXT:   S_CMP_LG_U32 [[COPY]], 0, implicit-def $scc
  ; CHECK-NEXT:   [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 5, 7, implicit $scc
  ; CHECK-NEXT:   S_CBRANCH_SCC1 %bb.2, implicit $scc
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   S_ENDPGM 0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    liveins: $sgpr0

    %0:sreg_32 = COPY $sgpr0
    S_CMP_LG_U32 %0, 0, implicit-def $scc
    %1:sreg_32 = S_CSELECT_B32 5, 7, implicit $scc
    S_CMP_EQ_U32 %1, 7, implicit-def $scc
    S_CBRANCH_SCC0 %bb.2, implicit $scc
    S_BRANCH %bb.1

  bb.1:
    S_ENDPGM 0

  bb.2:
    S_ENDPGM 0
...

# Neither constant is zero. s_cmp_lg sel, 7 is SCC.
---
name:            cselect_b32_5_7_cmp_lg_7
body:             |
  ; CHECK-LABEL: name: cselect_b32_5_7_cmp_lg_7
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT:   liveins: $sgpr0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  ; CHECK-NEXT:   S_CMP_LG_U32 [[COPY]], 0, implicit-def $scc
  ; CHECK-NEXT:   [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 5, 7, implicit $scc
  ; CHECK-NEXT:   S_CBRANCH_SCC0 %bb.2, implicit $scc
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   S_ENDPGM 0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    liveins: $sgpr0

    %0:sreg_32 = COPY $sgpr0
    S_CMP_LG_U32 %0, 0, implicit-def $scc
    %1:sreg_32 = S_CSELECT_B32 5, 7, implicit $scc
    S_CMP_LG_U32 %1, 7, implicit-def $scc
    S_CBRANCH_SCC0 %bb.2, implicit $scc
    S_BRANCH %bb.1

  bb.1:
    S_ENDPGM 0

  bb.2:
    S_ENDPGM 0
...

# The compared value is neither constant, so the result does not depend on SCC.
# Leave it alone.
---
name:            cselect_b32_5_7_cmp_eq_6
body:             |
  ; CHECK-LABEL: name: cselect_b32_5_7_cmp_eq_6
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT:   liveins: $sgpr0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  ; CHECK-NEXT:   S_CMP_LG_U32 [[COPY]], 0, implicit-def $scc
  ; CHECK-NEXT:   [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 5, 7, implicit $scc
  ; CHECK-NEXT:   S_CMP_EQ_U32 [[S_CSELECT_B32_]], 6, implicit-def $scc
  ; CHECK-NEXT:   S_CBRANCH_SCC0 %bb.2, implicit $scc
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   S_ENDPGM 0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    liveins: $sgpr0

    %0:sreg_32 = COPY $sgpr0
    S_CMP_LG_U32 %0, 0, implicit-def $scc
    %1:sreg_32 = S_CSELECT_B32 5, 7, implicit $scc
    S_CMP_EQ_U32 %1, 6, implicit-def $scc
    S_CBRANCH_SCC0 %bb.2, implicit $scc
    S_BRANCH %bb.1

  bb.1:
    S_ENDPGM 0

  bb.2:
    S_ENDPGM 0
...

# Both constants are equal, so the result does not depend on SCC.
---
name:            cselect_b32_3_3_cmp_eq_3
body:             |
  ; CHECK-LABEL: name: cselect_b32_3_3_cmp_eq_3
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT:   liveins: $sgpr0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  ; CHECK-NEXT:   S_CMP_LG_U32 [[COPY]], 0, implicit-def $scc
  ; CHECK-NEXT:   [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 3, 3, implicit $scc
  ; CHECK-NEXT:   S_CMP_EQ_U32 [[S_CSELECT_B32_]], 3, implicit-def $scc
  ; CHECK-NEXT:   S_CBRANCH_SCC0 %bb.2, implicit $scc
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   S_ENDPGM 0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    liveins: $sgpr0

    %0:sreg_32 = COPY $sgpr0
    S_CMP_LG_U32 %0, 0, implicit-def $scc
    %1:sreg_32 = S_CSELECT_B32 3, 3, implicit $scc
    S_CMP_EQ_U32 %1, 3, implicit-def $scc
    S_CBRANCH_SCC0 %bb.2, implicit $scc
    S_BRANCH %bb.1

  bb.1:
    S_ENDPGM 0

  bb.2:
    S_ENDPGM 0
...

# -1 and 0xffffffff are equal in 32 bits.
---
name:            cselect_b32_m1_0_cmp_lg_0xffffffff
body:             |
  ; CHECK-LABEL: name: cselect_b32_m1_0_cmp_lg_0xffffffff
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT:   liveins: $sgpr0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  ; CHECK-NEXT:   S_CMP_LG_U32 [[COPY]], 0, implicit-def $scc
  ; CHECK-NEXT:   [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 -1, 0, implicit $scc
  ; CHECK-NEXT:   S_CBRANCH_SCC1 %bb.2, implicit $scc
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   S_ENDPGM 0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    liveins: $sgpr0

    %0:sreg_32 = COPY $sgpr0
    S_CMP_LG_U32 %0, 0, implicit-def $scc
    %1:sreg_32 = S_CSELECT_B32 -1, 0, implicit $scc
    S_CMP_LG_U32 %1, 4294967295, implicit-def $scc
    S_CBRANCH_SCC0 %bb.2, implicit $scc
    S_BRANCH %bb.1

  bb.1:
    S_ENDPGM 0

  bb.2:
    S_ENDPGM 0
...

# S_CMPK form.
---
name:            cselect_b32_0_0xffff_cmpk_eq_0xffff
body:             |
  ; CHECK-LABEL: name: cselect_b32_0_0xffff_cmpk_eq_0xffff
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT:   liveins: $sgpr0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  ; CHECK-NEXT:   S_CMP_LG_U32 [[COPY]], 0, implicit-def $scc
  ; CHECK-NEXT:   [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 0, 65535, implicit $scc
  ; CHECK-NEXT:   S_CBRANCH_SCC1 %bb.2, implicit $scc
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   S_ENDPGM 0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    liveins: $sgpr0

    %0:sreg_32 = COPY $sgpr0
    S_CMP_LG_U32 %0, 0, implicit-def $scc
    %1:sreg_32 = S_CSELECT_B32 0, 65535, implicit $scc
    S_CMPK_EQ_U32 %1, 65535, implicit-def $scc
    S_CBRANCH_SCC0 %bb.2, implicit $scc
    S_BRANCH %bb.1

  bb.1:
    S_ENDPGM 0

  bb.2:
    S_ENDPGM 0
...

# Select and compare operands materialized with S_MOV_B32.
---
name:            cselect_b32_materialized
body:             |
  ; CHECK-LABEL: name: cselect_b32_materialized
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT:   liveins: $sgpr0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  ; CHECK-NEXT:   S_CMP_LG_U32 [[COPY]], 0, implicit-def $scc
  ; CHECK-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 3
  ; CHECK-NEXT:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 4
  ; CHECK-NEXT:   [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[S_MOV_B32_]], [[S_MOV_B32_1]], implicit $scc
  ; CHECK-NEXT:   S_CBRANCH_SCC0 %bb.2, implicit $scc
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   S_ENDPGM 0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    liveins: $sgpr0

    %0:sreg_32 = COPY $sgpr0
    S_CMP_LG_U32 %0, 0, implicit-def $scc
    %2:sreg_32 = S_MOV_B32 3
    %3:sreg_32 = S_MOV_B32 4
    %1:sreg_32 = S_CSELECT_B32 %2, %3, implicit $scc
    S_CMP_EQ_U32 %1, %2, implicit-def $scc
    S_CBRANCH_SCC0 %bb.2, implicit $scc
    S_BRANCH %bb.1

  bb.1:
    S_ENDPGM 0

  bb.2:
    S_ENDPGM 0
...

# 64-bit select and compare.
---
name:            cselect_b64_2_3_cmp_eq_3
body:             |
  ; CHECK-LABEL: name: cselect_b64_2_3_cmp_eq_3
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT:   liveins: $sgpr0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  ; CHECK-NEXT:   S_CMP_LG_U32 [[COPY]], 0, implicit-def $scc
  ; CHECK-NEXT:   [[S_CSELECT_B64_:%[0-9]+]]:sreg_64 = S_CSELECT_B64 2, 3, implicit $scc
  ; CHECK-NEXT:   S_CBRANCH_SCC1 %bb.2, implicit $scc
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   S_ENDPGM 0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    liveins: $sgpr0

    %0:sreg_32 = COPY $sgpr0
    S_CMP_LG_U32 %0, 0, implicit-def $scc
    %1:sreg_64 = S_CSELECT_B64 2, 3, implicit $scc
    S_CMP_EQ_U64 %1, 3, implicit-def $scc
    S_CBRANCH_SCC0 %bb.2, implicit $scc
    S_BRANCH %bb.1

  bb.1:
    S_ENDPGM 0

  bb.2:
    S_ENDPGM 0
...

# -1 and 0xffffffff are different in 64 bits. Leave it alone.
---
name:            cselect_b64_m1_0_cmp_lg_0xffffffff
body:             |
  ; CHECK-LABEL: name: cselect_b64_m1_0_cmp_lg_0xffffffff
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT:   liveins: $sgpr0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  ; CHECK-NEXT:   S_CMP_LG_U32 [[COPY]], 0, implicit-def $scc
  ; CHECK-NEXT:   [[S_CSELECT_B64_:%[0-9]+]]:sreg_64 = S_CSELECT_B64 -1, 0, implicit $scc
  ; CHECK-NEXT:   S_CMP_LG_U64 [[S_CSELECT_B64_]], 4294967295, implicit-def $scc
  ; CHECK-NEXT:   S_CBRANCH_SCC0 %bb.2, implicit $scc
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   S_ENDPGM 0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    liveins: $sgpr0

    %0:sreg_32 = COPY $sgpr0
    S_CMP_LG_U32 %0, 0, implicit-def $scc
    %1:sreg_64 = S_CSELECT_B64 -1, 0, implicit $scc
    S_CMP_LG_U64 %1, 4294967295, implicit-def $scc
    S_CBRANCH_SCC0 %bb.2, implicit $scc
    S_BRANCH %bb.1

  bb.1:
    S_ENDPGM 0

  bb.2:
    S_ENDPGM 0
...