llvm/test/CodeGen/AMDGPU/lower-term-opcodes.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgpu10.10 -run-pass=si-optimize-exec-masking -verify-machineinstrs  %s -o - | FileCheck %s
# RUN: llc -mtriple=amdgpu11.00 -run-pass=si-optimize-exec-masking -verify-machineinstrs  %s -o - | FileCheck %s

# RUN: llc -mtriple=amdgpu10.10 -passes=si-optimize-exec-masking -verify-machineinstrs  %s -o - | FileCheck %s
# RUN: llc -mtriple=amdgpu11.00 -passes=si-optimize-exec-masking -verify-machineinstrs  %s -o - | FileCheck %s
---
name: lower_term_opcodes
tracksRegLiveness: false
body: |
  ; CHECK-LABEL: name: lower_term_opcodes
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $sgpr0 = COPY $sgpr1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $sgpr0 = S_MOV_B32 0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $sgpr0 = S_MOV_B32 &SYMBOL
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3:
  ; CHECK-NEXT:   successors: %bb.4(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $sgpr0_sgpr1 = COPY $sgpr2_sgpr3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.4:
  ; CHECK-NEXT:   successors: %bb.5(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $sgpr0_sgpr1 = S_MOV_B64 0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.5:
  ; CHECK-NEXT:   successors: %bb.6(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $sgpr0_sgpr1 = S_MOV_B64 &SYMBOL
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.6:
  ; CHECK-NEXT:   successors: %bb.7(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $sgpr0 = S_XOR_B32 $sgpr1, $sgpr2, implicit-def $scc
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.7:
  ; CHECK-NEXT:   successors: %bb.8(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $sgpr0_sgpr1 = S_XOR_B64 $sgpr2_sgpr3, $sgpr2_sgpr3, implicit-def $scc
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.8:
  ; CHECK-NEXT:   successors: %bb.9(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $sgpr0 = S_OR_B32 $sgpr1, $sgpr2, implicit-def $scc
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.9:
  ; CHECK-NEXT:   successors: %bb.10(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $sgpr0_sgpr1 = S_OR_B64 $sgpr2_sgpr3, $sgpr2_sgpr3, implicit-def $scc
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.10:
  ; CHECK-NEXT:   successors: %bb.11(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $sgpr0 = S_ANDN2_B32 $sgpr1, $sgpr2, implicit-def $scc
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.11:
  ; CHECK-NEXT:   $sgpr0_sgpr1 = S_ANDN2_B64 $sgpr2_sgpr3, $sgpr2_sgpr3, implicit-def $scc
  bb.0:
    $sgpr0 = S_MOV_B32_term $sgpr1

  bb.1:
    $sgpr0 = S_MOV_B32_term 0

  bb.3:
    $sgpr0 = S_MOV_B32_term &SYMBOL

  bb.4:
    $sgpr0_sgpr1 = S_MOV_B64_term $sgpr2_sgpr3

  bb.5:
    $sgpr0_sgpr1 = S_MOV_B64_term 0

  bb.6:
    $sgpr0_sgpr1 = S_MOV_B64_term &SYMBOL

  bb.7:
    $sgpr0 = S_XOR_B32_term $sgpr1, $sgpr2, implicit-def $scc

  bb.8:
    $sgpr0_sgpr1 = S_XOR_B64_term $sgpr2_sgpr3, $sgpr2_sgpr3, implicit-def $scc

  bb.9:
    $sgpr0 = S_OR_B32_term $sgpr1, $sgpr2, implicit-def $scc

  bb.10:
    $sgpr0_sgpr1 = S_OR_B64_term $sgpr2_sgpr3, $sgpr2_sgpr3, implicit-def $scc

  bb.11:
    $sgpr0 = S_ANDN2_B32_term $sgpr1, $sgpr2, implicit-def $scc

  bb.12:
    $sgpr0_sgpr1 = S_ANDN2_B64_term $sgpr2_sgpr3, $sgpr2_sgpr3, implicit-def $scc
...