llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=SI %s
; RUN: llc -mtriple=amdgpu8.03 < %s | FileCheck -check-prefixes=VI %s
; RUN: llc -global-isel=0 -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11-TRUE16,GFX11-TRUE16-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11-TRUE16,GFX11-TRUE16-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11-FAKE16,GFX11-FAKE16-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11-FAKE16,GFX11-FAKE16-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgpu12.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12-TRUE16,GFX12-TRUE16-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgpu12.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12-TRUE16,GFX12-TRUE16-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgpu12.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12-FAKE16,GFX12-FAKE16-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgpu12.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12-FAKE16,GFX12-FAKE16-GISEL %s

declare half @llvm.sqrt.f16(half %a)
declare <2 x half> @llvm.sqrt.v2f16(<2 x half> %a)

define half @sqrt_f16(half %a) {
; SI-LABEL: sqrt_f16:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_sqrt_f32_e32 v0, v0
; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: sqrt_f16:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_sqrt_f16_e32 v0, v0
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: sqrt_f16:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_sqrt_f16_e32 v0.l, v0.l
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: sqrt_f16:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_sqrt_f16_e32 v0, v0
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: sqrt_f16:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_sqrt_f16_e32 v0.l, v0.l
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: sqrt_f16:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_sqrt_f16_e32 v0, v0
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %r.val = call half @llvm.sqrt.f16(half %a)
  ret half %r.val
}

; The original test with manual checks also had these NOT directives:
; COM: SI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]]
; COM: SI-NOT: v_and_b32
; COM: SI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_HI]]
; COM: VI-DAG: v_sqrt_f16_sdwa v[[R_F16_1:[0-9]+]], v[[A_V2_F16]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
; COM: VI-NOT: v_and_b32
; COM: VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_1]]
define <2 x half> @sqrt_v2f16(<2 x half> %a) {
; SI-LABEL: sqrt_v2f16:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_sqrt_f32_e32 v1, v1
; SI-NEXT:    v_sqrt_f32_e32 v0, v0
; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1
; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT:    v_or_b32_e32 v0, v0, v1
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: sqrt_v2f16:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_sqrt_f16_sdwa v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
; VI-NEXT:    v_sqrt_f16_e32 v0, v0
; VI-NEXT:    v_or_b32_e32 v0, v0, v1
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: sqrt_v2f16:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_sqrt_f16_e32 v0.l, v0.l
; GFX11-TRUE16-NEXT:    v_sqrt_f16_e32 v0.h, v0.h
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: sqrt_v2f16:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
; GFX11-FAKE16-NEXT:    v_sqrt_f16_e32 v0, v0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_sqrt_f16_e32 v1, v1
; GFX11-FAKE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: sqrt_v2f16:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_sqrt_f16_e32 v0.l, v0.l
; GFX12-TRUE16-NEXT:    v_sqrt_f16_e32 v0.h, v0.h
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: sqrt_v2f16:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
; GFX12-FAKE16-NEXT:    v_sqrt_f16_e32 v0, v0
; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1)
; GFX12-FAKE16-NEXT:    v_sqrt_f16_e32 v1, v1
; GFX12-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %r.val = call <2 x half> @llvm.sqrt.v2f16(<2 x half> %a)
  ret <2 x half> %r.val
}

define amdgpu_ps half @sqrt_f16_s(half inreg %x) {
; SI-LABEL: sqrt_f16_s:
; SI:       ; %bb.0:
; SI-NEXT:    v_cvt_f32_f16_e32 v0, s0
; SI-NEXT:    v_sqrt_f32_e32 v0, v0
; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-NEXT:    ; return to shader part epilog
;
; VI-LABEL: sqrt_f16_s:
; VI:       ; %bb.0:
; VI-NEXT:    v_sqrt_f16_e32 v0, s0
; VI-NEXT:    ; return to shader part epilog
;
; GFX11-TRUE16-LABEL: sqrt_f16_s:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    v_sqrt_f16_e32 v0.l, s0
; GFX11-TRUE16-NEXT:    ; return to shader part epilog
;
; GFX11-FAKE16-LABEL: sqrt_f16_s:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    v_sqrt_f16_e32 v0, s0
; GFX11-FAKE16-NEXT:    ; return to shader part epilog
;
; GFX12-TRUE16-LABEL: sqrt_f16_s:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    v_s_sqrt_f16 s0, s0
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1)
; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v0, s0
; GFX12-TRUE16-NEXT:    ; return to shader part epilog
;
; GFX12-FAKE16-LABEL: sqrt_f16_s:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    v_s_sqrt_f16 s0, s0
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1)
; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v0, s0
; GFX12-FAKE16-NEXT:    ; return to shader part epilog
  %result = call half @llvm.sqrt.f16(half %x)
  ret half %result
}

define amdgpu_ps half @sqrt_f16_v(half %x) {
; SI-LABEL: sqrt_f16_v:
; SI:       ; %bb.0:
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_sqrt_f32_e32 v0, v0
; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-NEXT:    ; return to shader part epilog
;
; VI-LABEL: sqrt_f16_v:
; VI:       ; %bb.0:
; VI-NEXT:    v_sqrt_f16_e32 v0, v0
; VI-NEXT:    ; return to shader part epilog
;
; GFX11-TRUE16-LABEL: sqrt_f16_v:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    v_sqrt_f16_e32 v0.l, v0.l
; GFX11-TRUE16-NEXT:    ; return to shader part epilog
;
; GFX11-FAKE16-LABEL: sqrt_f16_v:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    v_sqrt_f16_e32 v0, v0
; GFX11-FAKE16-NEXT:    ; return to shader part epilog
;
; GFX12-TRUE16-LABEL: sqrt_f16_v:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    v_sqrt_f16_e32 v0.l, v0.l
; GFX12-TRUE16-NEXT:    ; return to shader part epilog
;
; GFX12-FAKE16-LABEL: sqrt_f16_v:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    v_sqrt_f16_e32 v0, v0
; GFX12-FAKE16-NEXT:    ; return to shader part epilog
  %result = call half @llvm.sqrt.f16(half %x)
  ret half %result
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX11-FAKE16-GISEL: {{.*}}
; GFX11-FAKE16-SDAG: {{.*}}
; GFX11-TRUE16-GISEL: {{.*}}
; GFX11-TRUE16-SDAG: {{.*}}
; GFX12-FAKE16-GISEL: {{.*}}
; GFX12-FAKE16-SDAG: {{.*}}
; GFX12-TRUE16-GISEL: {{.*}}
; GFX12-TRUE16-SDAG: {{.*}}