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llvm/llvm-project/refs/heads/users/void/array-bounds-accessed/./llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll
blob: d56cd0ab863a49d54088310c5fddd3ebfc2162f6 [file] [edit]
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI,SIVI %s
; RUN: llc -mtriple=amdgpu8.03 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,SIVI,VIGFX9 %s
; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,VIGFX9 %s
declare half @llvm.fma.f16(half %a, half %b, half %c)
declare <2 x half> @llvm.fma.v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c)
declare <4 x half> @llvm.fma.v4f16(<4 x half> %a, <4 x half> %b, <4 x half> %c)
define half @fma_f16(half %a, half %b, half %c) {
; SI-LABEL: fma_f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
; SI-NEXT: v_cvt_f32_f16_e32 v3, v1
; SI-NEXT: v_cvt_f32_f16_e32 v4, v0
; SI-NEXT: s_movk_i32 s4, 0x3f1
; SI-NEXT: v_cvt_f64_f32_e32 v[0:1], v2
; SI-NEXT: v_cvt_f64_f32_e32 v[2:3], v3
; SI-NEXT: v_cvt_f64_f32_e32 v[4:5], v4
; SI-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
; SI-NEXT: v_and_b32_e32 v2, 0x1ff, v1
; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_lshrrev_b32_e32 v2, 8, v1
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v2, 0xffe, v2
; SI-NEXT: v_bfe_u32 v3, v1, 20, 11
; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_sub_i32_e32 v4, vcc, s4, v3
; SI-NEXT: v_or_b32_e32 v2, 0x1000, v0
; SI-NEXT: v_med3_i32 v4, v4, 0, 13
; SI-NEXT: v_lshrrev_b32_e32 v5, v4, v2
; SI-NEXT: v_lshlrev_b32_e32 v4, v4, v5
; SI-NEXT: v_cmp_ne_u32_e32 vcc, v4, v2
; SI-NEXT: s_movk_i32 s4, 0xfc10
; SI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; SI-NEXT: v_add_i32_e32 v3, vcc, s4, v3
; SI-NEXT: v_lshlrev_b32_e32 v4, 12, v3
; SI-NEXT: v_or_b32_e32 v2, v5, v2
; SI-NEXT: v_or_b32_e32 v4, v0, v4
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
; SI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; SI-NEXT: v_and_b32_e32 v4, 7, v2
; SI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v4
; SI-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v4
; SI-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_lshrrev_b32_e32 v2, 2, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; SI-NEXT: v_mov_b32_e32 v4, 0x7c00
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v3
; SI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; SI-NEXT: v_mov_b32_e32 v5, 0x7e00
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: s_movk_i32 s4, 0x40f
; SI-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, s4, v3
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; SI-NEXT: v_and_b32_e32 v1, 0x8000, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: fma_f16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_fma_f16 v0, v0, v1, v2
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: fma_f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_fma_f16 v0, v0, v1, v2
; GFX9-NEXT: s_setpc_b64 s[30:31]
%r.val = call half @llvm.fma.f16(half %a, half %b, half %c)
ret half %r.val
}
define half @fma_f16_imm_a(half %b, half %c) {
; SI-LABEL: fma_f16_imm_a:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: v_cvt_f32_f16_e32 v2, v0
; SI-NEXT: s_mov_b32 s4, 0
; SI-NEXT: s_mov_b32 s5, 0x40080000
; SI-NEXT: v_cvt_f64_f32_e32 v[0:1], v1
; SI-NEXT: v_cvt_f64_f32_e32 v[2:3], v2
; SI-NEXT: v_fma_f64 v[0:1], v[2:3], s[4:5], v[0:1]
; SI-NEXT: s_movk_i32 s4, 0x3f1
; SI-NEXT: v_and_b32_e32 v2, 0x1ff, v1
; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_lshrrev_b32_e32 v3, 8, v1
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v2, 0xffe, v3
; SI-NEXT: v_bfe_u32 v3, v1, 20, 11
; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_sub_i32_e32 v4, vcc, s4, v3
; SI-NEXT: v_or_b32_e32 v2, 0x1000, v0
; SI-NEXT: v_med3_i32 v4, v4, 0, 13
; SI-NEXT: v_lshrrev_b32_e32 v5, v4, v2
; SI-NEXT: v_lshlrev_b32_e32 v4, v4, v5
; SI-NEXT: v_cmp_ne_u32_e32 vcc, v4, v2
; SI-NEXT: s_movk_i32 s4, 0xfc10
; SI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; SI-NEXT: v_add_i32_e32 v3, vcc, s4, v3
; SI-NEXT: v_lshlrev_b32_e32 v4, 12, v3
; SI-NEXT: v_or_b32_e32 v2, v5, v2
; SI-NEXT: v_or_b32_e32 v4, v0, v4
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
; SI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; SI-NEXT: v_and_b32_e32 v4, 7, v2
; SI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v4
; SI-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v4
; SI-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_lshrrev_b32_e32 v2, 2, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; SI-NEXT: v_mov_b32_e32 v4, 0x7c00
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v3
; SI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; SI-NEXT: v_mov_b32_e32 v5, 0x7e00
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: s_movk_i32 s4, 0x40f
; SI-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, s4, v3
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; SI-NEXT: v_and_b32_e32 v1, 0x8000, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: fma_f16_imm_a:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_movk_i32 s4, 0x4200
; VI-NEXT: v_fma_f16 v0, v0, s4, v1
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: fma_f16_imm_a:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_movk_i32 s4, 0x4200
; GFX9-NEXT: v_fma_f16 v0, v0, s4, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
%r.val = call half @llvm.fma.f16(half 3.0, half %b, half %c)
ret half %r.val
}
define half @fma_f16_imm_b(half %a, half %c) {
; SI-LABEL: fma_f16_imm_b:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: v_cvt_f32_f16_e32 v2, v0
; SI-NEXT: s_mov_b32 s4, 0
; SI-NEXT: s_mov_b32 s5, 0x40080000
; SI-NEXT: v_cvt_f64_f32_e32 v[0:1], v1
; SI-NEXT: v_cvt_f64_f32_e32 v[2:3], v2
; SI-NEXT: v_fma_f64 v[0:1], v[2:3], s[4:5], v[0:1]
; SI-NEXT: s_movk_i32 s4, 0x3f1
; SI-NEXT: v_and_b32_e32 v2, 0x1ff, v1
; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_lshrrev_b32_e32 v3, 8, v1
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v2, 0xffe, v3
; SI-NEXT: v_bfe_u32 v3, v1, 20, 11
; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_sub_i32_e32 v4, vcc, s4, v3
; SI-NEXT: v_or_b32_e32 v2, 0x1000, v0
; SI-NEXT: v_med3_i32 v4, v4, 0, 13
; SI-NEXT: v_lshrrev_b32_e32 v5, v4, v2
; SI-NEXT: v_lshlrev_b32_e32 v4, v4, v5
; SI-NEXT: v_cmp_ne_u32_e32 vcc, v4, v2
; SI-NEXT: s_movk_i32 s4, 0xfc10
; SI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; SI-NEXT: v_add_i32_e32 v3, vcc, s4, v3
; SI-NEXT: v_lshlrev_b32_e32 v4, 12, v3
; SI-NEXT: v_or_b32_e32 v2, v5, v2
; SI-NEXT: v_or_b32_e32 v4, v0, v4
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
; SI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; SI-NEXT: v_and_b32_e32 v4, 7, v2
; SI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v4
; SI-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v4
; SI-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_lshrrev_b32_e32 v2, 2, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; SI-NEXT: v_mov_b32_e32 v4, 0x7c00
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v3
; SI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; SI-NEXT: v_mov_b32_e32 v5, 0x7e00
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: s_movk_i32 s4, 0x40f
; SI-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, s4, v3
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; SI-NEXT: v_and_b32_e32 v1, 0x8000, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: fma_f16_imm_b:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_movk_i32 s4, 0x4200
; VI-NEXT: v_fma_f16 v0, v0, s4, v1
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: fma_f16_imm_b:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_movk_i32 s4, 0x4200
; GFX9-NEXT: v_fma_f16 v0, v0, s4, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
%r.val = call half @llvm.fma.f16(half %a, half 3.0, half %c)
ret half %r.val
}
define half @fma_f16_imm_c(half %a, half %b) {
; SI-LABEL: fma_f16_imm_c:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: v_cvt_f32_f16_e32 v2, v0
; SI-NEXT: s_mov_b32 s4, 0
; SI-NEXT: s_mov_b32 s5, 0x40080000
; SI-NEXT: v_cvt_f64_f32_e32 v[0:1], v1
; SI-NEXT: v_cvt_f64_f32_e32 v[2:3], v2
; SI-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], s[4:5]
; SI-NEXT: s_movk_i32 s4, 0x3f1
; SI-NEXT: v_and_b32_e32 v2, 0x1ff, v1
; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_lshrrev_b32_e32 v3, 8, v1
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v2, 0xffe, v3
; SI-NEXT: v_bfe_u32 v3, v1, 20, 11
; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_sub_i32_e32 v4, vcc, s4, v3
; SI-NEXT: v_or_b32_e32 v2, 0x1000, v0
; SI-NEXT: v_med3_i32 v4, v4, 0, 13
; SI-NEXT: v_lshrrev_b32_e32 v5, v4, v2
; SI-NEXT: v_lshlrev_b32_e32 v4, v4, v5
; SI-NEXT: v_cmp_ne_u32_e32 vcc, v4, v2
; SI-NEXT: s_movk_i32 s4, 0xfc10
; SI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; SI-NEXT: v_add_i32_e32 v3, vcc, s4, v3
; SI-NEXT: v_lshlrev_b32_e32 v4, 12, v3
; SI-NEXT: v_or_b32_e32 v2, v5, v2
; SI-NEXT: v_or_b32_e32 v4, v0, v4
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
; SI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; SI-NEXT: v_and_b32_e32 v4, 7, v2
; SI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v4
; SI-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v4
; SI-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_lshrrev_b32_e32 v2, 2, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; SI-NEXT: v_mov_b32_e32 v4, 0x7c00
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v3
; SI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; SI-NEXT: v_mov_b32_e32 v5, 0x7e00
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: s_movk_i32 s4, 0x40f
; SI-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, s4, v3
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; SI-NEXT: v_and_b32_e32 v1, 0x8000, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: fma_f16_imm_c:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_movk_i32 s4, 0x4200
; VI-NEXT: v_fma_f16 v0, v0, v1, s4
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: fma_f16_imm_c:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_movk_i32 s4, 0x4200
; GFX9-NEXT: v_fma_f16 v0, v0, v1, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
%r.val = call half @llvm.fma.f16(half %a, half %b, half 3.0)
ret half %r.val
}
define <2 x half> @fma_v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c) {
; SI-LABEL: fma_v2f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v1
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
; SI-NEXT: v_cvt_f32_f16_e32 v6, v4
; SI-NEXT: v_cvt_f32_f16_e32 v7, v3
; SI-NEXT: s_movk_i32 s4, 0x3f1
; SI-NEXT: v_cvt_f64_f32_e32 v[3:4], v5
; SI-NEXT: v_cvt_f64_f32_e32 v[5:6], v6
; SI-NEXT: v_cvt_f64_f32_e32 v[7:8], v7
; SI-NEXT: s_movk_i32 s5, 0xfc10
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
; SI-NEXT: v_cvt_f32_f16_e32 v9, v1
; SI-NEXT: v_fma_f64 v[3:4], v[7:8], v[5:6], v[3:4]
; SI-NEXT: v_cvt_f32_f16_e32 v10, v0
; SI-NEXT: v_and_b32_e32 v5, 0x1ff, v4
; SI-NEXT: v_or_b32_e32 v3, v5, v3
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; SI-NEXT: v_lshrrev_b32_e32 v5, 8, v4
; SI-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v5, 0xffe, v5
; SI-NEXT: v_bfe_u32 v6, v4, 20, 11
; SI-NEXT: v_or_b32_e32 v3, v5, v3
; SI-NEXT: v_sub_i32_e32 v7, vcc, s4, v6
; SI-NEXT: v_or_b32_e32 v5, 0x1000, v3
; SI-NEXT: v_med3_i32 v7, v7, 0, 13
; SI-NEXT: v_lshrrev_b32_e32 v8, v7, v5
; SI-NEXT: v_lshlrev_b32_e32 v7, v7, v8
; SI-NEXT: v_cmp_ne_u32_e32 vcc, v7, v5
; SI-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; SI-NEXT: v_add_i32_e32 v6, vcc, s5, v6
; SI-NEXT: v_lshlrev_b32_e32 v7, 12, v6
; SI-NEXT: v_or_b32_e32 v5, v8, v5
; SI-NEXT: v_or_b32_e32 v7, v3, v7
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v6
; SI-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc
; SI-NEXT: v_and_b32_e32 v7, 7, v5
; SI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v7
; SI-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v7
; SI-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_lshrrev_b32_e32 v5, 2, v5
; SI-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; SI-NEXT: v_mov_b32_e32 v7, 0x7c00
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v6
; SI-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc
; SI-NEXT: v_mov_b32_e32 v8, 0x7e00
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; SI-NEXT: s_movk_i32 s6, 0x40f
; SI-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v6
; SI-NEXT: v_cndmask_b32_e32 v11, v5, v3, vcc
; SI-NEXT: v_cvt_f64_f32_e32 v[0:1], v2
; SI-NEXT: v_cvt_f64_f32_e32 v[2:3], v9
; SI-NEXT: v_cvt_f64_f32_e32 v[5:6], v10
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; SI-NEXT: v_and_b32_e32 v4, 0x8000, v4
; SI-NEXT: v_or_b32_e32 v4, v4, v11
; SI-NEXT: v_fma_f64 v[0:1], v[5:6], v[2:3], v[0:1]
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v4
; SI-NEXT: v_and_b32_e32 v3, 0x1ff, v1
; SI-NEXT: v_or_b32_e32 v0, v3, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_lshrrev_b32_e32 v3, 8, v1
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v3, 0xffe, v3
; SI-NEXT: v_bfe_u32 v4, v1, 20, 11
; SI-NEXT: v_or_b32_e32 v0, v3, v0
; SI-NEXT: v_sub_i32_e32 v5, vcc, s4, v4
; SI-NEXT: v_or_b32_e32 v3, 0x1000, v0
; SI-NEXT: v_med3_i32 v5, v5, 0, 13
; SI-NEXT: v_lshrrev_b32_e32 v6, v5, v3
; SI-NEXT: v_lshlrev_b32_e32 v5, v5, v6
; SI-NEXT: v_cmp_ne_u32_e32 vcc, v5, v3
; SI-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; SI-NEXT: v_add_i32_e32 v4, vcc, s5, v4
; SI-NEXT: v_lshlrev_b32_e32 v5, 12, v4
; SI-NEXT: v_or_b32_e32 v3, v6, v3
; SI-NEXT: v_or_b32_e32 v5, v0, v5
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v4
; SI-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; SI-NEXT: v_and_b32_e32 v5, 7, v3
; SI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v5
; SI-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v5
; SI-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_lshrrev_b32_e32 v3, 2, v3
; SI-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v4
; SI-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e32 v0, v7, v8, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v4
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
; SI-NEXT: v_and_b32_e32 v1, 0x8000, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v0, v0, v2
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: fma_v2f16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v0
; VI-NEXT: v_fma_f16 v3, v5, v4, v3
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_fma_f16 v0, v0, v1, v2
; VI-NEXT: v_or_b32_e32 v0, v0, v3
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: fma_v2f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_pk_fma_f16 v0, v0, v1, v2
; GFX9-NEXT: s_setpc_b64 s[30:31]
%r.val = call <2 x half> @llvm.fma.v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c)
ret <2 x half> %r.val
}
define <2 x half> @fma_v2f16_imm_a(<2 x half> %b, <2 x half> %c) {
; SI-LABEL: fma_v2f16_imm_a:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v2, v1
; SI-NEXT: v_cvt_f32_f16_e32 v4, v0
; SI-NEXT: s_mov_b32 s4, 0
; SI-NEXT: s_mov_b32 s5, 0x40080000
; SI-NEXT: v_cvt_f64_f32_e32 v[2:3], v2
; SI-NEXT: v_cvt_f64_f32_e32 v[4:5], v4
; SI-NEXT: s_movk_i32 s6, 0x3f1
; SI-NEXT: s_movk_i32 s7, 0xfc10
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; SI-NEXT: v_fma_f64 v[2:3], v[4:5], s[4:5], v[2:3]
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: v_and_b32_e32 v4, 0x1ff, v3
; SI-NEXT: v_or_b32_e32 v2, v4, v2
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; SI-NEXT: v_lshrrev_b32_e32 v4, 8, v3
; SI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v4, 0xffe, v4
; SI-NEXT: v_bfe_u32 v5, v3, 20, 11
; SI-NEXT: v_or_b32_e32 v2, v4, v2
; SI-NEXT: v_sub_i32_e32 v6, vcc, s6, v5
; SI-NEXT: v_or_b32_e32 v4, 0x1000, v2
; SI-NEXT: v_med3_i32 v6, v6, 0, 13
; SI-NEXT: v_lshrrev_b32_e32 v7, v6, v4
; SI-NEXT: v_lshlrev_b32_e32 v6, v6, v7
; SI-NEXT: v_cmp_ne_u32_e32 vcc, v6, v4
; SI-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
; SI-NEXT: v_lshlrev_b32_e32 v6, 12, v5
; SI-NEXT: v_or_b32_e32 v4, v7, v4
; SI-NEXT: v_or_b32_e32 v6, v2, v6
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v5
; SI-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; SI-NEXT: v_and_b32_e32 v6, 7, v4
; SI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v6
; SI-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v6
; SI-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_lshrrev_b32_e32 v4, 2, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: v_cvt_f32_f16_e32 v8, v0
; SI-NEXT: v_mov_b32_e32 v6, 0x7c00
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v5
; SI-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; SI-NEXT: v_mov_b32_e32 v7, 0x7e00
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; SI-NEXT: s_movk_i32 s8, 0x40f
; SI-NEXT: v_cndmask_b32_e32 v2, v6, v7, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, s8, v5
; SI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; SI-NEXT: v_cvt_f64_f32_e32 v[0:1], v1
; SI-NEXT: v_cvt_f64_f32_e32 v[4:5], v8
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; SI-NEXT: v_and_b32_e32 v3, 0x8000, v3
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_fma_f64 v[0:1], v[4:5], s[4:5], v[0:1]
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_and_b32_e32 v3, 0x1ff, v1
; SI-NEXT: v_or_b32_e32 v0, v3, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_lshrrev_b32_e32 v3, 8, v1
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v3, 0xffe, v3
; SI-NEXT: v_bfe_u32 v4, v1, 20, 11
; SI-NEXT: v_or_b32_e32 v0, v3, v0
; SI-NEXT: v_sub_i32_e32 v5, vcc, s6, v4
; SI-NEXT: v_or_b32_e32 v3, 0x1000, v0
; SI-NEXT: v_med3_i32 v5, v5, 0, 13
; SI-NEXT: v_lshrrev_b32_e32 v8, v5, v3
; SI-NEXT: v_lshlrev_b32_e32 v5, v5, v8
; SI-NEXT: v_cmp_ne_u32_e32 vcc, v5, v3
; SI-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
; SI-NEXT: v_lshlrev_b32_e32 v5, 12, v4
; SI-NEXT: v_or_b32_e32 v3, v8, v3
; SI-NEXT: v_or_b32_e32 v5, v0, v5
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v4
; SI-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; SI-NEXT: v_and_b32_e32 v5, 7, v3
; SI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v5
; SI-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v5
; SI-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; SI-NEXT: v_or_b32_e32 v5, v5, v8
; SI-NEXT: v_lshrrev_b32_e32 v3, 2, v3
; SI-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v4
; SI-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e32 v0, v6, v7, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, s8, v4
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
; SI-NEXT: v_and_b32_e32 v1, 0x8000, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: fma_v2f16_imm_a:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; VI-NEXT: s_movk_i32 s4, 0x4200
; VI-NEXT: v_fma_f16 v2, v3, s4, v2
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_fma_f16 v0, v0, s4, v1
; VI-NEXT: v_or_b32_e32 v0, v0, v2
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: fma_v2f16_imm_a:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_movk_i32 s4, 0x4200
; GFX9-NEXT: v_pk_fma_f16 v0, v0, s4, v1 op_sel_hi:[1,0,1]
; GFX9-NEXT: s_setpc_b64 s[30:31]
%r.val = call <2 x half> @llvm.fma.v2f16(<2 x half> <half 3.0, half 3.0>, <2 x half> %b, <2 x half> %c)
ret <2 x half> %r.val
}
define <2 x half> @fma_v2f16_imm_b(<2 x half> %a, <2 x half> %c) {
; SI-LABEL: fma_v2f16_imm_b:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v2, v1
; SI-NEXT: v_cvt_f32_f16_e32 v4, v0
; SI-NEXT: s_mov_b32 s4, 0
; SI-NEXT: s_mov_b32 s5, 0x40080000
; SI-NEXT: v_cvt_f64_f32_e32 v[2:3], v2
; SI-NEXT: v_cvt_f64_f32_e32 v[4:5], v4
; SI-NEXT: s_movk_i32 s6, 0x3f1
; SI-NEXT: s_movk_i32 s7, 0xfc10
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; SI-NEXT: v_fma_f64 v[2:3], v[4:5], s[4:5], v[2:3]
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: v_and_b32_e32 v4, 0x1ff, v3
; SI-NEXT: v_or_b32_e32 v2, v4, v2
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; SI-NEXT: v_lshrrev_b32_e32 v4, 8, v3
; SI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v4, 0xffe, v4
; SI-NEXT: v_bfe_u32 v5, v3, 20, 11
; SI-NEXT: v_or_b32_e32 v2, v4, v2
; SI-NEXT: v_sub_i32_e32 v6, vcc, s6, v5
; SI-NEXT: v_or_b32_e32 v4, 0x1000, v2
; SI-NEXT: v_med3_i32 v6, v6, 0, 13
; SI-NEXT: v_lshrrev_b32_e32 v7, v6, v4
; SI-NEXT: v_lshlrev_b32_e32 v6, v6, v7
; SI-NEXT: v_cmp_ne_u32_e32 vcc, v6, v4
; SI-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
; SI-NEXT: v_lshlrev_b32_e32 v6, 12, v5
; SI-NEXT: v_or_b32_e32 v4, v7, v4
; SI-NEXT: v_or_b32_e32 v6, v2, v6
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v5
; SI-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; SI-NEXT: v_and_b32_e32 v6, 7, v4
; SI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v6
; SI-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v6
; SI-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_lshrrev_b32_e32 v4, 2, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: v_cvt_f32_f16_e32 v8, v0
; SI-NEXT: v_mov_b32_e32 v6, 0x7c00
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v5
; SI-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; SI-NEXT: v_mov_b32_e32 v7, 0x7e00
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; SI-NEXT: s_movk_i32 s8, 0x40f
; SI-NEXT: v_cndmask_b32_e32 v2, v6, v7, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, s8, v5
; SI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; SI-NEXT: v_cvt_f64_f32_e32 v[0:1], v1
; SI-NEXT: v_cvt_f64_f32_e32 v[4:5], v8
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; SI-NEXT: v_and_b32_e32 v3, 0x8000, v3
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_fma_f64 v[0:1], v[4:5], s[4:5], v[0:1]
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_and_b32_e32 v3, 0x1ff, v1
; SI-NEXT: v_or_b32_e32 v0, v3, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_lshrrev_b32_e32 v3, 8, v1
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v3, 0xffe, v3
; SI-NEXT: v_bfe_u32 v4, v1, 20, 11
; SI-NEXT: v_or_b32_e32 v0, v3, v0
; SI-NEXT: v_sub_i32_e32 v5, vcc, s6, v4
; SI-NEXT: v_or_b32_e32 v3, 0x1000, v0
; SI-NEXT: v_med3_i32 v5, v5, 0, 13
; SI-NEXT: v_lshrrev_b32_e32 v8, v5, v3
; SI-NEXT: v_lshlrev_b32_e32 v5, v5, v8
; SI-NEXT: v_cmp_ne_u32_e32 vcc, v5, v3
; SI-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
; SI-NEXT: v_lshlrev_b32_e32 v5, 12, v4
; SI-NEXT: v_or_b32_e32 v3, v8, v3
; SI-NEXT: v_or_b32_e32 v5, v0, v5
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v4
; SI-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; SI-NEXT: v_and_b32_e32 v5, 7, v3
; SI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v5
; SI-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v5
; SI-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; SI-NEXT: v_or_b32_e32 v5, v5, v8
; SI-NEXT: v_lshrrev_b32_e32 v3, 2, v3
; SI-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v4
; SI-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e32 v0, v6, v7, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, s8, v4
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
; SI-NEXT: v_and_b32_e32 v1, 0x8000, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: fma_v2f16_imm_b:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; VI-NEXT: s_movk_i32 s4, 0x4200
; VI-NEXT: v_fma_f16 v2, v3, s4, v2
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_fma_f16 v0, v0, s4, v1
; VI-NEXT: v_or_b32_e32 v0, v0, v2
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: fma_v2f16_imm_b:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_movk_i32 s4, 0x4200
; GFX9-NEXT: v_pk_fma_f16 v0, v0, s4, v1 op_sel_hi:[1,0,1]
; GFX9-NEXT: s_setpc_b64 s[30:31]
%r.val = call <2 x half> @llvm.fma.v2f16(<2 x half> %a, <2 x half> <half 3.0, half 3.0>, <2 x half> %c)
ret <2 x half> %r.val
}
define <2 x half> @fma_v2f16_imm_c(<2 x half> %a, <2 x half> %b) {
; SI-LABEL: fma_v2f16_imm_c:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v2, v1
; SI-NEXT: v_cvt_f32_f16_e32 v4, v0
; SI-NEXT: s_mov_b32 s4, 0
; SI-NEXT: s_mov_b32 s5, 0x40080000
; SI-NEXT: v_cvt_f64_f32_e32 v[2:3], v2
; SI-NEXT: v_cvt_f64_f32_e32 v[4:5], v4
; SI-NEXT: s_movk_i32 s6, 0x3f1
; SI-NEXT: s_movk_i32 s7, 0xfc10
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; SI-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], s[4:5]
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: v_and_b32_e32 v4, 0x1ff, v3
; SI-NEXT: v_or_b32_e32 v2, v4, v2
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; SI-NEXT: v_lshrrev_b32_e32 v4, 8, v3
; SI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v4, 0xffe, v4
; SI-NEXT: v_bfe_u32 v5, v3, 20, 11
; SI-NEXT: v_or_b32_e32 v2, v4, v2
; SI-NEXT: v_sub_i32_e32 v6, vcc, s6, v5
; SI-NEXT: v_or_b32_e32 v4, 0x1000, v2
; SI-NEXT: v_med3_i32 v6, v6, 0, 13
; SI-NEXT: v_lshrrev_b32_e32 v7, v6, v4
; SI-NEXT: v_lshlrev_b32_e32 v6, v6, v7
; SI-NEXT: v_cmp_ne_u32_e32 vcc, v6, v4
; SI-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
; SI-NEXT: v_lshlrev_b32_e32 v6, 12, v5
; SI-NEXT: v_or_b32_e32 v4, v7, v4
; SI-NEXT: v_or_b32_e32 v6, v2, v6
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v5
; SI-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; SI-NEXT: v_and_b32_e32 v6, 7, v4
; SI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v6
; SI-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v6
; SI-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_lshrrev_b32_e32 v4, 2, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: v_cvt_f32_f16_e32 v8, v0
; SI-NEXT: v_mov_b32_e32 v6, 0x7c00
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v5
; SI-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; SI-NEXT: v_mov_b32_e32 v7, 0x7e00
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; SI-NEXT: s_movk_i32 s8, 0x40f
; SI-NEXT: v_cndmask_b32_e32 v2, v6, v7, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, s8, v5
; SI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; SI-NEXT: v_cvt_f64_f32_e32 v[0:1], v1
; SI-NEXT: v_cvt_f64_f32_e32 v[4:5], v8
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; SI-NEXT: v_and_b32_e32 v3, 0x8000, v3
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_fma_f64 v[0:1], v[4:5], v[0:1], s[4:5]
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_and_b32_e32 v3, 0x1ff, v1
; SI-NEXT: v_or_b32_e32 v0, v3, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_lshrrev_b32_e32 v3, 8, v1
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v3, 0xffe, v3
; SI-NEXT: v_bfe_u32 v4, v1, 20, 11
; SI-NEXT: v_or_b32_e32 v0, v3, v0
; SI-NEXT: v_sub_i32_e32 v5, vcc, s6, v4
; SI-NEXT: v_or_b32_e32 v3, 0x1000, v0
; SI-NEXT: v_med3_i32 v5, v5, 0, 13
; SI-NEXT: v_lshrrev_b32_e32 v8, v5, v3
; SI-NEXT: v_lshlrev_b32_e32 v5, v5, v8
; SI-NEXT: v_cmp_ne_u32_e32 vcc, v5, v3
; SI-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
; SI-NEXT: v_lshlrev_b32_e32 v5, 12, v4
; SI-NEXT: v_or_b32_e32 v3, v8, v3
; SI-NEXT: v_or_b32_e32 v5, v0, v5
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v4
; SI-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; SI-NEXT: v_and_b32_e32 v5, 7, v3
; SI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v5
; SI-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v5
; SI-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; SI-NEXT: v_or_b32_e32 v5, v5, v8
; SI-NEXT: v_lshrrev_b32_e32 v3, 2, v3
; SI-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v4
; SI-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e32 v0, v6, v7, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, s8, v4
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
; SI-NEXT: v_and_b32_e32 v1, 0x8000, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: fma_v2f16_imm_c:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; VI-NEXT: s_movk_i32 s4, 0x4200
; VI-NEXT: v_fma_f16 v2, v3, v2, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_fma_f16 v0, v0, v1, s4
; VI-NEXT: v_or_b32_e32 v0, v0, v2
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: fma_v2f16_imm_c:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_movk_i32 s4, 0x4200
; GFX9-NEXT: v_pk_fma_f16 v0, v0, v1, s4 op_sel_hi:[1,1,0]
; GFX9-NEXT: s_setpc_b64 s[30:31]
%r.val = call <2 x half> @llvm.fma.v2f16(<2 x half> %a, <2 x half> %b, <2 x half> <half 3.0, half 3.0>)
ret <2 x half> %r.val
}
define <4 x half> @fma_v4f16(<4 x half> %a, <4 x half> %b, <4 x half> %c) {
; SI-LABEL: fma_v4f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v3
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v5
; SI-NEXT: v_cvt_f32_f16_e32 v8, v8
; SI-NEXT: v_cvt_f32_f16_e32 v9, v7
; SI-NEXT: v_cvt_f32_f16_e32 v10, v6
; SI-NEXT: s_movk_i32 s4, 0x3f1
; SI-NEXT: v_cvt_f64_f32_e32 v[6:7], v8
; SI-NEXT: v_cvt_f64_f32_e32 v[8:9], v9
; SI-NEXT: v_cvt_f64_f32_e32 v[10:11], v10
; SI-NEXT: s_movk_i32 s5, 0xfc10
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v0
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v2
; SI-NEXT: v_fma_f64 v[7:8], v[10:11], v[8:9], v[6:7]
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v4
; SI-NEXT: v_and_b32_e32 v6, 0x1ff, v8
; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; SI-NEXT: v_lshrrev_b32_e32 v7, 8, v8
; SI-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v7, 0xffe, v7
; SI-NEXT: v_or_b32_e32 v10, v7, v6
; SI-NEXT: v_bfe_u32 v7, v8, 20, 11
; SI-NEXT: v_sub_i32_e32 v11, vcc, s4, v7
; SI-NEXT: v_or_b32_e32 v6, 0x1000, v10
; SI-NEXT: v_med3_i32 v11, v11, 0, 13
; SI-NEXT: v_lshrrev_b32_e32 v14, v11, v6
; SI-NEXT: v_lshlrev_b32_e32 v11, v11, v14
; SI-NEXT: v_cmp_ne_u32_e32 vcc, v11, v6
; SI-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; SI-NEXT: v_add_i32_e32 v11, vcc, s5, v7
; SI-NEXT: v_lshlrev_b32_e32 v7, 12, v11
; SI-NEXT: v_or_b32_e32 v6, v14, v6
; SI-NEXT: v_or_b32_e32 v7, v10, v7
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v11
; SI-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc
; SI-NEXT: v_and_b32_e32 v7, 7, v6
; SI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v7
; SI-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v7
; SI-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; SI-NEXT: v_or_b32_e32 v7, v7, v14
; SI-NEXT: v_lshrrev_b32_e32 v6, 2, v6
; SI-NEXT: v_add_i32_e32 v7, vcc, v6, v7
; SI-NEXT: v_cvt_f32_f16_e32 v9, v9
; SI-NEXT: v_cvt_f32_f16_e32 v13, v13
; SI-NEXT: v_cvt_f32_f16_e32 v15, v12
; SI-NEXT: v_mov_b32_e32 v6, 0x7c00
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v11
; SI-NEXT: v_cndmask_b32_e32 v14, v6, v7, vcc
; SI-NEXT: v_mov_b32_e32 v7, 0x7e00
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; SI-NEXT: s_movk_i32 s6, 0x40f
; SI-NEXT: v_cndmask_b32_e32 v10, v6, v7, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v11
; SI-NEXT: v_cndmask_b32_e32 v16, v14, v10, vcc
; SI-NEXT: v_cvt_f64_f32_e32 v[9:10], v9
; SI-NEXT: v_cvt_f64_f32_e32 v[11:12], v13
; SI-NEXT: v_cvt_f64_f32_e32 v[13:14], v15
; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: v_fma_f64 v[9:10], v[13:14], v[11:12], v[9:10]
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
; SI-NEXT: v_and_b32_e32 v11, 0x1ff, v10
; SI-NEXT: v_or_b32_e32 v9, v11, v9
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
; SI-NEXT: v_lshrrev_b32_e32 v11, 8, v10
; SI-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v11, 0xffe, v11
; SI-NEXT: v_bfe_u32 v12, v10, 20, 11
; SI-NEXT: v_or_b32_e32 v9, v11, v9
; SI-NEXT: v_sub_i32_e32 v13, vcc, s4, v12
; SI-NEXT: v_or_b32_e32 v11, 0x1000, v9
; SI-NEXT: v_med3_i32 v13, v13, 0, 13
; SI-NEXT: v_lshrrev_b32_e32 v14, v13, v11
; SI-NEXT: v_lshlrev_b32_e32 v13, v13, v14
; SI-NEXT: v_cmp_ne_u32_e32 vcc, v13, v11
; SI-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; SI-NEXT: v_add_i32_e32 v12, vcc, s5, v12
; SI-NEXT: v_lshlrev_b32_e32 v13, 12, v12
; SI-NEXT: v_or_b32_e32 v11, v14, v11
; SI-NEXT: v_or_b32_e32 v13, v9, v13
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v12
; SI-NEXT: v_cndmask_b32_e32 v11, v13, v11, vcc
; SI-NEXT: v_and_b32_e32 v13, 7, v11
; SI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v13
; SI-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v13
; SI-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_lshrrev_b32_e32 v11, 2, v11
; SI-NEXT: v_add_i32_e32 v11, vcc, v11, v13
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v12
; SI-NEXT: v_cndmask_b32_e32 v11, v6, v11, vcc
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
; SI-NEXT: v_and_b32_e32 v8, 0x8000, v8
; SI-NEXT: v_cndmask_b32_e32 v9, v6, v7, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v12
; SI-NEXT: v_or_b32_e32 v8, v8, v16
; SI-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc
; SI-NEXT: v_cvt_f64_f32_e32 v[11:12], v5
; SI-NEXT: v_cvt_f64_f32_e32 v[13:14], v3
; SI-NEXT: v_cvt_f64_f32_e32 v[15:16], v1
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v10
; SI-NEXT: v_and_b32_e32 v1, 0x8000, v1
; SI-NEXT: v_or_b32_e32 v1, v1, v9
; SI-NEXT: v_fma_f64 v[9:10], v[15:16], v[13:14], v[11:12]
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v1
; SI-NEXT: v_and_b32_e32 v1, 0x1ff, v10
; SI-NEXT: v_or_b32_e32 v1, v1, v9
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
; SI-NEXT: v_lshrrev_b32_e32 v3, 8, v10
; SI-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v3, 0xffe, v3
; SI-NEXT: v_bfe_u32 v5, v10, 20, 11
; SI-NEXT: v_or_b32_e32 v1, v3, v1
; SI-NEXT: v_sub_i32_e32 v9, vcc, s4, v5
; SI-NEXT: v_or_b32_e32 v3, 0x1000, v1
; SI-NEXT: v_med3_i32 v9, v9, 0, 13
; SI-NEXT: v_lshrrev_b32_e32 v12, v9, v3
; SI-NEXT: v_lshlrev_b32_e32 v9, v9, v12
; SI-NEXT: v_cmp_ne_u32_e32 vcc, v9, v3
; SI-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; SI-NEXT: v_add_i32_e32 v9, vcc, s5, v5
; SI-NEXT: v_lshlrev_b32_e32 v5, 12, v9
; SI-NEXT: v_or_b32_e32 v3, v12, v3
; SI-NEXT: v_or_b32_e32 v5, v1, v5
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v9
; SI-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; SI-NEXT: v_and_b32_e32 v5, 7, v3
; SI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v5
; SI-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v5
; SI-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; SI-NEXT: v_or_b32_e32 v5, v5, v12
; SI-NEXT: v_lshrrev_b32_e32 v3, 2, v3
; SI-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v9
; SI-NEXT: v_cndmask_b32_e32 v12, v6, v3, vcc
; SI-NEXT: v_cvt_f32_f16_e32 v3, v4
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
; SI-NEXT: v_cvt_f32_f16_e32 v4, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
; SI-NEXT: v_cvt_f64_f32_e32 v[0:1], v3
; SI-NEXT: v_cvt_f64_f32_e32 v[2:3], v2
; SI-NEXT: v_cvt_f64_f32_e32 v[4:5], v4
; SI-NEXT: v_cndmask_b32_e32 v13, v6, v7, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v9
; SI-NEXT: v_cndmask_b32_e32 v9, v12, v13, vcc
; SI-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
; SI-NEXT: v_and_b32_e32 v3, 0x1ff, v1
; SI-NEXT: v_or_b32_e32 v0, v3, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_lshrrev_b32_e32 v3, 8, v1
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v3, 0xffe, v3
; SI-NEXT: v_bfe_u32 v4, v1, 20, 11
; SI-NEXT: v_or_b32_e32 v0, v3, v0
; SI-NEXT: v_sub_i32_e32 v5, vcc, s4, v4
; SI-NEXT: v_and_b32_e32 v10, 0x8000, v10
; SI-NEXT: v_or_b32_e32 v3, 0x1000, v0
; SI-NEXT: v_med3_i32 v5, v5, 0, 13
; SI-NEXT: v_or_b32_e32 v2, v10, v9
; SI-NEXT: v_lshrrev_b32_e32 v9, v5, v3
; SI-NEXT: v_lshlrev_b32_e32 v5, v5, v9
; SI-NEXT: v_cmp_ne_u32_e32 vcc, v5, v3
; SI-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; SI-NEXT: v_add_i32_e32 v4, vcc, s5, v4
; SI-NEXT: v_lshlrev_b32_e32 v5, 12, v4
; SI-NEXT: v_or_b32_e32 v3, v9, v3
; SI-NEXT: v_or_b32_e32 v5, v0, v5
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v4
; SI-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; SI-NEXT: v_and_b32_e32 v5, 7, v3
; SI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v5
; SI-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v5
; SI-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; SI-NEXT: v_or_b32_e32 v5, v5, v9
; SI-NEXT: v_lshrrev_b32_e32 v3, 2, v3
; SI-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v4
; SI-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_cndmask_b32_e32 v0, v6, v7, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v4
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
; SI-NEXT: v_and_b32_e32 v1, 0x8000, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v0, v0, v11
; SI-NEXT: v_or_b32_e32 v1, v1, v8
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: fma_v4f16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v5
; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v3
; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v1
; VI-NEXT: v_fma_f16 v6, v8, v7, v6
; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v4
; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v0
; VI-NEXT: v_fma_f16 v7, v9, v8, v7
; VI-NEXT: v_fma_f16 v0, v0, v2, v4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v7
; VI-NEXT: v_fma_f16 v1, v1, v3, v5
; VI-NEXT: v_or_b32_e32 v0, v0, v2
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v6
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: fma_v4f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_pk_fma_f16 v0, v0, v2, v4
; GFX9-NEXT: v_pk_fma_f16 v1, v1, v3, v5
; GFX9-NEXT: s_setpc_b64 s[30:31]
%r.val = call <4 x half> @llvm.fma.v4f16(<4 x half> %a, <4 x half> %b, <4 x half> %c)
ret <4 x half> %r.val
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GCN: {{.*}}
; SIVI: {{.*}}
; VIGFX9: {{.*}}