llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.async.tensor.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel=0 -mtriple=amdgpu12.50 < %s | FileCheck %s -check-prefix=GFX12
; RUN: llc -global-isel=1 -mtriple=amdgpu12.50 < %s | FileCheck %s -check-prefix=GFX12
; RUN: llc -global-isel=0 -mtriple=amdgpu13.10 < %s | FileCheck %s -check-prefix=GFX13
; RUN: llc -global-isel=1 -mtriple=amdgpu13.10 < %s | FileCheck %s -check-prefix=GFX13

define amdgpu_ps void @test_asynccnt() {
; GFX12-LABEL: test_asynccnt:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-NEXT:    s_mov_b64 s[64:65], 0
; GFX12-NEXT:    v_nop
; GFX12-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-NEXT:    s_wait_asynccnt 0x0
; GFX12-NEXT:    s_endpgm
;
; GFX13-LABEL: test_asynccnt:
; GFX13:       ; %bb.0:
; GFX13-NEXT:    s_wait_asynccnt 0x0
; GFX13-NEXT:    s_endpgm
  call void @llvm.amdgcn.s.wait.asynccnt(i16 0)
  ret void
}

define amdgpu_ps void @test_tensorcnt() {
; GFX12-LABEL: test_tensorcnt:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-NEXT:    s_mov_b64 s[64:65], 0
; GFX12-NEXT:    v_nop
; GFX12-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-NEXT:    s_wait_tensorcnt 0x0
; GFX12-NEXT:    s_endpgm
;
; GFX13-LABEL: test_tensorcnt:
; GFX13:       ; %bb.0:
; GFX13-NEXT:    s_wait_tensorcnt 0x0
; GFX13-NEXT:    s_endpgm
  call void @llvm.amdgcn.s.wait.tensorcnt(i16 0)
  ret void
}

declare void @llvm.amdgcn.s.wait.asynccnt(i16)
declare void @llvm.amdgcn.s.wait.tensorcnt(i16)