llvm/test/CodeGen/AMDGPU/frem.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN:  llc -enable-misched=0 -mtriple=amdgpu6.00 -mattr=+mad-mac-f32-insts  < %s | FileCheck --check-prefix=SI %s
; RUN:  llc -enable-misched=0 -mtriple=amdgpu7.04 < %s | FileCheck --check-prefix=CI %s
; RUN:  llc -enable-misched=0 -mtriple=amdgpu8.02 < %s | FileCheck --check-prefix=VI %s
; RUN:  llc -enable-misched=0 -mtriple=amdgpu9.00 < %s | FileCheck --check-prefix=GFX9 %s
; RUN:  llc -enable-misched=0 -mtriple=amdgpu10.10 < %s | FileCheck --check-prefix=GFX10 %s
; RUN:  llc -enable-misched=0 -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck --check-prefixes=GFX11,GFX11-TRUE16 %s
; RUN:  llc -enable-misched=0 -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck --check-prefixes=GFX11,GFX11-FAKE16 %s
; RUN:  llc -enable-misched=0 -mtriple=amdgpu11.50 -mattr=+real-true16 < %s | FileCheck --check-prefixes=GFX1150,GFX1150-TRUE16 %s
; RUN:  llc -enable-misched=0 -mtriple=amdgpu11.50 -mattr=-real-true16 < %s | FileCheck --check-prefixes=GFX1150,GFX1150-FAKE16 %s
; RUN:  llc -enable-misched=0 -mtriple=amdgpu12.00 -mattr=+real-true16 < %s | FileCheck --check-prefixes=GFX1200,GFX1200-TRUE16 %s
; RUN:  llc -enable-misched=0 -mtriple=amdgpu12.00 -mattr=-real-true16 < %s | FileCheck --check-prefixes=GFX1200,GFX1200-FAKE16 %s

define half @frem_f16(half %in1, half %in2) #0 {
; SI-LABEL: frem_f16:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cvt_f32_f16_e64 v4, |v0|
; SI-NEXT:    v_cvt_f32_f16_e64 v3, |v1|
; SI-NEXT:    ; implicit-def: $vgpr2
; SI-NEXT:    v_cmp_ngt_f32_e32 vcc, v4, v3
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:  ; %bb.1: ; %frem.else
; SI-NEXT:    v_and_b32_e32 v2, 0xffff8000, v0
; SI-NEXT:    v_cmp_eq_f32_e32 vcc, v4, v3
; SI-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc
; SI-NEXT:    ; implicit-def: $vgpr4
; SI-NEXT:    ; implicit-def: $vgpr3
; SI-NEXT:  ; %bb.2: ; %Flow15
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB0_8
; SI-NEXT:  ; %bb.3: ; %frem.compute
; SI-NEXT:    s_mov_b32 s6, 0x7f800000
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v4|, s6
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v2, v4
; SI-NEXT:    v_cndmask_b32_e32 v7, 0, v2, vcc
; SI-NEXT:    v_frexp_mant_f32_e32 v2, v4
; SI-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; SI-NEXT:    v_ldexp_f32_e64 v4, v2, 11
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v3|, s6
; SI-NEXT:    v_frexp_mant_f32_e32 v2, v3
; SI-NEXT:    v_cndmask_b32_e32 v5, v3, v2, vcc
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v2, v3
; SI-NEXT:    v_ldexp_f32_e64 v3, v5, 1
; SI-NEXT:    v_cndmask_b32_e32 v8, 0, v2, vcc
; SI-NEXT:    v_div_scale_f32 v9, s[6:7], v3, v3, 1.0
; SI-NEXT:    v_add_i32_e32 v2, vcc, -1, v8
; SI-NEXT:    v_rcp_f32_e32 v10, v9
; SI-NEXT:    v_not_b32_e32 v5, v2
; SI-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
; SI-NEXT:    v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; SI-NEXT:    v_fma_f32 v10, v11, v10, v10
; SI-NEXT:    v_mul_f32_e32 v11, v6, v10
; SI-NEXT:    v_fma_f32 v12, -v9, v11, v6
; SI-NEXT:    v_fma_f32 v11, v12, v10, v11
; SI-NEXT:    v_fma_f32 v6, -v9, v11, v6
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
; SI-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v5
; SI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; SI-NEXT:    s_cbranch_execz .LBB0_7
; SI-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
; SI-NEXT:    v_sub_i32_e32 v5, vcc, v7, v8
; SI-NEXT:    v_add_i32_e32 v5, vcc, 11, v5
; SI-NEXT:    s_mov_b64 s[8:9], 0
; SI-NEXT:  .LBB0_5: ; %frem.loop_body
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v7, v4
; SI-NEXT:    v_mul_f32_e32 v4, v7, v6
; SI-NEXT:    v_rndne_f32_e32 v4, v4
; SI-NEXT:    v_fma_f32 v4, -v4, v3, v7
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; SI-NEXT:    v_add_f32_e32 v8, v4, v3
; SI-NEXT:    v_cndmask_b32_e32 v4, v4, v8, vcc
; SI-NEXT:    v_add_i32_e32 v5, vcc, -11, v5
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v5
; SI-NEXT:    v_ldexp_f32_e64 v4, v4, 11
; SI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; SI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; SI-NEXT:    s_cbranch_execnz .LBB0_5
; SI-NEXT:  ; %bb.6: ; %Flow
; SI-NEXT:    s_or_b64 exec, exec, s[8:9]
; SI-NEXT:    v_mov_b32_e32 v4, v7
; SI-NEXT:  .LBB0_7: ; %Flow14
; SI-NEXT:    s_or_b64 exec, exec, s[6:7]
; SI-NEXT:    v_add_i32_e32 v5, vcc, -10, v5
; SI-NEXT:    v_ldexp_f32_e32 v4, v4, v5
; SI-NEXT:    v_mul_f32_e32 v5, v4, v6
; SI-NEXT:    v_rndne_f32_e32 v5, v5
; SI-NEXT:    v_fma_f32 v4, -v5, v3, v4
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; SI-NEXT:    v_add_f32_e32 v3, v4, v3
; SI-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; SI-NEXT:    v_ldexp_f32_e32 v2, v3, v2
; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; SI-NEXT:    s_movk_i32 s6, 0x7fff
; SI-NEXT:    v_bfi_b32 v2, s6, v2, v0
; SI-NEXT:  .LBB0_8: ; %Flow16
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
; SI-NEXT:    v_cvt_f32_f16_e64 v0, |v0|
; SI-NEXT:    s_mov_b32 s4, 0x7f800000
; SI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v1
; SI-NEXT:    v_cmp_nle_f32_e64 s[4:5], s4, v0
; SI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; SI-NEXT:    v_mov_b32_e32 v0, 0x7e00
; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; CI-LABEL: frem_f16:
; CI:       ; %bb.0:
; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-NEXT:    v_cvt_f32_f16_e64 v4, |v0|
; CI-NEXT:    v_cvt_f32_f16_e64 v3, |v1|
; CI-NEXT:    ; implicit-def: $vgpr2
; CI-NEXT:    v_cmp_ngt_f32_e32 vcc, v4, v3
; CI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; CI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; CI-NEXT:  ; %bb.1: ; %frem.else
; CI-NEXT:    v_and_b32_e32 v2, 0xffff8000, v0
; CI-NEXT:    v_cmp_eq_f32_e32 vcc, v4, v3
; CI-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc
; CI-NEXT:    ; implicit-def: $vgpr4
; CI-NEXT:    ; implicit-def: $vgpr3
; CI-NEXT:  ; %bb.2: ; %Flow15
; CI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; CI-NEXT:    s_cbranch_execz .LBB0_8
; CI-NEXT:  ; %bb.3: ; %frem.compute
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v7, v4
; CI-NEXT:    v_frexp_mant_f32_e32 v2, v4
; CI-NEXT:    v_frexp_mant_f32_e32 v4, v3
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v8, v3
; CI-NEXT:    v_ldexp_f32_e64 v3, v4, 1
; CI-NEXT:    v_div_scale_f32 v9, s[6:7], v3, v3, 1.0
; CI-NEXT:    v_ldexp_f32_e64 v5, v2, 11
; CI-NEXT:    v_add_i32_e32 v2, vcc, -1, v8
; CI-NEXT:    v_not_b32_e32 v4, v2
; CI-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
; CI-NEXT:    v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
; CI-NEXT:    v_rcp_f32_e32 v10, v9
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; CI-NEXT:    v_fma_f32 v10, v11, v10, v10
; CI-NEXT:    v_mul_f32_e32 v11, v6, v10
; CI-NEXT:    v_fma_f32 v12, -v9, v11, v6
; CI-NEXT:    v_fma_f32 v11, v12, v10, v11
; CI-NEXT:    v_fma_f32 v6, -v9, v11, v6
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v4
; CI-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
; CI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; CI-NEXT:    s_cbranch_execz .LBB0_7
; CI-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
; CI-NEXT:    v_sub_i32_e32 v4, vcc, v7, v8
; CI-NEXT:    v_add_i32_e32 v4, vcc, 11, v4
; CI-NEXT:    s_mov_b64 s[8:9], 0
; CI-NEXT:  .LBB0_5: ; %frem.loop_body
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v7, v5
; CI-NEXT:    v_mul_f32_e32 v5, v7, v6
; CI-NEXT:    v_rndne_f32_e32 v5, v5
; CI-NEXT:    v_fma_f32 v5, -v5, v3, v7
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
; CI-NEXT:    v_add_f32_e32 v8, v5, v3
; CI-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc
; CI-NEXT:    v_add_i32_e32 v4, vcc, -11, v4
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v4
; CI-NEXT:    v_ldexp_f32_e64 v5, v5, 11
; CI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; CI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; CI-NEXT:    s_cbranch_execnz .LBB0_5
; CI-NEXT:  ; %bb.6: ; %Flow
; CI-NEXT:    s_or_b64 exec, exec, s[8:9]
; CI-NEXT:    v_mov_b32_e32 v5, v7
; CI-NEXT:  .LBB0_7: ; %Flow14
; CI-NEXT:    s_or_b64 exec, exec, s[6:7]
; CI-NEXT:    v_add_i32_e32 v4, vcc, -10, v4
; CI-NEXT:    v_ldexp_f32_e32 v4, v5, v4
; CI-NEXT:    v_mul_f32_e32 v5, v4, v6
; CI-NEXT:    v_rndne_f32_e32 v5, v5
; CI-NEXT:    v_fma_f32 v4, -v5, v3, v4
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; CI-NEXT:    v_add_f32_e32 v3, v4, v3
; CI-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; CI-NEXT:    v_ldexp_f32_e32 v2, v3, v2
; CI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; CI-NEXT:    s_movk_i32 s6, 0x7fff
; CI-NEXT:    v_bfi_b32 v2, s6, v2, v0
; CI-NEXT:  .LBB0_8: ; %Flow16
; CI-NEXT:    s_or_b64 exec, exec, s[4:5]
; CI-NEXT:    v_cvt_f32_f16_e32 v1, v1
; CI-NEXT:    v_cvt_f32_f16_e64 v0, |v0|
; CI-NEXT:    s_mov_b32 s4, 0x7f800000
; CI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v1
; CI-NEXT:    v_cmp_nle_f32_e64 s[4:5], s4, v0
; CI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; CI-NEXT:    v_mov_b32_e32 v0, 0x7e00
; CI-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
; CI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: frem_f16:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cvt_f32_f16_e64 v4, |v0|
; VI-NEXT:    v_cvt_f32_f16_e64 v3, |v1|
; VI-NEXT:    ; implicit-def: $vgpr2
; VI-NEXT:    v_cmp_ngt_f32_e32 vcc, v4, v3
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:  ; %bb.1: ; %frem.else
; VI-NEXT:    v_and_b32_e32 v2, 0x8000, v0
; VI-NEXT:    v_cmp_eq_f32_e32 vcc, v4, v3
; VI-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc
; VI-NEXT:    ; implicit-def: $vgpr4
; VI-NEXT:    ; implicit-def: $vgpr3
; VI-NEXT:  ; %bb.2: ; %Flow15
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB0_8
; VI-NEXT:  ; %bb.3: ; %frem.compute
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v7, v4
; VI-NEXT:    v_frexp_mant_f32_e32 v2, v4
; VI-NEXT:    v_frexp_mant_f32_e32 v4, v3
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v8, v3
; VI-NEXT:    v_ldexp_f32 v3, v4, 1
; VI-NEXT:    v_div_scale_f32 v9, s[6:7], v3, v3, 1.0
; VI-NEXT:    v_ldexp_f32 v5, v2, 11
; VI-NEXT:    v_add_u32_e32 v2, vcc, -1, v8
; VI-NEXT:    v_not_b32_e32 v4, v2
; VI-NEXT:    v_add_u32_e32 v4, vcc, v4, v7
; VI-NEXT:    v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
; VI-NEXT:    v_rcp_f32_e32 v10, v9
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; VI-NEXT:    v_fma_f32 v10, v11, v10, v10
; VI-NEXT:    v_mul_f32_e32 v11, v6, v10
; VI-NEXT:    v_fma_f32 v12, -v9, v11, v6
; VI-NEXT:    v_fma_f32 v11, v12, v10, v11
; VI-NEXT:    v_fma_f32 v6, -v9, v11, v6
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; VI-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v4
; VI-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
; VI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; VI-NEXT:    s_cbranch_execz .LBB0_7
; VI-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
; VI-NEXT:    v_sub_u32_e32 v4, vcc, v7, v8
; VI-NEXT:    v_add_u32_e32 v4, vcc, 11, v4
; VI-NEXT:    s_mov_b64 s[8:9], 0
; VI-NEXT:  .LBB0_5: ; %frem.loop_body
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v7, v5
; VI-NEXT:    v_mul_f32_e32 v5, v7, v6
; VI-NEXT:    v_rndne_f32_e32 v5, v5
; VI-NEXT:    v_fma_f32 v5, -v5, v3, v7
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
; VI-NEXT:    v_add_f32_e32 v8, v5, v3
; VI-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc
; VI-NEXT:    v_add_u32_e32 v4, vcc, -11, v4
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v4
; VI-NEXT:    v_ldexp_f32 v5, v5, 11
; VI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; VI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; VI-NEXT:    s_cbranch_execnz .LBB0_5
; VI-NEXT:  ; %bb.6: ; %Flow
; VI-NEXT:    s_or_b64 exec, exec, s[8:9]
; VI-NEXT:    v_mov_b32_e32 v5, v7
; VI-NEXT:  .LBB0_7: ; %Flow14
; VI-NEXT:    s_or_b64 exec, exec, s[6:7]
; VI-NEXT:    v_add_u32_e32 v4, vcc, -10, v4
; VI-NEXT:    v_ldexp_f32 v4, v5, v4
; VI-NEXT:    v_mul_f32_e32 v5, v4, v6
; VI-NEXT:    v_rndne_f32_e32 v5, v5
; VI-NEXT:    v_fma_f32 v4, -v5, v3, v4
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; VI-NEXT:    v_add_f32_e32 v3, v4, v3
; VI-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; VI-NEXT:    v_ldexp_f32 v2, v3, v2
; VI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; VI-NEXT:    s_movk_i32 s6, 0x7fff
; VI-NEXT:    v_bfi_b32 v2, s6, v2, v0
; VI-NEXT:  .LBB0_8: ; %Flow16
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_movk_i32 s4, 0x7c00
; VI-NEXT:    v_cmp_lg_f16_e32 vcc, 0, v1
; VI-NEXT:    v_cmp_nge_f16_e64 s[4:5], |v0|, s4
; VI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; VI-NEXT:    v_mov_b32_e32 v0, 0x7e00
; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: frem_f16:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_f32_f16_e64 v4, |v0|
; GFX9-NEXT:    v_cvt_f32_f16_e64 v3, |v1|
; GFX9-NEXT:    ; implicit-def: $vgpr2
; GFX9-NEXT:    v_cmp_ngt_f32_e32 vcc, v4, v3
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:  ; %bb.1: ; %frem.else
; GFX9-NEXT:    v_and_b32_e32 v2, 0x8000, v0
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, v4, v3
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc
; GFX9-NEXT:    ; implicit-def: $vgpr4
; GFX9-NEXT:    ; implicit-def: $vgpr3
; GFX9-NEXT:  ; %bb.2: ; %Flow15
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB0_8
; GFX9-NEXT:  ; %bb.3: ; %frem.compute
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v7, v4
; GFX9-NEXT:    v_frexp_mant_f32_e32 v2, v4
; GFX9-NEXT:    v_frexp_mant_f32_e32 v4, v3
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v8, v3
; GFX9-NEXT:    v_ldexp_f32 v3, v4, 1
; GFX9-NEXT:    v_div_scale_f32 v9, s[6:7], v3, v3, 1.0
; GFX9-NEXT:    v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
; GFX9-NEXT:    v_ldexp_f32 v5, v2, 11
; GFX9-NEXT:    v_add_u32_e32 v2, -1, v8
; GFX9-NEXT:    v_xad_u32 v4, v2, -1, v7
; GFX9-NEXT:    v_rcp_f32_e32 v10, v9
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; GFX9-NEXT:    v_fma_f32 v10, v11, v10, v10
; GFX9-NEXT:    v_mul_f32_e32 v11, v6, v10
; GFX9-NEXT:    v_fma_f32 v12, -v9, v11, v6
; GFX9-NEXT:    v_fma_f32 v11, v12, v10, v11
; GFX9-NEXT:    v_fma_f32 v6, -v9, v11, v6
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX9-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v4
; GFX9-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
; GFX9-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; GFX9-NEXT:    s_cbranch_execz .LBB0_7
; GFX9-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
; GFX9-NEXT:    v_sub_u32_e32 v4, v7, v8
; GFX9-NEXT:    v_add_u32_e32 v4, 11, v4
; GFX9-NEXT:    s_mov_b64 s[8:9], 0
; GFX9-NEXT:  .LBB0_5: ; %frem.loop_body
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v7, v5
; GFX9-NEXT:    v_mul_f32_e32 v5, v7, v6
; GFX9-NEXT:    v_rndne_f32_e32 v5, v5
; GFX9-NEXT:    v_fma_f32 v5, -v5, v3, v7
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
; GFX9-NEXT:    v_add_f32_e32 v8, v5, v3
; GFX9-NEXT:    v_add_u32_e32 v4, -11, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v4
; GFX9-NEXT:    v_ldexp_f32 v5, v5, 11
; GFX9-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; GFX9-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; GFX9-NEXT:    s_cbranch_execnz .LBB0_5
; GFX9-NEXT:  ; %bb.6: ; %Flow
; GFX9-NEXT:    s_or_b64 exec, exec, s[8:9]
; GFX9-NEXT:    v_mov_b32_e32 v5, v7
; GFX9-NEXT:  .LBB0_7: ; %Flow14
; GFX9-NEXT:    s_or_b64 exec, exec, s[6:7]
; GFX9-NEXT:    v_add_u32_e32 v4, -10, v4
; GFX9-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX9-NEXT:    v_mul_f32_e32 v5, v4, v6
; GFX9-NEXT:    v_rndne_f32_e32 v5, v5
; GFX9-NEXT:    v_fma_f32 v4, -v5, v3, v4
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; GFX9-NEXT:    v_add_f32_e32 v3, v4, v3
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX9-NEXT:    v_ldexp_f32 v2, v3, v2
; GFX9-NEXT:    v_cvt_f16_f32_e32 v2, v2
; GFX9-NEXT:    s_movk_i32 s6, 0x7fff
; GFX9-NEXT:    v_bfi_b32 v2, s6, v2, v0
; GFX9-NEXT:  .LBB0_8: ; %Flow16
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_movk_i32 s4, 0x7c00
; GFX9-NEXT:    v_cmp_lg_f16_e32 vcc, 0, v1
; GFX9-NEXT:    v_cmp_nge_f16_e64 s[4:5], |v0|, s4
; GFX9-NEXT:    s_and_b64 vcc, s[4:5], vcc
; GFX9-NEXT:    v_mov_b32_e32 v0, 0x7e00
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: frem_f16:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cvt_f32_f16_e64 v4, |v0|
; GFX10-NEXT:    v_cvt_f32_f16_e64 v3, |v1|
; GFX10-NEXT:    ; implicit-def: $vgpr2
; GFX10-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v4, v3
; GFX10-NEXT:    s_and_saveexec_b32 s4, vcc_lo
; GFX10-NEXT:    s_xor_b32 s4, exec_lo, s4
; GFX10-NEXT:  ; %bb.1: ; %frem.else
; GFX10-NEXT:    v_and_b32_e32 v2, 0x8000, v0
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v4, v3
; GFX10-NEXT:    ; implicit-def: $vgpr4
; GFX10-NEXT:    ; implicit-def: $vgpr3
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc_lo
; GFX10-NEXT:  ; %bb.2: ; %Flow15
; GFX10-NEXT:    s_andn2_saveexec_b32 s4, s4
; GFX10-NEXT:    s_cbranch_execz .LBB0_8
; GFX10-NEXT:  ; %bb.3: ; %frem.compute
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v7, v4
; GFX10-NEXT:    v_frexp_mant_f32_e32 v2, v4
; GFX10-NEXT:    v_frexp_mant_f32_e32 v4, v3
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v8, v3
; GFX10-NEXT:    v_ldexp_f32 v5, v2, 11
; GFX10-NEXT:    v_ldexp_f32 v3, v4, 1
; GFX10-NEXT:    v_add_nc_u32_e32 v2, -1, v8
; GFX10-NEXT:    v_div_scale_f32 v9, s5, v3, v3, 1.0
; GFX10-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v3, 1.0
; GFX10-NEXT:    v_xad_u32 v4, v2, -1, v7
; GFX10-NEXT:    v_rcp_f32_e32 v10, v9
; GFX10-NEXT:    s_denorm_mode 15
; GFX10-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; GFX10-NEXT:    v_fmac_f32_e32 v10, v11, v10
; GFX10-NEXT:    v_mul_f32_e32 v11, v6, v10
; GFX10-NEXT:    v_fma_f32 v12, -v9, v11, v6
; GFX10-NEXT:    v_fmac_f32_e32 v11, v12, v10
; GFX10-NEXT:    v_fma_f32 v6, -v9, v11, v6
; GFX10-NEXT:    s_denorm_mode 12
; GFX10-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
; GFX10-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 11, v4
; GFX10-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
; GFX10-NEXT:    s_and_saveexec_b32 s5, vcc_lo
; GFX10-NEXT:    s_cbranch_execz .LBB0_7
; GFX10-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
; GFX10-NEXT:    v_sub_nc_u32_e32 v4, v7, v8
; GFX10-NEXT:    s_mov_b32 s6, 0
; GFX10-NEXT:    v_add_nc_u32_e32 v4, 11, v4
; GFX10-NEXT:  .LBB0_5: ; %frem.loop_body
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v7, v5
; GFX10-NEXT:    v_add_nc_u32_e32 v4, -11, v4
; GFX10-NEXT:    v_mul_f32_e32 v5, v7, v6
; GFX10-NEXT:    v_rndne_f32_e32 v5, v5
; GFX10-NEXT:    v_fma_f32 v5, -v5, v3, v7
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX10-NEXT:    v_add_f32_e32 v8, v5, v3
; GFX10-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc_lo
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX10-NEXT:    v_ldexp_f32 v5, v5, 11
; GFX10-NEXT:    s_or_b32 s6, vcc_lo, s6
; GFX10-NEXT:    s_andn2_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    s_cbranch_execnz .LBB0_5
; GFX10-NEXT:  ; %bb.6: ; %Flow
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    v_mov_b32_e32 v5, v7
; GFX10-NEXT:  .LBB0_7: ; %Flow14
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s5
; GFX10-NEXT:    v_add_nc_u32_e32 v4, -10, v4
; GFX10-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX10-NEXT:    v_mul_f32_e32 v5, v4, v6
; GFX10-NEXT:    v_rndne_f32_e32 v5, v5
; GFX10-NEXT:    v_fma_f32 v4, -v5, v3, v4
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX10-NEXT:    v_add_f32_e32 v3, v4, v3
; GFX10-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v2, v3, v2
; GFX10-NEXT:    v_cvt_f16_f32_e32 v2, v2
; GFX10-NEXT:    v_bfi_b32 v2, 0x7fff, v2, v0
; GFX10-NEXT:  .LBB0_8: ; %Flow16
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v1
; GFX10-NEXT:    v_cmp_nge_f16_e64 s4, |v0|, 0x7c00
; GFX10-NEXT:    s_and_b32 vcc_lo, s4, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: frem_f16:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.l
; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v3, |v2.l|
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v1.l
; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v4, |v2.l|
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_lo16
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cmpx_ngt_f32_e32 v3, v4
; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT:  ; %bb.1: ; %frem.else
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.l
; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v3, v4
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0x8000, v2.l
; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.l, v2.l, v2.h, vcc_lo
; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow15
; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB0_8
; GFX11-TRUE16-NEXT:  ; %bb.3: ; %frem.compute
; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v7, v3
; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v2, v3
; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v3, v4
; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v8, v4
; GFX11-TRUE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v5, v2, 11
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v3, v3, 1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, -1, v8
; GFX11-TRUE16-NEXT:    v_div_scale_f32 v9, null, v3, v3, 1.0
; GFX11-TRUE16-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v3, 1.0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT:    v_xad_u32 v4, v2, -1, v7
; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v10, v9
; GFX11-TRUE16-NEXT:    s_denorm_mode 15
; GFX11-TRUE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v10, v11, v10
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v11, v6, v10
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v12, -v9, v11, v6
; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v11, v12, v10
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v6, -v9, v11, v6
; GFX11-TRUE16-NEXT:    s_denorm_mode 12
; GFX11-TRUE16-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
; GFX11-TRUE16-NEXT:    v_cmpx_lt_i32_e32 11, v4
; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB0_7
; GFX11-TRUE16-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
; GFX11-TRUE16-NEXT:    v_sub_nc_u32_e32 v4, v7, v8
; GFX11-TRUE16-NEXT:    s_mov_b32 s2, 0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v4, 11, v4
; GFX11-TRUE16-NEXT:  .LBB0_5: ; %frem.loop_body
; GFX11-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v7, v5 :: v_dual_add_nc_u32 v4, -11, v4
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v5, v7, v6
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX11-TRUE16-NEXT:    v_fma_f32 v5, -v5, v3, v7
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX11-TRUE16-NEXT:    v_add_f32_e32 v8, v5, v3
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc_lo
; GFX11-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v5, v5, 11
; GFX11-TRUE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX11-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB0_5
; GFX11-TRUE16-NEXT:  ; %bb.6: ; %Flow
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v5, v7
; GFX11-TRUE16-NEXT:  .LBB0_7: ; %Flow14
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v4, -10, v4
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v5, v4, v6
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX11-TRUE16-NEXT:    v_fma_f32 v4, -v5, v3, v4
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, v4, v3
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v2, v3, v2
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v0.l
; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v2.l, v2
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_bfi_b32 v2, 0x7fff, v2, v3
; GFX11-TRUE16-NEXT:  .LBB0_8: ; %Flow16
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v1.l
; GFX11-TRUE16-NEXT:    v_cmp_nge_f16_e64 s0, |v0.l|, 0x7c00
; GFX11-TRUE16-NEXT:    s_and_b32 s0, s0, vcc_lo
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v2.l, s0
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: frem_f16:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v4, |v0|
; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v3, |v1|
; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cmpx_ngt_f32_e32 v4, v3
; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT:  ; %bb.1: ; %frem.else
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0x8000, v0
; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v4, v3
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr4
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc_lo
; GFX11-FAKE16-NEXT:  ; %bb.2: ; %Flow15
; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB0_8
; GFX11-FAKE16-NEXT:  ; %bb.3: ; %frem.compute
; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v7, v4
; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v2, v4
; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v4, v3
; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v8, v3
; GFX11-FAKE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v5, v2, 11
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v3, v4, 1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v2, -1, v8
; GFX11-FAKE16-NEXT:    v_div_scale_f32 v9, null, v3, v3, 1.0
; GFX11-FAKE16-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v3, 1.0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT:    v_xad_u32 v4, v2, -1, v7
; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v10, v9
; GFX11-FAKE16-NEXT:    s_denorm_mode 15
; GFX11-FAKE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v10, v11, v10
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v11, v6, v10
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v12, -v9, v11, v6
; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v11, v12, v10
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v6, -v9, v11, v6
; GFX11-FAKE16-NEXT:    s_denorm_mode 12
; GFX11-FAKE16-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
; GFX11-FAKE16-NEXT:    v_cmpx_lt_i32_e32 11, v4
; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB0_7
; GFX11-FAKE16-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
; GFX11-FAKE16-NEXT:    v_sub_nc_u32_e32 v4, v7, v8
; GFX11-FAKE16-NEXT:    s_mov_b32 s2, 0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, 11, v4
; GFX11-FAKE16-NEXT:  .LBB0_5: ; %frem.loop_body
; GFX11-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v7, v5 :: v_dual_add_nc_u32 v4, -11, v4
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v5, v7, v6
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX11-FAKE16-NEXT:    v_fma_f32 v5, -v5, v3, v7
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX11-FAKE16-NEXT:    v_add_f32_e32 v8, v5, v3
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc_lo
; GFX11-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v5, v5, 11
; GFX11-FAKE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX11-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB0_5
; GFX11-FAKE16-NEXT:  ; %bb.6: ; %Flow
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, v7
; GFX11-FAKE16-NEXT:  .LBB0_7: ; %Flow14
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, -10, v4
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v5, v4, v6
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX11-FAKE16-NEXT:    v_fma_f32 v4, -v5, v3, v4
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, v4, v3
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v2, v3, v2
; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v2, v2
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_bfi_b32 v2, 0x7fff, v2, v0
; GFX11-FAKE16-NEXT:  .LBB0_8: ; %Flow16
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v1
; GFX11-FAKE16-NEXT:    v_cmp_nge_f16_e64 s0, |v0|, 0x7c00
; GFX11-FAKE16-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-TRUE16-LABEL: frem_f16:
; GFX1150-TRUE16:       ; %bb.0:
; GFX1150-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.l
; GFX1150-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cvt_f32_f16_e64 v3, |v2.l|
; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v1.l
; GFX1150-TRUE16-NEXT:    v_cvt_f32_f16_e64 v4, |v2.l|
; GFX1150-TRUE16-NEXT:    ; implicit-def: $vgpr2_lo16
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cmpx_ngt_f32_e32 v3, v4
; GFX1150-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX1150-TRUE16-NEXT:  ; %bb.1: ; %frem.else
; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.l
; GFX1150-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v3, v4
; GFX1150-TRUE16-NEXT:    ; implicit-def: $vgpr3
; GFX1150-TRUE16-NEXT:    ; implicit-def: $vgpr4
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_and_b16 v2.h, 0x8000, v2.l
; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v2.l, v2.l, v2.h, vcc_lo
; GFX1150-TRUE16-NEXT:  ; %bb.2: ; %Flow15
; GFX1150-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1150-TRUE16-NEXT:    s_cbranch_execz .LBB0_8
; GFX1150-TRUE16-NEXT:  ; %bb.3: ; %frem.compute
; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v7, v3
; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v2, v3
; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v3, v4
; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v8, v4
; GFX1150-TRUE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v5, v2, 11
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v3, v3, 1
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v2, -1, v8
; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v9, null, v3, v3, 1.0
; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v3, 1.0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT:    v_xad_u32 v4, v2, -1, v7
; GFX1150-TRUE16-NEXT:    v_rcp_f32_e32 v10, v9
; GFX1150-TRUE16-NEXT:    s_denorm_mode 15
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v10, v11, v10
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v11, v6, v10
; GFX1150-TRUE16-NEXT:    v_fma_f32 v12, -v9, v11, v6
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v11, v12, v10
; GFX1150-TRUE16-NEXT:    v_fma_f32 v6, -v9, v11, v6
; GFX1150-TRUE16-NEXT:    s_denorm_mode 12
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
; GFX1150-TRUE16-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
; GFX1150-TRUE16-NEXT:    v_cmpx_lt_i32_e32 11, v4
; GFX1150-TRUE16-NEXT:    s_cbranch_execz .LBB0_7
; GFX1150-TRUE16-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
; GFX1150-TRUE16-NEXT:    v_sub_nc_u32_e32 v4, v7, v8
; GFX1150-TRUE16-NEXT:    s_mov_b32 s2, 0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v4, 11, v4
; GFX1150-TRUE16-NEXT:  .LBB0_5: ; %frem.loop_body
; GFX1150-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_dual_mov_b32 v7, v5 :: v_dual_add_nc_u32 v4, -11, v4
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v5, v7, v6
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX1150-TRUE16-NEXT:    v_fma_f32 v5, -v5, v3, v7
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v8, v5, v3
; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc_lo
; GFX1150-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v5, v5, 11
; GFX1150-TRUE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1150-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1150-TRUE16-NEXT:    s_cbranch_execnz .LBB0_5
; GFX1150-TRUE16-NEXT:  ; %bb.6: ; %Flow
; GFX1150-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v5, v7
; GFX1150-TRUE16-NEXT:  .LBB0_7: ; %Flow14
; GFX1150-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v4, -10, v4
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v5, v4, v6
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX1150-TRUE16-NEXT:    v_fma_f32 v4, -v5, v3, v4
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v3, v4, v3
; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v2, v3, v2
; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v0.l
; GFX1150-TRUE16-NEXT:    v_cvt_f16_f32_e32 v2.l, v2
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_bfi_b32 v2, 0x7fff, v2, v3
; GFX1150-TRUE16-NEXT:  .LBB0_8: ; %Flow16
; GFX1150-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1150-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v1.l
; GFX1150-TRUE16-NEXT:    v_cmp_nge_f16_e64 s0, |v0.l|, 0x7c00
; GFX1150-TRUE16-NEXT:    s_and_b32 s0, s0, vcc_lo
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v2.l, s0
; GFX1150-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-FAKE16-LABEL: frem_f16:
; GFX1150-FAKE16:       ; %bb.0:
; GFX1150-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-FAKE16-NEXT:    v_cvt_f32_f16_e64 v4, |v0|
; GFX1150-FAKE16-NEXT:    v_cvt_f32_f16_e64 v3, |v1|
; GFX1150-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX1150-FAKE16-NEXT:    ; implicit-def: $vgpr2
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cmpx_ngt_f32_e32 v4, v3
; GFX1150-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX1150-FAKE16-NEXT:  ; %bb.1: ; %frem.else
; GFX1150-FAKE16-NEXT:    v_and_b32_e32 v2, 0x8000, v0
; GFX1150-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v4, v3
; GFX1150-FAKE16-NEXT:    ; implicit-def: $vgpr4
; GFX1150-FAKE16-NEXT:    ; implicit-def: $vgpr3
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc_lo
; GFX1150-FAKE16-NEXT:  ; %bb.2: ; %Flow15
; GFX1150-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1150-FAKE16-NEXT:    s_cbranch_execz .LBB0_8
; GFX1150-FAKE16-NEXT:  ; %bb.3: ; %frem.compute
; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v7, v4
; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v2, v4
; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v4, v3
; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v8, v3
; GFX1150-FAKE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v5, v2, 11
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v3, v4, 1
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v2, -1, v8
; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v9, null, v3, v3, 1.0
; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v3, 1.0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT:    v_xad_u32 v4, v2, -1, v7
; GFX1150-FAKE16-NEXT:    v_rcp_f32_e32 v10, v9
; GFX1150-FAKE16-NEXT:    s_denorm_mode 15
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v10, v11, v10
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v11, v6, v10
; GFX1150-FAKE16-NEXT:    v_fma_f32 v12, -v9, v11, v6
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v11, v12, v10
; GFX1150-FAKE16-NEXT:    v_fma_f32 v6, -v9, v11, v6
; GFX1150-FAKE16-NEXT:    s_denorm_mode 12
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
; GFX1150-FAKE16-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
; GFX1150-FAKE16-NEXT:    v_cmpx_lt_i32_e32 11, v4
; GFX1150-FAKE16-NEXT:    s_cbranch_execz .LBB0_7
; GFX1150-FAKE16-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
; GFX1150-FAKE16-NEXT:    v_sub_nc_u32_e32 v4, v7, v8
; GFX1150-FAKE16-NEXT:    s_mov_b32 s2, 0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v4, 11, v4
; GFX1150-FAKE16-NEXT:  .LBB0_5: ; %frem.loop_body
; GFX1150-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_dual_mov_b32 v7, v5 :: v_dual_add_nc_u32 v4, -11, v4
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v5, v7, v6
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX1150-FAKE16-NEXT:    v_fma_f32 v5, -v5, v3, v7
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v8, v5, v3
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc_lo
; GFX1150-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v5, v5, 11
; GFX1150-FAKE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1150-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1150-FAKE16-NEXT:    s_cbranch_execnz .LBB0_5
; GFX1150-FAKE16-NEXT:  ; %bb.6: ; %Flow
; GFX1150-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v5, v7
; GFX1150-FAKE16-NEXT:  .LBB0_7: ; %Flow14
; GFX1150-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v4, -10, v4
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v5, v4, v6
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX1150-FAKE16-NEXT:    v_fma_f32 v4, -v5, v3, v4
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v3, v4, v3
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v2, v3, v2
; GFX1150-FAKE16-NEXT:    v_cvt_f16_f32_e32 v2, v2
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_bfi_b32 v2, 0x7fff, v2, v0
; GFX1150-FAKE16-NEXT:  .LBB0_8: ; %Flow16
; GFX1150-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1150-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v1
; GFX1150-FAKE16-NEXT:    v_cmp_nge_f16_e64 s0, |v0|, 0x7c00
; GFX1150-FAKE16-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
; GFX1150-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-TRUE16-LABEL: frem_f16:
; GFX1200-TRUE16:       ; %bb.0:
; GFX1200-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.l
; GFX1200-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cvt_f32_f16_e64 v3, |v2.l|
; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v1.l
; GFX1200-TRUE16-NEXT:    v_cvt_f32_f16_e64 v4, |v2.l|
; GFX1200-TRUE16-NEXT:    ; implicit-def: $vgpr2_lo16
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cmpx_ngt_f32_e32 v3, v4
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX1200-TRUE16-NEXT:  ; %bb.1: ; %frem.else
; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.l
; GFX1200-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v3, v4
; GFX1200-TRUE16-NEXT:    ; implicit-def: $vgpr3
; GFX1200-TRUE16-NEXT:    ; implicit-def: $vgpr4
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_and_b16 v2.h, 0x8000, v2.l
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v2.l, v2.l, v2.h, vcc_lo
; GFX1200-TRUE16-NEXT:  ; %bb.2: ; %Flow15
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1200-TRUE16-NEXT:    s_cbranch_execz .LBB0_8
; GFX1200-TRUE16-NEXT:  ; %bb.3: ; %frem.compute
; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v7, v3
; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v2, v3
; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v3, v4
; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v8, v4
; GFX1200-TRUE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v5, v2, 11
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v3, v3, 1
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v9, null, v3, v3, 1.0
; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v3, 1.0
; GFX1200-TRUE16-NEXT:    v_rcp_f32_e32 v10, v9
; GFX1200-TRUE16-NEXT:    s_denorm_mode 15
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v10, v11, v10
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_dual_mul_f32 v11, v6, v10 :: v_dual_add_nc_u32 v2, -1, v8
; GFX1200-TRUE16-NEXT:    v_xad_u32 v4, v2, -1, v7
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f32 v12, -v9, v11, v6
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v11, v12, v10
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f32 v6, -v9, v11, v6
; GFX1200-TRUE16-NEXT:    s_denorm_mode 12
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
; GFX1200-TRUE16-NEXT:    v_cmpx_lt_i32_e32 11, v4
; GFX1200-TRUE16-NEXT:    s_cbranch_execz .LBB0_7
; GFX1200-TRUE16-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
; GFX1200-TRUE16-NEXT:    v_sub_nc_u32_e32 v4, v7, v8
; GFX1200-TRUE16-NEXT:    s_mov_b32 s2, 0
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v4, 11, v4
; GFX1200-TRUE16-NEXT:  .LBB0_5: ; %frem.loop_body
; GFX1200-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_dual_mov_b32 v7, v5 :: v_dual_add_nc_u32 v4, -11, v4
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v5, v7, v6
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX1200-TRUE16-NEXT:    v_fma_f32 v5, -v5, v3, v7
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v8, v5, v3
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc_lo
; GFX1200-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v5, v5, 11
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1200-TRUE16-NEXT:    s_cbranch_execnz .LBB0_5
; GFX1200-TRUE16-NEXT:  ; %bb.6: ; %Flow
; GFX1200-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v5, v7
; GFX1200-TRUE16-NEXT:  .LBB0_7: ; %Flow14
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v4, -10, v4
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v5, v4, v6
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX1200-TRUE16-NEXT:    v_fma_f32 v4, -v5, v3, v4
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v3, v4, v3
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v2, v3, v2
; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v0.l
; GFX1200-TRUE16-NEXT:    v_cvt_f16_f32_e32 v2.l, v2
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_bfi_b32 v2, 0x7fff, v2, v3
; GFX1200-TRUE16-NEXT:  .LBB0_8: ; %Flow16
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1200-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v1.l
; GFX1200-TRUE16-NEXT:    v_cmp_nge_f16_e64 s0, |v0.l|, 0x7c00
; GFX1200-TRUE16-NEXT:    s_and_b32 s0, s0, vcc_lo
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v2.l, s0
; GFX1200-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-FAKE16-LABEL: frem_f16:
; GFX1200-FAKE16:       ; %bb.0:
; GFX1200-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1200-FAKE16-NEXT:    v_cvt_f32_f16_e64 v4, |v0|
; GFX1200-FAKE16-NEXT:    v_cvt_f32_f16_e64 v3, |v1|
; GFX1200-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX1200-FAKE16-NEXT:    ; implicit-def: $vgpr2
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cmpx_ngt_f32_e32 v4, v3
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX1200-FAKE16-NEXT:  ; %bb.1: ; %frem.else
; GFX1200-FAKE16-NEXT:    v_and_b32_e32 v2, 0x8000, v0
; GFX1200-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v4, v3
; GFX1200-FAKE16-NEXT:    ; implicit-def: $vgpr4
; GFX1200-FAKE16-NEXT:    ; implicit-def: $vgpr3
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc_lo
; GFX1200-FAKE16-NEXT:  ; %bb.2: ; %Flow15
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1200-FAKE16-NEXT:    s_cbranch_execz .LBB0_8
; GFX1200-FAKE16-NEXT:  ; %bb.3: ; %frem.compute
; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v7, v4
; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v2, v4
; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v4, v3
; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v8, v3
; GFX1200-FAKE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v5, v2, 11
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v3, v4, 1
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v9, null, v3, v3, 1.0
; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v3, 1.0
; GFX1200-FAKE16-NEXT:    v_rcp_f32_e32 v10, v9
; GFX1200-FAKE16-NEXT:    s_denorm_mode 15
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v10, v11, v10
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_dual_mul_f32 v11, v6, v10 :: v_dual_add_nc_u32 v2, -1, v8
; GFX1200-FAKE16-NEXT:    v_xad_u32 v4, v2, -1, v7
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f32 v12, -v9, v11, v6
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v11, v12, v10
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f32 v6, -v9, v11, v6
; GFX1200-FAKE16-NEXT:    s_denorm_mode 12
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
; GFX1200-FAKE16-NEXT:    v_cmpx_lt_i32_e32 11, v4
; GFX1200-FAKE16-NEXT:    s_cbranch_execz .LBB0_7
; GFX1200-FAKE16-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
; GFX1200-FAKE16-NEXT:    v_sub_nc_u32_e32 v4, v7, v8
; GFX1200-FAKE16-NEXT:    s_mov_b32 s2, 0
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v4, 11, v4
; GFX1200-FAKE16-NEXT:  .LBB0_5: ; %frem.loop_body
; GFX1200-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_dual_mov_b32 v7, v5 :: v_dual_add_nc_u32 v4, -11, v4
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v5, v7, v6
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX1200-FAKE16-NEXT:    v_fma_f32 v5, -v5, v3, v7
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v8, v5, v3
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc_lo
; GFX1200-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v5, v5, 11
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1200-FAKE16-NEXT:    s_cbranch_execnz .LBB0_5
; GFX1200-FAKE16-NEXT:  ; %bb.6: ; %Flow
; GFX1200-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v5, v7
; GFX1200-FAKE16-NEXT:  .LBB0_7: ; %Flow14
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v4, -10, v4
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v5, v4, v6
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX1200-FAKE16-NEXT:    v_fma_f32 v4, -v5, v3, v4
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v3, v4, v3
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v2, v3, v2
; GFX1200-FAKE16-NEXT:    v_cvt_f16_f32_e32 v2, v2
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_bfi_b32 v2, 0x7fff, v2, v0
; GFX1200-FAKE16-NEXT:  .LBB0_8: ; %Flow16
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1200-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v1
; GFX1200-FAKE16-NEXT:    v_cmp_nge_f16_e64 s0, |v0|, 0x7c00
; GFX1200-FAKE16-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
; GFX1200-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %r2 = frem half %in1, %in2
  ret half %r2
}

define half @fast_frem_f16(half %in1, half %in2) #0 {
; SI-LABEL: fast_frem_f16:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cvt_f32_f16_e32 v4, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v2, v0
; SI-NEXT:    v_div_scale_f32 v1, s[4:5], v4, v4, v2
; SI-NEXT:    v_rcp_f32_e32 v3, v1
; SI-NEXT:    v_div_scale_f32 v0, vcc, v2, v4, v2
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    s_movk_i32 s4, 0x3f1
; SI-NEXT:    v_fma_f32 v5, -v1, v3, 1.0
; SI-NEXT:    v_fma_f32 v3, v5, v3, v3
; SI-NEXT:    v_mul_f32_e32 v5, v0, v3
; SI-NEXT:    v_fma_f32 v6, -v1, v5, v0
; SI-NEXT:    v_fma_f32 v5, v6, v3, v5
; SI-NEXT:    v_fma_f32 v0, -v1, v5, v0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    v_div_fmas_f32 v0, v0, v3, v5
; SI-NEXT:    v_div_fixup_f32 v0, v0, v4, v2
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-NEXT:    v_cvt_f64_f32_e32 v[2:3], v2
; SI-NEXT:    v_cvt_f64_f32_e32 v[4:5], v4
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_trunc_f32_e32 v0, v0
; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-NEXT:    v_cvt_f32_f16_e64 v0, -v0
; SI-NEXT:    v_cvt_f64_f32_e32 v[0:1], v0
; SI-NEXT:    v_fma_f64 v[0:1], v[0:1], v[4:5], v[2:3]
; SI-NEXT:    v_and_b32_e32 v2, 0x1ff, v1
; SI-NEXT:    v_or_b32_e32 v0, v2, v0
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT:    v_lshrrev_b32_e32 v2, 8, v1
; SI-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT:    v_and_b32_e32 v2, 0xffe, v2
; SI-NEXT:    v_bfe_u32 v3, v1, 20, 11
; SI-NEXT:    v_or_b32_e32 v0, v2, v0
; SI-NEXT:    v_sub_i32_e32 v4, vcc, s4, v3
; SI-NEXT:    v_or_b32_e32 v2, 0x1000, v0
; SI-NEXT:    v_med3_i32 v4, v4, 0, 13
; SI-NEXT:    v_lshrrev_b32_e32 v5, v4, v2
; SI-NEXT:    v_lshlrev_b32_e32 v4, v4, v5
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, v4, v2
; SI-NEXT:    s_movk_i32 s4, 0xfc10
; SI-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
; SI-NEXT:    v_add_i32_e32 v3, vcc, s4, v3
; SI-NEXT:    v_lshlrev_b32_e32 v4, 12, v3
; SI-NEXT:    v_or_b32_e32 v2, v5, v2
; SI-NEXT:    v_or_b32_e32 v4, v0, v4
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v3
; SI-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; SI-NEXT:    v_and_b32_e32 v4, 7, v2
; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v4
; SI-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v4
; SI-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
; SI-NEXT:    v_or_b32_e32 v4, v4, v5
; SI-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
; SI-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v3
; SI-NEXT:    v_mov_b32_e32 v4, 0x7c00
; SI-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT:    v_mov_b32_e32 v0, 0x7e00
; SI-NEXT:    s_movk_i32 s4, 0x40f
; SI-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
; SI-NEXT:    v_cmp_eq_u32_e32 vcc, s4, v3
; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
; SI-NEXT:    v_and_b32_e32 v1, 0x8000, v1
; SI-NEXT:    v_or_b32_e32 v0, v1, v0
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; CI-LABEL: fast_frem_f16:
; CI:       ; %bb.0:
; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-NEXT:    v_cvt_f32_f16_e32 v4, v1
; CI-NEXT:    v_cvt_f32_f16_e32 v2, v0
; CI-NEXT:    v_div_scale_f32 v1, s[4:5], v4, v4, v2
; CI-NEXT:    v_div_scale_f32 v0, vcc, v2, v4, v2
; CI-NEXT:    s_movk_i32 s4, 0x3f1
; CI-NEXT:    v_rcp_f32_e32 v3, v1
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v5, -v1, v3, 1.0
; CI-NEXT:    v_fma_f32 v3, v5, v3, v3
; CI-NEXT:    v_mul_f32_e32 v5, v0, v3
; CI-NEXT:    v_fma_f32 v6, -v1, v5, v0
; CI-NEXT:    v_fma_f32 v5, v6, v3, v5
; CI-NEXT:    v_fma_f32 v0, -v1, v5, v0
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v0, v0, v3, v5
; CI-NEXT:    v_div_fixup_f32 v0, v0, v4, v2
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; CI-NEXT:    v_cvt_f64_f32_e32 v[2:3], v2
; CI-NEXT:    v_cvt_f64_f32_e32 v[4:5], v4
; CI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; CI-NEXT:    v_trunc_f32_e32 v0, v0
; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; CI-NEXT:    v_cvt_f32_f16_e64 v0, -v0
; CI-NEXT:    v_cvt_f64_f32_e32 v[0:1], v0
; CI-NEXT:    v_fma_f64 v[0:1], v[0:1], v[4:5], v[2:3]
; CI-NEXT:    v_and_b32_e32 v2, 0x1ff, v1
; CI-NEXT:    v_or_b32_e32 v0, v2, v0
; CI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; CI-NEXT:    v_lshrrev_b32_e32 v2, 8, v1
; CI-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; CI-NEXT:    v_and_b32_e32 v2, 0xffe, v2
; CI-NEXT:    v_bfe_u32 v3, v1, 20, 11
; CI-NEXT:    v_or_b32_e32 v0, v2, v0
; CI-NEXT:    v_sub_i32_e32 v4, vcc, s4, v3
; CI-NEXT:    v_or_b32_e32 v2, 0x1000, v0
; CI-NEXT:    v_med3_i32 v4, v4, 0, 13
; CI-NEXT:    v_lshrrev_b32_e32 v5, v4, v2
; CI-NEXT:    v_lshlrev_b32_e32 v4, v4, v5
; CI-NEXT:    v_cmp_ne_u32_e32 vcc, v4, v2
; CI-NEXT:    s_movk_i32 s4, 0xfc10
; CI-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
; CI-NEXT:    v_add_i32_e32 v3, vcc, s4, v3
; CI-NEXT:    v_lshlrev_b32_e32 v4, 12, v3
; CI-NEXT:    v_or_b32_e32 v2, v5, v2
; CI-NEXT:    v_or_b32_e32 v4, v0, v4
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v3
; CI-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; CI-NEXT:    v_and_b32_e32 v4, 7, v2
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v4
; CI-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
; CI-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v4
; CI-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
; CI-NEXT:    v_or_b32_e32 v4, v4, v5
; CI-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
; CI-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v3
; CI-NEXT:    v_mov_b32_e32 v4, 0x7c00
; CI-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; CI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; CI-NEXT:    v_mov_b32_e32 v0, 0x7e00
; CI-NEXT:    s_movk_i32 s4, 0x40f
; CI-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
; CI-NEXT:    v_cmp_eq_u32_e32 vcc, s4, v3
; CI-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
; CI-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
; CI-NEXT:    v_and_b32_e32 v1, 0x8000, v1
; CI-NEXT:    v_or_b32_e32 v0, v1, v0
; CI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: fast_frem_f16:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cvt_f32_f16_e32 v3, v1
; VI-NEXT:    v_cvt_f32_f16_e32 v2, v0
; VI-NEXT:    v_rcp_f32_e32 v4, v3
; VI-NEXT:    v_mul_f32_e32 v5, v2, v4
; VI-NEXT:    v_mad_f32 v6, -v3, v5, v2
; VI-NEXT:    v_mac_f32_e32 v5, v6, v4
; VI-NEXT:    v_mad_f32 v2, -v3, v5, v2
; VI-NEXT:    v_mul_f32_e32 v2, v2, v4
; VI-NEXT:    v_and_b32_e32 v2, 0xff800000, v2
; VI-NEXT:    v_add_f32_e32 v2, v2, v5
; VI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; VI-NEXT:    v_div_fixup_f16 v2, v2, v1, v0
; VI-NEXT:    v_trunc_f16_e32 v2, v2
; VI-NEXT:    v_fma_f16 v0, -v2, v1, v0
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: fast_frem_f16:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_f32_f16_e32 v2, v1
; GFX9-NEXT:    v_rcp_f32_e32 v2, v2
; GFX9-NEXT:    v_mad_mix_f32 v3, v0, v2, neg(0) op_sel_hi:[1,0,0]
; GFX9-NEXT:    v_mad_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
; GFX9-NEXT:    v_mac_f32_e32 v3, v4, v2
; GFX9-NEXT:    v_mad_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
; GFX9-NEXT:    v_mul_f32_e32 v2, v4, v2
; GFX9-NEXT:    v_and_b32_e32 v2, 0xff800000, v2
; GFX9-NEXT:    v_add_f32_e32 v2, v2, v3
; GFX9-NEXT:    v_cvt_f16_f32_e32 v2, v2
; GFX9-NEXT:    v_div_fixup_f16 v2, v2, v1, v0
; GFX9-NEXT:    v_trunc_f16_e32 v2, v2
; GFX9-NEXT:    v_fma_f16 v0, -v2, v1, v0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: fast_frem_f16:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cvt_f32_f16_e32 v2, v1
; GFX10-NEXT:    v_cvt_f32_f16_e32 v5, v0
; GFX10-NEXT:    v_rcp_f32_e32 v3, v2
; GFX10-NEXT:    v_fma_mix_f32 v4, v0, v3, neg(0) op_sel_hi:[1,0,0]
; GFX10-NEXT:    v_mad_f32 v6, -v2, v4, v5
; GFX10-NEXT:    v_mac_f32_e32 v4, v6, v3
; GFX10-NEXT:    v_mad_f32 v2, -v2, v4, v5
; GFX10-NEXT:    v_mul_f32_e32 v2, v2, v3
; GFX10-NEXT:    v_and_b32_e32 v2, 0xff800000, v2
; GFX10-NEXT:    v_fma_mixlo_f16 v2, v2, 1.0, v4 op_sel_hi:[0,1,0]
; GFX10-NEXT:    v_div_fixup_f16 v2, v2, v1, v0
; GFX10-NEXT:    v_trunc_f16_e32 v2, v2
; GFX10-NEXT:    v_fma_f16 v0, -v2, v1, v0
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: fast_frem_f16:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v4, v1.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v0.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v1.l
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v4, v4
; GFX11-TRUE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v5, v3, v4, neg(0) op_sel_hi:[1,0,0]
; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v6, -v2, v5, v3 op_sel_hi:[1,0,1]
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v5, v6, v4
; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v2, -v2, v5, v3 op_sel_hi:[1,0,1]
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v2, v2, v4
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xff800000, v2
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_mixhi_f16 v1, v2, 1.0, v5 op_sel_hi:[0,1,0]
; GFX11-TRUE16-NEXT:    v_div_fixup_f16 v0.h, v1.h, v1.l, v0.l
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_trunc_f16_e32 v0.h, v0.h
; GFX11-TRUE16-NEXT:    v_fma_f16 v0.l, -v0.h, v1.l, v0.l
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fast_frem_f16:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v2, v1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v2, v2
; GFX11-FAKE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v3, v0, v2, neg(0) op_sel_hi:[1,0,0]
; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v3, v4, v2
; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v2, v4, v2
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff800000, v2
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_mixlo_f16 v2, v2, 1.0, v3 op_sel_hi:[0,1,0]
; GFX11-FAKE16-NEXT:    v_div_fixup_f16 v2, v2, v1, v0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_trunc_f16_e32 v2, v2
; GFX11-FAKE16-NEXT:    v_fma_f16 v0, -v2, v1, v0
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-TRUE16-LABEL: fast_frem_f16:
; GFX1150-TRUE16:       ; %bb.0:
; GFX1150-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-TRUE16-NEXT:    v_cvt_f32_f16_e32 v4, v1.l
; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v0.l
; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v1.l
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(TRANS32_DEP_1)
; GFX1150-TRUE16-NEXT:    v_rcp_f32_e32 v4, v4
; GFX1150-TRUE16-NEXT:    v_fma_mix_f32 v5, v3, v4, neg(0) op_sel_hi:[1,0,0]
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fma_mix_f32 v6, -v2, v5, v3 op_sel_hi:[1,0,1]
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v5, v6, v4
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fma_mix_f32 v2, -v2, v5, v3 op_sel_hi:[1,0,1]
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v2, v2, v4
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_and_b32_e32 v2, 0xff800000, v2
; GFX1150-TRUE16-NEXT:    v_fma_mixhi_f16 v1, v2, 1.0, v5 op_sel_hi:[0,1,0]
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_div_fixup_f16 v0.h, v1.h, v1.l, v0.l
; GFX1150-TRUE16-NEXT:    v_trunc_f16_e32 v0.h, v0.h
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fma_f16 v0.l, -v0.h, v1.l, v0.l
; GFX1150-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-FAKE16-LABEL: fast_frem_f16:
; GFX1150-FAKE16:       ; %bb.0:
; GFX1150-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-FAKE16-NEXT:    v_cvt_f32_f16_e32 v2, v1
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1)
; GFX1150-FAKE16-NEXT:    v_rcp_f32_e32 v2, v2
; GFX1150-FAKE16-NEXT:    v_fma_mix_f32 v3, v0, v2, neg(0) op_sel_hi:[1,0,0]
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v3, v4, v2
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v2, v4, v2
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff800000, v2
; GFX1150-FAKE16-NEXT:    v_fma_mixlo_f16 v2, v2, 1.0, v3 op_sel_hi:[0,1,0]
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_div_fixup_f16 v2, v2, v1, v0
; GFX1150-FAKE16-NEXT:    v_trunc_f16_e32 v2, v2
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fma_f16 v0, -v2, v1, v0
; GFX1150-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-TRUE16-LABEL: fast_frem_f16:
; GFX1200-TRUE16:       ; %bb.0:
; GFX1200-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1200-TRUE16-NEXT:    v_cvt_f32_f16_e32 v4, v1.l
; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v0.l
; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v1.l
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(TRANS32_DEP_1)
; GFX1200-TRUE16-NEXT:    v_rcp_f32_e32 v4, v4
; GFX1200-TRUE16-NEXT:    v_fma_mix_f32 v5, v3, v4, neg(0) op_sel_hi:[1,0,0]
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_mix_f32 v6, -v2, v5, v3 op_sel_hi:[1,0,1]
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v5, v6, v4
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_mix_f32 v2, -v2, v5, v3 op_sel_hi:[1,0,1]
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v2, v2, v4
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_and_b32_e32 v2, 0xff800000, v2
; GFX1200-TRUE16-NEXT:    v_fma_mixhi_f16 v1, v2, 1.0, v5 op_sel_hi:[0,1,0]
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_div_fixup_f16 v0.h, v1.h, v1.l, v0.l
; GFX1200-TRUE16-NEXT:    v_trunc_f16_e32 v0.h, v0.h
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f16 v0.l, -v0.h, v1.l, v0.l
; GFX1200-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-FAKE16-LABEL: fast_frem_f16:
; GFX1200-FAKE16:       ; %bb.0:
; GFX1200-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1200-FAKE16-NEXT:    v_cvt_f32_f16_e32 v2, v1
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1)
; GFX1200-FAKE16-NEXT:    v_rcp_f32_e32 v2, v2
; GFX1200-FAKE16-NEXT:    v_fma_mix_f32 v3, v0, v2, neg(0) op_sel_hi:[1,0,0]
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v3, v4, v2
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v2, v4, v2
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff800000, v2
; GFX1200-FAKE16-NEXT:    v_fma_mixlo_f16 v2, v2, 1.0, v3 op_sel_hi:[0,1,0]
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_div_fixup_f16 v2, v2, v1, v0
; GFX1200-FAKE16-NEXT:    v_trunc_f16_e32 v2, v2
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f16 v0, -v2, v1, v0
; GFX1200-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %r2 = frem fast half %in1, %in2
  ret half %r2
}

define half @unsafe_frem_f16(half %in1, half %in2) #0 {
; SI-LABEL: unsafe_frem_f16:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cvt_f32_f16_e32 v4, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v2, v0
; SI-NEXT:    v_div_scale_f32 v1, s[4:5], v4, v4, v2
; SI-NEXT:    v_rcp_f32_e32 v3, v1
; SI-NEXT:    v_div_scale_f32 v0, vcc, v2, v4, v2
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    s_movk_i32 s4, 0x3f1
; SI-NEXT:    v_fma_f32 v5, -v1, v3, 1.0
; SI-NEXT:    v_fma_f32 v3, v5, v3, v3
; SI-NEXT:    v_mul_f32_e32 v5, v0, v3
; SI-NEXT:    v_fma_f32 v6, -v1, v5, v0
; SI-NEXT:    v_fma_f32 v5, v6, v3, v5
; SI-NEXT:    v_fma_f32 v0, -v1, v5, v0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    v_div_fmas_f32 v0, v0, v3, v5
; SI-NEXT:    v_div_fixup_f32 v0, v0, v4, v2
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-NEXT:    v_cvt_f64_f32_e32 v[2:3], v2
; SI-NEXT:    v_cvt_f64_f32_e32 v[4:5], v4
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_trunc_f32_e32 v0, v0
; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-NEXT:    v_cvt_f32_f16_e64 v0, -v0
; SI-NEXT:    v_cvt_f64_f32_e32 v[0:1], v0
; SI-NEXT:    v_fma_f64 v[0:1], v[0:1], v[4:5], v[2:3]
; SI-NEXT:    v_and_b32_e32 v2, 0x1ff, v1
; SI-NEXT:    v_or_b32_e32 v0, v2, v0
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT:    v_lshrrev_b32_e32 v2, 8, v1
; SI-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT:    v_and_b32_e32 v2, 0xffe, v2
; SI-NEXT:    v_bfe_u32 v3, v1, 20, 11
; SI-NEXT:    v_or_b32_e32 v0, v2, v0
; SI-NEXT:    v_sub_i32_e32 v4, vcc, s4, v3
; SI-NEXT:    v_or_b32_e32 v2, 0x1000, v0
; SI-NEXT:    v_med3_i32 v4, v4, 0, 13
; SI-NEXT:    v_lshrrev_b32_e32 v5, v4, v2
; SI-NEXT:    v_lshlrev_b32_e32 v4, v4, v5
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, v4, v2
; SI-NEXT:    s_movk_i32 s4, 0xfc10
; SI-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
; SI-NEXT:    v_add_i32_e32 v3, vcc, s4, v3
; SI-NEXT:    v_lshlrev_b32_e32 v4, 12, v3
; SI-NEXT:    v_or_b32_e32 v2, v5, v2
; SI-NEXT:    v_or_b32_e32 v4, v0, v4
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v3
; SI-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; SI-NEXT:    v_and_b32_e32 v4, 7, v2
; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v4
; SI-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v4
; SI-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
; SI-NEXT:    v_or_b32_e32 v4, v4, v5
; SI-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
; SI-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v3
; SI-NEXT:    v_mov_b32_e32 v4, 0x7c00
; SI-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT:    v_mov_b32_e32 v0, 0x7e00
; SI-NEXT:    s_movk_i32 s4, 0x40f
; SI-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
; SI-NEXT:    v_cmp_eq_u32_e32 vcc, s4, v3
; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
; SI-NEXT:    v_and_b32_e32 v1, 0x8000, v1
; SI-NEXT:    v_or_b32_e32 v0, v1, v0
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; CI-LABEL: unsafe_frem_f16:
; CI:       ; %bb.0:
; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-NEXT:    v_cvt_f32_f16_e32 v4, v1
; CI-NEXT:    v_cvt_f32_f16_e32 v2, v0
; CI-NEXT:    v_div_scale_f32 v1, s[4:5], v4, v4, v2
; CI-NEXT:    v_div_scale_f32 v0, vcc, v2, v4, v2
; CI-NEXT:    s_movk_i32 s4, 0x3f1
; CI-NEXT:    v_rcp_f32_e32 v3, v1
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v5, -v1, v3, 1.0
; CI-NEXT:    v_fma_f32 v3, v5, v3, v3
; CI-NEXT:    v_mul_f32_e32 v5, v0, v3
; CI-NEXT:    v_fma_f32 v6, -v1, v5, v0
; CI-NEXT:    v_fma_f32 v5, v6, v3, v5
; CI-NEXT:    v_fma_f32 v0, -v1, v5, v0
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v0, v0, v3, v5
; CI-NEXT:    v_div_fixup_f32 v0, v0, v4, v2
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; CI-NEXT:    v_cvt_f64_f32_e32 v[2:3], v2
; CI-NEXT:    v_cvt_f64_f32_e32 v[4:5], v4
; CI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; CI-NEXT:    v_trunc_f32_e32 v0, v0
; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; CI-NEXT:    v_cvt_f32_f16_e64 v0, -v0
; CI-NEXT:    v_cvt_f64_f32_e32 v[0:1], v0
; CI-NEXT:    v_fma_f64 v[0:1], v[0:1], v[4:5], v[2:3]
; CI-NEXT:    v_and_b32_e32 v2, 0x1ff, v1
; CI-NEXT:    v_or_b32_e32 v0, v2, v0
; CI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; CI-NEXT:    v_lshrrev_b32_e32 v2, 8, v1
; CI-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; CI-NEXT:    v_and_b32_e32 v2, 0xffe, v2
; CI-NEXT:    v_bfe_u32 v3, v1, 20, 11
; CI-NEXT:    v_or_b32_e32 v0, v2, v0
; CI-NEXT:    v_sub_i32_e32 v4, vcc, s4, v3
; CI-NEXT:    v_or_b32_e32 v2, 0x1000, v0
; CI-NEXT:    v_med3_i32 v4, v4, 0, 13
; CI-NEXT:    v_lshrrev_b32_e32 v5, v4, v2
; CI-NEXT:    v_lshlrev_b32_e32 v4, v4, v5
; CI-NEXT:    v_cmp_ne_u32_e32 vcc, v4, v2
; CI-NEXT:    s_movk_i32 s4, 0xfc10
; CI-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
; CI-NEXT:    v_add_i32_e32 v3, vcc, s4, v3
; CI-NEXT:    v_lshlrev_b32_e32 v4, 12, v3
; CI-NEXT:    v_or_b32_e32 v2, v5, v2
; CI-NEXT:    v_or_b32_e32 v4, v0, v4
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v3
; CI-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; CI-NEXT:    v_and_b32_e32 v4, 7, v2
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v4
; CI-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
; CI-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v4
; CI-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
; CI-NEXT:    v_or_b32_e32 v4, v4, v5
; CI-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
; CI-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v3
; CI-NEXT:    v_mov_b32_e32 v4, 0x7c00
; CI-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; CI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; CI-NEXT:    v_mov_b32_e32 v0, 0x7e00
; CI-NEXT:    s_movk_i32 s4, 0x40f
; CI-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
; CI-NEXT:    v_cmp_eq_u32_e32 vcc, s4, v3
; CI-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
; CI-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
; CI-NEXT:    v_and_b32_e32 v1, 0x8000, v1
; CI-NEXT:    v_or_b32_e32 v0, v1, v0
; CI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: unsafe_frem_f16:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cvt_f32_f16_e32 v3, v1
; VI-NEXT:    v_cvt_f32_f16_e32 v2, v0
; VI-NEXT:    v_rcp_f32_e32 v4, v3
; VI-NEXT:    v_mul_f32_e32 v5, v2, v4
; VI-NEXT:    v_mad_f32 v6, -v3, v5, v2
; VI-NEXT:    v_mac_f32_e32 v5, v6, v4
; VI-NEXT:    v_mad_f32 v2, -v3, v5, v2
; VI-NEXT:    v_mul_f32_e32 v2, v2, v4
; VI-NEXT:    v_and_b32_e32 v2, 0xff800000, v2
; VI-NEXT:    v_add_f32_e32 v2, v2, v5
; VI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; VI-NEXT:    v_div_fixup_f16 v2, v2, v1, v0
; VI-NEXT:    v_trunc_f16_e32 v2, v2
; VI-NEXT:    v_fma_f16 v0, -v2, v1, v0
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: unsafe_frem_f16:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_f32_f16_e32 v2, v1
; GFX9-NEXT:    v_rcp_f32_e32 v2, v2
; GFX9-NEXT:    v_mad_mix_f32 v3, v0, v2, neg(0) op_sel_hi:[1,0,0]
; GFX9-NEXT:    v_mad_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
; GFX9-NEXT:    v_mac_f32_e32 v3, v4, v2
; GFX9-NEXT:    v_mad_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
; GFX9-NEXT:    v_mul_f32_e32 v2, v4, v2
; GFX9-NEXT:    v_and_b32_e32 v2, 0xff800000, v2
; GFX9-NEXT:    v_add_f32_e32 v2, v2, v3
; GFX9-NEXT:    v_cvt_f16_f32_e32 v2, v2
; GFX9-NEXT:    v_div_fixup_f16 v2, v2, v1, v0
; GFX9-NEXT:    v_trunc_f16_e32 v2, v2
; GFX9-NEXT:    v_fma_f16 v0, -v2, v1, v0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: unsafe_frem_f16:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cvt_f32_f16_e32 v2, v1
; GFX10-NEXT:    v_cvt_f32_f16_e32 v5, v0
; GFX10-NEXT:    v_rcp_f32_e32 v3, v2
; GFX10-NEXT:    v_fma_mix_f32 v4, v0, v3, neg(0) op_sel_hi:[1,0,0]
; GFX10-NEXT:    v_mad_f32 v6, -v2, v4, v5
; GFX10-NEXT:    v_mac_f32_e32 v4, v6, v3
; GFX10-NEXT:    v_mad_f32 v2, -v2, v4, v5
; GFX10-NEXT:    v_mul_f32_e32 v2, v2, v3
; GFX10-NEXT:    v_and_b32_e32 v2, 0xff800000, v2
; GFX10-NEXT:    v_fma_mixlo_f16 v2, v2, 1.0, v4 op_sel_hi:[0,1,0]
; GFX10-NEXT:    v_div_fixup_f16 v2, v2, v1, v0
; GFX10-NEXT:    v_trunc_f16_e32 v2, v2
; GFX10-NEXT:    v_fma_f16 v0, -v2, v1, v0
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: unsafe_frem_f16:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v4, v1.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v0.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v1.l
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v4, v4
; GFX11-TRUE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v5, v3, v4, neg(0) op_sel_hi:[1,0,0]
; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v6, -v2, v5, v3 op_sel_hi:[1,0,1]
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v5, v6, v4
; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v2, -v2, v5, v3 op_sel_hi:[1,0,1]
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v2, v2, v4
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xff800000, v2
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_mixhi_f16 v1, v2, 1.0, v5 op_sel_hi:[0,1,0]
; GFX11-TRUE16-NEXT:    v_div_fixup_f16 v0.h, v1.h, v1.l, v0.l
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_trunc_f16_e32 v0.h, v0.h
; GFX11-TRUE16-NEXT:    v_fma_f16 v0.l, -v0.h, v1.l, v0.l
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: unsafe_frem_f16:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v2, v1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v2, v2
; GFX11-FAKE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v3, v0, v2, neg(0) op_sel_hi:[1,0,0]
; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v3, v4, v2
; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v2, v4, v2
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff800000, v2
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_mixlo_f16 v2, v2, 1.0, v3 op_sel_hi:[0,1,0]
; GFX11-FAKE16-NEXT:    v_div_fixup_f16 v2, v2, v1, v0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_trunc_f16_e32 v2, v2
; GFX11-FAKE16-NEXT:    v_fma_f16 v0, -v2, v1, v0
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-TRUE16-LABEL: unsafe_frem_f16:
; GFX1150-TRUE16:       ; %bb.0:
; GFX1150-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-TRUE16-NEXT:    v_cvt_f32_f16_e32 v4, v1.l
; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v0.l
; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v1.l
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(TRANS32_DEP_1)
; GFX1150-TRUE16-NEXT:    v_rcp_f32_e32 v4, v4
; GFX1150-TRUE16-NEXT:    v_fma_mix_f32 v5, v3, v4, neg(0) op_sel_hi:[1,0,0]
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fma_mix_f32 v6, -v2, v5, v3 op_sel_hi:[1,0,1]
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v5, v6, v4
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fma_mix_f32 v2, -v2, v5, v3 op_sel_hi:[1,0,1]
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v2, v2, v4
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_and_b32_e32 v2, 0xff800000, v2
; GFX1150-TRUE16-NEXT:    v_fma_mixhi_f16 v1, v2, 1.0, v5 op_sel_hi:[0,1,0]
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_div_fixup_f16 v0.h, v1.h, v1.l, v0.l
; GFX1150-TRUE16-NEXT:    v_trunc_f16_e32 v0.h, v0.h
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fma_f16 v0.l, -v0.h, v1.l, v0.l
; GFX1150-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-FAKE16-LABEL: unsafe_frem_f16:
; GFX1150-FAKE16:       ; %bb.0:
; GFX1150-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-FAKE16-NEXT:    v_cvt_f32_f16_e32 v2, v1
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1)
; GFX1150-FAKE16-NEXT:    v_rcp_f32_e32 v2, v2
; GFX1150-FAKE16-NEXT:    v_fma_mix_f32 v3, v0, v2, neg(0) op_sel_hi:[1,0,0]
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v3, v4, v2
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v2, v4, v2
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff800000, v2
; GFX1150-FAKE16-NEXT:    v_fma_mixlo_f16 v2, v2, 1.0, v3 op_sel_hi:[0,1,0]
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_div_fixup_f16 v2, v2, v1, v0
; GFX1150-FAKE16-NEXT:    v_trunc_f16_e32 v2, v2
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fma_f16 v0, -v2, v1, v0
; GFX1150-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-TRUE16-LABEL: unsafe_frem_f16:
; GFX1200-TRUE16:       ; %bb.0:
; GFX1200-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1200-TRUE16-NEXT:    v_cvt_f32_f16_e32 v4, v1.l
; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v0.l
; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v1.l
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(TRANS32_DEP_1)
; GFX1200-TRUE16-NEXT:    v_rcp_f32_e32 v4, v4
; GFX1200-TRUE16-NEXT:    v_fma_mix_f32 v5, v3, v4, neg(0) op_sel_hi:[1,0,0]
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_mix_f32 v6, -v2, v5, v3 op_sel_hi:[1,0,1]
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v5, v6, v4
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_mix_f32 v2, -v2, v5, v3 op_sel_hi:[1,0,1]
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v2, v2, v4
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_and_b32_e32 v2, 0xff800000, v2
; GFX1200-TRUE16-NEXT:    v_fma_mixhi_f16 v1, v2, 1.0, v5 op_sel_hi:[0,1,0]
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_div_fixup_f16 v0.h, v1.h, v1.l, v0.l
; GFX1200-TRUE16-NEXT:    v_trunc_f16_e32 v0.h, v0.h
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f16 v0.l, -v0.h, v1.l, v0.l
; GFX1200-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-FAKE16-LABEL: unsafe_frem_f16:
; GFX1200-FAKE16:       ; %bb.0:
; GFX1200-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1200-FAKE16-NEXT:    v_cvt_f32_f16_e32 v2, v1
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1)
; GFX1200-FAKE16-NEXT:    v_rcp_f32_e32 v2, v2
; GFX1200-FAKE16-NEXT:    v_fma_mix_f32 v3, v0, v2, neg(0) op_sel_hi:[1,0,0]
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v3, v4, v2
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v2, v4, v2
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff800000, v2
; GFX1200-FAKE16-NEXT:    v_fma_mixlo_f16 v2, v2, 1.0, v3 op_sel_hi:[0,1,0]
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_div_fixup_f16 v2, v2, v1, v0
; GFX1200-FAKE16-NEXT:    v_trunc_f16_e32 v2, v2
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f16 v0, -v2, v1, v0
; GFX1200-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %r2 = frem afn half %in1, %in2
  ret half %r2
}

define float @frem_f32(float %in1, float %in2) #0 {
; SI-LABEL: frem_f32:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cmp_ngt_f32_e64 s[4:5], |v0|, |v1|
; SI-NEXT:    ; implicit-def: $vgpr2
; SI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; SI-NEXT:  ; %bb.1: ; %frem.else
; SI-NEXT:    v_and_b32_e32 v2, 0x80000000, v0
; SI-NEXT:    v_cmp_eq_f32_e64 vcc, |v0|, |v1|
; SI-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc
; SI-NEXT:  ; %bb.2: ; %Flow13
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB3_8
; SI-NEXT:  ; %bb.3: ; %frem.compute
; SI-NEXT:    s_mov_b32 s6, 0x7f800000
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, s6
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v2, v0
; SI-NEXT:    v_cndmask_b32_e32 v7, 0, v2, vcc
; SI-NEXT:    v_frexp_mant_f32_e64 v2, |v0|
; SI-NEXT:    v_cndmask_b32_e64 v2, |v0|, v2, vcc
; SI-NEXT:    v_ldexp_f32_e64 v4, v2, 12
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v1|, s6
; SI-NEXT:    v_frexp_mant_f32_e64 v2, |v1|
; SI-NEXT:    v_cndmask_b32_e64 v3, |v1|, v2, vcc
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v2, v1
; SI-NEXT:    v_ldexp_f32_e64 v3, v3, 1
; SI-NEXT:    v_cndmask_b32_e32 v8, 0, v2, vcc
; SI-NEXT:    v_div_scale_f32 v9, s[6:7], v3, v3, 1.0
; SI-NEXT:    v_add_i32_e32 v2, vcc, -1, v8
; SI-NEXT:    v_rcp_f32_e32 v10, v9
; SI-NEXT:    v_not_b32_e32 v5, v2
; SI-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
; SI-NEXT:    v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; SI-NEXT:    v_fma_f32 v10, v11, v10, v10
; SI-NEXT:    v_mul_f32_e32 v11, v6, v10
; SI-NEXT:    v_fma_f32 v12, -v9, v11, v6
; SI-NEXT:    v_fma_f32 v11, v12, v10, v11
; SI-NEXT:    v_fma_f32 v6, -v9, v11, v6
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
; SI-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v5
; SI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; SI-NEXT:    s_cbranch_execz .LBB3_7
; SI-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
; SI-NEXT:    v_sub_i32_e32 v5, vcc, v7, v8
; SI-NEXT:    v_add_i32_e32 v5, vcc, 12, v5
; SI-NEXT:    s_mov_b64 s[8:9], 0
; SI-NEXT:  .LBB3_5: ; %frem.loop_body
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v7, v4
; SI-NEXT:    v_mul_f32_e32 v4, v7, v6
; SI-NEXT:    v_rndne_f32_e32 v4, v4
; SI-NEXT:    v_fma_f32 v4, -v4, v3, v7
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; SI-NEXT:    v_add_f32_e32 v8, v4, v3
; SI-NEXT:    v_cndmask_b32_e32 v4, v4, v8, vcc
; SI-NEXT:    v_add_i32_e32 v5, vcc, -12, v5
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v5
; SI-NEXT:    v_ldexp_f32_e64 v4, v4, 12
; SI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; SI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; SI-NEXT:    s_cbranch_execnz .LBB3_5
; SI-NEXT:  ; %bb.6: ; %Flow
; SI-NEXT:    s_or_b64 exec, exec, s[8:9]
; SI-NEXT:    v_mov_b32_e32 v4, v7
; SI-NEXT:  .LBB3_7: ; %Flow12
; SI-NEXT:    s_or_b64 exec, exec, s[6:7]
; SI-NEXT:    v_add_i32_e32 v5, vcc, -11, v5
; SI-NEXT:    v_ldexp_f32_e32 v4, v4, v5
; SI-NEXT:    v_mul_f32_e32 v5, v4, v6
; SI-NEXT:    v_rndne_f32_e32 v5, v5
; SI-NEXT:    v_fma_f32 v4, -v5, v3, v4
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; SI-NEXT:    v_add_f32_e32 v3, v4, v3
; SI-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; SI-NEXT:    v_ldexp_f32_e32 v2, v3, v2
; SI-NEXT:    s_brev_b32 s6, -2
; SI-NEXT:    v_bfi_b32 v2, s6, v2, v0
; SI-NEXT:  .LBB3_8: ; %Flow14
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    s_mov_b32 s4, 0x7f800000
; SI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v1
; SI-NEXT:    v_cmp_nge_f32_e64 s[4:5], |v0|, s4
; SI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; SI-NEXT:    v_mov_b32_e32 v0, 0x7fc00000
; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; CI-LABEL: frem_f32:
; CI:       ; %bb.0:
; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-NEXT:    v_cmp_ngt_f32_e64 s[4:5], |v0|, |v1|
; CI-NEXT:    ; implicit-def: $vgpr2
; CI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; CI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; CI-NEXT:  ; %bb.1: ; %frem.else
; CI-NEXT:    v_and_b32_e32 v2, 0x80000000, v0
; CI-NEXT:    v_cmp_eq_f32_e64 vcc, |v0|, |v1|
; CI-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc
; CI-NEXT:  ; %bb.2: ; %Flow13
; CI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; CI-NEXT:    s_cbranch_execz .LBB3_8
; CI-NEXT:  ; %bb.3: ; %frem.compute
; CI-NEXT:    v_frexp_mant_f32_e64 v3, |v1|
; CI-NEXT:    v_ldexp_f32_e64 v3, v3, 1
; CI-NEXT:    v_div_scale_f32 v9, s[6:7], v3, v3, 1.0
; CI-NEXT:    v_frexp_mant_f32_e64 v2, |v0|
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v8, v1
; CI-NEXT:    v_ldexp_f32_e64 v5, v2, 12
; CI-NEXT:    v_add_i32_e32 v2, vcc, -1, v8
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v7, v0
; CI-NEXT:    v_not_b32_e32 v4, v2
; CI-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
; CI-NEXT:    v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
; CI-NEXT:    v_rcp_f32_e32 v10, v9
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; CI-NEXT:    v_fma_f32 v10, v11, v10, v10
; CI-NEXT:    v_mul_f32_e32 v11, v6, v10
; CI-NEXT:    v_fma_f32 v12, -v9, v11, v6
; CI-NEXT:    v_fma_f32 v11, v12, v10, v11
; CI-NEXT:    v_fma_f32 v6, -v9, v11, v6
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v4
; CI-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
; CI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; CI-NEXT:    s_cbranch_execz .LBB3_7
; CI-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
; CI-NEXT:    v_sub_i32_e32 v4, vcc, v7, v8
; CI-NEXT:    v_add_i32_e32 v4, vcc, 12, v4
; CI-NEXT:    s_mov_b64 s[8:9], 0
; CI-NEXT:  .LBB3_5: ; %frem.loop_body
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v7, v5
; CI-NEXT:    v_mul_f32_e32 v5, v7, v6
; CI-NEXT:    v_rndne_f32_e32 v5, v5
; CI-NEXT:    v_fma_f32 v5, -v5, v3, v7
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
; CI-NEXT:    v_add_f32_e32 v8, v5, v3
; CI-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc
; CI-NEXT:    v_add_i32_e32 v4, vcc, -12, v4
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v4
; CI-NEXT:    v_ldexp_f32_e64 v5, v5, 12
; CI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; CI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; CI-NEXT:    s_cbranch_execnz .LBB3_5
; CI-NEXT:  ; %bb.6: ; %Flow
; CI-NEXT:    s_or_b64 exec, exec, s[8:9]
; CI-NEXT:    v_mov_b32_e32 v5, v7
; CI-NEXT:  .LBB3_7: ; %Flow12
; CI-NEXT:    s_or_b64 exec, exec, s[6:7]
; CI-NEXT:    v_add_i32_e32 v4, vcc, -11, v4
; CI-NEXT:    v_ldexp_f32_e32 v4, v5, v4
; CI-NEXT:    v_mul_f32_e32 v5, v4, v6
; CI-NEXT:    v_rndne_f32_e32 v5, v5
; CI-NEXT:    v_fma_f32 v4, -v5, v3, v4
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; CI-NEXT:    v_add_f32_e32 v3, v4, v3
; CI-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; CI-NEXT:    v_ldexp_f32_e32 v2, v3, v2
; CI-NEXT:    s_brev_b32 s6, -2
; CI-NEXT:    v_bfi_b32 v2, s6, v2, v0
; CI-NEXT:  .LBB3_8: ; %Flow14
; CI-NEXT:    s_or_b64 exec, exec, s[4:5]
; CI-NEXT:    s_mov_b32 s4, 0x7f800000
; CI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v1
; CI-NEXT:    v_cmp_nge_f32_e64 s[4:5], |v0|, s4
; CI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; CI-NEXT:    v_mov_b32_e32 v0, 0x7fc00000
; CI-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
; CI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: frem_f32:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ngt_f32_e64 s[4:5], |v0|, |v1|
; VI-NEXT:    ; implicit-def: $vgpr2
; VI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; VI-NEXT:  ; %bb.1: ; %frem.else
; VI-NEXT:    v_and_b32_e32 v2, 0x80000000, v0
; VI-NEXT:    v_cmp_eq_f32_e64 vcc, |v0|, |v1|
; VI-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc
; VI-NEXT:  ; %bb.2: ; %Flow13
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB3_8
; VI-NEXT:  ; %bb.3: ; %frem.compute
; VI-NEXT:    v_frexp_mant_f32_e64 v3, |v1|
; VI-NEXT:    v_ldexp_f32 v3, v3, 1
; VI-NEXT:    v_div_scale_f32 v9, s[6:7], v3, v3, 1.0
; VI-NEXT:    v_frexp_mant_f32_e64 v2, |v0|
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v8, v1
; VI-NEXT:    v_ldexp_f32 v5, v2, 12
; VI-NEXT:    v_add_u32_e32 v2, vcc, -1, v8
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v7, v0
; VI-NEXT:    v_not_b32_e32 v4, v2
; VI-NEXT:    v_add_u32_e32 v4, vcc, v4, v7
; VI-NEXT:    v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
; VI-NEXT:    v_rcp_f32_e32 v10, v9
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; VI-NEXT:    v_fma_f32 v10, v11, v10, v10
; VI-NEXT:    v_mul_f32_e32 v11, v6, v10
; VI-NEXT:    v_fma_f32 v12, -v9, v11, v6
; VI-NEXT:    v_fma_f32 v11, v12, v10, v11
; VI-NEXT:    v_fma_f32 v6, -v9, v11, v6
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; VI-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v4
; VI-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
; VI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; VI-NEXT:    s_cbranch_execz .LBB3_7
; VI-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
; VI-NEXT:    v_sub_u32_e32 v4, vcc, v7, v8
; VI-NEXT:    v_add_u32_e32 v4, vcc, 12, v4
; VI-NEXT:    s_mov_b64 s[8:9], 0
; VI-NEXT:  .LBB3_5: ; %frem.loop_body
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v7, v5
; VI-NEXT:    v_mul_f32_e32 v5, v7, v6
; VI-NEXT:    v_rndne_f32_e32 v5, v5
; VI-NEXT:    v_fma_f32 v5, -v5, v3, v7
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
; VI-NEXT:    v_add_f32_e32 v8, v5, v3
; VI-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc
; VI-NEXT:    v_add_u32_e32 v4, vcc, -12, v4
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v4
; VI-NEXT:    v_ldexp_f32 v5, v5, 12
; VI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; VI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; VI-NEXT:    s_cbranch_execnz .LBB3_5
; VI-NEXT:  ; %bb.6: ; %Flow
; VI-NEXT:    s_or_b64 exec, exec, s[8:9]
; VI-NEXT:    v_mov_b32_e32 v5, v7
; VI-NEXT:  .LBB3_7: ; %Flow12
; VI-NEXT:    s_or_b64 exec, exec, s[6:7]
; VI-NEXT:    v_add_u32_e32 v4, vcc, -11, v4
; VI-NEXT:    v_ldexp_f32 v4, v5, v4
; VI-NEXT:    v_mul_f32_e32 v5, v4, v6
; VI-NEXT:    v_rndne_f32_e32 v5, v5
; VI-NEXT:    v_fma_f32 v4, -v5, v3, v4
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; VI-NEXT:    v_add_f32_e32 v3, v4, v3
; VI-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; VI-NEXT:    v_ldexp_f32 v2, v3, v2
; VI-NEXT:    s_brev_b32 s6, -2
; VI-NEXT:    v_bfi_b32 v2, s6, v2, v0
; VI-NEXT:  .LBB3_8: ; %Flow14
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_mov_b32 s4, 0x7f800000
; VI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v1
; VI-NEXT:    v_cmp_nge_f32_e64 s[4:5], |v0|, s4
; VI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; VI-NEXT:    v_mov_b32_e32 v0, 0x7fc00000
; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: frem_f32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ngt_f32_e64 s[4:5], |v0|, |v1|
; GFX9-NEXT:    ; implicit-def: $vgpr2
; GFX9-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; GFX9-NEXT:  ; %bb.1: ; %frem.else
; GFX9-NEXT:    v_and_b32_e32 v2, 0x80000000, v0
; GFX9-NEXT:    v_cmp_eq_f32_e64 vcc, |v0|, |v1|
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc
; GFX9-NEXT:  ; %bb.2: ; %Flow13
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB3_8
; GFX9-NEXT:  ; %bb.3: ; %frem.compute
; GFX9-NEXT:    v_frexp_mant_f32_e64 v3, |v1|
; GFX9-NEXT:    v_ldexp_f32 v3, v3, 1
; GFX9-NEXT:    v_div_scale_f32 v9, s[6:7], v3, v3, 1.0
; GFX9-NEXT:    v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
; GFX9-NEXT:    v_frexp_mant_f32_e64 v2, |v0|
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v7, v0
; GFX9-NEXT:    v_ldexp_f32 v5, v2, 12
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v8, v1
; GFX9-NEXT:    v_add_u32_e32 v2, -1, v8
; GFX9-NEXT:    v_xad_u32 v4, v2, -1, v7
; GFX9-NEXT:    v_rcp_f32_e32 v10, v9
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; GFX9-NEXT:    v_fma_f32 v10, v11, v10, v10
; GFX9-NEXT:    v_mul_f32_e32 v11, v6, v10
; GFX9-NEXT:    v_fma_f32 v12, -v9, v11, v6
; GFX9-NEXT:    v_fma_f32 v11, v12, v10, v11
; GFX9-NEXT:    v_fma_f32 v6, -v9, v11, v6
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX9-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v4
; GFX9-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
; GFX9-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; GFX9-NEXT:    s_cbranch_execz .LBB3_7
; GFX9-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
; GFX9-NEXT:    v_sub_u32_e32 v4, v7, v8
; GFX9-NEXT:    v_add_u32_e32 v4, 12, v4
; GFX9-NEXT:    s_mov_b64 s[8:9], 0
; GFX9-NEXT:  .LBB3_5: ; %frem.loop_body
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v7, v5
; GFX9-NEXT:    v_mul_f32_e32 v5, v7, v6
; GFX9-NEXT:    v_rndne_f32_e32 v5, v5
; GFX9-NEXT:    v_fma_f32 v5, -v5, v3, v7
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
; GFX9-NEXT:    v_add_f32_e32 v8, v5, v3
; GFX9-NEXT:    v_add_u32_e32 v4, -12, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v4
; GFX9-NEXT:    v_ldexp_f32 v5, v5, 12
; GFX9-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; GFX9-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; GFX9-NEXT:    s_cbranch_execnz .LBB3_5
; GFX9-NEXT:  ; %bb.6: ; %Flow
; GFX9-NEXT:    s_or_b64 exec, exec, s[8:9]
; GFX9-NEXT:    v_mov_b32_e32 v5, v7
; GFX9-NEXT:  .LBB3_7: ; %Flow12
; GFX9-NEXT:    s_or_b64 exec, exec, s[6:7]
; GFX9-NEXT:    v_add_u32_e32 v4, -11, v4
; GFX9-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX9-NEXT:    v_mul_f32_e32 v5, v4, v6
; GFX9-NEXT:    v_rndne_f32_e32 v5, v5
; GFX9-NEXT:    v_fma_f32 v4, -v5, v3, v4
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; GFX9-NEXT:    v_add_f32_e32 v3, v4, v3
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX9-NEXT:    v_ldexp_f32 v2, v3, v2
; GFX9-NEXT:    s_brev_b32 s6, -2
; GFX9-NEXT:    v_bfi_b32 v2, s6, v2, v0
; GFX9-NEXT:  .LBB3_8: ; %Flow14
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_mov_b32 s4, 0x7f800000
; GFX9-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v1
; GFX9-NEXT:    v_cmp_nge_f32_e64 s[4:5], |v0|, s4
; GFX9-NEXT:    s_and_b64 vcc, s[4:5], vcc
; GFX9-NEXT:    v_mov_b32_e32 v0, 0x7fc00000
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: frem_f32:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cmp_ngt_f32_e64 s4, |v0|, |v1|
; GFX10-NEXT:    ; implicit-def: $vgpr2
; GFX10-NEXT:    s_and_saveexec_b32 s5, s4
; GFX10-NEXT:    s_xor_b32 s4, exec_lo, s5
; GFX10-NEXT:  ; %bb.1: ; %frem.else
; GFX10-NEXT:    v_and_b32_e32 v2, 0x80000000, v0
; GFX10-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v0|, |v1|
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc_lo
; GFX10-NEXT:  ; %bb.2: ; %Flow13
; GFX10-NEXT:    s_andn2_saveexec_b32 s4, s4
; GFX10-NEXT:    s_cbranch_execz .LBB3_8
; GFX10-NEXT:  ; %bb.3: ; %frem.compute
; GFX10-NEXT:    v_frexp_mant_f32_e64 v3, |v1|
; GFX10-NEXT:    v_frexp_mant_f32_e64 v2, |v0|
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v7, v0
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v8, v1
; GFX10-NEXT:    v_ldexp_f32 v3, v3, 1
; GFX10-NEXT:    v_ldexp_f32 v5, v2, 12
; GFX10-NEXT:    v_add_nc_u32_e32 v2, -1, v8
; GFX10-NEXT:    v_div_scale_f32 v9, s5, v3, v3, 1.0
; GFX10-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v3, 1.0
; GFX10-NEXT:    v_xad_u32 v4, v2, -1, v7
; GFX10-NEXT:    v_rcp_f32_e32 v10, v9
; GFX10-NEXT:    s_denorm_mode 15
; GFX10-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; GFX10-NEXT:    v_fmac_f32_e32 v10, v11, v10
; GFX10-NEXT:    v_mul_f32_e32 v11, v6, v10
; GFX10-NEXT:    v_fma_f32 v12, -v9, v11, v6
; GFX10-NEXT:    v_fmac_f32_e32 v11, v12, v10
; GFX10-NEXT:    v_fma_f32 v6, -v9, v11, v6
; GFX10-NEXT:    s_denorm_mode 12
; GFX10-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
; GFX10-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 12, v4
; GFX10-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
; GFX10-NEXT:    s_and_saveexec_b32 s5, vcc_lo
; GFX10-NEXT:    s_cbranch_execz .LBB3_7
; GFX10-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
; GFX10-NEXT:    v_sub_nc_u32_e32 v4, v7, v8
; GFX10-NEXT:    s_mov_b32 s6, 0
; GFX10-NEXT:    v_add_nc_u32_e32 v4, 12, v4
; GFX10-NEXT:  .LBB3_5: ; %frem.loop_body
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v7, v5
; GFX10-NEXT:    v_add_nc_u32_e32 v4, -12, v4
; GFX10-NEXT:    v_mul_f32_e32 v5, v7, v6
; GFX10-NEXT:    v_rndne_f32_e32 v5, v5
; GFX10-NEXT:    v_fma_f32 v5, -v5, v3, v7
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX10-NEXT:    v_add_f32_e32 v8, v5, v3
; GFX10-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc_lo
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v4
; GFX10-NEXT:    v_ldexp_f32 v5, v5, 12
; GFX10-NEXT:    s_or_b32 s6, vcc_lo, s6
; GFX10-NEXT:    s_andn2_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    s_cbranch_execnz .LBB3_5
; GFX10-NEXT:  ; %bb.6: ; %Flow
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    v_mov_b32_e32 v5, v7
; GFX10-NEXT:  .LBB3_7: ; %Flow12
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s5
; GFX10-NEXT:    v_add_nc_u32_e32 v4, -11, v4
; GFX10-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX10-NEXT:    v_mul_f32_e32 v5, v4, v6
; GFX10-NEXT:    v_rndne_f32_e32 v5, v5
; GFX10-NEXT:    v_fma_f32 v4, -v5, v3, v4
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX10-NEXT:    v_add_f32_e32 v3, v4, v3
; GFX10-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v2, v3, v2
; GFX10-NEXT:    v_bfi_b32 v2, 0x7fffffff, v2, v0
; GFX10-NEXT:  .LBB3_8: ; %Flow14
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v1
; GFX10-NEXT:    v_cmp_nge_f32_e64 s4, |v0|, 0x7f800000
; GFX10-NEXT:    s_and_b32 vcc_lo, s4, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: frem_f32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cmp_ngt_f32_e64 s0, |v0|, |v1|
; GFX11-NEXT:    ; implicit-def: $vgpr2
; GFX11-NEXT:    s_and_saveexec_b32 s1, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX11-NEXT:  ; %bb.1: ; %frem.else
; GFX11-NEXT:    v_and_b32_e32 v2, 0x80000000, v0
; GFX11-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v0|, |v1|
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc_lo
; GFX11-NEXT:  ; %bb.2: ; %Flow13
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB3_8
; GFX11-NEXT:  ; %bb.3: ; %frem.compute
; GFX11-NEXT:    v_frexp_mant_f32_e64 v3, |v1|
; GFX11-NEXT:    v_frexp_mant_f32_e64 v2, |v0|
; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v7, v0
; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v8, v1
; GFX11-NEXT:    s_mov_b32 s1, exec_lo
; GFX11-NEXT:    v_ldexp_f32 v3, v3, 1
; GFX11-NEXT:    v_ldexp_f32 v5, v2, 12
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_add_nc_u32_e32 v2, -1, v8
; GFX11-NEXT:    v_div_scale_f32 v9, null, v3, v3, 1.0
; GFX11-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v3, 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_xad_u32 v4, v2, -1, v7
; GFX11-NEXT:    v_rcp_f32_e32 v10, v9
; GFX11-NEXT:    s_denorm_mode 15
; GFX11-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fmac_f32_e32 v10, v11, v10
; GFX11-NEXT:    v_mul_f32_e32 v11, v6, v10
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v12, -v9, v11, v6
; GFX11-NEXT:    v_fmac_f32_e32 v11, v12, v10
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v6, -v9, v11, v6
; GFX11-NEXT:    s_denorm_mode 12
; GFX11-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
; GFX11-NEXT:    v_cmpx_lt_i32_e32 12, v4
; GFX11-NEXT:    s_cbranch_execz .LBB3_7
; GFX11-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
; GFX11-NEXT:    v_sub_nc_u32_e32 v4, v7, v8
; GFX11-NEXT:    s_mov_b32 s2, 0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_add_nc_u32_e32 v4, 12, v4
; GFX11-NEXT:  .LBB3_5: ; %frem.loop_body
; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_dual_mov_b32 v7, v5 :: v_dual_add_nc_u32 v4, -12, v4
; GFX11-NEXT:    v_mul_f32_e32 v5, v7, v6
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_rndne_f32_e32 v5, v5
; GFX11-NEXT:    v_fma_f32 v5, -v5, v3, v7
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX11-NEXT:    v_add_f32_e32 v8, v5, v3
; GFX11-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc_lo
; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v4
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT:    v_ldexp_f32 v5, v5, 12
; GFX11-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX11-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX11-NEXT:    s_cbranch_execnz .LBB3_5
; GFX11-NEXT:  ; %bb.6: ; %Flow
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX11-NEXT:    v_mov_b32_e32 v5, v7
; GFX11-NEXT:  .LBB3_7: ; %Flow12
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX11-NEXT:    v_add_nc_u32_e32 v4, -11, v4
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX11-NEXT:    v_mul_f32_e32 v5, v4, v6
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_rndne_f32_e32 v5, v5
; GFX11-NEXT:    v_fma_f32 v4, -v5, v3, v4
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX11-NEXT:    v_add_f32_e32 v3, v4, v3
; GFX11-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_ldexp_f32 v2, v3, v2
; GFX11-NEXT:    v_bfi_b32 v2, 0x7fffffff, v2, v0
; GFX11-NEXT:  .LBB3_8: ; %Flow14
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v1
; GFX11-NEXT:    v_cmp_nge_f32_e64 s0, |v0|, 0x7f800000
; GFX11-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-LABEL: frem_f32:
; GFX1150:       ; %bb.0:
; GFX1150-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-NEXT:    v_cmp_ngt_f32_e64 s0, |v0|, |v1|
; GFX1150-NEXT:    ; implicit-def: $vgpr2
; GFX1150-NEXT:    s_and_saveexec_b32 s1, s0
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX1150-NEXT:  ; %bb.1: ; %frem.else
; GFX1150-NEXT:    v_and_b32_e32 v2, 0x80000000, v0
; GFX1150-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v0|, |v1|
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1150-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc_lo
; GFX1150-NEXT:  ; %bb.2: ; %Flow13
; GFX1150-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1150-NEXT:    s_cbranch_execz .LBB3_8
; GFX1150-NEXT:  ; %bb.3: ; %frem.compute
; GFX1150-NEXT:    v_frexp_mant_f32_e64 v3, |v1|
; GFX1150-NEXT:    v_frexp_mant_f32_e64 v2, |v0|
; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v7, v0
; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v8, v1
; GFX1150-NEXT:    s_mov_b32 s1, exec_lo
; GFX1150-NEXT:    v_ldexp_f32 v3, v3, 1
; GFX1150-NEXT:    v_ldexp_f32 v5, v2, 12
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_add_nc_u32_e32 v2, -1, v8
; GFX1150-NEXT:    v_div_scale_f32 v9, null, v3, v3, 1.0
; GFX1150-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v3, 1.0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_xad_u32 v4, v2, -1, v7
; GFX1150-NEXT:    v_rcp_f32_e32 v10, v9
; GFX1150-NEXT:    s_denorm_mode 15
; GFX1150-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; GFX1150-NEXT:    v_fmac_f32_e32 v10, v11, v10
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f32_e32 v11, v6, v10
; GFX1150-NEXT:    v_fma_f32 v12, -v9, v11, v6
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fmac_f32_e32 v11, v12, v10
; GFX1150-NEXT:    v_fma_f32 v6, -v9, v11, v6
; GFX1150-NEXT:    s_denorm_mode 12
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
; GFX1150-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
; GFX1150-NEXT:    v_cmpx_lt_i32_e32 12, v4
; GFX1150-NEXT:    s_cbranch_execz .LBB3_7
; GFX1150-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
; GFX1150-NEXT:    v_sub_nc_u32_e32 v4, v7, v8
; GFX1150-NEXT:    s_mov_b32 s2, 0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_add_nc_u32_e32 v4, 12, v4
; GFX1150-NEXT:  .LBB3_5: ; %frem.loop_body
; GFX1150-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_dual_mov_b32 v7, v5 :: v_dual_add_nc_u32 v4, -12, v4
; GFX1150-NEXT:    v_mul_f32_e32 v5, v7, v6
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_rndne_f32_e32 v5, v5
; GFX1150-NEXT:    v_fma_f32 v5, -v5, v3, v7
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX1150-NEXT:    v_add_f32_e32 v8, v5, v3
; GFX1150-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc_lo
; GFX1150-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v4
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT:    v_ldexp_f32 v5, v5, 12
; GFX1150-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1150-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1150-NEXT:    s_cbranch_execnz .LBB3_5
; GFX1150-NEXT:  ; %bb.6: ; %Flow
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1150-NEXT:    v_mov_b32_e32 v5, v7
; GFX1150-NEXT:  .LBB3_7: ; %Flow12
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1150-NEXT:    v_add_nc_u32_e32 v4, -11, v4
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX1150-NEXT:    v_mul_f32_e32 v5, v4, v6
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_rndne_f32_e32 v5, v5
; GFX1150-NEXT:    v_fma_f32 v4, -v5, v3, v4
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX1150-NEXT:    v_add_f32_e32 v3, v4, v3
; GFX1150-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f32 v2, v3, v2
; GFX1150-NEXT:    v_bfi_b32 v2, 0x7fffffff, v2, v0
; GFX1150-NEXT:  .LBB3_8: ; %Flow14
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1150-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v1
; GFX1150-NEXT:    v_cmp_nge_f32_e64 s0, |v0|, 0x7f800000
; GFX1150-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1150-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo
; GFX1150-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: frem_f32:
; GFX1200:       ; %bb.0:
; GFX1200-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT:    s_wait_expcnt 0x0
; GFX1200-NEXT:    s_wait_samplecnt 0x0
; GFX1200-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-NEXT:    s_wait_kmcnt 0x0
; GFX1200-NEXT:    v_cmp_ngt_f32_e64 s0, |v0|, |v1|
; GFX1200-NEXT:    ; implicit-def: $vgpr2
; GFX1200-NEXT:    s_and_saveexec_b32 s1, s0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX1200-NEXT:  ; %bb.1: ; %frem.else
; GFX1200-NEXT:    v_and_b32_e32 v2, 0x80000000, v0
; GFX1200-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v0|, |v1|
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc_lo
; GFX1200-NEXT:  ; %bb.2: ; %Flow13
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1200-NEXT:    s_cbranch_execz .LBB3_8
; GFX1200-NEXT:  ; %bb.3: ; %frem.compute
; GFX1200-NEXT:    v_frexp_mant_f32_e64 v3, |v1|
; GFX1200-NEXT:    v_frexp_mant_f32_e64 v2, |v0|
; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v7, v0
; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v8, v1
; GFX1200-NEXT:    s_mov_b32 s1, exec_lo
; GFX1200-NEXT:    v_ldexp_f32 v3, v3, 1
; GFX1200-NEXT:    v_ldexp_f32 v5, v2, 12
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT:    v_div_scale_f32 v9, null, v3, v3, 1.0
; GFX1200-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v3, 1.0
; GFX1200-NEXT:    v_rcp_f32_e32 v10, v9
; GFX1200-NEXT:    s_denorm_mode 15
; GFX1200-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; GFX1200-NEXT:    v_fmac_f32_e32 v10, v11, v10
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_dual_mul_f32 v11, v6, v10 :: v_dual_add_nc_u32 v2, -1, v8
; GFX1200-NEXT:    v_xad_u32 v4, v2, -1, v7
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v12, -v9, v11, v6
; GFX1200-NEXT:    v_fmac_f32_e32 v11, v12, v10
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v6, -v9, v11, v6
; GFX1200-NEXT:    s_denorm_mode 12
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
; GFX1200-NEXT:    v_cmpx_lt_i32_e32 12, v4
; GFX1200-NEXT:    s_cbranch_execz .LBB3_7
; GFX1200-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
; GFX1200-NEXT:    v_sub_nc_u32_e32 v4, v7, v8
; GFX1200-NEXT:    s_mov_b32 s2, 0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_add_nc_u32_e32 v4, 12, v4
; GFX1200-NEXT:  .LBB3_5: ; %frem.loop_body
; GFX1200-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_dual_mov_b32 v7, v5 :: v_dual_add_nc_u32 v4, -12, v4
; GFX1200-NEXT:    v_mul_f32_e32 v5, v7, v6
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_rndne_f32_e32 v5, v5
; GFX1200-NEXT:    v_fma_f32 v5, -v5, v3, v7
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX1200-NEXT:    v_add_f32_e32 v8, v5, v3
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc_lo
; GFX1200-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v4
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-NEXT:    v_ldexp_f32 v5, v5, 12
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1200-NEXT:    s_cbranch_execnz .LBB3_5
; GFX1200-NEXT:  ; %bb.6: ; %Flow
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1200-NEXT:    v_mov_b32_e32 v5, v7
; GFX1200-NEXT:  .LBB3_7: ; %Flow12
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1200-NEXT:    v_add_nc_u32_e32 v4, -11, v4
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX1200-NEXT:    v_mul_f32_e32 v5, v4, v6
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_rndne_f32_e32 v5, v5
; GFX1200-NEXT:    v_fma_f32 v4, -v5, v3, v4
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX1200-NEXT:    v_add_f32_e32 v3, v4, v3
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_ldexp_f32 v2, v3, v2
; GFX1200-NEXT:    v_bfi_b32 v2, 0x7fffffff, v2, v0
; GFX1200-NEXT:  .LBB3_8: ; %Flow14
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1200-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v1
; GFX1200-NEXT:    v_cmp_nge_f32_e64 s0, |v0|, 0x7f800000
; GFX1200-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo
; GFX1200-NEXT:    s_setpc_b64 s[30:31]
   %r2 = frem float %in1, %in2
  ret float %r2
}

define float @fast_frem_f32(float %in1, float %in2) #0 {
; SI-LABEL: fast_frem_f32:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, v0
; SI-NEXT:    v_rcp_f32_e32 v4, v3
; SI-NEXT:    v_div_scale_f32 v2, vcc, v0, v1, v0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
; SI-NEXT:    v_fma_f32 v4, v5, v4, v4
; SI-NEXT:    v_mul_f32_e32 v5, v2, v4
; SI-NEXT:    v_fma_f32 v6, -v3, v5, v2
; SI-NEXT:    v_fma_f32 v5, v6, v4, v5
; SI-NEXT:    v_fma_f32 v2, -v3, v5, v2
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
; SI-NEXT:    v_div_fixup_f32 v2, v2, v1, v0
; SI-NEXT:    v_trunc_f32_e32 v2, v2
; SI-NEXT:    v_fma_f32 v0, -v2, v1, v0
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; CI-LABEL: fast_frem_f32:
; CI:       ; %bb.0:
; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, v0
; CI-NEXT:    v_div_scale_f32 v2, vcc, v0, v1, v0
; CI-NEXT:    v_rcp_f32_e32 v4, v3
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
; CI-NEXT:    v_fma_f32 v4, v5, v4, v4
; CI-NEXT:    v_mul_f32_e32 v5, v2, v4
; CI-NEXT:    v_fma_f32 v6, -v3, v5, v2
; CI-NEXT:    v_fma_f32 v5, v6, v4, v5
; CI-NEXT:    v_fma_f32 v2, -v3, v5, v2
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
; CI-NEXT:    v_div_fixup_f32 v2, v2, v1, v0
; CI-NEXT:    v_trunc_f32_e32 v2, v2
; CI-NEXT:    v_fma_f32 v0, -v2, v1, v0
; CI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: fast_frem_f32:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, v0
; VI-NEXT:    v_div_scale_f32 v2, vcc, v0, v1, v0
; VI-NEXT:    v_rcp_f32_e32 v4, v3
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
; VI-NEXT:    v_fma_f32 v4, v5, v4, v4
; VI-NEXT:    v_mul_f32_e32 v5, v2, v4
; VI-NEXT:    v_fma_f32 v6, -v3, v5, v2
; VI-NEXT:    v_fma_f32 v5, v6, v4, v5
; VI-NEXT:    v_fma_f32 v2, -v3, v5, v2
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; VI-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
; VI-NEXT:    v_div_fixup_f32 v2, v2, v1, v0
; VI-NEXT:    v_trunc_f32_e32 v2, v2
; VI-NEXT:    v_fma_f32 v0, -v2, v1, v0
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: fast_frem_f32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, v0
; GFX9-NEXT:    v_div_scale_f32 v2, vcc, v0, v1, v0
; GFX9-NEXT:    v_rcp_f32_e32 v4, v3
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
; GFX9-NEXT:    v_fma_f32 v4, v5, v4, v4
; GFX9-NEXT:    v_mul_f32_e32 v5, v2, v4
; GFX9-NEXT:    v_fma_f32 v6, -v3, v5, v2
; GFX9-NEXT:    v_fma_f32 v5, v6, v4, v5
; GFX9-NEXT:    v_fma_f32 v2, -v3, v5, v2
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX9-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
; GFX9-NEXT:    v_div_fixup_f32 v2, v2, v1, v0
; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
; GFX9-NEXT:    v_fma_f32 v0, -v2, v1, v0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: fast_frem_f32:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_div_scale_f32 v3, s4, v1, v1, v0
; GFX10-NEXT:    v_div_scale_f32 v2, vcc_lo, v0, v1, v0
; GFX10-NEXT:    v_rcp_f32_e32 v4, v3
; GFX10-NEXT:    s_denorm_mode 15
; GFX10-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
; GFX10-NEXT:    v_fmac_f32_e32 v4, v5, v4
; GFX10-NEXT:    v_mul_f32_e32 v5, v2, v4
; GFX10-NEXT:    v_fma_f32 v6, -v3, v5, v2
; GFX10-NEXT:    v_fmac_f32_e32 v5, v6, v4
; GFX10-NEXT:    v_fma_f32 v2, -v3, v5, v2
; GFX10-NEXT:    s_denorm_mode 12
; GFX10-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
; GFX10-NEXT:    v_div_fixup_f32 v2, v2, v1, v0
; GFX10-NEXT:    v_trunc_f32_e32 v2, v2
; GFX10-NEXT:    v_fma_f32 v0, -v2, v1, v0
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: fast_frem_f32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_div_scale_f32 v3, null, v1, v1, v0
; GFX11-NEXT:    v_div_scale_f32 v2, vcc_lo, v0, v1, v0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_rcp_f32_e32 v4, v3
; GFX11-NEXT:    s_denorm_mode 15
; GFX11-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
; GFX11-NEXT:    v_fmac_f32_e32 v4, v5, v4
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_mul_f32_e32 v5, v2, v4
; GFX11-NEXT:    v_fma_f32 v6, -v3, v5, v2
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fmac_f32_e32 v5, v6, v4
; GFX11-NEXT:    v_fma_f32 v2, -v3, v5, v2
; GFX11-NEXT:    s_denorm_mode 12
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
; GFX11-NEXT:    v_div_fixup_f32 v2, v2, v1, v0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_trunc_f32_e32 v2, v2
; GFX11-NEXT:    v_fma_f32 v0, -v2, v1, v0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-LABEL: fast_frem_f32:
; GFX1150:       ; %bb.0:
; GFX1150-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-NEXT:    v_div_scale_f32 v3, null, v1, v1, v0
; GFX1150-NEXT:    v_div_scale_f32 v2, vcc_lo, v0, v1, v0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
; GFX1150-NEXT:    v_rcp_f32_e32 v4, v3
; GFX1150-NEXT:    s_denorm_mode 15
; GFX1150-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fmac_f32_e32 v4, v5, v4
; GFX1150-NEXT:    v_mul_f32_e32 v5, v2, v4
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f32 v6, -v3, v5, v2
; GFX1150-NEXT:    v_fmac_f32_e32 v5, v6, v4
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f32 v2, -v3, v5, v2
; GFX1150-NEXT:    s_denorm_mode 12
; GFX1150-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_div_fixup_f32 v2, v2, v1, v0
; GFX1150-NEXT:    v_trunc_f32_e32 v2, v2
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f32 v0, -v2, v1, v0
; GFX1150-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: fast_frem_f32:
; GFX1200:       ; %bb.0:
; GFX1200-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT:    s_wait_expcnt 0x0
; GFX1200-NEXT:    s_wait_samplecnt 0x0
; GFX1200-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-NEXT:    s_wait_kmcnt 0x0
; GFX1200-NEXT:    v_div_scale_f32 v3, null, v1, v1, v0
; GFX1200-NEXT:    v_div_scale_f32 v2, vcc_lo, v0, v1, v0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
; GFX1200-NEXT:    v_rcp_f32_e32 v4, v3
; GFX1200-NEXT:    s_denorm_mode 15
; GFX1200-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fmac_f32_e32 v4, v5, v4
; GFX1200-NEXT:    v_mul_f32_e32 v5, v2, v4
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v6, -v3, v5, v2
; GFX1200-NEXT:    v_fmac_f32_e32 v5, v6, v4
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v2, -v3, v5, v2
; GFX1200-NEXT:    s_denorm_mode 12
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_div_fixup_f32 v2, v2, v1, v0
; GFX1200-NEXT:    v_trunc_f32_e32 v2, v2
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v0, -v2, v1, v0
; GFX1200-NEXT:    s_setpc_b64 s[30:31]
   %r2 = frem fast float %in1, %in2
  ret float %r2
}

define float @unsafe_frem_f32(float %in1, float %in2) #0 {
; SI-LABEL: unsafe_frem_f32:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, v0
; SI-NEXT:    v_rcp_f32_e32 v4, v3
; SI-NEXT:    v_div_scale_f32 v2, vcc, v0, v1, v0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
; SI-NEXT:    v_fma_f32 v4, v5, v4, v4
; SI-NEXT:    v_mul_f32_e32 v5, v2, v4
; SI-NEXT:    v_fma_f32 v6, -v3, v5, v2
; SI-NEXT:    v_fma_f32 v5, v6, v4, v5
; SI-NEXT:    v_fma_f32 v2, -v3, v5, v2
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
; SI-NEXT:    v_div_fixup_f32 v2, v2, v1, v0
; SI-NEXT:    v_trunc_f32_e32 v2, v2
; SI-NEXT:    v_fma_f32 v0, -v2, v1, v0
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; CI-LABEL: unsafe_frem_f32:
; CI:       ; %bb.0:
; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, v0
; CI-NEXT:    v_div_scale_f32 v2, vcc, v0, v1, v0
; CI-NEXT:    v_rcp_f32_e32 v4, v3
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
; CI-NEXT:    v_fma_f32 v4, v5, v4, v4
; CI-NEXT:    v_mul_f32_e32 v5, v2, v4
; CI-NEXT:    v_fma_f32 v6, -v3, v5, v2
; CI-NEXT:    v_fma_f32 v5, v6, v4, v5
; CI-NEXT:    v_fma_f32 v2, -v3, v5, v2
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
; CI-NEXT:    v_div_fixup_f32 v2, v2, v1, v0
; CI-NEXT:    v_trunc_f32_e32 v2, v2
; CI-NEXT:    v_fma_f32 v0, -v2, v1, v0
; CI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: unsafe_frem_f32:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, v0
; VI-NEXT:    v_div_scale_f32 v2, vcc, v0, v1, v0
; VI-NEXT:    v_rcp_f32_e32 v4, v3
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
; VI-NEXT:    v_fma_f32 v4, v5, v4, v4
; VI-NEXT:    v_mul_f32_e32 v5, v2, v4
; VI-NEXT:    v_fma_f32 v6, -v3, v5, v2
; VI-NEXT:    v_fma_f32 v5, v6, v4, v5
; VI-NEXT:    v_fma_f32 v2, -v3, v5, v2
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; VI-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
; VI-NEXT:    v_div_fixup_f32 v2, v2, v1, v0
; VI-NEXT:    v_trunc_f32_e32 v2, v2
; VI-NEXT:    v_fma_f32 v0, -v2, v1, v0
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: unsafe_frem_f32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, v0
; GFX9-NEXT:    v_div_scale_f32 v2, vcc, v0, v1, v0
; GFX9-NEXT:    v_rcp_f32_e32 v4, v3
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
; GFX9-NEXT:    v_fma_f32 v4, v5, v4, v4
; GFX9-NEXT:    v_mul_f32_e32 v5, v2, v4
; GFX9-NEXT:    v_fma_f32 v6, -v3, v5, v2
; GFX9-NEXT:    v_fma_f32 v5, v6, v4, v5
; GFX9-NEXT:    v_fma_f32 v2, -v3, v5, v2
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX9-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
; GFX9-NEXT:    v_div_fixup_f32 v2, v2, v1, v0
; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
; GFX9-NEXT:    v_fma_f32 v0, -v2, v1, v0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: unsafe_frem_f32:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_div_scale_f32 v3, s4, v1, v1, v0
; GFX10-NEXT:    v_div_scale_f32 v2, vcc_lo, v0, v1, v0
; GFX10-NEXT:    v_rcp_f32_e32 v4, v3
; GFX10-NEXT:    s_denorm_mode 15
; GFX10-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
; GFX10-NEXT:    v_fmac_f32_e32 v4, v5, v4
; GFX10-NEXT:    v_mul_f32_e32 v5, v2, v4
; GFX10-NEXT:    v_fma_f32 v6, -v3, v5, v2
; GFX10-NEXT:    v_fmac_f32_e32 v5, v6, v4
; GFX10-NEXT:    v_fma_f32 v2, -v3, v5, v2
; GFX10-NEXT:    s_denorm_mode 12
; GFX10-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
; GFX10-NEXT:    v_div_fixup_f32 v2, v2, v1, v0
; GFX10-NEXT:    v_trunc_f32_e32 v2, v2
; GFX10-NEXT:    v_fma_f32 v0, -v2, v1, v0
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: unsafe_frem_f32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_div_scale_f32 v3, null, v1, v1, v0
; GFX11-NEXT:    v_div_scale_f32 v2, vcc_lo, v0, v1, v0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_rcp_f32_e32 v4, v3
; GFX11-NEXT:    s_denorm_mode 15
; GFX11-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
; GFX11-NEXT:    v_fmac_f32_e32 v4, v5, v4
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_mul_f32_e32 v5, v2, v4
; GFX11-NEXT:    v_fma_f32 v6, -v3, v5, v2
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fmac_f32_e32 v5, v6, v4
; GFX11-NEXT:    v_fma_f32 v2, -v3, v5, v2
; GFX11-NEXT:    s_denorm_mode 12
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
; GFX11-NEXT:    v_div_fixup_f32 v2, v2, v1, v0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_trunc_f32_e32 v2, v2
; GFX11-NEXT:    v_fma_f32 v0, -v2, v1, v0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-LABEL: unsafe_frem_f32:
; GFX1150:       ; %bb.0:
; GFX1150-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-NEXT:    v_div_scale_f32 v3, null, v1, v1, v0
; GFX1150-NEXT:    v_div_scale_f32 v2, vcc_lo, v0, v1, v0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
; GFX1150-NEXT:    v_rcp_f32_e32 v4, v3
; GFX1150-NEXT:    s_denorm_mode 15
; GFX1150-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fmac_f32_e32 v4, v5, v4
; GFX1150-NEXT:    v_mul_f32_e32 v5, v2, v4
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f32 v6, -v3, v5, v2
; GFX1150-NEXT:    v_fmac_f32_e32 v5, v6, v4
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f32 v2, -v3, v5, v2
; GFX1150-NEXT:    s_denorm_mode 12
; GFX1150-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_div_fixup_f32 v2, v2, v1, v0
; GFX1150-NEXT:    v_trunc_f32_e32 v2, v2
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f32 v0, -v2, v1, v0
; GFX1150-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: unsafe_frem_f32:
; GFX1200:       ; %bb.0:
; GFX1200-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT:    s_wait_expcnt 0x0
; GFX1200-NEXT:    s_wait_samplecnt 0x0
; GFX1200-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-NEXT:    s_wait_kmcnt 0x0
; GFX1200-NEXT:    v_div_scale_f32 v3, null, v1, v1, v0
; GFX1200-NEXT:    v_div_scale_f32 v2, vcc_lo, v0, v1, v0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
; GFX1200-NEXT:    v_rcp_f32_e32 v4, v3
; GFX1200-NEXT:    s_denorm_mode 15
; GFX1200-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fmac_f32_e32 v4, v5, v4
; GFX1200-NEXT:    v_mul_f32_e32 v5, v2, v4
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v6, -v3, v5, v2
; GFX1200-NEXT:    v_fmac_f32_e32 v5, v6, v4
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v2, -v3, v5, v2
; GFX1200-NEXT:    s_denorm_mode 12
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_div_fixup_f32 v2, v2, v1, v0
; GFX1200-NEXT:    v_trunc_f32_e32 v2, v2
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v0, -v2, v1, v0
; GFX1200-NEXT:    s_setpc_b64 s[30:31]
   %r2 = frem afn float %in1, %in2
  ret float %r2
}

define double @frem_f64(double %in1, double %in2) #0 {
; SI-LABEL: frem_f64:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cmp_ngt_f64_e64 s[4:5], |v[0:1]|, |v[2:3]|
; SI-NEXT:    ; implicit-def: $vgpr4_vgpr5
; SI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; SI-NEXT:  ; %bb.1: ; %frem.else
; SI-NEXT:    v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[2:3]|
; SI-NEXT:    v_and_b32_e32 v4, 0x80000000, v1
; SI-NEXT:    v_cndmask_b32_e32 v5, v1, v4, vcc
; SI-NEXT:    v_cndmask_b32_e64 v4, v0, 0, vcc
; SI-NEXT:  ; %bb.2: ; %Flow13
; SI-NEXT:    s_andn2_saveexec_b64 s[6:7], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB6_8
; SI-NEXT:  ; %bb.3: ; %frem.compute
; SI-NEXT:    v_and_b32_e32 v6, 0x7fffffff, v1
; SI-NEXT:    s_mov_b32 s4, 0x7ff00000
; SI-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, s4, v6
; SI-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc
; SI-NEXT:    v_frexp_exp_i32_f64_e32 v6, v[0:1]
; SI-NEXT:    v_cndmask_b32_e32 v4, v0, v4, vcc
; SI-NEXT:    v_cndmask_b32_e32 v10, 0, v6, vcc
; SI-NEXT:    v_ldexp_f64 v[8:9], v[4:5], 26
; SI-NEXT:    v_and_b32_e32 v6, 0x7fffffff, v3
; SI-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[2:3]|
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, s4, v6
; SI-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc
; SI-NEXT:    v_frexp_exp_i32_f64_e32 v6, v[2:3]
; SI-NEXT:    v_cndmask_b32_e32 v4, v2, v4, vcc
; SI-NEXT:    v_cndmask_b32_e32 v11, 0, v6, vcc
; SI-NEXT:    v_add_i32_e32 v14, vcc, -1, v11
; SI-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 1
; SI-NEXT:    v_not_b32_e32 v6, v14
; SI-NEXT:    v_add_i32_e32 v15, vcc, v6, v10
; SI-NEXT:    v_div_scale_f64 v[6:7], s[4:5], v[4:5], v[4:5], 1.0
; SI-NEXT:    s_brev_b32 s12, -2
; SI-NEXT:    s_mov_b32 s8, -1
; SI-NEXT:    v_rcp_f64_e32 v[12:13], v[6:7]
; SI-NEXT:    v_cmp_eq_u32_e32 vcc, v5, v7
; SI-NEXT:    v_fma_f64 v[16:17], -v[6:7], v[12:13], 1.0
; SI-NEXT:    v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
; SI-NEXT:    v_fma_f64 v[16:17], -v[6:7], v[12:13], 1.0
; SI-NEXT:    v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
; SI-NEXT:    v_div_scale_f64 v[16:17], s[4:5], 1.0, v[4:5], 1.0
; SI-NEXT:    s_mov_b32 s4, 0x3ff00000
; SI-NEXT:    v_mul_f64 v[18:19], v[16:17], v[12:13]
; SI-NEXT:    v_cmp_eq_u32_e64 s[4:5], s4, v17
; SI-NEXT:    v_fma_f64 v[20:21], -v[6:7], v[18:19], v[16:17]
; SI-NEXT:    s_xor_b64 vcc, s[4:5], vcc
; SI-NEXT:    v_div_fmas_f64 v[6:7], v[20:21], v[12:13], v[18:19]
; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v15
; SI-NEXT:    v_div_fixup_f64 v[6:7], v[6:7], v[4:5], 1.0
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_cbranch_execz .LBB6_7
; SI-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
; SI-NEXT:    v_sub_i32_e32 v10, vcc, v10, v11
; SI-NEXT:    v_add_i32_e32 v15, vcc, 26, v10
; SI-NEXT:    s_mov_b64 s[10:11], 0
; SI-NEXT:    s_mov_b32 s9, 0x432fffff
; SI-NEXT:    v_mov_b32_e32 v10, 0
; SI-NEXT:    v_mov_b32_e32 v16, 0x43300000
; SI-NEXT:  .LBB6_5: ; %frem.loop_body
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v13, v9
; SI-NEXT:    v_mov_b32_e32 v12, v8
; SI-NEXT:    v_mul_f64 v[8:9], v[12:13], v[6:7]
; SI-NEXT:    v_bfi_b32 v11, s12, v16, v9
; SI-NEXT:    v_add_f64 v[17:18], v[8:9], v[10:11]
; SI-NEXT:    v_cmp_gt_f64_e64 vcc, |v[8:9]|, s[8:9]
; SI-NEXT:    v_add_f64 v[17:18], v[17:18], -v[10:11]
; SI-NEXT:    v_cndmask_b32_e32 v9, v18, v9, vcc
; SI-NEXT:    v_cndmask_b32_e32 v8, v17, v8, vcc
; SI-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[4:5], v[12:13]
; SI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[8:9]
; SI-NEXT:    v_add_f64 v[17:18], v[8:9], v[4:5]
; SI-NEXT:    v_cndmask_b32_e32 v9, v9, v18, vcc
; SI-NEXT:    v_cndmask_b32_e32 v8, v8, v17, vcc
; SI-NEXT:    v_subrev_i32_e32 v15, vcc, 26, v15
; SI-NEXT:    v_ldexp_f64 v[8:9], v[8:9], 26
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v15
; SI-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
; SI-NEXT:    s_andn2_b64 exec, exec, s[10:11]
; SI-NEXT:    s_cbranch_execnz .LBB6_5
; SI-NEXT:  ; %bb.6: ; %Flow
; SI-NEXT:    s_or_b64 exec, exec, s[10:11]
; SI-NEXT:    v_mov_b32_e32 v8, v12
; SI-NEXT:    v_mov_b32_e32 v9, v13
; SI-NEXT:  .LBB6_7: ; %Flow12
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    v_subrev_i32_e32 v10, vcc, 25, v15
; SI-NEXT:    v_ldexp_f64 v[8:9], v[8:9], v10
; SI-NEXT:    s_mov_b32 s4, -1
; SI-NEXT:    v_mul_f64 v[6:7], v[8:9], v[6:7]
; SI-NEXT:    s_mov_b32 s5, 0x432fffff
; SI-NEXT:    v_cmp_gt_f64_e64 vcc, |v[6:7]|, s[4:5]
; SI-NEXT:    s_brev_b32 s4, -2
; SI-NEXT:    v_mov_b32_e32 v10, 0x43300000
; SI-NEXT:    v_bfi_b32 v11, s4, v10, v7
; SI-NEXT:    v_mov_b32_e32 v10, 0
; SI-NEXT:    v_add_f64 v[12:13], v[6:7], v[10:11]
; SI-NEXT:    v_add_f64 v[10:11], v[12:13], -v[10:11]
; SI-NEXT:    v_cndmask_b32_e32 v7, v11, v7, vcc
; SI-NEXT:    v_cndmask_b32_e32 v6, v10, v6, vcc
; SI-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[4:5], v[8:9]
; SI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[6:7]
; SI-NEXT:    v_add_f64 v[4:5], v[6:7], v[4:5]
; SI-NEXT:    v_cndmask_b32_e32 v5, v7, v5, vcc
; SI-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc
; SI-NEXT:    v_ldexp_f64 v[4:5], v[4:5], v14
; SI-NEXT:    v_bfi_b32 v5, s4, v5, v1
; SI-NEXT:  .LBB6_8: ; %Flow14
; SI-NEXT:    s_or_b64 exec, exec, s[6:7]
; SI-NEXT:    s_mov_b32 s4, 0
; SI-NEXT:    s_mov_b32 s5, 0x7ff00000
; SI-NEXT:    v_cmp_lg_f64_e32 vcc, 0, v[2:3]
; SI-NEXT:    v_cmp_nge_f64_e64 s[4:5], |v[0:1]|, s[4:5]
; SI-NEXT:    v_mov_b32_e32 v1, 0x7ff80000
; SI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; SI-NEXT:    v_cndmask_b32_e32 v0, 0, v4, vcc
; SI-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; CI-LABEL: frem_f64:
; CI:       ; %bb.0:
; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-NEXT:    v_cmp_ngt_f64_e64 s[4:5], |v[0:1]|, |v[2:3]|
; CI-NEXT:    ; implicit-def: $vgpr4_vgpr5
; CI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; CI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; CI-NEXT:    s_cbranch_execz .LBB6_2
; CI-NEXT:  ; %bb.1: ; %frem.else
; CI-NEXT:    v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[2:3]|
; CI-NEXT:    v_and_b32_e32 v4, 0x80000000, v1
; CI-NEXT:    v_cndmask_b32_e32 v5, v1, v4, vcc
; CI-NEXT:    v_cndmask_b32_e64 v4, v0, 0, vcc
; CI-NEXT:  .LBB6_2: ; %Flow13
; CI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; CI-NEXT:    s_cbranch_execz .LBB6_8
; CI-NEXT:  ; %bb.3: ; %frem.compute
; CI-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; CI-NEXT:    v_frexp_exp_i32_f64_e32 v11, v[2:3]
; CI-NEXT:    v_frexp_exp_i32_f64_e32 v10, v[0:1]
; CI-NEXT:    v_ldexp_f64 v[8:9], v[4:5], 26
; CI-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[2:3]|
; CI-NEXT:    v_add_i32_e32 v12, vcc, -1, v11
; CI-NEXT:    v_not_b32_e32 v6, v12
; CI-NEXT:    v_add_i32_e32 v13, vcc, v6, v10
; CI-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 1
; CI-NEXT:    v_div_scale_f64 v[6:7], s[6:7], v[4:5], v[4:5], 1.0
; CI-NEXT:    v_rcp_f64_e32 v[14:15], v[6:7]
; CI-NEXT:    v_fma_f64 v[16:17], -v[6:7], v[14:15], 1.0
; CI-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
; CI-NEXT:    v_fma_f64 v[16:17], -v[6:7], v[14:15], 1.0
; CI-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
; CI-NEXT:    v_div_scale_f64 v[16:17], vcc, 1.0, v[4:5], 1.0
; CI-NEXT:    v_mul_f64 v[18:19], v[16:17], v[14:15]
; CI-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[18:19], v[16:17]
; CI-NEXT:    s_nop 1
; CI-NEXT:    v_div_fmas_f64 v[6:7], v[6:7], v[14:15], v[18:19]
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v13
; CI-NEXT:    v_div_fixup_f64 v[6:7], v[6:7], v[4:5], 1.0
; CI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; CI-NEXT:    s_cbranch_execz .LBB6_7
; CI-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
; CI-NEXT:    v_sub_i32_e32 v10, vcc, v10, v11
; CI-NEXT:    v_add_i32_e32 v13, vcc, 26, v10
; CI-NEXT:    s_mov_b64 s[8:9], 0
; CI-NEXT:  .LBB6_5: ; %frem.loop_body
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v11, v9
; CI-NEXT:    v_mov_b32_e32 v10, v8
; CI-NEXT:    v_mul_f64 v[8:9], v[10:11], v[6:7]
; CI-NEXT:    v_rndne_f64_e32 v[8:9], v[8:9]
; CI-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[4:5], v[10:11]
; CI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[8:9]
; CI-NEXT:    v_add_f64 v[14:15], v[8:9], v[4:5]
; CI-NEXT:    v_cndmask_b32_e32 v9, v9, v15, vcc
; CI-NEXT:    v_cndmask_b32_e32 v8, v8, v14, vcc
; CI-NEXT:    v_ldexp_f64 v[8:9], v[8:9], 26
; CI-NEXT:    v_subrev_i32_e32 v13, vcc, 26, v13
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v13
; CI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; CI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; CI-NEXT:    s_cbranch_execnz .LBB6_5
; CI-NEXT:  ; %bb.6: ; %Flow
; CI-NEXT:    s_or_b64 exec, exec, s[8:9]
; CI-NEXT:    v_mov_b32_e32 v8, v10
; CI-NEXT:    v_mov_b32_e32 v9, v11
; CI-NEXT:  .LBB6_7: ; %Flow12
; CI-NEXT:    s_or_b64 exec, exec, s[6:7]
; CI-NEXT:    v_subrev_i32_e32 v10, vcc, 25, v13
; CI-NEXT:    v_ldexp_f64 v[8:9], v[8:9], v10
; CI-NEXT:    s_brev_b32 s6, -2
; CI-NEXT:    v_mul_f64 v[6:7], v[8:9], v[6:7]
; CI-NEXT:    v_rndne_f64_e32 v[6:7], v[6:7]
; CI-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[4:5], v[8:9]
; CI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[6:7]
; CI-NEXT:    v_add_f64 v[4:5], v[6:7], v[4:5]
; CI-NEXT:    v_cndmask_b32_e32 v5, v7, v5, vcc
; CI-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc
; CI-NEXT:    v_ldexp_f64 v[4:5], v[4:5], v12
; CI-NEXT:    v_bfi_b32 v5, s6, v5, v1
; CI-NEXT:  .LBB6_8: ; %Flow14
; CI-NEXT:    s_or_b64 exec, exec, s[4:5]
; CI-NEXT:    s_mov_b32 s4, 0
; CI-NEXT:    s_mov_b32 s5, 0x7ff00000
; CI-NEXT:    v_cmp_lg_f64_e32 vcc, 0, v[2:3]
; CI-NEXT:    v_cmp_nge_f64_e64 s[4:5], |v[0:1]|, s[4:5]
; CI-NEXT:    v_mov_b32_e32 v1, 0x7ff80000
; CI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; CI-NEXT:    v_cndmask_b32_e32 v0, 0, v4, vcc
; CI-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
; CI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: frem_f64:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ngt_f64_e64 s[4:5], |v[0:1]|, |v[2:3]|
; VI-NEXT:    ; implicit-def: $vgpr4_vgpr5
; VI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; VI-NEXT:    s_cbranch_execz .LBB6_2
; VI-NEXT:  ; %bb.1: ; %frem.else
; VI-NEXT:    v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[2:3]|
; VI-NEXT:    v_and_b32_e32 v4, 0x80000000, v1
; VI-NEXT:    v_cndmask_b32_e32 v5, v1, v4, vcc
; VI-NEXT:    v_cndmask_b32_e64 v4, v0, 0, vcc
; VI-NEXT:  .LBB6_2: ; %Flow13
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB6_8
; VI-NEXT:  ; %bb.3: ; %frem.compute
; VI-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; VI-NEXT:    v_frexp_exp_i32_f64_e32 v11, v[2:3]
; VI-NEXT:    v_frexp_exp_i32_f64_e32 v10, v[0:1]
; VI-NEXT:    v_ldexp_f64 v[8:9], v[4:5], 26
; VI-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[2:3]|
; VI-NEXT:    v_add_u32_e32 v12, vcc, -1, v11
; VI-NEXT:    v_not_b32_e32 v6, v12
; VI-NEXT:    v_add_u32_e32 v13, vcc, v6, v10
; VI-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 1
; VI-NEXT:    v_div_scale_f64 v[6:7], s[6:7], v[4:5], v[4:5], 1.0
; VI-NEXT:    v_rcp_f64_e32 v[14:15], v[6:7]
; VI-NEXT:    v_fma_f64 v[16:17], -v[6:7], v[14:15], 1.0
; VI-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
; VI-NEXT:    v_fma_f64 v[16:17], -v[6:7], v[14:15], 1.0
; VI-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
; VI-NEXT:    v_div_scale_f64 v[16:17], vcc, 1.0, v[4:5], 1.0
; VI-NEXT:    v_mul_f64 v[18:19], v[16:17], v[14:15]
; VI-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[18:19], v[16:17]
; VI-NEXT:    s_nop 1
; VI-NEXT:    v_div_fmas_f64 v[6:7], v[6:7], v[14:15], v[18:19]
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v13
; VI-NEXT:    v_div_fixup_f64 v[6:7], v[6:7], v[4:5], 1.0
; VI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; VI-NEXT:    s_cbranch_execz .LBB6_7
; VI-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
; VI-NEXT:    v_sub_u32_e32 v10, vcc, v10, v11
; VI-NEXT:    v_add_u32_e32 v13, vcc, 26, v10
; VI-NEXT:    s_mov_b64 s[8:9], 0
; VI-NEXT:  .LBB6_5: ; %frem.loop_body
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v11, v9
; VI-NEXT:    v_mov_b32_e32 v10, v8
; VI-NEXT:    v_mul_f64 v[8:9], v[10:11], v[6:7]
; VI-NEXT:    v_rndne_f64_e32 v[8:9], v[8:9]
; VI-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[4:5], v[10:11]
; VI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[8:9]
; VI-NEXT:    v_add_f64 v[14:15], v[8:9], v[4:5]
; VI-NEXT:    v_cndmask_b32_e32 v9, v9, v15, vcc
; VI-NEXT:    v_cndmask_b32_e32 v8, v8, v14, vcc
; VI-NEXT:    v_ldexp_f64 v[8:9], v[8:9], 26
; VI-NEXT:    v_subrev_u32_e32 v13, vcc, 26, v13
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v13
; VI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; VI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; VI-NEXT:    s_cbranch_execnz .LBB6_5
; VI-NEXT:  ; %bb.6: ; %Flow
; VI-NEXT:    s_or_b64 exec, exec, s[8:9]
; VI-NEXT:    v_mov_b32_e32 v8, v10
; VI-NEXT:    v_mov_b32_e32 v9, v11
; VI-NEXT:  .LBB6_7: ; %Flow12
; VI-NEXT:    s_or_b64 exec, exec, s[6:7]
; VI-NEXT:    v_subrev_u32_e32 v10, vcc, 25, v13
; VI-NEXT:    v_ldexp_f64 v[8:9], v[8:9], v10
; VI-NEXT:    s_brev_b32 s6, -2
; VI-NEXT:    v_mul_f64 v[6:7], v[8:9], v[6:7]
; VI-NEXT:    v_rndne_f64_e32 v[6:7], v[6:7]
; VI-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[4:5], v[8:9]
; VI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[6:7]
; VI-NEXT:    v_add_f64 v[4:5], v[6:7], v[4:5]
; VI-NEXT:    v_cndmask_b32_e32 v5, v7, v5, vcc
; VI-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc
; VI-NEXT:    v_ldexp_f64 v[4:5], v[4:5], v12
; VI-NEXT:    v_bfi_b32 v5, s6, v5, v1
; VI-NEXT:  .LBB6_8: ; %Flow14
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_mov_b32 s4, 0
; VI-NEXT:    s_mov_b32 s5, 0x7ff00000
; VI-NEXT:    v_cmp_lg_f64_e32 vcc, 0, v[2:3]
; VI-NEXT:    v_cmp_nge_f64_e64 s[4:5], |v[0:1]|, s[4:5]
; VI-NEXT:    v_mov_b32_e32 v1, 0x7ff80000
; VI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; VI-NEXT:    v_cndmask_b32_e32 v0, 0, v4, vcc
; VI-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: frem_f64:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ngt_f64_e64 s[4:5], |v[0:1]|, |v[2:3]|
; GFX9-NEXT:    ; implicit-def: $vgpr4_vgpr5
; GFX9-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; GFX9-NEXT:    s_cbranch_execz .LBB6_2
; GFX9-NEXT:  ; %bb.1: ; %frem.else
; GFX9-NEXT:    v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[2:3]|
; GFX9-NEXT:    v_and_b32_e32 v4, 0x80000000, v1
; GFX9-NEXT:    v_cndmask_b32_e32 v5, v1, v4, vcc
; GFX9-NEXT:    v_cndmask_b32_e64 v4, v0, 0, vcc
; GFX9-NEXT:  .LBB6_2: ; %Flow13
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB6_8
; GFX9-NEXT:  ; %bb.3: ; %frem.compute
; GFX9-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; GFX9-NEXT:    v_frexp_exp_i32_f64_e32 v11, v[2:3]
; GFX9-NEXT:    v_frexp_exp_i32_f64_e32 v10, v[0:1]
; GFX9-NEXT:    v_ldexp_f64 v[8:9], v[4:5], 26
; GFX9-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[2:3]|
; GFX9-NEXT:    v_add_u32_e32 v12, -1, v11
; GFX9-NEXT:    v_xad_u32 v13, v12, -1, v10
; GFX9-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 1
; GFX9-NEXT:    v_div_scale_f64 v[6:7], s[6:7], v[4:5], v[4:5], 1.0
; GFX9-NEXT:    v_rcp_f64_e32 v[14:15], v[6:7]
; GFX9-NEXT:    v_fma_f64 v[16:17], -v[6:7], v[14:15], 1.0
; GFX9-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
; GFX9-NEXT:    v_fma_f64 v[16:17], -v[6:7], v[14:15], 1.0
; GFX9-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
; GFX9-NEXT:    v_div_scale_f64 v[16:17], vcc, 1.0, v[4:5], 1.0
; GFX9-NEXT:    v_mul_f64 v[18:19], v[16:17], v[14:15]
; GFX9-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[18:19], v[16:17]
; GFX9-NEXT:    s_nop 1
; GFX9-NEXT:    v_div_fmas_f64 v[6:7], v[6:7], v[14:15], v[18:19]
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v13
; GFX9-NEXT:    v_div_fixup_f64 v[6:7], v[6:7], v[4:5], 1.0
; GFX9-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; GFX9-NEXT:    s_cbranch_execz .LBB6_7
; GFX9-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
; GFX9-NEXT:    v_sub_u32_e32 v10, v10, v11
; GFX9-NEXT:    v_add_u32_e32 v13, 26, v10
; GFX9-NEXT:    s_mov_b64 s[8:9], 0
; GFX9-NEXT:  .LBB6_5: ; %frem.loop_body
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v11, v9
; GFX9-NEXT:    v_mov_b32_e32 v10, v8
; GFX9-NEXT:    v_mul_f64 v[8:9], v[10:11], v[6:7]
; GFX9-NEXT:    v_subrev_u32_e32 v13, 26, v13
; GFX9-NEXT:    v_rndne_f64_e32 v[8:9], v[8:9]
; GFX9-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[4:5], v[10:11]
; GFX9-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[8:9]
; GFX9-NEXT:    v_add_f64 v[14:15], v[8:9], v[4:5]
; GFX9-NEXT:    v_cndmask_b32_e32 v9, v9, v15, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v8, v8, v14, vcc
; GFX9-NEXT:    v_ldexp_f64 v[8:9], v[8:9], 26
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v13
; GFX9-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; GFX9-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; GFX9-NEXT:    s_cbranch_execnz .LBB6_5
; GFX9-NEXT:  ; %bb.6: ; %Flow
; GFX9-NEXT:    s_or_b64 exec, exec, s[8:9]
; GFX9-NEXT:    v_mov_b32_e32 v8, v10
; GFX9-NEXT:    v_mov_b32_e32 v9, v11
; GFX9-NEXT:  .LBB6_7: ; %Flow12
; GFX9-NEXT:    s_or_b64 exec, exec, s[6:7]
; GFX9-NEXT:    v_subrev_u32_e32 v10, 25, v13
; GFX9-NEXT:    v_ldexp_f64 v[8:9], v[8:9], v10
; GFX9-NEXT:    s_brev_b32 s6, -2
; GFX9-NEXT:    v_mul_f64 v[6:7], v[8:9], v[6:7]
; GFX9-NEXT:    v_rndne_f64_e32 v[6:7], v[6:7]
; GFX9-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[4:5], v[8:9]
; GFX9-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[6:7]
; GFX9-NEXT:    v_add_f64 v[4:5], v[6:7], v[4:5]
; GFX9-NEXT:    v_cndmask_b32_e32 v5, v7, v5, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc
; GFX9-NEXT:    v_ldexp_f64 v[4:5], v[4:5], v12
; GFX9-NEXT:    v_bfi_b32 v5, s6, v5, v1
; GFX9-NEXT:  .LBB6_8: ; %Flow14
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_mov_b32 s4, 0
; GFX9-NEXT:    s_mov_b32 s5, 0x7ff00000
; GFX9-NEXT:    v_cmp_lg_f64_e32 vcc, 0, v[2:3]
; GFX9-NEXT:    v_cmp_nge_f64_e64 s[4:5], |v[0:1]|, s[4:5]
; GFX9-NEXT:    v_mov_b32_e32 v1, 0x7ff80000
; GFX9-NEXT:    s_and_b64 vcc, s[4:5], vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v0, 0, v4, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: frem_f64:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cmp_ngt_f64_e64 s4, |v[0:1]|, |v[2:3]|
; GFX10-NEXT:    ; implicit-def: $vgpr4_vgpr5
; GFX10-NEXT:    s_and_saveexec_b32 s5, s4
; GFX10-NEXT:    s_xor_b32 s4, exec_lo, s5
; GFX10-NEXT:    s_cbranch_execz .LBB6_2
; GFX10-NEXT:  ; %bb.1: ; %frem.else
; GFX10-NEXT:    v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[2:3]|
; GFX10-NEXT:    v_and_b32_e32 v4, 0x80000000, v1
; GFX10-NEXT:    v_cndmask_b32_e32 v5, v1, v4, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e64 v4, v0, 0, vcc_lo
; GFX10-NEXT:  .LBB6_2: ; %Flow13
; GFX10-NEXT:    s_andn2_saveexec_b32 s4, s4
; GFX10-NEXT:    s_cbranch_execz .LBB6_8
; GFX10-NEXT:  ; %bb.3: ; %frem.compute
; GFX10-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; GFX10-NEXT:    v_frexp_exp_i32_f64_e32 v11, v[2:3]
; GFX10-NEXT:    v_frexp_exp_i32_f64_e32 v10, v[0:1]
; GFX10-NEXT:    v_ldexp_f64 v[8:9], v[4:5], 26
; GFX10-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[2:3]|
; GFX10-NEXT:    v_add_nc_u32_e32 v12, -1, v11
; GFX10-NEXT:    v_xad_u32 v13, v12, -1, v10
; GFX10-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 1
; GFX10-NEXT:    v_div_scale_f64 v[6:7], s5, v[4:5], v[4:5], 1.0
; GFX10-NEXT:    v_rcp_f64_e32 v[14:15], v[6:7]
; GFX10-NEXT:    v_fma_f64 v[16:17], -v[6:7], v[14:15], 1.0
; GFX10-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
; GFX10-NEXT:    v_fma_f64 v[16:17], -v[6:7], v[14:15], 1.0
; GFX10-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
; GFX10-NEXT:    v_div_scale_f64 v[16:17], vcc_lo, 1.0, v[4:5], 1.0
; GFX10-NEXT:    v_mul_f64 v[18:19], v[16:17], v[14:15]
; GFX10-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[18:19], v[16:17]
; GFX10-NEXT:    v_div_fmas_f64 v[6:7], v[6:7], v[14:15], v[18:19]
; GFX10-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 26, v13
; GFX10-NEXT:    v_div_fixup_f64 v[6:7], v[6:7], v[4:5], 1.0
; GFX10-NEXT:    s_and_saveexec_b32 s5, vcc_lo
; GFX10-NEXT:    s_cbranch_execz .LBB6_7
; GFX10-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
; GFX10-NEXT:    v_sub_nc_u32_e32 v10, v10, v11
; GFX10-NEXT:    s_mov_b32 s6, 0
; GFX10-NEXT:    v_add_nc_u32_e32 v13, 26, v10
; GFX10-NEXT:  .LBB6_5: ; %frem.loop_body
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v11, v9
; GFX10-NEXT:    v_mov_b32_e32 v10, v8
; GFX10-NEXT:    v_subrev_nc_u32_e32 v13, 26, v13
; GFX10-NEXT:    v_mul_f64 v[8:9], v[10:11], v[6:7]
; GFX10-NEXT:    v_rndne_f64_e32 v[8:9], v[8:9]
; GFX10-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[4:5], v[10:11]
; GFX10-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[8:9]
; GFX10-NEXT:    v_add_f64 v[14:15], v[8:9], v[4:5]
; GFX10-NEXT:    v_cndmask_b32_e32 v9, v9, v15, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v8, v8, v14, vcc_lo
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v13
; GFX10-NEXT:    v_ldexp_f64 v[8:9], v[8:9], 26
; GFX10-NEXT:    s_or_b32 s6, vcc_lo, s6
; GFX10-NEXT:    s_andn2_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    s_cbranch_execnz .LBB6_5
; GFX10-NEXT:  ; %bb.6: ; %Flow
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    v_mov_b32_e32 v8, v10
; GFX10-NEXT:    v_mov_b32_e32 v9, v11
; GFX10-NEXT:  .LBB6_7: ; %Flow12
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s5
; GFX10-NEXT:    v_subrev_nc_u32_e32 v10, 25, v13
; GFX10-NEXT:    v_ldexp_f64 v[8:9], v[8:9], v10
; GFX10-NEXT:    v_mul_f64 v[6:7], v[8:9], v[6:7]
; GFX10-NEXT:    v_rndne_f64_e32 v[6:7], v[6:7]
; GFX10-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[4:5], v[8:9]
; GFX10-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX10-NEXT:    v_add_f64 v[4:5], v[6:7], v[4:5]
; GFX10-NEXT:    v_cndmask_b32_e32 v5, v7, v5, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc_lo
; GFX10-NEXT:    v_ldexp_f64 v[4:5], v[4:5], v12
; GFX10-NEXT:    v_bfi_b32 v5, 0x7fffffff, v5, v1
; GFX10-NEXT:  .LBB6_8: ; %Flow14
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT:    v_cmp_lg_f64_e32 vcc_lo, 0, v[2:3]
; GFX10-NEXT:    v_cmp_nge_f64_e64 s4, |v[0:1]|, 0x7ff00000
; GFX10-NEXT:    s_and_b32 vcc_lo, s4, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0, v4, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v1, 0x7ff80000, v5, vcc_lo
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: frem_f64:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cmp_ngt_f64_e64 s0, |v[0:1]|, |v[2:3]|
; GFX11-NEXT:    ; implicit-def: $vgpr4_vgpr5
; GFX11-NEXT:    s_and_saveexec_b32 s1, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX11-NEXT:    s_cbranch_execz .LBB6_2
; GFX11-NEXT:  ; %bb.1: ; %frem.else
; GFX11-NEXT:    v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[2:3]|
; GFX11-NEXT:    v_and_b32_e32 v4, 0x80000000, v1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_cndmask_b32_e32 v5, v1, v4, vcc_lo
; GFX11-NEXT:    v_cndmask_b32_e64 v4, v0, 0, vcc_lo
; GFX11-NEXT:  .LBB6_2: ; %Flow13
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB6_8
; GFX11-NEXT:  ; %bb.3: ; %frem.compute
; GFX11-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; GFX11-NEXT:    v_frexp_exp_i32_f64_e32 v11, v[2:3]
; GFX11-NEXT:    v_frexp_exp_i32_f64_e32 v10, v[0:1]
; GFX11-NEXT:    s_mov_b32 s1, exec_lo
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_ldexp_f64 v[8:9], v[4:5], 26
; GFX11-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[2:3]|
; GFX11-NEXT:    v_add_nc_u32_e32 v12, -1, v11
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_xad_u32 v13, v12, -1, v10
; GFX11-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], 1.0
; GFX11-NEXT:    v_rcp_f64_e32 v[14:15], v[6:7]
; GFX11-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT:    v_fma_f64 v[16:17], -v[6:7], v[14:15], 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
; GFX11-NEXT:    v_fma_f64 v[16:17], -v[6:7], v[14:15], 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
; GFX11-NEXT:    v_div_scale_f64 v[16:17], vcc_lo, 1.0, v[4:5], 1.0
; GFX11-NEXT:    v_mul_f64 v[18:19], v[16:17], v[14:15]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[18:19], v[16:17]
; GFX11-NEXT:    v_div_fmas_f64 v[6:7], v[6:7], v[14:15], v[18:19]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_div_fixup_f64 v[6:7], v[6:7], v[4:5], 1.0
; GFX11-NEXT:    v_cmpx_lt_i32_e32 26, v13
; GFX11-NEXT:    s_cbranch_execz .LBB6_7
; GFX11-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
; GFX11-NEXT:    v_sub_nc_u32_e32 v10, v10, v11
; GFX11-NEXT:    s_mov_b32 s2, 0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_add_nc_u32_e32 v13, 26, v10
; GFX11-NEXT:    .p2align 6
; GFX11-NEXT:  .LBB6_5: ; %frem.loop_body
; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT:    v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8
; GFX11-NEXT:    v_subrev_nc_u32_e32 v13, 26, v13
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_mul_f64 v[8:9], v[10:11], v[6:7]
; GFX11-NEXT:    v_rndne_f64_e32 v[8:9], v[8:9]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[4:5], v[10:11]
; GFX11-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[8:9]
; GFX11-NEXT:    v_add_f64 v[14:15], v[8:9], v[4:5]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT:    v_dual_cndmask_b32 v9, v9, v15 :: v_dual_cndmask_b32 v8, v8, v14
; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v13
; GFX11-NEXT:    v_ldexp_f64 v[8:9], v[8:9], 26
; GFX11-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX11-NEXT:    s_cbranch_execnz .LBB6_5
; GFX11-NEXT:  ; %bb.6: ; %Flow
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX11-NEXT:    v_dual_mov_b32 v8, v10 :: v_dual_mov_b32 v9, v11
; GFX11-NEXT:  .LBB6_7: ; %Flow12
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX11-NEXT:    v_subrev_nc_u32_e32 v10, 25, v13
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_ldexp_f64 v[8:9], v[8:9], v10
; GFX11-NEXT:    v_mul_f64 v[6:7], v[8:9], v[6:7]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_rndne_f64_e32 v[6:7], v[6:7]
; GFX11-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[4:5], v[8:9]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX11-NEXT:    v_add_f64 v[4:5], v[6:7], v[4:5]
; GFX11-NEXT:    v_dual_cndmask_b32 v5, v7, v5 :: v_dual_cndmask_b32 v4, v6, v4
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_ldexp_f64 v[4:5], v[4:5], v12
; GFX11-NEXT:    v_bfi_b32 v5, 0x7fffffff, v5, v1
; GFX11-NEXT:  .LBB6_8: ; %Flow14
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    v_cmp_lg_f64_e32 vcc_lo, 0, v[2:3]
; GFX11-NEXT:    v_cmp_nge_f64_e64 s0, |v[0:1]|, 0x7ff00000
; GFX11-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX11-NEXT:    v_dual_cndmask_b32 v0, 0, v4 :: v_dual_cndmask_b32 v1, 0x7ff80000, v5
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-LABEL: frem_f64:
; GFX1150:       ; %bb.0:
; GFX1150-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-NEXT:    v_cmp_ngt_f64_e64 s0, |v[0:1]|, |v[2:3]|
; GFX1150-NEXT:    ; implicit-def: $vgpr4_vgpr5
; GFX1150-NEXT:    s_and_saveexec_b32 s1, s0
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX1150-NEXT:    s_cbranch_execz .LBB6_2
; GFX1150-NEXT:  ; %bb.1: ; %frem.else
; GFX1150-NEXT:    v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[2:3]|
; GFX1150-NEXT:    v_and_b32_e32 v4, 0x80000000, v1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_cndmask_b32_e32 v5, v1, v4, vcc_lo
; GFX1150-NEXT:    v_cndmask_b32_e64 v4, v0, 0, vcc_lo
; GFX1150-NEXT:  .LBB6_2: ; %Flow13
; GFX1150-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1150-NEXT:    s_cbranch_execz .LBB6_8
; GFX1150-NEXT:  ; %bb.3: ; %frem.compute
; GFX1150-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; GFX1150-NEXT:    v_frexp_exp_i32_f64_e32 v11, v[2:3]
; GFX1150-NEXT:    v_frexp_exp_i32_f64_e32 v10, v[0:1]
; GFX1150-NEXT:    s_mov_b32 s1, exec_lo
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1150-NEXT:    v_ldexp_f64 v[8:9], v[4:5], 26
; GFX1150-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[2:3]|
; GFX1150-NEXT:    v_add_nc_u32_e32 v12, -1, v11
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_xad_u32 v13, v12, -1, v10
; GFX1150-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], 1.0
; GFX1150-NEXT:    v_rcp_f64_e32 v[14:15], v[6:7]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[16:17], -v[6:7], v[14:15], 1.0
; GFX1150-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[16:17], -v[6:7], v[14:15], 1.0
; GFX1150-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
; GFX1150-NEXT:    v_div_scale_f64 v[16:17], vcc_lo, 1.0, v[4:5], 1.0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f64 v[18:19], v[16:17], v[14:15]
; GFX1150-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[18:19], v[16:17]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_div_fmas_f64 v[6:7], v[6:7], v[14:15], v[18:19]
; GFX1150-NEXT:    v_div_fixup_f64 v[6:7], v[6:7], v[4:5], 1.0
; GFX1150-NEXT:    v_cmpx_lt_i32_e32 26, v13
; GFX1150-NEXT:    s_cbranch_execz .LBB6_7
; GFX1150-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
; GFX1150-NEXT:    v_sub_nc_u32_e32 v10, v10, v11
; GFX1150-NEXT:    s_mov_b32 s2, 0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_add_nc_u32_e32 v13, 26, v10
; GFX1150-NEXT:    .p2align 6
; GFX1150-NEXT:  .LBB6_5: ; %frem.loop_body
; GFX1150-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1150-NEXT:    v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8
; GFX1150-NEXT:    v_subrev_nc_u32_e32 v13, 26, v13
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f64 v[8:9], v[10:11], v[6:7]
; GFX1150-NEXT:    v_rndne_f64_e32 v[8:9], v[8:9]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[4:5], v[10:11]
; GFX1150-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[8:9]
; GFX1150-NEXT:    v_add_f64 v[14:15], v[8:9], v[4:5]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-NEXT:    v_dual_cndmask_b32 v9, v9, v15 :: v_dual_cndmask_b32 v8, v8, v14
; GFX1150-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v13
; GFX1150-NEXT:    v_ldexp_f64 v[8:9], v[8:9], 26
; GFX1150-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1150-NEXT:    s_cbranch_execnz .LBB6_5
; GFX1150-NEXT:  ; %bb.6: ; %Flow
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1150-NEXT:    v_dual_mov_b32 v8, v10 :: v_dual_mov_b32 v9, v11
; GFX1150-NEXT:  .LBB6_7: ; %Flow12
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1150-NEXT:    v_subrev_nc_u32_e32 v10, 25, v13
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f64 v[8:9], v[8:9], v10
; GFX1150-NEXT:    v_mul_f64 v[6:7], v[8:9], v[6:7]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_rndne_f64_e32 v[6:7], v[6:7]
; GFX1150-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[4:5], v[8:9]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX1150-NEXT:    v_add_f64 v[4:5], v[6:7], v[4:5]
; GFX1150-NEXT:    v_dual_cndmask_b32 v5, v7, v5 :: v_dual_cndmask_b32 v4, v6, v4
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f64 v[4:5], v[4:5], v12
; GFX1150-NEXT:    v_bfi_b32 v5, 0x7fffffff, v5, v1
; GFX1150-NEXT:  .LBB6_8: ; %Flow14
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1150-NEXT:    v_cmp_lg_f64_e32 vcc_lo, 0, v[2:3]
; GFX1150-NEXT:    v_cmp_nge_f64_e64 s0, |v[0:1]|, 0x7ff00000
; GFX1150-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1150-NEXT:    v_dual_cndmask_b32 v0, 0, v4 :: v_dual_cndmask_b32 v1, 0x7ff80000, v5
; GFX1150-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: frem_f64:
; GFX1200:       ; %bb.0:
; GFX1200-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT:    s_wait_expcnt 0x0
; GFX1200-NEXT:    s_wait_samplecnt 0x0
; GFX1200-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-NEXT:    s_wait_kmcnt 0x0
; GFX1200-NEXT:    v_cmp_ngt_f64_e64 s0, |v[0:1]|, |v[2:3]|
; GFX1200-NEXT:    ; implicit-def: $vgpr4_vgpr5
; GFX1200-NEXT:    s_and_saveexec_b32 s1, s0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX1200-NEXT:    s_cbranch_execz .LBB6_2
; GFX1200-NEXT:  ; %bb.1: ; %frem.else
; GFX1200-NEXT:    v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[2:3]|
; GFX1200-NEXT:    v_and_b32_e32 v4, 0x80000000, v1
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT:    v_cndmask_b32_e32 v5, v1, v4, vcc_lo
; GFX1200-NEXT:    v_cndmask_b32_e64 v4, v0, 0, vcc_lo
; GFX1200-NEXT:  .LBB6_2: ; %Flow13
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1200-NEXT:    s_cbranch_execz .LBB6_8
; GFX1200-NEXT:  ; %bb.3: ; %frem.compute
; GFX1200-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; GFX1200-NEXT:    v_frexp_exp_i32_f64_e32 v11, v[2:3]
; GFX1200-NEXT:    v_frexp_exp_i32_f64_e32 v10, v[0:1]
; GFX1200-NEXT:    s_mov_b32 s1, exec_lo
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1200-NEXT:    v_ldexp_f64 v[8:9], v[4:5], 26
; GFX1200-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[2:3]|
; GFX1200-NEXT:    v_add_nc_u32_e32 v12, -1, v11
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT:    v_xad_u32 v13, v12, -1, v10
; GFX1200-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], 1.0
; GFX1200-NEXT:    v_rcp_f64_e32 v[14:15], v[6:7]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f64 v[16:17], -v[6:7], v[14:15], 1.0
; GFX1200-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f64 v[16:17], -v[6:7], v[14:15], 1.0
; GFX1200-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
; GFX1200-NEXT:    v_div_scale_f64 v[16:17], vcc_lo, 1.0, v[4:5], 1.0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_mul_f64_e32 v[18:19], v[16:17], v[14:15]
; GFX1200-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[18:19], v[16:17]
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_div_fmas_f64 v[6:7], v[6:7], v[14:15], v[18:19]
; GFX1200-NEXT:    v_div_fixup_f64 v[6:7], v[6:7], v[4:5], 1.0
; GFX1200-NEXT:    v_cmpx_lt_i32_e32 26, v13
; GFX1200-NEXT:    s_cbranch_execz .LBB6_7
; GFX1200-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
; GFX1200-NEXT:    v_sub_nc_u32_e32 v10, v10, v11
; GFX1200-NEXT:    s_mov_b32 s2, 0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_add_nc_u32_e32 v13, 26, v10
; GFX1200-NEXT:  .LBB6_5: ; %frem.loop_body
; GFX1200-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT:    v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8
; GFX1200-NEXT:    v_subrev_nc_u32_e32 v13, 26, v13
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_mul_f64_e32 v[8:9], v[10:11], v[6:7]
; GFX1200-NEXT:    v_rndne_f64_e32 v[8:9], v[8:9]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[4:5], v[10:11]
; GFX1200-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[8:9]
; GFX1200-NEXT:    v_add_f64_e32 v[14:15], v[8:9], v[4:5]
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT:    v_dual_cndmask_b32 v9, v9, v15 :: v_dual_cndmask_b32 v8, v8, v14
; GFX1200-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v13
; GFX1200-NEXT:    v_ldexp_f64 v[8:9], v[8:9], 26
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1200-NEXT:    s_cbranch_execnz .LBB6_5
; GFX1200-NEXT:  ; %bb.6: ; %Flow
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1200-NEXT:    v_dual_mov_b32 v8, v10 :: v_dual_mov_b32 v9, v11
; GFX1200-NEXT:  .LBB6_7: ; %Flow12
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1200-NEXT:    v_subrev_nc_u32_e32 v10, 25, v13
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_ldexp_f64 v[8:9], v[8:9], v10
; GFX1200-NEXT:    v_mul_f64_e32 v[6:7], v[8:9], v[6:7]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_rndne_f64_e32 v[6:7], v[6:7]
; GFX1200-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[4:5], v[8:9]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX1200-NEXT:    v_add_f64_e32 v[4:5], v[6:7], v[4:5]
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_dual_cndmask_b32 v5, v7, v5 :: v_dual_cndmask_b32 v4, v6, v4
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_ldexp_f64 v[4:5], v[4:5], v12
; GFX1200-NEXT:    v_bfi_b32 v5, 0x7fffffff, v5, v1
; GFX1200-NEXT:  .LBB6_8: ; %Flow14
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1200-NEXT:    v_cmp_lg_f64_e32 vcc_lo, 0, v[2:3]
; GFX1200-NEXT:    v_cmp_nge_f64_e64 s0, |v[0:1]|, 0x7ff00000
; GFX1200-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    v_dual_cndmask_b32 v0, 0, v4 :: v_dual_cndmask_b32 v1, 0x7ff80000, v5
; GFX1200-NEXT:    s_setpc_b64 s[30:31]
   %r2 = frem double %in1, %in2
  ret double %r2
}

define double @fast_frem_f64(double %in1, double %in2) #0 {
; SI-LABEL: fast_frem_f64:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_div_scale_f64 v[4:5], s[4:5], v[2:3], v[2:3], v[0:1]
; SI-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
; SI-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v5
; SI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; SI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; SI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; SI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; SI-NEXT:    v_div_scale_f64 v[8:9], s[4:5], v[0:1], v[2:3], v[0:1]
; SI-NEXT:    v_mul_f64 v[10:11], v[8:9], v[6:7]
; SI-NEXT:    v_cmp_eq_u32_e64 s[4:5], v1, v9
; SI-NEXT:    v_fma_f64 v[12:13], -v[4:5], v[10:11], v[8:9]
; SI-NEXT:    s_xor_b64 vcc, s[4:5], vcc
; SI-NEXT:    v_div_fmas_f64 v[4:5], v[12:13], v[6:7], v[10:11]
; SI-NEXT:    s_movk_i32 s4, 0xfc01
; SI-NEXT:    s_mov_b32 s5, 0xfffff
; SI-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
; SI-NEXT:    v_bfe_u32 v6, v5, 20, 11
; SI-NEXT:    v_add_i32_e32 v8, vcc, s4, v6
; SI-NEXT:    s_mov_b32 s4, -1
; SI-NEXT:    v_lshr_b64 v[6:7], s[4:5], v8
; SI-NEXT:    v_and_b32_e32 v9, 0x80000000, v5
; SI-NEXT:    v_bfi_b32 v7, v7, 0, v5
; SI-NEXT:    v_bfi_b32 v6, v6, 0, v4
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v8
; SI-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc
; SI-NEXT:    v_cmp_lt_i32_e64 s[4:5], 51, v8
; SI-NEXT:    v_cndmask_b32_e64 v6, v6, 0, vcc
; SI-NEXT:    v_cndmask_b32_e64 v5, v7, v5, s[4:5]
; SI-NEXT:    v_cndmask_b32_e64 v4, v6, v4, s[4:5]
; SI-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; CI-LABEL: fast_frem_f64:
; CI:       ; %bb.0:
; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-NEXT:    v_div_scale_f64 v[4:5], s[4:5], v[2:3], v[2:3], v[0:1]
; CI-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
; CI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; CI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; CI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; CI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; CI-NEXT:    v_div_scale_f64 v[8:9], vcc, v[0:1], v[2:3], v[0:1]
; CI-NEXT:    v_mul_f64 v[10:11], v[8:9], v[6:7]
; CI-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
; CI-NEXT:    s_nop 1
; CI-NEXT:    v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
; CI-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
; CI-NEXT:    v_trunc_f64_e32 v[4:5], v[4:5]
; CI-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
; CI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: fast_frem_f64:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_div_scale_f64 v[4:5], s[4:5], v[2:3], v[2:3], v[0:1]
; VI-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
; VI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; VI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; VI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; VI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; VI-NEXT:    v_div_scale_f64 v[8:9], vcc, v[0:1], v[2:3], v[0:1]
; VI-NEXT:    v_mul_f64 v[10:11], v[8:9], v[6:7]
; VI-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
; VI-NEXT:    s_nop 1
; VI-NEXT:    v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
; VI-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
; VI-NEXT:    v_trunc_f64_e32 v[4:5], v[4:5]
; VI-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: fast_frem_f64:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_div_scale_f64 v[4:5], s[4:5], v[2:3], v[2:3], v[0:1]
; GFX9-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
; GFX9-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX9-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX9-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX9-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX9-NEXT:    v_div_scale_f64 v[8:9], vcc, v[0:1], v[2:3], v[0:1]
; GFX9-NEXT:    v_mul_f64 v[10:11], v[8:9], v[6:7]
; GFX9-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
; GFX9-NEXT:    s_nop 1
; GFX9-NEXT:    v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
; GFX9-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
; GFX9-NEXT:    v_trunc_f64_e32 v[4:5], v[4:5]
; GFX9-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: fast_frem_f64:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_div_scale_f64 v[4:5], s4, v[2:3], v[2:3], v[0:1]
; GFX10-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
; GFX10-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX10-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX10-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX10-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX10-NEXT:    v_div_scale_f64 v[8:9], vcc_lo, v[0:1], v[2:3], v[0:1]
; GFX10-NEXT:    v_mul_f64 v[10:11], v[8:9], v[6:7]
; GFX10-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
; GFX10-NEXT:    v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
; GFX10-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
; GFX10-NEXT:    v_trunc_f64_e32 v[4:5], v[4:5]
; GFX10-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: fast_frem_f64:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], v[0:1]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
; GFX11-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX11-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX11-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX11-NEXT:    v_div_scale_f64 v[8:9], vcc_lo, v[0:1], v[2:3], v[0:1]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_mul_f64 v[10:11], v[8:9], v[6:7]
; GFX11-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
; GFX11-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_trunc_f64_e32 v[4:5], v[4:5]
; GFX11-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-LABEL: fast_frem_f64:
; GFX1150:       ; %bb.0:
; GFX1150-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-NEXT:    v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], v[0:1]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
; GFX1150-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX1150-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX1150-NEXT:    v_div_scale_f64 v[8:9], vcc_lo, v[0:1], v[2:3], v[0:1]
; GFX1150-NEXT:    v_mul_f64 v[10:11], v[8:9], v[6:7]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
; GFX1150-NEXT:    v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
; GFX1150-NEXT:    v_trunc_f64_e32 v[4:5], v[4:5]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
; GFX1150-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: fast_frem_f64:
; GFX1200:       ; %bb.0:
; GFX1200-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT:    s_wait_expcnt 0x0
; GFX1200-NEXT:    s_wait_samplecnt 0x0
; GFX1200-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-NEXT:    s_wait_kmcnt 0x0
; GFX1200-NEXT:    v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], v[0:1]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
; GFX1200-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX1200-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX1200-NEXT:    v_div_scale_f64 v[8:9], vcc_lo, v[0:1], v[2:3], v[0:1]
; GFX1200-NEXT:    v_mul_f64_e32 v[10:11], v[8:9], v[6:7]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
; GFX1200-NEXT:    v_trunc_f64_e32 v[4:5], v[4:5]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
; GFX1200-NEXT:    s_setpc_b64 s[30:31]
   %r2 = frem fast double %in1, %in2
  ret double %r2
}

define double @unsafe_frem_f64(double %in1, double %in2) #0 {
; SI-LABEL: unsafe_frem_f64:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_div_scale_f64 v[4:5], s[4:5], v[2:3], v[2:3], v[0:1]
; SI-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
; SI-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v5
; SI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; SI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; SI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; SI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; SI-NEXT:    v_div_scale_f64 v[8:9], s[4:5], v[0:1], v[2:3], v[0:1]
; SI-NEXT:    v_mul_f64 v[10:11], v[8:9], v[6:7]
; SI-NEXT:    v_cmp_eq_u32_e64 s[4:5], v1, v9
; SI-NEXT:    v_fma_f64 v[12:13], -v[4:5], v[10:11], v[8:9]
; SI-NEXT:    s_xor_b64 vcc, s[4:5], vcc
; SI-NEXT:    v_div_fmas_f64 v[4:5], v[12:13], v[6:7], v[10:11]
; SI-NEXT:    s_movk_i32 s4, 0xfc01
; SI-NEXT:    s_mov_b32 s5, 0xfffff
; SI-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
; SI-NEXT:    v_bfe_u32 v6, v5, 20, 11
; SI-NEXT:    v_add_i32_e32 v8, vcc, s4, v6
; SI-NEXT:    s_mov_b32 s4, -1
; SI-NEXT:    v_lshr_b64 v[6:7], s[4:5], v8
; SI-NEXT:    v_and_b32_e32 v9, 0x80000000, v5
; SI-NEXT:    v_bfi_b32 v7, v7, 0, v5
; SI-NEXT:    v_bfi_b32 v6, v6, 0, v4
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v8
; SI-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc
; SI-NEXT:    v_cmp_lt_i32_e64 s[4:5], 51, v8
; SI-NEXT:    v_cndmask_b32_e64 v6, v6, 0, vcc
; SI-NEXT:    v_cndmask_b32_e64 v5, v7, v5, s[4:5]
; SI-NEXT:    v_cndmask_b32_e64 v4, v6, v4, s[4:5]
; SI-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; CI-LABEL: unsafe_frem_f64:
; CI:       ; %bb.0:
; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-NEXT:    v_div_scale_f64 v[4:5], s[4:5], v[2:3], v[2:3], v[0:1]
; CI-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
; CI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; CI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; CI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; CI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; CI-NEXT:    v_div_scale_f64 v[8:9], vcc, v[0:1], v[2:3], v[0:1]
; CI-NEXT:    v_mul_f64 v[10:11], v[8:9], v[6:7]
; CI-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
; CI-NEXT:    s_nop 1
; CI-NEXT:    v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
; CI-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
; CI-NEXT:    v_trunc_f64_e32 v[4:5], v[4:5]
; CI-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
; CI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: unsafe_frem_f64:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_div_scale_f64 v[4:5], s[4:5], v[2:3], v[2:3], v[0:1]
; VI-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
; VI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; VI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; VI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; VI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; VI-NEXT:    v_div_scale_f64 v[8:9], vcc, v[0:1], v[2:3], v[0:1]
; VI-NEXT:    v_mul_f64 v[10:11], v[8:9], v[6:7]
; VI-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
; VI-NEXT:    s_nop 1
; VI-NEXT:    v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
; VI-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
; VI-NEXT:    v_trunc_f64_e32 v[4:5], v[4:5]
; VI-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: unsafe_frem_f64:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_div_scale_f64 v[4:5], s[4:5], v[2:3], v[2:3], v[0:1]
; GFX9-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
; GFX9-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX9-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX9-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX9-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX9-NEXT:    v_div_scale_f64 v[8:9], vcc, v[0:1], v[2:3], v[0:1]
; GFX9-NEXT:    v_mul_f64 v[10:11], v[8:9], v[6:7]
; GFX9-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
; GFX9-NEXT:    s_nop 1
; GFX9-NEXT:    v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
; GFX9-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
; GFX9-NEXT:    v_trunc_f64_e32 v[4:5], v[4:5]
; GFX9-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: unsafe_frem_f64:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_div_scale_f64 v[4:5], s4, v[2:3], v[2:3], v[0:1]
; GFX10-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
; GFX10-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX10-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX10-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX10-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX10-NEXT:    v_div_scale_f64 v[8:9], vcc_lo, v[0:1], v[2:3], v[0:1]
; GFX10-NEXT:    v_mul_f64 v[10:11], v[8:9], v[6:7]
; GFX10-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
; GFX10-NEXT:    v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
; GFX10-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
; GFX10-NEXT:    v_trunc_f64_e32 v[4:5], v[4:5]
; GFX10-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: unsafe_frem_f64:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], v[0:1]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
; GFX11-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX11-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX11-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX11-NEXT:    v_div_scale_f64 v[8:9], vcc_lo, v[0:1], v[2:3], v[0:1]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_mul_f64 v[10:11], v[8:9], v[6:7]
; GFX11-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
; GFX11-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_trunc_f64_e32 v[4:5], v[4:5]
; GFX11-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-LABEL: unsafe_frem_f64:
; GFX1150:       ; %bb.0:
; GFX1150-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-NEXT:    v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], v[0:1]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
; GFX1150-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX1150-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX1150-NEXT:    v_div_scale_f64 v[8:9], vcc_lo, v[0:1], v[2:3], v[0:1]
; GFX1150-NEXT:    v_mul_f64 v[10:11], v[8:9], v[6:7]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
; GFX1150-NEXT:    v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
; GFX1150-NEXT:    v_trunc_f64_e32 v[4:5], v[4:5]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
; GFX1150-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: unsafe_frem_f64:
; GFX1200:       ; %bb.0:
; GFX1200-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT:    s_wait_expcnt 0x0
; GFX1200-NEXT:    s_wait_samplecnt 0x0
; GFX1200-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-NEXT:    s_wait_kmcnt 0x0
; GFX1200-NEXT:    v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], v[0:1]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
; GFX1200-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX1200-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX1200-NEXT:    v_div_scale_f64 v[8:9], vcc_lo, v[0:1], v[2:3], v[0:1]
; GFX1200-NEXT:    v_mul_f64_e32 v[10:11], v[8:9], v[6:7]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
; GFX1200-NEXT:    v_trunc_f64_e32 v[4:5], v[4:5]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
; GFX1200-NEXT:    s_setpc_b64 s[30:31]
   %r2 = frem afn double %in1, %in2
  ret double %r2
}

define <2 x half> @frem_v2f16(<2 x half> %in1, <2 x half> %in2) #0 {
; SI-LABEL: frem_v2f16:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cvt_f32_f16_e64 v4, |v0|
; SI-NEXT:    v_cvt_f32_f16_e64 v3, |v1|
; SI-NEXT:    ; implicit-def: $vgpr2
; SI-NEXT:    v_cmp_ngt_f32_e32 vcc, v4, v3
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:  ; %bb.1: ; %frem.else20
; SI-NEXT:    v_and_b32_e32 v2, 0xffff8000, v0
; SI-NEXT:    v_cmp_eq_f32_e32 vcc, v4, v3
; SI-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc
; SI-NEXT:    ; implicit-def: $vgpr4
; SI-NEXT:    ; implicit-def: $vgpr3
; SI-NEXT:  ; %bb.2: ; %Flow54
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB9_8
; SI-NEXT:  ; %bb.3: ; %frem.compute19
; SI-NEXT:    s_mov_b32 s6, 0x7f800000
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v4|, s6
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v2, v4
; SI-NEXT:    v_cndmask_b32_e32 v7, 0, v2, vcc
; SI-NEXT:    v_frexp_mant_f32_e32 v2, v4
; SI-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; SI-NEXT:    v_ldexp_f32_e64 v4, v2, 11
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v3|, s6
; SI-NEXT:    v_frexp_mant_f32_e32 v2, v3
; SI-NEXT:    v_cndmask_b32_e32 v5, v3, v2, vcc
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v2, v3
; SI-NEXT:    v_ldexp_f32_e64 v3, v5, 1
; SI-NEXT:    v_cndmask_b32_e32 v8, 0, v2, vcc
; SI-NEXT:    v_div_scale_f32 v9, s[6:7], v3, v3, 1.0
; SI-NEXT:    v_add_i32_e32 v2, vcc, -1, v8
; SI-NEXT:    v_rcp_f32_e32 v10, v9
; SI-NEXT:    v_not_b32_e32 v5, v2
; SI-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
; SI-NEXT:    v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; SI-NEXT:    v_fma_f32 v10, v11, v10, v10
; SI-NEXT:    v_mul_f32_e32 v11, v6, v10
; SI-NEXT:    v_fma_f32 v12, -v9, v11, v6
; SI-NEXT:    v_fma_f32 v11, v12, v10, v11
; SI-NEXT:    v_fma_f32 v6, -v9, v11, v6
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
; SI-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v5
; SI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; SI-NEXT:    s_cbranch_execz .LBB9_7
; SI-NEXT:  ; %bb.4: ; %frem.loop_body27.preheader
; SI-NEXT:    v_sub_i32_e32 v5, vcc, v7, v8
; SI-NEXT:    v_add_i32_e32 v5, vcc, 11, v5
; SI-NEXT:    s_mov_b64 s[8:9], 0
; SI-NEXT:  .LBB9_5: ; %frem.loop_body27
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v7, v4
; SI-NEXT:    v_mul_f32_e32 v4, v7, v6
; SI-NEXT:    v_rndne_f32_e32 v4, v4
; SI-NEXT:    v_fma_f32 v4, -v4, v3, v7
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; SI-NEXT:    v_add_f32_e32 v8, v4, v3
; SI-NEXT:    v_cndmask_b32_e32 v4, v4, v8, vcc
; SI-NEXT:    v_add_i32_e32 v5, vcc, -11, v5
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v5
; SI-NEXT:    v_ldexp_f32_e64 v4, v4, 11
; SI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; SI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; SI-NEXT:    s_cbranch_execnz .LBB9_5
; SI-NEXT:  ; %bb.6: ; %Flow52
; SI-NEXT:    s_or_b64 exec, exec, s[8:9]
; SI-NEXT:    v_mov_b32_e32 v4, v7
; SI-NEXT:  .LBB9_7: ; %Flow53
; SI-NEXT:    s_or_b64 exec, exec, s[6:7]
; SI-NEXT:    v_add_i32_e32 v5, vcc, -10, v5
; SI-NEXT:    v_ldexp_f32_e32 v4, v4, v5
; SI-NEXT:    v_mul_f32_e32 v5, v4, v6
; SI-NEXT:    v_rndne_f32_e32 v5, v5
; SI-NEXT:    v_fma_f32 v4, -v5, v3, v4
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; SI-NEXT:    v_add_f32_e32 v3, v4, v3
; SI-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; SI-NEXT:    v_ldexp_f32_e32 v2, v3, v2
; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; SI-NEXT:    s_movk_i32 s6, 0x7fff
; SI-NEXT:    v_bfi_b32 v2, s6, v2, v0
; SI-NEXT:  .LBB9_8: ; %Flow55
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    v_lshrrev_b32_e32 v4, 16, v1
; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; SI-NEXT:    v_cvt_f32_f16_e64 v7, |v3|
; SI-NEXT:    v_cvt_f32_f16_e64 v6, |v4|
; SI-NEXT:    ; implicit-def: $vgpr5
; SI-NEXT:    v_cmp_ngt_f32_e32 vcc, v7, v6
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:  ; %bb.9: ; %frem.else
; SI-NEXT:    v_and_b32_e32 v5, 0x8000, v3
; SI-NEXT:    v_cmp_eq_f32_e32 vcc, v7, v6
; SI-NEXT:    v_cndmask_b32_e32 v5, v3, v5, vcc
; SI-NEXT:    ; implicit-def: $vgpr7
; SI-NEXT:    ; implicit-def: $vgpr6
; SI-NEXT:  ; %bb.10: ; %Flow50
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB9_16
; SI-NEXT:  ; %bb.11: ; %frem.compute
; SI-NEXT:    s_mov_b32 s6, 0x7f800000
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v7|, s6
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v5, v7
; SI-NEXT:    v_cndmask_b32_e32 v10, 0, v5, vcc
; SI-NEXT:    v_frexp_mant_f32_e32 v5, v7
; SI-NEXT:    v_cndmask_b32_e32 v5, v7, v5, vcc
; SI-NEXT:    v_ldexp_f32_e64 v7, v5, 11
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v6|, s6
; SI-NEXT:    v_frexp_mant_f32_e32 v5, v6
; SI-NEXT:    v_cndmask_b32_e32 v8, v6, v5, vcc
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v5, v6
; SI-NEXT:    v_ldexp_f32_e64 v6, v8, 1
; SI-NEXT:    v_cndmask_b32_e32 v11, 0, v5, vcc
; SI-NEXT:    v_div_scale_f32 v12, s[6:7], v6, v6, 1.0
; SI-NEXT:    v_add_i32_e32 v5, vcc, -1, v11
; SI-NEXT:    v_rcp_f32_e32 v13, v12
; SI-NEXT:    v_not_b32_e32 v8, v5
; SI-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
; SI-NEXT:    v_div_scale_f32 v9, vcc, 1.0, v6, 1.0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    v_fma_f32 v14, -v12, v13, 1.0
; SI-NEXT:    v_fma_f32 v13, v14, v13, v13
; SI-NEXT:    v_mul_f32_e32 v14, v9, v13
; SI-NEXT:    v_fma_f32 v15, -v12, v14, v9
; SI-NEXT:    v_fma_f32 v14, v15, v13, v14
; SI-NEXT:    v_fma_f32 v9, -v12, v14, v9
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    v_div_fmas_f32 v9, v9, v13, v14
; SI-NEXT:    v_div_fixup_f32 v9, v9, v6, 1.0
; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v8
; SI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; SI-NEXT:    s_cbranch_execz .LBB9_15
; SI-NEXT:  ; %bb.12: ; %frem.loop_body.preheader
; SI-NEXT:    v_sub_i32_e32 v8, vcc, v10, v11
; SI-NEXT:    v_add_i32_e32 v8, vcc, 11, v8
; SI-NEXT:    s_mov_b64 s[8:9], 0
; SI-NEXT:  .LBB9_13: ; %frem.loop_body
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v10, v7
; SI-NEXT:    v_mul_f32_e32 v7, v10, v9
; SI-NEXT:    v_rndne_f32_e32 v7, v7
; SI-NEXT:    v_fma_f32 v7, -v7, v6, v10
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v7
; SI-NEXT:    v_add_f32_e32 v11, v7, v6
; SI-NEXT:    v_cndmask_b32_e32 v7, v7, v11, vcc
; SI-NEXT:    v_add_i32_e32 v8, vcc, -11, v8
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v8
; SI-NEXT:    v_ldexp_f32_e64 v7, v7, 11
; SI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; SI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; SI-NEXT:    s_cbranch_execnz .LBB9_13
; SI-NEXT:  ; %bb.14: ; %Flow
; SI-NEXT:    s_or_b64 exec, exec, s[8:9]
; SI-NEXT:    v_mov_b32_e32 v7, v10
; SI-NEXT:  .LBB9_15: ; %Flow49
; SI-NEXT:    s_or_b64 exec, exec, s[6:7]
; SI-NEXT:    v_add_i32_e32 v8, vcc, -10, v8
; SI-NEXT:    v_ldexp_f32_e32 v7, v7, v8
; SI-NEXT:    v_mul_f32_e32 v8, v7, v9
; SI-NEXT:    v_rndne_f32_e32 v8, v8
; SI-NEXT:    v_fma_f32 v7, -v8, v6, v7
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v7
; SI-NEXT:    v_add_f32_e32 v6, v7, v6
; SI-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc
; SI-NEXT:    v_ldexp_f32_e32 v5, v6, v5
; SI-NEXT:    v_cvt_f16_f32_e32 v5, v5
; SI-NEXT:    v_and_b32_e32 v6, 0x8000, v3
; SI-NEXT:    v_and_b32_e32 v5, 0x7fff, v5
; SI-NEXT:    v_or_b32_e32 v5, v5, v6
; SI-NEXT:  .LBB9_16: ; %Flow51
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
; SI-NEXT:    v_cvt_f32_f16_e64 v0, |v0|
; SI-NEXT:    s_mov_b32 s6, 0x7f800000
; SI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v1
; SI-NEXT:    v_cmp_nle_f32_e64 s[4:5], s6, v0
; SI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; SI-NEXT:    v_mov_b32_e32 v0, 0x7e00
; SI-NEXT:    v_cndmask_b32_e32 v1, v0, v2, vcc
; SI-NEXT:    v_cvt_f32_f16_e32 v2, v4
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v2
; SI-NEXT:    v_cvt_f32_f16_e64 v2, |v3|
; SI-NEXT:    v_cmp_nle_f32_e64 s[4:5], s6, v2
; SI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT:    v_or_b32_e32 v0, v1, v0
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; CI-LABEL: frem_v2f16:
; CI:       ; %bb.0:
; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-NEXT:    v_cvt_f32_f16_e64 v4, |v0|
; CI-NEXT:    v_cvt_f32_f16_e64 v3, |v1|
; CI-NEXT:    ; implicit-def: $vgpr2
; CI-NEXT:    v_cmp_ngt_f32_e32 vcc, v4, v3
; CI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; CI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; CI-NEXT:  ; %bb.1: ; %frem.else20
; CI-NEXT:    v_and_b32_e32 v2, 0xffff8000, v0
; CI-NEXT:    v_cmp_eq_f32_e32 vcc, v4, v3
; CI-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc
; CI-NEXT:    ; implicit-def: $vgpr4
; CI-NEXT:    ; implicit-def: $vgpr3
; CI-NEXT:  ; %bb.2: ; %Flow54
; CI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; CI-NEXT:    s_cbranch_execz .LBB9_8
; CI-NEXT:  ; %bb.3: ; %frem.compute19
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v7, v4
; CI-NEXT:    v_frexp_mant_f32_e32 v2, v4
; CI-NEXT:    v_frexp_mant_f32_e32 v4, v3
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v8, v3
; CI-NEXT:    v_ldexp_f32_e64 v3, v4, 1
; CI-NEXT:    v_div_scale_f32 v9, s[6:7], v3, v3, 1.0
; CI-NEXT:    v_ldexp_f32_e64 v5, v2, 11
; CI-NEXT:    v_add_i32_e32 v2, vcc, -1, v8
; CI-NEXT:    v_not_b32_e32 v4, v2
; CI-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
; CI-NEXT:    v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
; CI-NEXT:    v_rcp_f32_e32 v10, v9
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; CI-NEXT:    v_fma_f32 v10, v11, v10, v10
; CI-NEXT:    v_mul_f32_e32 v11, v6, v10
; CI-NEXT:    v_fma_f32 v12, -v9, v11, v6
; CI-NEXT:    v_fma_f32 v11, v12, v10, v11
; CI-NEXT:    v_fma_f32 v6, -v9, v11, v6
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v4
; CI-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
; CI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; CI-NEXT:    s_cbranch_execz .LBB9_7
; CI-NEXT:  ; %bb.4: ; %frem.loop_body27.preheader
; CI-NEXT:    v_sub_i32_e32 v4, vcc, v7, v8
; CI-NEXT:    v_add_i32_e32 v4, vcc, 11, v4
; CI-NEXT:    s_mov_b64 s[8:9], 0
; CI-NEXT:  .LBB9_5: ; %frem.loop_body27
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v7, v5
; CI-NEXT:    v_mul_f32_e32 v5, v7, v6
; CI-NEXT:    v_rndne_f32_e32 v5, v5
; CI-NEXT:    v_fma_f32 v5, -v5, v3, v7
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
; CI-NEXT:    v_add_f32_e32 v8, v5, v3
; CI-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc
; CI-NEXT:    v_add_i32_e32 v4, vcc, -11, v4
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v4
; CI-NEXT:    v_ldexp_f32_e64 v5, v5, 11
; CI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; CI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; CI-NEXT:    s_cbranch_execnz .LBB9_5
; CI-NEXT:  ; %bb.6: ; %Flow52
; CI-NEXT:    s_or_b64 exec, exec, s[8:9]
; CI-NEXT:    v_mov_b32_e32 v5, v7
; CI-NEXT:  .LBB9_7: ; %Flow53
; CI-NEXT:    s_or_b64 exec, exec, s[6:7]
; CI-NEXT:    v_add_i32_e32 v4, vcc, -10, v4
; CI-NEXT:    v_ldexp_f32_e32 v4, v5, v4
; CI-NEXT:    v_mul_f32_e32 v5, v4, v6
; CI-NEXT:    v_rndne_f32_e32 v5, v5
; CI-NEXT:    v_fma_f32 v4, -v5, v3, v4
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; CI-NEXT:    v_add_f32_e32 v3, v4, v3
; CI-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; CI-NEXT:    v_ldexp_f32_e32 v2, v3, v2
; CI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; CI-NEXT:    s_movk_i32 s6, 0x7fff
; CI-NEXT:    v_bfi_b32 v2, s6, v2, v0
; CI-NEXT:  .LBB9_8: ; %Flow55
; CI-NEXT:    s_or_b64 exec, exec, s[4:5]
; CI-NEXT:    v_lshrrev_b32_e32 v4, 16, v1
; CI-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; CI-NEXT:    v_cvt_f32_f16_e64 v7, |v3|
; CI-NEXT:    v_cvt_f32_f16_e64 v6, |v4|
; CI-NEXT:    ; implicit-def: $vgpr5
; CI-NEXT:    v_cmp_ngt_f32_e32 vcc, v7, v6
; CI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; CI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; CI-NEXT:  ; %bb.9: ; %frem.else
; CI-NEXT:    v_and_b32_e32 v5, 0x8000, v3
; CI-NEXT:    v_cmp_eq_f32_e32 vcc, v7, v6
; CI-NEXT:    v_cndmask_b32_e32 v5, v3, v5, vcc
; CI-NEXT:    ; implicit-def: $vgpr7
; CI-NEXT:    ; implicit-def: $vgpr6
; CI-NEXT:  ; %bb.10: ; %Flow50
; CI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; CI-NEXT:    s_cbranch_execz .LBB9_16
; CI-NEXT:  ; %bb.11: ; %frem.compute
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v10, v7
; CI-NEXT:    v_frexp_mant_f32_e32 v5, v7
; CI-NEXT:    v_frexp_mant_f32_e32 v7, v6
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v11, v6
; CI-NEXT:    v_ldexp_f32_e64 v6, v7, 1
; CI-NEXT:    v_div_scale_f32 v12, s[6:7], v6, v6, 1.0
; CI-NEXT:    v_ldexp_f32_e64 v8, v5, 11
; CI-NEXT:    v_add_i32_e32 v5, vcc, -1, v11
; CI-NEXT:    v_not_b32_e32 v7, v5
; CI-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
; CI-NEXT:    v_div_scale_f32 v9, vcc, 1.0, v6, 1.0
; CI-NEXT:    v_rcp_f32_e32 v13, v12
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v14, -v12, v13, 1.0
; CI-NEXT:    v_fma_f32 v13, v14, v13, v13
; CI-NEXT:    v_mul_f32_e32 v14, v9, v13
; CI-NEXT:    v_fma_f32 v15, -v12, v14, v9
; CI-NEXT:    v_fma_f32 v14, v15, v13, v14
; CI-NEXT:    v_fma_f32 v9, -v12, v14, v9
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v9, v9, v13, v14
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v7
; CI-NEXT:    v_div_fixup_f32 v9, v9, v6, 1.0
; CI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; CI-NEXT:    s_cbranch_execz .LBB9_15
; CI-NEXT:  ; %bb.12: ; %frem.loop_body.preheader
; CI-NEXT:    v_sub_i32_e32 v7, vcc, v10, v11
; CI-NEXT:    v_add_i32_e32 v7, vcc, 11, v7
; CI-NEXT:    s_mov_b64 s[8:9], 0
; CI-NEXT:  .LBB9_13: ; %frem.loop_body
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v10, v8
; CI-NEXT:    v_mul_f32_e32 v8, v10, v9
; CI-NEXT:    v_rndne_f32_e32 v8, v8
; CI-NEXT:    v_fma_f32 v8, -v8, v6, v10
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v8
; CI-NEXT:    v_add_f32_e32 v11, v8, v6
; CI-NEXT:    v_cndmask_b32_e32 v8, v8, v11, vcc
; CI-NEXT:    v_add_i32_e32 v7, vcc, -11, v7
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v7
; CI-NEXT:    v_ldexp_f32_e64 v8, v8, 11
; CI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; CI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; CI-NEXT:    s_cbranch_execnz .LBB9_13
; CI-NEXT:  ; %bb.14: ; %Flow
; CI-NEXT:    s_or_b64 exec, exec, s[8:9]
; CI-NEXT:    v_mov_b32_e32 v8, v10
; CI-NEXT:  .LBB9_15: ; %Flow49
; CI-NEXT:    s_or_b64 exec, exec, s[6:7]
; CI-NEXT:    v_add_i32_e32 v7, vcc, -10, v7
; CI-NEXT:    v_ldexp_f32_e32 v7, v8, v7
; CI-NEXT:    v_mul_f32_e32 v8, v7, v9
; CI-NEXT:    v_rndne_f32_e32 v8, v8
; CI-NEXT:    v_fma_f32 v7, -v8, v6, v7
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v7
; CI-NEXT:    v_add_f32_e32 v6, v7, v6
; CI-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc
; CI-NEXT:    v_ldexp_f32_e32 v5, v6, v5
; CI-NEXT:    v_cvt_f16_f32_e32 v5, v5
; CI-NEXT:    v_and_b32_e32 v6, 0x8000, v3
; CI-NEXT:    v_and_b32_e32 v5, 0x7fff, v5
; CI-NEXT:    v_or_b32_e32 v5, v5, v6
; CI-NEXT:  .LBB9_16: ; %Flow51
; CI-NEXT:    s_or_b64 exec, exec, s[4:5]
; CI-NEXT:    v_cvt_f32_f16_e32 v1, v1
; CI-NEXT:    v_cvt_f32_f16_e64 v0, |v0|
; CI-NEXT:    s_mov_b32 s6, 0x7f800000
; CI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v1
; CI-NEXT:    v_cmp_nle_f32_e64 s[4:5], s6, v0
; CI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; CI-NEXT:    v_mov_b32_e32 v0, 0x7e00
; CI-NEXT:    v_cndmask_b32_e32 v1, v0, v2, vcc
; CI-NEXT:    v_cvt_f32_f16_e32 v2, v4
; CI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; CI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v2
; CI-NEXT:    v_cvt_f32_f16_e64 v2, |v3|
; CI-NEXT:    v_cmp_nle_f32_e64 s[4:5], s6, v2
; CI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; CI-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
; CI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
; CI-NEXT:    v_or_b32_e32 v0, v1, v0
; CI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: frem_v2f16:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cvt_f32_f16_e64 v4, |v0|
; VI-NEXT:    v_cvt_f32_f16_e64 v3, |v1|
; VI-NEXT:    ; implicit-def: $vgpr2
; VI-NEXT:    v_cmp_ngt_f32_e32 vcc, v4, v3
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:  ; %bb.1: ; %frem.else20
; VI-NEXT:    v_and_b32_e32 v2, 0x8000, v0
; VI-NEXT:    v_cmp_eq_f32_e32 vcc, v4, v3
; VI-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc
; VI-NEXT:    ; implicit-def: $vgpr4
; VI-NEXT:    ; implicit-def: $vgpr3
; VI-NEXT:  ; %bb.2: ; %Flow54
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB9_8
; VI-NEXT:  ; %bb.3: ; %frem.compute19
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v7, v4
; VI-NEXT:    v_frexp_mant_f32_e32 v2, v4
; VI-NEXT:    v_frexp_mant_f32_e32 v4, v3
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v8, v3
; VI-NEXT:    v_ldexp_f32 v3, v4, 1
; VI-NEXT:    v_div_scale_f32 v9, s[6:7], v3, v3, 1.0
; VI-NEXT:    v_ldexp_f32 v5, v2, 11
; VI-NEXT:    v_add_u32_e32 v2, vcc, -1, v8
; VI-NEXT:    v_not_b32_e32 v4, v2
; VI-NEXT:    v_add_u32_e32 v4, vcc, v4, v7
; VI-NEXT:    v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
; VI-NEXT:    v_rcp_f32_e32 v10, v9
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; VI-NEXT:    v_fma_f32 v10, v11, v10, v10
; VI-NEXT:    v_mul_f32_e32 v11, v6, v10
; VI-NEXT:    v_fma_f32 v12, -v9, v11, v6
; VI-NEXT:    v_fma_f32 v11, v12, v10, v11
; VI-NEXT:    v_fma_f32 v6, -v9, v11, v6
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; VI-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v4
; VI-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
; VI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; VI-NEXT:    s_cbranch_execz .LBB9_7
; VI-NEXT:  ; %bb.4: ; %frem.loop_body27.preheader
; VI-NEXT:    v_sub_u32_e32 v4, vcc, v7, v8
; VI-NEXT:    v_add_u32_e32 v4, vcc, 11, v4
; VI-NEXT:    s_mov_b64 s[8:9], 0
; VI-NEXT:  .LBB9_5: ; %frem.loop_body27
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v7, v5
; VI-NEXT:    v_mul_f32_e32 v5, v7, v6
; VI-NEXT:    v_rndne_f32_e32 v5, v5
; VI-NEXT:    v_fma_f32 v5, -v5, v3, v7
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
; VI-NEXT:    v_add_f32_e32 v8, v5, v3
; VI-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc
; VI-NEXT:    v_add_u32_e32 v4, vcc, -11, v4
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v4
; VI-NEXT:    v_ldexp_f32 v5, v5, 11
; VI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; VI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; VI-NEXT:    s_cbranch_execnz .LBB9_5
; VI-NEXT:  ; %bb.6: ; %Flow52
; VI-NEXT:    s_or_b64 exec, exec, s[8:9]
; VI-NEXT:    v_mov_b32_e32 v5, v7
; VI-NEXT:  .LBB9_7: ; %Flow53
; VI-NEXT:    s_or_b64 exec, exec, s[6:7]
; VI-NEXT:    v_add_u32_e32 v4, vcc, -10, v4
; VI-NEXT:    v_ldexp_f32 v4, v5, v4
; VI-NEXT:    v_mul_f32_e32 v5, v4, v6
; VI-NEXT:    v_rndne_f32_e32 v5, v5
; VI-NEXT:    v_fma_f32 v4, -v5, v3, v4
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; VI-NEXT:    v_add_f32_e32 v3, v4, v3
; VI-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; VI-NEXT:    v_ldexp_f32 v2, v3, v2
; VI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; VI-NEXT:    s_movk_i32 s6, 0x7fff
; VI-NEXT:    v_bfi_b32 v2, s6, v2, v0
; VI-NEXT:  .LBB9_8: ; %Flow55
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; VI-NEXT:    v_lshrrev_b32_e32 v4, 16, v1
; VI-NEXT:    v_cvt_f32_f16_e64 v7, |v3|
; VI-NEXT:    v_cvt_f32_f16_e64 v6, |v4|
; VI-NEXT:    ; implicit-def: $vgpr5
; VI-NEXT:    v_cmp_ngt_f32_e32 vcc, v7, v6
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:  ; %bb.9: ; %frem.else
; VI-NEXT:    v_and_b32_e32 v5, 0x8000, v3
; VI-NEXT:    v_cmp_eq_f32_e32 vcc, v7, v6
; VI-NEXT:    v_cndmask_b32_e32 v5, v3, v5, vcc
; VI-NEXT:    ; implicit-def: $vgpr7
; VI-NEXT:    ; implicit-def: $vgpr6
; VI-NEXT:  ; %bb.10: ; %Flow50
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB9_16
; VI-NEXT:  ; %bb.11: ; %frem.compute
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v10, v7
; VI-NEXT:    v_frexp_mant_f32_e32 v5, v7
; VI-NEXT:    v_frexp_mant_f32_e32 v7, v6
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v11, v6
; VI-NEXT:    v_ldexp_f32 v6, v7, 1
; VI-NEXT:    v_div_scale_f32 v12, s[6:7], v6, v6, 1.0
; VI-NEXT:    v_ldexp_f32 v8, v5, 11
; VI-NEXT:    v_add_u32_e32 v5, vcc, -1, v11
; VI-NEXT:    v_not_b32_e32 v7, v5
; VI-NEXT:    v_add_u32_e32 v7, vcc, v7, v10
; VI-NEXT:    v_div_scale_f32 v9, vcc, 1.0, v6, 1.0
; VI-NEXT:    v_rcp_f32_e32 v13, v12
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT:    v_fma_f32 v14, -v12, v13, 1.0
; VI-NEXT:    v_fma_f32 v13, v14, v13, v13
; VI-NEXT:    v_mul_f32_e32 v14, v9, v13
; VI-NEXT:    v_fma_f32 v15, -v12, v14, v9
; VI-NEXT:    v_fma_f32 v14, v15, v13, v14
; VI-NEXT:    v_fma_f32 v9, -v12, v14, v9
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; VI-NEXT:    v_div_fmas_f32 v9, v9, v13, v14
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v7
; VI-NEXT:    v_div_fixup_f32 v9, v9, v6, 1.0
; VI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; VI-NEXT:    s_cbranch_execz .LBB9_15
; VI-NEXT:  ; %bb.12: ; %frem.loop_body.preheader
; VI-NEXT:    v_sub_u32_e32 v7, vcc, v10, v11
; VI-NEXT:    v_add_u32_e32 v7, vcc, 11, v7
; VI-NEXT:    s_mov_b64 s[8:9], 0
; VI-NEXT:  .LBB9_13: ; %frem.loop_body
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v10, v8
; VI-NEXT:    v_mul_f32_e32 v8, v10, v9
; VI-NEXT:    v_rndne_f32_e32 v8, v8
; VI-NEXT:    v_fma_f32 v8, -v8, v6, v10
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v8
; VI-NEXT:    v_add_f32_e32 v11, v8, v6
; VI-NEXT:    v_cndmask_b32_e32 v8, v8, v11, vcc
; VI-NEXT:    v_add_u32_e32 v7, vcc, -11, v7
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v7
; VI-NEXT:    v_ldexp_f32 v8, v8, 11
; VI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; VI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; VI-NEXT:    s_cbranch_execnz .LBB9_13
; VI-NEXT:  ; %bb.14: ; %Flow
; VI-NEXT:    s_or_b64 exec, exec, s[8:9]
; VI-NEXT:    v_mov_b32_e32 v8, v10
; VI-NEXT:  .LBB9_15: ; %Flow49
; VI-NEXT:    s_or_b64 exec, exec, s[6:7]
; VI-NEXT:    v_add_u32_e32 v7, vcc, -10, v7
; VI-NEXT:    v_ldexp_f32 v7, v8, v7
; VI-NEXT:    v_mul_f32_e32 v8, v7, v9
; VI-NEXT:    v_rndne_f32_e32 v8, v8
; VI-NEXT:    v_fma_f32 v7, -v8, v6, v7
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v7
; VI-NEXT:    v_add_f32_e32 v6, v7, v6
; VI-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc
; VI-NEXT:    v_ldexp_f32 v5, v6, v5
; VI-NEXT:    v_cvt_f16_f32_e32 v5, v5
; VI-NEXT:    s_movk_i32 s6, 0x7fff
; VI-NEXT:    v_bfi_b32 v5, s6, v5, v3
; VI-NEXT:  .LBB9_16: ; %Flow51
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_movk_i32 s6, 0x7c00
; VI-NEXT:    v_cmp_lg_f16_e32 vcc, 0, v1
; VI-NEXT:    v_cmp_nge_f16_e64 s[4:5], |v0|, s6
; VI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; VI-NEXT:    v_mov_b32_e32 v0, 0x7e00
; VI-NEXT:    v_cndmask_b32_e32 v1, v0, v2, vcc
; VI-NEXT:    v_cmp_lg_f16_e32 vcc, 0, v4
; VI-NEXT:    v_cmp_nge_f16_e64 s[4:5], |v3|, s6
; VI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; VI-NEXT:    v_cndmask_b32_sdwa v0, v0, v5, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: frem_v2f16:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_f32_f16_e64 v4, |v0|
; GFX9-NEXT:    v_cvt_f32_f16_e64 v3, |v1|
; GFX9-NEXT:    ; implicit-def: $vgpr2
; GFX9-NEXT:    v_cmp_ngt_f32_e32 vcc, v4, v3
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:  ; %bb.1: ; %frem.else20
; GFX9-NEXT:    v_and_b32_e32 v2, 0x8000, v0
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, v4, v3
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc
; GFX9-NEXT:    ; implicit-def: $vgpr4
; GFX9-NEXT:    ; implicit-def: $vgpr3
; GFX9-NEXT:  ; %bb.2: ; %Flow54
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB9_8
; GFX9-NEXT:  ; %bb.3: ; %frem.compute19
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v7, v4
; GFX9-NEXT:    v_frexp_mant_f32_e32 v2, v4
; GFX9-NEXT:    v_frexp_mant_f32_e32 v4, v3
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v8, v3
; GFX9-NEXT:    v_ldexp_f32 v3, v4, 1
; GFX9-NEXT:    v_div_scale_f32 v9, s[6:7], v3, v3, 1.0
; GFX9-NEXT:    v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
; GFX9-NEXT:    v_ldexp_f32 v5, v2, 11
; GFX9-NEXT:    v_add_u32_e32 v2, -1, v8
; GFX9-NEXT:    v_xad_u32 v4, v2, -1, v7
; GFX9-NEXT:    v_rcp_f32_e32 v10, v9
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; GFX9-NEXT:    v_fma_f32 v10, v11, v10, v10
; GFX9-NEXT:    v_mul_f32_e32 v11, v6, v10
; GFX9-NEXT:    v_fma_f32 v12, -v9, v11, v6
; GFX9-NEXT:    v_fma_f32 v11, v12, v10, v11
; GFX9-NEXT:    v_fma_f32 v6, -v9, v11, v6
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX9-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v4
; GFX9-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
; GFX9-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; GFX9-NEXT:    s_cbranch_execz .LBB9_7
; GFX9-NEXT:  ; %bb.4: ; %frem.loop_body27.preheader
; GFX9-NEXT:    v_sub_u32_e32 v4, v7, v8
; GFX9-NEXT:    v_add_u32_e32 v4, 11, v4
; GFX9-NEXT:    s_mov_b64 s[8:9], 0
; GFX9-NEXT:  .LBB9_5: ; %frem.loop_body27
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v7, v5
; GFX9-NEXT:    v_mul_f32_e32 v5, v7, v6
; GFX9-NEXT:    v_rndne_f32_e32 v5, v5
; GFX9-NEXT:    v_fma_f32 v5, -v5, v3, v7
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
; GFX9-NEXT:    v_add_f32_e32 v8, v5, v3
; GFX9-NEXT:    v_add_u32_e32 v4, -11, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v4
; GFX9-NEXT:    v_ldexp_f32 v5, v5, 11
; GFX9-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; GFX9-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; GFX9-NEXT:    s_cbranch_execnz .LBB9_5
; GFX9-NEXT:  ; %bb.6: ; %Flow52
; GFX9-NEXT:    s_or_b64 exec, exec, s[8:9]
; GFX9-NEXT:    v_mov_b32_e32 v5, v7
; GFX9-NEXT:  .LBB9_7: ; %Flow53
; GFX9-NEXT:    s_or_b64 exec, exec, s[6:7]
; GFX9-NEXT:    v_add_u32_e32 v4, -10, v4
; GFX9-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX9-NEXT:    v_mul_f32_e32 v5, v4, v6
; GFX9-NEXT:    v_rndne_f32_e32 v5, v5
; GFX9-NEXT:    v_fma_f32 v4, -v5, v3, v4
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; GFX9-NEXT:    v_add_f32_e32 v3, v4, v3
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX9-NEXT:    v_ldexp_f32 v2, v3, v2
; GFX9-NEXT:    v_cvt_f16_f32_e32 v2, v2
; GFX9-NEXT:    s_movk_i32 s6, 0x7fff
; GFX9-NEXT:    v_bfi_b32 v2, s6, v2, v0
; GFX9-NEXT:  .LBB9_8: ; %Flow55
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX9-NEXT:    v_cvt_f32_f16_e64 v6, |v3|
; GFX9-NEXT:    v_cvt_f32_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-NEXT:    ; implicit-def: $vgpr4
; GFX9-NEXT:    v_cmp_ngt_f32_e32 vcc, v6, v5
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:  ; %bb.9: ; %frem.else
; GFX9-NEXT:    v_and_b32_e32 v4, 0x8000, v3
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, v6, v5
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v3, v4, vcc
; GFX9-NEXT:    ; implicit-def: $vgpr6
; GFX9-NEXT:    ; implicit-def: $vgpr5
; GFX9-NEXT:  ; %bb.10: ; %Flow50
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB9_16
; GFX9-NEXT:  ; %bb.11: ; %frem.compute
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v9, v6
; GFX9-NEXT:    v_frexp_mant_f32_e32 v4, v6
; GFX9-NEXT:    v_frexp_mant_f32_e32 v6, v5
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v10, v5
; GFX9-NEXT:    v_ldexp_f32 v5, v6, 1
; GFX9-NEXT:    v_div_scale_f32 v11, s[6:7], v5, v5, 1.0
; GFX9-NEXT:    v_div_scale_f32 v8, vcc, 1.0, v5, 1.0
; GFX9-NEXT:    v_ldexp_f32 v7, v4, 11
; GFX9-NEXT:    v_add_u32_e32 v4, -1, v10
; GFX9-NEXT:    v_xad_u32 v6, v4, -1, v9
; GFX9-NEXT:    v_rcp_f32_e32 v12, v11
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT:    v_fma_f32 v13, -v11, v12, 1.0
; GFX9-NEXT:    v_fma_f32 v12, v13, v12, v12
; GFX9-NEXT:    v_mul_f32_e32 v13, v8, v12
; GFX9-NEXT:    v_fma_f32 v14, -v11, v13, v8
; GFX9-NEXT:    v_fma_f32 v13, v14, v12, v13
; GFX9-NEXT:    v_fma_f32 v8, -v11, v13, v8
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX9-NEXT:    v_div_fmas_f32 v8, v8, v12, v13
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v6
; GFX9-NEXT:    v_div_fixup_f32 v8, v8, v5, 1.0
; GFX9-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; GFX9-NEXT:    s_cbranch_execz .LBB9_15
; GFX9-NEXT:  ; %bb.12: ; %frem.loop_body.preheader
; GFX9-NEXT:    v_sub_u32_e32 v6, v9, v10
; GFX9-NEXT:    v_add_u32_e32 v6, 11, v6
; GFX9-NEXT:    s_mov_b64 s[8:9], 0
; GFX9-NEXT:  .LBB9_13: ; %frem.loop_body
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v9, v7
; GFX9-NEXT:    v_mul_f32_e32 v7, v9, v8
; GFX9-NEXT:    v_rndne_f32_e32 v7, v7
; GFX9-NEXT:    v_fma_f32 v7, -v7, v5, v9
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v7
; GFX9-NEXT:    v_add_f32_e32 v10, v7, v5
; GFX9-NEXT:    v_add_u32_e32 v6, -11, v6
; GFX9-NEXT:    v_cndmask_b32_e32 v7, v7, v10, vcc
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v6
; GFX9-NEXT:    v_ldexp_f32 v7, v7, 11
; GFX9-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; GFX9-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; GFX9-NEXT:    s_cbranch_execnz .LBB9_13
; GFX9-NEXT:  ; %bb.14: ; %Flow
; GFX9-NEXT:    s_or_b64 exec, exec, s[8:9]
; GFX9-NEXT:    v_mov_b32_e32 v7, v9
; GFX9-NEXT:  .LBB9_15: ; %Flow49
; GFX9-NEXT:    s_or_b64 exec, exec, s[6:7]
; GFX9-NEXT:    v_add_u32_e32 v6, -10, v6
; GFX9-NEXT:    v_ldexp_f32 v6, v7, v6
; GFX9-NEXT:    v_mul_f32_e32 v7, v6, v8
; GFX9-NEXT:    v_rndne_f32_e32 v7, v7
; GFX9-NEXT:    v_fma_f32 v6, -v7, v5, v6
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v6
; GFX9-NEXT:    v_add_f32_e32 v5, v6, v5
; GFX9-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc
; GFX9-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX9-NEXT:    v_cvt_f16_f32_e32 v4, v4
; GFX9-NEXT:    s_movk_i32 s6, 0x7fff
; GFX9-NEXT:    v_bfi_b32 v4, s6, v4, v3
; GFX9-NEXT:  .LBB9_16: ; %Flow51
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_movk_i32 s6, 0x7c00
; GFX9-NEXT:    v_cmp_lg_f16_e32 vcc, 0, v1
; GFX9-NEXT:    v_cmp_nge_f16_e64 s[4:5], |v0|, s6
; GFX9-NEXT:    v_mov_b32_e32 v5, 0
; GFX9-NEXT:    s_and_b64 vcc, s[4:5], vcc
; GFX9-NEXT:    v_mov_b32_e32 v0, 0x7e00
; GFX9-NEXT:    v_cmp_lg_f16_sdwa s[4:5], v1, v5 src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT:    v_cmp_nge_f16_e64 s[6:7], |v3|, s6
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc
; GFX9-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX9-NEXT:    s_mov_b32 s4, 0x5040100
; GFX9-NEXT:    v_perm_b32 v0, v0, v2, s4
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: frem_v2f16:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cvt_f32_f16_e64 v4, |v0|
; GFX10-NEXT:    v_cvt_f32_f16_e64 v3, |v1|
; GFX10-NEXT:    ; implicit-def: $vgpr2
; GFX10-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v4, v3
; GFX10-NEXT:    s_and_saveexec_b32 s4, vcc_lo
; GFX10-NEXT:    s_xor_b32 s4, exec_lo, s4
; GFX10-NEXT:  ; %bb.1: ; %frem.else20
; GFX10-NEXT:    v_and_b32_e32 v2, 0x8000, v0
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v4, v3
; GFX10-NEXT:    ; implicit-def: $vgpr4
; GFX10-NEXT:    ; implicit-def: $vgpr3
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc_lo
; GFX10-NEXT:  ; %bb.2: ; %Flow54
; GFX10-NEXT:    s_andn2_saveexec_b32 s4, s4
; GFX10-NEXT:    s_cbranch_execz .LBB9_8
; GFX10-NEXT:  ; %bb.3: ; %frem.compute19
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v7, v4
; GFX10-NEXT:    v_frexp_mant_f32_e32 v2, v4
; GFX10-NEXT:    v_frexp_mant_f32_e32 v4, v3
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v8, v3
; GFX10-NEXT:    v_ldexp_f32 v5, v2, 11
; GFX10-NEXT:    v_ldexp_f32 v3, v4, 1
; GFX10-NEXT:    v_add_nc_u32_e32 v2, -1, v8
; GFX10-NEXT:    v_div_scale_f32 v9, s5, v3, v3, 1.0
; GFX10-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v3, 1.0
; GFX10-NEXT:    v_xad_u32 v4, v2, -1, v7
; GFX10-NEXT:    v_rcp_f32_e32 v10, v9
; GFX10-NEXT:    s_denorm_mode 15
; GFX10-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; GFX10-NEXT:    v_fmac_f32_e32 v10, v11, v10
; GFX10-NEXT:    v_mul_f32_e32 v11, v6, v10
; GFX10-NEXT:    v_fma_f32 v12, -v9, v11, v6
; GFX10-NEXT:    v_fmac_f32_e32 v11, v12, v10
; GFX10-NEXT:    v_fma_f32 v6, -v9, v11, v6
; GFX10-NEXT:    s_denorm_mode 12
; GFX10-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
; GFX10-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 11, v4
; GFX10-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
; GFX10-NEXT:    s_and_saveexec_b32 s5, vcc_lo
; GFX10-NEXT:    s_cbranch_execz .LBB9_7
; GFX10-NEXT:  ; %bb.4: ; %frem.loop_body27.preheader
; GFX10-NEXT:    v_sub_nc_u32_e32 v4, v7, v8
; GFX10-NEXT:    s_mov_b32 s6, 0
; GFX10-NEXT:    v_add_nc_u32_e32 v4, 11, v4
; GFX10-NEXT:  .LBB9_5: ; %frem.loop_body27
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v7, v5
; GFX10-NEXT:    v_add_nc_u32_e32 v4, -11, v4
; GFX10-NEXT:    v_mul_f32_e32 v5, v7, v6
; GFX10-NEXT:    v_rndne_f32_e32 v5, v5
; GFX10-NEXT:    v_fma_f32 v5, -v5, v3, v7
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX10-NEXT:    v_add_f32_e32 v8, v5, v3
; GFX10-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc_lo
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX10-NEXT:    v_ldexp_f32 v5, v5, 11
; GFX10-NEXT:    s_or_b32 s6, vcc_lo, s6
; GFX10-NEXT:    s_andn2_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    s_cbranch_execnz .LBB9_5
; GFX10-NEXT:  ; %bb.6: ; %Flow52
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    v_mov_b32_e32 v5, v7
; GFX10-NEXT:  .LBB9_7: ; %Flow53
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s5
; GFX10-NEXT:    v_add_nc_u32_e32 v4, -10, v4
; GFX10-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX10-NEXT:    v_mul_f32_e32 v5, v4, v6
; GFX10-NEXT:    v_rndne_f32_e32 v5, v5
; GFX10-NEXT:    v_fma_f32 v4, -v5, v3, v4
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX10-NEXT:    v_add_f32_e32 v3, v4, v3
; GFX10-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v2, v3, v2
; GFX10-NEXT:    v_cvt_f16_f32_e32 v2, v2
; GFX10-NEXT:    v_bfi_b32 v2, 0x7fff, v2, v0
; GFX10-NEXT:  .LBB9_8: ; %Flow55
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX10-NEXT:    v_cvt_f32_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT:    ; implicit-def: $vgpr4
; GFX10-NEXT:    v_cvt_f32_f16_e64 v6, |v3|
; GFX10-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v6, v5
; GFX10-NEXT:    s_and_saveexec_b32 s4, vcc_lo
; GFX10-NEXT:    s_xor_b32 s4, exec_lo, s4
; GFX10-NEXT:  ; %bb.9: ; %frem.else
; GFX10-NEXT:    v_and_b32_e32 v4, 0x8000, v3
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v6, v5
; GFX10-NEXT:    ; implicit-def: $vgpr6
; GFX10-NEXT:    ; implicit-def: $vgpr5
; GFX10-NEXT:    v_cndmask_b32_e32 v4, v3, v4, vcc_lo
; GFX10-NEXT:  ; %bb.10: ; %Flow50
; GFX10-NEXT:    s_andn2_saveexec_b32 s4, s4
; GFX10-NEXT:    s_cbranch_execz .LBB9_16
; GFX10-NEXT:  ; %bb.11: ; %frem.compute
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v9, v6
; GFX10-NEXT:    v_frexp_mant_f32_e32 v4, v6
; GFX10-NEXT:    v_frexp_mant_f32_e32 v6, v5
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v10, v5
; GFX10-NEXT:    v_ldexp_f32 v7, v4, 11
; GFX10-NEXT:    v_ldexp_f32 v5, v6, 1
; GFX10-NEXT:    v_add_nc_u32_e32 v4, -1, v10
; GFX10-NEXT:    v_div_scale_f32 v11, s5, v5, v5, 1.0
; GFX10-NEXT:    v_div_scale_f32 v8, vcc_lo, 1.0, v5, 1.0
; GFX10-NEXT:    v_xad_u32 v6, v4, -1, v9
; GFX10-NEXT:    v_rcp_f32_e32 v12, v11
; GFX10-NEXT:    s_denorm_mode 15
; GFX10-NEXT:    v_fma_f32 v13, -v11, v12, 1.0
; GFX10-NEXT:    v_fmac_f32_e32 v12, v13, v12
; GFX10-NEXT:    v_mul_f32_e32 v13, v8, v12
; GFX10-NEXT:    v_fma_f32 v14, -v11, v13, v8
; GFX10-NEXT:    v_fmac_f32_e32 v13, v14, v12
; GFX10-NEXT:    v_fma_f32 v8, -v11, v13, v8
; GFX10-NEXT:    s_denorm_mode 12
; GFX10-NEXT:    v_div_fmas_f32 v8, v8, v12, v13
; GFX10-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 11, v6
; GFX10-NEXT:    v_div_fixup_f32 v8, v8, v5, 1.0
; GFX10-NEXT:    s_and_saveexec_b32 s5, vcc_lo
; GFX10-NEXT:    s_cbranch_execz .LBB9_15
; GFX10-NEXT:  ; %bb.12: ; %frem.loop_body.preheader
; GFX10-NEXT:    v_sub_nc_u32_e32 v6, v9, v10
; GFX10-NEXT:    s_mov_b32 s6, 0
; GFX10-NEXT:    v_add_nc_u32_e32 v6, 11, v6
; GFX10-NEXT:  .LBB9_13: ; %frem.loop_body
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v9, v7
; GFX10-NEXT:    v_add_nc_u32_e32 v6, -11, v6
; GFX10-NEXT:    v_mul_f32_e32 v7, v9, v8
; GFX10-NEXT:    v_rndne_f32_e32 v7, v7
; GFX10-NEXT:    v_fma_f32 v7, -v7, v5, v9
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v7
; GFX10-NEXT:    v_add_f32_e32 v10, v7, v5
; GFX10-NEXT:    v_cndmask_b32_e32 v7, v7, v10, vcc_lo
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX10-NEXT:    v_ldexp_f32 v7, v7, 11
; GFX10-NEXT:    s_or_b32 s6, vcc_lo, s6
; GFX10-NEXT:    s_andn2_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    s_cbranch_execnz .LBB9_13
; GFX10-NEXT:  ; %bb.14: ; %Flow
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    v_mov_b32_e32 v7, v9
; GFX10-NEXT:  .LBB9_15: ; %Flow49
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s5
; GFX10-NEXT:    v_add_nc_u32_e32 v6, -10, v6
; GFX10-NEXT:    v_ldexp_f32 v6, v7, v6
; GFX10-NEXT:    v_mul_f32_e32 v7, v6, v8
; GFX10-NEXT:    v_rndne_f32_e32 v7, v7
; GFX10-NEXT:    v_fma_f32 v6, -v7, v5, v6
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v6
; GFX10-NEXT:    v_add_f32_e32 v5, v6, v5
; GFX10-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX10-NEXT:    v_cvt_f16_f32_e32 v4, v4
; GFX10-NEXT:    v_bfi_b32 v4, 0x7fff, v4, v3
; GFX10-NEXT:  .LBB9_16: ; %Flow51
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v1
; GFX10-NEXT:    v_cmp_nge_f16_e64 s4, |v0|, 0x7c00
; GFX10-NEXT:    v_cmp_nge_f16_e64 s5, |v3|, 0x7c00
; GFX10-NEXT:    s_and_b32 vcc_lo, s4, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
; GFX10-NEXT:    v_mov_b32_e32 v2, 0
; GFX10-NEXT:    v_cmp_lg_f16_sdwa s4, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT:    s_and_b32 vcc_lo, s5, s4
; GFX10-NEXT:    v_cndmask_b32_e32 v1, 0x7e00, v4, vcc_lo
; GFX10-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: frem_v2f16:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v4, |v0.l|
; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v3, |v1.l|
; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_lo16
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cmpx_ngt_f32_e32 v4, v3
; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT:  ; %bb.1: ; %frem.else20
; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0x8000, v0.l
; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v4, v3
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.l, v0.l, v2.l, vcc_lo
; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow54
; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB9_8
; GFX11-TRUE16-NEXT:  ; %bb.3: ; %frem.compute19
; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v7, v4
; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v2, v4
; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v4, v3
; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v8, v3
; GFX11-TRUE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v5, v2, 11
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v3, v4, 1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, -1, v8
; GFX11-TRUE16-NEXT:    v_div_scale_f32 v9, null, v3, v3, 1.0
; GFX11-TRUE16-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v3, 1.0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT:    v_xad_u32 v4, v2, -1, v7
; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v10, v9
; GFX11-TRUE16-NEXT:    s_denorm_mode 15
; GFX11-TRUE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v10, v11, v10
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v11, v6, v10
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v12, -v9, v11, v6
; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v11, v12, v10
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v6, -v9, v11, v6
; GFX11-TRUE16-NEXT:    s_denorm_mode 12
; GFX11-TRUE16-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
; GFX11-TRUE16-NEXT:    v_cmpx_lt_i32_e32 11, v4
; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB9_7
; GFX11-TRUE16-NEXT:  ; %bb.4: ; %frem.loop_body27.preheader
; GFX11-TRUE16-NEXT:    v_sub_nc_u32_e32 v4, v7, v8
; GFX11-TRUE16-NEXT:    s_mov_b32 s2, 0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v4, 11, v4
; GFX11-TRUE16-NEXT:  .LBB9_5: ; %frem.loop_body27
; GFX11-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v7, v5 :: v_dual_add_nc_u32 v4, -11, v4
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v5, v7, v6
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX11-TRUE16-NEXT:    v_fma_f32 v5, -v5, v3, v7
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX11-TRUE16-NEXT:    v_add_f32_e32 v8, v5, v3
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc_lo
; GFX11-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v5, v5, 11
; GFX11-TRUE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX11-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB9_5
; GFX11-TRUE16-NEXT:  ; %bb.6: ; %Flow52
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v5, v7
; GFX11-TRUE16-NEXT:  .LBB9_7: ; %Flow53
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v4, -10, v4
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v5, v4, v6
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX11-TRUE16-NEXT:    v_fma_f32 v4, -v5, v3, v4
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, v4, v3
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v2, v3, v2
; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v2.l, v2
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_bfi_b32 v2, 0x7fff, v2, v0
; GFX11-TRUE16-NEXT:  .LBB9_8: ; %Flow55
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v5, |v0.h|
; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v4, |v1.h|
; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cmpx_ngt_f32_e32 v5, v4
; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT:  ; %bb.9: ; %frem.else
; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0x8000, v0.h
; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v5, v4
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_cndmask_b16 v3.l, v0.h, v2.h, vcc_lo
; GFX11-TRUE16-NEXT:  ; %bb.10: ; %Flow50
; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB9_16
; GFX11-TRUE16-NEXT:  ; %bb.11: ; %frem.compute
; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v8, v5
; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v3, v5
; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v5, v4
; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v9, v4
; GFX11-TRUE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v6, v3, 11
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v4, v5, 1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v3, -1, v9
; GFX11-TRUE16-NEXT:    v_div_scale_f32 v10, null, v4, v4, 1.0
; GFX11-TRUE16-NEXT:    v_div_scale_f32 v7, vcc_lo, 1.0, v4, 1.0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT:    v_xad_u32 v5, v3, -1, v8
; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v11, v10
; GFX11-TRUE16-NEXT:    s_denorm_mode 15
; GFX11-TRUE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT:    v_fma_f32 v12, -v10, v11, 1.0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v11, v12, v11
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v12, v7, v11
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v13, -v10, v12, v7
; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v12, v13, v11
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v7, -v10, v12, v7
; GFX11-TRUE16-NEXT:    s_denorm_mode 12
; GFX11-TRUE16-NEXT:    v_div_fmas_f32 v7, v7, v11, v12
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_div_fixup_f32 v7, v7, v4, 1.0
; GFX11-TRUE16-NEXT:    v_cmpx_lt_i32_e32 11, v5
; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB9_15
; GFX11-TRUE16-NEXT:  ; %bb.12: ; %frem.loop_body.preheader
; GFX11-TRUE16-NEXT:    v_sub_nc_u32_e32 v5, v8, v9
; GFX11-TRUE16-NEXT:    s_mov_b32 s2, 0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v5, 11, v5
; GFX11-TRUE16-NEXT:  .LBB9_13: ; %frem.loop_body
; GFX11-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v8, v6 :: v_dual_add_nc_u32 v5, -11, v5
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v6, v8, v7
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v6, v6
; GFX11-TRUE16-NEXT:    v_fma_f32 v6, -v6, v4, v8
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v6
; GFX11-TRUE16-NEXT:    v_add_f32_e32 v9, v6, v4
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v6, v9, vcc_lo
; GFX11-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v6, v6, 11
; GFX11-TRUE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX11-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB9_13
; GFX11-TRUE16-NEXT:  ; %bb.14: ; %Flow
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v6, v8
; GFX11-TRUE16-NEXT:  .LBB9_15: ; %Flow49
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v5, -10, v5
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v5, v6, v5
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v6, v5, v7
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v6, v6
; GFX11-TRUE16-NEXT:    v_fma_f32 v5, -v6, v4, v5
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX11-TRUE16-NEXT:    v_add_f32_e32 v4, v5, v4
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc_lo
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v3, v4, v3
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v0.h
; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v3.l, v3
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_bfi_b32 v3, 0x7fff, v3, v4
; GFX11-TRUE16-NEXT:  .LBB9_16: ; %Flow51
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v1.l
; GFX11-TRUE16-NEXT:    v_cmp_nge_f16_e64 s0, |v0.l|, 0x7c00
; GFX11-TRUE16-NEXT:    s_and_b32 s0, s0, vcc_lo
; GFX11-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v1.h
; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v2.l, s0
; GFX11-TRUE16-NEXT:    v_cmp_nge_f16_e64 s0, |v0.h|, 0x7c00
; GFX11-TRUE16-NEXT:    s_and_b32 s0, s0, vcc_lo
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, 0x7e00, v3.l, s0
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: frem_v2f16:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v4, |v0|
; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v3, |v1|
; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cmpx_ngt_f32_e32 v4, v3
; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT:  ; %bb.1: ; %frem.else20
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0x8000, v0
; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v4, v3
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr4
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc_lo
; GFX11-FAKE16-NEXT:  ; %bb.2: ; %Flow54
; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB9_8
; GFX11-FAKE16-NEXT:  ; %bb.3: ; %frem.compute19
; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v7, v4
; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v2, v4
; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v4, v3
; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v8, v3
; GFX11-FAKE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v5, v2, 11
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v3, v4, 1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v2, -1, v8
; GFX11-FAKE16-NEXT:    v_div_scale_f32 v9, null, v3, v3, 1.0
; GFX11-FAKE16-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v3, 1.0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT:    v_xad_u32 v4, v2, -1, v7
; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v10, v9
; GFX11-FAKE16-NEXT:    s_denorm_mode 15
; GFX11-FAKE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v10, v11, v10
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v11, v6, v10
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v12, -v9, v11, v6
; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v11, v12, v10
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v6, -v9, v11, v6
; GFX11-FAKE16-NEXT:    s_denorm_mode 12
; GFX11-FAKE16-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
; GFX11-FAKE16-NEXT:    v_cmpx_lt_i32_e32 11, v4
; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB9_7
; GFX11-FAKE16-NEXT:  ; %bb.4: ; %frem.loop_body27.preheader
; GFX11-FAKE16-NEXT:    v_sub_nc_u32_e32 v4, v7, v8
; GFX11-FAKE16-NEXT:    s_mov_b32 s2, 0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, 11, v4
; GFX11-FAKE16-NEXT:  .LBB9_5: ; %frem.loop_body27
; GFX11-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v7, v5 :: v_dual_add_nc_u32 v4, -11, v4
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v5, v7, v6
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX11-FAKE16-NEXT:    v_fma_f32 v5, -v5, v3, v7
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX11-FAKE16-NEXT:    v_add_f32_e32 v8, v5, v3
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc_lo
; GFX11-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v5, v5, 11
; GFX11-FAKE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX11-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB9_5
; GFX11-FAKE16-NEXT:  ; %bb.6: ; %Flow52
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, v7
; GFX11-FAKE16-NEXT:  .LBB9_7: ; %Flow53
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, -10, v4
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v5, v4, v6
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX11-FAKE16-NEXT:    v_fma_f32 v4, -v5, v3, v4
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, v4, v3
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v2, v3, v2
; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v2, v2
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_bfi_b32 v2, 0x7fff, v2, v0
; GFX11-FAKE16-NEXT:  .LBB9_8: ; %Flow55
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v1
; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v7, |v3|
; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v6, |v4|
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cmpx_ngt_f32_e32 v7, v6
; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT:  ; %bb.9: ; %frem.else
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0x8000, v3
; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v7, v6
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v3, v5, vcc_lo
; GFX11-FAKE16-NEXT:  ; %bb.10: ; %Flow50
; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB9_16
; GFX11-FAKE16-NEXT:  ; %bb.11: ; %frem.compute
; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v10, v7
; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v5, v7
; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v7, v6
; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v11, v6
; GFX11-FAKE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v8, v5, 11
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v6, v7, 1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v5, -1, v11
; GFX11-FAKE16-NEXT:    v_div_scale_f32 v12, null, v6, v6, 1.0
; GFX11-FAKE16-NEXT:    v_div_scale_f32 v9, vcc_lo, 1.0, v6, 1.0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT:    v_xad_u32 v7, v5, -1, v10
; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v13, v12
; GFX11-FAKE16-NEXT:    s_denorm_mode 15
; GFX11-FAKE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT:    v_fma_f32 v14, -v12, v13, 1.0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v13, v14, v13
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v14, v9, v13
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v15, -v12, v14, v9
; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v14, v15, v13
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v9, -v12, v14, v9
; GFX11-FAKE16-NEXT:    s_denorm_mode 12
; GFX11-FAKE16-NEXT:    v_div_fmas_f32 v9, v9, v13, v14
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_div_fixup_f32 v9, v9, v6, 1.0
; GFX11-FAKE16-NEXT:    v_cmpx_lt_i32_e32 11, v7
; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB9_15
; GFX11-FAKE16-NEXT:  ; %bb.12: ; %frem.loop_body.preheader
; GFX11-FAKE16-NEXT:    v_sub_nc_u32_e32 v7, v10, v11
; GFX11-FAKE16-NEXT:    s_mov_b32 s2, 0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v7, 11, v7
; GFX11-FAKE16-NEXT:  .LBB9_13: ; %frem.loop_body
; GFX11-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v10, v8 :: v_dual_add_nc_u32 v7, -11, v7
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v8, v10, v9
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v8, v8
; GFX11-FAKE16-NEXT:    v_fma_f32 v8, -v8, v6, v10
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v8
; GFX11-FAKE16-NEXT:    v_add_f32_e32 v11, v8, v6
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v8, v11, vcc_lo
; GFX11-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v7
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v8, v8, 11
; GFX11-FAKE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX11-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB9_13
; GFX11-FAKE16-NEXT:  ; %bb.14: ; %Flow
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, v10
; GFX11-FAKE16-NEXT:  .LBB9_15: ; %Flow49
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v7, -10, v7
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v7, v8, v7
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v8, v7, v9
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v8, v8
; GFX11-FAKE16-NEXT:    v_fma_f32 v7, -v8, v6, v7
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v7
; GFX11-FAKE16-NEXT:    v_add_f32_e32 v6, v7, v6
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v5, v6, v5
; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v5, v5
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_bfi_b32 v5, 0x7fff, v5, v3
; GFX11-FAKE16-NEXT:  .LBB9_16: ; %Flow51
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v1
; GFX11-FAKE16-NEXT:    v_cmp_nge_f16_e64 s0, |v0|, 0x7c00
; GFX11-FAKE16-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX11-FAKE16-NEXT:    v_cmp_nge_f16_e64 s0, |v3|, 0x7c00
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
; GFX11-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v4
; GFX11-FAKE16-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x7e00, v5, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-TRUE16-LABEL: frem_v2f16:
; GFX1150-TRUE16:       ; %bb.0:
; GFX1150-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-TRUE16-NEXT:    v_cvt_f32_f16_e64 v4, |v0.l|
; GFX1150-TRUE16-NEXT:    v_cvt_f32_f16_e64 v3, |v1.l|
; GFX1150-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX1150-TRUE16-NEXT:    ; implicit-def: $vgpr2_lo16
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cmpx_ngt_f32_e32 v4, v3
; GFX1150-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX1150-TRUE16-NEXT:  ; %bb.1: ; %frem.else20
; GFX1150-TRUE16-NEXT:    v_and_b16 v2.l, 0x8000, v0.l
; GFX1150-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v4, v3
; GFX1150-TRUE16-NEXT:    ; implicit-def: $vgpr4
; GFX1150-TRUE16-NEXT:    ; implicit-def: $vgpr3
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v2.l, v0.l, v2.l, vcc_lo
; GFX1150-TRUE16-NEXT:  ; %bb.2: ; %Flow54
; GFX1150-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1150-TRUE16-NEXT:    s_cbranch_execz .LBB9_8
; GFX1150-TRUE16-NEXT:  ; %bb.3: ; %frem.compute19
; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v7, v4
; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v2, v4
; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v4, v3
; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v8, v3
; GFX1150-TRUE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v5, v2, 11
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v3, v4, 1
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v2, -1, v8
; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v9, null, v3, v3, 1.0
; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v3, 1.0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT:    v_xad_u32 v4, v2, -1, v7
; GFX1150-TRUE16-NEXT:    v_rcp_f32_e32 v10, v9
; GFX1150-TRUE16-NEXT:    s_denorm_mode 15
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v10, v11, v10
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v11, v6, v10
; GFX1150-TRUE16-NEXT:    v_fma_f32 v12, -v9, v11, v6
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v11, v12, v10
; GFX1150-TRUE16-NEXT:    v_fma_f32 v6, -v9, v11, v6
; GFX1150-TRUE16-NEXT:    s_denorm_mode 12
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
; GFX1150-TRUE16-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
; GFX1150-TRUE16-NEXT:    v_cmpx_lt_i32_e32 11, v4
; GFX1150-TRUE16-NEXT:    s_cbranch_execz .LBB9_7
; GFX1150-TRUE16-NEXT:  ; %bb.4: ; %frem.loop_body27.preheader
; GFX1150-TRUE16-NEXT:    v_sub_nc_u32_e32 v4, v7, v8
; GFX1150-TRUE16-NEXT:    s_mov_b32 s2, 0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v4, 11, v4
; GFX1150-TRUE16-NEXT:  .LBB9_5: ; %frem.loop_body27
; GFX1150-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_dual_mov_b32 v7, v5 :: v_dual_add_nc_u32 v4, -11, v4
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v5, v7, v6
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX1150-TRUE16-NEXT:    v_fma_f32 v5, -v5, v3, v7
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v8, v5, v3
; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc_lo
; GFX1150-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v5, v5, 11
; GFX1150-TRUE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1150-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1150-TRUE16-NEXT:    s_cbranch_execnz .LBB9_5
; GFX1150-TRUE16-NEXT:  ; %bb.6: ; %Flow52
; GFX1150-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v5, v7
; GFX1150-TRUE16-NEXT:  .LBB9_7: ; %Flow53
; GFX1150-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v4, -10, v4
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v5, v4, v6
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX1150-TRUE16-NEXT:    v_fma_f32 v4, -v5, v3, v4
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v3, v4, v3
; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v2, v3, v2
; GFX1150-TRUE16-NEXT:    v_cvt_f16_f32_e32 v2.l, v2
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_bfi_b32 v2, 0x7fff, v2, v0
; GFX1150-TRUE16-NEXT:  .LBB9_8: ; %Flow55
; GFX1150-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1150-TRUE16-NEXT:    v_cvt_f32_f16_e64 v5, |v0.h|
; GFX1150-TRUE16-NEXT:    v_cvt_f32_f16_e64 v4, |v1.h|
; GFX1150-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX1150-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cmpx_ngt_f32_e32 v5, v4
; GFX1150-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX1150-TRUE16-NEXT:  ; %bb.9: ; %frem.else
; GFX1150-TRUE16-NEXT:    v_and_b16 v2.h, 0x8000, v0.h
; GFX1150-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v5, v4
; GFX1150-TRUE16-NEXT:    ; implicit-def: $vgpr5
; GFX1150-TRUE16-NEXT:    ; implicit-def: $vgpr4
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v3.l, v0.h, v2.h, vcc_lo
; GFX1150-TRUE16-NEXT:  ; %bb.10: ; %Flow50
; GFX1150-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1150-TRUE16-NEXT:    s_cbranch_execz .LBB9_16
; GFX1150-TRUE16-NEXT:  ; %bb.11: ; %frem.compute
; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v8, v5
; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v3, v5
; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v5, v4
; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v9, v4
; GFX1150-TRUE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v6, v3, 11
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v4, v5, 1
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v3, -1, v9
; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v10, null, v4, v4, 1.0
; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v7, vcc_lo, 1.0, v4, 1.0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT:    v_xad_u32 v5, v3, -1, v8
; GFX1150-TRUE16-NEXT:    v_rcp_f32_e32 v11, v10
; GFX1150-TRUE16-NEXT:    s_denorm_mode 15
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fma_f32 v12, -v10, v11, 1.0
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v11, v12, v11
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v12, v7, v11
; GFX1150-TRUE16-NEXT:    v_fma_f32 v13, -v10, v12, v7
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v12, v13, v11
; GFX1150-TRUE16-NEXT:    v_fma_f32 v7, -v10, v12, v7
; GFX1150-TRUE16-NEXT:    s_denorm_mode 12
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_div_fmas_f32 v7, v7, v11, v12
; GFX1150-TRUE16-NEXT:    v_div_fixup_f32 v7, v7, v4, 1.0
; GFX1150-TRUE16-NEXT:    v_cmpx_lt_i32_e32 11, v5
; GFX1150-TRUE16-NEXT:    s_cbranch_execz .LBB9_15
; GFX1150-TRUE16-NEXT:  ; %bb.12: ; %frem.loop_body.preheader
; GFX1150-TRUE16-NEXT:    v_sub_nc_u32_e32 v5, v8, v9
; GFX1150-TRUE16-NEXT:    s_mov_b32 s2, 0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v5, 11, v5
; GFX1150-TRUE16-NEXT:  .LBB9_13: ; %frem.loop_body
; GFX1150-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_dual_mov_b32 v8, v6 :: v_dual_add_nc_u32 v5, -11, v5
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v6, v8, v7
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v6, v6
; GFX1150-TRUE16-NEXT:    v_fma_f32 v6, -v6, v4, v8
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v6
; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v9, v6, v4
; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v6, v9, vcc_lo
; GFX1150-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v6, v6, 11
; GFX1150-TRUE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1150-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1150-TRUE16-NEXT:    s_cbranch_execnz .LBB9_13
; GFX1150-TRUE16-NEXT:  ; %bb.14: ; %Flow
; GFX1150-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v6, v8
; GFX1150-TRUE16-NEXT:  .LBB9_15: ; %Flow49
; GFX1150-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v5, -10, v5
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v5, v6, v5
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v6, v5, v7
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v6, v6
; GFX1150-TRUE16-NEXT:    v_fma_f32 v5, -v6, v4, v5
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v4, v5, v4
; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc_lo
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v3, v4, v3
; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v0.h
; GFX1150-TRUE16-NEXT:    v_cvt_f16_f32_e32 v3.l, v3
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_bfi_b32 v3, 0x7fff, v3, v4
; GFX1150-TRUE16-NEXT:  .LBB9_16: ; %Flow51
; GFX1150-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1150-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v1.l
; GFX1150-TRUE16-NEXT:    v_cmp_nge_f16_e64 s0, |v0.l|, 0x7c00
; GFX1150-TRUE16-NEXT:    s_and_b32 s0, s0, vcc_lo
; GFX1150-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v1.h
; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v2.l, s0
; GFX1150-TRUE16-NEXT:    v_cmp_nge_f16_e64 s0, |v0.h|, 0x7c00
; GFX1150-TRUE16-NEXT:    s_and_b32 s0, s0, vcc_lo
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v0.h, 0x7e00, v3.l, s0
; GFX1150-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-FAKE16-LABEL: frem_v2f16:
; GFX1150-FAKE16:       ; %bb.0:
; GFX1150-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-FAKE16-NEXT:    v_cvt_f32_f16_e64 v4, |v0|
; GFX1150-FAKE16-NEXT:    v_cvt_f32_f16_e64 v3, |v1|
; GFX1150-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX1150-FAKE16-NEXT:    ; implicit-def: $vgpr2
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cmpx_ngt_f32_e32 v4, v3
; GFX1150-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX1150-FAKE16-NEXT:  ; %bb.1: ; %frem.else20
; GFX1150-FAKE16-NEXT:    v_and_b32_e32 v2, 0x8000, v0
; GFX1150-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v4, v3
; GFX1150-FAKE16-NEXT:    ; implicit-def: $vgpr4
; GFX1150-FAKE16-NEXT:    ; implicit-def: $vgpr3
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc_lo
; GFX1150-FAKE16-NEXT:  ; %bb.2: ; %Flow54
; GFX1150-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1150-FAKE16-NEXT:    s_cbranch_execz .LBB9_8
; GFX1150-FAKE16-NEXT:  ; %bb.3: ; %frem.compute19
; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v7, v4
; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v2, v4
; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v4, v3
; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v8, v3
; GFX1150-FAKE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v5, v2, 11
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v3, v4, 1
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v2, -1, v8
; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v9, null, v3, v3, 1.0
; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v3, 1.0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT:    v_xad_u32 v4, v2, -1, v7
; GFX1150-FAKE16-NEXT:    v_rcp_f32_e32 v10, v9
; GFX1150-FAKE16-NEXT:    s_denorm_mode 15
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v10, v11, v10
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v11, v6, v10
; GFX1150-FAKE16-NEXT:    v_fma_f32 v12, -v9, v11, v6
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v11, v12, v10
; GFX1150-FAKE16-NEXT:    v_fma_f32 v6, -v9, v11, v6
; GFX1150-FAKE16-NEXT:    s_denorm_mode 12
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
; GFX1150-FAKE16-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
; GFX1150-FAKE16-NEXT:    v_cmpx_lt_i32_e32 11, v4
; GFX1150-FAKE16-NEXT:    s_cbranch_execz .LBB9_7
; GFX1150-FAKE16-NEXT:  ; %bb.4: ; %frem.loop_body27.preheader
; GFX1150-FAKE16-NEXT:    v_sub_nc_u32_e32 v4, v7, v8
; GFX1150-FAKE16-NEXT:    s_mov_b32 s2, 0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v4, 11, v4
; GFX1150-FAKE16-NEXT:  .LBB9_5: ; %frem.loop_body27
; GFX1150-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_dual_mov_b32 v7, v5 :: v_dual_add_nc_u32 v4, -11, v4
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v5, v7, v6
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX1150-FAKE16-NEXT:    v_fma_f32 v5, -v5, v3, v7
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v8, v5, v3
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc_lo
; GFX1150-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v5, v5, 11
; GFX1150-FAKE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1150-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1150-FAKE16-NEXT:    s_cbranch_execnz .LBB9_5
; GFX1150-FAKE16-NEXT:  ; %bb.6: ; %Flow52
; GFX1150-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v5, v7
; GFX1150-FAKE16-NEXT:  .LBB9_7: ; %Flow53
; GFX1150-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v4, -10, v4
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v5, v4, v6
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX1150-FAKE16-NEXT:    v_fma_f32 v4, -v5, v3, v4
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v3, v4, v3
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v2, v3, v2
; GFX1150-FAKE16-NEXT:    v_cvt_f16_f32_e32 v2, v2
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_bfi_b32 v2, 0x7fff, v2, v0
; GFX1150-FAKE16-NEXT:  .LBB9_8: ; %Flow55
; GFX1150-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1150-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX1150-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v1
; GFX1150-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX1150-FAKE16-NEXT:    ; implicit-def: $vgpr5
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1150-FAKE16-NEXT:    v_cvt_f32_f16_e64 v7, |v3|
; GFX1150-FAKE16-NEXT:    v_cvt_f32_f16_e64 v6, |v4|
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cmpx_ngt_f32_e32 v7, v6
; GFX1150-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX1150-FAKE16-NEXT:  ; %bb.9: ; %frem.else
; GFX1150-FAKE16-NEXT:    v_and_b32_e32 v5, 0x8000, v3
; GFX1150-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v7, v6
; GFX1150-FAKE16-NEXT:    ; implicit-def: $vgpr7
; GFX1150-FAKE16-NEXT:    ; implicit-def: $vgpr6
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v3, v5, vcc_lo
; GFX1150-FAKE16-NEXT:  ; %bb.10: ; %Flow50
; GFX1150-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1150-FAKE16-NEXT:    s_cbranch_execz .LBB9_16
; GFX1150-FAKE16-NEXT:  ; %bb.11: ; %frem.compute
; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v10, v7
; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v5, v7
; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v7, v6
; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v11, v6
; GFX1150-FAKE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v8, v5, 11
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v6, v7, 1
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v5, -1, v11
; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v12, null, v6, v6, 1.0
; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v9, vcc_lo, 1.0, v6, 1.0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT:    v_xad_u32 v7, v5, -1, v10
; GFX1150-FAKE16-NEXT:    v_rcp_f32_e32 v13, v12
; GFX1150-FAKE16-NEXT:    s_denorm_mode 15
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fma_f32 v14, -v12, v13, 1.0
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v13, v14, v13
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v14, v9, v13
; GFX1150-FAKE16-NEXT:    v_fma_f32 v15, -v12, v14, v9
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v14, v15, v13
; GFX1150-FAKE16-NEXT:    v_fma_f32 v9, -v12, v14, v9
; GFX1150-FAKE16-NEXT:    s_denorm_mode 12
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_div_fmas_f32 v9, v9, v13, v14
; GFX1150-FAKE16-NEXT:    v_div_fixup_f32 v9, v9, v6, 1.0
; GFX1150-FAKE16-NEXT:    v_cmpx_lt_i32_e32 11, v7
; GFX1150-FAKE16-NEXT:    s_cbranch_execz .LBB9_15
; GFX1150-FAKE16-NEXT:  ; %bb.12: ; %frem.loop_body.preheader
; GFX1150-FAKE16-NEXT:    v_sub_nc_u32_e32 v7, v10, v11
; GFX1150-FAKE16-NEXT:    s_mov_b32 s2, 0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v7, 11, v7
; GFX1150-FAKE16-NEXT:  .LBB9_13: ; %frem.loop_body
; GFX1150-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_dual_mov_b32 v10, v8 :: v_dual_add_nc_u32 v7, -11, v7
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v8, v10, v9
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v8, v8
; GFX1150-FAKE16-NEXT:    v_fma_f32 v8, -v8, v6, v10
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v8
; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v11, v8, v6
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v8, v11, vcc_lo
; GFX1150-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v7
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v8, v8, 11
; GFX1150-FAKE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1150-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1150-FAKE16-NEXT:    s_cbranch_execnz .LBB9_13
; GFX1150-FAKE16-NEXT:  ; %bb.14: ; %Flow
; GFX1150-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v8, v10
; GFX1150-FAKE16-NEXT:  .LBB9_15: ; %Flow49
; GFX1150-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v7, -10, v7
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v7, v8, v7
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v8, v7, v9
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v8, v8
; GFX1150-FAKE16-NEXT:    v_fma_f32 v7, -v8, v6, v7
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v7
; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v6, v7, v6
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc_lo
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v5, v6, v5
; GFX1150-FAKE16-NEXT:    v_cvt_f16_f32_e32 v5, v5
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_bfi_b32 v5, 0x7fff, v5, v3
; GFX1150-FAKE16-NEXT:  .LBB9_16: ; %Flow51
; GFX1150-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1150-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v1
; GFX1150-FAKE16-NEXT:    v_cmp_nge_f16_e64 s0, |v0|, 0x7c00
; GFX1150-FAKE16-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1150-FAKE16-NEXT:    v_cmp_nge_f16_e64 s0, |v3|, 0x7c00
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
; GFX1150-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v4
; GFX1150-FAKE16-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x7e00, v5, vcc_lo
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
; GFX1150-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-TRUE16-LABEL: frem_v2f16:
; GFX1200-TRUE16:       ; %bb.0:
; GFX1200-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1200-TRUE16-NEXT:    v_cvt_f32_f16_e64 v4, |v0.l|
; GFX1200-TRUE16-NEXT:    v_cvt_f32_f16_e64 v3, |v1.l|
; GFX1200-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX1200-TRUE16-NEXT:    ; implicit-def: $vgpr2_lo16
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cmpx_ngt_f32_e32 v4, v3
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX1200-TRUE16-NEXT:  ; %bb.1: ; %frem.else20
; GFX1200-TRUE16-NEXT:    v_and_b16 v2.l, 0x8000, v0.l
; GFX1200-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v4, v3
; GFX1200-TRUE16-NEXT:    ; implicit-def: $vgpr4
; GFX1200-TRUE16-NEXT:    ; implicit-def: $vgpr3
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v2.l, v0.l, v2.l, vcc_lo
; GFX1200-TRUE16-NEXT:  ; %bb.2: ; %Flow54
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1200-TRUE16-NEXT:    s_cbranch_execz .LBB9_8
; GFX1200-TRUE16-NEXT:  ; %bb.3: ; %frem.compute19
; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v7, v4
; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v2, v4
; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v4, v3
; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v8, v3
; GFX1200-TRUE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v5, v2, 11
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v3, v4, 1
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v9, null, v3, v3, 1.0
; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v3, 1.0
; GFX1200-TRUE16-NEXT:    v_rcp_f32_e32 v10, v9
; GFX1200-TRUE16-NEXT:    s_denorm_mode 15
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v10, v11, v10
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_dual_mul_f32 v11, v6, v10 :: v_dual_add_nc_u32 v2, -1, v8
; GFX1200-TRUE16-NEXT:    v_xad_u32 v4, v2, -1, v7
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f32 v12, -v9, v11, v6
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v11, v12, v10
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f32 v6, -v9, v11, v6
; GFX1200-TRUE16-NEXT:    s_denorm_mode 12
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
; GFX1200-TRUE16-NEXT:    v_cmpx_lt_i32_e32 11, v4
; GFX1200-TRUE16-NEXT:    s_cbranch_execz .LBB9_7
; GFX1200-TRUE16-NEXT:  ; %bb.4: ; %frem.loop_body27.preheader
; GFX1200-TRUE16-NEXT:    v_sub_nc_u32_e32 v4, v7, v8
; GFX1200-TRUE16-NEXT:    s_mov_b32 s2, 0
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v4, 11, v4
; GFX1200-TRUE16-NEXT:  .LBB9_5: ; %frem.loop_body27
; GFX1200-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_dual_mov_b32 v7, v5 :: v_dual_add_nc_u32 v4, -11, v4
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v5, v7, v6
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX1200-TRUE16-NEXT:    v_fma_f32 v5, -v5, v3, v7
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v8, v5, v3
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc_lo
; GFX1200-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v5, v5, 11
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1200-TRUE16-NEXT:    s_cbranch_execnz .LBB9_5
; GFX1200-TRUE16-NEXT:  ; %bb.6: ; %Flow52
; GFX1200-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v5, v7
; GFX1200-TRUE16-NEXT:  .LBB9_7: ; %Flow53
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v4, -10, v4
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v5, v4, v6
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX1200-TRUE16-NEXT:    v_fma_f32 v4, -v5, v3, v4
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v3, v4, v3
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v2, v3, v2
; GFX1200-TRUE16-NEXT:    v_cvt_f16_f32_e32 v2.l, v2
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_bfi_b32 v2, 0x7fff, v2, v0
; GFX1200-TRUE16-NEXT:  .LBB9_8: ; %Flow55
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1200-TRUE16-NEXT:    v_cvt_f32_f16_e64 v5, |v0.h|
; GFX1200-TRUE16-NEXT:    v_cvt_f32_f16_e64 v4, |v1.h|
; GFX1200-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX1200-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cmpx_ngt_f32_e32 v5, v4
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX1200-TRUE16-NEXT:  ; %bb.9: ; %frem.else
; GFX1200-TRUE16-NEXT:    v_and_b16 v2.h, 0x8000, v0.h
; GFX1200-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v5, v4
; GFX1200-TRUE16-NEXT:    ; implicit-def: $vgpr5
; GFX1200-TRUE16-NEXT:    ; implicit-def: $vgpr4
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v3.l, v0.h, v2.h, vcc_lo
; GFX1200-TRUE16-NEXT:  ; %bb.10: ; %Flow50
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1200-TRUE16-NEXT:    s_cbranch_execz .LBB9_16
; GFX1200-TRUE16-NEXT:  ; %bb.11: ; %frem.compute
; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v8, v5
; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v3, v5
; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v5, v4
; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v9, v4
; GFX1200-TRUE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v6, v3, 11
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v4, v5, 1
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v10, null, v4, v4, 1.0
; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v7, vcc_lo, 1.0, v4, 1.0
; GFX1200-TRUE16-NEXT:    v_rcp_f32_e32 v11, v10
; GFX1200-TRUE16-NEXT:    s_denorm_mode 15
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f32 v12, -v10, v11, 1.0
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v11, v12, v11
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_dual_mul_f32 v12, v7, v11 :: v_dual_add_nc_u32 v3, -1, v9
; GFX1200-TRUE16-NEXT:    v_xad_u32 v5, v3, -1, v8
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f32 v13, -v10, v12, v7
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v12, v13, v11
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f32 v7, -v10, v12, v7
; GFX1200-TRUE16-NEXT:    s_denorm_mode 12
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    v_div_fmas_f32 v7, v7, v11, v12
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_div_fixup_f32 v7, v7, v4, 1.0
; GFX1200-TRUE16-NEXT:    v_cmpx_lt_i32_e32 11, v5
; GFX1200-TRUE16-NEXT:    s_cbranch_execz .LBB9_15
; GFX1200-TRUE16-NEXT:  ; %bb.12: ; %frem.loop_body.preheader
; GFX1200-TRUE16-NEXT:    v_sub_nc_u32_e32 v5, v8, v9
; GFX1200-TRUE16-NEXT:    s_mov_b32 s2, 0
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v5, 11, v5
; GFX1200-TRUE16-NEXT:  .LBB9_13: ; %frem.loop_body
; GFX1200-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_dual_mov_b32 v8, v6 :: v_dual_add_nc_u32 v5, -11, v5
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v6, v8, v7
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v6, v6
; GFX1200-TRUE16-NEXT:    v_fma_f32 v6, -v6, v4, v8
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v6
; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v9, v6, v4
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v6, v9, vcc_lo
; GFX1200-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v6, v6, 11
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1200-TRUE16-NEXT:    s_cbranch_execnz .LBB9_13
; GFX1200-TRUE16-NEXT:  ; %bb.14: ; %Flow
; GFX1200-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v6, v8
; GFX1200-TRUE16-NEXT:  .LBB9_15: ; %Flow49
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v5, -10, v5
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v5, v6, v5
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v6, v5, v7
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v6, v6
; GFX1200-TRUE16-NEXT:    v_fma_f32 v5, -v6, v4, v5
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v4, v5, v4
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc_lo
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v3, v4, v3
; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v0.h
; GFX1200-TRUE16-NEXT:    v_cvt_f16_f32_e32 v3.l, v3
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_bfi_b32 v3, 0x7fff, v3, v4
; GFX1200-TRUE16-NEXT:  .LBB9_16: ; %Flow51
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1200-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v1.l
; GFX1200-TRUE16-NEXT:    v_cmp_nge_f16_e64 s0, |v0.l|, 0x7c00
; GFX1200-TRUE16-NEXT:    s_and_b32 s0, s0, vcc_lo
; GFX1200-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v1.h
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v2.l, s0
; GFX1200-TRUE16-NEXT:    v_cmp_nge_f16_e64 s0, |v0.h|, 0x7c00
; GFX1200-TRUE16-NEXT:    s_and_b32 s0, s0, vcc_lo
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v0.h, 0x7e00, v3.l, s0
; GFX1200-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-FAKE16-LABEL: frem_v2f16:
; GFX1200-FAKE16:       ; %bb.0:
; GFX1200-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1200-FAKE16-NEXT:    v_cvt_f32_f16_e64 v4, |v0|
; GFX1200-FAKE16-NEXT:    v_cvt_f32_f16_e64 v3, |v1|
; GFX1200-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX1200-FAKE16-NEXT:    ; implicit-def: $vgpr2
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cmpx_ngt_f32_e32 v4, v3
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX1200-FAKE16-NEXT:  ; %bb.1: ; %frem.else20
; GFX1200-FAKE16-NEXT:    v_and_b32_e32 v2, 0x8000, v0
; GFX1200-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v4, v3
; GFX1200-FAKE16-NEXT:    ; implicit-def: $vgpr4
; GFX1200-FAKE16-NEXT:    ; implicit-def: $vgpr3
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc_lo
; GFX1200-FAKE16-NEXT:  ; %bb.2: ; %Flow54
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1200-FAKE16-NEXT:    s_cbranch_execz .LBB9_8
; GFX1200-FAKE16-NEXT:  ; %bb.3: ; %frem.compute19
; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v7, v4
; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v2, v4
; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v4, v3
; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v8, v3
; GFX1200-FAKE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v5, v2, 11
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v3, v4, 1
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v9, null, v3, v3, 1.0
; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v3, 1.0
; GFX1200-FAKE16-NEXT:    v_rcp_f32_e32 v10, v9
; GFX1200-FAKE16-NEXT:    s_denorm_mode 15
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v10, v11, v10
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_dual_mul_f32 v11, v6, v10 :: v_dual_add_nc_u32 v2, -1, v8
; GFX1200-FAKE16-NEXT:    v_xad_u32 v4, v2, -1, v7
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f32 v12, -v9, v11, v6
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v11, v12, v10
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f32 v6, -v9, v11, v6
; GFX1200-FAKE16-NEXT:    s_denorm_mode 12
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
; GFX1200-FAKE16-NEXT:    v_cmpx_lt_i32_e32 11, v4
; GFX1200-FAKE16-NEXT:    s_cbranch_execz .LBB9_7
; GFX1200-FAKE16-NEXT:  ; %bb.4: ; %frem.loop_body27.preheader
; GFX1200-FAKE16-NEXT:    v_sub_nc_u32_e32 v4, v7, v8
; GFX1200-FAKE16-NEXT:    s_mov_b32 s2, 0
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v4, 11, v4
; GFX1200-FAKE16-NEXT:  .LBB9_5: ; %frem.loop_body27
; GFX1200-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_dual_mov_b32 v7, v5 :: v_dual_add_nc_u32 v4, -11, v4
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v5, v7, v6
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX1200-FAKE16-NEXT:    v_fma_f32 v5, -v5, v3, v7
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v8, v5, v3
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc_lo
; GFX1200-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v5, v5, 11
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1200-FAKE16-NEXT:    s_cbranch_execnz .LBB9_5
; GFX1200-FAKE16-NEXT:  ; %bb.6: ; %Flow52
; GFX1200-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v5, v7
; GFX1200-FAKE16-NEXT:  .LBB9_7: ; %Flow53
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v4, -10, v4
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v5, v4, v6
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX1200-FAKE16-NEXT:    v_fma_f32 v4, -v5, v3, v4
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v3, v4, v3
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v2, v3, v2
; GFX1200-FAKE16-NEXT:    v_cvt_f16_f32_e32 v2, v2
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_bfi_b32 v2, 0x7fff, v2, v0
; GFX1200-FAKE16-NEXT:  .LBB9_8: ; %Flow55
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1200-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX1200-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v1
; GFX1200-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX1200-FAKE16-NEXT:    ; implicit-def: $vgpr5
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-FAKE16-NEXT:    v_cvt_f32_f16_e64 v7, |v3|
; GFX1200-FAKE16-NEXT:    v_cvt_f32_f16_e64 v6, |v4|
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cmpx_ngt_f32_e32 v7, v6
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX1200-FAKE16-NEXT:  ; %bb.9: ; %frem.else
; GFX1200-FAKE16-NEXT:    v_and_b32_e32 v5, 0x8000, v3
; GFX1200-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v7, v6
; GFX1200-FAKE16-NEXT:    ; implicit-def: $vgpr7
; GFX1200-FAKE16-NEXT:    ; implicit-def: $vgpr6
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v3, v5, vcc_lo
; GFX1200-FAKE16-NEXT:  ; %bb.10: ; %Flow50
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1200-FAKE16-NEXT:    s_cbranch_execz .LBB9_16
; GFX1200-FAKE16-NEXT:  ; %bb.11: ; %frem.compute
; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v10, v7
; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v5, v7
; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v7, v6
; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v11, v6
; GFX1200-FAKE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v8, v5, 11
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v6, v7, 1
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v12, null, v6, v6, 1.0
; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v9, vcc_lo, 1.0, v6, 1.0
; GFX1200-FAKE16-NEXT:    v_rcp_f32_e32 v13, v12
; GFX1200-FAKE16-NEXT:    s_denorm_mode 15
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f32 v14, -v12, v13, 1.0
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v13, v14, v13
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_dual_mul_f32 v14, v9, v13 :: v_dual_add_nc_u32 v5, -1, v11
; GFX1200-FAKE16-NEXT:    v_xad_u32 v7, v5, -1, v10
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f32 v15, -v12, v14, v9
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v14, v15, v13
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f32 v9, -v12, v14, v9
; GFX1200-FAKE16-NEXT:    s_denorm_mode 12
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    v_div_fmas_f32 v9, v9, v13, v14
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_div_fixup_f32 v9, v9, v6, 1.0
; GFX1200-FAKE16-NEXT:    v_cmpx_lt_i32_e32 11, v7
; GFX1200-FAKE16-NEXT:    s_cbranch_execz .LBB9_15
; GFX1200-FAKE16-NEXT:  ; %bb.12: ; %frem.loop_body.preheader
; GFX1200-FAKE16-NEXT:    v_sub_nc_u32_e32 v7, v10, v11
; GFX1200-FAKE16-NEXT:    s_mov_b32 s2, 0
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v7, 11, v7
; GFX1200-FAKE16-NEXT:  .LBB9_13: ; %frem.loop_body
; GFX1200-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_dual_mov_b32 v10, v8 :: v_dual_add_nc_u32 v7, -11, v7
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v8, v10, v9
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v8, v8
; GFX1200-FAKE16-NEXT:    v_fma_f32 v8, -v8, v6, v10
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v8
; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v11, v8, v6
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v8, v11, vcc_lo
; GFX1200-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v7
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v8, v8, 11
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1200-FAKE16-NEXT:    s_cbranch_execnz .LBB9_13
; GFX1200-FAKE16-NEXT:  ; %bb.14: ; %Flow
; GFX1200-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v8, v10
; GFX1200-FAKE16-NEXT:  .LBB9_15: ; %Flow49
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v7, -10, v7
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v7, v8, v7
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v8, v7, v9
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v8, v8
; GFX1200-FAKE16-NEXT:    v_fma_f32 v7, -v8, v6, v7
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v7
; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v6, v7, v6
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc_lo
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v5, v6, v5
; GFX1200-FAKE16-NEXT:    v_cvt_f16_f32_e32 v5, v5
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_bfi_b32 v5, 0x7fff, v5, v3
; GFX1200-FAKE16-NEXT:  .LBB9_16: ; %Flow51
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1200-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v1
; GFX1200-FAKE16-NEXT:    v_cmp_nge_f16_e64 s0, |v0|, 0x7c00
; GFX1200-FAKE16-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1200-FAKE16-NEXT:    v_cmp_nge_f16_e64 s0, |v3|, 0x7c00
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
; GFX1200-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v4
; GFX1200-FAKE16-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x7e00, v5, vcc_lo
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
; GFX1200-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %r2 = frem <2 x half> %in1, %in2
  ret <2 x half> %r2
}

define <4 x half> @frem_v4f16(<4 x half> %in1, <4 x half> %in2) #0 {
; SI-LABEL: frem_v4f16:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cvt_f32_f16_e64 v6, |v0|
; SI-NEXT:    v_cvt_f32_f16_e64 v5, |v2|
; SI-NEXT:    ; implicit-def: $vgpr4
; SI-NEXT:    v_cmp_ngt_f32_e32 vcc, v6, v5
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:  ; %bb.1: ; %frem.else86
; SI-NEXT:    v_and_b32_e32 v4, 0xffff8000, v0
; SI-NEXT:    v_cmp_eq_f32_e32 vcc, v6, v5
; SI-NEXT:    v_cndmask_b32_e32 v4, v0, v4, vcc
; SI-NEXT:    ; implicit-def: $vgpr6
; SI-NEXT:    ; implicit-def: $vgpr5
; SI-NEXT:  ; %bb.2: ; %Flow132
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB10_8
; SI-NEXT:  ; %bb.3: ; %frem.compute85
; SI-NEXT:    s_mov_b32 s6, 0x7f800000
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v6|, s6
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v4, v6
; SI-NEXT:    v_cndmask_b32_e32 v9, 0, v4, vcc
; SI-NEXT:    v_frexp_mant_f32_e32 v4, v6
; SI-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc
; SI-NEXT:    v_ldexp_f32_e64 v6, v4, 11
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v5|, s6
; SI-NEXT:    v_frexp_mant_f32_e32 v4, v5
; SI-NEXT:    v_cndmask_b32_e32 v7, v5, v4, vcc
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v4, v5
; SI-NEXT:    v_ldexp_f32_e64 v5, v7, 1
; SI-NEXT:    v_cndmask_b32_e32 v10, 0, v4, vcc
; SI-NEXT:    v_div_scale_f32 v11, s[6:7], v5, v5, 1.0
; SI-NEXT:    v_add_i32_e32 v4, vcc, -1, v10
; SI-NEXT:    v_rcp_f32_e32 v12, v11
; SI-NEXT:    v_not_b32_e32 v7, v4
; SI-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
; SI-NEXT:    v_div_scale_f32 v8, vcc, 1.0, v5, 1.0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    v_fma_f32 v13, -v11, v12, 1.0
; SI-NEXT:    v_fma_f32 v12, v13, v12, v12
; SI-NEXT:    v_mul_f32_e32 v13, v8, v12
; SI-NEXT:    v_fma_f32 v14, -v11, v13, v8
; SI-NEXT:    v_fma_f32 v13, v14, v12, v13
; SI-NEXT:    v_fma_f32 v8, -v11, v13, v8
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    v_div_fmas_f32 v8, v8, v12, v13
; SI-NEXT:    v_div_fixup_f32 v8, v8, v5, 1.0
; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v7
; SI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; SI-NEXT:    s_cbranch_execz .LBB10_7
; SI-NEXT:  ; %bb.4: ; %frem.loop_body93.preheader
; SI-NEXT:    v_sub_i32_e32 v7, vcc, v9, v10
; SI-NEXT:    v_add_i32_e32 v7, vcc, 11, v7
; SI-NEXT:    s_mov_b64 s[8:9], 0
; SI-NEXT:  .LBB10_5: ; %frem.loop_body93
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v9, v6
; SI-NEXT:    v_mul_f32_e32 v6, v9, v8
; SI-NEXT:    v_rndne_f32_e32 v6, v6
; SI-NEXT:    v_fma_f32 v6, -v6, v5, v9
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v6
; SI-NEXT:    v_add_f32_e32 v10, v6, v5
; SI-NEXT:    v_cndmask_b32_e32 v6, v6, v10, vcc
; SI-NEXT:    v_add_i32_e32 v7, vcc, -11, v7
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v7
; SI-NEXT:    v_ldexp_f32_e64 v6, v6, 11
; SI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; SI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; SI-NEXT:    s_cbranch_execnz .LBB10_5
; SI-NEXT:  ; %bb.6: ; %Flow130
; SI-NEXT:    s_or_b64 exec, exec, s[8:9]
; SI-NEXT:    v_mov_b32_e32 v6, v9
; SI-NEXT:  .LBB10_7: ; %Flow131
; SI-NEXT:    s_or_b64 exec, exec, s[6:7]
; SI-NEXT:    v_add_i32_e32 v7, vcc, -10, v7
; SI-NEXT:    v_ldexp_f32_e32 v6, v6, v7
; SI-NEXT:    v_mul_f32_e32 v7, v6, v8
; SI-NEXT:    v_rndne_f32_e32 v7, v7
; SI-NEXT:    v_fma_f32 v6, -v7, v5, v6
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v6
; SI-NEXT:    v_add_f32_e32 v5, v6, v5
; SI-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc
; SI-NEXT:    v_ldexp_f32_e32 v4, v5, v4
; SI-NEXT:    v_cvt_f16_f32_e32 v4, v4
; SI-NEXT:    s_movk_i32 s6, 0x7fff
; SI-NEXT:    v_bfi_b32 v4, s6, v4, v0
; SI-NEXT:  .LBB10_8: ; %Flow133
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    v_lshrrev_b32_e32 v8, 16, v2
; SI-NEXT:    v_lshrrev_b32_e32 v7, 16, v0
; SI-NEXT:    v_cvt_f32_f16_e64 v11, |v7|
; SI-NEXT:    v_cvt_f32_f16_e64 v10, |v8|
; SI-NEXT:    v_lshrrev_b32_e32 v6, 16, v3
; SI-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
; SI-NEXT:    ; implicit-def: $vgpr9
; SI-NEXT:    v_cmp_ngt_f32_e32 vcc, v11, v10
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:  ; %bb.9: ; %frem.else53
; SI-NEXT:    v_and_b32_e32 v9, 0x8000, v7
; SI-NEXT:    v_cmp_eq_f32_e32 vcc, v11, v10
; SI-NEXT:    v_cndmask_b32_e32 v9, v7, v9, vcc
; SI-NEXT:    ; implicit-def: $vgpr11
; SI-NEXT:    ; implicit-def: $vgpr10
; SI-NEXT:  ; %bb.10: ; %Flow128
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB10_16
; SI-NEXT:  ; %bb.11: ; %frem.compute52
; SI-NEXT:    s_mov_b32 s6, 0x7f800000
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v11|, s6
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v9, v11
; SI-NEXT:    v_cndmask_b32_e32 v14, 0, v9, vcc
; SI-NEXT:    v_frexp_mant_f32_e32 v9, v11
; SI-NEXT:    v_cndmask_b32_e32 v9, v11, v9, vcc
; SI-NEXT:    v_ldexp_f32_e64 v11, v9, 11
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v10|, s6
; SI-NEXT:    v_frexp_mant_f32_e32 v9, v10
; SI-NEXT:    v_cndmask_b32_e32 v12, v10, v9, vcc
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v9, v10
; SI-NEXT:    v_ldexp_f32_e64 v10, v12, 1
; SI-NEXT:    v_cndmask_b32_e32 v15, 0, v9, vcc
; SI-NEXT:    v_div_scale_f32 v16, s[6:7], v10, v10, 1.0
; SI-NEXT:    v_add_i32_e32 v9, vcc, -1, v15
; SI-NEXT:    v_rcp_f32_e32 v17, v16
; SI-NEXT:    v_not_b32_e32 v12, v9
; SI-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
; SI-NEXT:    v_div_scale_f32 v13, vcc, 1.0, v10, 1.0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    v_fma_f32 v18, -v16, v17, 1.0
; SI-NEXT:    v_fma_f32 v17, v18, v17, v17
; SI-NEXT:    v_mul_f32_e32 v18, v13, v17
; SI-NEXT:    v_fma_f32 v19, -v16, v18, v13
; SI-NEXT:    v_fma_f32 v18, v19, v17, v18
; SI-NEXT:    v_fma_f32 v13, -v16, v18, v13
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    v_div_fmas_f32 v13, v13, v17, v18
; SI-NEXT:    v_div_fixup_f32 v13, v13, v10, 1.0
; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v12
; SI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; SI-NEXT:    s_cbranch_execz .LBB10_15
; SI-NEXT:  ; %bb.12: ; %frem.loop_body60.preheader
; SI-NEXT:    v_sub_i32_e32 v12, vcc, v14, v15
; SI-NEXT:    v_add_i32_e32 v12, vcc, 11, v12
; SI-NEXT:    s_mov_b64 s[8:9], 0
; SI-NEXT:  .LBB10_13: ; %frem.loop_body60
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v14, v11
; SI-NEXT:    v_mul_f32_e32 v11, v14, v13
; SI-NEXT:    v_rndne_f32_e32 v11, v11
; SI-NEXT:    v_fma_f32 v11, -v11, v10, v14
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v11
; SI-NEXT:    v_add_f32_e32 v15, v11, v10
; SI-NEXT:    v_cndmask_b32_e32 v11, v11, v15, vcc
; SI-NEXT:    v_add_i32_e32 v12, vcc, -11, v12
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v12
; SI-NEXT:    v_ldexp_f32_e64 v11, v11, 11
; SI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; SI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; SI-NEXT:    s_cbranch_execnz .LBB10_13
; SI-NEXT:  ; %bb.14: ; %Flow126
; SI-NEXT:    s_or_b64 exec, exec, s[8:9]
; SI-NEXT:    v_mov_b32_e32 v11, v14
; SI-NEXT:  .LBB10_15: ; %Flow127
; SI-NEXT:    s_or_b64 exec, exec, s[6:7]
; SI-NEXT:    v_add_i32_e32 v12, vcc, -10, v12
; SI-NEXT:    v_ldexp_f32_e32 v11, v11, v12
; SI-NEXT:    v_mul_f32_e32 v12, v11, v13
; SI-NEXT:    v_rndne_f32_e32 v12, v12
; SI-NEXT:    v_fma_f32 v11, -v12, v10, v11
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v11
; SI-NEXT:    v_add_f32_e32 v10, v11, v10
; SI-NEXT:    v_cndmask_b32_e32 v10, v11, v10, vcc
; SI-NEXT:    v_ldexp_f32_e32 v9, v10, v9
; SI-NEXT:    v_cvt_f16_f32_e32 v9, v9
; SI-NEXT:    v_and_b32_e32 v10, 0x8000, v7
; SI-NEXT:    v_and_b32_e32 v9, 0x7fff, v9
; SI-NEXT:    v_or_b32_e32 v9, v9, v10
; SI-NEXT:  .LBB10_16: ; %Flow129
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    v_cvt_f32_f16_e64 v12, |v1|
; SI-NEXT:    v_cvt_f32_f16_e64 v11, |v3|
; SI-NEXT:    ; implicit-def: $vgpr10
; SI-NEXT:    v_cmp_ngt_f32_e32 vcc, v12, v11
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:  ; %bb.17: ; %frem.else20
; SI-NEXT:    v_and_b32_e32 v10, 0xffff8000, v1
; SI-NEXT:    v_cmp_eq_f32_e32 vcc, v12, v11
; SI-NEXT:    v_cndmask_b32_e32 v10, v1, v10, vcc
; SI-NEXT:    ; implicit-def: $vgpr12
; SI-NEXT:    ; implicit-def: $vgpr11
; SI-NEXT:  ; %bb.18: ; %Flow124
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB10_24
; SI-NEXT:  ; %bb.19: ; %frem.compute19
; SI-NEXT:    s_mov_b32 s6, 0x7f800000
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v12|, s6
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v10, v12
; SI-NEXT:    v_cndmask_b32_e32 v15, 0, v10, vcc
; SI-NEXT:    v_frexp_mant_f32_e32 v10, v12
; SI-NEXT:    v_cndmask_b32_e32 v10, v12, v10, vcc
; SI-NEXT:    v_ldexp_f32_e64 v12, v10, 11
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v11|, s6
; SI-NEXT:    v_frexp_mant_f32_e32 v10, v11
; SI-NEXT:    v_cndmask_b32_e32 v13, v11, v10, vcc
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v10, v11
; SI-NEXT:    v_ldexp_f32_e64 v11, v13, 1
; SI-NEXT:    v_cndmask_b32_e32 v16, 0, v10, vcc
; SI-NEXT:    v_div_scale_f32 v17, s[6:7], v11, v11, 1.0
; SI-NEXT:    v_add_i32_e32 v10, vcc, -1, v16
; SI-NEXT:    v_rcp_f32_e32 v18, v17
; SI-NEXT:    v_not_b32_e32 v13, v10
; SI-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
; SI-NEXT:    v_div_scale_f32 v14, vcc, 1.0, v11, 1.0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    v_fma_f32 v19, -v17, v18, 1.0
; SI-NEXT:    v_fma_f32 v18, v19, v18, v18
; SI-NEXT:    v_mul_f32_e32 v19, v14, v18
; SI-NEXT:    v_fma_f32 v20, -v17, v19, v14
; SI-NEXT:    v_fma_f32 v19, v20, v18, v19
; SI-NEXT:    v_fma_f32 v14, -v17, v19, v14
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    v_div_fmas_f32 v14, v14, v18, v19
; SI-NEXT:    v_div_fixup_f32 v14, v14, v11, 1.0
; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v13
; SI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; SI-NEXT:    s_cbranch_execz .LBB10_23
; SI-NEXT:  ; %bb.20: ; %frem.loop_body27.preheader
; SI-NEXT:    v_sub_i32_e32 v13, vcc, v15, v16
; SI-NEXT:    v_add_i32_e32 v13, vcc, 11, v13
; SI-NEXT:    s_mov_b64 s[8:9], 0
; SI-NEXT:  .LBB10_21: ; %frem.loop_body27
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v15, v12
; SI-NEXT:    v_mul_f32_e32 v12, v15, v14
; SI-NEXT:    v_rndne_f32_e32 v12, v12
; SI-NEXT:    v_fma_f32 v12, -v12, v11, v15
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v12
; SI-NEXT:    v_add_f32_e32 v16, v12, v11
; SI-NEXT:    v_cndmask_b32_e32 v12, v12, v16, vcc
; SI-NEXT:    v_add_i32_e32 v13, vcc, -11, v13
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v13
; SI-NEXT:    v_ldexp_f32_e64 v12, v12, 11
; SI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; SI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; SI-NEXT:    s_cbranch_execnz .LBB10_21
; SI-NEXT:  ; %bb.22: ; %Flow122
; SI-NEXT:    s_or_b64 exec, exec, s[8:9]
; SI-NEXT:    v_mov_b32_e32 v12, v15
; SI-NEXT:  .LBB10_23: ; %Flow123
; SI-NEXT:    s_or_b64 exec, exec, s[6:7]
; SI-NEXT:    v_add_i32_e32 v13, vcc, -10, v13
; SI-NEXT:    v_ldexp_f32_e32 v12, v12, v13
; SI-NEXT:    v_mul_f32_e32 v13, v12, v14
; SI-NEXT:    v_rndne_f32_e32 v13, v13
; SI-NEXT:    v_fma_f32 v12, -v13, v11, v12
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v12
; SI-NEXT:    v_add_f32_e32 v11, v12, v11
; SI-NEXT:    v_cndmask_b32_e32 v11, v12, v11, vcc
; SI-NEXT:    v_ldexp_f32_e32 v10, v11, v10
; SI-NEXT:    v_cvt_f16_f32_e32 v10, v10
; SI-NEXT:    s_movk_i32 s6, 0x7fff
; SI-NEXT:    v_bfi_b32 v10, s6, v10, v1
; SI-NEXT:  .LBB10_24: ; %Flow125
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    v_cvt_f32_f16_e64 v13, |v5|
; SI-NEXT:    v_cvt_f32_f16_e64 v12, |v6|
; SI-NEXT:    ; implicit-def: $vgpr11
; SI-NEXT:    v_cmp_ngt_f32_e32 vcc, v13, v12
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:  ; %bb.25: ; %frem.else
; SI-NEXT:    v_and_b32_e32 v11, 0x8000, v5
; SI-NEXT:    v_cmp_eq_f32_e32 vcc, v13, v12
; SI-NEXT:    v_cndmask_b32_e32 v11, v5, v11, vcc
; SI-NEXT:    ; implicit-def: $vgpr13
; SI-NEXT:    ; implicit-def: $vgpr12
; SI-NEXT:  ; %bb.26: ; %Flow120
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB10_32
; SI-NEXT:  ; %bb.27: ; %frem.compute
; SI-NEXT:    s_mov_b32 s6, 0x7f800000
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v13|, s6
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v11, v13
; SI-NEXT:    v_cndmask_b32_e32 v16, 0, v11, vcc
; SI-NEXT:    v_frexp_mant_f32_e32 v11, v13
; SI-NEXT:    v_cndmask_b32_e32 v11, v13, v11, vcc
; SI-NEXT:    v_ldexp_f32_e64 v13, v11, 11
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v12|, s6
; SI-NEXT:    v_frexp_mant_f32_e32 v11, v12
; SI-NEXT:    v_cndmask_b32_e32 v14, v12, v11, vcc
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v11, v12
; SI-NEXT:    v_ldexp_f32_e64 v12, v14, 1
; SI-NEXT:    v_cndmask_b32_e32 v17, 0, v11, vcc
; SI-NEXT:    v_div_scale_f32 v18, s[6:7], v12, v12, 1.0
; SI-NEXT:    v_add_i32_e32 v11, vcc, -1, v17
; SI-NEXT:    v_rcp_f32_e32 v19, v18
; SI-NEXT:    v_not_b32_e32 v14, v11
; SI-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
; SI-NEXT:    v_div_scale_f32 v15, vcc, 1.0, v12, 1.0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    v_fma_f32 v20, -v18, v19, 1.0
; SI-NEXT:    v_fma_f32 v19, v20, v19, v19
; SI-NEXT:    v_mul_f32_e32 v20, v15, v19
; SI-NEXT:    v_fma_f32 v21, -v18, v20, v15
; SI-NEXT:    v_fma_f32 v20, v21, v19, v20
; SI-NEXT:    v_fma_f32 v15, -v18, v20, v15
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    v_div_fmas_f32 v15, v15, v19, v20
; SI-NEXT:    v_div_fixup_f32 v15, v15, v12, 1.0
; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v14
; SI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; SI-NEXT:    s_cbranch_execz .LBB10_31
; SI-NEXT:  ; %bb.28: ; %frem.loop_body.preheader
; SI-NEXT:    v_sub_i32_e32 v14, vcc, v16, v17
; SI-NEXT:    v_add_i32_e32 v14, vcc, 11, v14
; SI-NEXT:    s_mov_b64 s[8:9], 0
; SI-NEXT:  .LBB10_29: ; %frem.loop_body
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v16, v13
; SI-NEXT:    v_mul_f32_e32 v13, v16, v15
; SI-NEXT:    v_rndne_f32_e32 v13, v13
; SI-NEXT:    v_fma_f32 v13, -v13, v12, v16
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v13
; SI-NEXT:    v_add_f32_e32 v17, v13, v12
; SI-NEXT:    v_cndmask_b32_e32 v13, v13, v17, vcc
; SI-NEXT:    v_add_i32_e32 v14, vcc, -11, v14
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v14
; SI-NEXT:    v_ldexp_f32_e64 v13, v13, 11
; SI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; SI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; SI-NEXT:    s_cbranch_execnz .LBB10_29
; SI-NEXT:  ; %bb.30: ; %Flow
; SI-NEXT:    s_or_b64 exec, exec, s[8:9]
; SI-NEXT:    v_mov_b32_e32 v13, v16
; SI-NEXT:  .LBB10_31: ; %Flow119
; SI-NEXT:    s_or_b64 exec, exec, s[6:7]
; SI-NEXT:    v_add_i32_e32 v14, vcc, -10, v14
; SI-NEXT:    v_ldexp_f32_e32 v13, v13, v14
; SI-NEXT:    v_mul_f32_e32 v14, v13, v15
; SI-NEXT:    v_rndne_f32_e32 v14, v14
; SI-NEXT:    v_fma_f32 v13, -v14, v12, v13
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v13
; SI-NEXT:    v_add_f32_e32 v12, v13, v12
; SI-NEXT:    v_cndmask_b32_e32 v12, v13, v12, vcc
; SI-NEXT:    v_ldexp_f32_e32 v11, v12, v11
; SI-NEXT:    v_cvt_f16_f32_e32 v11, v11
; SI-NEXT:    v_and_b32_e32 v12, 0x8000, v5
; SI-NEXT:    v_and_b32_e32 v11, 0x7fff, v11
; SI-NEXT:    v_or_b32_e32 v11, v11, v12
; SI-NEXT:  .LBB10_32: ; %Flow121
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    v_cvt_f32_f16_e32 v2, v2
; SI-NEXT:    v_cvt_f32_f16_e64 v0, |v0|
; SI-NEXT:    s_mov_b32 s6, 0x7f800000
; SI-NEXT:    v_cvt_f32_f16_e32 v3, v3
; SI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v2
; SI-NEXT:    v_cmp_nle_f32_e64 s[4:5], s6, v0
; SI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; SI-NEXT:    v_mov_b32_e32 v0, 0x7e00
; SI-NEXT:    v_cndmask_b32_e32 v2, v0, v4, vcc
; SI-NEXT:    v_cvt_f32_f16_e32 v4, v8
; SI-NEXT:    v_cvt_f32_f16_e64 v1, |v1|
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v4
; SI-NEXT:    v_cvt_f32_f16_e64 v4, |v7|
; SI-NEXT:    v_cmp_nle_f32_e64 s[4:5], s6, v4
; SI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; SI-NEXT:    v_cndmask_b32_e32 v4, v0, v9, vcc
; SI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v3, v6
; SI-NEXT:    v_cmp_nle_f32_e64 s[4:5], s6, v1
; SI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; SI-NEXT:    v_cndmask_b32_e32 v1, v0, v10, vcc
; SI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v3
; SI-NEXT:    v_cvt_f32_f16_e64 v3, |v5|
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_cmp_nle_f32_e64 s[4:5], s6, v3
; SI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; SI-NEXT:    v_cndmask_b32_e32 v3, v0, v11, vcc
; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v4
; SI-NEXT:    v_or_b32_e32 v0, v2, v0
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v3
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; CI-LABEL: frem_v4f16:
; CI:       ; %bb.0:
; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-NEXT:    v_cvt_f32_f16_e64 v6, |v0|
; CI-NEXT:    v_cvt_f32_f16_e64 v5, |v2|
; CI-NEXT:    ; implicit-def: $vgpr4
; CI-NEXT:    v_cmp_ngt_f32_e32 vcc, v6, v5
; CI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; CI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; CI-NEXT:  ; %bb.1: ; %frem.else86
; CI-NEXT:    v_and_b32_e32 v4, 0xffff8000, v0
; CI-NEXT:    v_cmp_eq_f32_e32 vcc, v6, v5
; CI-NEXT:    v_cndmask_b32_e32 v4, v0, v4, vcc
; CI-NEXT:    ; implicit-def: $vgpr6
; CI-NEXT:    ; implicit-def: $vgpr5
; CI-NEXT:  ; %bb.2: ; %Flow132
; CI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; CI-NEXT:    s_cbranch_execz .LBB10_8
; CI-NEXT:  ; %bb.3: ; %frem.compute85
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v9, v6
; CI-NEXT:    v_frexp_mant_f32_e32 v4, v6
; CI-NEXT:    v_frexp_mant_f32_e32 v6, v5
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v10, v5
; CI-NEXT:    v_ldexp_f32_e64 v5, v6, 1
; CI-NEXT:    v_div_scale_f32 v11, s[6:7], v5, v5, 1.0
; CI-NEXT:    v_ldexp_f32_e64 v7, v4, 11
; CI-NEXT:    v_add_i32_e32 v4, vcc, -1, v10
; CI-NEXT:    v_not_b32_e32 v6, v4
; CI-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
; CI-NEXT:    v_div_scale_f32 v8, vcc, 1.0, v5, 1.0
; CI-NEXT:    v_rcp_f32_e32 v12, v11
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v13, -v11, v12, 1.0
; CI-NEXT:    v_fma_f32 v12, v13, v12, v12
; CI-NEXT:    v_mul_f32_e32 v13, v8, v12
; CI-NEXT:    v_fma_f32 v14, -v11, v13, v8
; CI-NEXT:    v_fma_f32 v13, v14, v12, v13
; CI-NEXT:    v_fma_f32 v8, -v11, v13, v8
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v8, v8, v12, v13
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v6
; CI-NEXT:    v_div_fixup_f32 v8, v8, v5, 1.0
; CI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; CI-NEXT:    s_cbranch_execz .LBB10_7
; CI-NEXT:  ; %bb.4: ; %frem.loop_body93.preheader
; CI-NEXT:    v_sub_i32_e32 v6, vcc, v9, v10
; CI-NEXT:    v_add_i32_e32 v6, vcc, 11, v6
; CI-NEXT:    s_mov_b64 s[8:9], 0
; CI-NEXT:  .LBB10_5: ; %frem.loop_body93
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v9, v7
; CI-NEXT:    v_mul_f32_e32 v7, v9, v8
; CI-NEXT:    v_rndne_f32_e32 v7, v7
; CI-NEXT:    v_fma_f32 v7, -v7, v5, v9
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v7
; CI-NEXT:    v_add_f32_e32 v10, v7, v5
; CI-NEXT:    v_cndmask_b32_e32 v7, v7, v10, vcc
; CI-NEXT:    v_add_i32_e32 v6, vcc, -11, v6
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v6
; CI-NEXT:    v_ldexp_f32_e64 v7, v7, 11
; CI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; CI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; CI-NEXT:    s_cbranch_execnz .LBB10_5
; CI-NEXT:  ; %bb.6: ; %Flow130
; CI-NEXT:    s_or_b64 exec, exec, s[8:9]
; CI-NEXT:    v_mov_b32_e32 v7, v9
; CI-NEXT:  .LBB10_7: ; %Flow131
; CI-NEXT:    s_or_b64 exec, exec, s[6:7]
; CI-NEXT:    v_add_i32_e32 v6, vcc, -10, v6
; CI-NEXT:    v_ldexp_f32_e32 v6, v7, v6
; CI-NEXT:    v_mul_f32_e32 v7, v6, v8
; CI-NEXT:    v_rndne_f32_e32 v7, v7
; CI-NEXT:    v_fma_f32 v6, -v7, v5, v6
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v6
; CI-NEXT:    v_add_f32_e32 v5, v6, v5
; CI-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc
; CI-NEXT:    v_ldexp_f32_e32 v4, v5, v4
; CI-NEXT:    v_cvt_f16_f32_e32 v4, v4
; CI-NEXT:    s_movk_i32 s6, 0x7fff
; CI-NEXT:    v_bfi_b32 v4, s6, v4, v0
; CI-NEXT:  .LBB10_8: ; %Flow133
; CI-NEXT:    s_or_b64 exec, exec, s[4:5]
; CI-NEXT:    v_lshrrev_b32_e32 v8, 16, v2
; CI-NEXT:    v_lshrrev_b32_e32 v7, 16, v0
; CI-NEXT:    v_cvt_f32_f16_e64 v11, |v7|
; CI-NEXT:    v_cvt_f32_f16_e64 v10, |v8|
; CI-NEXT:    v_lshrrev_b32_e32 v6, 16, v3
; CI-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
; CI-NEXT:    ; implicit-def: $vgpr9
; CI-NEXT:    v_cmp_ngt_f32_e32 vcc, v11, v10
; CI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; CI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; CI-NEXT:  ; %bb.9: ; %frem.else53
; CI-NEXT:    v_and_b32_e32 v9, 0x8000, v7
; CI-NEXT:    v_cmp_eq_f32_e32 vcc, v11, v10
; CI-NEXT:    v_cndmask_b32_e32 v9, v7, v9, vcc
; CI-NEXT:    ; implicit-def: $vgpr11
; CI-NEXT:    ; implicit-def: $vgpr10
; CI-NEXT:  ; %bb.10: ; %Flow128
; CI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; CI-NEXT:    s_cbranch_execz .LBB10_16
; CI-NEXT:  ; %bb.11: ; %frem.compute52
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v14, v11
; CI-NEXT:    v_frexp_mant_f32_e32 v9, v11
; CI-NEXT:    v_frexp_mant_f32_e32 v11, v10
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v15, v10
; CI-NEXT:    v_ldexp_f32_e64 v10, v11, 1
; CI-NEXT:    v_div_scale_f32 v16, s[6:7], v10, v10, 1.0
; CI-NEXT:    v_ldexp_f32_e64 v12, v9, 11
; CI-NEXT:    v_add_i32_e32 v9, vcc, -1, v15
; CI-NEXT:    v_not_b32_e32 v11, v9
; CI-NEXT:    v_add_i32_e32 v11, vcc, v11, v14
; CI-NEXT:    v_div_scale_f32 v13, vcc, 1.0, v10, 1.0
; CI-NEXT:    v_rcp_f32_e32 v17, v16
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v18, -v16, v17, 1.0
; CI-NEXT:    v_fma_f32 v17, v18, v17, v17
; CI-NEXT:    v_mul_f32_e32 v18, v13, v17
; CI-NEXT:    v_fma_f32 v19, -v16, v18, v13
; CI-NEXT:    v_fma_f32 v18, v19, v17, v18
; CI-NEXT:    v_fma_f32 v13, -v16, v18, v13
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v13, v13, v17, v18
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v11
; CI-NEXT:    v_div_fixup_f32 v13, v13, v10, 1.0
; CI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; CI-NEXT:    s_cbranch_execz .LBB10_15
; CI-NEXT:  ; %bb.12: ; %frem.loop_body60.preheader
; CI-NEXT:    v_sub_i32_e32 v11, vcc, v14, v15
; CI-NEXT:    v_add_i32_e32 v11, vcc, 11, v11
; CI-NEXT:    s_mov_b64 s[8:9], 0
; CI-NEXT:  .LBB10_13: ; %frem.loop_body60
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v14, v12
; CI-NEXT:    v_mul_f32_e32 v12, v14, v13
; CI-NEXT:    v_rndne_f32_e32 v12, v12
; CI-NEXT:    v_fma_f32 v12, -v12, v10, v14
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v12
; CI-NEXT:    v_add_f32_e32 v15, v12, v10
; CI-NEXT:    v_cndmask_b32_e32 v12, v12, v15, vcc
; CI-NEXT:    v_add_i32_e32 v11, vcc, -11, v11
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v11
; CI-NEXT:    v_ldexp_f32_e64 v12, v12, 11
; CI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; CI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; CI-NEXT:    s_cbranch_execnz .LBB10_13
; CI-NEXT:  ; %bb.14: ; %Flow126
; CI-NEXT:    s_or_b64 exec, exec, s[8:9]
; CI-NEXT:    v_mov_b32_e32 v12, v14
; CI-NEXT:  .LBB10_15: ; %Flow127
; CI-NEXT:    s_or_b64 exec, exec, s[6:7]
; CI-NEXT:    v_add_i32_e32 v11, vcc, -10, v11
; CI-NEXT:    v_ldexp_f32_e32 v11, v12, v11
; CI-NEXT:    v_mul_f32_e32 v12, v11, v13
; CI-NEXT:    v_rndne_f32_e32 v12, v12
; CI-NEXT:    v_fma_f32 v11, -v12, v10, v11
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v11
; CI-NEXT:    v_add_f32_e32 v10, v11, v10
; CI-NEXT:    v_cndmask_b32_e32 v10, v11, v10, vcc
; CI-NEXT:    v_ldexp_f32_e32 v9, v10, v9
; CI-NEXT:    v_cvt_f16_f32_e32 v9, v9
; CI-NEXT:    v_and_b32_e32 v10, 0x8000, v7
; CI-NEXT:    v_and_b32_e32 v9, 0x7fff, v9
; CI-NEXT:    v_or_b32_e32 v9, v9, v10
; CI-NEXT:  .LBB10_16: ; %Flow129
; CI-NEXT:    s_or_b64 exec, exec, s[4:5]
; CI-NEXT:    v_cvt_f32_f16_e64 v12, |v1|
; CI-NEXT:    v_cvt_f32_f16_e64 v11, |v3|
; CI-NEXT:    ; implicit-def: $vgpr10
; CI-NEXT:    v_cmp_ngt_f32_e32 vcc, v12, v11
; CI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; CI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; CI-NEXT:  ; %bb.17: ; %frem.else20
; CI-NEXT:    v_and_b32_e32 v10, 0xffff8000, v1
; CI-NEXT:    v_cmp_eq_f32_e32 vcc, v12, v11
; CI-NEXT:    v_cndmask_b32_e32 v10, v1, v10, vcc
; CI-NEXT:    ; implicit-def: $vgpr12
; CI-NEXT:    ; implicit-def: $vgpr11
; CI-NEXT:  ; %bb.18: ; %Flow124
; CI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; CI-NEXT:    s_cbranch_execz .LBB10_24
; CI-NEXT:  ; %bb.19: ; %frem.compute19
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v15, v12
; CI-NEXT:    v_frexp_mant_f32_e32 v10, v12
; CI-NEXT:    v_frexp_mant_f32_e32 v12, v11
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v16, v11
; CI-NEXT:    v_ldexp_f32_e64 v11, v12, 1
; CI-NEXT:    v_div_scale_f32 v17, s[6:7], v11, v11, 1.0
; CI-NEXT:    v_ldexp_f32_e64 v13, v10, 11
; CI-NEXT:    v_add_i32_e32 v10, vcc, -1, v16
; CI-NEXT:    v_not_b32_e32 v12, v10
; CI-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
; CI-NEXT:    v_div_scale_f32 v14, vcc, 1.0, v11, 1.0
; CI-NEXT:    v_rcp_f32_e32 v18, v17
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v19, -v17, v18, 1.0
; CI-NEXT:    v_fma_f32 v18, v19, v18, v18
; CI-NEXT:    v_mul_f32_e32 v19, v14, v18
; CI-NEXT:    v_fma_f32 v20, -v17, v19, v14
; CI-NEXT:    v_fma_f32 v19, v20, v18, v19
; CI-NEXT:    v_fma_f32 v14, -v17, v19, v14
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v14, v14, v18, v19
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v12
; CI-NEXT:    v_div_fixup_f32 v14, v14, v11, 1.0
; CI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; CI-NEXT:    s_cbranch_execz .LBB10_23
; CI-NEXT:  ; %bb.20: ; %frem.loop_body27.preheader
; CI-NEXT:    v_sub_i32_e32 v12, vcc, v15, v16
; CI-NEXT:    v_add_i32_e32 v12, vcc, 11, v12
; CI-NEXT:    s_mov_b64 s[8:9], 0
; CI-NEXT:  .LBB10_21: ; %frem.loop_body27
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v15, v13
; CI-NEXT:    v_mul_f32_e32 v13, v15, v14
; CI-NEXT:    v_rndne_f32_e32 v13, v13
; CI-NEXT:    v_fma_f32 v13, -v13, v11, v15
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v13
; CI-NEXT:    v_add_f32_e32 v16, v13, v11
; CI-NEXT:    v_cndmask_b32_e32 v13, v13, v16, vcc
; CI-NEXT:    v_add_i32_e32 v12, vcc, -11, v12
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v12
; CI-NEXT:    v_ldexp_f32_e64 v13, v13, 11
; CI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; CI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; CI-NEXT:    s_cbranch_execnz .LBB10_21
; CI-NEXT:  ; %bb.22: ; %Flow122
; CI-NEXT:    s_or_b64 exec, exec, s[8:9]
; CI-NEXT:    v_mov_b32_e32 v13, v15
; CI-NEXT:  .LBB10_23: ; %Flow123
; CI-NEXT:    s_or_b64 exec, exec, s[6:7]
; CI-NEXT:    v_add_i32_e32 v12, vcc, -10, v12
; CI-NEXT:    v_ldexp_f32_e32 v12, v13, v12
; CI-NEXT:    v_mul_f32_e32 v13, v12, v14
; CI-NEXT:    v_rndne_f32_e32 v13, v13
; CI-NEXT:    v_fma_f32 v12, -v13, v11, v12
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v12
; CI-NEXT:    v_add_f32_e32 v11, v12, v11
; CI-NEXT:    v_cndmask_b32_e32 v11, v12, v11, vcc
; CI-NEXT:    v_ldexp_f32_e32 v10, v11, v10
; CI-NEXT:    v_cvt_f16_f32_e32 v10, v10
; CI-NEXT:    s_movk_i32 s6, 0x7fff
; CI-NEXT:    v_bfi_b32 v10, s6, v10, v1
; CI-NEXT:  .LBB10_24: ; %Flow125
; CI-NEXT:    s_or_b64 exec, exec, s[4:5]
; CI-NEXT:    v_cvt_f32_f16_e64 v13, |v5|
; CI-NEXT:    v_cvt_f32_f16_e64 v12, |v6|
; CI-NEXT:    ; implicit-def: $vgpr11
; CI-NEXT:    v_cmp_ngt_f32_e32 vcc, v13, v12
; CI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; CI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; CI-NEXT:  ; %bb.25: ; %frem.else
; CI-NEXT:    v_and_b32_e32 v11, 0x8000, v5
; CI-NEXT:    v_cmp_eq_f32_e32 vcc, v13, v12
; CI-NEXT:    v_cndmask_b32_e32 v11, v5, v11, vcc
; CI-NEXT:    ; implicit-def: $vgpr13
; CI-NEXT:    ; implicit-def: $vgpr12
; CI-NEXT:  ; %bb.26: ; %Flow120
; CI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; CI-NEXT:    s_cbranch_execz .LBB10_32
; CI-NEXT:  ; %bb.27: ; %frem.compute
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v16, v13
; CI-NEXT:    v_frexp_mant_f32_e32 v11, v13
; CI-NEXT:    v_frexp_mant_f32_e32 v13, v12
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v17, v12
; CI-NEXT:    v_ldexp_f32_e64 v12, v13, 1
; CI-NEXT:    v_div_scale_f32 v18, s[6:7], v12, v12, 1.0
; CI-NEXT:    v_ldexp_f32_e64 v14, v11, 11
; CI-NEXT:    v_add_i32_e32 v11, vcc, -1, v17
; CI-NEXT:    v_not_b32_e32 v13, v11
; CI-NEXT:    v_add_i32_e32 v13, vcc, v13, v16
; CI-NEXT:    v_div_scale_f32 v15, vcc, 1.0, v12, 1.0
; CI-NEXT:    v_rcp_f32_e32 v19, v18
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v20, -v18, v19, 1.0
; CI-NEXT:    v_fma_f32 v19, v20, v19, v19
; CI-NEXT:    v_mul_f32_e32 v20, v15, v19
; CI-NEXT:    v_fma_f32 v21, -v18, v20, v15
; CI-NEXT:    v_fma_f32 v20, v21, v19, v20
; CI-NEXT:    v_fma_f32 v15, -v18, v20, v15
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v15, v15, v19, v20
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v13
; CI-NEXT:    v_div_fixup_f32 v15, v15, v12, 1.0
; CI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; CI-NEXT:    s_cbranch_execz .LBB10_31
; CI-NEXT:  ; %bb.28: ; %frem.loop_body.preheader
; CI-NEXT:    v_sub_i32_e32 v13, vcc, v16, v17
; CI-NEXT:    v_add_i32_e32 v13, vcc, 11, v13
; CI-NEXT:    s_mov_b64 s[8:9], 0
; CI-NEXT:  .LBB10_29: ; %frem.loop_body
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v16, v14
; CI-NEXT:    v_mul_f32_e32 v14, v16, v15
; CI-NEXT:    v_rndne_f32_e32 v14, v14
; CI-NEXT:    v_fma_f32 v14, -v14, v12, v16
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v14
; CI-NEXT:    v_add_f32_e32 v17, v14, v12
; CI-NEXT:    v_cndmask_b32_e32 v14, v14, v17, vcc
; CI-NEXT:    v_add_i32_e32 v13, vcc, -11, v13
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v13
; CI-NEXT:    v_ldexp_f32_e64 v14, v14, 11
; CI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; CI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; CI-NEXT:    s_cbranch_execnz .LBB10_29
; CI-NEXT:  ; %bb.30: ; %Flow
; CI-NEXT:    s_or_b64 exec, exec, s[8:9]
; CI-NEXT:    v_mov_b32_e32 v14, v16
; CI-NEXT:  .LBB10_31: ; %Flow119
; CI-NEXT:    s_or_b64 exec, exec, s[6:7]
; CI-NEXT:    v_add_i32_e32 v13, vcc, -10, v13
; CI-NEXT:    v_ldexp_f32_e32 v13, v14, v13
; CI-NEXT:    v_mul_f32_e32 v14, v13, v15
; CI-NEXT:    v_rndne_f32_e32 v14, v14
; CI-NEXT:    v_fma_f32 v13, -v14, v12, v13
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v13
; CI-NEXT:    v_add_f32_e32 v12, v13, v12
; CI-NEXT:    v_cndmask_b32_e32 v12, v13, v12, vcc
; CI-NEXT:    v_ldexp_f32_e32 v11, v12, v11
; CI-NEXT:    v_cvt_f16_f32_e32 v11, v11
; CI-NEXT:    v_and_b32_e32 v12, 0x8000, v5
; CI-NEXT:    v_and_b32_e32 v11, 0x7fff, v11
; CI-NEXT:    v_or_b32_e32 v11, v11, v12
; CI-NEXT:  .LBB10_32: ; %Flow121
; CI-NEXT:    s_or_b64 exec, exec, s[4:5]
; CI-NEXT:    v_cvt_f32_f16_e32 v2, v2
; CI-NEXT:    v_cvt_f32_f16_e64 v0, |v0|
; CI-NEXT:    s_mov_b32 s6, 0x7f800000
; CI-NEXT:    v_cvt_f32_f16_e32 v3, v3
; CI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v2
; CI-NEXT:    v_cmp_nle_f32_e64 s[4:5], s6, v0
; CI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; CI-NEXT:    v_mov_b32_e32 v0, 0x7e00
; CI-NEXT:    v_cndmask_b32_e32 v2, v0, v4, vcc
; CI-NEXT:    v_cvt_f32_f16_e32 v4, v8
; CI-NEXT:    v_cvt_f32_f16_e64 v1, |v1|
; CI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; CI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v4
; CI-NEXT:    v_cvt_f32_f16_e64 v4, |v7|
; CI-NEXT:    v_cmp_nle_f32_e64 s[4:5], s6, v4
; CI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; CI-NEXT:    v_cndmask_b32_e32 v4, v0, v9, vcc
; CI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v3
; CI-NEXT:    v_cvt_f32_f16_e32 v3, v6
; CI-NEXT:    v_cmp_nle_f32_e64 s[4:5], s6, v1
; CI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; CI-NEXT:    v_cndmask_b32_e32 v1, v0, v10, vcc
; CI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v3
; CI-NEXT:    v_cvt_f32_f16_e64 v3, |v5|
; CI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; CI-NEXT:    v_cmp_nle_f32_e64 s[4:5], s6, v3
; CI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; CI-NEXT:    v_cndmask_b32_e32 v3, v0, v11, vcc
; CI-NEXT:    v_lshlrev_b32_e32 v0, 16, v4
; CI-NEXT:    v_or_b32_e32 v0, v2, v0
; CI-NEXT:    v_lshlrev_b32_e32 v2, 16, v3
; CI-NEXT:    v_or_b32_e32 v1, v1, v2
; CI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: frem_v4f16:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cvt_f32_f16_e64 v6, |v0|
; VI-NEXT:    v_cvt_f32_f16_e64 v5, |v2|
; VI-NEXT:    ; implicit-def: $vgpr4
; VI-NEXT:    v_cmp_ngt_f32_e32 vcc, v6, v5
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:  ; %bb.1: ; %frem.else86
; VI-NEXT:    v_and_b32_e32 v4, 0x8000, v0
; VI-NEXT:    v_cmp_eq_f32_e32 vcc, v6, v5
; VI-NEXT:    v_cndmask_b32_e32 v4, v0, v4, vcc
; VI-NEXT:    ; implicit-def: $vgpr6
; VI-NEXT:    ; implicit-def: $vgpr5
; VI-NEXT:  ; %bb.2: ; %Flow132
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB10_8
; VI-NEXT:  ; %bb.3: ; %frem.compute85
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v9, v6
; VI-NEXT:    v_frexp_mant_f32_e32 v4, v6
; VI-NEXT:    v_frexp_mant_f32_e32 v6, v5
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v10, v5
; VI-NEXT:    v_ldexp_f32 v5, v6, 1
; VI-NEXT:    v_div_scale_f32 v11, s[6:7], v5, v5, 1.0
; VI-NEXT:    v_ldexp_f32 v7, v4, 11
; VI-NEXT:    v_add_u32_e32 v4, vcc, -1, v10
; VI-NEXT:    v_not_b32_e32 v6, v4
; VI-NEXT:    v_add_u32_e32 v6, vcc, v6, v9
; VI-NEXT:    v_div_scale_f32 v8, vcc, 1.0, v5, 1.0
; VI-NEXT:    v_rcp_f32_e32 v12, v11
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT:    v_fma_f32 v13, -v11, v12, 1.0
; VI-NEXT:    v_fma_f32 v12, v13, v12, v12
; VI-NEXT:    v_mul_f32_e32 v13, v8, v12
; VI-NEXT:    v_fma_f32 v14, -v11, v13, v8
; VI-NEXT:    v_fma_f32 v13, v14, v12, v13
; VI-NEXT:    v_fma_f32 v8, -v11, v13, v8
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; VI-NEXT:    v_div_fmas_f32 v8, v8, v12, v13
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v6
; VI-NEXT:    v_div_fixup_f32 v8, v8, v5, 1.0
; VI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; VI-NEXT:    s_cbranch_execz .LBB10_7
; VI-NEXT:  ; %bb.4: ; %frem.loop_body93.preheader
; VI-NEXT:    v_sub_u32_e32 v6, vcc, v9, v10
; VI-NEXT:    v_add_u32_e32 v6, vcc, 11, v6
; VI-NEXT:    s_mov_b64 s[8:9], 0
; VI-NEXT:  .LBB10_5: ; %frem.loop_body93
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v9, v7
; VI-NEXT:    v_mul_f32_e32 v7, v9, v8
; VI-NEXT:    v_rndne_f32_e32 v7, v7
; VI-NEXT:    v_fma_f32 v7, -v7, v5, v9
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v7
; VI-NEXT:    v_add_f32_e32 v10, v7, v5
; VI-NEXT:    v_cndmask_b32_e32 v7, v7, v10, vcc
; VI-NEXT:    v_add_u32_e32 v6, vcc, -11, v6
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v6
; VI-NEXT:    v_ldexp_f32 v7, v7, 11
; VI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; VI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; VI-NEXT:    s_cbranch_execnz .LBB10_5
; VI-NEXT:  ; %bb.6: ; %Flow130
; VI-NEXT:    s_or_b64 exec, exec, s[8:9]
; VI-NEXT:    v_mov_b32_e32 v7, v9
; VI-NEXT:  .LBB10_7: ; %Flow131
; VI-NEXT:    s_or_b64 exec, exec, s[6:7]
; VI-NEXT:    v_add_u32_e32 v6, vcc, -10, v6
; VI-NEXT:    v_ldexp_f32 v6, v7, v6
; VI-NEXT:    v_mul_f32_e32 v7, v6, v8
; VI-NEXT:    v_rndne_f32_e32 v7, v7
; VI-NEXT:    v_fma_f32 v6, -v7, v5, v6
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v6
; VI-NEXT:    v_add_f32_e32 v5, v6, v5
; VI-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc
; VI-NEXT:    v_ldexp_f32 v4, v5, v4
; VI-NEXT:    v_cvt_f16_f32_e32 v4, v4
; VI-NEXT:    s_movk_i32 s6, 0x7fff
; VI-NEXT:    v_bfi_b32 v4, s6, v4, v0
; VI-NEXT:  .LBB10_8: ; %Flow133
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    v_lshrrev_b32_e32 v5, 16, v0
; VI-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
; VI-NEXT:    v_cvt_f32_f16_e64 v9, |v5|
; VI-NEXT:    v_cvt_f32_f16_e64 v8, |v6|
; VI-NEXT:    ; implicit-def: $vgpr7
; VI-NEXT:    v_cmp_ngt_f32_e32 vcc, v9, v8
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:  ; %bb.9: ; %frem.else53
; VI-NEXT:    v_and_b32_e32 v7, 0x8000, v5
; VI-NEXT:    v_cmp_eq_f32_e32 vcc, v9, v8
; VI-NEXT:    v_cndmask_b32_e32 v7, v5, v7, vcc
; VI-NEXT:    ; implicit-def: $vgpr9
; VI-NEXT:    ; implicit-def: $vgpr8
; VI-NEXT:  ; %bb.10: ; %Flow128
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB10_16
; VI-NEXT:  ; %bb.11: ; %frem.compute52
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v12, v9
; VI-NEXT:    v_frexp_mant_f32_e32 v7, v9
; VI-NEXT:    v_frexp_mant_f32_e32 v9, v8
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v13, v8
; VI-NEXT:    v_ldexp_f32 v8, v9, 1
; VI-NEXT:    v_div_scale_f32 v14, s[6:7], v8, v8, 1.0
; VI-NEXT:    v_ldexp_f32 v10, v7, 11
; VI-NEXT:    v_add_u32_e32 v7, vcc, -1, v13
; VI-NEXT:    v_not_b32_e32 v9, v7
; VI-NEXT:    v_add_u32_e32 v9, vcc, v9, v12
; VI-NEXT:    v_div_scale_f32 v11, vcc, 1.0, v8, 1.0
; VI-NEXT:    v_rcp_f32_e32 v15, v14
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT:    v_fma_f32 v16, -v14, v15, 1.0
; VI-NEXT:    v_fma_f32 v15, v16, v15, v15
; VI-NEXT:    v_mul_f32_e32 v16, v11, v15
; VI-NEXT:    v_fma_f32 v17, -v14, v16, v11
; VI-NEXT:    v_fma_f32 v16, v17, v15, v16
; VI-NEXT:    v_fma_f32 v11, -v14, v16, v11
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; VI-NEXT:    v_div_fmas_f32 v11, v11, v15, v16
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v9
; VI-NEXT:    v_div_fixup_f32 v11, v11, v8, 1.0
; VI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; VI-NEXT:    s_cbranch_execz .LBB10_15
; VI-NEXT:  ; %bb.12: ; %frem.loop_body60.preheader
; VI-NEXT:    v_sub_u32_e32 v9, vcc, v12, v13
; VI-NEXT:    v_add_u32_e32 v9, vcc, 11, v9
; VI-NEXT:    s_mov_b64 s[8:9], 0
; VI-NEXT:  .LBB10_13: ; %frem.loop_body60
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v12, v10
; VI-NEXT:    v_mul_f32_e32 v10, v12, v11
; VI-NEXT:    v_rndne_f32_e32 v10, v10
; VI-NEXT:    v_fma_f32 v10, -v10, v8, v12
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v10
; VI-NEXT:    v_add_f32_e32 v13, v10, v8
; VI-NEXT:    v_cndmask_b32_e32 v10, v10, v13, vcc
; VI-NEXT:    v_add_u32_e32 v9, vcc, -11, v9
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v9
; VI-NEXT:    v_ldexp_f32 v10, v10, 11
; VI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; VI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; VI-NEXT:    s_cbranch_execnz .LBB10_13
; VI-NEXT:  ; %bb.14: ; %Flow126
; VI-NEXT:    s_or_b64 exec, exec, s[8:9]
; VI-NEXT:    v_mov_b32_e32 v10, v12
; VI-NEXT:  .LBB10_15: ; %Flow127
; VI-NEXT:    s_or_b64 exec, exec, s[6:7]
; VI-NEXT:    v_add_u32_e32 v9, vcc, -10, v9
; VI-NEXT:    v_ldexp_f32 v9, v10, v9
; VI-NEXT:    v_mul_f32_e32 v10, v9, v11
; VI-NEXT:    v_rndne_f32_e32 v10, v10
; VI-NEXT:    v_fma_f32 v9, -v10, v8, v9
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v9
; VI-NEXT:    v_add_f32_e32 v8, v9, v8
; VI-NEXT:    v_cndmask_b32_e32 v8, v9, v8, vcc
; VI-NEXT:    v_ldexp_f32 v7, v8, v7
; VI-NEXT:    v_cvt_f16_f32_e32 v7, v7
; VI-NEXT:    s_movk_i32 s6, 0x7fff
; VI-NEXT:    v_bfi_b32 v7, s6, v7, v5
; VI-NEXT:  .LBB10_16: ; %Flow129
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    v_cvt_f32_f16_e64 v10, |v1|
; VI-NEXT:    v_cvt_f32_f16_e64 v9, |v3|
; VI-NEXT:    ; implicit-def: $vgpr8
; VI-NEXT:    v_cmp_ngt_f32_e32 vcc, v10, v9
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:  ; %bb.17: ; %frem.else20
; VI-NEXT:    v_and_b32_e32 v8, 0x8000, v1
; VI-NEXT:    v_cmp_eq_f32_e32 vcc, v10, v9
; VI-NEXT:    v_cndmask_b32_e32 v8, v1, v8, vcc
; VI-NEXT:    ; implicit-def: $vgpr10
; VI-NEXT:    ; implicit-def: $vgpr9
; VI-NEXT:  ; %bb.18: ; %Flow124
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB10_24
; VI-NEXT:  ; %bb.19: ; %frem.compute19
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v13, v10
; VI-NEXT:    v_frexp_mant_f32_e32 v8, v10
; VI-NEXT:    v_frexp_mant_f32_e32 v10, v9
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v14, v9
; VI-NEXT:    v_ldexp_f32 v9, v10, 1
; VI-NEXT:    v_div_scale_f32 v15, s[6:7], v9, v9, 1.0
; VI-NEXT:    v_ldexp_f32 v11, v8, 11
; VI-NEXT:    v_add_u32_e32 v8, vcc, -1, v14
; VI-NEXT:    v_not_b32_e32 v10, v8
; VI-NEXT:    v_add_u32_e32 v10, vcc, v10, v13
; VI-NEXT:    v_div_scale_f32 v12, vcc, 1.0, v9, 1.0
; VI-NEXT:    v_rcp_f32_e32 v16, v15
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT:    v_fma_f32 v17, -v15, v16, 1.0
; VI-NEXT:    v_fma_f32 v16, v17, v16, v16
; VI-NEXT:    v_mul_f32_e32 v17, v12, v16
; VI-NEXT:    v_fma_f32 v18, -v15, v17, v12
; VI-NEXT:    v_fma_f32 v17, v18, v16, v17
; VI-NEXT:    v_fma_f32 v12, -v15, v17, v12
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; VI-NEXT:    v_div_fmas_f32 v12, v12, v16, v17
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v10
; VI-NEXT:    v_div_fixup_f32 v12, v12, v9, 1.0
; VI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; VI-NEXT:    s_cbranch_execz .LBB10_23
; VI-NEXT:  ; %bb.20: ; %frem.loop_body27.preheader
; VI-NEXT:    v_sub_u32_e32 v10, vcc, v13, v14
; VI-NEXT:    v_add_u32_e32 v10, vcc, 11, v10
; VI-NEXT:    s_mov_b64 s[8:9], 0
; VI-NEXT:  .LBB10_21: ; %frem.loop_body27
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v13, v11
; VI-NEXT:    v_mul_f32_e32 v11, v13, v12
; VI-NEXT:    v_rndne_f32_e32 v11, v11
; VI-NEXT:    v_fma_f32 v11, -v11, v9, v13
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v11
; VI-NEXT:    v_add_f32_e32 v14, v11, v9
; VI-NEXT:    v_cndmask_b32_e32 v11, v11, v14, vcc
; VI-NEXT:    v_add_u32_e32 v10, vcc, -11, v10
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v10
; VI-NEXT:    v_ldexp_f32 v11, v11, 11
; VI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; VI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; VI-NEXT:    s_cbranch_execnz .LBB10_21
; VI-NEXT:  ; %bb.22: ; %Flow122
; VI-NEXT:    s_or_b64 exec, exec, s[8:9]
; VI-NEXT:    v_mov_b32_e32 v11, v13
; VI-NEXT:  .LBB10_23: ; %Flow123
; VI-NEXT:    s_or_b64 exec, exec, s[6:7]
; VI-NEXT:    v_add_u32_e32 v10, vcc, -10, v10
; VI-NEXT:    v_ldexp_f32 v10, v11, v10
; VI-NEXT:    v_mul_f32_e32 v11, v10, v12
; VI-NEXT:    v_rndne_f32_e32 v11, v11
; VI-NEXT:    v_fma_f32 v10, -v11, v9, v10
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v10
; VI-NEXT:    v_add_f32_e32 v9, v10, v9
; VI-NEXT:    v_cndmask_b32_e32 v9, v10, v9, vcc
; VI-NEXT:    v_ldexp_f32 v8, v9, v8
; VI-NEXT:    v_cvt_f16_f32_e32 v8, v8
; VI-NEXT:    s_movk_i32 s6, 0x7fff
; VI-NEXT:    v_bfi_b32 v8, s6, v8, v1
; VI-NEXT:  .LBB10_24: ; %Flow125
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    v_lshrrev_b32_e32 v9, 16, v1
; VI-NEXT:    v_lshrrev_b32_e32 v10, 16, v3
; VI-NEXT:    v_cvt_f32_f16_e64 v13, |v9|
; VI-NEXT:    v_cvt_f32_f16_e64 v12, |v10|
; VI-NEXT:    ; implicit-def: $vgpr11
; VI-NEXT:    v_cmp_ngt_f32_e32 vcc, v13, v12
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:  ; %bb.25: ; %frem.else
; VI-NEXT:    v_and_b32_e32 v11, 0x8000, v9
; VI-NEXT:    v_cmp_eq_f32_e32 vcc, v13, v12
; VI-NEXT:    v_cndmask_b32_e32 v11, v9, v11, vcc
; VI-NEXT:    ; implicit-def: $vgpr13
; VI-NEXT:    ; implicit-def: $vgpr12
; VI-NEXT:  ; %bb.26: ; %Flow120
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB10_32
; VI-NEXT:  ; %bb.27: ; %frem.compute
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v16, v13
; VI-NEXT:    v_frexp_mant_f32_e32 v11, v13
; VI-NEXT:    v_frexp_mant_f32_e32 v13, v12
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v17, v12
; VI-NEXT:    v_ldexp_f32 v12, v13, 1
; VI-NEXT:    v_div_scale_f32 v18, s[6:7], v12, v12, 1.0
; VI-NEXT:    v_ldexp_f32 v14, v11, 11
; VI-NEXT:    v_add_u32_e32 v11, vcc, -1, v17
; VI-NEXT:    v_not_b32_e32 v13, v11
; VI-NEXT:    v_add_u32_e32 v13, vcc, v13, v16
; VI-NEXT:    v_div_scale_f32 v15, vcc, 1.0, v12, 1.0
; VI-NEXT:    v_rcp_f32_e32 v19, v18
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT:    v_fma_f32 v20, -v18, v19, 1.0
; VI-NEXT:    v_fma_f32 v19, v20, v19, v19
; VI-NEXT:    v_mul_f32_e32 v20, v15, v19
; VI-NEXT:    v_fma_f32 v21, -v18, v20, v15
; VI-NEXT:    v_fma_f32 v20, v21, v19, v20
; VI-NEXT:    v_fma_f32 v15, -v18, v20, v15
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; VI-NEXT:    v_div_fmas_f32 v15, v15, v19, v20
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v13
; VI-NEXT:    v_div_fixup_f32 v15, v15, v12, 1.0
; VI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; VI-NEXT:    s_cbranch_execz .LBB10_31
; VI-NEXT:  ; %bb.28: ; %frem.loop_body.preheader
; VI-NEXT:    v_sub_u32_e32 v13, vcc, v16, v17
; VI-NEXT:    v_add_u32_e32 v13, vcc, 11, v13
; VI-NEXT:    s_mov_b64 s[8:9], 0
; VI-NEXT:  .LBB10_29: ; %frem.loop_body
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v16, v14
; VI-NEXT:    v_mul_f32_e32 v14, v16, v15
; VI-NEXT:    v_rndne_f32_e32 v14, v14
; VI-NEXT:    v_fma_f32 v14, -v14, v12, v16
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v14
; VI-NEXT:    v_add_f32_e32 v17, v14, v12
; VI-NEXT:    v_cndmask_b32_e32 v14, v14, v17, vcc
; VI-NEXT:    v_add_u32_e32 v13, vcc, -11, v13
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v13
; VI-NEXT:    v_ldexp_f32 v14, v14, 11
; VI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; VI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; VI-NEXT:    s_cbranch_execnz .LBB10_29
; VI-NEXT:  ; %bb.30: ; %Flow
; VI-NEXT:    s_or_b64 exec, exec, s[8:9]
; VI-NEXT:    v_mov_b32_e32 v14, v16
; VI-NEXT:  .LBB10_31: ; %Flow119
; VI-NEXT:    s_or_b64 exec, exec, s[6:7]
; VI-NEXT:    v_add_u32_e32 v13, vcc, -10, v13
; VI-NEXT:    v_ldexp_f32 v13, v14, v13
; VI-NEXT:    v_mul_f32_e32 v14, v13, v15
; VI-NEXT:    v_rndne_f32_e32 v14, v14
; VI-NEXT:    v_fma_f32 v13, -v14, v12, v13
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v13
; VI-NEXT:    v_add_f32_e32 v12, v13, v12
; VI-NEXT:    v_cndmask_b32_e32 v12, v13, v12, vcc
; VI-NEXT:    v_ldexp_f32 v11, v12, v11
; VI-NEXT:    v_cvt_f16_f32_e32 v11, v11
; VI-NEXT:    s_movk_i32 s6, 0x7fff
; VI-NEXT:    v_bfi_b32 v11, s6, v11, v9
; VI-NEXT:  .LBB10_32: ; %Flow121
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_movk_i32 s6, 0x7c00
; VI-NEXT:    v_cmp_lg_f16_e32 vcc, 0, v2
; VI-NEXT:    v_cmp_nge_f16_e64 s[4:5], |v0|, s6
; VI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; VI-NEXT:    v_mov_b32_e32 v0, 0x7e00
; VI-NEXT:    v_cndmask_b32_e32 v2, v0, v4, vcc
; VI-NEXT:    v_cmp_lg_f16_e32 vcc, 0, v6
; VI-NEXT:    v_cmp_nge_f16_e64 s[4:5], |v5|, s6
; VI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; VI-NEXT:    v_cndmask_b32_sdwa v4, v0, v7, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_cmp_lg_f16_e32 vcc, 0, v3
; VI-NEXT:    v_cmp_nge_f16_e64 s[4:5], |v1|, s6
; VI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; VI-NEXT:    v_cndmask_b32_e32 v1, v0, v8, vcc
; VI-NEXT:    v_cmp_lg_f16_e32 vcc, 0, v10
; VI-NEXT:    v_cmp_nge_f16_e64 s[4:5], |v9|, s6
; VI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; VI-NEXT:    v_cndmask_b32_sdwa v3, v0, v11, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_sdwa v0, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT:    v_or_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: frem_v4f16:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_f32_f16_e64 v6, |v0|
; GFX9-NEXT:    v_cvt_f32_f16_e64 v5, |v2|
; GFX9-NEXT:    ; implicit-def: $vgpr4
; GFX9-NEXT:    v_cmp_ngt_f32_e32 vcc, v6, v5
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:  ; %bb.1: ; %frem.else86
; GFX9-NEXT:    v_and_b32_e32 v4, 0x8000, v0
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, v6, v5
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v0, v4, vcc
; GFX9-NEXT:    ; implicit-def: $vgpr6
; GFX9-NEXT:    ; implicit-def: $vgpr5
; GFX9-NEXT:  ; %bb.2: ; %Flow132
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB10_8
; GFX9-NEXT:  ; %bb.3: ; %frem.compute85
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v9, v6
; GFX9-NEXT:    v_frexp_mant_f32_e32 v4, v6
; GFX9-NEXT:    v_frexp_mant_f32_e32 v6, v5
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v10, v5
; GFX9-NEXT:    v_ldexp_f32 v5, v6, 1
; GFX9-NEXT:    v_div_scale_f32 v11, s[6:7], v5, v5, 1.0
; GFX9-NEXT:    v_div_scale_f32 v8, vcc, 1.0, v5, 1.0
; GFX9-NEXT:    v_ldexp_f32 v7, v4, 11
; GFX9-NEXT:    v_add_u32_e32 v4, -1, v10
; GFX9-NEXT:    v_xad_u32 v6, v4, -1, v9
; GFX9-NEXT:    v_rcp_f32_e32 v12, v11
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT:    v_fma_f32 v13, -v11, v12, 1.0
; GFX9-NEXT:    v_fma_f32 v12, v13, v12, v12
; GFX9-NEXT:    v_mul_f32_e32 v13, v8, v12
; GFX9-NEXT:    v_fma_f32 v14, -v11, v13, v8
; GFX9-NEXT:    v_fma_f32 v13, v14, v12, v13
; GFX9-NEXT:    v_fma_f32 v8, -v11, v13, v8
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX9-NEXT:    v_div_fmas_f32 v8, v8, v12, v13
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v6
; GFX9-NEXT:    v_div_fixup_f32 v8, v8, v5, 1.0
; GFX9-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; GFX9-NEXT:    s_cbranch_execz .LBB10_7
; GFX9-NEXT:  ; %bb.4: ; %frem.loop_body93.preheader
; GFX9-NEXT:    v_sub_u32_e32 v6, v9, v10
; GFX9-NEXT:    v_add_u32_e32 v6, 11, v6
; GFX9-NEXT:    s_mov_b64 s[8:9], 0
; GFX9-NEXT:  .LBB10_5: ; %frem.loop_body93
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v9, v7
; GFX9-NEXT:    v_mul_f32_e32 v7, v9, v8
; GFX9-NEXT:    v_rndne_f32_e32 v7, v7
; GFX9-NEXT:    v_fma_f32 v7, -v7, v5, v9
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v7
; GFX9-NEXT:    v_add_f32_e32 v10, v7, v5
; GFX9-NEXT:    v_add_u32_e32 v6, -11, v6
; GFX9-NEXT:    v_cndmask_b32_e32 v7, v7, v10, vcc
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v6
; GFX9-NEXT:    v_ldexp_f32 v7, v7, 11
; GFX9-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; GFX9-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; GFX9-NEXT:    s_cbranch_execnz .LBB10_5
; GFX9-NEXT:  ; %bb.6: ; %Flow130
; GFX9-NEXT:    s_or_b64 exec, exec, s[8:9]
; GFX9-NEXT:    v_mov_b32_e32 v7, v9
; GFX9-NEXT:  .LBB10_7: ; %Flow131
; GFX9-NEXT:    s_or_b64 exec, exec, s[6:7]
; GFX9-NEXT:    v_add_u32_e32 v6, -10, v6
; GFX9-NEXT:    v_ldexp_f32 v6, v7, v6
; GFX9-NEXT:    v_mul_f32_e32 v7, v6, v8
; GFX9-NEXT:    v_rndne_f32_e32 v7, v7
; GFX9-NEXT:    v_fma_f32 v6, -v7, v5, v6
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v6
; GFX9-NEXT:    v_add_f32_e32 v5, v6, v5
; GFX9-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc
; GFX9-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX9-NEXT:    v_cvt_f16_f32_e32 v4, v4
; GFX9-NEXT:    s_movk_i32 s6, 0x7fff
; GFX9-NEXT:    v_bfi_b32 v4, s6, v4, v0
; GFX9-NEXT:  .LBB10_8: ; %Flow133
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 16, v0
; GFX9-NEXT:    v_cvt_f32_f16_e64 v8, |v5|
; GFX9-NEXT:    v_cvt_f32_f16_sdwa v7, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-NEXT:    ; implicit-def: $vgpr6
; GFX9-NEXT:    v_cmp_ngt_f32_e32 vcc, v8, v7
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:  ; %bb.9: ; %frem.else53
; GFX9-NEXT:    v_and_b32_e32 v6, 0x8000, v5
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, v8, v7
; GFX9-NEXT:    v_cndmask_b32_e32 v6, v5, v6, vcc
; GFX9-NEXT:    ; implicit-def: $vgpr8
; GFX9-NEXT:    ; implicit-def: $vgpr7
; GFX9-NEXT:  ; %bb.10: ; %Flow128
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB10_16
; GFX9-NEXT:  ; %bb.11: ; %frem.compute52
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v11, v8
; GFX9-NEXT:    v_frexp_mant_f32_e32 v6, v8
; GFX9-NEXT:    v_frexp_mant_f32_e32 v8, v7
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v12, v7
; GFX9-NEXT:    v_ldexp_f32 v7, v8, 1
; GFX9-NEXT:    v_div_scale_f32 v13, s[6:7], v7, v7, 1.0
; GFX9-NEXT:    v_div_scale_f32 v10, vcc, 1.0, v7, 1.0
; GFX9-NEXT:    v_ldexp_f32 v9, v6, 11
; GFX9-NEXT:    v_add_u32_e32 v6, -1, v12
; GFX9-NEXT:    v_xad_u32 v8, v6, -1, v11
; GFX9-NEXT:    v_rcp_f32_e32 v14, v13
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT:    v_fma_f32 v15, -v13, v14, 1.0
; GFX9-NEXT:    v_fma_f32 v14, v15, v14, v14
; GFX9-NEXT:    v_mul_f32_e32 v15, v10, v14
; GFX9-NEXT:    v_fma_f32 v16, -v13, v15, v10
; GFX9-NEXT:    v_fma_f32 v15, v16, v14, v15
; GFX9-NEXT:    v_fma_f32 v10, -v13, v15, v10
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX9-NEXT:    v_div_fmas_f32 v10, v10, v14, v15
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v8
; GFX9-NEXT:    v_div_fixup_f32 v10, v10, v7, 1.0
; GFX9-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; GFX9-NEXT:    s_cbranch_execz .LBB10_15
; GFX9-NEXT:  ; %bb.12: ; %frem.loop_body60.preheader
; GFX9-NEXT:    v_sub_u32_e32 v8, v11, v12
; GFX9-NEXT:    v_add_u32_e32 v8, 11, v8
; GFX9-NEXT:    s_mov_b64 s[8:9], 0
; GFX9-NEXT:  .LBB10_13: ; %frem.loop_body60
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v11, v9
; GFX9-NEXT:    v_mul_f32_e32 v9, v11, v10
; GFX9-NEXT:    v_rndne_f32_e32 v9, v9
; GFX9-NEXT:    v_fma_f32 v9, -v9, v7, v11
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v9
; GFX9-NEXT:    v_add_f32_e32 v12, v9, v7
; GFX9-NEXT:    v_add_u32_e32 v8, -11, v8
; GFX9-NEXT:    v_cndmask_b32_e32 v9, v9, v12, vcc
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v8
; GFX9-NEXT:    v_ldexp_f32 v9, v9, 11
; GFX9-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; GFX9-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; GFX9-NEXT:    s_cbranch_execnz .LBB10_13
; GFX9-NEXT:  ; %bb.14: ; %Flow126
; GFX9-NEXT:    s_or_b64 exec, exec, s[8:9]
; GFX9-NEXT:    v_mov_b32_e32 v9, v11
; GFX9-NEXT:  .LBB10_15: ; %Flow127
; GFX9-NEXT:    s_or_b64 exec, exec, s[6:7]
; GFX9-NEXT:    v_add_u32_e32 v8, -10, v8
; GFX9-NEXT:    v_ldexp_f32 v8, v9, v8
; GFX9-NEXT:    v_mul_f32_e32 v9, v8, v10
; GFX9-NEXT:    v_rndne_f32_e32 v9, v9
; GFX9-NEXT:    v_fma_f32 v8, -v9, v7, v8
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v8
; GFX9-NEXT:    v_add_f32_e32 v7, v8, v7
; GFX9-NEXT:    v_cndmask_b32_e32 v7, v8, v7, vcc
; GFX9-NEXT:    v_ldexp_f32 v6, v7, v6
; GFX9-NEXT:    v_cvt_f16_f32_e32 v6, v6
; GFX9-NEXT:    s_movk_i32 s6, 0x7fff
; GFX9-NEXT:    v_bfi_b32 v6, s6, v6, v5
; GFX9-NEXT:  .LBB10_16: ; %Flow129
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    v_cvt_f32_f16_e64 v9, |v1|
; GFX9-NEXT:    v_cvt_f32_f16_e64 v8, |v3|
; GFX9-NEXT:    ; implicit-def: $vgpr7
; GFX9-NEXT:    v_cmp_ngt_f32_e32 vcc, v9, v8
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:  ; %bb.17: ; %frem.else20
; GFX9-NEXT:    v_and_b32_e32 v7, 0x8000, v1
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, v9, v8
; GFX9-NEXT:    v_cndmask_b32_e32 v7, v1, v7, vcc
; GFX9-NEXT:    ; implicit-def: $vgpr9
; GFX9-NEXT:    ; implicit-def: $vgpr8
; GFX9-NEXT:  ; %bb.18: ; %Flow124
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB10_24
; GFX9-NEXT:  ; %bb.19: ; %frem.compute19
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v12, v9
; GFX9-NEXT:    v_frexp_mant_f32_e32 v7, v9
; GFX9-NEXT:    v_frexp_mant_f32_e32 v9, v8
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v13, v8
; GFX9-NEXT:    v_ldexp_f32 v8, v9, 1
; GFX9-NEXT:    v_div_scale_f32 v14, s[6:7], v8, v8, 1.0
; GFX9-NEXT:    v_div_scale_f32 v11, vcc, 1.0, v8, 1.0
; GFX9-NEXT:    v_ldexp_f32 v10, v7, 11
; GFX9-NEXT:    v_add_u32_e32 v7, -1, v13
; GFX9-NEXT:    v_xad_u32 v9, v7, -1, v12
; GFX9-NEXT:    v_rcp_f32_e32 v15, v14
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT:    v_fma_f32 v16, -v14, v15, 1.0
; GFX9-NEXT:    v_fma_f32 v15, v16, v15, v15
; GFX9-NEXT:    v_mul_f32_e32 v16, v11, v15
; GFX9-NEXT:    v_fma_f32 v17, -v14, v16, v11
; GFX9-NEXT:    v_fma_f32 v16, v17, v15, v16
; GFX9-NEXT:    v_fma_f32 v11, -v14, v16, v11
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX9-NEXT:    v_div_fmas_f32 v11, v11, v15, v16
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v9
; GFX9-NEXT:    v_div_fixup_f32 v11, v11, v8, 1.0
; GFX9-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; GFX9-NEXT:    s_cbranch_execz .LBB10_23
; GFX9-NEXT:  ; %bb.20: ; %frem.loop_body27.preheader
; GFX9-NEXT:    v_sub_u32_e32 v9, v12, v13
; GFX9-NEXT:    v_add_u32_e32 v9, 11, v9
; GFX9-NEXT:    s_mov_b64 s[8:9], 0
; GFX9-NEXT:  .LBB10_21: ; %frem.loop_body27
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v12, v10
; GFX9-NEXT:    v_mul_f32_e32 v10, v12, v11
; GFX9-NEXT:    v_rndne_f32_e32 v10, v10
; GFX9-NEXT:    v_fma_f32 v10, -v10, v8, v12
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v10
; GFX9-NEXT:    v_add_f32_e32 v13, v10, v8
; GFX9-NEXT:    v_add_u32_e32 v9, -11, v9
; GFX9-NEXT:    v_cndmask_b32_e32 v10, v10, v13, vcc
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v9
; GFX9-NEXT:    v_ldexp_f32 v10, v10, 11
; GFX9-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; GFX9-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; GFX9-NEXT:    s_cbranch_execnz .LBB10_21
; GFX9-NEXT:  ; %bb.22: ; %Flow122
; GFX9-NEXT:    s_or_b64 exec, exec, s[8:9]
; GFX9-NEXT:    v_mov_b32_e32 v10, v12
; GFX9-NEXT:  .LBB10_23: ; %Flow123
; GFX9-NEXT:    s_or_b64 exec, exec, s[6:7]
; GFX9-NEXT:    v_add_u32_e32 v9, -10, v9
; GFX9-NEXT:    v_ldexp_f32 v9, v10, v9
; GFX9-NEXT:    v_mul_f32_e32 v10, v9, v11
; GFX9-NEXT:    v_rndne_f32_e32 v10, v10
; GFX9-NEXT:    v_fma_f32 v9, -v10, v8, v9
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v9
; GFX9-NEXT:    v_add_f32_e32 v8, v9, v8
; GFX9-NEXT:    v_cndmask_b32_e32 v8, v9, v8, vcc
; GFX9-NEXT:    v_ldexp_f32 v7, v8, v7
; GFX9-NEXT:    v_cvt_f16_f32_e32 v7, v7
; GFX9-NEXT:    s_movk_i32 s6, 0x7fff
; GFX9-NEXT:    v_bfi_b32 v7, s6, v7, v1
; GFX9-NEXT:  .LBB10_24: ; %Flow125
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    v_lshrrev_b32_e32 v8, 16, v1
; GFX9-NEXT:    v_cvt_f32_f16_e64 v11, |v8|
; GFX9-NEXT:    v_cvt_f32_f16_sdwa v10, |v3| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-NEXT:    ; implicit-def: $vgpr9
; GFX9-NEXT:    v_cmp_ngt_f32_e32 vcc, v11, v10
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:  ; %bb.25: ; %frem.else
; GFX9-NEXT:    v_and_b32_e32 v9, 0x8000, v8
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, v11, v10
; GFX9-NEXT:    v_cndmask_b32_e32 v9, v8, v9, vcc
; GFX9-NEXT:    ; implicit-def: $vgpr11
; GFX9-NEXT:    ; implicit-def: $vgpr10
; GFX9-NEXT:  ; %bb.26: ; %Flow120
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB10_32
; GFX9-NEXT:  ; %bb.27: ; %frem.compute
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v14, v11
; GFX9-NEXT:    v_frexp_mant_f32_e32 v9, v11
; GFX9-NEXT:    v_frexp_mant_f32_e32 v11, v10
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v15, v10
; GFX9-NEXT:    v_ldexp_f32 v10, v11, 1
; GFX9-NEXT:    v_div_scale_f32 v16, s[6:7], v10, v10, 1.0
; GFX9-NEXT:    v_div_scale_f32 v13, vcc, 1.0, v10, 1.0
; GFX9-NEXT:    v_ldexp_f32 v12, v9, 11
; GFX9-NEXT:    v_add_u32_e32 v9, -1, v15
; GFX9-NEXT:    v_xad_u32 v11, v9, -1, v14
; GFX9-NEXT:    v_rcp_f32_e32 v17, v16
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT:    v_fma_f32 v18, -v16, v17, 1.0
; GFX9-NEXT:    v_fma_f32 v17, v18, v17, v17
; GFX9-NEXT:    v_mul_f32_e32 v18, v13, v17
; GFX9-NEXT:    v_fma_f32 v19, -v16, v18, v13
; GFX9-NEXT:    v_fma_f32 v18, v19, v17, v18
; GFX9-NEXT:    v_fma_f32 v13, -v16, v18, v13
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX9-NEXT:    v_div_fmas_f32 v13, v13, v17, v18
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v11
; GFX9-NEXT:    v_div_fixup_f32 v13, v13, v10, 1.0
; GFX9-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; GFX9-NEXT:    s_cbranch_execz .LBB10_31
; GFX9-NEXT:  ; %bb.28: ; %frem.loop_body.preheader
; GFX9-NEXT:    v_sub_u32_e32 v11, v14, v15
; GFX9-NEXT:    v_add_u32_e32 v11, 11, v11
; GFX9-NEXT:    s_mov_b64 s[8:9], 0
; GFX9-NEXT:  .LBB10_29: ; %frem.loop_body
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v14, v12
; GFX9-NEXT:    v_mul_f32_e32 v12, v14, v13
; GFX9-NEXT:    v_rndne_f32_e32 v12, v12
; GFX9-NEXT:    v_fma_f32 v12, -v12, v10, v14
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v12
; GFX9-NEXT:    v_add_f32_e32 v15, v12, v10
; GFX9-NEXT:    v_add_u32_e32 v11, -11, v11
; GFX9-NEXT:    v_cndmask_b32_e32 v12, v12, v15, vcc
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v11
; GFX9-NEXT:    v_ldexp_f32 v12, v12, 11
; GFX9-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; GFX9-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; GFX9-NEXT:    s_cbranch_execnz .LBB10_29
; GFX9-NEXT:  ; %bb.30: ; %Flow
; GFX9-NEXT:    s_or_b64 exec, exec, s[8:9]
; GFX9-NEXT:    v_mov_b32_e32 v12, v14
; GFX9-NEXT:  .LBB10_31: ; %Flow119
; GFX9-NEXT:    s_or_b64 exec, exec, s[6:7]
; GFX9-NEXT:    v_add_u32_e32 v11, -10, v11
; GFX9-NEXT:    v_ldexp_f32 v11, v12, v11
; GFX9-NEXT:    v_mul_f32_e32 v12, v11, v13
; GFX9-NEXT:    v_rndne_f32_e32 v12, v12
; GFX9-NEXT:    v_fma_f32 v11, -v12, v10, v11
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v11
; GFX9-NEXT:    v_add_f32_e32 v10, v11, v10
; GFX9-NEXT:    v_cndmask_b32_e32 v10, v11, v10, vcc
; GFX9-NEXT:    v_ldexp_f32 v9, v10, v9
; GFX9-NEXT:    v_cvt_f16_f32_e32 v9, v9
; GFX9-NEXT:    s_movk_i32 s6, 0x7fff
; GFX9-NEXT:    v_bfi_b32 v9, s6, v9, v8
; GFX9-NEXT:  .LBB10_32: ; %Flow121
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_movk_i32 s8, 0x7c00
; GFX9-NEXT:    v_cmp_lg_f16_e32 vcc, 0, v2
; GFX9-NEXT:    v_cmp_nge_f16_e64 s[4:5], |v0|, s8
; GFX9-NEXT:    v_mov_b32_e32 v10, 0
; GFX9-NEXT:    s_and_b64 vcc, s[4:5], vcc
; GFX9-NEXT:    v_mov_b32_e32 v0, 0x7e00
; GFX9-NEXT:    v_cmp_lg_f16_sdwa s[4:5], v2, v10 src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT:    v_cmp_nge_f16_e64 s[6:7], |v5|, s8
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v0, v4, vcc
; GFX9-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v0, v6, vcc
; GFX9-NEXT:    v_cmp_lg_f16_e32 vcc, 0, v3
; GFX9-NEXT:    v_cmp_nge_f16_e64 s[4:5], |v1|, s8
; GFX9-NEXT:    s_and_b64 vcc, s[4:5], vcc
; GFX9-NEXT:    v_cmp_lg_f16_sdwa s[4:5], v3, v10 src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT:    v_cmp_nge_f16_e64 s[6:7], |v8|, s8
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v0, v7, vcc
; GFX9-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v0, v9, vcc
; GFX9-NEXT:    s_mov_b32 s4, 0x5040100
; GFX9-NEXT:    v_perm_b32 v0, v2, v4, s4
; GFX9-NEXT:    v_perm_b32 v1, v3, v1, s4
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: frem_v4f16:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cvt_f32_f16_e64 v6, |v0|
; GFX10-NEXT:    v_cvt_f32_f16_e64 v5, |v2|
; GFX10-NEXT:    ; implicit-def: $vgpr4
; GFX10-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v6, v5
; GFX10-NEXT:    s_and_saveexec_b32 s4, vcc_lo
; GFX10-NEXT:    s_xor_b32 s4, exec_lo, s4
; GFX10-NEXT:  ; %bb.1: ; %frem.else86
; GFX10-NEXT:    v_and_b32_e32 v4, 0x8000, v0
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v6, v5
; GFX10-NEXT:    ; implicit-def: $vgpr6
; GFX10-NEXT:    ; implicit-def: $vgpr5
; GFX10-NEXT:    v_cndmask_b32_e32 v4, v0, v4, vcc_lo
; GFX10-NEXT:  ; %bb.2: ; %Flow132
; GFX10-NEXT:    s_andn2_saveexec_b32 s4, s4
; GFX10-NEXT:    s_cbranch_execz .LBB10_8
; GFX10-NEXT:  ; %bb.3: ; %frem.compute85
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v9, v6
; GFX10-NEXT:    v_frexp_mant_f32_e32 v4, v6
; GFX10-NEXT:    v_frexp_mant_f32_e32 v6, v5
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v10, v5
; GFX10-NEXT:    v_ldexp_f32 v7, v4, 11
; GFX10-NEXT:    v_ldexp_f32 v5, v6, 1
; GFX10-NEXT:    v_add_nc_u32_e32 v4, -1, v10
; GFX10-NEXT:    v_div_scale_f32 v11, s5, v5, v5, 1.0
; GFX10-NEXT:    v_div_scale_f32 v8, vcc_lo, 1.0, v5, 1.0
; GFX10-NEXT:    v_xad_u32 v6, v4, -1, v9
; GFX10-NEXT:    v_rcp_f32_e32 v12, v11
; GFX10-NEXT:    s_denorm_mode 15
; GFX10-NEXT:    v_fma_f32 v13, -v11, v12, 1.0
; GFX10-NEXT:    v_fmac_f32_e32 v12, v13, v12
; GFX10-NEXT:    v_mul_f32_e32 v13, v8, v12
; GFX10-NEXT:    v_fma_f32 v14, -v11, v13, v8
; GFX10-NEXT:    v_fmac_f32_e32 v13, v14, v12
; GFX10-NEXT:    v_fma_f32 v8, -v11, v13, v8
; GFX10-NEXT:    s_denorm_mode 12
; GFX10-NEXT:    v_div_fmas_f32 v8, v8, v12, v13
; GFX10-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 11, v6
; GFX10-NEXT:    v_div_fixup_f32 v8, v8, v5, 1.0
; GFX10-NEXT:    s_and_saveexec_b32 s5, vcc_lo
; GFX10-NEXT:    s_cbranch_execz .LBB10_7
; GFX10-NEXT:  ; %bb.4: ; %frem.loop_body93.preheader
; GFX10-NEXT:    v_sub_nc_u32_e32 v6, v9, v10
; GFX10-NEXT:    s_mov_b32 s6, 0
; GFX10-NEXT:    v_add_nc_u32_e32 v6, 11, v6
; GFX10-NEXT:  .LBB10_5: ; %frem.loop_body93
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v9, v7
; GFX10-NEXT:    v_add_nc_u32_e32 v6, -11, v6
; GFX10-NEXT:    v_mul_f32_e32 v7, v9, v8
; GFX10-NEXT:    v_rndne_f32_e32 v7, v7
; GFX10-NEXT:    v_fma_f32 v7, -v7, v5, v9
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v7
; GFX10-NEXT:    v_add_f32_e32 v10, v7, v5
; GFX10-NEXT:    v_cndmask_b32_e32 v7, v7, v10, vcc_lo
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX10-NEXT:    v_ldexp_f32 v7, v7, 11
; GFX10-NEXT:    s_or_b32 s6, vcc_lo, s6
; GFX10-NEXT:    s_andn2_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    s_cbranch_execnz .LBB10_5
; GFX10-NEXT:  ; %bb.6: ; %Flow130
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    v_mov_b32_e32 v7, v9
; GFX10-NEXT:  .LBB10_7: ; %Flow131
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s5
; GFX10-NEXT:    v_add_nc_u32_e32 v6, -10, v6
; GFX10-NEXT:    v_ldexp_f32 v6, v7, v6
; GFX10-NEXT:    v_mul_f32_e32 v7, v6, v8
; GFX10-NEXT:    v_rndne_f32_e32 v7, v7
; GFX10-NEXT:    v_fma_f32 v6, -v7, v5, v6
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v6
; GFX10-NEXT:    v_add_f32_e32 v5, v6, v5
; GFX10-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX10-NEXT:    v_cvt_f16_f32_e32 v4, v4
; GFX10-NEXT:    v_bfi_b32 v4, 0x7fff, v4, v0
; GFX10-NEXT:  .LBB10_8: ; %Flow133
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT:    v_lshrrev_b32_e32 v5, 16, v0
; GFX10-NEXT:    v_cvt_f32_f16_sdwa v7, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT:    ; implicit-def: $vgpr6
; GFX10-NEXT:    v_cvt_f32_f16_e64 v8, |v5|
; GFX10-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v8, v7
; GFX10-NEXT:    s_and_saveexec_b32 s4, vcc_lo
; GFX10-NEXT:    s_xor_b32 s4, exec_lo, s4
; GFX10-NEXT:  ; %bb.9: ; %frem.else53
; GFX10-NEXT:    v_and_b32_e32 v6, 0x8000, v5
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v8, v7
; GFX10-NEXT:    ; implicit-def: $vgpr8
; GFX10-NEXT:    ; implicit-def: $vgpr7
; GFX10-NEXT:    v_cndmask_b32_e32 v6, v5, v6, vcc_lo
; GFX10-NEXT:  ; %bb.10: ; %Flow128
; GFX10-NEXT:    s_andn2_saveexec_b32 s4, s4
; GFX10-NEXT:    s_cbranch_execz .LBB10_16
; GFX10-NEXT:  ; %bb.11: ; %frem.compute52
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v11, v8
; GFX10-NEXT:    v_frexp_mant_f32_e32 v6, v8
; GFX10-NEXT:    v_frexp_mant_f32_e32 v8, v7
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v12, v7
; GFX10-NEXT:    v_ldexp_f32 v9, v6, 11
; GFX10-NEXT:    v_ldexp_f32 v7, v8, 1
; GFX10-NEXT:    v_add_nc_u32_e32 v6, -1, v12
; GFX10-NEXT:    v_div_scale_f32 v13, s5, v7, v7, 1.0
; GFX10-NEXT:    v_div_scale_f32 v10, vcc_lo, 1.0, v7, 1.0
; GFX10-NEXT:    v_xad_u32 v8, v6, -1, v11
; GFX10-NEXT:    v_rcp_f32_e32 v14, v13
; GFX10-NEXT:    s_denorm_mode 15
; GFX10-NEXT:    v_fma_f32 v15, -v13, v14, 1.0
; GFX10-NEXT:    v_fmac_f32_e32 v14, v15, v14
; GFX10-NEXT:    v_mul_f32_e32 v15, v10, v14
; GFX10-NEXT:    v_fma_f32 v16, -v13, v15, v10
; GFX10-NEXT:    v_fmac_f32_e32 v15, v16, v14
; GFX10-NEXT:    v_fma_f32 v10, -v13, v15, v10
; GFX10-NEXT:    s_denorm_mode 12
; GFX10-NEXT:    v_div_fmas_f32 v10, v10, v14, v15
; GFX10-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 11, v8
; GFX10-NEXT:    v_div_fixup_f32 v10, v10, v7, 1.0
; GFX10-NEXT:    s_and_saveexec_b32 s5, vcc_lo
; GFX10-NEXT:    s_cbranch_execz .LBB10_15
; GFX10-NEXT:  ; %bb.12: ; %frem.loop_body60.preheader
; GFX10-NEXT:    v_sub_nc_u32_e32 v8, v11, v12
; GFX10-NEXT:    s_mov_b32 s6, 0
; GFX10-NEXT:    v_add_nc_u32_e32 v8, 11, v8
; GFX10-NEXT:  .LBB10_13: ; %frem.loop_body60
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v11, v9
; GFX10-NEXT:    v_add_nc_u32_e32 v8, -11, v8
; GFX10-NEXT:    v_mul_f32_e32 v9, v11, v10
; GFX10-NEXT:    v_rndne_f32_e32 v9, v9
; GFX10-NEXT:    v_fma_f32 v9, -v9, v7, v11
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v9
; GFX10-NEXT:    v_add_f32_e32 v12, v9, v7
; GFX10-NEXT:    v_cndmask_b32_e32 v9, v9, v12, vcc_lo
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v8
; GFX10-NEXT:    v_ldexp_f32 v9, v9, 11
; GFX10-NEXT:    s_or_b32 s6, vcc_lo, s6
; GFX10-NEXT:    s_andn2_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    s_cbranch_execnz .LBB10_13
; GFX10-NEXT:  ; %bb.14: ; %Flow126
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    v_mov_b32_e32 v9, v11
; GFX10-NEXT:  .LBB10_15: ; %Flow127
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s5
; GFX10-NEXT:    v_add_nc_u32_e32 v8, -10, v8
; GFX10-NEXT:    v_ldexp_f32 v8, v9, v8
; GFX10-NEXT:    v_mul_f32_e32 v9, v8, v10
; GFX10-NEXT:    v_rndne_f32_e32 v9, v9
; GFX10-NEXT:    v_fma_f32 v8, -v9, v7, v8
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v8
; GFX10-NEXT:    v_add_f32_e32 v7, v8, v7
; GFX10-NEXT:    v_cndmask_b32_e32 v7, v8, v7, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v6, v7, v6
; GFX10-NEXT:    v_cvt_f16_f32_e32 v6, v6
; GFX10-NEXT:    v_bfi_b32 v6, 0x7fff, v6, v5
; GFX10-NEXT:  .LBB10_16: ; %Flow129
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT:    v_cvt_f32_f16_e64 v9, |v1|
; GFX10-NEXT:    v_cvt_f32_f16_e64 v8, |v3|
; GFX10-NEXT:    ; implicit-def: $vgpr7
; GFX10-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v9, v8
; GFX10-NEXT:    s_and_saveexec_b32 s4, vcc_lo
; GFX10-NEXT:    s_xor_b32 s4, exec_lo, s4
; GFX10-NEXT:  ; %bb.17: ; %frem.else20
; GFX10-NEXT:    v_and_b32_e32 v7, 0x8000, v1
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v9, v8
; GFX10-NEXT:    ; implicit-def: $vgpr9
; GFX10-NEXT:    ; implicit-def: $vgpr8
; GFX10-NEXT:    v_cndmask_b32_e32 v7, v1, v7, vcc_lo
; GFX10-NEXT:  ; %bb.18: ; %Flow124
; GFX10-NEXT:    s_andn2_saveexec_b32 s4, s4
; GFX10-NEXT:    s_cbranch_execz .LBB10_24
; GFX10-NEXT:  ; %bb.19: ; %frem.compute19
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v12, v9
; GFX10-NEXT:    v_frexp_mant_f32_e32 v7, v9
; GFX10-NEXT:    v_frexp_mant_f32_e32 v9, v8
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v13, v8
; GFX10-NEXT:    v_ldexp_f32 v10, v7, 11
; GFX10-NEXT:    v_ldexp_f32 v8, v9, 1
; GFX10-NEXT:    v_add_nc_u32_e32 v7, -1, v13
; GFX10-NEXT:    v_div_scale_f32 v14, s5, v8, v8, 1.0
; GFX10-NEXT:    v_div_scale_f32 v11, vcc_lo, 1.0, v8, 1.0
; GFX10-NEXT:    v_xad_u32 v9, v7, -1, v12
; GFX10-NEXT:    v_rcp_f32_e32 v15, v14
; GFX10-NEXT:    s_denorm_mode 15
; GFX10-NEXT:    v_fma_f32 v16, -v14, v15, 1.0
; GFX10-NEXT:    v_fmac_f32_e32 v15, v16, v15
; GFX10-NEXT:    v_mul_f32_e32 v16, v11, v15
; GFX10-NEXT:    v_fma_f32 v17, -v14, v16, v11
; GFX10-NEXT:    v_fmac_f32_e32 v16, v17, v15
; GFX10-NEXT:    v_fma_f32 v11, -v14, v16, v11
; GFX10-NEXT:    s_denorm_mode 12
; GFX10-NEXT:    v_div_fmas_f32 v11, v11, v15, v16
; GFX10-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 11, v9
; GFX10-NEXT:    v_div_fixup_f32 v11, v11, v8, 1.0
; GFX10-NEXT:    s_and_saveexec_b32 s5, vcc_lo
; GFX10-NEXT:    s_cbranch_execz .LBB10_23
; GFX10-NEXT:  ; %bb.20: ; %frem.loop_body27.preheader
; GFX10-NEXT:    v_sub_nc_u32_e32 v9, v12, v13
; GFX10-NEXT:    s_mov_b32 s6, 0
; GFX10-NEXT:    v_add_nc_u32_e32 v9, 11, v9
; GFX10-NEXT:  .LBB10_21: ; %frem.loop_body27
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v12, v10
; GFX10-NEXT:    v_add_nc_u32_e32 v9, -11, v9
; GFX10-NEXT:    v_mul_f32_e32 v10, v12, v11
; GFX10-NEXT:    v_rndne_f32_e32 v10, v10
; GFX10-NEXT:    v_fma_f32 v10, -v10, v8, v12
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v10
; GFX10-NEXT:    v_add_f32_e32 v13, v10, v8
; GFX10-NEXT:    v_cndmask_b32_e32 v10, v10, v13, vcc_lo
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v9
; GFX10-NEXT:    v_ldexp_f32 v10, v10, 11
; GFX10-NEXT:    s_or_b32 s6, vcc_lo, s6
; GFX10-NEXT:    s_andn2_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    s_cbranch_execnz .LBB10_21
; GFX10-NEXT:  ; %bb.22: ; %Flow122
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    v_mov_b32_e32 v10, v12
; GFX10-NEXT:  .LBB10_23: ; %Flow123
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s5
; GFX10-NEXT:    v_add_nc_u32_e32 v9, -10, v9
; GFX10-NEXT:    v_ldexp_f32 v9, v10, v9
; GFX10-NEXT:    v_mul_f32_e32 v10, v9, v11
; GFX10-NEXT:    v_rndne_f32_e32 v10, v10
; GFX10-NEXT:    v_fma_f32 v9, -v10, v8, v9
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v9
; GFX10-NEXT:    v_add_f32_e32 v8, v9, v8
; GFX10-NEXT:    v_cndmask_b32_e32 v8, v9, v8, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v7, v8, v7
; GFX10-NEXT:    v_cvt_f16_f32_e32 v7, v7
; GFX10-NEXT:    v_bfi_b32 v7, 0x7fff, v7, v1
; GFX10-NEXT:  .LBB10_24: ; %Flow125
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT:    v_lshrrev_b32_e32 v8, 16, v1
; GFX10-NEXT:    v_cvt_f32_f16_sdwa v10, |v3| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT:    ; implicit-def: $vgpr9
; GFX10-NEXT:    v_cvt_f32_f16_e64 v11, |v8|
; GFX10-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v11, v10
; GFX10-NEXT:    s_and_saveexec_b32 s4, vcc_lo
; GFX10-NEXT:    s_xor_b32 s4, exec_lo, s4
; GFX10-NEXT:  ; %bb.25: ; %frem.else
; GFX10-NEXT:    v_and_b32_e32 v9, 0x8000, v8
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v11, v10
; GFX10-NEXT:    ; implicit-def: $vgpr11
; GFX10-NEXT:    ; implicit-def: $vgpr10
; GFX10-NEXT:    v_cndmask_b32_e32 v9, v8, v9, vcc_lo
; GFX10-NEXT:  ; %bb.26: ; %Flow120
; GFX10-NEXT:    s_andn2_saveexec_b32 s4, s4
; GFX10-NEXT:    s_cbranch_execz .LBB10_32
; GFX10-NEXT:  ; %bb.27: ; %frem.compute
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v14, v11
; GFX10-NEXT:    v_frexp_mant_f32_e32 v9, v11
; GFX10-NEXT:    v_frexp_mant_f32_e32 v11, v10
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v15, v10
; GFX10-NEXT:    v_ldexp_f32 v12, v9, 11
; GFX10-NEXT:    v_ldexp_f32 v10, v11, 1
; GFX10-NEXT:    v_add_nc_u32_e32 v9, -1, v15
; GFX10-NEXT:    v_div_scale_f32 v16, s5, v10, v10, 1.0
; GFX10-NEXT:    v_div_scale_f32 v13, vcc_lo, 1.0, v10, 1.0
; GFX10-NEXT:    v_xad_u32 v11, v9, -1, v14
; GFX10-NEXT:    v_rcp_f32_e32 v17, v16
; GFX10-NEXT:    s_denorm_mode 15
; GFX10-NEXT:    v_fma_f32 v18, -v16, v17, 1.0
; GFX10-NEXT:    v_fmac_f32_e32 v17, v18, v17
; GFX10-NEXT:    v_mul_f32_e32 v18, v13, v17
; GFX10-NEXT:    v_fma_f32 v19, -v16, v18, v13
; GFX10-NEXT:    v_fmac_f32_e32 v18, v19, v17
; GFX10-NEXT:    v_fma_f32 v13, -v16, v18, v13
; GFX10-NEXT:    s_denorm_mode 12
; GFX10-NEXT:    v_div_fmas_f32 v13, v13, v17, v18
; GFX10-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 11, v11
; GFX10-NEXT:    v_div_fixup_f32 v13, v13, v10, 1.0
; GFX10-NEXT:    s_and_saveexec_b32 s5, vcc_lo
; GFX10-NEXT:    s_cbranch_execz .LBB10_31
; GFX10-NEXT:  ; %bb.28: ; %frem.loop_body.preheader
; GFX10-NEXT:    v_sub_nc_u32_e32 v11, v14, v15
; GFX10-NEXT:    s_mov_b32 s6, 0
; GFX10-NEXT:    v_add_nc_u32_e32 v11, 11, v11
; GFX10-NEXT:  .LBB10_29: ; %frem.loop_body
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v14, v12
; GFX10-NEXT:    v_add_nc_u32_e32 v11, -11, v11
; GFX10-NEXT:    v_mul_f32_e32 v12, v14, v13
; GFX10-NEXT:    v_rndne_f32_e32 v12, v12
; GFX10-NEXT:    v_fma_f32 v12, -v12, v10, v14
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v12
; GFX10-NEXT:    v_add_f32_e32 v15, v12, v10
; GFX10-NEXT:    v_cndmask_b32_e32 v12, v12, v15, vcc_lo
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v11
; GFX10-NEXT:    v_ldexp_f32 v12, v12, 11
; GFX10-NEXT:    s_or_b32 s6, vcc_lo, s6
; GFX10-NEXT:    s_andn2_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    s_cbranch_execnz .LBB10_29
; GFX10-NEXT:  ; %bb.30: ; %Flow
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    v_mov_b32_e32 v12, v14
; GFX10-NEXT:  .LBB10_31: ; %Flow119
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s5
; GFX10-NEXT:    v_add_nc_u32_e32 v11, -10, v11
; GFX10-NEXT:    v_ldexp_f32 v11, v12, v11
; GFX10-NEXT:    v_mul_f32_e32 v12, v11, v13
; GFX10-NEXT:    v_rndne_f32_e32 v12, v12
; GFX10-NEXT:    v_fma_f32 v11, -v12, v10, v11
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v11
; GFX10-NEXT:    v_add_f32_e32 v10, v11, v10
; GFX10-NEXT:    v_cndmask_b32_e32 v10, v11, v10, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v9, v10, v9
; GFX10-NEXT:    v_cvt_f16_f32_e32 v9, v9
; GFX10-NEXT:    v_bfi_b32 v9, 0x7fff, v9, v8
; GFX10-NEXT:  .LBB10_32: ; %Flow121
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v2
; GFX10-NEXT:    v_cmp_nge_f16_e64 s4, |v0|, 0x7c00
; GFX10-NEXT:    v_cmp_nge_f16_e64 s5, |v5|, 0x7c00
; GFX10-NEXT:    s_and_b32 vcc_lo, s4, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v4, vcc_lo
; GFX10-NEXT:    v_mov_b32_e32 v4, 0
; GFX10-NEXT:    v_cmp_lg_f16_sdwa s4, v2, v4 src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT:    s_and_b32 vcc_lo, s5, s4
; GFX10-NEXT:    v_cmp_nge_f16_e64 s4, |v1|, 0x7c00
; GFX10-NEXT:    v_cndmask_b32_e32 v2, 0x7e00, v6, vcc_lo
; GFX10-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v3
; GFX10-NEXT:    v_cmp_nge_f16_e64 s5, |v8|, 0x7c00
; GFX10-NEXT:    v_perm_b32 v0, v2, v0, 0x5040100
; GFX10-NEXT:    s_and_b32 vcc_lo, s4, vcc_lo
; GFX10-NEXT:    v_cmp_lg_f16_sdwa s4, v3, v4 src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT:    v_cndmask_b32_e32 v1, 0x7e00, v7, vcc_lo
; GFX10-NEXT:    s_and_b32 vcc_lo, s5, s4
; GFX10-NEXT:    v_cndmask_b32_e32 v3, 0x7e00, v9, vcc_lo
; GFX10-NEXT:    v_perm_b32 v1, v3, v1, 0x5040100
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: frem_v4f16:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v6, |v0.l|
; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v5, |v2.l|
; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_lo16
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cmpx_ngt_f32_e32 v6, v5
; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT:  ; %bb.1: ; %frem.else86
; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0x8000, v0.l
; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v6, v5
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.l, v0.l, v4.l, vcc_lo
; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow132
; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB10_8
; GFX11-TRUE16-NEXT:  ; %bb.3: ; %frem.compute85
; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v9, v6
; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v4, v6
; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v6, v5
; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v10, v5
; GFX11-TRUE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v7, v4, 11
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v5, v6, 1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v4, -1, v10
; GFX11-TRUE16-NEXT:    v_div_scale_f32 v11, null, v5, v5, 1.0
; GFX11-TRUE16-NEXT:    v_div_scale_f32 v8, vcc_lo, 1.0, v5, 1.0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT:    v_xad_u32 v6, v4, -1, v9
; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v12, v11
; GFX11-TRUE16-NEXT:    s_denorm_mode 15
; GFX11-TRUE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT:    v_fma_f32 v13, -v11, v12, 1.0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v12, v13, v12
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v13, v8, v12
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v14, -v11, v13, v8
; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v13, v14, v12
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v8, -v11, v13, v8
; GFX11-TRUE16-NEXT:    s_denorm_mode 12
; GFX11-TRUE16-NEXT:    v_div_fmas_f32 v8, v8, v12, v13
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_div_fixup_f32 v8, v8, v5, 1.0
; GFX11-TRUE16-NEXT:    v_cmpx_lt_i32_e32 11, v6
; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB10_7
; GFX11-TRUE16-NEXT:  ; %bb.4: ; %frem.loop_body93.preheader
; GFX11-TRUE16-NEXT:    v_sub_nc_u32_e32 v6, v9, v10
; GFX11-TRUE16-NEXT:    s_mov_b32 s2, 0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v6, 11, v6
; GFX11-TRUE16-NEXT:  .LBB10_5: ; %frem.loop_body93
; GFX11-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v9, v7 :: v_dual_add_nc_u32 v6, -11, v6
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v7, v9, v8
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v7, v7
; GFX11-TRUE16-NEXT:    v_fma_f32 v7, -v7, v5, v9
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v7
; GFX11-TRUE16-NEXT:    v_add_f32_e32 v10, v7, v5
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v7, v7, v10, vcc_lo
; GFX11-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v7, v7, 11
; GFX11-TRUE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX11-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB10_5
; GFX11-TRUE16-NEXT:  ; %bb.6: ; %Flow130
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v7, v9
; GFX11-TRUE16-NEXT:  .LBB10_7: ; %Flow131
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v6, -10, v6
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v6, v7, v6
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v7, v6, v8
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v7, v7
; GFX11-TRUE16-NEXT:    v_fma_f32 v6, -v7, v5, v6
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v6
; GFX11-TRUE16-NEXT:    v_add_f32_e32 v5, v6, v5
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc_lo
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v4.l, v4
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_bfi_b32 v4, 0x7fff, v4, v0
; GFX11-TRUE16-NEXT:  .LBB10_8: ; %Flow133
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v7, |v0.h|
; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v6, |v2.h|
; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cmpx_ngt_f32_e32 v7, v6
; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT:  ; %bb.9: ; %frem.else53
; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0x8000, v0.h
; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v7, v6
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_cndmask_b16 v5.l, v0.h, v4.h, vcc_lo
; GFX11-TRUE16-NEXT:  ; %bb.10: ; %Flow128
; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB10_16
; GFX11-TRUE16-NEXT:  ; %bb.11: ; %frem.compute52
; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v10, v7
; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v5, v7
; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v7, v6
; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v11, v6
; GFX11-TRUE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v8, v5, 11
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v6, v7, 1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v5, -1, v11
; GFX11-TRUE16-NEXT:    v_div_scale_f32 v12, null, v6, v6, 1.0
; GFX11-TRUE16-NEXT:    v_div_scale_f32 v9, vcc_lo, 1.0, v6, 1.0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT:    v_xad_u32 v7, v5, -1, v10
; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v13, v12
; GFX11-TRUE16-NEXT:    s_denorm_mode 15
; GFX11-TRUE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT:    v_fma_f32 v14, -v12, v13, 1.0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v13, v14, v13
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v14, v9, v13
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v15, -v12, v14, v9
; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v14, v15, v13
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v9, -v12, v14, v9
; GFX11-TRUE16-NEXT:    s_denorm_mode 12
; GFX11-TRUE16-NEXT:    v_div_fmas_f32 v9, v9, v13, v14
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_div_fixup_f32 v9, v9, v6, 1.0
; GFX11-TRUE16-NEXT:    v_cmpx_lt_i32_e32 11, v7
; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB10_15
; GFX11-TRUE16-NEXT:  ; %bb.12: ; %frem.loop_body60.preheader
; GFX11-TRUE16-NEXT:    v_sub_nc_u32_e32 v7, v10, v11
; GFX11-TRUE16-NEXT:    s_mov_b32 s2, 0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v7, 11, v7
; GFX11-TRUE16-NEXT:  .LBB10_13: ; %frem.loop_body60
; GFX11-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v10, v8 :: v_dual_add_nc_u32 v7, -11, v7
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v8, v10, v9
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v8, v8
; GFX11-TRUE16-NEXT:    v_fma_f32 v8, -v8, v6, v10
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v8
; GFX11-TRUE16-NEXT:    v_add_f32_e32 v11, v8, v6
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v8, v8, v11, vcc_lo
; GFX11-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v7
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v8, v8, 11
; GFX11-TRUE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX11-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB10_13
; GFX11-TRUE16-NEXT:  ; %bb.14: ; %Flow126
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v8, v10
; GFX11-TRUE16-NEXT:  .LBB10_15: ; %Flow127
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v7, -10, v7
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v7, v8, v7
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v8, v7, v9
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v8, v8
; GFX11-TRUE16-NEXT:    v_fma_f32 v7, -v8, v6, v7
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v7
; GFX11-TRUE16-NEXT:    v_add_f32_e32 v6, v7, v6
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc_lo
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v5, v6, v5
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v0.h
; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v5.l, v5
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_bfi_b32 v5, 0x7fff, v5, v6
; GFX11-TRUE16-NEXT:  .LBB10_16: ; %Flow129
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v8, |v1.l|
; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v7, |v3.l|
; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_lo16
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cmpx_ngt_f32_e32 v8, v7
; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT:  ; %bb.17: ; %frem.else20
; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0x8000, v1.l
; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v8, v7
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_cndmask_b16 v6.l, v1.l, v4.h, vcc_lo
; GFX11-TRUE16-NEXT:  ; %bb.18: ; %Flow124
; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB10_24
; GFX11-TRUE16-NEXT:  ; %bb.19: ; %frem.compute19
; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v11, v8
; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v6, v8
; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v8, v7
; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v12, v7
; GFX11-TRUE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v9, v6, 11
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v7, v8, 1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v6, -1, v12
; GFX11-TRUE16-NEXT:    v_div_scale_f32 v13, null, v7, v7, 1.0
; GFX11-TRUE16-NEXT:    v_div_scale_f32 v10, vcc_lo, 1.0, v7, 1.0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT:    v_xad_u32 v8, v6, -1, v11
; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v14, v13
; GFX11-TRUE16-NEXT:    s_denorm_mode 15
; GFX11-TRUE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT:    v_fma_f32 v15, -v13, v14, 1.0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v14, v15, v14
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v15, v10, v14
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v16, -v13, v15, v10
; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v15, v16, v14
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v10, -v13, v15, v10
; GFX11-TRUE16-NEXT:    s_denorm_mode 12
; GFX11-TRUE16-NEXT:    v_div_fmas_f32 v10, v10, v14, v15
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_div_fixup_f32 v10, v10, v7, 1.0
; GFX11-TRUE16-NEXT:    v_cmpx_lt_i32_e32 11, v8
; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB10_23
; GFX11-TRUE16-NEXT:  ; %bb.20: ; %frem.loop_body27.preheader
; GFX11-TRUE16-NEXT:    v_sub_nc_u32_e32 v8, v11, v12
; GFX11-TRUE16-NEXT:    s_mov_b32 s2, 0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v8, 11, v8
; GFX11-TRUE16-NEXT:  .LBB10_21: ; %frem.loop_body27
; GFX11-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v11, v9 :: v_dual_add_nc_u32 v8, -11, v8
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v9, v11, v10
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v9, v9
; GFX11-TRUE16-NEXT:    v_fma_f32 v9, -v9, v7, v11
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v9
; GFX11-TRUE16-NEXT:    v_add_f32_e32 v12, v9, v7
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v9, v9, v12, vcc_lo
; GFX11-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v8
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v9, v9, 11
; GFX11-TRUE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX11-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB10_21
; GFX11-TRUE16-NEXT:  ; %bb.22: ; %Flow122
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v9, v11
; GFX11-TRUE16-NEXT:  .LBB10_23: ; %Flow123
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v8, -10, v8
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v8, v9, v8
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v9, v8, v10
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v9, v9
; GFX11-TRUE16-NEXT:    v_fma_f32 v8, -v9, v7, v8
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v8
; GFX11-TRUE16-NEXT:    v_add_f32_e32 v7, v8, v7
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v7, v8, v7, vcc_lo
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v6, v7, v6
; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v6.l, v6
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_bfi_b32 v6, 0x7fff, v6, v1
; GFX11-TRUE16-NEXT:  .LBB10_24: ; %Flow125
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v9, |v1.h|
; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v8, |v3.h|
; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cmpx_ngt_f32_e32 v9, v8
; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT:  ; %bb.25: ; %frem.else
; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0x8000, v1.h
; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v9, v8
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_cndmask_b16 v7.l, v1.h, v4.h, vcc_lo
; GFX11-TRUE16-NEXT:  ; %bb.26: ; %Flow120
; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB10_32
; GFX11-TRUE16-NEXT:  ; %bb.27: ; %frem.compute
; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v12, v9
; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v7, v9
; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v9, v8
; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v13, v8
; GFX11-TRUE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v10, v7, 11
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v8, v9, 1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v7, -1, v13
; GFX11-TRUE16-NEXT:    v_div_scale_f32 v14, null, v8, v8, 1.0
; GFX11-TRUE16-NEXT:    v_div_scale_f32 v11, vcc_lo, 1.0, v8, 1.0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT:    v_xad_u32 v9, v7, -1, v12
; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v15, v14
; GFX11-TRUE16-NEXT:    s_denorm_mode 15
; GFX11-TRUE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT:    v_fma_f32 v16, -v14, v15, 1.0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v15, v16, v15
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v16, v11, v15
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v17, -v14, v16, v11
; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v16, v17, v15
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v11, -v14, v16, v11
; GFX11-TRUE16-NEXT:    s_denorm_mode 12
; GFX11-TRUE16-NEXT:    v_div_fmas_f32 v11, v11, v15, v16
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_div_fixup_f32 v11, v11, v8, 1.0
; GFX11-TRUE16-NEXT:    v_cmpx_lt_i32_e32 11, v9
; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB10_31
; GFX11-TRUE16-NEXT:  ; %bb.28: ; %frem.loop_body.preheader
; GFX11-TRUE16-NEXT:    v_sub_nc_u32_e32 v9, v12, v13
; GFX11-TRUE16-NEXT:    s_mov_b32 s2, 0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v9, 11, v9
; GFX11-TRUE16-NEXT:  .LBB10_29: ; %frem.loop_body
; GFX11-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v12, v10 :: v_dual_add_nc_u32 v9, -11, v9
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v10, v12, v11
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v10, v10
; GFX11-TRUE16-NEXT:    v_fma_f32 v10, -v10, v8, v12
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v10
; GFX11-TRUE16-NEXT:    v_add_f32_e32 v13, v10, v8
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v10, v10, v13, vcc_lo
; GFX11-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v9
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v10, v10, 11
; GFX11-TRUE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX11-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB10_29
; GFX11-TRUE16-NEXT:  ; %bb.30: ; %Flow
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v10, v12
; GFX11-TRUE16-NEXT:  .LBB10_31: ; %Flow119
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v9, -10, v9
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v9, v10, v9
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v10, v9, v11
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v10, v10
; GFX11-TRUE16-NEXT:    v_fma_f32 v9, -v10, v8, v9
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v9
; GFX11-TRUE16-NEXT:    v_add_f32_e32 v8, v9, v8
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v8, v9, v8, vcc_lo
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v7, v8, v7
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v1.h
; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v7.l, v7
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_bfi_b32 v7, 0x7fff, v7, v8
; GFX11-TRUE16-NEXT:  .LBB10_32: ; %Flow121
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v2.l
; GFX11-TRUE16-NEXT:    v_cmp_nge_f16_e64 s0, |v0.l|, 0x7c00
; GFX11-TRUE16-NEXT:    s_and_b32 s0, s0, vcc_lo
; GFX11-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v2.h
; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v4.l, s0
; GFX11-TRUE16-NEXT:    v_cmp_nge_f16_e64 s0, |v0.h|, 0x7c00
; GFX11-TRUE16-NEXT:    s_and_b32 s0, s0, vcc_lo
; GFX11-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v3.l
; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, 0x7e00, v5.l, s0
; GFX11-TRUE16-NEXT:    v_cmp_nge_f16_e64 s0, |v1.l|, 0x7c00
; GFX11-TRUE16-NEXT:    s_and_b32 s0, s0, vcc_lo
; GFX11-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v3.h
; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, 0x7e00, v6.l, s0
; GFX11-TRUE16-NEXT:    v_cmp_nge_f16_e64 s0, |v1.h|, 0x7c00
; GFX11-TRUE16-NEXT:    s_and_b32 s0, s0, vcc_lo
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, 0x7e00, v7.l, s0
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: frem_v4f16:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v6, |v0|
; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v5, |v2|
; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr4
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cmpx_ngt_f32_e32 v6, v5
; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT:  ; %bb.1: ; %frem.else86
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0x8000, v0
; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v6, v5
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v0, v4, vcc_lo
; GFX11-FAKE16-NEXT:  ; %bb.2: ; %Flow132
; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB10_8
; GFX11-FAKE16-NEXT:  ; %bb.3: ; %frem.compute85
; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v9, v6
; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v4, v6
; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v6, v5
; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v10, v5
; GFX11-FAKE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v7, v4, 11
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v5, v6, 1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, -1, v10
; GFX11-FAKE16-NEXT:    v_div_scale_f32 v11, null, v5, v5, 1.0
; GFX11-FAKE16-NEXT:    v_div_scale_f32 v8, vcc_lo, 1.0, v5, 1.0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT:    v_xad_u32 v6, v4, -1, v9
; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v12, v11
; GFX11-FAKE16-NEXT:    s_denorm_mode 15
; GFX11-FAKE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT:    v_fma_f32 v13, -v11, v12, 1.0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v12, v13, v12
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v13, v8, v12
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v14, -v11, v13, v8
; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v13, v14, v12
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v8, -v11, v13, v8
; GFX11-FAKE16-NEXT:    s_denorm_mode 12
; GFX11-FAKE16-NEXT:    v_div_fmas_f32 v8, v8, v12, v13
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_div_fixup_f32 v8, v8, v5, 1.0
; GFX11-FAKE16-NEXT:    v_cmpx_lt_i32_e32 11, v6
; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB10_7
; GFX11-FAKE16-NEXT:  ; %bb.4: ; %frem.loop_body93.preheader
; GFX11-FAKE16-NEXT:    v_sub_nc_u32_e32 v6, v9, v10
; GFX11-FAKE16-NEXT:    s_mov_b32 s2, 0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v6, 11, v6
; GFX11-FAKE16-NEXT:  .LBB10_5: ; %frem.loop_body93
; GFX11-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v9, v7 :: v_dual_add_nc_u32 v6, -11, v6
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v7, v9, v8
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v7, v7
; GFX11-FAKE16-NEXT:    v_fma_f32 v7, -v7, v5, v9
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v7
; GFX11-FAKE16-NEXT:    v_add_f32_e32 v10, v7, v5
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v7, v10, vcc_lo
; GFX11-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v7, v7, 11
; GFX11-FAKE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX11-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB10_5
; GFX11-FAKE16-NEXT:  ; %bb.6: ; %Flow130
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v7, v9
; GFX11-FAKE16-NEXT:  .LBB10_7: ; %Flow131
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v6, -10, v6
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v6, v7, v6
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v7, v6, v8
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v7, v7
; GFX11-FAKE16-NEXT:    v_fma_f32 v6, -v7, v5, v6
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v6
; GFX11-FAKE16-NEXT:    v_add_f32_e32 v5, v6, v5
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v4, v4
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_bfi_b32 v4, 0x7fff, v4, v0
; GFX11-FAKE16-NEXT:  .LBB10_8: ; %Flow133
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v0
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v9, |v5|
; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v8, |v6|
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cmpx_ngt_f32_e32 v9, v8
; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT:  ; %bb.9: ; %frem.else53
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0x8000, v5
; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v9, v8
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr8
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v5, v7, vcc_lo
; GFX11-FAKE16-NEXT:  ; %bb.10: ; %Flow128
; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB10_16
; GFX11-FAKE16-NEXT:  ; %bb.11: ; %frem.compute52
; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v12, v9
; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v7, v9
; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v9, v8
; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v13, v8
; GFX11-FAKE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v10, v7, 11
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v8, v9, 1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v7, -1, v13
; GFX11-FAKE16-NEXT:    v_div_scale_f32 v14, null, v8, v8, 1.0
; GFX11-FAKE16-NEXT:    v_div_scale_f32 v11, vcc_lo, 1.0, v8, 1.0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT:    v_xad_u32 v9, v7, -1, v12
; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v15, v14
; GFX11-FAKE16-NEXT:    s_denorm_mode 15
; GFX11-FAKE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT:    v_fma_f32 v16, -v14, v15, 1.0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v15, v16, v15
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v16, v11, v15
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v17, -v14, v16, v11
; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v16, v17, v15
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v11, -v14, v16, v11
; GFX11-FAKE16-NEXT:    s_denorm_mode 12
; GFX11-FAKE16-NEXT:    v_div_fmas_f32 v11, v11, v15, v16
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_div_fixup_f32 v11, v11, v8, 1.0
; GFX11-FAKE16-NEXT:    v_cmpx_lt_i32_e32 11, v9
; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB10_15
; GFX11-FAKE16-NEXT:  ; %bb.12: ; %frem.loop_body60.preheader
; GFX11-FAKE16-NEXT:    v_sub_nc_u32_e32 v9, v12, v13
; GFX11-FAKE16-NEXT:    s_mov_b32 s2, 0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v9, 11, v9
; GFX11-FAKE16-NEXT:  .LBB10_13: ; %frem.loop_body60
; GFX11-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v12, v10 :: v_dual_add_nc_u32 v9, -11, v9
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v10, v12, v11
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v10, v10
; GFX11-FAKE16-NEXT:    v_fma_f32 v10, -v10, v8, v12
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v10
; GFX11-FAKE16-NEXT:    v_add_f32_e32 v13, v10, v8
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v10, v10, v13, vcc_lo
; GFX11-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v9
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v10, v10, 11
; GFX11-FAKE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX11-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB10_13
; GFX11-FAKE16-NEXT:  ; %bb.14: ; %Flow126
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v10, v12
; GFX11-FAKE16-NEXT:  .LBB10_15: ; %Flow127
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v9, -10, v9
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v9, v10, v9
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v10, v9, v11
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v10, v10
; GFX11-FAKE16-NEXT:    v_fma_f32 v9, -v10, v8, v9
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v9
; GFX11-FAKE16-NEXT:    v_add_f32_e32 v8, v9, v8
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v9, v8, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v7, v8, v7
; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v7, v7
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_bfi_b32 v7, 0x7fff, v7, v5
; GFX11-FAKE16-NEXT:  .LBB10_16: ; %Flow129
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v10, |v1|
; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v9, |v3|
; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr8
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cmpx_ngt_f32_e32 v10, v9
; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT:  ; %bb.17: ; %frem.else20
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0x8000, v1
; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v10, v9
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v1, v8, vcc_lo
; GFX11-FAKE16-NEXT:  ; %bb.18: ; %Flow124
; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB10_24
; GFX11-FAKE16-NEXT:  ; %bb.19: ; %frem.compute19
; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v13, v10
; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v8, v10
; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v10, v9
; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v14, v9
; GFX11-FAKE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v11, v8, 11
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v9, v10, 1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v8, -1, v14
; GFX11-FAKE16-NEXT:    v_div_scale_f32 v15, null, v9, v9, 1.0
; GFX11-FAKE16-NEXT:    v_div_scale_f32 v12, vcc_lo, 1.0, v9, 1.0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT:    v_xad_u32 v10, v8, -1, v13
; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v16, v15
; GFX11-FAKE16-NEXT:    s_denorm_mode 15
; GFX11-FAKE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT:    v_fma_f32 v17, -v15, v16, 1.0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v16, v17, v16
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v17, v12, v16
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v18, -v15, v17, v12
; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v17, v18, v16
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v12, -v15, v17, v12
; GFX11-FAKE16-NEXT:    s_denorm_mode 12
; GFX11-FAKE16-NEXT:    v_div_fmas_f32 v12, v12, v16, v17
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_div_fixup_f32 v12, v12, v9, 1.0
; GFX11-FAKE16-NEXT:    v_cmpx_lt_i32_e32 11, v10
; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB10_23
; GFX11-FAKE16-NEXT:  ; %bb.20: ; %frem.loop_body27.preheader
; GFX11-FAKE16-NEXT:    v_sub_nc_u32_e32 v10, v13, v14
; GFX11-FAKE16-NEXT:    s_mov_b32 s2, 0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v10, 11, v10
; GFX11-FAKE16-NEXT:  .LBB10_21: ; %frem.loop_body27
; GFX11-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v13, v11 :: v_dual_add_nc_u32 v10, -11, v10
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v11, v13, v12
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v11, v11
; GFX11-FAKE16-NEXT:    v_fma_f32 v11, -v11, v9, v13
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v11
; GFX11-FAKE16-NEXT:    v_add_f32_e32 v14, v11, v9
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v11, v14, vcc_lo
; GFX11-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v10
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v11, v11, 11
; GFX11-FAKE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX11-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB10_21
; GFX11-FAKE16-NEXT:  ; %bb.22: ; %Flow122
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v11, v13
; GFX11-FAKE16-NEXT:  .LBB10_23: ; %Flow123
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v10, -10, v10
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v10, v11, v10
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v11, v10, v12
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v11, v11
; GFX11-FAKE16-NEXT:    v_fma_f32 v10, -v11, v9, v10
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v10
; GFX11-FAKE16-NEXT:    v_add_f32_e32 v9, v10, v9
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v10, v9, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v8, v9, v8
; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v8, v8
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_bfi_b32 v8, 0x7fff, v8, v1
; GFX11-FAKE16-NEXT:  .LBB10_24: ; %Flow125
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v1
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v3
; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v13, |v9|
; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v12, |v10|
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cmpx_ngt_f32_e32 v13, v12
; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT:  ; %bb.25: ; %frem.else
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0x8000, v9
; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v13, v12
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v9, v11, vcc_lo
; GFX11-FAKE16-NEXT:  ; %bb.26: ; %Flow120
; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB10_32
; GFX11-FAKE16-NEXT:  ; %bb.27: ; %frem.compute
; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v16, v13
; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v11, v13
; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v13, v12
; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v17, v12
; GFX11-FAKE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v14, v11, 11
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v12, v13, 1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v11, -1, v17
; GFX11-FAKE16-NEXT:    v_div_scale_f32 v18, null, v12, v12, 1.0
; GFX11-FAKE16-NEXT:    v_div_scale_f32 v15, vcc_lo, 1.0, v12, 1.0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT:    v_xad_u32 v13, v11, -1, v16
; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v19, v18
; GFX11-FAKE16-NEXT:    s_denorm_mode 15
; GFX11-FAKE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT:    v_fma_f32 v20, -v18, v19, 1.0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v19, v20, v19
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v20, v15, v19
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v21, -v18, v20, v15
; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v20, v21, v19
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v15, -v18, v20, v15
; GFX11-FAKE16-NEXT:    s_denorm_mode 12
; GFX11-FAKE16-NEXT:    v_div_fmas_f32 v15, v15, v19, v20
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_div_fixup_f32 v15, v15, v12, 1.0
; GFX11-FAKE16-NEXT:    v_cmpx_lt_i32_e32 11, v13
; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB10_31
; GFX11-FAKE16-NEXT:  ; %bb.28: ; %frem.loop_body.preheader
; GFX11-FAKE16-NEXT:    v_sub_nc_u32_e32 v13, v16, v17
; GFX11-FAKE16-NEXT:    s_mov_b32 s2, 0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v13, 11, v13
; GFX11-FAKE16-NEXT:  .LBB10_29: ; %frem.loop_body
; GFX11-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v16, v14 :: v_dual_add_nc_u32 v13, -11, v13
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v14, v16, v15
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v14, v14
; GFX11-FAKE16-NEXT:    v_fma_f32 v14, -v14, v12, v16
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v14
; GFX11-FAKE16-NEXT:    v_add_f32_e32 v17, v14, v12
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v14, v14, v17, vcc_lo
; GFX11-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v13
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v14, v14, 11
; GFX11-FAKE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX11-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB10_29
; GFX11-FAKE16-NEXT:  ; %bb.30: ; %Flow
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v14, v16
; GFX11-FAKE16-NEXT:  .LBB10_31: ; %Flow119
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v13, -10, v13
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v13, v14, v13
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v14, v13, v15
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v14, v14
; GFX11-FAKE16-NEXT:    v_fma_f32 v13, -v14, v12, v13
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v13
; GFX11-FAKE16-NEXT:    v_add_f32_e32 v12, v13, v12
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v13, v12, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v11, v12, v11
; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v11, v11
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_bfi_b32 v11, 0x7fff, v11, v9
; GFX11-FAKE16-NEXT:  .LBB10_32: ; %Flow121
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v2
; GFX11-FAKE16-NEXT:    v_cmp_nge_f16_e64 s0, |v0|, 0x7c00
; GFX11-FAKE16-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX11-FAKE16-NEXT:    v_cmp_nge_f16_e64 s0, |v5|, 0x7c00
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v4, vcc_lo
; GFX11-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v6
; GFX11-FAKE16-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX11-FAKE16-NEXT:    v_cmp_nge_f16_e64 s0, |v1|, 0x7c00
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, 0x7e00, v7, vcc_lo
; GFX11-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v3
; GFX11-FAKE16-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX11-FAKE16-NEXT:    v_cmp_nge_f16_e64 s0, |v9|, 0x7c00
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x7e00, v8, vcc_lo
; GFX11-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v10
; GFX11-FAKE16-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, 0x7e00, v11, vcc_lo
; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v2, v0, 0x5040100
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v3, v1, 0x5040100
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-TRUE16-LABEL: frem_v4f16:
; GFX1150-TRUE16:       ; %bb.0:
; GFX1150-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-TRUE16-NEXT:    v_cvt_f32_f16_e64 v6, |v0.l|
; GFX1150-TRUE16-NEXT:    v_cvt_f32_f16_e64 v5, |v2.l|
; GFX1150-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX1150-TRUE16-NEXT:    ; implicit-def: $vgpr4_lo16
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cmpx_ngt_f32_e32 v6, v5
; GFX1150-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX1150-TRUE16-NEXT:  ; %bb.1: ; %frem.else86
; GFX1150-TRUE16-NEXT:    v_and_b16 v4.l, 0x8000, v0.l
; GFX1150-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v6, v5
; GFX1150-TRUE16-NEXT:    ; implicit-def: $vgpr6
; GFX1150-TRUE16-NEXT:    ; implicit-def: $vgpr5
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v4.l, v0.l, v4.l, vcc_lo
; GFX1150-TRUE16-NEXT:  ; %bb.2: ; %Flow132
; GFX1150-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1150-TRUE16-NEXT:    s_cbranch_execz .LBB10_8
; GFX1150-TRUE16-NEXT:  ; %bb.3: ; %frem.compute85
; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v9, v6
; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v4, v6
; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v6, v5
; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v10, v5
; GFX1150-TRUE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v7, v4, 11
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v5, v6, 1
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v4, -1, v10
; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v11, null, v5, v5, 1.0
; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v8, vcc_lo, 1.0, v5, 1.0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT:    v_xad_u32 v6, v4, -1, v9
; GFX1150-TRUE16-NEXT:    v_rcp_f32_e32 v12, v11
; GFX1150-TRUE16-NEXT:    s_denorm_mode 15
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fma_f32 v13, -v11, v12, 1.0
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v12, v13, v12
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v13, v8, v12
; GFX1150-TRUE16-NEXT:    v_fma_f32 v14, -v11, v13, v8
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v13, v14, v12
; GFX1150-TRUE16-NEXT:    v_fma_f32 v8, -v11, v13, v8
; GFX1150-TRUE16-NEXT:    s_denorm_mode 12
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_div_fmas_f32 v8, v8, v12, v13
; GFX1150-TRUE16-NEXT:    v_div_fixup_f32 v8, v8, v5, 1.0
; GFX1150-TRUE16-NEXT:    v_cmpx_lt_i32_e32 11, v6
; GFX1150-TRUE16-NEXT:    s_cbranch_execz .LBB10_7
; GFX1150-TRUE16-NEXT:  ; %bb.4: ; %frem.loop_body93.preheader
; GFX1150-TRUE16-NEXT:    v_sub_nc_u32_e32 v6, v9, v10
; GFX1150-TRUE16-NEXT:    s_mov_b32 s2, 0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v6, 11, v6
; GFX1150-TRUE16-NEXT:  .LBB10_5: ; %frem.loop_body93
; GFX1150-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_dual_mov_b32 v9, v7 :: v_dual_add_nc_u32 v6, -11, v6
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v7, v9, v8
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v7, v7
; GFX1150-TRUE16-NEXT:    v_fma_f32 v7, -v7, v5, v9
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v7
; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v10, v7, v5
; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v7, v7, v10, vcc_lo
; GFX1150-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v7, v7, 11
; GFX1150-TRUE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1150-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1150-TRUE16-NEXT:    s_cbranch_execnz .LBB10_5
; GFX1150-TRUE16-NEXT:  ; %bb.6: ; %Flow130
; GFX1150-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v7, v9
; GFX1150-TRUE16-NEXT:  .LBB10_7: ; %Flow131
; GFX1150-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v6, -10, v6
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v6, v7, v6
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v7, v6, v8
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v7, v7
; GFX1150-TRUE16-NEXT:    v_fma_f32 v6, -v7, v5, v6
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v6
; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v5, v6, v5
; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc_lo
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX1150-TRUE16-NEXT:    v_cvt_f16_f32_e32 v4.l, v4
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_bfi_b32 v4, 0x7fff, v4, v0
; GFX1150-TRUE16-NEXT:  .LBB10_8: ; %Flow133
; GFX1150-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1150-TRUE16-NEXT:    v_cvt_f32_f16_e64 v7, |v0.h|
; GFX1150-TRUE16-NEXT:    v_cvt_f32_f16_e64 v6, |v2.h|
; GFX1150-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX1150-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cmpx_ngt_f32_e32 v7, v6
; GFX1150-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX1150-TRUE16-NEXT:  ; %bb.9: ; %frem.else53
; GFX1150-TRUE16-NEXT:    v_and_b16 v4.h, 0x8000, v0.h
; GFX1150-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v7, v6
; GFX1150-TRUE16-NEXT:    ; implicit-def: $vgpr7
; GFX1150-TRUE16-NEXT:    ; implicit-def: $vgpr6
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v5.l, v0.h, v4.h, vcc_lo
; GFX1150-TRUE16-NEXT:  ; %bb.10: ; %Flow128
; GFX1150-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1150-TRUE16-NEXT:    s_cbranch_execz .LBB10_16
; GFX1150-TRUE16-NEXT:  ; %bb.11: ; %frem.compute52
; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v10, v7
; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v5, v7
; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v7, v6
; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v11, v6
; GFX1150-TRUE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v8, v5, 11
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v6, v7, 1
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v5, -1, v11
; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v12, null, v6, v6, 1.0
; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v9, vcc_lo, 1.0, v6, 1.0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT:    v_xad_u32 v7, v5, -1, v10
; GFX1150-TRUE16-NEXT:    v_rcp_f32_e32 v13, v12
; GFX1150-TRUE16-NEXT:    s_denorm_mode 15
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fma_f32 v14, -v12, v13, 1.0
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v13, v14, v13
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v14, v9, v13
; GFX1150-TRUE16-NEXT:    v_fma_f32 v15, -v12, v14, v9
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v14, v15, v13
; GFX1150-TRUE16-NEXT:    v_fma_f32 v9, -v12, v14, v9
; GFX1150-TRUE16-NEXT:    s_denorm_mode 12
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_div_fmas_f32 v9, v9, v13, v14
; GFX1150-TRUE16-NEXT:    v_div_fixup_f32 v9, v9, v6, 1.0
; GFX1150-TRUE16-NEXT:    v_cmpx_lt_i32_e32 11, v7
; GFX1150-TRUE16-NEXT:    s_cbranch_execz .LBB10_15
; GFX1150-TRUE16-NEXT:  ; %bb.12: ; %frem.loop_body60.preheader
; GFX1150-TRUE16-NEXT:    v_sub_nc_u32_e32 v7, v10, v11
; GFX1150-TRUE16-NEXT:    s_mov_b32 s2, 0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v7, 11, v7
; GFX1150-TRUE16-NEXT:  .LBB10_13: ; %frem.loop_body60
; GFX1150-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_dual_mov_b32 v10, v8 :: v_dual_add_nc_u32 v7, -11, v7
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v8, v10, v9
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v8, v8
; GFX1150-TRUE16-NEXT:    v_fma_f32 v8, -v8, v6, v10
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v8
; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v11, v8, v6
; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v8, v8, v11, vcc_lo
; GFX1150-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v7
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v8, v8, 11
; GFX1150-TRUE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1150-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1150-TRUE16-NEXT:    s_cbranch_execnz .LBB10_13
; GFX1150-TRUE16-NEXT:  ; %bb.14: ; %Flow126
; GFX1150-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v8, v10
; GFX1150-TRUE16-NEXT:  .LBB10_15: ; %Flow127
; GFX1150-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v7, -10, v7
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v7, v8, v7
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v8, v7, v9
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v8, v8
; GFX1150-TRUE16-NEXT:    v_fma_f32 v7, -v8, v6, v7
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v7
; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v6, v7, v6
; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc_lo
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v5, v6, v5
; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v0.h
; GFX1150-TRUE16-NEXT:    v_cvt_f16_f32_e32 v5.l, v5
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_bfi_b32 v5, 0x7fff, v5, v6
; GFX1150-TRUE16-NEXT:  .LBB10_16: ; %Flow129
; GFX1150-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1150-TRUE16-NEXT:    v_cvt_f32_f16_e64 v8, |v1.l|
; GFX1150-TRUE16-NEXT:    v_cvt_f32_f16_e64 v7, |v3.l|
; GFX1150-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX1150-TRUE16-NEXT:    ; implicit-def: $vgpr6_lo16
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cmpx_ngt_f32_e32 v8, v7
; GFX1150-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX1150-TRUE16-NEXT:  ; %bb.17: ; %frem.else20
; GFX1150-TRUE16-NEXT:    v_and_b16 v4.h, 0x8000, v1.l
; GFX1150-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v8, v7
; GFX1150-TRUE16-NEXT:    ; implicit-def: $vgpr8
; GFX1150-TRUE16-NEXT:    ; implicit-def: $vgpr7
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v6.l, v1.l, v4.h, vcc_lo
; GFX1150-TRUE16-NEXT:  ; %bb.18: ; %Flow124
; GFX1150-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1150-TRUE16-NEXT:    s_cbranch_execz .LBB10_24
; GFX1150-TRUE16-NEXT:  ; %bb.19: ; %frem.compute19
; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v11, v8
; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v6, v8
; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v8, v7
; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v12, v7
; GFX1150-TRUE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v9, v6, 11
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v7, v8, 1
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v6, -1, v12
; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v13, null, v7, v7, 1.0
; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v10, vcc_lo, 1.0, v7, 1.0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT:    v_xad_u32 v8, v6, -1, v11
; GFX1150-TRUE16-NEXT:    v_rcp_f32_e32 v14, v13
; GFX1150-TRUE16-NEXT:    s_denorm_mode 15
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fma_f32 v15, -v13, v14, 1.0
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v14, v15, v14
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v15, v10, v14
; GFX1150-TRUE16-NEXT:    v_fma_f32 v16, -v13, v15, v10
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v15, v16, v14
; GFX1150-TRUE16-NEXT:    v_fma_f32 v10, -v13, v15, v10
; GFX1150-TRUE16-NEXT:    s_denorm_mode 12
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_div_fmas_f32 v10, v10, v14, v15
; GFX1150-TRUE16-NEXT:    v_div_fixup_f32 v10, v10, v7, 1.0
; GFX1150-TRUE16-NEXT:    v_cmpx_lt_i32_e32 11, v8
; GFX1150-TRUE16-NEXT:    s_cbranch_execz .LBB10_23
; GFX1150-TRUE16-NEXT:  ; %bb.20: ; %frem.loop_body27.preheader
; GFX1150-TRUE16-NEXT:    v_sub_nc_u32_e32 v8, v11, v12
; GFX1150-TRUE16-NEXT:    s_mov_b32 s2, 0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v8, 11, v8
; GFX1150-TRUE16-NEXT:  .LBB10_21: ; %frem.loop_body27
; GFX1150-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_dual_mov_b32 v11, v9 :: v_dual_add_nc_u32 v8, -11, v8
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v9, v11, v10
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v9, v9
; GFX1150-TRUE16-NEXT:    v_fma_f32 v9, -v9, v7, v11
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v9
; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v12, v9, v7
; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v9, v9, v12, vcc_lo
; GFX1150-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v8
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v9, v9, 11
; GFX1150-TRUE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1150-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1150-TRUE16-NEXT:    s_cbranch_execnz .LBB10_21
; GFX1150-TRUE16-NEXT:  ; %bb.22: ; %Flow122
; GFX1150-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v9, v11
; GFX1150-TRUE16-NEXT:  .LBB10_23: ; %Flow123
; GFX1150-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v8, -10, v8
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v8, v9, v8
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v9, v8, v10
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v9, v9
; GFX1150-TRUE16-NEXT:    v_fma_f32 v8, -v9, v7, v8
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v8
; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v7, v8, v7
; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v7, v8, v7, vcc_lo
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v6, v7, v6
; GFX1150-TRUE16-NEXT:    v_cvt_f16_f32_e32 v6.l, v6
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_bfi_b32 v6, 0x7fff, v6, v1
; GFX1150-TRUE16-NEXT:  .LBB10_24: ; %Flow125
; GFX1150-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1150-TRUE16-NEXT:    v_cvt_f32_f16_e64 v9, |v1.h|
; GFX1150-TRUE16-NEXT:    v_cvt_f32_f16_e64 v8, |v3.h|
; GFX1150-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX1150-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cmpx_ngt_f32_e32 v9, v8
; GFX1150-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX1150-TRUE16-NEXT:  ; %bb.25: ; %frem.else
; GFX1150-TRUE16-NEXT:    v_and_b16 v4.h, 0x8000, v1.h
; GFX1150-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v9, v8
; GFX1150-TRUE16-NEXT:    ; implicit-def: $vgpr9
; GFX1150-TRUE16-NEXT:    ; implicit-def: $vgpr8
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v7.l, v1.h, v4.h, vcc_lo
; GFX1150-TRUE16-NEXT:  ; %bb.26: ; %Flow120
; GFX1150-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1150-TRUE16-NEXT:    s_cbranch_execz .LBB10_32
; GFX1150-TRUE16-NEXT:  ; %bb.27: ; %frem.compute
; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v12, v9
; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v7, v9
; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v9, v8
; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v13, v8
; GFX1150-TRUE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v10, v7, 11
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v8, v9, 1
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v7, -1, v13
; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v14, null, v8, v8, 1.0
; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v11, vcc_lo, 1.0, v8, 1.0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT:    v_xad_u32 v9, v7, -1, v12
; GFX1150-TRUE16-NEXT:    v_rcp_f32_e32 v15, v14
; GFX1150-TRUE16-NEXT:    s_denorm_mode 15
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fma_f32 v16, -v14, v15, 1.0
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v15, v16, v15
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v16, v11, v15
; GFX1150-TRUE16-NEXT:    v_fma_f32 v17, -v14, v16, v11
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v16, v17, v15
; GFX1150-TRUE16-NEXT:    v_fma_f32 v11, -v14, v16, v11
; GFX1150-TRUE16-NEXT:    s_denorm_mode 12
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_div_fmas_f32 v11, v11, v15, v16
; GFX1150-TRUE16-NEXT:    v_div_fixup_f32 v11, v11, v8, 1.0
; GFX1150-TRUE16-NEXT:    v_cmpx_lt_i32_e32 11, v9
; GFX1150-TRUE16-NEXT:    s_cbranch_execz .LBB10_31
; GFX1150-TRUE16-NEXT:  ; %bb.28: ; %frem.loop_body.preheader
; GFX1150-TRUE16-NEXT:    v_sub_nc_u32_e32 v9, v12, v13
; GFX1150-TRUE16-NEXT:    s_mov_b32 s2, 0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v9, 11, v9
; GFX1150-TRUE16-NEXT:  .LBB10_29: ; %frem.loop_body
; GFX1150-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_dual_mov_b32 v12, v10 :: v_dual_add_nc_u32 v9, -11, v9
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v10, v12, v11
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v10, v10
; GFX1150-TRUE16-NEXT:    v_fma_f32 v10, -v10, v8, v12
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v10
; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v13, v10, v8
; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v10, v10, v13, vcc_lo
; GFX1150-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v9
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v10, v10, 11
; GFX1150-TRUE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1150-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1150-TRUE16-NEXT:    s_cbranch_execnz .LBB10_29
; GFX1150-TRUE16-NEXT:  ; %bb.30: ; %Flow
; GFX1150-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v10, v12
; GFX1150-TRUE16-NEXT:  .LBB10_31: ; %Flow119
; GFX1150-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v9, -10, v9
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v9, v10, v9
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v10, v9, v11
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v10, v10
; GFX1150-TRUE16-NEXT:    v_fma_f32 v9, -v10, v8, v9
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v9
; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v8, v9, v8
; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v8, v9, v8, vcc_lo
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v7, v8, v7
; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v1.h
; GFX1150-TRUE16-NEXT:    v_cvt_f16_f32_e32 v7.l, v7
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_bfi_b32 v7, 0x7fff, v7, v8
; GFX1150-TRUE16-NEXT:  .LBB10_32: ; %Flow121
; GFX1150-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1150-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v2.l
; GFX1150-TRUE16-NEXT:    v_cmp_nge_f16_e64 s0, |v0.l|, 0x7c00
; GFX1150-TRUE16-NEXT:    s_and_b32 s0, s0, vcc_lo
; GFX1150-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v2.h
; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v4.l, s0
; GFX1150-TRUE16-NEXT:    v_cmp_nge_f16_e64 s0, |v0.h|, 0x7c00
; GFX1150-TRUE16-NEXT:    s_and_b32 s0, s0, vcc_lo
; GFX1150-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v3.l
; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v0.h, 0x7e00, v5.l, s0
; GFX1150-TRUE16-NEXT:    v_cmp_nge_f16_e64 s0, |v1.l|, 0x7c00
; GFX1150-TRUE16-NEXT:    s_and_b32 s0, s0, vcc_lo
; GFX1150-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v3.h
; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v1.l, 0x7e00, v6.l, s0
; GFX1150-TRUE16-NEXT:    v_cmp_nge_f16_e64 s0, |v1.h|, 0x7c00
; GFX1150-TRUE16-NEXT:    s_and_b32 s0, s0, vcc_lo
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v1.h, 0x7e00, v7.l, s0
; GFX1150-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-FAKE16-LABEL: frem_v4f16:
; GFX1150-FAKE16:       ; %bb.0:
; GFX1150-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-FAKE16-NEXT:    v_cvt_f32_f16_e64 v6, |v0|
; GFX1150-FAKE16-NEXT:    v_cvt_f32_f16_e64 v5, |v2|
; GFX1150-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX1150-FAKE16-NEXT:    ; implicit-def: $vgpr4
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cmpx_ngt_f32_e32 v6, v5
; GFX1150-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX1150-FAKE16-NEXT:  ; %bb.1: ; %frem.else86
; GFX1150-FAKE16-NEXT:    v_and_b32_e32 v4, 0x8000, v0
; GFX1150-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v6, v5
; GFX1150-FAKE16-NEXT:    ; implicit-def: $vgpr6
; GFX1150-FAKE16-NEXT:    ; implicit-def: $vgpr5
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v0, v4, vcc_lo
; GFX1150-FAKE16-NEXT:  ; %bb.2: ; %Flow132
; GFX1150-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1150-FAKE16-NEXT:    s_cbranch_execz .LBB10_8
; GFX1150-FAKE16-NEXT:  ; %bb.3: ; %frem.compute85
; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v9, v6
; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v4, v6
; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v6, v5
; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v10, v5
; GFX1150-FAKE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v7, v4, 11
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v5, v6, 1
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v4, -1, v10
; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v11, null, v5, v5, 1.0
; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v8, vcc_lo, 1.0, v5, 1.0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT:    v_xad_u32 v6, v4, -1, v9
; GFX1150-FAKE16-NEXT:    v_rcp_f32_e32 v12, v11
; GFX1150-FAKE16-NEXT:    s_denorm_mode 15
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fma_f32 v13, -v11, v12, 1.0
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v12, v13, v12
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v13, v8, v12
; GFX1150-FAKE16-NEXT:    v_fma_f32 v14, -v11, v13, v8
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v13, v14, v12
; GFX1150-FAKE16-NEXT:    v_fma_f32 v8, -v11, v13, v8
; GFX1150-FAKE16-NEXT:    s_denorm_mode 12
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_div_fmas_f32 v8, v8, v12, v13
; GFX1150-FAKE16-NEXT:    v_div_fixup_f32 v8, v8, v5, 1.0
; GFX1150-FAKE16-NEXT:    v_cmpx_lt_i32_e32 11, v6
; GFX1150-FAKE16-NEXT:    s_cbranch_execz .LBB10_7
; GFX1150-FAKE16-NEXT:  ; %bb.4: ; %frem.loop_body93.preheader
; GFX1150-FAKE16-NEXT:    v_sub_nc_u32_e32 v6, v9, v10
; GFX1150-FAKE16-NEXT:    s_mov_b32 s2, 0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v6, 11, v6
; GFX1150-FAKE16-NEXT:  .LBB10_5: ; %frem.loop_body93
; GFX1150-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_dual_mov_b32 v9, v7 :: v_dual_add_nc_u32 v6, -11, v6
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v7, v9, v8
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v7, v7
; GFX1150-FAKE16-NEXT:    v_fma_f32 v7, -v7, v5, v9
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v7
; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v10, v7, v5
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v7, v10, vcc_lo
; GFX1150-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v7, v7, 11
; GFX1150-FAKE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1150-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1150-FAKE16-NEXT:    s_cbranch_execnz .LBB10_5
; GFX1150-FAKE16-NEXT:  ; %bb.6: ; %Flow130
; GFX1150-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v7, v9
; GFX1150-FAKE16-NEXT:  .LBB10_7: ; %Flow131
; GFX1150-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v6, -10, v6
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v6, v7, v6
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v7, v6, v8
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v7, v7
; GFX1150-FAKE16-NEXT:    v_fma_f32 v6, -v7, v5, v6
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v6
; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v5, v6, v5
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc_lo
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX1150-FAKE16-NEXT:    v_cvt_f16_f32_e32 v4, v4
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_bfi_b32 v4, 0x7fff, v4, v0
; GFX1150-FAKE16-NEXT:  .LBB10_8: ; %Flow133
; GFX1150-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1150-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v0
; GFX1150-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
; GFX1150-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX1150-FAKE16-NEXT:    ; implicit-def: $vgpr7
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1150-FAKE16-NEXT:    v_cvt_f32_f16_e64 v9, |v5|
; GFX1150-FAKE16-NEXT:    v_cvt_f32_f16_e64 v8, |v6|
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cmpx_ngt_f32_e32 v9, v8
; GFX1150-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX1150-FAKE16-NEXT:  ; %bb.9: ; %frem.else53
; GFX1150-FAKE16-NEXT:    v_and_b32_e32 v7, 0x8000, v5
; GFX1150-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v9, v8
; GFX1150-FAKE16-NEXT:    ; implicit-def: $vgpr9
; GFX1150-FAKE16-NEXT:    ; implicit-def: $vgpr8
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v5, v7, vcc_lo
; GFX1150-FAKE16-NEXT:  ; %bb.10: ; %Flow128
; GFX1150-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1150-FAKE16-NEXT:    s_cbranch_execz .LBB10_16
; GFX1150-FAKE16-NEXT:  ; %bb.11: ; %frem.compute52
; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v12, v9
; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v7, v9
; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v9, v8
; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v13, v8
; GFX1150-FAKE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v10, v7, 11
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v8, v9, 1
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v7, -1, v13
; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v14, null, v8, v8, 1.0
; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v11, vcc_lo, 1.0, v8, 1.0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT:    v_xad_u32 v9, v7, -1, v12
; GFX1150-FAKE16-NEXT:    v_rcp_f32_e32 v15, v14
; GFX1150-FAKE16-NEXT:    s_denorm_mode 15
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fma_f32 v16, -v14, v15, 1.0
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v15, v16, v15
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v16, v11, v15
; GFX1150-FAKE16-NEXT:    v_fma_f32 v17, -v14, v16, v11
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v16, v17, v15
; GFX1150-FAKE16-NEXT:    v_fma_f32 v11, -v14, v16, v11
; GFX1150-FAKE16-NEXT:    s_denorm_mode 12
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_div_fmas_f32 v11, v11, v15, v16
; GFX1150-FAKE16-NEXT:    v_div_fixup_f32 v11, v11, v8, 1.0
; GFX1150-FAKE16-NEXT:    v_cmpx_lt_i32_e32 11, v9
; GFX1150-FAKE16-NEXT:    s_cbranch_execz .LBB10_15
; GFX1150-FAKE16-NEXT:  ; %bb.12: ; %frem.loop_body60.preheader
; GFX1150-FAKE16-NEXT:    v_sub_nc_u32_e32 v9, v12, v13
; GFX1150-FAKE16-NEXT:    s_mov_b32 s2, 0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v9, 11, v9
; GFX1150-FAKE16-NEXT:  .LBB10_13: ; %frem.loop_body60
; GFX1150-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_dual_mov_b32 v12, v10 :: v_dual_add_nc_u32 v9, -11, v9
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v10, v12, v11
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v10, v10
; GFX1150-FAKE16-NEXT:    v_fma_f32 v10, -v10, v8, v12
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v10
; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v13, v10, v8
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v10, v10, v13, vcc_lo
; GFX1150-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v9
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v10, v10, 11
; GFX1150-FAKE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1150-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1150-FAKE16-NEXT:    s_cbranch_execnz .LBB10_13
; GFX1150-FAKE16-NEXT:  ; %bb.14: ; %Flow126
; GFX1150-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v10, v12
; GFX1150-FAKE16-NEXT:  .LBB10_15: ; %Flow127
; GFX1150-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v9, -10, v9
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v9, v10, v9
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v10, v9, v11
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v10, v10
; GFX1150-FAKE16-NEXT:    v_fma_f32 v9, -v10, v8, v9
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v9
; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v8, v9, v8
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v9, v8, vcc_lo
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v7, v8, v7
; GFX1150-FAKE16-NEXT:    v_cvt_f16_f32_e32 v7, v7
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_bfi_b32 v7, 0x7fff, v7, v5
; GFX1150-FAKE16-NEXT:  .LBB10_16: ; %Flow129
; GFX1150-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1150-FAKE16-NEXT:    v_cvt_f32_f16_e64 v10, |v1|
; GFX1150-FAKE16-NEXT:    v_cvt_f32_f16_e64 v9, |v3|
; GFX1150-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX1150-FAKE16-NEXT:    ; implicit-def: $vgpr8
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cmpx_ngt_f32_e32 v10, v9
; GFX1150-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX1150-FAKE16-NEXT:  ; %bb.17: ; %frem.else20
; GFX1150-FAKE16-NEXT:    v_and_b32_e32 v8, 0x8000, v1
; GFX1150-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v10, v9
; GFX1150-FAKE16-NEXT:    ; implicit-def: $vgpr10
; GFX1150-FAKE16-NEXT:    ; implicit-def: $vgpr9
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v1, v8, vcc_lo
; GFX1150-FAKE16-NEXT:  ; %bb.18: ; %Flow124
; GFX1150-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1150-FAKE16-NEXT:    s_cbranch_execz .LBB10_24
; GFX1150-FAKE16-NEXT:  ; %bb.19: ; %frem.compute19
; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v13, v10
; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v8, v10
; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v10, v9
; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v14, v9
; GFX1150-FAKE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v11, v8, 11
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v9, v10, 1
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v8, -1, v14
; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v15, null, v9, v9, 1.0
; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v12, vcc_lo, 1.0, v9, 1.0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT:    v_xad_u32 v10, v8, -1, v13
; GFX1150-FAKE16-NEXT:    v_rcp_f32_e32 v16, v15
; GFX1150-FAKE16-NEXT:    s_denorm_mode 15
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fma_f32 v17, -v15, v16, 1.0
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v16, v17, v16
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v17, v12, v16
; GFX1150-FAKE16-NEXT:    v_fma_f32 v18, -v15, v17, v12
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v17, v18, v16
; GFX1150-FAKE16-NEXT:    v_fma_f32 v12, -v15, v17, v12
; GFX1150-FAKE16-NEXT:    s_denorm_mode 12
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_div_fmas_f32 v12, v12, v16, v17
; GFX1150-FAKE16-NEXT:    v_div_fixup_f32 v12, v12, v9, 1.0
; GFX1150-FAKE16-NEXT:    v_cmpx_lt_i32_e32 11, v10
; GFX1150-FAKE16-NEXT:    s_cbranch_execz .LBB10_23
; GFX1150-FAKE16-NEXT:  ; %bb.20: ; %frem.loop_body27.preheader
; GFX1150-FAKE16-NEXT:    v_sub_nc_u32_e32 v10, v13, v14
; GFX1150-FAKE16-NEXT:    s_mov_b32 s2, 0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v10, 11, v10
; GFX1150-FAKE16-NEXT:  .LBB10_21: ; %frem.loop_body27
; GFX1150-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_dual_mov_b32 v13, v11 :: v_dual_add_nc_u32 v10, -11, v10
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v11, v13, v12
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v11, v11
; GFX1150-FAKE16-NEXT:    v_fma_f32 v11, -v11, v9, v13
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v11
; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v14, v11, v9
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v11, v14, vcc_lo
; GFX1150-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v10
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v11, v11, 11
; GFX1150-FAKE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1150-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1150-FAKE16-NEXT:    s_cbranch_execnz .LBB10_21
; GFX1150-FAKE16-NEXT:  ; %bb.22: ; %Flow122
; GFX1150-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v11, v13
; GFX1150-FAKE16-NEXT:  .LBB10_23: ; %Flow123
; GFX1150-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v10, -10, v10
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v10, v11, v10
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v11, v10, v12
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v11, v11
; GFX1150-FAKE16-NEXT:    v_fma_f32 v10, -v11, v9, v10
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v10
; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v9, v10, v9
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v10, v9, vcc_lo
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v8, v9, v8
; GFX1150-FAKE16-NEXT:    v_cvt_f16_f32_e32 v8, v8
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_bfi_b32 v8, 0x7fff, v8, v1
; GFX1150-FAKE16-NEXT:  .LBB10_24: ; %Flow125
; GFX1150-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1150-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v1
; GFX1150-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v3
; GFX1150-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX1150-FAKE16-NEXT:    ; implicit-def: $vgpr11
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1150-FAKE16-NEXT:    v_cvt_f32_f16_e64 v13, |v9|
; GFX1150-FAKE16-NEXT:    v_cvt_f32_f16_e64 v12, |v10|
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cmpx_ngt_f32_e32 v13, v12
; GFX1150-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX1150-FAKE16-NEXT:  ; %bb.25: ; %frem.else
; GFX1150-FAKE16-NEXT:    v_and_b32_e32 v11, 0x8000, v9
; GFX1150-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v13, v12
; GFX1150-FAKE16-NEXT:    ; implicit-def: $vgpr13
; GFX1150-FAKE16-NEXT:    ; implicit-def: $vgpr12
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v9, v11, vcc_lo
; GFX1150-FAKE16-NEXT:  ; %bb.26: ; %Flow120
; GFX1150-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1150-FAKE16-NEXT:    s_cbranch_execz .LBB10_32
; GFX1150-FAKE16-NEXT:  ; %bb.27: ; %frem.compute
; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v16, v13
; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v11, v13
; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v13, v12
; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v17, v12
; GFX1150-FAKE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v14, v11, 11
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v12, v13, 1
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v11, -1, v17
; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v18, null, v12, v12, 1.0
; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v15, vcc_lo, 1.0, v12, 1.0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT:    v_xad_u32 v13, v11, -1, v16
; GFX1150-FAKE16-NEXT:    v_rcp_f32_e32 v19, v18
; GFX1150-FAKE16-NEXT:    s_denorm_mode 15
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fma_f32 v20, -v18, v19, 1.0
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v19, v20, v19
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v20, v15, v19
; GFX1150-FAKE16-NEXT:    v_fma_f32 v21, -v18, v20, v15
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v20, v21, v19
; GFX1150-FAKE16-NEXT:    v_fma_f32 v15, -v18, v20, v15
; GFX1150-FAKE16-NEXT:    s_denorm_mode 12
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_div_fmas_f32 v15, v15, v19, v20
; GFX1150-FAKE16-NEXT:    v_div_fixup_f32 v15, v15, v12, 1.0
; GFX1150-FAKE16-NEXT:    v_cmpx_lt_i32_e32 11, v13
; GFX1150-FAKE16-NEXT:    s_cbranch_execz .LBB10_31
; GFX1150-FAKE16-NEXT:  ; %bb.28: ; %frem.loop_body.preheader
; GFX1150-FAKE16-NEXT:    v_sub_nc_u32_e32 v13, v16, v17
; GFX1150-FAKE16-NEXT:    s_mov_b32 s2, 0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v13, 11, v13
; GFX1150-FAKE16-NEXT:  .LBB10_29: ; %frem.loop_body
; GFX1150-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_dual_mov_b32 v16, v14 :: v_dual_add_nc_u32 v13, -11, v13
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v14, v16, v15
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v14, v14
; GFX1150-FAKE16-NEXT:    v_fma_f32 v14, -v14, v12, v16
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v14
; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v17, v14, v12
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v14, v14, v17, vcc_lo
; GFX1150-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v13
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v14, v14, 11
; GFX1150-FAKE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1150-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1150-FAKE16-NEXT:    s_cbranch_execnz .LBB10_29
; GFX1150-FAKE16-NEXT:  ; %bb.30: ; %Flow
; GFX1150-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v14, v16
; GFX1150-FAKE16-NEXT:  .LBB10_31: ; %Flow119
; GFX1150-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v13, -10, v13
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v13, v14, v13
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v14, v13, v15
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v14, v14
; GFX1150-FAKE16-NEXT:    v_fma_f32 v13, -v14, v12, v13
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v13
; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v12, v13, v12
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v13, v12, vcc_lo
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v11, v12, v11
; GFX1150-FAKE16-NEXT:    v_cvt_f16_f32_e32 v11, v11
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_bfi_b32 v11, 0x7fff, v11, v9
; GFX1150-FAKE16-NEXT:  .LBB10_32: ; %Flow121
; GFX1150-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1150-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v2
; GFX1150-FAKE16-NEXT:    v_cmp_nge_f16_e64 s0, |v0|, 0x7c00
; GFX1150-FAKE16-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1150-FAKE16-NEXT:    v_cmp_nge_f16_e64 s0, |v5|, 0x7c00
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v4, vcc_lo
; GFX1150-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v6
; GFX1150-FAKE16-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1150-FAKE16-NEXT:    v_cmp_nge_f16_e64 s0, |v1|, 0x7c00
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v2, 0x7e00, v7, vcc_lo
; GFX1150-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v3
; GFX1150-FAKE16-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1150-FAKE16-NEXT:    v_cmp_nge_f16_e64 s0, |v9|, 0x7c00
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x7e00, v8, vcc_lo
; GFX1150-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v10
; GFX1150-FAKE16-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v3, 0x7e00, v11, vcc_lo
; GFX1150-FAKE16-NEXT:    v_perm_b32 v0, v2, v0, 0x5040100
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1150-FAKE16-NEXT:    v_perm_b32 v1, v3, v1, 0x5040100
; GFX1150-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-TRUE16-LABEL: frem_v4f16:
; GFX1200-TRUE16:       ; %bb.0:
; GFX1200-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1200-TRUE16-NEXT:    v_cvt_f32_f16_e64 v6, |v0.l|
; GFX1200-TRUE16-NEXT:    v_cvt_f32_f16_e64 v5, |v2.l|
; GFX1200-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX1200-TRUE16-NEXT:    ; implicit-def: $vgpr4_lo16
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cmpx_ngt_f32_e32 v6, v5
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX1200-TRUE16-NEXT:  ; %bb.1: ; %frem.else86
; GFX1200-TRUE16-NEXT:    v_and_b16 v4.l, 0x8000, v0.l
; GFX1200-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v6, v5
; GFX1200-TRUE16-NEXT:    ; implicit-def: $vgpr6
; GFX1200-TRUE16-NEXT:    ; implicit-def: $vgpr5
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v4.l, v0.l, v4.l, vcc_lo
; GFX1200-TRUE16-NEXT:  ; %bb.2: ; %Flow132
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1200-TRUE16-NEXT:    s_cbranch_execz .LBB10_8
; GFX1200-TRUE16-NEXT:  ; %bb.3: ; %frem.compute85
; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v9, v6
; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v4, v6
; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v6, v5
; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v10, v5
; GFX1200-TRUE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v7, v4, 11
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v5, v6, 1
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v11, null, v5, v5, 1.0
; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v8, vcc_lo, 1.0, v5, 1.0
; GFX1200-TRUE16-NEXT:    v_rcp_f32_e32 v12, v11
; GFX1200-TRUE16-NEXT:    s_denorm_mode 15
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f32 v13, -v11, v12, 1.0
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v12, v13, v12
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_dual_mul_f32 v13, v8, v12 :: v_dual_add_nc_u32 v4, -1, v10
; GFX1200-TRUE16-NEXT:    v_xad_u32 v6, v4, -1, v9
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f32 v14, -v11, v13, v8
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v13, v14, v12
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f32 v8, -v11, v13, v8
; GFX1200-TRUE16-NEXT:    s_denorm_mode 12
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    v_div_fmas_f32 v8, v8, v12, v13
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_div_fixup_f32 v8, v8, v5, 1.0
; GFX1200-TRUE16-NEXT:    v_cmpx_lt_i32_e32 11, v6
; GFX1200-TRUE16-NEXT:    s_cbranch_execz .LBB10_7
; GFX1200-TRUE16-NEXT:  ; %bb.4: ; %frem.loop_body93.preheader
; GFX1200-TRUE16-NEXT:    v_sub_nc_u32_e32 v6, v9, v10
; GFX1200-TRUE16-NEXT:    s_mov_b32 s2, 0
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v6, 11, v6
; GFX1200-TRUE16-NEXT:  .LBB10_5: ; %frem.loop_body93
; GFX1200-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_dual_mov_b32 v9, v7 :: v_dual_add_nc_u32 v6, -11, v6
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v7, v9, v8
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v7, v7
; GFX1200-TRUE16-NEXT:    v_fma_f32 v7, -v7, v5, v9
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v7
; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v10, v7, v5
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v7, v7, v10, vcc_lo
; GFX1200-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v7, v7, 11
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1200-TRUE16-NEXT:    s_cbranch_execnz .LBB10_5
; GFX1200-TRUE16-NEXT:  ; %bb.6: ; %Flow130
; GFX1200-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v7, v9
; GFX1200-TRUE16-NEXT:  .LBB10_7: ; %Flow131
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v6, -10, v6
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v6, v7, v6
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v7, v6, v8
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v7, v7
; GFX1200-TRUE16-NEXT:    v_fma_f32 v6, -v7, v5, v6
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v6
; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v5, v6, v5
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc_lo
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX1200-TRUE16-NEXT:    v_cvt_f16_f32_e32 v4.l, v4
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_bfi_b32 v4, 0x7fff, v4, v0
; GFX1200-TRUE16-NEXT:  .LBB10_8: ; %Flow133
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1200-TRUE16-NEXT:    v_cvt_f32_f16_e64 v7, |v0.h|
; GFX1200-TRUE16-NEXT:    v_cvt_f32_f16_e64 v6, |v2.h|
; GFX1200-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX1200-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cmpx_ngt_f32_e32 v7, v6
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX1200-TRUE16-NEXT:  ; %bb.9: ; %frem.else53
; GFX1200-TRUE16-NEXT:    v_and_b16 v4.h, 0x8000, v0.h
; GFX1200-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v7, v6
; GFX1200-TRUE16-NEXT:    ; implicit-def: $vgpr7
; GFX1200-TRUE16-NEXT:    ; implicit-def: $vgpr6
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v5.l, v0.h, v4.h, vcc_lo
; GFX1200-TRUE16-NEXT:  ; %bb.10: ; %Flow128
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1200-TRUE16-NEXT:    s_cbranch_execz .LBB10_16
; GFX1200-TRUE16-NEXT:  ; %bb.11: ; %frem.compute52
; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v10, v7
; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v5, v7
; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v7, v6
; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v11, v6
; GFX1200-TRUE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v8, v5, 11
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v6, v7, 1
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v12, null, v6, v6, 1.0
; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v9, vcc_lo, 1.0, v6, 1.0
; GFX1200-TRUE16-NEXT:    v_rcp_f32_e32 v13, v12
; GFX1200-TRUE16-NEXT:    s_denorm_mode 15
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f32 v14, -v12, v13, 1.0
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v13, v14, v13
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_dual_mul_f32 v14, v9, v13 :: v_dual_add_nc_u32 v5, -1, v11
; GFX1200-TRUE16-NEXT:    v_xad_u32 v7, v5, -1, v10
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f32 v15, -v12, v14, v9
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v14, v15, v13
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f32 v9, -v12, v14, v9
; GFX1200-TRUE16-NEXT:    s_denorm_mode 12
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    v_div_fmas_f32 v9, v9, v13, v14
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_div_fixup_f32 v9, v9, v6, 1.0
; GFX1200-TRUE16-NEXT:    v_cmpx_lt_i32_e32 11, v7
; GFX1200-TRUE16-NEXT:    s_cbranch_execz .LBB10_15
; GFX1200-TRUE16-NEXT:  ; %bb.12: ; %frem.loop_body60.preheader
; GFX1200-TRUE16-NEXT:    v_sub_nc_u32_e32 v7, v10, v11
; GFX1200-TRUE16-NEXT:    s_mov_b32 s2, 0
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v7, 11, v7
; GFX1200-TRUE16-NEXT:  .LBB10_13: ; %frem.loop_body60
; GFX1200-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_dual_mov_b32 v10, v8 :: v_dual_add_nc_u32 v7, -11, v7
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v8, v10, v9
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v8, v8
; GFX1200-TRUE16-NEXT:    v_fma_f32 v8, -v8, v6, v10
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v8
; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v11, v8, v6
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v8, v8, v11, vcc_lo
; GFX1200-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v7
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v8, v8, 11
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1200-TRUE16-NEXT:    s_cbranch_execnz .LBB10_13
; GFX1200-TRUE16-NEXT:  ; %bb.14: ; %Flow126
; GFX1200-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v8, v10
; GFX1200-TRUE16-NEXT:  .LBB10_15: ; %Flow127
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v7, -10, v7
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v7, v8, v7
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v8, v7, v9
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v8, v8
; GFX1200-TRUE16-NEXT:    v_fma_f32 v7, -v8, v6, v7
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v7
; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v6, v7, v6
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc_lo
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v5, v6, v5
; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v0.h
; GFX1200-TRUE16-NEXT:    v_cvt_f16_f32_e32 v5.l, v5
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_bfi_b32 v5, 0x7fff, v5, v6
; GFX1200-TRUE16-NEXT:  .LBB10_16: ; %Flow129
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1200-TRUE16-NEXT:    v_cvt_f32_f16_e64 v8, |v1.l|
; GFX1200-TRUE16-NEXT:    v_cvt_f32_f16_e64 v7, |v3.l|
; GFX1200-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX1200-TRUE16-NEXT:    ; implicit-def: $vgpr6_lo16
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cmpx_ngt_f32_e32 v8, v7
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX1200-TRUE16-NEXT:  ; %bb.17: ; %frem.else20
; GFX1200-TRUE16-NEXT:    v_and_b16 v4.h, 0x8000, v1.l
; GFX1200-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v8, v7
; GFX1200-TRUE16-NEXT:    ; implicit-def: $vgpr8
; GFX1200-TRUE16-NEXT:    ; implicit-def: $vgpr7
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v6.l, v1.l, v4.h, vcc_lo
; GFX1200-TRUE16-NEXT:  ; %bb.18: ; %Flow124
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1200-TRUE16-NEXT:    s_cbranch_execz .LBB10_24
; GFX1200-TRUE16-NEXT:  ; %bb.19: ; %frem.compute19
; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v11, v8
; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v6, v8
; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v8, v7
; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v12, v7
; GFX1200-TRUE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v9, v6, 11
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v7, v8, 1
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v13, null, v7, v7, 1.0
; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v10, vcc_lo, 1.0, v7, 1.0
; GFX1200-TRUE16-NEXT:    v_rcp_f32_e32 v14, v13
; GFX1200-TRUE16-NEXT:    s_denorm_mode 15
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f32 v15, -v13, v14, 1.0
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v14, v15, v14
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_dual_mul_f32 v15, v10, v14 :: v_dual_add_nc_u32 v6, -1, v12
; GFX1200-TRUE16-NEXT:    v_xad_u32 v8, v6, -1, v11
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f32 v16, -v13, v15, v10
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v15, v16, v14
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f32 v10, -v13, v15, v10
; GFX1200-TRUE16-NEXT:    s_denorm_mode 12
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    v_div_fmas_f32 v10, v10, v14, v15
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_div_fixup_f32 v10, v10, v7, 1.0
; GFX1200-TRUE16-NEXT:    v_cmpx_lt_i32_e32 11, v8
; GFX1200-TRUE16-NEXT:    s_cbranch_execz .LBB10_23
; GFX1200-TRUE16-NEXT:  ; %bb.20: ; %frem.loop_body27.preheader
; GFX1200-TRUE16-NEXT:    v_sub_nc_u32_e32 v8, v11, v12
; GFX1200-TRUE16-NEXT:    s_mov_b32 s2, 0
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v8, 11, v8
; GFX1200-TRUE16-NEXT:  .LBB10_21: ; %frem.loop_body27
; GFX1200-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_dual_mov_b32 v11, v9 :: v_dual_add_nc_u32 v8, -11, v8
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v9, v11, v10
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v9, v9
; GFX1200-TRUE16-NEXT:    v_fma_f32 v9, -v9, v7, v11
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v9
; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v12, v9, v7
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v9, v9, v12, vcc_lo
; GFX1200-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v8
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v9, v9, 11
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1200-TRUE16-NEXT:    s_cbranch_execnz .LBB10_21
; GFX1200-TRUE16-NEXT:  ; %bb.22: ; %Flow122
; GFX1200-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v9, v11
; GFX1200-TRUE16-NEXT:  .LBB10_23: ; %Flow123
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v8, -10, v8
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v8, v9, v8
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v9, v8, v10
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v9, v9
; GFX1200-TRUE16-NEXT:    v_fma_f32 v8, -v9, v7, v8
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v8
; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v7, v8, v7
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v7, v8, v7, vcc_lo
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v6, v7, v6
; GFX1200-TRUE16-NEXT:    v_cvt_f16_f32_e32 v6.l, v6
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_bfi_b32 v6, 0x7fff, v6, v1
; GFX1200-TRUE16-NEXT:  .LBB10_24: ; %Flow125
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1200-TRUE16-NEXT:    v_cvt_f32_f16_e64 v9, |v1.h|
; GFX1200-TRUE16-NEXT:    v_cvt_f32_f16_e64 v8, |v3.h|
; GFX1200-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX1200-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cmpx_ngt_f32_e32 v9, v8
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX1200-TRUE16-NEXT:  ; %bb.25: ; %frem.else
; GFX1200-TRUE16-NEXT:    v_and_b16 v4.h, 0x8000, v1.h
; GFX1200-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v9, v8
; GFX1200-TRUE16-NEXT:    ; implicit-def: $vgpr9
; GFX1200-TRUE16-NEXT:    ; implicit-def: $vgpr8
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v7.l, v1.h, v4.h, vcc_lo
; GFX1200-TRUE16-NEXT:  ; %bb.26: ; %Flow120
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1200-TRUE16-NEXT:    s_cbranch_execz .LBB10_32
; GFX1200-TRUE16-NEXT:  ; %bb.27: ; %frem.compute
; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v12, v9
; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v7, v9
; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v9, v8
; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v13, v8
; GFX1200-TRUE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v10, v7, 11
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v8, v9, 1
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v14, null, v8, v8, 1.0
; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v11, vcc_lo, 1.0, v8, 1.0
; GFX1200-TRUE16-NEXT:    v_rcp_f32_e32 v15, v14
; GFX1200-TRUE16-NEXT:    s_denorm_mode 15
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f32 v16, -v14, v15, 1.0
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v15, v16, v15
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_dual_mul_f32 v16, v11, v15 :: v_dual_add_nc_u32 v7, -1, v13
; GFX1200-TRUE16-NEXT:    v_xad_u32 v9, v7, -1, v12
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f32 v17, -v14, v16, v11
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v16, v17, v15
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f32 v11, -v14, v16, v11
; GFX1200-TRUE16-NEXT:    s_denorm_mode 12
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    v_div_fmas_f32 v11, v11, v15, v16
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_div_fixup_f32 v11, v11, v8, 1.0
; GFX1200-TRUE16-NEXT:    v_cmpx_lt_i32_e32 11, v9
; GFX1200-TRUE16-NEXT:    s_cbranch_execz .LBB10_31
; GFX1200-TRUE16-NEXT:  ; %bb.28: ; %frem.loop_body.preheader
; GFX1200-TRUE16-NEXT:    v_sub_nc_u32_e32 v9, v12, v13
; GFX1200-TRUE16-NEXT:    s_mov_b32 s2, 0
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v9, 11, v9
; GFX1200-TRUE16-NEXT:  .LBB10_29: ; %frem.loop_body
; GFX1200-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_dual_mov_b32 v12, v10 :: v_dual_add_nc_u32 v9, -11, v9
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v10, v12, v11
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v10, v10
; GFX1200-TRUE16-NEXT:    v_fma_f32 v10, -v10, v8, v12
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v10
; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v13, v10, v8
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v10, v10, v13, vcc_lo
; GFX1200-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v9
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v10, v10, 11
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1200-TRUE16-NEXT:    s_cbranch_execnz .LBB10_29
; GFX1200-TRUE16-NEXT:  ; %bb.30: ; %Flow
; GFX1200-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v10, v12
; GFX1200-TRUE16-NEXT:  .LBB10_31: ; %Flow119
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v9, -10, v9
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v9, v10, v9
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v10, v9, v11
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v10, v10
; GFX1200-TRUE16-NEXT:    v_fma_f32 v9, -v10, v8, v9
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v9
; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v8, v9, v8
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v8, v9, v8, vcc_lo
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v7, v8, v7
; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v1.h
; GFX1200-TRUE16-NEXT:    v_cvt_f16_f32_e32 v7.l, v7
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_bfi_b32 v7, 0x7fff, v7, v8
; GFX1200-TRUE16-NEXT:  .LBB10_32: ; %Flow121
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1200-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v2.l
; GFX1200-TRUE16-NEXT:    v_cmp_nge_f16_e64 s0, |v0.l|, 0x7c00
; GFX1200-TRUE16-NEXT:    s_and_b32 s0, s0, vcc_lo
; GFX1200-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v2.h
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v4.l, s0
; GFX1200-TRUE16-NEXT:    v_cmp_nge_f16_e64 s0, |v0.h|, 0x7c00
; GFX1200-TRUE16-NEXT:    s_and_b32 s0, s0, vcc_lo
; GFX1200-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v3.l
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v0.h, 0x7e00, v5.l, s0
; GFX1200-TRUE16-NEXT:    v_cmp_nge_f16_e64 s0, |v1.l|, 0x7c00
; GFX1200-TRUE16-NEXT:    s_and_b32 s0, s0, vcc_lo
; GFX1200-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v3.h
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v1.l, 0x7e00, v6.l, s0
; GFX1200-TRUE16-NEXT:    v_cmp_nge_f16_e64 s0, |v1.h|, 0x7c00
; GFX1200-TRUE16-NEXT:    s_and_b32 s0, s0, vcc_lo
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v1.h, 0x7e00, v7.l, s0
; GFX1200-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-FAKE16-LABEL: frem_v4f16:
; GFX1200-FAKE16:       ; %bb.0:
; GFX1200-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1200-FAKE16-NEXT:    v_cvt_f32_f16_e64 v6, |v0|
; GFX1200-FAKE16-NEXT:    v_cvt_f32_f16_e64 v5, |v2|
; GFX1200-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX1200-FAKE16-NEXT:    ; implicit-def: $vgpr4
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cmpx_ngt_f32_e32 v6, v5
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX1200-FAKE16-NEXT:  ; %bb.1: ; %frem.else86
; GFX1200-FAKE16-NEXT:    v_and_b32_e32 v4, 0x8000, v0
; GFX1200-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v6, v5
; GFX1200-FAKE16-NEXT:    ; implicit-def: $vgpr6
; GFX1200-FAKE16-NEXT:    ; implicit-def: $vgpr5
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v0, v4, vcc_lo
; GFX1200-FAKE16-NEXT:  ; %bb.2: ; %Flow132
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1200-FAKE16-NEXT:    s_cbranch_execz .LBB10_8
; GFX1200-FAKE16-NEXT:  ; %bb.3: ; %frem.compute85
; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v9, v6
; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v4, v6
; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v6, v5
; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v10, v5
; GFX1200-FAKE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v7, v4, 11
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v5, v6, 1
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v11, null, v5, v5, 1.0
; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v8, vcc_lo, 1.0, v5, 1.0
; GFX1200-FAKE16-NEXT:    v_rcp_f32_e32 v12, v11
; GFX1200-FAKE16-NEXT:    s_denorm_mode 15
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f32 v13, -v11, v12, 1.0
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v12, v13, v12
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_dual_mul_f32 v13, v8, v12 :: v_dual_add_nc_u32 v4, -1, v10
; GFX1200-FAKE16-NEXT:    v_xad_u32 v6, v4, -1, v9
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f32 v14, -v11, v13, v8
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v13, v14, v12
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f32 v8, -v11, v13, v8
; GFX1200-FAKE16-NEXT:    s_denorm_mode 12
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    v_div_fmas_f32 v8, v8, v12, v13
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_div_fixup_f32 v8, v8, v5, 1.0
; GFX1200-FAKE16-NEXT:    v_cmpx_lt_i32_e32 11, v6
; GFX1200-FAKE16-NEXT:    s_cbranch_execz .LBB10_7
; GFX1200-FAKE16-NEXT:  ; %bb.4: ; %frem.loop_body93.preheader
; GFX1200-FAKE16-NEXT:    v_sub_nc_u32_e32 v6, v9, v10
; GFX1200-FAKE16-NEXT:    s_mov_b32 s2, 0
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v6, 11, v6
; GFX1200-FAKE16-NEXT:  .LBB10_5: ; %frem.loop_body93
; GFX1200-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_dual_mov_b32 v9, v7 :: v_dual_add_nc_u32 v6, -11, v6
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v7, v9, v8
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v7, v7
; GFX1200-FAKE16-NEXT:    v_fma_f32 v7, -v7, v5, v9
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v7
; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v10, v7, v5
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v7, v10, vcc_lo
; GFX1200-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v7, v7, 11
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1200-FAKE16-NEXT:    s_cbranch_execnz .LBB10_5
; GFX1200-FAKE16-NEXT:  ; %bb.6: ; %Flow130
; GFX1200-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v7, v9
; GFX1200-FAKE16-NEXT:  .LBB10_7: ; %Flow131
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v6, -10, v6
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v6, v7, v6
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v7, v6, v8
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v7, v7
; GFX1200-FAKE16-NEXT:    v_fma_f32 v6, -v7, v5, v6
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v6
; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v5, v6, v5
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc_lo
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX1200-FAKE16-NEXT:    v_cvt_f16_f32_e32 v4, v4
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_bfi_b32 v4, 0x7fff, v4, v0
; GFX1200-FAKE16-NEXT:  .LBB10_8: ; %Flow133
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1200-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v0
; GFX1200-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
; GFX1200-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX1200-FAKE16-NEXT:    ; implicit-def: $vgpr7
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-FAKE16-NEXT:    v_cvt_f32_f16_e64 v9, |v5|
; GFX1200-FAKE16-NEXT:    v_cvt_f32_f16_e64 v8, |v6|
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cmpx_ngt_f32_e32 v9, v8
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX1200-FAKE16-NEXT:  ; %bb.9: ; %frem.else53
; GFX1200-FAKE16-NEXT:    v_and_b32_e32 v7, 0x8000, v5
; GFX1200-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v9, v8
; GFX1200-FAKE16-NEXT:    ; implicit-def: $vgpr9
; GFX1200-FAKE16-NEXT:    ; implicit-def: $vgpr8
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v5, v7, vcc_lo
; GFX1200-FAKE16-NEXT:  ; %bb.10: ; %Flow128
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1200-FAKE16-NEXT:    s_cbranch_execz .LBB10_16
; GFX1200-FAKE16-NEXT:  ; %bb.11: ; %frem.compute52
; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v12, v9
; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v7, v9
; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v9, v8
; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v13, v8
; GFX1200-FAKE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v10, v7, 11
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v8, v9, 1
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v14, null, v8, v8, 1.0
; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v11, vcc_lo, 1.0, v8, 1.0
; GFX1200-FAKE16-NEXT:    v_rcp_f32_e32 v15, v14
; GFX1200-FAKE16-NEXT:    s_denorm_mode 15
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f32 v16, -v14, v15, 1.0
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v15, v16, v15
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_dual_mul_f32 v16, v11, v15 :: v_dual_add_nc_u32 v7, -1, v13
; GFX1200-FAKE16-NEXT:    v_xad_u32 v9, v7, -1, v12
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f32 v17, -v14, v16, v11
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v16, v17, v15
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f32 v11, -v14, v16, v11
; GFX1200-FAKE16-NEXT:    s_denorm_mode 12
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    v_div_fmas_f32 v11, v11, v15, v16
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_div_fixup_f32 v11, v11, v8, 1.0
; GFX1200-FAKE16-NEXT:    v_cmpx_lt_i32_e32 11, v9
; GFX1200-FAKE16-NEXT:    s_cbranch_execz .LBB10_15
; GFX1200-FAKE16-NEXT:  ; %bb.12: ; %frem.loop_body60.preheader
; GFX1200-FAKE16-NEXT:    v_sub_nc_u32_e32 v9, v12, v13
; GFX1200-FAKE16-NEXT:    s_mov_b32 s2, 0
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v9, 11, v9
; GFX1200-FAKE16-NEXT:  .LBB10_13: ; %frem.loop_body60
; GFX1200-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_dual_mov_b32 v12, v10 :: v_dual_add_nc_u32 v9, -11, v9
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v10, v12, v11
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v10, v10
; GFX1200-FAKE16-NEXT:    v_fma_f32 v10, -v10, v8, v12
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v10
; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v13, v10, v8
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v10, v10, v13, vcc_lo
; GFX1200-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v9
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v10, v10, 11
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1200-FAKE16-NEXT:    s_cbranch_execnz .LBB10_13
; GFX1200-FAKE16-NEXT:  ; %bb.14: ; %Flow126
; GFX1200-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v10, v12
; GFX1200-FAKE16-NEXT:  .LBB10_15: ; %Flow127
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v9, -10, v9
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v9, v10, v9
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v10, v9, v11
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v10, v10
; GFX1200-FAKE16-NEXT:    v_fma_f32 v9, -v10, v8, v9
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v9
; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v8, v9, v8
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v9, v8, vcc_lo
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v7, v8, v7
; GFX1200-FAKE16-NEXT:    v_cvt_f16_f32_e32 v7, v7
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_bfi_b32 v7, 0x7fff, v7, v5
; GFX1200-FAKE16-NEXT:  .LBB10_16: ; %Flow129
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1200-FAKE16-NEXT:    v_cvt_f32_f16_e64 v10, |v1|
; GFX1200-FAKE16-NEXT:    v_cvt_f32_f16_e64 v9, |v3|
; GFX1200-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX1200-FAKE16-NEXT:    ; implicit-def: $vgpr8
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cmpx_ngt_f32_e32 v10, v9
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX1200-FAKE16-NEXT:  ; %bb.17: ; %frem.else20
; GFX1200-FAKE16-NEXT:    v_and_b32_e32 v8, 0x8000, v1
; GFX1200-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v10, v9
; GFX1200-FAKE16-NEXT:    ; implicit-def: $vgpr10
; GFX1200-FAKE16-NEXT:    ; implicit-def: $vgpr9
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v1, v8, vcc_lo
; GFX1200-FAKE16-NEXT:  ; %bb.18: ; %Flow124
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1200-FAKE16-NEXT:    s_cbranch_execz .LBB10_24
; GFX1200-FAKE16-NEXT:  ; %bb.19: ; %frem.compute19
; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v13, v10
; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v8, v10
; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v10, v9
; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v14, v9
; GFX1200-FAKE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v11, v8, 11
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v9, v10, 1
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v15, null, v9, v9, 1.0
; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v12, vcc_lo, 1.0, v9, 1.0
; GFX1200-FAKE16-NEXT:    v_rcp_f32_e32 v16, v15
; GFX1200-FAKE16-NEXT:    s_denorm_mode 15
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f32 v17, -v15, v16, 1.0
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v16, v17, v16
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_dual_mul_f32 v17, v12, v16 :: v_dual_add_nc_u32 v8, -1, v14
; GFX1200-FAKE16-NEXT:    v_xad_u32 v10, v8, -1, v13
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f32 v18, -v15, v17, v12
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v17, v18, v16
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f32 v12, -v15, v17, v12
; GFX1200-FAKE16-NEXT:    s_denorm_mode 12
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    v_div_fmas_f32 v12, v12, v16, v17
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_div_fixup_f32 v12, v12, v9, 1.0
; GFX1200-FAKE16-NEXT:    v_cmpx_lt_i32_e32 11, v10
; GFX1200-FAKE16-NEXT:    s_cbranch_execz .LBB10_23
; GFX1200-FAKE16-NEXT:  ; %bb.20: ; %frem.loop_body27.preheader
; GFX1200-FAKE16-NEXT:    v_sub_nc_u32_e32 v10, v13, v14
; GFX1200-FAKE16-NEXT:    s_mov_b32 s2, 0
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v10, 11, v10
; GFX1200-FAKE16-NEXT:  .LBB10_21: ; %frem.loop_body27
; GFX1200-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_dual_mov_b32 v13, v11 :: v_dual_add_nc_u32 v10, -11, v10
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v11, v13, v12
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v11, v11
; GFX1200-FAKE16-NEXT:    v_fma_f32 v11, -v11, v9, v13
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v11
; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v14, v11, v9
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v11, v14, vcc_lo
; GFX1200-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v10
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v11, v11, 11
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1200-FAKE16-NEXT:    s_cbranch_execnz .LBB10_21
; GFX1200-FAKE16-NEXT:  ; %bb.22: ; %Flow122
; GFX1200-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v11, v13
; GFX1200-FAKE16-NEXT:  .LBB10_23: ; %Flow123
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v10, -10, v10
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v10, v11, v10
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v11, v10, v12
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v11, v11
; GFX1200-FAKE16-NEXT:    v_fma_f32 v10, -v11, v9, v10
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v10
; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v9, v10, v9
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v10, v9, vcc_lo
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v8, v9, v8
; GFX1200-FAKE16-NEXT:    v_cvt_f16_f32_e32 v8, v8
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_bfi_b32 v8, 0x7fff, v8, v1
; GFX1200-FAKE16-NEXT:  .LBB10_24: ; %Flow125
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1200-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v1
; GFX1200-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v3
; GFX1200-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX1200-FAKE16-NEXT:    ; implicit-def: $vgpr11
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-FAKE16-NEXT:    v_cvt_f32_f16_e64 v13, |v9|
; GFX1200-FAKE16-NEXT:    v_cvt_f32_f16_e64 v12, |v10|
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cmpx_ngt_f32_e32 v13, v12
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX1200-FAKE16-NEXT:  ; %bb.25: ; %frem.else
; GFX1200-FAKE16-NEXT:    v_and_b32_e32 v11, 0x8000, v9
; GFX1200-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v13, v12
; GFX1200-FAKE16-NEXT:    ; implicit-def: $vgpr13
; GFX1200-FAKE16-NEXT:    ; implicit-def: $vgpr12
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v9, v11, vcc_lo
; GFX1200-FAKE16-NEXT:  ; %bb.26: ; %Flow120
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1200-FAKE16-NEXT:    s_cbranch_execz .LBB10_32
; GFX1200-FAKE16-NEXT:  ; %bb.27: ; %frem.compute
; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v16, v13
; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v11, v13
; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v13, v12
; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v17, v12
; GFX1200-FAKE16-NEXT:    s_mov_b32 s1, exec_lo
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v14, v11, 11
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v12, v13, 1
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v18, null, v12, v12, 1.0
; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v15, vcc_lo, 1.0, v12, 1.0
; GFX1200-FAKE16-NEXT:    v_rcp_f32_e32 v19, v18
; GFX1200-FAKE16-NEXT:    s_denorm_mode 15
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f32 v20, -v18, v19, 1.0
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v19, v20, v19
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_dual_mul_f32 v20, v15, v19 :: v_dual_add_nc_u32 v11, -1, v17
; GFX1200-FAKE16-NEXT:    v_xad_u32 v13, v11, -1, v16
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f32 v21, -v18, v20, v15
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v20, v21, v19
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f32 v15, -v18, v20, v15
; GFX1200-FAKE16-NEXT:    s_denorm_mode 12
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    v_div_fmas_f32 v15, v15, v19, v20
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_div_fixup_f32 v15, v15, v12, 1.0
; GFX1200-FAKE16-NEXT:    v_cmpx_lt_i32_e32 11, v13
; GFX1200-FAKE16-NEXT:    s_cbranch_execz .LBB10_31
; GFX1200-FAKE16-NEXT:  ; %bb.28: ; %frem.loop_body.preheader
; GFX1200-FAKE16-NEXT:    v_sub_nc_u32_e32 v13, v16, v17
; GFX1200-FAKE16-NEXT:    s_mov_b32 s2, 0
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v13, 11, v13
; GFX1200-FAKE16-NEXT:  .LBB10_29: ; %frem.loop_body
; GFX1200-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_dual_mov_b32 v16, v14 :: v_dual_add_nc_u32 v13, -11, v13
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v14, v16, v15
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v14, v14
; GFX1200-FAKE16-NEXT:    v_fma_f32 v14, -v14, v12, v16
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v14
; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v17, v14, v12
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v14, v14, v17, vcc_lo
; GFX1200-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v13
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v14, v14, 11
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1200-FAKE16-NEXT:    s_cbranch_execnz .LBB10_29
; GFX1200-FAKE16-NEXT:  ; %bb.30: ; %Flow
; GFX1200-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v14, v16
; GFX1200-FAKE16-NEXT:  .LBB10_31: ; %Flow119
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v13, -10, v13
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v13, v14, v13
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v14, v13, v15
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v14, v14
; GFX1200-FAKE16-NEXT:    v_fma_f32 v13, -v14, v12, v13
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v13
; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v12, v13, v12
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v13, v12, vcc_lo
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v11, v12, v11
; GFX1200-FAKE16-NEXT:    v_cvt_f16_f32_e32 v11, v11
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_bfi_b32 v11, 0x7fff, v11, v9
; GFX1200-FAKE16-NEXT:  .LBB10_32: ; %Flow121
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1200-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v2
; GFX1200-FAKE16-NEXT:    v_cmp_nge_f16_e64 s0, |v0|, 0x7c00
; GFX1200-FAKE16-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1200-FAKE16-NEXT:    v_cmp_nge_f16_e64 s0, |v5|, 0x7c00
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v4, vcc_lo
; GFX1200-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v6
; GFX1200-FAKE16-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1200-FAKE16-NEXT:    v_cmp_nge_f16_e64 s0, |v1|, 0x7c00
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v2, 0x7e00, v7, vcc_lo
; GFX1200-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v3
; GFX1200-FAKE16-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1200-FAKE16-NEXT:    v_cmp_nge_f16_e64 s0, |v9|, 0x7c00
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x7e00, v8, vcc_lo
; GFX1200-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v10
; GFX1200-FAKE16-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v3, 0x7e00, v11, vcc_lo
; GFX1200-FAKE16-NEXT:    v_perm_b32 v0, v2, v0, 0x5040100
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-FAKE16-NEXT:    v_perm_b32 v1, v3, v1, 0x5040100
; GFX1200-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %r2 = frem <4 x half> %in1, %in2
  ret <4 x half> %r2
}

define <2 x float> @frem_v2f32(<2 x float> %in1, <2 x float> %in2) #0 {
; SI-LABEL: frem_v2f32:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cmp_ngt_f32_e64 s[4:5], |v0|, |v2|
; SI-NEXT:    ; implicit-def: $vgpr4
; SI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; SI-NEXT:  ; %bb.1: ; %frem.else16
; SI-NEXT:    v_and_b32_e32 v4, 0x80000000, v0
; SI-NEXT:    v_cmp_eq_f32_e64 vcc, |v0|, |v2|
; SI-NEXT:    v_cndmask_b32_e32 v4, v0, v4, vcc
; SI-NEXT:  ; %bb.2: ; %Flow50
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB11_8
; SI-NEXT:  ; %bb.3: ; %frem.compute15
; SI-NEXT:    s_mov_b32 s6, 0x7f800000
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, s6
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v4, v0
; SI-NEXT:    v_cndmask_b32_e32 v9, 0, v4, vcc
; SI-NEXT:    v_frexp_mant_f32_e64 v4, |v0|
; SI-NEXT:    v_cndmask_b32_e64 v4, |v0|, v4, vcc
; SI-NEXT:    v_ldexp_f32_e64 v6, v4, 12
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v2|, s6
; SI-NEXT:    v_frexp_mant_f32_e64 v4, |v2|
; SI-NEXT:    v_cndmask_b32_e64 v5, |v2|, v4, vcc
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v4, v2
; SI-NEXT:    v_ldexp_f32_e64 v5, v5, 1
; SI-NEXT:    v_cndmask_b32_e32 v10, 0, v4, vcc
; SI-NEXT:    v_div_scale_f32 v11, s[6:7], v5, v5, 1.0
; SI-NEXT:    v_add_i32_e32 v4, vcc, -1, v10
; SI-NEXT:    v_rcp_f32_e32 v12, v11
; SI-NEXT:    v_not_b32_e32 v7, v4
; SI-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
; SI-NEXT:    v_div_scale_f32 v8, vcc, 1.0, v5, 1.0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    v_fma_f32 v13, -v11, v12, 1.0
; SI-NEXT:    v_fma_f32 v12, v13, v12, v12
; SI-NEXT:    v_mul_f32_e32 v13, v8, v12
; SI-NEXT:    v_fma_f32 v14, -v11, v13, v8
; SI-NEXT:    v_fma_f32 v13, v14, v12, v13
; SI-NEXT:    v_fma_f32 v8, -v11, v13, v8
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    v_div_fmas_f32 v8, v8, v12, v13
; SI-NEXT:    v_div_fixup_f32 v8, v8, v5, 1.0
; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v7
; SI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; SI-NEXT:    s_cbranch_execz .LBB11_7
; SI-NEXT:  ; %bb.4: ; %frem.loop_body23.preheader
; SI-NEXT:    v_sub_i32_e32 v7, vcc, v9, v10
; SI-NEXT:    v_add_i32_e32 v7, vcc, 12, v7
; SI-NEXT:    s_mov_b64 s[8:9], 0
; SI-NEXT:  .LBB11_5: ; %frem.loop_body23
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v9, v6
; SI-NEXT:    v_mul_f32_e32 v6, v9, v8
; SI-NEXT:    v_rndne_f32_e32 v6, v6
; SI-NEXT:    v_fma_f32 v6, -v6, v5, v9
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v6
; SI-NEXT:    v_add_f32_e32 v10, v6, v5
; SI-NEXT:    v_cndmask_b32_e32 v6, v6, v10, vcc
; SI-NEXT:    v_add_i32_e32 v7, vcc, -12, v7
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v7
; SI-NEXT:    v_ldexp_f32_e64 v6, v6, 12
; SI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; SI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; SI-NEXT:    s_cbranch_execnz .LBB11_5
; SI-NEXT:  ; %bb.6: ; %Flow48
; SI-NEXT:    s_or_b64 exec, exec, s[8:9]
; SI-NEXT:    v_mov_b32_e32 v6, v9
; SI-NEXT:  .LBB11_7: ; %Flow49
; SI-NEXT:    s_or_b64 exec, exec, s[6:7]
; SI-NEXT:    v_add_i32_e32 v7, vcc, -11, v7
; SI-NEXT:    v_ldexp_f32_e32 v6, v6, v7
; SI-NEXT:    v_mul_f32_e32 v7, v6, v8
; SI-NEXT:    v_rndne_f32_e32 v7, v7
; SI-NEXT:    v_fma_f32 v6, -v7, v5, v6
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v6
; SI-NEXT:    v_add_f32_e32 v5, v6, v5
; SI-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc
; SI-NEXT:    v_ldexp_f32_e32 v4, v5, v4
; SI-NEXT:    s_brev_b32 s6, -2
; SI-NEXT:    v_bfi_b32 v4, s6, v4, v0
; SI-NEXT:  .LBB11_8: ; %Flow51
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    v_cmp_ngt_f32_e64 s[4:5], |v1|, |v3|
; SI-NEXT:    ; implicit-def: $vgpr5
; SI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; SI-NEXT:  ; %bb.9: ; %frem.else
; SI-NEXT:    v_and_b32_e32 v5, 0x80000000, v1
; SI-NEXT:    v_cmp_eq_f32_e64 vcc, |v1|, |v3|
; SI-NEXT:    v_cndmask_b32_e32 v5, v1, v5, vcc
; SI-NEXT:  ; %bb.10: ; %Flow46
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB11_16
; SI-NEXT:  ; %bb.11: ; %frem.compute
; SI-NEXT:    s_mov_b32 s6, 0x7f800000
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v1|, s6
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v5, v1
; SI-NEXT:    v_cndmask_b32_e32 v10, 0, v5, vcc
; SI-NEXT:    v_frexp_mant_f32_e64 v5, |v1|
; SI-NEXT:    v_cndmask_b32_e64 v5, |v1|, v5, vcc
; SI-NEXT:    v_ldexp_f32_e64 v7, v5, 12
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v3|, s6
; SI-NEXT:    v_frexp_mant_f32_e64 v5, |v3|
; SI-NEXT:    v_cndmask_b32_e64 v6, |v3|, v5, vcc
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v5, v3
; SI-NEXT:    v_ldexp_f32_e64 v6, v6, 1
; SI-NEXT:    v_cndmask_b32_e32 v11, 0, v5, vcc
; SI-NEXT:    v_div_scale_f32 v12, s[6:7], v6, v6, 1.0
; SI-NEXT:    v_add_i32_e32 v5, vcc, -1, v11
; SI-NEXT:    v_rcp_f32_e32 v13, v12
; SI-NEXT:    v_not_b32_e32 v8, v5
; SI-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
; SI-NEXT:    v_div_scale_f32 v9, vcc, 1.0, v6, 1.0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    v_fma_f32 v14, -v12, v13, 1.0
; SI-NEXT:    v_fma_f32 v13, v14, v13, v13
; SI-NEXT:    v_mul_f32_e32 v14, v9, v13
; SI-NEXT:    v_fma_f32 v15, -v12, v14, v9
; SI-NEXT:    v_fma_f32 v14, v15, v13, v14
; SI-NEXT:    v_fma_f32 v9, -v12, v14, v9
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    v_div_fmas_f32 v9, v9, v13, v14
; SI-NEXT:    v_div_fixup_f32 v9, v9, v6, 1.0
; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v8
; SI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; SI-NEXT:    s_cbranch_execz .LBB11_15
; SI-NEXT:  ; %bb.12: ; %frem.loop_body.preheader
; SI-NEXT:    v_sub_i32_e32 v8, vcc, v10, v11
; SI-NEXT:    v_add_i32_e32 v8, vcc, 12, v8
; SI-NEXT:    s_mov_b64 s[8:9], 0
; SI-NEXT:  .LBB11_13: ; %frem.loop_body
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v10, v7
; SI-NEXT:    v_mul_f32_e32 v7, v10, v9
; SI-NEXT:    v_rndne_f32_e32 v7, v7
; SI-NEXT:    v_fma_f32 v7, -v7, v6, v10
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v7
; SI-NEXT:    v_add_f32_e32 v11, v7, v6
; SI-NEXT:    v_cndmask_b32_e32 v7, v7, v11, vcc
; SI-NEXT:    v_add_i32_e32 v8, vcc, -12, v8
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v8
; SI-NEXT:    v_ldexp_f32_e64 v7, v7, 12
; SI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; SI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; SI-NEXT:    s_cbranch_execnz .LBB11_13
; SI-NEXT:  ; %bb.14: ; %Flow
; SI-NEXT:    s_or_b64 exec, exec, s[8:9]
; SI-NEXT:    v_mov_b32_e32 v7, v10
; SI-NEXT:  .LBB11_15: ; %Flow45
; SI-NEXT:    s_or_b64 exec, exec, s[6:7]
; SI-NEXT:    v_add_i32_e32 v8, vcc, -11, v8
; SI-NEXT:    v_ldexp_f32_e32 v7, v7, v8
; SI-NEXT:    v_mul_f32_e32 v8, v7, v9
; SI-NEXT:    v_rndne_f32_e32 v8, v8
; SI-NEXT:    v_fma_f32 v7, -v8, v6, v7
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v7
; SI-NEXT:    v_add_f32_e32 v6, v7, v6
; SI-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc
; SI-NEXT:    v_ldexp_f32_e32 v5, v6, v5
; SI-NEXT:    s_brev_b32 s6, -2
; SI-NEXT:    v_bfi_b32 v5, s6, v5, v1
; SI-NEXT:  .LBB11_16: ; %Flow47
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    s_mov_b32 s6, 0x7f800000
; SI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v2
; SI-NEXT:    v_cmp_nge_f32_e64 s[4:5], |v0|, s6
; SI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; SI-NEXT:    v_mov_b32_e32 v2, 0x7fc00000
; SI-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc
; SI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v3
; SI-NEXT:    v_cmp_nge_f32_e64 s[4:5], |v1|, s6
; SI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; SI-NEXT:    v_cndmask_b32_e32 v1, v2, v5, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; CI-LABEL: frem_v2f32:
; CI:       ; %bb.0:
; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-NEXT:    v_cmp_ngt_f32_e64 s[4:5], |v0|, |v2|
; CI-NEXT:    ; implicit-def: $vgpr4
; CI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; CI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; CI-NEXT:  ; %bb.1: ; %frem.else16
; CI-NEXT:    v_and_b32_e32 v4, 0x80000000, v0
; CI-NEXT:    v_cmp_eq_f32_e64 vcc, |v0|, |v2|
; CI-NEXT:    v_cndmask_b32_e32 v4, v0, v4, vcc
; CI-NEXT:  ; %bb.2: ; %Flow50
; CI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; CI-NEXT:    s_cbranch_execz .LBB11_8
; CI-NEXT:  ; %bb.3: ; %frem.compute15
; CI-NEXT:    v_frexp_mant_f32_e64 v5, |v2|
; CI-NEXT:    v_ldexp_f32_e64 v5, v5, 1
; CI-NEXT:    v_div_scale_f32 v11, s[6:7], v5, v5, 1.0
; CI-NEXT:    v_frexp_mant_f32_e64 v4, |v0|
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v10, v2
; CI-NEXT:    v_ldexp_f32_e64 v7, v4, 12
; CI-NEXT:    v_add_i32_e32 v4, vcc, -1, v10
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v9, v0
; CI-NEXT:    v_not_b32_e32 v6, v4
; CI-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
; CI-NEXT:    v_div_scale_f32 v8, vcc, 1.0, v5, 1.0
; CI-NEXT:    v_rcp_f32_e32 v12, v11
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v13, -v11, v12, 1.0
; CI-NEXT:    v_fma_f32 v12, v13, v12, v12
; CI-NEXT:    v_mul_f32_e32 v13, v8, v12
; CI-NEXT:    v_fma_f32 v14, -v11, v13, v8
; CI-NEXT:    v_fma_f32 v13, v14, v12, v13
; CI-NEXT:    v_fma_f32 v8, -v11, v13, v8
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v8, v8, v12, v13
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v6
; CI-NEXT:    v_div_fixup_f32 v8, v8, v5, 1.0
; CI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; CI-NEXT:    s_cbranch_execz .LBB11_7
; CI-NEXT:  ; %bb.4: ; %frem.loop_body23.preheader
; CI-NEXT:    v_sub_i32_e32 v6, vcc, v9, v10
; CI-NEXT:    v_add_i32_e32 v6, vcc, 12, v6
; CI-NEXT:    s_mov_b64 s[8:9], 0
; CI-NEXT:  .LBB11_5: ; %frem.loop_body23
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v9, v7
; CI-NEXT:    v_mul_f32_e32 v7, v9, v8
; CI-NEXT:    v_rndne_f32_e32 v7, v7
; CI-NEXT:    v_fma_f32 v7, -v7, v5, v9
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v7
; CI-NEXT:    v_add_f32_e32 v10, v7, v5
; CI-NEXT:    v_cndmask_b32_e32 v7, v7, v10, vcc
; CI-NEXT:    v_add_i32_e32 v6, vcc, -12, v6
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v6
; CI-NEXT:    v_ldexp_f32_e64 v7, v7, 12
; CI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; CI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; CI-NEXT:    s_cbranch_execnz .LBB11_5
; CI-NEXT:  ; %bb.6: ; %Flow48
; CI-NEXT:    s_or_b64 exec, exec, s[8:9]
; CI-NEXT:    v_mov_b32_e32 v7, v9
; CI-NEXT:  .LBB11_7: ; %Flow49
; CI-NEXT:    s_or_b64 exec, exec, s[6:7]
; CI-NEXT:    v_add_i32_e32 v6, vcc, -11, v6
; CI-NEXT:    v_ldexp_f32_e32 v6, v7, v6
; CI-NEXT:    v_mul_f32_e32 v7, v6, v8
; CI-NEXT:    v_rndne_f32_e32 v7, v7
; CI-NEXT:    v_fma_f32 v6, -v7, v5, v6
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v6
; CI-NEXT:    v_add_f32_e32 v5, v6, v5
; CI-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc
; CI-NEXT:    v_ldexp_f32_e32 v4, v5, v4
; CI-NEXT:    s_brev_b32 s6, -2
; CI-NEXT:    v_bfi_b32 v4, s6, v4, v0
; CI-NEXT:  .LBB11_8: ; %Flow51
; CI-NEXT:    s_or_b64 exec, exec, s[4:5]
; CI-NEXT:    v_cmp_ngt_f32_e64 s[4:5], |v1|, |v3|
; CI-NEXT:    ; implicit-def: $vgpr5
; CI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; CI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; CI-NEXT:  ; %bb.9: ; %frem.else
; CI-NEXT:    v_and_b32_e32 v5, 0x80000000, v1
; CI-NEXT:    v_cmp_eq_f32_e64 vcc, |v1|, |v3|
; CI-NEXT:    v_cndmask_b32_e32 v5, v1, v5, vcc
; CI-NEXT:  ; %bb.10: ; %Flow46
; CI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; CI-NEXT:    s_cbranch_execz .LBB11_16
; CI-NEXT:  ; %bb.11: ; %frem.compute
; CI-NEXT:    v_frexp_mant_f32_e64 v6, |v3|
; CI-NEXT:    v_ldexp_f32_e64 v6, v6, 1
; CI-NEXT:    v_div_scale_f32 v12, s[6:7], v6, v6, 1.0
; CI-NEXT:    v_frexp_mant_f32_e64 v5, |v1|
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v11, v3
; CI-NEXT:    v_ldexp_f32_e64 v8, v5, 12
; CI-NEXT:    v_add_i32_e32 v5, vcc, -1, v11
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v10, v1
; CI-NEXT:    v_not_b32_e32 v7, v5
; CI-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
; CI-NEXT:    v_div_scale_f32 v9, vcc, 1.0, v6, 1.0
; CI-NEXT:    v_rcp_f32_e32 v13, v12
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v14, -v12, v13, 1.0
; CI-NEXT:    v_fma_f32 v13, v14, v13, v13
; CI-NEXT:    v_mul_f32_e32 v14, v9, v13
; CI-NEXT:    v_fma_f32 v15, -v12, v14, v9
; CI-NEXT:    v_fma_f32 v14, v15, v13, v14
; CI-NEXT:    v_fma_f32 v9, -v12, v14, v9
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v9, v9, v13, v14
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v7
; CI-NEXT:    v_div_fixup_f32 v9, v9, v6, 1.0
; CI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; CI-NEXT:    s_cbranch_execz .LBB11_15
; CI-NEXT:  ; %bb.12: ; %frem.loop_body.preheader
; CI-NEXT:    v_sub_i32_e32 v7, vcc, v10, v11
; CI-NEXT:    v_add_i32_e32 v7, vcc, 12, v7
; CI-NEXT:    s_mov_b64 s[8:9], 0
; CI-NEXT:  .LBB11_13: ; %frem.loop_body
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v10, v8
; CI-NEXT:    v_mul_f32_e32 v8, v10, v9
; CI-NEXT:    v_rndne_f32_e32 v8, v8
; CI-NEXT:    v_fma_f32 v8, -v8, v6, v10
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v8
; CI-NEXT:    v_add_f32_e32 v11, v8, v6
; CI-NEXT:    v_cndmask_b32_e32 v8, v8, v11, vcc
; CI-NEXT:    v_add_i32_e32 v7, vcc, -12, v7
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v7
; CI-NEXT:    v_ldexp_f32_e64 v8, v8, 12
; CI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; CI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; CI-NEXT:    s_cbranch_execnz .LBB11_13
; CI-NEXT:  ; %bb.14: ; %Flow
; CI-NEXT:    s_or_b64 exec, exec, s[8:9]
; CI-NEXT:    v_mov_b32_e32 v8, v10
; CI-NEXT:  .LBB11_15: ; %Flow45
; CI-NEXT:    s_or_b64 exec, exec, s[6:7]
; CI-NEXT:    v_add_i32_e32 v7, vcc, -11, v7
; CI-NEXT:    v_ldexp_f32_e32 v7, v8, v7
; CI-NEXT:    v_mul_f32_e32 v8, v7, v9
; CI-NEXT:    v_rndne_f32_e32 v8, v8
; CI-NEXT:    v_fma_f32 v7, -v8, v6, v7
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v7
; CI-NEXT:    v_add_f32_e32 v6, v7, v6
; CI-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc
; CI-NEXT:    v_ldexp_f32_e32 v5, v6, v5
; CI-NEXT:    s_brev_b32 s6, -2
; CI-NEXT:    v_bfi_b32 v5, s6, v5, v1
; CI-NEXT:  .LBB11_16: ; %Flow47
; CI-NEXT:    s_or_b64 exec, exec, s[4:5]
; CI-NEXT:    s_mov_b32 s6, 0x7f800000
; CI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v2
; CI-NEXT:    v_cmp_nge_f32_e64 s[4:5], |v0|, s6
; CI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; CI-NEXT:    v_mov_b32_e32 v2, 0x7fc00000
; CI-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc
; CI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v3
; CI-NEXT:    v_cmp_nge_f32_e64 s[4:5], |v1|, s6
; CI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; CI-NEXT:    v_cndmask_b32_e32 v1, v2, v5, vcc
; CI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: frem_v2f32:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ngt_f32_e64 s[4:5], |v0|, |v2|
; VI-NEXT:    ; implicit-def: $vgpr4
; VI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; VI-NEXT:  ; %bb.1: ; %frem.else16
; VI-NEXT:    v_and_b32_e32 v4, 0x80000000, v0
; VI-NEXT:    v_cmp_eq_f32_e64 vcc, |v0|, |v2|
; VI-NEXT:    v_cndmask_b32_e32 v4, v0, v4, vcc
; VI-NEXT:  ; %bb.2: ; %Flow50
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB11_8
; VI-NEXT:  ; %bb.3: ; %frem.compute15
; VI-NEXT:    v_frexp_mant_f32_e64 v5, |v2|
; VI-NEXT:    v_ldexp_f32 v5, v5, 1
; VI-NEXT:    v_div_scale_f32 v11, s[6:7], v5, v5, 1.0
; VI-NEXT:    v_frexp_mant_f32_e64 v4, |v0|
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v10, v2
; VI-NEXT:    v_ldexp_f32 v7, v4, 12
; VI-NEXT:    v_add_u32_e32 v4, vcc, -1, v10
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v9, v0
; VI-NEXT:    v_not_b32_e32 v6, v4
; VI-NEXT:    v_add_u32_e32 v6, vcc, v6, v9
; VI-NEXT:    v_div_scale_f32 v8, vcc, 1.0, v5, 1.0
; VI-NEXT:    v_rcp_f32_e32 v12, v11
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT:    v_fma_f32 v13, -v11, v12, 1.0
; VI-NEXT:    v_fma_f32 v12, v13, v12, v12
; VI-NEXT:    v_mul_f32_e32 v13, v8, v12
; VI-NEXT:    v_fma_f32 v14, -v11, v13, v8
; VI-NEXT:    v_fma_f32 v13, v14, v12, v13
; VI-NEXT:    v_fma_f32 v8, -v11, v13, v8
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; VI-NEXT:    v_div_fmas_f32 v8, v8, v12, v13
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v6
; VI-NEXT:    v_div_fixup_f32 v8, v8, v5, 1.0
; VI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; VI-NEXT:    s_cbranch_execz .LBB11_7
; VI-NEXT:  ; %bb.4: ; %frem.loop_body23.preheader
; VI-NEXT:    v_sub_u32_e32 v6, vcc, v9, v10
; VI-NEXT:    v_add_u32_e32 v6, vcc, 12, v6
; VI-NEXT:    s_mov_b64 s[8:9], 0
; VI-NEXT:  .LBB11_5: ; %frem.loop_body23
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v9, v7
; VI-NEXT:    v_mul_f32_e32 v7, v9, v8
; VI-NEXT:    v_rndne_f32_e32 v7, v7
; VI-NEXT:    v_fma_f32 v7, -v7, v5, v9
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v7
; VI-NEXT:    v_add_f32_e32 v10, v7, v5
; VI-NEXT:    v_cndmask_b32_e32 v7, v7, v10, vcc
; VI-NEXT:    v_add_u32_e32 v6, vcc, -12, v6
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v6
; VI-NEXT:    v_ldexp_f32 v7, v7, 12
; VI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; VI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; VI-NEXT:    s_cbranch_execnz .LBB11_5
; VI-NEXT:  ; %bb.6: ; %Flow48
; VI-NEXT:    s_or_b64 exec, exec, s[8:9]
; VI-NEXT:    v_mov_b32_e32 v7, v9
; VI-NEXT:  .LBB11_7: ; %Flow49
; VI-NEXT:    s_or_b64 exec, exec, s[6:7]
; VI-NEXT:    v_add_u32_e32 v6, vcc, -11, v6
; VI-NEXT:    v_ldexp_f32 v6, v7, v6
; VI-NEXT:    v_mul_f32_e32 v7, v6, v8
; VI-NEXT:    v_rndne_f32_e32 v7, v7
; VI-NEXT:    v_fma_f32 v6, -v7, v5, v6
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v6
; VI-NEXT:    v_add_f32_e32 v5, v6, v5
; VI-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc
; VI-NEXT:    v_ldexp_f32 v4, v5, v4
; VI-NEXT:    s_brev_b32 s6, -2
; VI-NEXT:    v_bfi_b32 v4, s6, v4, v0
; VI-NEXT:  .LBB11_8: ; %Flow51
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    v_cmp_ngt_f32_e64 s[4:5], |v1|, |v3|
; VI-NEXT:    ; implicit-def: $vgpr5
; VI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; VI-NEXT:  ; %bb.9: ; %frem.else
; VI-NEXT:    v_and_b32_e32 v5, 0x80000000, v1
; VI-NEXT:    v_cmp_eq_f32_e64 vcc, |v1|, |v3|
; VI-NEXT:    v_cndmask_b32_e32 v5, v1, v5, vcc
; VI-NEXT:  ; %bb.10: ; %Flow46
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB11_16
; VI-NEXT:  ; %bb.11: ; %frem.compute
; VI-NEXT:    v_frexp_mant_f32_e64 v6, |v3|
; VI-NEXT:    v_ldexp_f32 v6, v6, 1
; VI-NEXT:    v_div_scale_f32 v12, s[6:7], v6, v6, 1.0
; VI-NEXT:    v_frexp_mant_f32_e64 v5, |v1|
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v11, v3
; VI-NEXT:    v_ldexp_f32 v8, v5, 12
; VI-NEXT:    v_add_u32_e32 v5, vcc, -1, v11
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v10, v1
; VI-NEXT:    v_not_b32_e32 v7, v5
; VI-NEXT:    v_add_u32_e32 v7, vcc, v7, v10
; VI-NEXT:    v_div_scale_f32 v9, vcc, 1.0, v6, 1.0
; VI-NEXT:    v_rcp_f32_e32 v13, v12
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT:    v_fma_f32 v14, -v12, v13, 1.0
; VI-NEXT:    v_fma_f32 v13, v14, v13, v13
; VI-NEXT:    v_mul_f32_e32 v14, v9, v13
; VI-NEXT:    v_fma_f32 v15, -v12, v14, v9
; VI-NEXT:    v_fma_f32 v14, v15, v13, v14
; VI-NEXT:    v_fma_f32 v9, -v12, v14, v9
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; VI-NEXT:    v_div_fmas_f32 v9, v9, v13, v14
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v7
; VI-NEXT:    v_div_fixup_f32 v9, v9, v6, 1.0
; VI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; VI-NEXT:    s_cbranch_execz .LBB11_15
; VI-NEXT:  ; %bb.12: ; %frem.loop_body.preheader
; VI-NEXT:    v_sub_u32_e32 v7, vcc, v10, v11
; VI-NEXT:    v_add_u32_e32 v7, vcc, 12, v7
; VI-NEXT:    s_mov_b64 s[8:9], 0
; VI-NEXT:  .LBB11_13: ; %frem.loop_body
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v10, v8
; VI-NEXT:    v_mul_f32_e32 v8, v10, v9
; VI-NEXT:    v_rndne_f32_e32 v8, v8
; VI-NEXT:    v_fma_f32 v8, -v8, v6, v10
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v8
; VI-NEXT:    v_add_f32_e32 v11, v8, v6
; VI-NEXT:    v_cndmask_b32_e32 v8, v8, v11, vcc
; VI-NEXT:    v_add_u32_e32 v7, vcc, -12, v7
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v7
; VI-NEXT:    v_ldexp_f32 v8, v8, 12
; VI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; VI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; VI-NEXT:    s_cbranch_execnz .LBB11_13
; VI-NEXT:  ; %bb.14: ; %Flow
; VI-NEXT:    s_or_b64 exec, exec, s[8:9]
; VI-NEXT:    v_mov_b32_e32 v8, v10
; VI-NEXT:  .LBB11_15: ; %Flow45
; VI-NEXT:    s_or_b64 exec, exec, s[6:7]
; VI-NEXT:    v_add_u32_e32 v7, vcc, -11, v7
; VI-NEXT:    v_ldexp_f32 v7, v8, v7
; VI-NEXT:    v_mul_f32_e32 v8, v7, v9
; VI-NEXT:    v_rndne_f32_e32 v8, v8
; VI-NEXT:    v_fma_f32 v7, -v8, v6, v7
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v7
; VI-NEXT:    v_add_f32_e32 v6, v7, v6
; VI-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc
; VI-NEXT:    v_ldexp_f32 v5, v6, v5
; VI-NEXT:    s_brev_b32 s6, -2
; VI-NEXT:    v_bfi_b32 v5, s6, v5, v1
; VI-NEXT:  .LBB11_16: ; %Flow47
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_mov_b32 s6, 0x7f800000
; VI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v2
; VI-NEXT:    v_cmp_nge_f32_e64 s[4:5], |v0|, s6
; VI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; VI-NEXT:    v_mov_b32_e32 v2, 0x7fc00000
; VI-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc
; VI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v3
; VI-NEXT:    v_cmp_nge_f32_e64 s[4:5], |v1|, s6
; VI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; VI-NEXT:    v_cndmask_b32_e32 v1, v2, v5, vcc
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: frem_v2f32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ngt_f32_e64 s[4:5], |v0|, |v2|
; GFX9-NEXT:    ; implicit-def: $vgpr4
; GFX9-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; GFX9-NEXT:  ; %bb.1: ; %frem.else16
; GFX9-NEXT:    v_and_b32_e32 v4, 0x80000000, v0
; GFX9-NEXT:    v_cmp_eq_f32_e64 vcc, |v0|, |v2|
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v0, v4, vcc
; GFX9-NEXT:  ; %bb.2: ; %Flow50
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB11_8
; GFX9-NEXT:  ; %bb.3: ; %frem.compute15
; GFX9-NEXT:    v_frexp_mant_f32_e64 v5, |v2|
; GFX9-NEXT:    v_ldexp_f32 v5, v5, 1
; GFX9-NEXT:    v_div_scale_f32 v11, s[6:7], v5, v5, 1.0
; GFX9-NEXT:    v_div_scale_f32 v8, vcc, 1.0, v5, 1.0
; GFX9-NEXT:    v_frexp_mant_f32_e64 v4, |v0|
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v9, v0
; GFX9-NEXT:    v_ldexp_f32 v7, v4, 12
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v10, v2
; GFX9-NEXT:    v_add_u32_e32 v4, -1, v10
; GFX9-NEXT:    v_xad_u32 v6, v4, -1, v9
; GFX9-NEXT:    v_rcp_f32_e32 v12, v11
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT:    v_fma_f32 v13, -v11, v12, 1.0
; GFX9-NEXT:    v_fma_f32 v12, v13, v12, v12
; GFX9-NEXT:    v_mul_f32_e32 v13, v8, v12
; GFX9-NEXT:    v_fma_f32 v14, -v11, v13, v8
; GFX9-NEXT:    v_fma_f32 v13, v14, v12, v13
; GFX9-NEXT:    v_fma_f32 v8, -v11, v13, v8
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX9-NEXT:    v_div_fmas_f32 v8, v8, v12, v13
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v6
; GFX9-NEXT:    v_div_fixup_f32 v8, v8, v5, 1.0
; GFX9-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; GFX9-NEXT:    s_cbranch_execz .LBB11_7
; GFX9-NEXT:  ; %bb.4: ; %frem.loop_body23.preheader
; GFX9-NEXT:    v_sub_u32_e32 v6, v9, v10
; GFX9-NEXT:    v_add_u32_e32 v6, 12, v6
; GFX9-NEXT:    s_mov_b64 s[8:9], 0
; GFX9-NEXT:  .LBB11_5: ; %frem.loop_body23
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v9, v7
; GFX9-NEXT:    v_mul_f32_e32 v7, v9, v8
; GFX9-NEXT:    v_rndne_f32_e32 v7, v7
; GFX9-NEXT:    v_fma_f32 v7, -v7, v5, v9
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v7
; GFX9-NEXT:    v_add_f32_e32 v10, v7, v5
; GFX9-NEXT:    v_add_u32_e32 v6, -12, v6
; GFX9-NEXT:    v_cndmask_b32_e32 v7, v7, v10, vcc
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v6
; GFX9-NEXT:    v_ldexp_f32 v7, v7, 12
; GFX9-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; GFX9-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; GFX9-NEXT:    s_cbranch_execnz .LBB11_5
; GFX9-NEXT:  ; %bb.6: ; %Flow48
; GFX9-NEXT:    s_or_b64 exec, exec, s[8:9]
; GFX9-NEXT:    v_mov_b32_e32 v7, v9
; GFX9-NEXT:  .LBB11_7: ; %Flow49
; GFX9-NEXT:    s_or_b64 exec, exec, s[6:7]
; GFX9-NEXT:    v_add_u32_e32 v6, -11, v6
; GFX9-NEXT:    v_ldexp_f32 v6, v7, v6
; GFX9-NEXT:    v_mul_f32_e32 v7, v6, v8
; GFX9-NEXT:    v_rndne_f32_e32 v7, v7
; GFX9-NEXT:    v_fma_f32 v6, -v7, v5, v6
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v6
; GFX9-NEXT:    v_add_f32_e32 v5, v6, v5
; GFX9-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc
; GFX9-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX9-NEXT:    s_brev_b32 s6, -2
; GFX9-NEXT:    v_bfi_b32 v4, s6, v4, v0
; GFX9-NEXT:  .LBB11_8: ; %Flow51
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    v_cmp_ngt_f32_e64 s[4:5], |v1|, |v3|
; GFX9-NEXT:    ; implicit-def: $vgpr5
; GFX9-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; GFX9-NEXT:  ; %bb.9: ; %frem.else
; GFX9-NEXT:    v_and_b32_e32 v5, 0x80000000, v1
; GFX9-NEXT:    v_cmp_eq_f32_e64 vcc, |v1|, |v3|
; GFX9-NEXT:    v_cndmask_b32_e32 v5, v1, v5, vcc
; GFX9-NEXT:  ; %bb.10: ; %Flow46
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB11_16
; GFX9-NEXT:  ; %bb.11: ; %frem.compute
; GFX9-NEXT:    v_frexp_mant_f32_e64 v6, |v3|
; GFX9-NEXT:    v_ldexp_f32 v6, v6, 1
; GFX9-NEXT:    v_div_scale_f32 v12, s[6:7], v6, v6, 1.0
; GFX9-NEXT:    v_div_scale_f32 v9, vcc, 1.0, v6, 1.0
; GFX9-NEXT:    v_frexp_mant_f32_e64 v5, |v1|
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v10, v1
; GFX9-NEXT:    v_ldexp_f32 v8, v5, 12
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v11, v3
; GFX9-NEXT:    v_add_u32_e32 v5, -1, v11
; GFX9-NEXT:    v_xad_u32 v7, v5, -1, v10
; GFX9-NEXT:    v_rcp_f32_e32 v13, v12
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT:    v_fma_f32 v14, -v12, v13, 1.0
; GFX9-NEXT:    v_fma_f32 v13, v14, v13, v13
; GFX9-NEXT:    v_mul_f32_e32 v14, v9, v13
; GFX9-NEXT:    v_fma_f32 v15, -v12, v14, v9
; GFX9-NEXT:    v_fma_f32 v14, v15, v13, v14
; GFX9-NEXT:    v_fma_f32 v9, -v12, v14, v9
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX9-NEXT:    v_div_fmas_f32 v9, v9, v13, v14
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v7
; GFX9-NEXT:    v_div_fixup_f32 v9, v9, v6, 1.0
; GFX9-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; GFX9-NEXT:    s_cbranch_execz .LBB11_15
; GFX9-NEXT:  ; %bb.12: ; %frem.loop_body.preheader
; GFX9-NEXT:    v_sub_u32_e32 v7, v10, v11
; GFX9-NEXT:    v_add_u32_e32 v7, 12, v7
; GFX9-NEXT:    s_mov_b64 s[8:9], 0
; GFX9-NEXT:  .LBB11_13: ; %frem.loop_body
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v10, v8
; GFX9-NEXT:    v_mul_f32_e32 v8, v10, v9
; GFX9-NEXT:    v_rndne_f32_e32 v8, v8
; GFX9-NEXT:    v_fma_f32 v8, -v8, v6, v10
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v8
; GFX9-NEXT:    v_add_f32_e32 v11, v8, v6
; GFX9-NEXT:    v_add_u32_e32 v7, -12, v7
; GFX9-NEXT:    v_cndmask_b32_e32 v8, v8, v11, vcc
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v7
; GFX9-NEXT:    v_ldexp_f32 v8, v8, 12
; GFX9-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; GFX9-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; GFX9-NEXT:    s_cbranch_execnz .LBB11_13
; GFX9-NEXT:  ; %bb.14: ; %Flow
; GFX9-NEXT:    s_or_b64 exec, exec, s[8:9]
; GFX9-NEXT:    v_mov_b32_e32 v8, v10
; GFX9-NEXT:  .LBB11_15: ; %Flow45
; GFX9-NEXT:    s_or_b64 exec, exec, s[6:7]
; GFX9-NEXT:    v_add_u32_e32 v7, -11, v7
; GFX9-NEXT:    v_ldexp_f32 v7, v8, v7
; GFX9-NEXT:    v_mul_f32_e32 v8, v7, v9
; GFX9-NEXT:    v_rndne_f32_e32 v8, v8
; GFX9-NEXT:    v_fma_f32 v7, -v8, v6, v7
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v7
; GFX9-NEXT:    v_add_f32_e32 v6, v7, v6
; GFX9-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc
; GFX9-NEXT:    v_ldexp_f32 v5, v6, v5
; GFX9-NEXT:    s_brev_b32 s6, -2
; GFX9-NEXT:    v_bfi_b32 v5, s6, v5, v1
; GFX9-NEXT:  .LBB11_16: ; %Flow47
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_mov_b32 s6, 0x7f800000
; GFX9-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v2
; GFX9-NEXT:    v_cmp_nge_f32_e64 s[4:5], |v0|, s6
; GFX9-NEXT:    s_and_b64 vcc, s[4:5], vcc
; GFX9-NEXT:    v_mov_b32_e32 v2, 0x7fc00000
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc
; GFX9-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v3
; GFX9-NEXT:    v_cmp_nge_f32_e64 s[4:5], |v1|, s6
; GFX9-NEXT:    s_and_b64 vcc, s[4:5], vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v2, v5, vcc
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: frem_v2f32:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cmp_ngt_f32_e64 s4, |v0|, |v2|
; GFX10-NEXT:    ; implicit-def: $vgpr4
; GFX10-NEXT:    s_and_saveexec_b32 s5, s4
; GFX10-NEXT:    s_xor_b32 s4, exec_lo, s5
; GFX10-NEXT:  ; %bb.1: ; %frem.else16
; GFX10-NEXT:    v_and_b32_e32 v4, 0x80000000, v0
; GFX10-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v0|, |v2|
; GFX10-NEXT:    v_cndmask_b32_e32 v4, v0, v4, vcc_lo
; GFX10-NEXT:  ; %bb.2: ; %Flow50
; GFX10-NEXT:    s_andn2_saveexec_b32 s4, s4
; GFX10-NEXT:    s_cbranch_execz .LBB11_8
; GFX10-NEXT:  ; %bb.3: ; %frem.compute15
; GFX10-NEXT:    v_frexp_mant_f32_e64 v5, |v2|
; GFX10-NEXT:    v_frexp_mant_f32_e64 v4, |v0|
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v9, v0
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v10, v2
; GFX10-NEXT:    v_ldexp_f32 v5, v5, 1
; GFX10-NEXT:    v_ldexp_f32 v7, v4, 12
; GFX10-NEXT:    v_add_nc_u32_e32 v4, -1, v10
; GFX10-NEXT:    v_div_scale_f32 v11, s5, v5, v5, 1.0
; GFX10-NEXT:    v_div_scale_f32 v8, vcc_lo, 1.0, v5, 1.0
; GFX10-NEXT:    v_xad_u32 v6, v4, -1, v9
; GFX10-NEXT:    v_rcp_f32_e32 v12, v11
; GFX10-NEXT:    s_denorm_mode 15
; GFX10-NEXT:    v_fma_f32 v13, -v11, v12, 1.0
; GFX10-NEXT:    v_fmac_f32_e32 v12, v13, v12
; GFX10-NEXT:    v_mul_f32_e32 v13, v8, v12
; GFX10-NEXT:    v_fma_f32 v14, -v11, v13, v8
; GFX10-NEXT:    v_fmac_f32_e32 v13, v14, v12
; GFX10-NEXT:    v_fma_f32 v8, -v11, v13, v8
; GFX10-NEXT:    s_denorm_mode 12
; GFX10-NEXT:    v_div_fmas_f32 v8, v8, v12, v13
; GFX10-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 12, v6
; GFX10-NEXT:    v_div_fixup_f32 v8, v8, v5, 1.0
; GFX10-NEXT:    s_and_saveexec_b32 s5, vcc_lo
; GFX10-NEXT:    s_cbranch_execz .LBB11_7
; GFX10-NEXT:  ; %bb.4: ; %frem.loop_body23.preheader
; GFX10-NEXT:    v_sub_nc_u32_e32 v6, v9, v10
; GFX10-NEXT:    s_mov_b32 s6, 0
; GFX10-NEXT:    v_add_nc_u32_e32 v6, 12, v6
; GFX10-NEXT:  .LBB11_5: ; %frem.loop_body23
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v9, v7
; GFX10-NEXT:    v_add_nc_u32_e32 v6, -12, v6
; GFX10-NEXT:    v_mul_f32_e32 v7, v9, v8
; GFX10-NEXT:    v_rndne_f32_e32 v7, v7
; GFX10-NEXT:    v_fma_f32 v7, -v7, v5, v9
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v7
; GFX10-NEXT:    v_add_f32_e32 v10, v7, v5
; GFX10-NEXT:    v_cndmask_b32_e32 v7, v7, v10, vcc_lo
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v6
; GFX10-NEXT:    v_ldexp_f32 v7, v7, 12
; GFX10-NEXT:    s_or_b32 s6, vcc_lo, s6
; GFX10-NEXT:    s_andn2_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    s_cbranch_execnz .LBB11_5
; GFX10-NEXT:  ; %bb.6: ; %Flow48
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    v_mov_b32_e32 v7, v9
; GFX10-NEXT:  .LBB11_7: ; %Flow49
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s5
; GFX10-NEXT:    v_add_nc_u32_e32 v6, -11, v6
; GFX10-NEXT:    v_ldexp_f32 v6, v7, v6
; GFX10-NEXT:    v_mul_f32_e32 v7, v6, v8
; GFX10-NEXT:    v_rndne_f32_e32 v7, v7
; GFX10-NEXT:    v_fma_f32 v6, -v7, v5, v6
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v6
; GFX10-NEXT:    v_add_f32_e32 v5, v6, v5
; GFX10-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX10-NEXT:    v_bfi_b32 v4, 0x7fffffff, v4, v0
; GFX10-NEXT:  .LBB11_8: ; %Flow51
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT:    v_cmp_ngt_f32_e64 s4, |v1|, |v3|
; GFX10-NEXT:    ; implicit-def: $vgpr5
; GFX10-NEXT:    s_and_saveexec_b32 s5, s4
; GFX10-NEXT:    s_xor_b32 s4, exec_lo, s5
; GFX10-NEXT:  ; %bb.9: ; %frem.else
; GFX10-NEXT:    v_and_b32_e32 v5, 0x80000000, v1
; GFX10-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v1|, |v3|
; GFX10-NEXT:    v_cndmask_b32_e32 v5, v1, v5, vcc_lo
; GFX10-NEXT:  ; %bb.10: ; %Flow46
; GFX10-NEXT:    s_andn2_saveexec_b32 s4, s4
; GFX10-NEXT:    s_cbranch_execz .LBB11_16
; GFX10-NEXT:  ; %bb.11: ; %frem.compute
; GFX10-NEXT:    v_frexp_mant_f32_e64 v6, |v3|
; GFX10-NEXT:    v_frexp_mant_f32_e64 v5, |v1|
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v10, v1
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v11, v3
; GFX10-NEXT:    v_ldexp_f32 v6, v6, 1
; GFX10-NEXT:    v_ldexp_f32 v8, v5, 12
; GFX10-NEXT:    v_add_nc_u32_e32 v5, -1, v11
; GFX10-NEXT:    v_div_scale_f32 v12, s5, v6, v6, 1.0
; GFX10-NEXT:    v_div_scale_f32 v9, vcc_lo, 1.0, v6, 1.0
; GFX10-NEXT:    v_xad_u32 v7, v5, -1, v10
; GFX10-NEXT:    v_rcp_f32_e32 v13, v12
; GFX10-NEXT:    s_denorm_mode 15
; GFX10-NEXT:    v_fma_f32 v14, -v12, v13, 1.0
; GFX10-NEXT:    v_fmac_f32_e32 v13, v14, v13
; GFX10-NEXT:    v_mul_f32_e32 v14, v9, v13
; GFX10-NEXT:    v_fma_f32 v15, -v12, v14, v9
; GFX10-NEXT:    v_fmac_f32_e32 v14, v15, v13
; GFX10-NEXT:    v_fma_f32 v9, -v12, v14, v9
; GFX10-NEXT:    s_denorm_mode 12
; GFX10-NEXT:    v_div_fmas_f32 v9, v9, v13, v14
; GFX10-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 12, v7
; GFX10-NEXT:    v_div_fixup_f32 v9, v9, v6, 1.0
; GFX10-NEXT:    s_and_saveexec_b32 s5, vcc_lo
; GFX10-NEXT:    s_cbranch_execz .LBB11_15
; GFX10-NEXT:  ; %bb.12: ; %frem.loop_body.preheader
; GFX10-NEXT:    v_sub_nc_u32_e32 v7, v10, v11
; GFX10-NEXT:    s_mov_b32 s6, 0
; GFX10-NEXT:    v_add_nc_u32_e32 v7, 12, v7
; GFX10-NEXT:  .LBB11_13: ; %frem.loop_body
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v10, v8
; GFX10-NEXT:    v_add_nc_u32_e32 v7, -12, v7
; GFX10-NEXT:    v_mul_f32_e32 v8, v10, v9
; GFX10-NEXT:    v_rndne_f32_e32 v8, v8
; GFX10-NEXT:    v_fma_f32 v8, -v8, v6, v10
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v8
; GFX10-NEXT:    v_add_f32_e32 v11, v8, v6
; GFX10-NEXT:    v_cndmask_b32_e32 v8, v8, v11, vcc_lo
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v7
; GFX10-NEXT:    v_ldexp_f32 v8, v8, 12
; GFX10-NEXT:    s_or_b32 s6, vcc_lo, s6
; GFX10-NEXT:    s_andn2_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    s_cbranch_execnz .LBB11_13
; GFX10-NEXT:  ; %bb.14: ; %Flow
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    v_mov_b32_e32 v8, v10
; GFX10-NEXT:  .LBB11_15: ; %Flow45
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s5
; GFX10-NEXT:    v_add_nc_u32_e32 v7, -11, v7
; GFX10-NEXT:    v_ldexp_f32 v7, v8, v7
; GFX10-NEXT:    v_mul_f32_e32 v8, v7, v9
; GFX10-NEXT:    v_rndne_f32_e32 v8, v8
; GFX10-NEXT:    v_fma_f32 v7, -v8, v6, v7
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v7
; GFX10-NEXT:    v_add_f32_e32 v6, v7, v6
; GFX10-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v5, v6, v5
; GFX10-NEXT:    v_bfi_b32 v5, 0x7fffffff, v5, v1
; GFX10-NEXT:  .LBB11_16: ; %Flow47
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v2
; GFX10-NEXT:    v_cmp_nge_f32_e64 s4, |v0|, 0x7f800000
; GFX10-NEXT:    s_and_b32 vcc_lo, s4, vcc_lo
; GFX10-NEXT:    v_cmp_nge_f32_e64 s4, |v1|, 0x7f800000
; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v4, vcc_lo
; GFX10-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v3
; GFX10-NEXT:    s_and_b32 vcc_lo, s4, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v5, vcc_lo
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: frem_v2f32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cmp_ngt_f32_e64 s0, |v0|, |v2|
; GFX11-NEXT:    ; implicit-def: $vgpr4
; GFX11-NEXT:    s_and_saveexec_b32 s1, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX11-NEXT:  ; %bb.1: ; %frem.else16
; GFX11-NEXT:    v_and_b32_e32 v4, 0x80000000, v0
; GFX11-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v0|, |v2|
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT:    v_cndmask_b32_e32 v4, v0, v4, vcc_lo
; GFX11-NEXT:  ; %bb.2: ; %Flow50
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB11_8
; GFX11-NEXT:  ; %bb.3: ; %frem.compute15
; GFX11-NEXT:    v_frexp_mant_f32_e64 v5, |v2|
; GFX11-NEXT:    v_frexp_mant_f32_e64 v4, |v0|
; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v9, v0
; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v10, v2
; GFX11-NEXT:    s_mov_b32 s1, exec_lo
; GFX11-NEXT:    v_ldexp_f32 v5, v5, 1
; GFX11-NEXT:    v_ldexp_f32 v7, v4, 12
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_add_nc_u32_e32 v4, -1, v10
; GFX11-NEXT:    v_div_scale_f32 v11, null, v5, v5, 1.0
; GFX11-NEXT:    v_div_scale_f32 v8, vcc_lo, 1.0, v5, 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_xad_u32 v6, v4, -1, v9
; GFX11-NEXT:    v_rcp_f32_e32 v12, v11
; GFX11-NEXT:    s_denorm_mode 15
; GFX11-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT:    v_fma_f32 v13, -v11, v12, 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fmac_f32_e32 v12, v13, v12
; GFX11-NEXT:    v_mul_f32_e32 v13, v8, v12
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v14, -v11, v13, v8
; GFX11-NEXT:    v_fmac_f32_e32 v13, v14, v12
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v8, -v11, v13, v8
; GFX11-NEXT:    s_denorm_mode 12
; GFX11-NEXT:    v_div_fmas_f32 v8, v8, v12, v13
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_div_fixup_f32 v8, v8, v5, 1.0
; GFX11-NEXT:    v_cmpx_lt_i32_e32 12, v6
; GFX11-NEXT:    s_cbranch_execz .LBB11_7
; GFX11-NEXT:  ; %bb.4: ; %frem.loop_body23.preheader
; GFX11-NEXT:    v_sub_nc_u32_e32 v6, v9, v10
; GFX11-NEXT:    s_mov_b32 s2, 0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_add_nc_u32_e32 v6, 12, v6
; GFX11-NEXT:  .LBB11_5: ; %frem.loop_body23
; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_dual_mov_b32 v9, v7 :: v_dual_add_nc_u32 v6, -12, v6
; GFX11-NEXT:    v_mul_f32_e32 v7, v9, v8
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_rndne_f32_e32 v7, v7
; GFX11-NEXT:    v_fma_f32 v7, -v7, v5, v9
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v7
; GFX11-NEXT:    v_add_f32_e32 v10, v7, v5
; GFX11-NEXT:    v_cndmask_b32_e32 v7, v7, v10, vcc_lo
; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v6
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT:    v_ldexp_f32 v7, v7, 12
; GFX11-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX11-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX11-NEXT:    s_cbranch_execnz .LBB11_5
; GFX11-NEXT:  ; %bb.6: ; %Flow48
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX11-NEXT:    v_mov_b32_e32 v7, v9
; GFX11-NEXT:  .LBB11_7: ; %Flow49
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX11-NEXT:    v_add_nc_u32_e32 v6, -11, v6
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_ldexp_f32 v6, v7, v6
; GFX11-NEXT:    v_mul_f32_e32 v7, v6, v8
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_rndne_f32_e32 v7, v7
; GFX11-NEXT:    v_fma_f32 v6, -v7, v5, v6
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v6
; GFX11-NEXT:    v_add_f32_e32 v5, v6, v5
; GFX11-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc_lo
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX11-NEXT:    v_bfi_b32 v4, 0x7fffffff, v4, v0
; GFX11-NEXT:  .LBB11_8: ; %Flow51
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    v_cmp_ngt_f32_e64 s0, |v1|, |v3|
; GFX11-NEXT:    ; implicit-def: $vgpr5
; GFX11-NEXT:    s_and_saveexec_b32 s1, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX11-NEXT:  ; %bb.9: ; %frem.else
; GFX11-NEXT:    v_and_b32_e32 v5, 0x80000000, v1
; GFX11-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v1|, |v3|
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT:    v_cndmask_b32_e32 v5, v1, v5, vcc_lo
; GFX11-NEXT:  ; %bb.10: ; %Flow46
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB11_16
; GFX11-NEXT:  ; %bb.11: ; %frem.compute
; GFX11-NEXT:    v_frexp_mant_f32_e64 v6, |v3|
; GFX11-NEXT:    v_frexp_mant_f32_e64 v5, |v1|
; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v10, v1
; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v11, v3
; GFX11-NEXT:    s_mov_b32 s1, exec_lo
; GFX11-NEXT:    v_ldexp_f32 v6, v6, 1
; GFX11-NEXT:    v_ldexp_f32 v8, v5, 12
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_add_nc_u32_e32 v5, -1, v11
; GFX11-NEXT:    v_div_scale_f32 v12, null, v6, v6, 1.0
; GFX11-NEXT:    v_div_scale_f32 v9, vcc_lo, 1.0, v6, 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_xad_u32 v7, v5, -1, v10
; GFX11-NEXT:    v_rcp_f32_e32 v13, v12
; GFX11-NEXT:    s_denorm_mode 15
; GFX11-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT:    v_fma_f32 v14, -v12, v13, 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fmac_f32_e32 v13, v14, v13
; GFX11-NEXT:    v_mul_f32_e32 v14, v9, v13
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v15, -v12, v14, v9
; GFX11-NEXT:    v_fmac_f32_e32 v14, v15, v13
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v9, -v12, v14, v9
; GFX11-NEXT:    s_denorm_mode 12
; GFX11-NEXT:    v_div_fmas_f32 v9, v9, v13, v14
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_div_fixup_f32 v9, v9, v6, 1.0
; GFX11-NEXT:    v_cmpx_lt_i32_e32 12, v7
; GFX11-NEXT:    s_cbranch_execz .LBB11_15
; GFX11-NEXT:  ; %bb.12: ; %frem.loop_body.preheader
; GFX11-NEXT:    v_sub_nc_u32_e32 v7, v10, v11
; GFX11-NEXT:    s_mov_b32 s2, 0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_add_nc_u32_e32 v7, 12, v7
; GFX11-NEXT:  .LBB11_13: ; %frem.loop_body
; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_dual_mov_b32 v10, v8 :: v_dual_add_nc_u32 v7, -12, v7
; GFX11-NEXT:    v_mul_f32_e32 v8, v10, v9
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_rndne_f32_e32 v8, v8
; GFX11-NEXT:    v_fma_f32 v8, -v8, v6, v10
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v8
; GFX11-NEXT:    v_add_f32_e32 v11, v8, v6
; GFX11-NEXT:    v_cndmask_b32_e32 v8, v8, v11, vcc_lo
; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v7
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT:    v_ldexp_f32 v8, v8, 12
; GFX11-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX11-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX11-NEXT:    s_cbranch_execnz .LBB11_13
; GFX11-NEXT:  ; %bb.14: ; %Flow
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX11-NEXT:    v_mov_b32_e32 v8, v10
; GFX11-NEXT:  .LBB11_15: ; %Flow45
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX11-NEXT:    v_add_nc_u32_e32 v7, -11, v7
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_ldexp_f32 v7, v8, v7
; GFX11-NEXT:    v_mul_f32_e32 v8, v7, v9
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_rndne_f32_e32 v8, v8
; GFX11-NEXT:    v_fma_f32 v7, -v8, v6, v7
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v7
; GFX11-NEXT:    v_add_f32_e32 v6, v7, v6
; GFX11-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc_lo
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_ldexp_f32 v5, v6, v5
; GFX11-NEXT:    v_bfi_b32 v5, 0x7fffffff, v5, v1
; GFX11-NEXT:  .LBB11_16: ; %Flow47
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v2
; GFX11-NEXT:    v_cmp_nge_f32_e64 s0, |v0|, 0x7f800000
; GFX11-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX11-NEXT:    v_cmp_nge_f32_e64 s0, |v1|, 0x7f800000
; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v4, vcc_lo
; GFX11-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v3
; GFX11-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX11-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v5, vcc_lo
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-LABEL: frem_v2f32:
; GFX1150:       ; %bb.0:
; GFX1150-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-NEXT:    v_cmp_ngt_f32_e64 s0, |v0|, |v2|
; GFX1150-NEXT:    ; implicit-def: $vgpr4
; GFX1150-NEXT:    s_and_saveexec_b32 s1, s0
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX1150-NEXT:  ; %bb.1: ; %frem.else16
; GFX1150-NEXT:    v_and_b32_e32 v4, 0x80000000, v0
; GFX1150-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v0|, |v2|
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1150-NEXT:    v_cndmask_b32_e32 v4, v0, v4, vcc_lo
; GFX1150-NEXT:  ; %bb.2: ; %Flow50
; GFX1150-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1150-NEXT:    s_cbranch_execz .LBB11_8
; GFX1150-NEXT:  ; %bb.3: ; %frem.compute15
; GFX1150-NEXT:    v_frexp_mant_f32_e64 v5, |v2|
; GFX1150-NEXT:    v_frexp_mant_f32_e64 v4, |v0|
; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v9, v0
; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v10, v2
; GFX1150-NEXT:    s_mov_b32 s1, exec_lo
; GFX1150-NEXT:    v_ldexp_f32 v5, v5, 1
; GFX1150-NEXT:    v_ldexp_f32 v7, v4, 12
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_add_nc_u32_e32 v4, -1, v10
; GFX1150-NEXT:    v_div_scale_f32 v11, null, v5, v5, 1.0
; GFX1150-NEXT:    v_div_scale_f32 v8, vcc_lo, 1.0, v5, 1.0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_xad_u32 v6, v4, -1, v9
; GFX1150-NEXT:    v_rcp_f32_e32 v12, v11
; GFX1150-NEXT:    s_denorm_mode 15
; GFX1150-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f32 v13, -v11, v12, 1.0
; GFX1150-NEXT:    v_fmac_f32_e32 v12, v13, v12
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f32_e32 v13, v8, v12
; GFX1150-NEXT:    v_fma_f32 v14, -v11, v13, v8
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fmac_f32_e32 v13, v14, v12
; GFX1150-NEXT:    v_fma_f32 v8, -v11, v13, v8
; GFX1150-NEXT:    s_denorm_mode 12
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_div_fmas_f32 v8, v8, v12, v13
; GFX1150-NEXT:    v_div_fixup_f32 v8, v8, v5, 1.0
; GFX1150-NEXT:    v_cmpx_lt_i32_e32 12, v6
; GFX1150-NEXT:    s_cbranch_execz .LBB11_7
; GFX1150-NEXT:  ; %bb.4: ; %frem.loop_body23.preheader
; GFX1150-NEXT:    v_sub_nc_u32_e32 v6, v9, v10
; GFX1150-NEXT:    s_mov_b32 s2, 0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_add_nc_u32_e32 v6, 12, v6
; GFX1150-NEXT:  .LBB11_5: ; %frem.loop_body23
; GFX1150-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_dual_mov_b32 v9, v7 :: v_dual_add_nc_u32 v6, -12, v6
; GFX1150-NEXT:    v_mul_f32_e32 v7, v9, v8
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_rndne_f32_e32 v7, v7
; GFX1150-NEXT:    v_fma_f32 v7, -v7, v5, v9
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v7
; GFX1150-NEXT:    v_add_f32_e32 v10, v7, v5
; GFX1150-NEXT:    v_cndmask_b32_e32 v7, v7, v10, vcc_lo
; GFX1150-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v6
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT:    v_ldexp_f32 v7, v7, 12
; GFX1150-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1150-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1150-NEXT:    s_cbranch_execnz .LBB11_5
; GFX1150-NEXT:  ; %bb.6: ; %Flow48
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1150-NEXT:    v_mov_b32_e32 v7, v9
; GFX1150-NEXT:  .LBB11_7: ; %Flow49
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1150-NEXT:    v_add_nc_u32_e32 v6, -11, v6
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f32 v6, v7, v6
; GFX1150-NEXT:    v_mul_f32_e32 v7, v6, v8
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_rndne_f32_e32 v7, v7
; GFX1150-NEXT:    v_fma_f32 v6, -v7, v5, v6
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v6
; GFX1150-NEXT:    v_add_f32_e32 v5, v6, v5
; GFX1150-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc_lo
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX1150-NEXT:    v_bfi_b32 v4, 0x7fffffff, v4, v0
; GFX1150-NEXT:  .LBB11_8: ; %Flow51
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1150-NEXT:    v_cmp_ngt_f32_e64 s0, |v1|, |v3|
; GFX1150-NEXT:    ; implicit-def: $vgpr5
; GFX1150-NEXT:    s_and_saveexec_b32 s1, s0
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX1150-NEXT:  ; %bb.9: ; %frem.else
; GFX1150-NEXT:    v_and_b32_e32 v5, 0x80000000, v1
; GFX1150-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v1|, |v3|
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1150-NEXT:    v_cndmask_b32_e32 v5, v1, v5, vcc_lo
; GFX1150-NEXT:  ; %bb.10: ; %Flow46
; GFX1150-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1150-NEXT:    s_cbranch_execz .LBB11_16
; GFX1150-NEXT:  ; %bb.11: ; %frem.compute
; GFX1150-NEXT:    v_frexp_mant_f32_e64 v6, |v3|
; GFX1150-NEXT:    v_frexp_mant_f32_e64 v5, |v1|
; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v10, v1
; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v11, v3
; GFX1150-NEXT:    s_mov_b32 s1, exec_lo
; GFX1150-NEXT:    v_ldexp_f32 v6, v6, 1
; GFX1150-NEXT:    v_ldexp_f32 v8, v5, 12
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_add_nc_u32_e32 v5, -1, v11
; GFX1150-NEXT:    v_div_scale_f32 v12, null, v6, v6, 1.0
; GFX1150-NEXT:    v_div_scale_f32 v9, vcc_lo, 1.0, v6, 1.0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_xad_u32 v7, v5, -1, v10
; GFX1150-NEXT:    v_rcp_f32_e32 v13, v12
; GFX1150-NEXT:    s_denorm_mode 15
; GFX1150-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f32 v14, -v12, v13, 1.0
; GFX1150-NEXT:    v_fmac_f32_e32 v13, v14, v13
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f32_e32 v14, v9, v13
; GFX1150-NEXT:    v_fma_f32 v15, -v12, v14, v9
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fmac_f32_e32 v14, v15, v13
; GFX1150-NEXT:    v_fma_f32 v9, -v12, v14, v9
; GFX1150-NEXT:    s_denorm_mode 12
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_div_fmas_f32 v9, v9, v13, v14
; GFX1150-NEXT:    v_div_fixup_f32 v9, v9, v6, 1.0
; GFX1150-NEXT:    v_cmpx_lt_i32_e32 12, v7
; GFX1150-NEXT:    s_cbranch_execz .LBB11_15
; GFX1150-NEXT:  ; %bb.12: ; %frem.loop_body.preheader
; GFX1150-NEXT:    v_sub_nc_u32_e32 v7, v10, v11
; GFX1150-NEXT:    s_mov_b32 s2, 0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_add_nc_u32_e32 v7, 12, v7
; GFX1150-NEXT:  .LBB11_13: ; %frem.loop_body
; GFX1150-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_dual_mov_b32 v10, v8 :: v_dual_add_nc_u32 v7, -12, v7
; GFX1150-NEXT:    v_mul_f32_e32 v8, v10, v9
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_rndne_f32_e32 v8, v8
; GFX1150-NEXT:    v_fma_f32 v8, -v8, v6, v10
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v8
; GFX1150-NEXT:    v_add_f32_e32 v11, v8, v6
; GFX1150-NEXT:    v_cndmask_b32_e32 v8, v8, v11, vcc_lo
; GFX1150-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v7
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT:    v_ldexp_f32 v8, v8, 12
; GFX1150-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1150-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1150-NEXT:    s_cbranch_execnz .LBB11_13
; GFX1150-NEXT:  ; %bb.14: ; %Flow
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1150-NEXT:    v_mov_b32_e32 v8, v10
; GFX1150-NEXT:  .LBB11_15: ; %Flow45
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1150-NEXT:    v_add_nc_u32_e32 v7, -11, v7
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f32 v7, v8, v7
; GFX1150-NEXT:    v_mul_f32_e32 v8, v7, v9
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_rndne_f32_e32 v8, v8
; GFX1150-NEXT:    v_fma_f32 v7, -v8, v6, v7
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v7
; GFX1150-NEXT:    v_add_f32_e32 v6, v7, v6
; GFX1150-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc_lo
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f32 v5, v6, v5
; GFX1150-NEXT:    v_bfi_b32 v5, 0x7fffffff, v5, v1
; GFX1150-NEXT:  .LBB11_16: ; %Flow47
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1150-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v2
; GFX1150-NEXT:    v_cmp_nge_f32_e64 s0, |v0|, 0x7f800000
; GFX1150-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1150-NEXT:    v_cmp_nge_f32_e64 s0, |v1|, 0x7f800000
; GFX1150-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v4, vcc_lo
; GFX1150-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v3
; GFX1150-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1150-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v5, vcc_lo
; GFX1150-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: frem_v2f32:
; GFX1200:       ; %bb.0:
; GFX1200-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT:    s_wait_expcnt 0x0
; GFX1200-NEXT:    s_wait_samplecnt 0x0
; GFX1200-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-NEXT:    s_wait_kmcnt 0x0
; GFX1200-NEXT:    v_cmp_ngt_f32_e64 s0, |v0|, |v2|
; GFX1200-NEXT:    ; implicit-def: $vgpr4
; GFX1200-NEXT:    s_and_saveexec_b32 s1, s0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX1200-NEXT:  ; %bb.1: ; %frem.else16
; GFX1200-NEXT:    v_and_b32_e32 v4, 0x80000000, v0
; GFX1200-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v0|, |v2|
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-NEXT:    v_cndmask_b32_e32 v4, v0, v4, vcc_lo
; GFX1200-NEXT:  ; %bb.2: ; %Flow50
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1200-NEXT:    s_cbranch_execz .LBB11_8
; GFX1200-NEXT:  ; %bb.3: ; %frem.compute15
; GFX1200-NEXT:    v_frexp_mant_f32_e64 v5, |v2|
; GFX1200-NEXT:    v_frexp_mant_f32_e64 v4, |v0|
; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v9, v0
; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v10, v2
; GFX1200-NEXT:    s_mov_b32 s1, exec_lo
; GFX1200-NEXT:    v_ldexp_f32 v5, v5, 1
; GFX1200-NEXT:    v_ldexp_f32 v7, v4, 12
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT:    v_div_scale_f32 v11, null, v5, v5, 1.0
; GFX1200-NEXT:    v_div_scale_f32 v8, vcc_lo, 1.0, v5, 1.0
; GFX1200-NEXT:    v_rcp_f32_e32 v12, v11
; GFX1200-NEXT:    s_denorm_mode 15
; GFX1200-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v13, -v11, v12, 1.0
; GFX1200-NEXT:    v_fmac_f32_e32 v12, v13, v12
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_dual_mul_f32 v13, v8, v12 :: v_dual_add_nc_u32 v4, -1, v10
; GFX1200-NEXT:    v_xad_u32 v6, v4, -1, v9
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v14, -v11, v13, v8
; GFX1200-NEXT:    v_fmac_f32_e32 v13, v14, v12
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v8, -v11, v13, v8
; GFX1200-NEXT:    s_denorm_mode 12
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_div_fmas_f32 v8, v8, v12, v13
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_div_fixup_f32 v8, v8, v5, 1.0
; GFX1200-NEXT:    v_cmpx_lt_i32_e32 12, v6
; GFX1200-NEXT:    s_cbranch_execz .LBB11_7
; GFX1200-NEXT:  ; %bb.4: ; %frem.loop_body23.preheader
; GFX1200-NEXT:    v_sub_nc_u32_e32 v6, v9, v10
; GFX1200-NEXT:    s_mov_b32 s2, 0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_add_nc_u32_e32 v6, 12, v6
; GFX1200-NEXT:  .LBB11_5: ; %frem.loop_body23
; GFX1200-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_dual_mov_b32 v9, v7 :: v_dual_add_nc_u32 v6, -12, v6
; GFX1200-NEXT:    v_mul_f32_e32 v7, v9, v8
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_rndne_f32_e32 v7, v7
; GFX1200-NEXT:    v_fma_f32 v7, -v7, v5, v9
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v7
; GFX1200-NEXT:    v_add_f32_e32 v10, v7, v5
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_cndmask_b32_e32 v7, v7, v10, vcc_lo
; GFX1200-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v6
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-NEXT:    v_ldexp_f32 v7, v7, 12
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1200-NEXT:    s_cbranch_execnz .LBB11_5
; GFX1200-NEXT:  ; %bb.6: ; %Flow48
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1200-NEXT:    v_mov_b32_e32 v7, v9
; GFX1200-NEXT:  .LBB11_7: ; %Flow49
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1200-NEXT:    v_add_nc_u32_e32 v6, -11, v6
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_ldexp_f32 v6, v7, v6
; GFX1200-NEXT:    v_mul_f32_e32 v7, v6, v8
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_rndne_f32_e32 v7, v7
; GFX1200-NEXT:    v_fma_f32 v6, -v7, v5, v6
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v6
; GFX1200-NEXT:    v_add_f32_e32 v5, v6, v5
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc_lo
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_ldexp_f32 v4, v5, v4
; GFX1200-NEXT:    v_bfi_b32 v4, 0x7fffffff, v4, v0
; GFX1200-NEXT:  .LBB11_8: ; %Flow51
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1200-NEXT:    v_cmp_ngt_f32_e64 s0, |v1|, |v3|
; GFX1200-NEXT:    ; implicit-def: $vgpr5
; GFX1200-NEXT:    s_and_saveexec_b32 s1, s0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX1200-NEXT:  ; %bb.9: ; %frem.else
; GFX1200-NEXT:    v_and_b32_e32 v5, 0x80000000, v1
; GFX1200-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v1|, |v3|
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-NEXT:    v_cndmask_b32_e32 v5, v1, v5, vcc_lo
; GFX1200-NEXT:  ; %bb.10: ; %Flow46
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1200-NEXT:    s_cbranch_execz .LBB11_16
; GFX1200-NEXT:  ; %bb.11: ; %frem.compute
; GFX1200-NEXT:    v_frexp_mant_f32_e64 v6, |v3|
; GFX1200-NEXT:    v_frexp_mant_f32_e64 v5, |v1|
; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v10, v1
; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v11, v3
; GFX1200-NEXT:    s_mov_b32 s1, exec_lo
; GFX1200-NEXT:    v_ldexp_f32 v6, v6, 1
; GFX1200-NEXT:    v_ldexp_f32 v8, v5, 12
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT:    v_div_scale_f32 v12, null, v6, v6, 1.0
; GFX1200-NEXT:    v_div_scale_f32 v9, vcc_lo, 1.0, v6, 1.0
; GFX1200-NEXT:    v_rcp_f32_e32 v13, v12
; GFX1200-NEXT:    s_denorm_mode 15
; GFX1200-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v14, -v12, v13, 1.0
; GFX1200-NEXT:    v_fmac_f32_e32 v13, v14, v13
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_dual_mul_f32 v14, v9, v13 :: v_dual_add_nc_u32 v5, -1, v11
; GFX1200-NEXT:    v_xad_u32 v7, v5, -1, v10
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v15, -v12, v14, v9
; GFX1200-NEXT:    v_fmac_f32_e32 v14, v15, v13
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v9, -v12, v14, v9
; GFX1200-NEXT:    s_denorm_mode 12
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_div_fmas_f32 v9, v9, v13, v14
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_div_fixup_f32 v9, v9, v6, 1.0
; GFX1200-NEXT:    v_cmpx_lt_i32_e32 12, v7
; GFX1200-NEXT:    s_cbranch_execz .LBB11_15
; GFX1200-NEXT:  ; %bb.12: ; %frem.loop_body.preheader
; GFX1200-NEXT:    v_sub_nc_u32_e32 v7, v10, v11
; GFX1200-NEXT:    s_mov_b32 s2, 0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_add_nc_u32_e32 v7, 12, v7
; GFX1200-NEXT:  .LBB11_13: ; %frem.loop_body
; GFX1200-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_dual_mov_b32 v10, v8 :: v_dual_add_nc_u32 v7, -12, v7
; GFX1200-NEXT:    v_mul_f32_e32 v8, v10, v9
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_rndne_f32_e32 v8, v8
; GFX1200-NEXT:    v_fma_f32 v8, -v8, v6, v10
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v8
; GFX1200-NEXT:    v_add_f32_e32 v11, v8, v6
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_cndmask_b32_e32 v8, v8, v11, vcc_lo
; GFX1200-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v7
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-NEXT:    v_ldexp_f32 v8, v8, 12
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1200-NEXT:    s_cbranch_execnz .LBB11_13
; GFX1200-NEXT:  ; %bb.14: ; %Flow
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1200-NEXT:    v_mov_b32_e32 v8, v10
; GFX1200-NEXT:  .LBB11_15: ; %Flow45
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1200-NEXT:    v_add_nc_u32_e32 v7, -11, v7
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_ldexp_f32 v7, v8, v7
; GFX1200-NEXT:    v_mul_f32_e32 v8, v7, v9
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_rndne_f32_e32 v8, v8
; GFX1200-NEXT:    v_fma_f32 v7, -v8, v6, v7
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v7
; GFX1200-NEXT:    v_add_f32_e32 v6, v7, v6
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc_lo
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_ldexp_f32 v5, v6, v5
; GFX1200-NEXT:    v_bfi_b32 v5, 0x7fffffff, v5, v1
; GFX1200-NEXT:  .LBB11_16: ; %Flow47
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1200-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v2
; GFX1200-NEXT:    v_cmp_nge_f32_e64 s0, |v0|, 0x7f800000
; GFX1200-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1200-NEXT:    v_cmp_nge_f32_e64 s0, |v1|, 0x7f800000
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v4, vcc_lo
; GFX1200-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v3
; GFX1200-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v5, vcc_lo
; GFX1200-NEXT:    s_setpc_b64 s[30:31]
   %r2 = frem <2 x float> %in1, %in2
  ret <2 x float> %r2
}

define <4 x float> @frem_v4f32(<4 x float> %in1, <4 x float> %in2) #0 {
; SI-LABEL: frem_v4f32:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cmp_ngt_f32_e64 s[4:5], |v0|, |v4|
; SI-NEXT:    ; implicit-def: $vgpr8
; SI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; SI-NEXT:  ; %bb.1: ; %frem.else78
; SI-NEXT:    v_and_b32_e32 v8, 0x80000000, v0
; SI-NEXT:    v_cmp_eq_f32_e64 vcc, |v0|, |v4|
; SI-NEXT:    v_cndmask_b32_e32 v8, v0, v8, vcc
; SI-NEXT:  ; %bb.2: ; %Flow124
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB12_8
; SI-NEXT:  ; %bb.3: ; %frem.compute77
; SI-NEXT:    s_mov_b32 s6, 0x7f800000
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, s6
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v8, v0
; SI-NEXT:    v_cndmask_b32_e32 v13, 0, v8, vcc
; SI-NEXT:    v_frexp_mant_f32_e64 v8, |v0|
; SI-NEXT:    v_cndmask_b32_e64 v8, |v0|, v8, vcc
; SI-NEXT:    v_ldexp_f32_e64 v10, v8, 12
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v4|, s6
; SI-NEXT:    v_frexp_mant_f32_e64 v8, |v4|
; SI-NEXT:    v_cndmask_b32_e64 v9, |v4|, v8, vcc
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v8, v4
; SI-NEXT:    v_ldexp_f32_e64 v9, v9, 1
; SI-NEXT:    v_cndmask_b32_e32 v14, 0, v8, vcc
; SI-NEXT:    v_div_scale_f32 v15, s[6:7], v9, v9, 1.0
; SI-NEXT:    v_add_i32_e32 v8, vcc, -1, v14
; SI-NEXT:    v_rcp_f32_e32 v16, v15
; SI-NEXT:    v_not_b32_e32 v11, v8
; SI-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
; SI-NEXT:    v_div_scale_f32 v12, vcc, 1.0, v9, 1.0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    v_fma_f32 v17, -v15, v16, 1.0
; SI-NEXT:    v_fma_f32 v16, v17, v16, v16
; SI-NEXT:    v_mul_f32_e32 v17, v12, v16
; SI-NEXT:    v_fma_f32 v18, -v15, v17, v12
; SI-NEXT:    v_fma_f32 v17, v18, v16, v17
; SI-NEXT:    v_fma_f32 v12, -v15, v17, v12
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    v_div_fmas_f32 v12, v12, v16, v17
; SI-NEXT:    v_div_fixup_f32 v12, v12, v9, 1.0
; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v11
; SI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; SI-NEXT:    s_cbranch_execz .LBB12_7
; SI-NEXT:  ; %bb.4: ; %frem.loop_body85.preheader
; SI-NEXT:    v_sub_i32_e32 v11, vcc, v13, v14
; SI-NEXT:    v_add_i32_e32 v11, vcc, 12, v11
; SI-NEXT:    s_mov_b64 s[8:9], 0
; SI-NEXT:  .LBB12_5: ; %frem.loop_body85
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v13, v10
; SI-NEXT:    v_mul_f32_e32 v10, v13, v12
; SI-NEXT:    v_rndne_f32_e32 v10, v10
; SI-NEXT:    v_fma_f32 v10, -v10, v9, v13
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v10
; SI-NEXT:    v_add_f32_e32 v14, v10, v9
; SI-NEXT:    v_cndmask_b32_e32 v10, v10, v14, vcc
; SI-NEXT:    v_add_i32_e32 v11, vcc, -12, v11
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v11
; SI-NEXT:    v_ldexp_f32_e64 v10, v10, 12
; SI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; SI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; SI-NEXT:    s_cbranch_execnz .LBB12_5
; SI-NEXT:  ; %bb.6: ; %Flow122
; SI-NEXT:    s_or_b64 exec, exec, s[8:9]
; SI-NEXT:    v_mov_b32_e32 v10, v13
; SI-NEXT:  .LBB12_7: ; %Flow123
; SI-NEXT:    s_or_b64 exec, exec, s[6:7]
; SI-NEXT:    v_add_i32_e32 v11, vcc, -11, v11
; SI-NEXT:    v_ldexp_f32_e32 v10, v10, v11
; SI-NEXT:    v_mul_f32_e32 v11, v10, v12
; SI-NEXT:    v_rndne_f32_e32 v11, v11
; SI-NEXT:    v_fma_f32 v10, -v11, v9, v10
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v10
; SI-NEXT:    v_add_f32_e32 v9, v10, v9
; SI-NEXT:    v_cndmask_b32_e32 v9, v10, v9, vcc
; SI-NEXT:    v_ldexp_f32_e32 v8, v9, v8
; SI-NEXT:    s_brev_b32 s6, -2
; SI-NEXT:    v_bfi_b32 v8, s6, v8, v0
; SI-NEXT:  .LBB12_8: ; %Flow125
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    v_cmp_ngt_f32_e64 s[4:5], |v1|, |v5|
; SI-NEXT:    ; implicit-def: $vgpr9
; SI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; SI-NEXT:  ; %bb.9: ; %frem.else47
; SI-NEXT:    v_and_b32_e32 v9, 0x80000000, v1
; SI-NEXT:    v_cmp_eq_f32_e64 vcc, |v1|, |v5|
; SI-NEXT:    v_cndmask_b32_e32 v9, v1, v9, vcc
; SI-NEXT:  ; %bb.10: ; %Flow120
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB12_16
; SI-NEXT:  ; %bb.11: ; %frem.compute46
; SI-NEXT:    s_mov_b32 s6, 0x7f800000
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v1|, s6
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v9, v1
; SI-NEXT:    v_cndmask_b32_e32 v14, 0, v9, vcc
; SI-NEXT:    v_frexp_mant_f32_e64 v9, |v1|
; SI-NEXT:    v_cndmask_b32_e64 v9, |v1|, v9, vcc
; SI-NEXT:    v_ldexp_f32_e64 v11, v9, 12
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v5|, s6
; SI-NEXT:    v_frexp_mant_f32_e64 v9, |v5|
; SI-NEXT:    v_cndmask_b32_e64 v10, |v5|, v9, vcc
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v9, v5
; SI-NEXT:    v_ldexp_f32_e64 v10, v10, 1
; SI-NEXT:    v_cndmask_b32_e32 v15, 0, v9, vcc
; SI-NEXT:    v_div_scale_f32 v16, s[6:7], v10, v10, 1.0
; SI-NEXT:    v_add_i32_e32 v9, vcc, -1, v15
; SI-NEXT:    v_rcp_f32_e32 v17, v16
; SI-NEXT:    v_not_b32_e32 v12, v9
; SI-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
; SI-NEXT:    v_div_scale_f32 v13, vcc, 1.0, v10, 1.0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    v_fma_f32 v18, -v16, v17, 1.0
; SI-NEXT:    v_fma_f32 v17, v18, v17, v17
; SI-NEXT:    v_mul_f32_e32 v18, v13, v17
; SI-NEXT:    v_fma_f32 v19, -v16, v18, v13
; SI-NEXT:    v_fma_f32 v18, v19, v17, v18
; SI-NEXT:    v_fma_f32 v13, -v16, v18, v13
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    v_div_fmas_f32 v13, v13, v17, v18
; SI-NEXT:    v_div_fixup_f32 v13, v13, v10, 1.0
; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v12
; SI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; SI-NEXT:    s_cbranch_execz .LBB12_15
; SI-NEXT:  ; %bb.12: ; %frem.loop_body54.preheader
; SI-NEXT:    v_sub_i32_e32 v12, vcc, v14, v15
; SI-NEXT:    v_add_i32_e32 v12, vcc, 12, v12
; SI-NEXT:    s_mov_b64 s[8:9], 0
; SI-NEXT:  .LBB12_13: ; %frem.loop_body54
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v14, v11
; SI-NEXT:    v_mul_f32_e32 v11, v14, v13
; SI-NEXT:    v_rndne_f32_e32 v11, v11
; SI-NEXT:    v_fma_f32 v11, -v11, v10, v14
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v11
; SI-NEXT:    v_add_f32_e32 v15, v11, v10
; SI-NEXT:    v_cndmask_b32_e32 v11, v11, v15, vcc
; SI-NEXT:    v_add_i32_e32 v12, vcc, -12, v12
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v12
; SI-NEXT:    v_ldexp_f32_e64 v11, v11, 12
; SI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; SI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; SI-NEXT:    s_cbranch_execnz .LBB12_13
; SI-NEXT:  ; %bb.14: ; %Flow118
; SI-NEXT:    s_or_b64 exec, exec, s[8:9]
; SI-NEXT:    v_mov_b32_e32 v11, v14
; SI-NEXT:  .LBB12_15: ; %Flow119
; SI-NEXT:    s_or_b64 exec, exec, s[6:7]
; SI-NEXT:    v_add_i32_e32 v12, vcc, -11, v12
; SI-NEXT:    v_ldexp_f32_e32 v11, v11, v12
; SI-NEXT:    v_mul_f32_e32 v12, v11, v13
; SI-NEXT:    v_rndne_f32_e32 v12, v12
; SI-NEXT:    v_fma_f32 v11, -v12, v10, v11
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v11
; SI-NEXT:    v_add_f32_e32 v10, v11, v10
; SI-NEXT:    v_cndmask_b32_e32 v10, v11, v10, vcc
; SI-NEXT:    v_ldexp_f32_e32 v9, v10, v9
; SI-NEXT:    s_brev_b32 s6, -2
; SI-NEXT:    v_bfi_b32 v9, s6, v9, v1
; SI-NEXT:  .LBB12_16: ; %Flow121
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    v_cmp_ngt_f32_e64 s[4:5], |v2|, |v6|
; SI-NEXT:    ; implicit-def: $vgpr10
; SI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; SI-NEXT:  ; %bb.17: ; %frem.else16
; SI-NEXT:    v_and_b32_e32 v10, 0x80000000, v2
; SI-NEXT:    v_cmp_eq_f32_e64 vcc, |v2|, |v6|
; SI-NEXT:    v_cndmask_b32_e32 v10, v2, v10, vcc
; SI-NEXT:  ; %bb.18: ; %Flow116
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB12_24
; SI-NEXT:  ; %bb.19: ; %frem.compute15
; SI-NEXT:    s_mov_b32 s6, 0x7f800000
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v2|, s6
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v10, v2
; SI-NEXT:    v_cndmask_b32_e32 v15, 0, v10, vcc
; SI-NEXT:    v_frexp_mant_f32_e64 v10, |v2|
; SI-NEXT:    v_cndmask_b32_e64 v10, |v2|, v10, vcc
; SI-NEXT:    v_ldexp_f32_e64 v12, v10, 12
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v6|, s6
; SI-NEXT:    v_frexp_mant_f32_e64 v10, |v6|
; SI-NEXT:    v_cndmask_b32_e64 v11, |v6|, v10, vcc
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v10, v6
; SI-NEXT:    v_ldexp_f32_e64 v11, v11, 1
; SI-NEXT:    v_cndmask_b32_e32 v16, 0, v10, vcc
; SI-NEXT:    v_div_scale_f32 v17, s[6:7], v11, v11, 1.0
; SI-NEXT:    v_add_i32_e32 v10, vcc, -1, v16
; SI-NEXT:    v_rcp_f32_e32 v18, v17
; SI-NEXT:    v_not_b32_e32 v13, v10
; SI-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
; SI-NEXT:    v_div_scale_f32 v14, vcc, 1.0, v11, 1.0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    v_fma_f32 v19, -v17, v18, 1.0
; SI-NEXT:    v_fma_f32 v18, v19, v18, v18
; SI-NEXT:    v_mul_f32_e32 v19, v14, v18
; SI-NEXT:    v_fma_f32 v20, -v17, v19, v14
; SI-NEXT:    v_fma_f32 v19, v20, v18, v19
; SI-NEXT:    v_fma_f32 v14, -v17, v19, v14
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    v_div_fmas_f32 v14, v14, v18, v19
; SI-NEXT:    v_div_fixup_f32 v14, v14, v11, 1.0
; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v13
; SI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; SI-NEXT:    s_cbranch_execz .LBB12_23
; SI-NEXT:  ; %bb.20: ; %frem.loop_body23.preheader
; SI-NEXT:    v_sub_i32_e32 v13, vcc, v15, v16
; SI-NEXT:    v_add_i32_e32 v13, vcc, 12, v13
; SI-NEXT:    s_mov_b64 s[8:9], 0
; SI-NEXT:  .LBB12_21: ; %frem.loop_body23
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v15, v12
; SI-NEXT:    v_mul_f32_e32 v12, v15, v14
; SI-NEXT:    v_rndne_f32_e32 v12, v12
; SI-NEXT:    v_fma_f32 v12, -v12, v11, v15
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v12
; SI-NEXT:    v_add_f32_e32 v16, v12, v11
; SI-NEXT:    v_cndmask_b32_e32 v12, v12, v16, vcc
; SI-NEXT:    v_add_i32_e32 v13, vcc, -12, v13
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v13
; SI-NEXT:    v_ldexp_f32_e64 v12, v12, 12
; SI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; SI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; SI-NEXT:    s_cbranch_execnz .LBB12_21
; SI-NEXT:  ; %bb.22: ; %Flow114
; SI-NEXT:    s_or_b64 exec, exec, s[8:9]
; SI-NEXT:    v_mov_b32_e32 v12, v15
; SI-NEXT:  .LBB12_23: ; %Flow115
; SI-NEXT:    s_or_b64 exec, exec, s[6:7]
; SI-NEXT:    v_add_i32_e32 v13, vcc, -11, v13
; SI-NEXT:    v_ldexp_f32_e32 v12, v12, v13
; SI-NEXT:    v_mul_f32_e32 v13, v12, v14
; SI-NEXT:    v_rndne_f32_e32 v13, v13
; SI-NEXT:    v_fma_f32 v12, -v13, v11, v12
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v12
; SI-NEXT:    v_add_f32_e32 v11, v12, v11
; SI-NEXT:    v_cndmask_b32_e32 v11, v12, v11, vcc
; SI-NEXT:    v_ldexp_f32_e32 v10, v11, v10
; SI-NEXT:    s_brev_b32 s6, -2
; SI-NEXT:    v_bfi_b32 v10, s6, v10, v2
; SI-NEXT:  .LBB12_24: ; %Flow117
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    v_cmp_ngt_f32_e64 s[4:5], |v3|, |v7|
; SI-NEXT:    ; implicit-def: $vgpr11
; SI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; SI-NEXT:  ; %bb.25: ; %frem.else
; SI-NEXT:    v_and_b32_e32 v11, 0x80000000, v3
; SI-NEXT:    v_cmp_eq_f32_e64 vcc, |v3|, |v7|
; SI-NEXT:    v_cndmask_b32_e32 v11, v3, v11, vcc
; SI-NEXT:  ; %bb.26: ; %Flow112
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB12_32
; SI-NEXT:  ; %bb.27: ; %frem.compute
; SI-NEXT:    s_mov_b32 s6, 0x7f800000
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v3|, s6
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v11, v3
; SI-NEXT:    v_cndmask_b32_e32 v16, 0, v11, vcc
; SI-NEXT:    v_frexp_mant_f32_e64 v11, |v3|
; SI-NEXT:    v_cndmask_b32_e64 v11, |v3|, v11, vcc
; SI-NEXT:    v_ldexp_f32_e64 v13, v11, 12
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v7|, s6
; SI-NEXT:    v_frexp_mant_f32_e64 v11, |v7|
; SI-NEXT:    v_cndmask_b32_e64 v12, |v7|, v11, vcc
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v11, v7
; SI-NEXT:    v_ldexp_f32_e64 v12, v12, 1
; SI-NEXT:    v_cndmask_b32_e32 v17, 0, v11, vcc
; SI-NEXT:    v_div_scale_f32 v18, s[6:7], v12, v12, 1.0
; SI-NEXT:    v_add_i32_e32 v11, vcc, -1, v17
; SI-NEXT:    v_rcp_f32_e32 v19, v18
; SI-NEXT:    v_not_b32_e32 v14, v11
; SI-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
; SI-NEXT:    v_div_scale_f32 v15, vcc, 1.0, v12, 1.0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    v_fma_f32 v20, -v18, v19, 1.0
; SI-NEXT:    v_fma_f32 v19, v20, v19, v19
; SI-NEXT:    v_mul_f32_e32 v20, v15, v19
; SI-NEXT:    v_fma_f32 v21, -v18, v20, v15
; SI-NEXT:    v_fma_f32 v20, v21, v19, v20
; SI-NEXT:    v_fma_f32 v15, -v18, v20, v15
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    v_div_fmas_f32 v15, v15, v19, v20
; SI-NEXT:    v_div_fixup_f32 v15, v15, v12, 1.0
; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v14
; SI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; SI-NEXT:    s_cbranch_execz .LBB12_31
; SI-NEXT:  ; %bb.28: ; %frem.loop_body.preheader
; SI-NEXT:    v_sub_i32_e32 v14, vcc, v16, v17
; SI-NEXT:    v_add_i32_e32 v14, vcc, 12, v14
; SI-NEXT:    s_mov_b64 s[8:9], 0
; SI-NEXT:  .LBB12_29: ; %frem.loop_body
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v16, v13
; SI-NEXT:    v_mul_f32_e32 v13, v16, v15
; SI-NEXT:    v_rndne_f32_e32 v13, v13
; SI-NEXT:    v_fma_f32 v13, -v13, v12, v16
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v13
; SI-NEXT:    v_add_f32_e32 v17, v13, v12
; SI-NEXT:    v_cndmask_b32_e32 v13, v13, v17, vcc
; SI-NEXT:    v_add_i32_e32 v14, vcc, -12, v14
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v14
; SI-NEXT:    v_ldexp_f32_e64 v13, v13, 12
; SI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; SI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; SI-NEXT:    s_cbranch_execnz .LBB12_29
; SI-NEXT:  ; %bb.30: ; %Flow
; SI-NEXT:    s_or_b64 exec, exec, s[8:9]
; SI-NEXT:    v_mov_b32_e32 v13, v16
; SI-NEXT:  .LBB12_31: ; %Flow111
; SI-NEXT:    s_or_b64 exec, exec, s[6:7]
; SI-NEXT:    v_add_i32_e32 v14, vcc, -11, v14
; SI-NEXT:    v_ldexp_f32_e32 v13, v13, v14
; SI-NEXT:    v_mul_f32_e32 v14, v13, v15
; SI-NEXT:    v_rndne_f32_e32 v14, v14
; SI-NEXT:    v_fma_f32 v13, -v14, v12, v13
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v13
; SI-NEXT:    v_add_f32_e32 v12, v13, v12
; SI-NEXT:    v_cndmask_b32_e32 v12, v13, v12, vcc
; SI-NEXT:    v_ldexp_f32_e32 v11, v12, v11
; SI-NEXT:    s_brev_b32 s6, -2
; SI-NEXT:    v_bfi_b32 v11, s6, v11, v3
; SI-NEXT:  .LBB12_32: ; %Flow113
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    s_mov_b32 s6, 0x7f800000
; SI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v4
; SI-NEXT:    v_cmp_nge_f32_e64 s[4:5], |v0|, s6
; SI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; SI-NEXT:    v_mov_b32_e32 v4, 0x7fc00000
; SI-NEXT:    v_cndmask_b32_e32 v0, v4, v8, vcc
; SI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v5
; SI-NEXT:    v_cmp_nge_f32_e64 s[4:5], |v1|, s6
; SI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; SI-NEXT:    v_cndmask_b32_e32 v1, v4, v9, vcc
; SI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v6
; SI-NEXT:    v_cmp_nge_f32_e64 s[4:5], |v2|, s6
; SI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; SI-NEXT:    v_cndmask_b32_e32 v2, v4, v10, vcc
; SI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v7
; SI-NEXT:    v_cmp_nge_f32_e64 s[4:5], |v3|, s6
; SI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; SI-NEXT:    v_cndmask_b32_e32 v3, v4, v11, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; CI-LABEL: frem_v4f32:
; CI:       ; %bb.0:
; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-NEXT:    v_cmp_ngt_f32_e64 s[4:5], |v0|, |v4|
; CI-NEXT:    ; implicit-def: $vgpr8
; CI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; CI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; CI-NEXT:  ; %bb.1: ; %frem.else78
; CI-NEXT:    v_and_b32_e32 v8, 0x80000000, v0
; CI-NEXT:    v_cmp_eq_f32_e64 vcc, |v0|, |v4|
; CI-NEXT:    v_cndmask_b32_e32 v8, v0, v8, vcc
; CI-NEXT:  ; %bb.2: ; %Flow124
; CI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; CI-NEXT:    s_cbranch_execz .LBB12_8
; CI-NEXT:  ; %bb.3: ; %frem.compute77
; CI-NEXT:    v_frexp_mant_f32_e64 v9, |v4|
; CI-NEXT:    v_ldexp_f32_e64 v9, v9, 1
; CI-NEXT:    v_div_scale_f32 v15, s[6:7], v9, v9, 1.0
; CI-NEXT:    v_frexp_mant_f32_e64 v8, |v0|
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v14, v4
; CI-NEXT:    v_ldexp_f32_e64 v11, v8, 12
; CI-NEXT:    v_add_i32_e32 v8, vcc, -1, v14
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v13, v0
; CI-NEXT:    v_not_b32_e32 v10, v8
; CI-NEXT:    v_add_i32_e32 v10, vcc, v10, v13
; CI-NEXT:    v_div_scale_f32 v12, vcc, 1.0, v9, 1.0
; CI-NEXT:    v_rcp_f32_e32 v16, v15
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v17, -v15, v16, 1.0
; CI-NEXT:    v_fma_f32 v16, v17, v16, v16
; CI-NEXT:    v_mul_f32_e32 v17, v12, v16
; CI-NEXT:    v_fma_f32 v18, -v15, v17, v12
; CI-NEXT:    v_fma_f32 v17, v18, v16, v17
; CI-NEXT:    v_fma_f32 v12, -v15, v17, v12
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v12, v12, v16, v17
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v10
; CI-NEXT:    v_div_fixup_f32 v12, v12, v9, 1.0
; CI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; CI-NEXT:    s_cbranch_execz .LBB12_7
; CI-NEXT:  ; %bb.4: ; %frem.loop_body85.preheader
; CI-NEXT:    v_sub_i32_e32 v10, vcc, v13, v14
; CI-NEXT:    v_add_i32_e32 v10, vcc, 12, v10
; CI-NEXT:    s_mov_b64 s[8:9], 0
; CI-NEXT:  .LBB12_5: ; %frem.loop_body85
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v13, v11
; CI-NEXT:    v_mul_f32_e32 v11, v13, v12
; CI-NEXT:    v_rndne_f32_e32 v11, v11
; CI-NEXT:    v_fma_f32 v11, -v11, v9, v13
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v11
; CI-NEXT:    v_add_f32_e32 v14, v11, v9
; CI-NEXT:    v_cndmask_b32_e32 v11, v11, v14, vcc
; CI-NEXT:    v_add_i32_e32 v10, vcc, -12, v10
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v10
; CI-NEXT:    v_ldexp_f32_e64 v11, v11, 12
; CI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; CI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; CI-NEXT:    s_cbranch_execnz .LBB12_5
; CI-NEXT:  ; %bb.6: ; %Flow122
; CI-NEXT:    s_or_b64 exec, exec, s[8:9]
; CI-NEXT:    v_mov_b32_e32 v11, v13
; CI-NEXT:  .LBB12_7: ; %Flow123
; CI-NEXT:    s_or_b64 exec, exec, s[6:7]
; CI-NEXT:    v_add_i32_e32 v10, vcc, -11, v10
; CI-NEXT:    v_ldexp_f32_e32 v10, v11, v10
; CI-NEXT:    v_mul_f32_e32 v11, v10, v12
; CI-NEXT:    v_rndne_f32_e32 v11, v11
; CI-NEXT:    v_fma_f32 v10, -v11, v9, v10
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v10
; CI-NEXT:    v_add_f32_e32 v9, v10, v9
; CI-NEXT:    v_cndmask_b32_e32 v9, v10, v9, vcc
; CI-NEXT:    v_ldexp_f32_e32 v8, v9, v8
; CI-NEXT:    s_brev_b32 s6, -2
; CI-NEXT:    v_bfi_b32 v8, s6, v8, v0
; CI-NEXT:  .LBB12_8: ; %Flow125
; CI-NEXT:    s_or_b64 exec, exec, s[4:5]
; CI-NEXT:    v_cmp_ngt_f32_e64 s[4:5], |v1|, |v5|
; CI-NEXT:    ; implicit-def: $vgpr9
; CI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; CI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; CI-NEXT:  ; %bb.9: ; %frem.else47
; CI-NEXT:    v_and_b32_e32 v9, 0x80000000, v1
; CI-NEXT:    v_cmp_eq_f32_e64 vcc, |v1|, |v5|
; CI-NEXT:    v_cndmask_b32_e32 v9, v1, v9, vcc
; CI-NEXT:  ; %bb.10: ; %Flow120
; CI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; CI-NEXT:    s_cbranch_execz .LBB12_16
; CI-NEXT:  ; %bb.11: ; %frem.compute46
; CI-NEXT:    v_frexp_mant_f32_e64 v10, |v5|
; CI-NEXT:    v_ldexp_f32_e64 v10, v10, 1
; CI-NEXT:    v_div_scale_f32 v16, s[6:7], v10, v10, 1.0
; CI-NEXT:    v_frexp_mant_f32_e64 v9, |v1|
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v15, v5
; CI-NEXT:    v_ldexp_f32_e64 v12, v9, 12
; CI-NEXT:    v_add_i32_e32 v9, vcc, -1, v15
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v14, v1
; CI-NEXT:    v_not_b32_e32 v11, v9
; CI-NEXT:    v_add_i32_e32 v11, vcc, v11, v14
; CI-NEXT:    v_div_scale_f32 v13, vcc, 1.0, v10, 1.0
; CI-NEXT:    v_rcp_f32_e32 v17, v16
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v18, -v16, v17, 1.0
; CI-NEXT:    v_fma_f32 v17, v18, v17, v17
; CI-NEXT:    v_mul_f32_e32 v18, v13, v17
; CI-NEXT:    v_fma_f32 v19, -v16, v18, v13
; CI-NEXT:    v_fma_f32 v18, v19, v17, v18
; CI-NEXT:    v_fma_f32 v13, -v16, v18, v13
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v13, v13, v17, v18
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v11
; CI-NEXT:    v_div_fixup_f32 v13, v13, v10, 1.0
; CI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; CI-NEXT:    s_cbranch_execz .LBB12_15
; CI-NEXT:  ; %bb.12: ; %frem.loop_body54.preheader
; CI-NEXT:    v_sub_i32_e32 v11, vcc, v14, v15
; CI-NEXT:    v_add_i32_e32 v11, vcc, 12, v11
; CI-NEXT:    s_mov_b64 s[8:9], 0
; CI-NEXT:  .LBB12_13: ; %frem.loop_body54
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v14, v12
; CI-NEXT:    v_mul_f32_e32 v12, v14, v13
; CI-NEXT:    v_rndne_f32_e32 v12, v12
; CI-NEXT:    v_fma_f32 v12, -v12, v10, v14
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v12
; CI-NEXT:    v_add_f32_e32 v15, v12, v10
; CI-NEXT:    v_cndmask_b32_e32 v12, v12, v15, vcc
; CI-NEXT:    v_add_i32_e32 v11, vcc, -12, v11
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v11
; CI-NEXT:    v_ldexp_f32_e64 v12, v12, 12
; CI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; CI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; CI-NEXT:    s_cbranch_execnz .LBB12_13
; CI-NEXT:  ; %bb.14: ; %Flow118
; CI-NEXT:    s_or_b64 exec, exec, s[8:9]
; CI-NEXT:    v_mov_b32_e32 v12, v14
; CI-NEXT:  .LBB12_15: ; %Flow119
; CI-NEXT:    s_or_b64 exec, exec, s[6:7]
; CI-NEXT:    v_add_i32_e32 v11, vcc, -11, v11
; CI-NEXT:    v_ldexp_f32_e32 v11, v12, v11
; CI-NEXT:    v_mul_f32_e32 v12, v11, v13
; CI-NEXT:    v_rndne_f32_e32 v12, v12
; CI-NEXT:    v_fma_f32 v11, -v12, v10, v11
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v11
; CI-NEXT:    v_add_f32_e32 v10, v11, v10
; CI-NEXT:    v_cndmask_b32_e32 v10, v11, v10, vcc
; CI-NEXT:    v_ldexp_f32_e32 v9, v10, v9
; CI-NEXT:    s_brev_b32 s6, -2
; CI-NEXT:    v_bfi_b32 v9, s6, v9, v1
; CI-NEXT:  .LBB12_16: ; %Flow121
; CI-NEXT:    s_or_b64 exec, exec, s[4:5]
; CI-NEXT:    v_cmp_ngt_f32_e64 s[4:5], |v2|, |v6|
; CI-NEXT:    ; implicit-def: $vgpr10
; CI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; CI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; CI-NEXT:  ; %bb.17: ; %frem.else16
; CI-NEXT:    v_and_b32_e32 v10, 0x80000000, v2
; CI-NEXT:    v_cmp_eq_f32_e64 vcc, |v2|, |v6|
; CI-NEXT:    v_cndmask_b32_e32 v10, v2, v10, vcc
; CI-NEXT:  ; %bb.18: ; %Flow116
; CI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; CI-NEXT:    s_cbranch_execz .LBB12_24
; CI-NEXT:  ; %bb.19: ; %frem.compute15
; CI-NEXT:    v_frexp_mant_f32_e64 v11, |v6|
; CI-NEXT:    v_ldexp_f32_e64 v11, v11, 1
; CI-NEXT:    v_div_scale_f32 v17, s[6:7], v11, v11, 1.0
; CI-NEXT:    v_frexp_mant_f32_e64 v10, |v2|
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v16, v6
; CI-NEXT:    v_ldexp_f32_e64 v13, v10, 12
; CI-NEXT:    v_add_i32_e32 v10, vcc, -1, v16
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v15, v2
; CI-NEXT:    v_not_b32_e32 v12, v10
; CI-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
; CI-NEXT:    v_div_scale_f32 v14, vcc, 1.0, v11, 1.0
; CI-NEXT:    v_rcp_f32_e32 v18, v17
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v19, -v17, v18, 1.0
; CI-NEXT:    v_fma_f32 v18, v19, v18, v18
; CI-NEXT:    v_mul_f32_e32 v19, v14, v18
; CI-NEXT:    v_fma_f32 v20, -v17, v19, v14
; CI-NEXT:    v_fma_f32 v19, v20, v18, v19
; CI-NEXT:    v_fma_f32 v14, -v17, v19, v14
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v14, v14, v18, v19
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v12
; CI-NEXT:    v_div_fixup_f32 v14, v14, v11, 1.0
; CI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; CI-NEXT:    s_cbranch_execz .LBB12_23
; CI-NEXT:  ; %bb.20: ; %frem.loop_body23.preheader
; CI-NEXT:    v_sub_i32_e32 v12, vcc, v15, v16
; CI-NEXT:    v_add_i32_e32 v12, vcc, 12, v12
; CI-NEXT:    s_mov_b64 s[8:9], 0
; CI-NEXT:  .LBB12_21: ; %frem.loop_body23
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v15, v13
; CI-NEXT:    v_mul_f32_e32 v13, v15, v14
; CI-NEXT:    v_rndne_f32_e32 v13, v13
; CI-NEXT:    v_fma_f32 v13, -v13, v11, v15
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v13
; CI-NEXT:    v_add_f32_e32 v16, v13, v11
; CI-NEXT:    v_cndmask_b32_e32 v13, v13, v16, vcc
; CI-NEXT:    v_add_i32_e32 v12, vcc, -12, v12
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v12
; CI-NEXT:    v_ldexp_f32_e64 v13, v13, 12
; CI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; CI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; CI-NEXT:    s_cbranch_execnz .LBB12_21
; CI-NEXT:  ; %bb.22: ; %Flow114
; CI-NEXT:    s_or_b64 exec, exec, s[8:9]
; CI-NEXT:    v_mov_b32_e32 v13, v15
; CI-NEXT:  .LBB12_23: ; %Flow115
; CI-NEXT:    s_or_b64 exec, exec, s[6:7]
; CI-NEXT:    v_add_i32_e32 v12, vcc, -11, v12
; CI-NEXT:    v_ldexp_f32_e32 v12, v13, v12
; CI-NEXT:    v_mul_f32_e32 v13, v12, v14
; CI-NEXT:    v_rndne_f32_e32 v13, v13
; CI-NEXT:    v_fma_f32 v12, -v13, v11, v12
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v12
; CI-NEXT:    v_add_f32_e32 v11, v12, v11
; CI-NEXT:    v_cndmask_b32_e32 v11, v12, v11, vcc
; CI-NEXT:    v_ldexp_f32_e32 v10, v11, v10
; CI-NEXT:    s_brev_b32 s6, -2
; CI-NEXT:    v_bfi_b32 v10, s6, v10, v2
; CI-NEXT:  .LBB12_24: ; %Flow117
; CI-NEXT:    s_or_b64 exec, exec, s[4:5]
; CI-NEXT:    v_cmp_ngt_f32_e64 s[4:5], |v3|, |v7|
; CI-NEXT:    ; implicit-def: $vgpr11
; CI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; CI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; CI-NEXT:  ; %bb.25: ; %frem.else
; CI-NEXT:    v_and_b32_e32 v11, 0x80000000, v3
; CI-NEXT:    v_cmp_eq_f32_e64 vcc, |v3|, |v7|
; CI-NEXT:    v_cndmask_b32_e32 v11, v3, v11, vcc
; CI-NEXT:  ; %bb.26: ; %Flow112
; CI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; CI-NEXT:    s_cbranch_execz .LBB12_32
; CI-NEXT:  ; %bb.27: ; %frem.compute
; CI-NEXT:    v_frexp_mant_f32_e64 v12, |v7|
; CI-NEXT:    v_ldexp_f32_e64 v12, v12, 1
; CI-NEXT:    v_div_scale_f32 v18, s[6:7], v12, v12, 1.0
; CI-NEXT:    v_frexp_mant_f32_e64 v11, |v3|
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v17, v7
; CI-NEXT:    v_ldexp_f32_e64 v14, v11, 12
; CI-NEXT:    v_add_i32_e32 v11, vcc, -1, v17
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v16, v3
; CI-NEXT:    v_not_b32_e32 v13, v11
; CI-NEXT:    v_add_i32_e32 v13, vcc, v13, v16
; CI-NEXT:    v_div_scale_f32 v15, vcc, 1.0, v12, 1.0
; CI-NEXT:    v_rcp_f32_e32 v19, v18
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v20, -v18, v19, 1.0
; CI-NEXT:    v_fma_f32 v19, v20, v19, v19
; CI-NEXT:    v_mul_f32_e32 v20, v15, v19
; CI-NEXT:    v_fma_f32 v21, -v18, v20, v15
; CI-NEXT:    v_fma_f32 v20, v21, v19, v20
; CI-NEXT:    v_fma_f32 v15, -v18, v20, v15
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v15, v15, v19, v20
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v13
; CI-NEXT:    v_div_fixup_f32 v15, v15, v12, 1.0
; CI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; CI-NEXT:    s_cbranch_execz .LBB12_31
; CI-NEXT:  ; %bb.28: ; %frem.loop_body.preheader
; CI-NEXT:    v_sub_i32_e32 v13, vcc, v16, v17
; CI-NEXT:    v_add_i32_e32 v13, vcc, 12, v13
; CI-NEXT:    s_mov_b64 s[8:9], 0
; CI-NEXT:  .LBB12_29: ; %frem.loop_body
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v16, v14
; CI-NEXT:    v_mul_f32_e32 v14, v16, v15
; CI-NEXT:    v_rndne_f32_e32 v14, v14
; CI-NEXT:    v_fma_f32 v14, -v14, v12, v16
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v14
; CI-NEXT:    v_add_f32_e32 v17, v14, v12
; CI-NEXT:    v_cndmask_b32_e32 v14, v14, v17, vcc
; CI-NEXT:    v_add_i32_e32 v13, vcc, -12, v13
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v13
; CI-NEXT:    v_ldexp_f32_e64 v14, v14, 12
; CI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; CI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; CI-NEXT:    s_cbranch_execnz .LBB12_29
; CI-NEXT:  ; %bb.30: ; %Flow
; CI-NEXT:    s_or_b64 exec, exec, s[8:9]
; CI-NEXT:    v_mov_b32_e32 v14, v16
; CI-NEXT:  .LBB12_31: ; %Flow111
; CI-NEXT:    s_or_b64 exec, exec, s[6:7]
; CI-NEXT:    v_add_i32_e32 v13, vcc, -11, v13
; CI-NEXT:    v_ldexp_f32_e32 v13, v14, v13
; CI-NEXT:    v_mul_f32_e32 v14, v13, v15
; CI-NEXT:    v_rndne_f32_e32 v14, v14
; CI-NEXT:    v_fma_f32 v13, -v14, v12, v13
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v13
; CI-NEXT:    v_add_f32_e32 v12, v13, v12
; CI-NEXT:    v_cndmask_b32_e32 v12, v13, v12, vcc
; CI-NEXT:    v_ldexp_f32_e32 v11, v12, v11
; CI-NEXT:    s_brev_b32 s6, -2
; CI-NEXT:    v_bfi_b32 v11, s6, v11, v3
; CI-NEXT:  .LBB12_32: ; %Flow113
; CI-NEXT:    s_or_b64 exec, exec, s[4:5]
; CI-NEXT:    s_mov_b32 s6, 0x7f800000
; CI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v4
; CI-NEXT:    v_cmp_nge_f32_e64 s[4:5], |v0|, s6
; CI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; CI-NEXT:    v_mov_b32_e32 v4, 0x7fc00000
; CI-NEXT:    v_cndmask_b32_e32 v0, v4, v8, vcc
; CI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v5
; CI-NEXT:    v_cmp_nge_f32_e64 s[4:5], |v1|, s6
; CI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; CI-NEXT:    v_cndmask_b32_e32 v1, v4, v9, vcc
; CI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v6
; CI-NEXT:    v_cmp_nge_f32_e64 s[4:5], |v2|, s6
; CI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; CI-NEXT:    v_cndmask_b32_e32 v2, v4, v10, vcc
; CI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v7
; CI-NEXT:    v_cmp_nge_f32_e64 s[4:5], |v3|, s6
; CI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; CI-NEXT:    v_cndmask_b32_e32 v3, v4, v11, vcc
; CI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: frem_v4f32:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ngt_f32_e64 s[4:5], |v0|, |v4|
; VI-NEXT:    ; implicit-def: $vgpr8
; VI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; VI-NEXT:  ; %bb.1: ; %frem.else78
; VI-NEXT:    v_and_b32_e32 v8, 0x80000000, v0
; VI-NEXT:    v_cmp_eq_f32_e64 vcc, |v0|, |v4|
; VI-NEXT:    v_cndmask_b32_e32 v8, v0, v8, vcc
; VI-NEXT:  ; %bb.2: ; %Flow124
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB12_8
; VI-NEXT:  ; %bb.3: ; %frem.compute77
; VI-NEXT:    v_frexp_mant_f32_e64 v9, |v4|
; VI-NEXT:    v_ldexp_f32 v9, v9, 1
; VI-NEXT:    v_div_scale_f32 v15, s[6:7], v9, v9, 1.0
; VI-NEXT:    v_frexp_mant_f32_e64 v8, |v0|
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v14, v4
; VI-NEXT:    v_ldexp_f32 v11, v8, 12
; VI-NEXT:    v_add_u32_e32 v8, vcc, -1, v14
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v13, v0
; VI-NEXT:    v_not_b32_e32 v10, v8
; VI-NEXT:    v_add_u32_e32 v10, vcc, v10, v13
; VI-NEXT:    v_div_scale_f32 v12, vcc, 1.0, v9, 1.0
; VI-NEXT:    v_rcp_f32_e32 v16, v15
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT:    v_fma_f32 v17, -v15, v16, 1.0
; VI-NEXT:    v_fma_f32 v16, v17, v16, v16
; VI-NEXT:    v_mul_f32_e32 v17, v12, v16
; VI-NEXT:    v_fma_f32 v18, -v15, v17, v12
; VI-NEXT:    v_fma_f32 v17, v18, v16, v17
; VI-NEXT:    v_fma_f32 v12, -v15, v17, v12
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; VI-NEXT:    v_div_fmas_f32 v12, v12, v16, v17
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v10
; VI-NEXT:    v_div_fixup_f32 v12, v12, v9, 1.0
; VI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; VI-NEXT:    s_cbranch_execz .LBB12_7
; VI-NEXT:  ; %bb.4: ; %frem.loop_body85.preheader
; VI-NEXT:    v_sub_u32_e32 v10, vcc, v13, v14
; VI-NEXT:    v_add_u32_e32 v10, vcc, 12, v10
; VI-NEXT:    s_mov_b64 s[8:9], 0
; VI-NEXT:  .LBB12_5: ; %frem.loop_body85
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v13, v11
; VI-NEXT:    v_mul_f32_e32 v11, v13, v12
; VI-NEXT:    v_rndne_f32_e32 v11, v11
; VI-NEXT:    v_fma_f32 v11, -v11, v9, v13
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v11
; VI-NEXT:    v_add_f32_e32 v14, v11, v9
; VI-NEXT:    v_cndmask_b32_e32 v11, v11, v14, vcc
; VI-NEXT:    v_add_u32_e32 v10, vcc, -12, v10
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v10
; VI-NEXT:    v_ldexp_f32 v11, v11, 12
; VI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; VI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; VI-NEXT:    s_cbranch_execnz .LBB12_5
; VI-NEXT:  ; %bb.6: ; %Flow122
; VI-NEXT:    s_or_b64 exec, exec, s[8:9]
; VI-NEXT:    v_mov_b32_e32 v11, v13
; VI-NEXT:  .LBB12_7: ; %Flow123
; VI-NEXT:    s_or_b64 exec, exec, s[6:7]
; VI-NEXT:    v_add_u32_e32 v10, vcc, -11, v10
; VI-NEXT:    v_ldexp_f32 v10, v11, v10
; VI-NEXT:    v_mul_f32_e32 v11, v10, v12
; VI-NEXT:    v_rndne_f32_e32 v11, v11
; VI-NEXT:    v_fma_f32 v10, -v11, v9, v10
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v10
; VI-NEXT:    v_add_f32_e32 v9, v10, v9
; VI-NEXT:    v_cndmask_b32_e32 v9, v10, v9, vcc
; VI-NEXT:    v_ldexp_f32 v8, v9, v8
; VI-NEXT:    s_brev_b32 s6, -2
; VI-NEXT:    v_bfi_b32 v8, s6, v8, v0
; VI-NEXT:  .LBB12_8: ; %Flow125
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    v_cmp_ngt_f32_e64 s[4:5], |v1|, |v5|
; VI-NEXT:    ; implicit-def: $vgpr9
; VI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; VI-NEXT:  ; %bb.9: ; %frem.else47
; VI-NEXT:    v_and_b32_e32 v9, 0x80000000, v1
; VI-NEXT:    v_cmp_eq_f32_e64 vcc, |v1|, |v5|
; VI-NEXT:    v_cndmask_b32_e32 v9, v1, v9, vcc
; VI-NEXT:  ; %bb.10: ; %Flow120
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB12_16
; VI-NEXT:  ; %bb.11: ; %frem.compute46
; VI-NEXT:    v_frexp_mant_f32_e64 v10, |v5|
; VI-NEXT:    v_ldexp_f32 v10, v10, 1
; VI-NEXT:    v_div_scale_f32 v16, s[6:7], v10, v10, 1.0
; VI-NEXT:    v_frexp_mant_f32_e64 v9, |v1|
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v15, v5
; VI-NEXT:    v_ldexp_f32 v12, v9, 12
; VI-NEXT:    v_add_u32_e32 v9, vcc, -1, v15
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v14, v1
; VI-NEXT:    v_not_b32_e32 v11, v9
; VI-NEXT:    v_add_u32_e32 v11, vcc, v11, v14
; VI-NEXT:    v_div_scale_f32 v13, vcc, 1.0, v10, 1.0
; VI-NEXT:    v_rcp_f32_e32 v17, v16
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT:    v_fma_f32 v18, -v16, v17, 1.0
; VI-NEXT:    v_fma_f32 v17, v18, v17, v17
; VI-NEXT:    v_mul_f32_e32 v18, v13, v17
; VI-NEXT:    v_fma_f32 v19, -v16, v18, v13
; VI-NEXT:    v_fma_f32 v18, v19, v17, v18
; VI-NEXT:    v_fma_f32 v13, -v16, v18, v13
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; VI-NEXT:    v_div_fmas_f32 v13, v13, v17, v18
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v11
; VI-NEXT:    v_div_fixup_f32 v13, v13, v10, 1.0
; VI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; VI-NEXT:    s_cbranch_execz .LBB12_15
; VI-NEXT:  ; %bb.12: ; %frem.loop_body54.preheader
; VI-NEXT:    v_sub_u32_e32 v11, vcc, v14, v15
; VI-NEXT:    v_add_u32_e32 v11, vcc, 12, v11
; VI-NEXT:    s_mov_b64 s[8:9], 0
; VI-NEXT:  .LBB12_13: ; %frem.loop_body54
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v14, v12
; VI-NEXT:    v_mul_f32_e32 v12, v14, v13
; VI-NEXT:    v_rndne_f32_e32 v12, v12
; VI-NEXT:    v_fma_f32 v12, -v12, v10, v14
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v12
; VI-NEXT:    v_add_f32_e32 v15, v12, v10
; VI-NEXT:    v_cndmask_b32_e32 v12, v12, v15, vcc
; VI-NEXT:    v_add_u32_e32 v11, vcc, -12, v11
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v11
; VI-NEXT:    v_ldexp_f32 v12, v12, 12
; VI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; VI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; VI-NEXT:    s_cbranch_execnz .LBB12_13
; VI-NEXT:  ; %bb.14: ; %Flow118
; VI-NEXT:    s_or_b64 exec, exec, s[8:9]
; VI-NEXT:    v_mov_b32_e32 v12, v14
; VI-NEXT:  .LBB12_15: ; %Flow119
; VI-NEXT:    s_or_b64 exec, exec, s[6:7]
; VI-NEXT:    v_add_u32_e32 v11, vcc, -11, v11
; VI-NEXT:    v_ldexp_f32 v11, v12, v11
; VI-NEXT:    v_mul_f32_e32 v12, v11, v13
; VI-NEXT:    v_rndne_f32_e32 v12, v12
; VI-NEXT:    v_fma_f32 v11, -v12, v10, v11
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v11
; VI-NEXT:    v_add_f32_e32 v10, v11, v10
; VI-NEXT:    v_cndmask_b32_e32 v10, v11, v10, vcc
; VI-NEXT:    v_ldexp_f32 v9, v10, v9
; VI-NEXT:    s_brev_b32 s6, -2
; VI-NEXT:    v_bfi_b32 v9, s6, v9, v1
; VI-NEXT:  .LBB12_16: ; %Flow121
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    v_cmp_ngt_f32_e64 s[4:5], |v2|, |v6|
; VI-NEXT:    ; implicit-def: $vgpr10
; VI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; VI-NEXT:  ; %bb.17: ; %frem.else16
; VI-NEXT:    v_and_b32_e32 v10, 0x80000000, v2
; VI-NEXT:    v_cmp_eq_f32_e64 vcc, |v2|, |v6|
; VI-NEXT:    v_cndmask_b32_e32 v10, v2, v10, vcc
; VI-NEXT:  ; %bb.18: ; %Flow116
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB12_24
; VI-NEXT:  ; %bb.19: ; %frem.compute15
; VI-NEXT:    v_frexp_mant_f32_e64 v11, |v6|
; VI-NEXT:    v_ldexp_f32 v11, v11, 1
; VI-NEXT:    v_div_scale_f32 v17, s[6:7], v11, v11, 1.0
; VI-NEXT:    v_frexp_mant_f32_e64 v10, |v2|
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v16, v6
; VI-NEXT:    v_ldexp_f32 v13, v10, 12
; VI-NEXT:    v_add_u32_e32 v10, vcc, -1, v16
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v15, v2
; VI-NEXT:    v_not_b32_e32 v12, v10
; VI-NEXT:    v_add_u32_e32 v12, vcc, v12, v15
; VI-NEXT:    v_div_scale_f32 v14, vcc, 1.0, v11, 1.0
; VI-NEXT:    v_rcp_f32_e32 v18, v17
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT:    v_fma_f32 v19, -v17, v18, 1.0
; VI-NEXT:    v_fma_f32 v18, v19, v18, v18
; VI-NEXT:    v_mul_f32_e32 v19, v14, v18
; VI-NEXT:    v_fma_f32 v20, -v17, v19, v14
; VI-NEXT:    v_fma_f32 v19, v20, v18, v19
; VI-NEXT:    v_fma_f32 v14, -v17, v19, v14
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; VI-NEXT:    v_div_fmas_f32 v14, v14, v18, v19
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v12
; VI-NEXT:    v_div_fixup_f32 v14, v14, v11, 1.0
; VI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; VI-NEXT:    s_cbranch_execz .LBB12_23
; VI-NEXT:  ; %bb.20: ; %frem.loop_body23.preheader
; VI-NEXT:    v_sub_u32_e32 v12, vcc, v15, v16
; VI-NEXT:    v_add_u32_e32 v12, vcc, 12, v12
; VI-NEXT:    s_mov_b64 s[8:9], 0
; VI-NEXT:  .LBB12_21: ; %frem.loop_body23
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v15, v13
; VI-NEXT:    v_mul_f32_e32 v13, v15, v14
; VI-NEXT:    v_rndne_f32_e32 v13, v13
; VI-NEXT:    v_fma_f32 v13, -v13, v11, v15
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v13
; VI-NEXT:    v_add_f32_e32 v16, v13, v11
; VI-NEXT:    v_cndmask_b32_e32 v13, v13, v16, vcc
; VI-NEXT:    v_add_u32_e32 v12, vcc, -12, v12
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v12
; VI-NEXT:    v_ldexp_f32 v13, v13, 12
; VI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; VI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; VI-NEXT:    s_cbranch_execnz .LBB12_21
; VI-NEXT:  ; %bb.22: ; %Flow114
; VI-NEXT:    s_or_b64 exec, exec, s[8:9]
; VI-NEXT:    v_mov_b32_e32 v13, v15
; VI-NEXT:  .LBB12_23: ; %Flow115
; VI-NEXT:    s_or_b64 exec, exec, s[6:7]
; VI-NEXT:    v_add_u32_e32 v12, vcc, -11, v12
; VI-NEXT:    v_ldexp_f32 v12, v13, v12
; VI-NEXT:    v_mul_f32_e32 v13, v12, v14
; VI-NEXT:    v_rndne_f32_e32 v13, v13
; VI-NEXT:    v_fma_f32 v12, -v13, v11, v12
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v12
; VI-NEXT:    v_add_f32_e32 v11, v12, v11
; VI-NEXT:    v_cndmask_b32_e32 v11, v12, v11, vcc
; VI-NEXT:    v_ldexp_f32 v10, v11, v10
; VI-NEXT:    s_brev_b32 s6, -2
; VI-NEXT:    v_bfi_b32 v10, s6, v10, v2
; VI-NEXT:  .LBB12_24: ; %Flow117
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    v_cmp_ngt_f32_e64 s[4:5], |v3|, |v7|
; VI-NEXT:    ; implicit-def: $vgpr11
; VI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; VI-NEXT:  ; %bb.25: ; %frem.else
; VI-NEXT:    v_and_b32_e32 v11, 0x80000000, v3
; VI-NEXT:    v_cmp_eq_f32_e64 vcc, |v3|, |v7|
; VI-NEXT:    v_cndmask_b32_e32 v11, v3, v11, vcc
; VI-NEXT:  ; %bb.26: ; %Flow112
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB12_32
; VI-NEXT:  ; %bb.27: ; %frem.compute
; VI-NEXT:    v_frexp_mant_f32_e64 v12, |v7|
; VI-NEXT:    v_ldexp_f32 v12, v12, 1
; VI-NEXT:    v_div_scale_f32 v18, s[6:7], v12, v12, 1.0
; VI-NEXT:    v_frexp_mant_f32_e64 v11, |v3|
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v17, v7
; VI-NEXT:    v_ldexp_f32 v14, v11, 12
; VI-NEXT:    v_add_u32_e32 v11, vcc, -1, v17
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v16, v3
; VI-NEXT:    v_not_b32_e32 v13, v11
; VI-NEXT:    v_add_u32_e32 v13, vcc, v13, v16
; VI-NEXT:    v_div_scale_f32 v15, vcc, 1.0, v12, 1.0
; VI-NEXT:    v_rcp_f32_e32 v19, v18
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT:    v_fma_f32 v20, -v18, v19, 1.0
; VI-NEXT:    v_fma_f32 v19, v20, v19, v19
; VI-NEXT:    v_mul_f32_e32 v20, v15, v19
; VI-NEXT:    v_fma_f32 v21, -v18, v20, v15
; VI-NEXT:    v_fma_f32 v20, v21, v19, v20
; VI-NEXT:    v_fma_f32 v15, -v18, v20, v15
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; VI-NEXT:    v_div_fmas_f32 v15, v15, v19, v20
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v13
; VI-NEXT:    v_div_fixup_f32 v15, v15, v12, 1.0
; VI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; VI-NEXT:    s_cbranch_execz .LBB12_31
; VI-NEXT:  ; %bb.28: ; %frem.loop_body.preheader
; VI-NEXT:    v_sub_u32_e32 v13, vcc, v16, v17
; VI-NEXT:    v_add_u32_e32 v13, vcc, 12, v13
; VI-NEXT:    s_mov_b64 s[8:9], 0
; VI-NEXT:  .LBB12_29: ; %frem.loop_body
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v16, v14
; VI-NEXT:    v_mul_f32_e32 v14, v16, v15
; VI-NEXT:    v_rndne_f32_e32 v14, v14
; VI-NEXT:    v_fma_f32 v14, -v14, v12, v16
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v14
; VI-NEXT:    v_add_f32_e32 v17, v14, v12
; VI-NEXT:    v_cndmask_b32_e32 v14, v14, v17, vcc
; VI-NEXT:    v_add_u32_e32 v13, vcc, -12, v13
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v13
; VI-NEXT:    v_ldexp_f32 v14, v14, 12
; VI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; VI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; VI-NEXT:    s_cbranch_execnz .LBB12_29
; VI-NEXT:  ; %bb.30: ; %Flow
; VI-NEXT:    s_or_b64 exec, exec, s[8:9]
; VI-NEXT:    v_mov_b32_e32 v14, v16
; VI-NEXT:  .LBB12_31: ; %Flow111
; VI-NEXT:    s_or_b64 exec, exec, s[6:7]
; VI-NEXT:    v_add_u32_e32 v13, vcc, -11, v13
; VI-NEXT:    v_ldexp_f32 v13, v14, v13
; VI-NEXT:    v_mul_f32_e32 v14, v13, v15
; VI-NEXT:    v_rndne_f32_e32 v14, v14
; VI-NEXT:    v_fma_f32 v13, -v14, v12, v13
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v13
; VI-NEXT:    v_add_f32_e32 v12, v13, v12
; VI-NEXT:    v_cndmask_b32_e32 v12, v13, v12, vcc
; VI-NEXT:    v_ldexp_f32 v11, v12, v11
; VI-NEXT:    s_brev_b32 s6, -2
; VI-NEXT:    v_bfi_b32 v11, s6, v11, v3
; VI-NEXT:  .LBB12_32: ; %Flow113
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_mov_b32 s6, 0x7f800000
; VI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v4
; VI-NEXT:    v_cmp_nge_f32_e64 s[4:5], |v0|, s6
; VI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; VI-NEXT:    v_mov_b32_e32 v4, 0x7fc00000
; VI-NEXT:    v_cndmask_b32_e32 v0, v4, v8, vcc
; VI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v5
; VI-NEXT:    v_cmp_nge_f32_e64 s[4:5], |v1|, s6
; VI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; VI-NEXT:    v_cndmask_b32_e32 v1, v4, v9, vcc
; VI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v6
; VI-NEXT:    v_cmp_nge_f32_e64 s[4:5], |v2|, s6
; VI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; VI-NEXT:    v_cndmask_b32_e32 v2, v4, v10, vcc
; VI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v7
; VI-NEXT:    v_cmp_nge_f32_e64 s[4:5], |v3|, s6
; VI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; VI-NEXT:    v_cndmask_b32_e32 v3, v4, v11, vcc
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: frem_v4f32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ngt_f32_e64 s[4:5], |v0|, |v4|
; GFX9-NEXT:    ; implicit-def: $vgpr8
; GFX9-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; GFX9-NEXT:  ; %bb.1: ; %frem.else78
; GFX9-NEXT:    v_and_b32_e32 v8, 0x80000000, v0
; GFX9-NEXT:    v_cmp_eq_f32_e64 vcc, |v0|, |v4|
; GFX9-NEXT:    v_cndmask_b32_e32 v8, v0, v8, vcc
; GFX9-NEXT:  ; %bb.2: ; %Flow124
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB12_8
; GFX9-NEXT:  ; %bb.3: ; %frem.compute77
; GFX9-NEXT:    v_frexp_mant_f32_e64 v9, |v4|
; GFX9-NEXT:    v_ldexp_f32 v9, v9, 1
; GFX9-NEXT:    v_div_scale_f32 v15, s[6:7], v9, v9, 1.0
; GFX9-NEXT:    v_div_scale_f32 v12, vcc, 1.0, v9, 1.0
; GFX9-NEXT:    v_frexp_mant_f32_e64 v8, |v0|
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v13, v0
; GFX9-NEXT:    v_ldexp_f32 v11, v8, 12
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v14, v4
; GFX9-NEXT:    v_add_u32_e32 v8, -1, v14
; GFX9-NEXT:    v_xad_u32 v10, v8, -1, v13
; GFX9-NEXT:    v_rcp_f32_e32 v16, v15
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT:    v_fma_f32 v17, -v15, v16, 1.0
; GFX9-NEXT:    v_fma_f32 v16, v17, v16, v16
; GFX9-NEXT:    v_mul_f32_e32 v17, v12, v16
; GFX9-NEXT:    v_fma_f32 v18, -v15, v17, v12
; GFX9-NEXT:    v_fma_f32 v17, v18, v16, v17
; GFX9-NEXT:    v_fma_f32 v12, -v15, v17, v12
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX9-NEXT:    v_div_fmas_f32 v12, v12, v16, v17
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v10
; GFX9-NEXT:    v_div_fixup_f32 v12, v12, v9, 1.0
; GFX9-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; GFX9-NEXT:    s_cbranch_execz .LBB12_7
; GFX9-NEXT:  ; %bb.4: ; %frem.loop_body85.preheader
; GFX9-NEXT:    v_sub_u32_e32 v10, v13, v14
; GFX9-NEXT:    v_add_u32_e32 v10, 12, v10
; GFX9-NEXT:    s_mov_b64 s[8:9], 0
; GFX9-NEXT:  .LBB12_5: ; %frem.loop_body85
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v13, v11
; GFX9-NEXT:    v_mul_f32_e32 v11, v13, v12
; GFX9-NEXT:    v_rndne_f32_e32 v11, v11
; GFX9-NEXT:    v_fma_f32 v11, -v11, v9, v13
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v11
; GFX9-NEXT:    v_add_f32_e32 v14, v11, v9
; GFX9-NEXT:    v_add_u32_e32 v10, -12, v10
; GFX9-NEXT:    v_cndmask_b32_e32 v11, v11, v14, vcc
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v10
; GFX9-NEXT:    v_ldexp_f32 v11, v11, 12
; GFX9-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; GFX9-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; GFX9-NEXT:    s_cbranch_execnz .LBB12_5
; GFX9-NEXT:  ; %bb.6: ; %Flow122
; GFX9-NEXT:    s_or_b64 exec, exec, s[8:9]
; GFX9-NEXT:    v_mov_b32_e32 v11, v13
; GFX9-NEXT:  .LBB12_7: ; %Flow123
; GFX9-NEXT:    s_or_b64 exec, exec, s[6:7]
; GFX9-NEXT:    v_add_u32_e32 v10, -11, v10
; GFX9-NEXT:    v_ldexp_f32 v10, v11, v10
; GFX9-NEXT:    v_mul_f32_e32 v11, v10, v12
; GFX9-NEXT:    v_rndne_f32_e32 v11, v11
; GFX9-NEXT:    v_fma_f32 v10, -v11, v9, v10
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v10
; GFX9-NEXT:    v_add_f32_e32 v9, v10, v9
; GFX9-NEXT:    v_cndmask_b32_e32 v9, v10, v9, vcc
; GFX9-NEXT:    v_ldexp_f32 v8, v9, v8
; GFX9-NEXT:    s_brev_b32 s6, -2
; GFX9-NEXT:    v_bfi_b32 v8, s6, v8, v0
; GFX9-NEXT:  .LBB12_8: ; %Flow125
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    v_cmp_ngt_f32_e64 s[4:5], |v1|, |v5|
; GFX9-NEXT:    ; implicit-def: $vgpr9
; GFX9-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; GFX9-NEXT:  ; %bb.9: ; %frem.else47
; GFX9-NEXT:    v_and_b32_e32 v9, 0x80000000, v1
; GFX9-NEXT:    v_cmp_eq_f32_e64 vcc, |v1|, |v5|
; GFX9-NEXT:    v_cndmask_b32_e32 v9, v1, v9, vcc
; GFX9-NEXT:  ; %bb.10: ; %Flow120
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB12_16
; GFX9-NEXT:  ; %bb.11: ; %frem.compute46
; GFX9-NEXT:    v_frexp_mant_f32_e64 v10, |v5|
; GFX9-NEXT:    v_ldexp_f32 v10, v10, 1
; GFX9-NEXT:    v_div_scale_f32 v16, s[6:7], v10, v10, 1.0
; GFX9-NEXT:    v_div_scale_f32 v13, vcc, 1.0, v10, 1.0
; GFX9-NEXT:    v_frexp_mant_f32_e64 v9, |v1|
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v14, v1
; GFX9-NEXT:    v_ldexp_f32 v12, v9, 12
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v15, v5
; GFX9-NEXT:    v_add_u32_e32 v9, -1, v15
; GFX9-NEXT:    v_xad_u32 v11, v9, -1, v14
; GFX9-NEXT:    v_rcp_f32_e32 v17, v16
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT:    v_fma_f32 v18, -v16, v17, 1.0
; GFX9-NEXT:    v_fma_f32 v17, v18, v17, v17
; GFX9-NEXT:    v_mul_f32_e32 v18, v13, v17
; GFX9-NEXT:    v_fma_f32 v19, -v16, v18, v13
; GFX9-NEXT:    v_fma_f32 v18, v19, v17, v18
; GFX9-NEXT:    v_fma_f32 v13, -v16, v18, v13
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX9-NEXT:    v_div_fmas_f32 v13, v13, v17, v18
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v11
; GFX9-NEXT:    v_div_fixup_f32 v13, v13, v10, 1.0
; GFX9-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; GFX9-NEXT:    s_cbranch_execz .LBB12_15
; GFX9-NEXT:  ; %bb.12: ; %frem.loop_body54.preheader
; GFX9-NEXT:    v_sub_u32_e32 v11, v14, v15
; GFX9-NEXT:    v_add_u32_e32 v11, 12, v11
; GFX9-NEXT:    s_mov_b64 s[8:9], 0
; GFX9-NEXT:  .LBB12_13: ; %frem.loop_body54
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v14, v12
; GFX9-NEXT:    v_mul_f32_e32 v12, v14, v13
; GFX9-NEXT:    v_rndne_f32_e32 v12, v12
; GFX9-NEXT:    v_fma_f32 v12, -v12, v10, v14
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v12
; GFX9-NEXT:    v_add_f32_e32 v15, v12, v10
; GFX9-NEXT:    v_add_u32_e32 v11, -12, v11
; GFX9-NEXT:    v_cndmask_b32_e32 v12, v12, v15, vcc
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v11
; GFX9-NEXT:    v_ldexp_f32 v12, v12, 12
; GFX9-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; GFX9-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; GFX9-NEXT:    s_cbranch_execnz .LBB12_13
; GFX9-NEXT:  ; %bb.14: ; %Flow118
; GFX9-NEXT:    s_or_b64 exec, exec, s[8:9]
; GFX9-NEXT:    v_mov_b32_e32 v12, v14
; GFX9-NEXT:  .LBB12_15: ; %Flow119
; GFX9-NEXT:    s_or_b64 exec, exec, s[6:7]
; GFX9-NEXT:    v_add_u32_e32 v11, -11, v11
; GFX9-NEXT:    v_ldexp_f32 v11, v12, v11
; GFX9-NEXT:    v_mul_f32_e32 v12, v11, v13
; GFX9-NEXT:    v_rndne_f32_e32 v12, v12
; GFX9-NEXT:    v_fma_f32 v11, -v12, v10, v11
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v11
; GFX9-NEXT:    v_add_f32_e32 v10, v11, v10
; GFX9-NEXT:    v_cndmask_b32_e32 v10, v11, v10, vcc
; GFX9-NEXT:    v_ldexp_f32 v9, v10, v9
; GFX9-NEXT:    s_brev_b32 s6, -2
; GFX9-NEXT:    v_bfi_b32 v9, s6, v9, v1
; GFX9-NEXT:  .LBB12_16: ; %Flow121
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    v_cmp_ngt_f32_e64 s[4:5], |v2|, |v6|
; GFX9-NEXT:    ; implicit-def: $vgpr10
; GFX9-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; GFX9-NEXT:  ; %bb.17: ; %frem.else16
; GFX9-NEXT:    v_and_b32_e32 v10, 0x80000000, v2
; GFX9-NEXT:    v_cmp_eq_f32_e64 vcc, |v2|, |v6|
; GFX9-NEXT:    v_cndmask_b32_e32 v10, v2, v10, vcc
; GFX9-NEXT:  ; %bb.18: ; %Flow116
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB12_24
; GFX9-NEXT:  ; %bb.19: ; %frem.compute15
; GFX9-NEXT:    v_frexp_mant_f32_e64 v11, |v6|
; GFX9-NEXT:    v_ldexp_f32 v11, v11, 1
; GFX9-NEXT:    v_div_scale_f32 v17, s[6:7], v11, v11, 1.0
; GFX9-NEXT:    v_div_scale_f32 v14, vcc, 1.0, v11, 1.0
; GFX9-NEXT:    v_frexp_mant_f32_e64 v10, |v2|
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v15, v2
; GFX9-NEXT:    v_ldexp_f32 v13, v10, 12
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v16, v6
; GFX9-NEXT:    v_add_u32_e32 v10, -1, v16
; GFX9-NEXT:    v_xad_u32 v12, v10, -1, v15
; GFX9-NEXT:    v_rcp_f32_e32 v18, v17
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT:    v_fma_f32 v19, -v17, v18, 1.0
; GFX9-NEXT:    v_fma_f32 v18, v19, v18, v18
; GFX9-NEXT:    v_mul_f32_e32 v19, v14, v18
; GFX9-NEXT:    v_fma_f32 v20, -v17, v19, v14
; GFX9-NEXT:    v_fma_f32 v19, v20, v18, v19
; GFX9-NEXT:    v_fma_f32 v14, -v17, v19, v14
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX9-NEXT:    v_div_fmas_f32 v14, v14, v18, v19
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v12
; GFX9-NEXT:    v_div_fixup_f32 v14, v14, v11, 1.0
; GFX9-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; GFX9-NEXT:    s_cbranch_execz .LBB12_23
; GFX9-NEXT:  ; %bb.20: ; %frem.loop_body23.preheader
; GFX9-NEXT:    v_sub_u32_e32 v12, v15, v16
; GFX9-NEXT:    v_add_u32_e32 v12, 12, v12
; GFX9-NEXT:    s_mov_b64 s[8:9], 0
; GFX9-NEXT:  .LBB12_21: ; %frem.loop_body23
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v15, v13
; GFX9-NEXT:    v_mul_f32_e32 v13, v15, v14
; GFX9-NEXT:    v_rndne_f32_e32 v13, v13
; GFX9-NEXT:    v_fma_f32 v13, -v13, v11, v15
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v13
; GFX9-NEXT:    v_add_f32_e32 v16, v13, v11
; GFX9-NEXT:    v_add_u32_e32 v12, -12, v12
; GFX9-NEXT:    v_cndmask_b32_e32 v13, v13, v16, vcc
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v12
; GFX9-NEXT:    v_ldexp_f32 v13, v13, 12
; GFX9-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; GFX9-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; GFX9-NEXT:    s_cbranch_execnz .LBB12_21
; GFX9-NEXT:  ; %bb.22: ; %Flow114
; GFX9-NEXT:    s_or_b64 exec, exec, s[8:9]
; GFX9-NEXT:    v_mov_b32_e32 v13, v15
; GFX9-NEXT:  .LBB12_23: ; %Flow115
; GFX9-NEXT:    s_or_b64 exec, exec, s[6:7]
; GFX9-NEXT:    v_add_u32_e32 v12, -11, v12
; GFX9-NEXT:    v_ldexp_f32 v12, v13, v12
; GFX9-NEXT:    v_mul_f32_e32 v13, v12, v14
; GFX9-NEXT:    v_rndne_f32_e32 v13, v13
; GFX9-NEXT:    v_fma_f32 v12, -v13, v11, v12
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v12
; GFX9-NEXT:    v_add_f32_e32 v11, v12, v11
; GFX9-NEXT:    v_cndmask_b32_e32 v11, v12, v11, vcc
; GFX9-NEXT:    v_ldexp_f32 v10, v11, v10
; GFX9-NEXT:    s_brev_b32 s6, -2
; GFX9-NEXT:    v_bfi_b32 v10, s6, v10, v2
; GFX9-NEXT:  .LBB12_24: ; %Flow117
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    v_cmp_ngt_f32_e64 s[4:5], |v3|, |v7|
; GFX9-NEXT:    ; implicit-def: $vgpr11
; GFX9-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; GFX9-NEXT:  ; %bb.25: ; %frem.else
; GFX9-NEXT:    v_and_b32_e32 v11, 0x80000000, v3
; GFX9-NEXT:    v_cmp_eq_f32_e64 vcc, |v3|, |v7|
; GFX9-NEXT:    v_cndmask_b32_e32 v11, v3, v11, vcc
; GFX9-NEXT:  ; %bb.26: ; %Flow112
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB12_32
; GFX9-NEXT:  ; %bb.27: ; %frem.compute
; GFX9-NEXT:    v_frexp_mant_f32_e64 v12, |v7|
; GFX9-NEXT:    v_ldexp_f32 v12, v12, 1
; GFX9-NEXT:    v_div_scale_f32 v18, s[6:7], v12, v12, 1.0
; GFX9-NEXT:    v_div_scale_f32 v15, vcc, 1.0, v12, 1.0
; GFX9-NEXT:    v_frexp_mant_f32_e64 v11, |v3|
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v16, v3
; GFX9-NEXT:    v_ldexp_f32 v14, v11, 12
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v17, v7
; GFX9-NEXT:    v_add_u32_e32 v11, -1, v17
; GFX9-NEXT:    v_xad_u32 v13, v11, -1, v16
; GFX9-NEXT:    v_rcp_f32_e32 v19, v18
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT:    v_fma_f32 v20, -v18, v19, 1.0
; GFX9-NEXT:    v_fma_f32 v19, v20, v19, v19
; GFX9-NEXT:    v_mul_f32_e32 v20, v15, v19
; GFX9-NEXT:    v_fma_f32 v21, -v18, v20, v15
; GFX9-NEXT:    v_fma_f32 v20, v21, v19, v20
; GFX9-NEXT:    v_fma_f32 v15, -v18, v20, v15
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX9-NEXT:    v_div_fmas_f32 v15, v15, v19, v20
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v13
; GFX9-NEXT:    v_div_fixup_f32 v15, v15, v12, 1.0
; GFX9-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; GFX9-NEXT:    s_cbranch_execz .LBB12_31
; GFX9-NEXT:  ; %bb.28: ; %frem.loop_body.preheader
; GFX9-NEXT:    v_sub_u32_e32 v13, v16, v17
; GFX9-NEXT:    v_add_u32_e32 v13, 12, v13
; GFX9-NEXT:    s_mov_b64 s[8:9], 0
; GFX9-NEXT:  .LBB12_29: ; %frem.loop_body
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v16, v14
; GFX9-NEXT:    v_mul_f32_e32 v14, v16, v15
; GFX9-NEXT:    v_rndne_f32_e32 v14, v14
; GFX9-NEXT:    v_fma_f32 v14, -v14, v12, v16
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v14
; GFX9-NEXT:    v_add_f32_e32 v17, v14, v12
; GFX9-NEXT:    v_add_u32_e32 v13, -12, v13
; GFX9-NEXT:    v_cndmask_b32_e32 v14, v14, v17, vcc
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v13
; GFX9-NEXT:    v_ldexp_f32 v14, v14, 12
; GFX9-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; GFX9-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; GFX9-NEXT:    s_cbranch_execnz .LBB12_29
; GFX9-NEXT:  ; %bb.30: ; %Flow
; GFX9-NEXT:    s_or_b64 exec, exec, s[8:9]
; GFX9-NEXT:    v_mov_b32_e32 v14, v16
; GFX9-NEXT:  .LBB12_31: ; %Flow111
; GFX9-NEXT:    s_or_b64 exec, exec, s[6:7]
; GFX9-NEXT:    v_add_u32_e32 v13, -11, v13
; GFX9-NEXT:    v_ldexp_f32 v13, v14, v13
; GFX9-NEXT:    v_mul_f32_e32 v14, v13, v15
; GFX9-NEXT:    v_rndne_f32_e32 v14, v14
; GFX9-NEXT:    v_fma_f32 v13, -v14, v12, v13
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v13
; GFX9-NEXT:    v_add_f32_e32 v12, v13, v12
; GFX9-NEXT:    v_cndmask_b32_e32 v12, v13, v12, vcc
; GFX9-NEXT:    v_ldexp_f32 v11, v12, v11
; GFX9-NEXT:    s_brev_b32 s6, -2
; GFX9-NEXT:    v_bfi_b32 v11, s6, v11, v3
; GFX9-NEXT:  .LBB12_32: ; %Flow113
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_mov_b32 s6, 0x7f800000
; GFX9-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v4
; GFX9-NEXT:    v_cmp_nge_f32_e64 s[4:5], |v0|, s6
; GFX9-NEXT:    s_and_b64 vcc, s[4:5], vcc
; GFX9-NEXT:    v_mov_b32_e32 v4, 0x7fc00000
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v4, v8, vcc
; GFX9-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v5
; GFX9-NEXT:    v_cmp_nge_f32_e64 s[4:5], |v1|, s6
; GFX9-NEXT:    s_and_b64 vcc, s[4:5], vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v4, v9, vcc
; GFX9-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v6
; GFX9-NEXT:    v_cmp_nge_f32_e64 s[4:5], |v2|, s6
; GFX9-NEXT:    s_and_b64 vcc, s[4:5], vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v4, v10, vcc
; GFX9-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v7
; GFX9-NEXT:    v_cmp_nge_f32_e64 s[4:5], |v3|, s6
; GFX9-NEXT:    s_and_b64 vcc, s[4:5], vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v4, v11, vcc
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: frem_v4f32:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cmp_ngt_f32_e64 s4, |v0|, |v4|
; GFX10-NEXT:    ; implicit-def: $vgpr8
; GFX10-NEXT:    s_and_saveexec_b32 s5, s4
; GFX10-NEXT:    s_xor_b32 s4, exec_lo, s5
; GFX10-NEXT:  ; %bb.1: ; %frem.else78
; GFX10-NEXT:    v_and_b32_e32 v8, 0x80000000, v0
; GFX10-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v0|, |v4|
; GFX10-NEXT:    v_cndmask_b32_e32 v8, v0, v8, vcc_lo
; GFX10-NEXT:  ; %bb.2: ; %Flow124
; GFX10-NEXT:    s_andn2_saveexec_b32 s4, s4
; GFX10-NEXT:    s_cbranch_execz .LBB12_8
; GFX10-NEXT:  ; %bb.3: ; %frem.compute77
; GFX10-NEXT:    v_frexp_mant_f32_e64 v9, |v4|
; GFX10-NEXT:    v_frexp_mant_f32_e64 v8, |v0|
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v13, v0
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v14, v4
; GFX10-NEXT:    v_ldexp_f32 v9, v9, 1
; GFX10-NEXT:    v_ldexp_f32 v11, v8, 12
; GFX10-NEXT:    v_add_nc_u32_e32 v8, -1, v14
; GFX10-NEXT:    v_div_scale_f32 v15, s5, v9, v9, 1.0
; GFX10-NEXT:    v_div_scale_f32 v12, vcc_lo, 1.0, v9, 1.0
; GFX10-NEXT:    v_xad_u32 v10, v8, -1, v13
; GFX10-NEXT:    v_rcp_f32_e32 v16, v15
; GFX10-NEXT:    s_denorm_mode 15
; GFX10-NEXT:    v_fma_f32 v17, -v15, v16, 1.0
; GFX10-NEXT:    v_fmac_f32_e32 v16, v17, v16
; GFX10-NEXT:    v_mul_f32_e32 v17, v12, v16
; GFX10-NEXT:    v_fma_f32 v18, -v15, v17, v12
; GFX10-NEXT:    v_fmac_f32_e32 v17, v18, v16
; GFX10-NEXT:    v_fma_f32 v12, -v15, v17, v12
; GFX10-NEXT:    s_denorm_mode 12
; GFX10-NEXT:    v_div_fmas_f32 v12, v12, v16, v17
; GFX10-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 12, v10
; GFX10-NEXT:    v_div_fixup_f32 v12, v12, v9, 1.0
; GFX10-NEXT:    s_and_saveexec_b32 s5, vcc_lo
; GFX10-NEXT:    s_cbranch_execz .LBB12_7
; GFX10-NEXT:  ; %bb.4: ; %frem.loop_body85.preheader
; GFX10-NEXT:    v_sub_nc_u32_e32 v10, v13, v14
; GFX10-NEXT:    s_mov_b32 s6, 0
; GFX10-NEXT:    v_add_nc_u32_e32 v10, 12, v10
; GFX10-NEXT:  .LBB12_5: ; %frem.loop_body85
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v13, v11
; GFX10-NEXT:    v_add_nc_u32_e32 v10, -12, v10
; GFX10-NEXT:    v_mul_f32_e32 v11, v13, v12
; GFX10-NEXT:    v_rndne_f32_e32 v11, v11
; GFX10-NEXT:    v_fma_f32 v11, -v11, v9, v13
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v11
; GFX10-NEXT:    v_add_f32_e32 v14, v11, v9
; GFX10-NEXT:    v_cndmask_b32_e32 v11, v11, v14, vcc_lo
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v10
; GFX10-NEXT:    v_ldexp_f32 v11, v11, 12
; GFX10-NEXT:    s_or_b32 s6, vcc_lo, s6
; GFX10-NEXT:    s_andn2_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    s_cbranch_execnz .LBB12_5
; GFX10-NEXT:  ; %bb.6: ; %Flow122
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    v_mov_b32_e32 v11, v13
; GFX10-NEXT:  .LBB12_7: ; %Flow123
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s5
; GFX10-NEXT:    v_add_nc_u32_e32 v10, -11, v10
; GFX10-NEXT:    v_ldexp_f32 v10, v11, v10
; GFX10-NEXT:    v_mul_f32_e32 v11, v10, v12
; GFX10-NEXT:    v_rndne_f32_e32 v11, v11
; GFX10-NEXT:    v_fma_f32 v10, -v11, v9, v10
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v10
; GFX10-NEXT:    v_add_f32_e32 v9, v10, v9
; GFX10-NEXT:    v_cndmask_b32_e32 v9, v10, v9, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v8, v9, v8
; GFX10-NEXT:    v_bfi_b32 v8, 0x7fffffff, v8, v0
; GFX10-NEXT:  .LBB12_8: ; %Flow125
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT:    v_cmp_ngt_f32_e64 s4, |v1|, |v5|
; GFX10-NEXT:    ; implicit-def: $vgpr9
; GFX10-NEXT:    s_and_saveexec_b32 s5, s4
; GFX10-NEXT:    s_xor_b32 s4, exec_lo, s5
; GFX10-NEXT:  ; %bb.9: ; %frem.else47
; GFX10-NEXT:    v_and_b32_e32 v9, 0x80000000, v1
; GFX10-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v1|, |v5|
; GFX10-NEXT:    v_cndmask_b32_e32 v9, v1, v9, vcc_lo
; GFX10-NEXT:  ; %bb.10: ; %Flow120
; GFX10-NEXT:    s_andn2_saveexec_b32 s4, s4
; GFX10-NEXT:    s_cbranch_execz .LBB12_16
; GFX10-NEXT:  ; %bb.11: ; %frem.compute46
; GFX10-NEXT:    v_frexp_mant_f32_e64 v10, |v5|
; GFX10-NEXT:    v_frexp_mant_f32_e64 v9, |v1|
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v14, v1
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v15, v5
; GFX10-NEXT:    v_ldexp_f32 v10, v10, 1
; GFX10-NEXT:    v_ldexp_f32 v12, v9, 12
; GFX10-NEXT:    v_add_nc_u32_e32 v9, -1, v15
; GFX10-NEXT:    v_div_scale_f32 v16, s5, v10, v10, 1.0
; GFX10-NEXT:    v_div_scale_f32 v13, vcc_lo, 1.0, v10, 1.0
; GFX10-NEXT:    v_xad_u32 v11, v9, -1, v14
; GFX10-NEXT:    v_rcp_f32_e32 v17, v16
; GFX10-NEXT:    s_denorm_mode 15
; GFX10-NEXT:    v_fma_f32 v18, -v16, v17, 1.0
; GFX10-NEXT:    v_fmac_f32_e32 v17, v18, v17
; GFX10-NEXT:    v_mul_f32_e32 v18, v13, v17
; GFX10-NEXT:    v_fma_f32 v19, -v16, v18, v13
; GFX10-NEXT:    v_fmac_f32_e32 v18, v19, v17
; GFX10-NEXT:    v_fma_f32 v13, -v16, v18, v13
; GFX10-NEXT:    s_denorm_mode 12
; GFX10-NEXT:    v_div_fmas_f32 v13, v13, v17, v18
; GFX10-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 12, v11
; GFX10-NEXT:    v_div_fixup_f32 v13, v13, v10, 1.0
; GFX10-NEXT:    s_and_saveexec_b32 s5, vcc_lo
; GFX10-NEXT:    s_cbranch_execz .LBB12_15
; GFX10-NEXT:  ; %bb.12: ; %frem.loop_body54.preheader
; GFX10-NEXT:    v_sub_nc_u32_e32 v11, v14, v15
; GFX10-NEXT:    s_mov_b32 s6, 0
; GFX10-NEXT:    v_add_nc_u32_e32 v11, 12, v11
; GFX10-NEXT:  .LBB12_13: ; %frem.loop_body54
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v14, v12
; GFX10-NEXT:    v_add_nc_u32_e32 v11, -12, v11
; GFX10-NEXT:    v_mul_f32_e32 v12, v14, v13
; GFX10-NEXT:    v_rndne_f32_e32 v12, v12
; GFX10-NEXT:    v_fma_f32 v12, -v12, v10, v14
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v12
; GFX10-NEXT:    v_add_f32_e32 v15, v12, v10
; GFX10-NEXT:    v_cndmask_b32_e32 v12, v12, v15, vcc_lo
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v11
; GFX10-NEXT:    v_ldexp_f32 v12, v12, 12
; GFX10-NEXT:    s_or_b32 s6, vcc_lo, s6
; GFX10-NEXT:    s_andn2_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    s_cbranch_execnz .LBB12_13
; GFX10-NEXT:  ; %bb.14: ; %Flow118
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    v_mov_b32_e32 v12, v14
; GFX10-NEXT:  .LBB12_15: ; %Flow119
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s5
; GFX10-NEXT:    v_add_nc_u32_e32 v11, -11, v11
; GFX10-NEXT:    v_ldexp_f32 v11, v12, v11
; GFX10-NEXT:    v_mul_f32_e32 v12, v11, v13
; GFX10-NEXT:    v_rndne_f32_e32 v12, v12
; GFX10-NEXT:    v_fma_f32 v11, -v12, v10, v11
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v11
; GFX10-NEXT:    v_add_f32_e32 v10, v11, v10
; GFX10-NEXT:    v_cndmask_b32_e32 v10, v11, v10, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v9, v10, v9
; GFX10-NEXT:    v_bfi_b32 v9, 0x7fffffff, v9, v1
; GFX10-NEXT:  .LBB12_16: ; %Flow121
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT:    v_cmp_ngt_f32_e64 s4, |v2|, |v6|
; GFX10-NEXT:    ; implicit-def: $vgpr10
; GFX10-NEXT:    s_and_saveexec_b32 s5, s4
; GFX10-NEXT:    s_xor_b32 s4, exec_lo, s5
; GFX10-NEXT:  ; %bb.17: ; %frem.else16
; GFX10-NEXT:    v_and_b32_e32 v10, 0x80000000, v2
; GFX10-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v2|, |v6|
; GFX10-NEXT:    v_cndmask_b32_e32 v10, v2, v10, vcc_lo
; GFX10-NEXT:  ; %bb.18: ; %Flow116
; GFX10-NEXT:    s_andn2_saveexec_b32 s4, s4
; GFX10-NEXT:    s_cbranch_execz .LBB12_24
; GFX10-NEXT:  ; %bb.19: ; %frem.compute15
; GFX10-NEXT:    v_frexp_mant_f32_e64 v11, |v6|
; GFX10-NEXT:    v_frexp_mant_f32_e64 v10, |v2|
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v15, v2
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v16, v6
; GFX10-NEXT:    v_ldexp_f32 v11, v11, 1
; GFX10-NEXT:    v_ldexp_f32 v13, v10, 12
; GFX10-NEXT:    v_add_nc_u32_e32 v10, -1, v16
; GFX10-NEXT:    v_div_scale_f32 v17, s5, v11, v11, 1.0
; GFX10-NEXT:    v_div_scale_f32 v14, vcc_lo, 1.0, v11, 1.0
; GFX10-NEXT:    v_xad_u32 v12, v10, -1, v15
; GFX10-NEXT:    v_rcp_f32_e32 v18, v17
; GFX10-NEXT:    s_denorm_mode 15
; GFX10-NEXT:    v_fma_f32 v19, -v17, v18, 1.0
; GFX10-NEXT:    v_fmac_f32_e32 v18, v19, v18
; GFX10-NEXT:    v_mul_f32_e32 v19, v14, v18
; GFX10-NEXT:    v_fma_f32 v20, -v17, v19, v14
; GFX10-NEXT:    v_fmac_f32_e32 v19, v20, v18
; GFX10-NEXT:    v_fma_f32 v14, -v17, v19, v14
; GFX10-NEXT:    s_denorm_mode 12
; GFX10-NEXT:    v_div_fmas_f32 v14, v14, v18, v19
; GFX10-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 12, v12
; GFX10-NEXT:    v_div_fixup_f32 v14, v14, v11, 1.0
; GFX10-NEXT:    s_and_saveexec_b32 s5, vcc_lo
; GFX10-NEXT:    s_cbranch_execz .LBB12_23
; GFX10-NEXT:  ; %bb.20: ; %frem.loop_body23.preheader
; GFX10-NEXT:    v_sub_nc_u32_e32 v12, v15, v16
; GFX10-NEXT:    s_mov_b32 s6, 0
; GFX10-NEXT:    v_add_nc_u32_e32 v12, 12, v12
; GFX10-NEXT:  .LBB12_21: ; %frem.loop_body23
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v15, v13
; GFX10-NEXT:    v_add_nc_u32_e32 v12, -12, v12
; GFX10-NEXT:    v_mul_f32_e32 v13, v15, v14
; GFX10-NEXT:    v_rndne_f32_e32 v13, v13
; GFX10-NEXT:    v_fma_f32 v13, -v13, v11, v15
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v13
; GFX10-NEXT:    v_add_f32_e32 v16, v13, v11
; GFX10-NEXT:    v_cndmask_b32_e32 v13, v13, v16, vcc_lo
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v12
; GFX10-NEXT:    v_ldexp_f32 v13, v13, 12
; GFX10-NEXT:    s_or_b32 s6, vcc_lo, s6
; GFX10-NEXT:    s_andn2_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    s_cbranch_execnz .LBB12_21
; GFX10-NEXT:  ; %bb.22: ; %Flow114
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    v_mov_b32_e32 v13, v15
; GFX10-NEXT:  .LBB12_23: ; %Flow115
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s5
; GFX10-NEXT:    v_add_nc_u32_e32 v12, -11, v12
; GFX10-NEXT:    v_ldexp_f32 v12, v13, v12
; GFX10-NEXT:    v_mul_f32_e32 v13, v12, v14
; GFX10-NEXT:    v_rndne_f32_e32 v13, v13
; GFX10-NEXT:    v_fma_f32 v12, -v13, v11, v12
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v12
; GFX10-NEXT:    v_add_f32_e32 v11, v12, v11
; GFX10-NEXT:    v_cndmask_b32_e32 v11, v12, v11, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v10, v11, v10
; GFX10-NEXT:    v_bfi_b32 v10, 0x7fffffff, v10, v2
; GFX10-NEXT:  .LBB12_24: ; %Flow117
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT:    v_cmp_ngt_f32_e64 s4, |v3|, |v7|
; GFX10-NEXT:    ; implicit-def: $vgpr11
; GFX10-NEXT:    s_and_saveexec_b32 s5, s4
; GFX10-NEXT:    s_xor_b32 s4, exec_lo, s5
; GFX10-NEXT:  ; %bb.25: ; %frem.else
; GFX10-NEXT:    v_and_b32_e32 v11, 0x80000000, v3
; GFX10-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v3|, |v7|
; GFX10-NEXT:    v_cndmask_b32_e32 v11, v3, v11, vcc_lo
; GFX10-NEXT:  ; %bb.26: ; %Flow112
; GFX10-NEXT:    s_andn2_saveexec_b32 s4, s4
; GFX10-NEXT:    s_cbranch_execz .LBB12_32
; GFX10-NEXT:  ; %bb.27: ; %frem.compute
; GFX10-NEXT:    v_frexp_mant_f32_e64 v12, |v7|
; GFX10-NEXT:    v_frexp_mant_f32_e64 v11, |v3|
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v16, v3
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v17, v7
; GFX10-NEXT:    v_ldexp_f32 v12, v12, 1
; GFX10-NEXT:    v_ldexp_f32 v14, v11, 12
; GFX10-NEXT:    v_add_nc_u32_e32 v11, -1, v17
; GFX10-NEXT:    v_div_scale_f32 v18, s5, v12, v12, 1.0
; GFX10-NEXT:    v_div_scale_f32 v15, vcc_lo, 1.0, v12, 1.0
; GFX10-NEXT:    v_xad_u32 v13, v11, -1, v16
; GFX10-NEXT:    v_rcp_f32_e32 v19, v18
; GFX10-NEXT:    s_denorm_mode 15
; GFX10-NEXT:    v_fma_f32 v20, -v18, v19, 1.0
; GFX10-NEXT:    v_fmac_f32_e32 v19, v20, v19
; GFX10-NEXT:    v_mul_f32_e32 v20, v15, v19
; GFX10-NEXT:    v_fma_f32 v21, -v18, v20, v15
; GFX10-NEXT:    v_fmac_f32_e32 v20, v21, v19
; GFX10-NEXT:    v_fma_f32 v15, -v18, v20, v15
; GFX10-NEXT:    s_denorm_mode 12
; GFX10-NEXT:    v_div_fmas_f32 v15, v15, v19, v20
; GFX10-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 12, v13
; GFX10-NEXT:    v_div_fixup_f32 v15, v15, v12, 1.0
; GFX10-NEXT:    s_and_saveexec_b32 s5, vcc_lo
; GFX10-NEXT:    s_cbranch_execz .LBB12_31
; GFX10-NEXT:  ; %bb.28: ; %frem.loop_body.preheader
; GFX10-NEXT:    v_sub_nc_u32_e32 v13, v16, v17
; GFX10-NEXT:    s_mov_b32 s6, 0
; GFX10-NEXT:    v_add_nc_u32_e32 v13, 12, v13
; GFX10-NEXT:  .LBB12_29: ; %frem.loop_body
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v16, v14
; GFX10-NEXT:    v_add_nc_u32_e32 v13, -12, v13
; GFX10-NEXT:    v_mul_f32_e32 v14, v16, v15
; GFX10-NEXT:    v_rndne_f32_e32 v14, v14
; GFX10-NEXT:    v_fma_f32 v14, -v14, v12, v16
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v14
; GFX10-NEXT:    v_add_f32_e32 v17, v14, v12
; GFX10-NEXT:    v_cndmask_b32_e32 v14, v14, v17, vcc_lo
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v13
; GFX10-NEXT:    v_ldexp_f32 v14, v14, 12
; GFX10-NEXT:    s_or_b32 s6, vcc_lo, s6
; GFX10-NEXT:    s_andn2_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    s_cbranch_execnz .LBB12_29
; GFX10-NEXT:  ; %bb.30: ; %Flow
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    v_mov_b32_e32 v14, v16
; GFX10-NEXT:  .LBB12_31: ; %Flow111
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s5
; GFX10-NEXT:    v_add_nc_u32_e32 v13, -11, v13
; GFX10-NEXT:    v_ldexp_f32 v13, v14, v13
; GFX10-NEXT:    v_mul_f32_e32 v14, v13, v15
; GFX10-NEXT:    v_rndne_f32_e32 v14, v14
; GFX10-NEXT:    v_fma_f32 v13, -v14, v12, v13
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v13
; GFX10-NEXT:    v_add_f32_e32 v12, v13, v12
; GFX10-NEXT:    v_cndmask_b32_e32 v12, v13, v12, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v11, v12, v11
; GFX10-NEXT:    v_bfi_b32 v11, 0x7fffffff, v11, v3
; GFX10-NEXT:  .LBB12_32: ; %Flow113
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v4
; GFX10-NEXT:    v_cmp_nge_f32_e64 s4, |v0|, 0x7f800000
; GFX10-NEXT:    s_and_b32 vcc_lo, s4, vcc_lo
; GFX10-NEXT:    v_cmp_nge_f32_e64 s4, |v1|, 0x7f800000
; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v8, vcc_lo
; GFX10-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v5
; GFX10-NEXT:    s_and_b32 vcc_lo, s4, vcc_lo
; GFX10-NEXT:    v_cmp_nge_f32_e64 s4, |v2|, 0x7f800000
; GFX10-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v9, vcc_lo
; GFX10-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v6
; GFX10-NEXT:    s_and_b32 vcc_lo, s4, vcc_lo
; GFX10-NEXT:    v_cmp_nge_f32_e64 s4, |v3|, 0x7f800000
; GFX10-NEXT:    v_cndmask_b32_e32 v2, 0x7fc00000, v10, vcc_lo
; GFX10-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v7
; GFX10-NEXT:    s_and_b32 vcc_lo, s4, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v3, 0x7fc00000, v11, vcc_lo
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: frem_v4f32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cmp_ngt_f32_e64 s0, |v0|, |v4|
; GFX11-NEXT:    ; implicit-def: $vgpr8
; GFX11-NEXT:    s_and_saveexec_b32 s1, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX11-NEXT:  ; %bb.1: ; %frem.else78
; GFX11-NEXT:    v_and_b32_e32 v8, 0x80000000, v0
; GFX11-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v0|, |v4|
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT:    v_cndmask_b32_e32 v8, v0, v8, vcc_lo
; GFX11-NEXT:  ; %bb.2: ; %Flow124
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB12_8
; GFX11-NEXT:  ; %bb.3: ; %frem.compute77
; GFX11-NEXT:    v_frexp_mant_f32_e64 v9, |v4|
; GFX11-NEXT:    v_frexp_mant_f32_e64 v8, |v0|
; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v13, v0
; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v14, v4
; GFX11-NEXT:    s_mov_b32 s1, exec_lo
; GFX11-NEXT:    v_ldexp_f32 v9, v9, 1
; GFX11-NEXT:    v_ldexp_f32 v11, v8, 12
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_add_nc_u32_e32 v8, -1, v14
; GFX11-NEXT:    v_div_scale_f32 v15, null, v9, v9, 1.0
; GFX11-NEXT:    v_div_scale_f32 v12, vcc_lo, 1.0, v9, 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_xad_u32 v10, v8, -1, v13
; GFX11-NEXT:    v_rcp_f32_e32 v16, v15
; GFX11-NEXT:    s_denorm_mode 15
; GFX11-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT:    v_fma_f32 v17, -v15, v16, 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fmac_f32_e32 v16, v17, v16
; GFX11-NEXT:    v_mul_f32_e32 v17, v12, v16
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v18, -v15, v17, v12
; GFX11-NEXT:    v_fmac_f32_e32 v17, v18, v16
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v12, -v15, v17, v12
; GFX11-NEXT:    s_denorm_mode 12
; GFX11-NEXT:    v_div_fmas_f32 v12, v12, v16, v17
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_div_fixup_f32 v12, v12, v9, 1.0
; GFX11-NEXT:    v_cmpx_lt_i32_e32 12, v10
; GFX11-NEXT:    s_cbranch_execz .LBB12_7
; GFX11-NEXT:  ; %bb.4: ; %frem.loop_body85.preheader
; GFX11-NEXT:    v_sub_nc_u32_e32 v10, v13, v14
; GFX11-NEXT:    s_mov_b32 s2, 0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_add_nc_u32_e32 v10, 12, v10
; GFX11-NEXT:  .LBB12_5: ; %frem.loop_body85
; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_dual_mov_b32 v13, v11 :: v_dual_add_nc_u32 v10, -12, v10
; GFX11-NEXT:    v_mul_f32_e32 v11, v13, v12
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_rndne_f32_e32 v11, v11
; GFX11-NEXT:    v_fma_f32 v11, -v11, v9, v13
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v11
; GFX11-NEXT:    v_add_f32_e32 v14, v11, v9
; GFX11-NEXT:    v_cndmask_b32_e32 v11, v11, v14, vcc_lo
; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v10
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT:    v_ldexp_f32 v11, v11, 12
; GFX11-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX11-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX11-NEXT:    s_cbranch_execnz .LBB12_5
; GFX11-NEXT:  ; %bb.6: ; %Flow122
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX11-NEXT:    v_mov_b32_e32 v11, v13
; GFX11-NEXT:  .LBB12_7: ; %Flow123
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX11-NEXT:    v_add_nc_u32_e32 v10, -11, v10
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_ldexp_f32 v10, v11, v10
; GFX11-NEXT:    v_mul_f32_e32 v11, v10, v12
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_rndne_f32_e32 v11, v11
; GFX11-NEXT:    v_fma_f32 v10, -v11, v9, v10
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v10
; GFX11-NEXT:    v_add_f32_e32 v9, v10, v9
; GFX11-NEXT:    v_cndmask_b32_e32 v9, v10, v9, vcc_lo
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_ldexp_f32 v8, v9, v8
; GFX11-NEXT:    v_bfi_b32 v8, 0x7fffffff, v8, v0
; GFX11-NEXT:  .LBB12_8: ; %Flow125
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    v_cmp_ngt_f32_e64 s0, |v1|, |v5|
; GFX11-NEXT:    ; implicit-def: $vgpr9
; GFX11-NEXT:    s_and_saveexec_b32 s1, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX11-NEXT:  ; %bb.9: ; %frem.else47
; GFX11-NEXT:    v_and_b32_e32 v9, 0x80000000, v1
; GFX11-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v1|, |v5|
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT:    v_cndmask_b32_e32 v9, v1, v9, vcc_lo
; GFX11-NEXT:  ; %bb.10: ; %Flow120
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB12_16
; GFX11-NEXT:  ; %bb.11: ; %frem.compute46
; GFX11-NEXT:    v_frexp_mant_f32_e64 v10, |v5|
; GFX11-NEXT:    v_frexp_mant_f32_e64 v9, |v1|
; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v14, v1
; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v15, v5
; GFX11-NEXT:    s_mov_b32 s1, exec_lo
; GFX11-NEXT:    v_ldexp_f32 v10, v10, 1
; GFX11-NEXT:    v_ldexp_f32 v12, v9, 12
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_add_nc_u32_e32 v9, -1, v15
; GFX11-NEXT:    v_div_scale_f32 v16, null, v10, v10, 1.0
; GFX11-NEXT:    v_div_scale_f32 v13, vcc_lo, 1.0, v10, 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_xad_u32 v11, v9, -1, v14
; GFX11-NEXT:    v_rcp_f32_e32 v17, v16
; GFX11-NEXT:    s_denorm_mode 15
; GFX11-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT:    v_fma_f32 v18, -v16, v17, 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fmac_f32_e32 v17, v18, v17
; GFX11-NEXT:    v_mul_f32_e32 v18, v13, v17
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v19, -v16, v18, v13
; GFX11-NEXT:    v_fmac_f32_e32 v18, v19, v17
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v13, -v16, v18, v13
; GFX11-NEXT:    s_denorm_mode 12
; GFX11-NEXT:    v_div_fmas_f32 v13, v13, v17, v18
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_div_fixup_f32 v13, v13, v10, 1.0
; GFX11-NEXT:    v_cmpx_lt_i32_e32 12, v11
; GFX11-NEXT:    s_cbranch_execz .LBB12_15
; GFX11-NEXT:  ; %bb.12: ; %frem.loop_body54.preheader
; GFX11-NEXT:    v_sub_nc_u32_e32 v11, v14, v15
; GFX11-NEXT:    s_mov_b32 s2, 0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_add_nc_u32_e32 v11, 12, v11
; GFX11-NEXT:  .LBB12_13: ; %frem.loop_body54
; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_dual_mov_b32 v14, v12 :: v_dual_add_nc_u32 v11, -12, v11
; GFX11-NEXT:    v_mul_f32_e32 v12, v14, v13
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_rndne_f32_e32 v12, v12
; GFX11-NEXT:    v_fma_f32 v12, -v12, v10, v14
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v12
; GFX11-NEXT:    v_add_f32_e32 v15, v12, v10
; GFX11-NEXT:    v_cndmask_b32_e32 v12, v12, v15, vcc_lo
; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v11
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT:    v_ldexp_f32 v12, v12, 12
; GFX11-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX11-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX11-NEXT:    s_cbranch_execnz .LBB12_13
; GFX11-NEXT:  ; %bb.14: ; %Flow118
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX11-NEXT:    v_mov_b32_e32 v12, v14
; GFX11-NEXT:  .LBB12_15: ; %Flow119
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX11-NEXT:    v_add_nc_u32_e32 v11, -11, v11
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_ldexp_f32 v11, v12, v11
; GFX11-NEXT:    v_mul_f32_e32 v12, v11, v13
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_rndne_f32_e32 v12, v12
; GFX11-NEXT:    v_fma_f32 v11, -v12, v10, v11
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v11
; GFX11-NEXT:    v_add_f32_e32 v10, v11, v10
; GFX11-NEXT:    v_cndmask_b32_e32 v10, v11, v10, vcc_lo
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_ldexp_f32 v9, v10, v9
; GFX11-NEXT:    v_bfi_b32 v9, 0x7fffffff, v9, v1
; GFX11-NEXT:  .LBB12_16: ; %Flow121
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    v_cmp_ngt_f32_e64 s0, |v2|, |v6|
; GFX11-NEXT:    ; implicit-def: $vgpr10
; GFX11-NEXT:    s_and_saveexec_b32 s1, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX11-NEXT:  ; %bb.17: ; %frem.else16
; GFX11-NEXT:    v_and_b32_e32 v10, 0x80000000, v2
; GFX11-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v2|, |v6|
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT:    v_cndmask_b32_e32 v10, v2, v10, vcc_lo
; GFX11-NEXT:  ; %bb.18: ; %Flow116
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB12_24
; GFX11-NEXT:  ; %bb.19: ; %frem.compute15
; GFX11-NEXT:    v_frexp_mant_f32_e64 v11, |v6|
; GFX11-NEXT:    v_frexp_mant_f32_e64 v10, |v2|
; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v15, v2
; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v16, v6
; GFX11-NEXT:    s_mov_b32 s1, exec_lo
; GFX11-NEXT:    v_ldexp_f32 v11, v11, 1
; GFX11-NEXT:    v_ldexp_f32 v13, v10, 12
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_add_nc_u32_e32 v10, -1, v16
; GFX11-NEXT:    v_div_scale_f32 v17, null, v11, v11, 1.0
; GFX11-NEXT:    v_div_scale_f32 v14, vcc_lo, 1.0, v11, 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_xad_u32 v12, v10, -1, v15
; GFX11-NEXT:    v_rcp_f32_e32 v18, v17
; GFX11-NEXT:    s_denorm_mode 15
; GFX11-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT:    v_fma_f32 v19, -v17, v18, 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fmac_f32_e32 v18, v19, v18
; GFX11-NEXT:    v_mul_f32_e32 v19, v14, v18
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v20, -v17, v19, v14
; GFX11-NEXT:    v_fmac_f32_e32 v19, v20, v18
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v14, -v17, v19, v14
; GFX11-NEXT:    s_denorm_mode 12
; GFX11-NEXT:    v_div_fmas_f32 v14, v14, v18, v19
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_div_fixup_f32 v14, v14, v11, 1.0
; GFX11-NEXT:    v_cmpx_lt_i32_e32 12, v12
; GFX11-NEXT:    s_cbranch_execz .LBB12_23
; GFX11-NEXT:  ; %bb.20: ; %frem.loop_body23.preheader
; GFX11-NEXT:    v_sub_nc_u32_e32 v12, v15, v16
; GFX11-NEXT:    s_mov_b32 s2, 0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_add_nc_u32_e32 v12, 12, v12
; GFX11-NEXT:  .LBB12_21: ; %frem.loop_body23
; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_dual_mov_b32 v15, v13 :: v_dual_add_nc_u32 v12, -12, v12
; GFX11-NEXT:    v_mul_f32_e32 v13, v15, v14
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_rndne_f32_e32 v13, v13
; GFX11-NEXT:    v_fma_f32 v13, -v13, v11, v15
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v13
; GFX11-NEXT:    v_add_f32_e32 v16, v13, v11
; GFX11-NEXT:    v_cndmask_b32_e32 v13, v13, v16, vcc_lo
; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v12
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT:    v_ldexp_f32 v13, v13, 12
; GFX11-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX11-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX11-NEXT:    s_cbranch_execnz .LBB12_21
; GFX11-NEXT:  ; %bb.22: ; %Flow114
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX11-NEXT:    v_mov_b32_e32 v13, v15
; GFX11-NEXT:  .LBB12_23: ; %Flow115
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX11-NEXT:    v_add_nc_u32_e32 v12, -11, v12
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_ldexp_f32 v12, v13, v12
; GFX11-NEXT:    v_mul_f32_e32 v13, v12, v14
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_rndne_f32_e32 v13, v13
; GFX11-NEXT:    v_fma_f32 v12, -v13, v11, v12
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v12
; GFX11-NEXT:    v_add_f32_e32 v11, v12, v11
; GFX11-NEXT:    v_cndmask_b32_e32 v11, v12, v11, vcc_lo
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_ldexp_f32 v10, v11, v10
; GFX11-NEXT:    v_bfi_b32 v10, 0x7fffffff, v10, v2
; GFX11-NEXT:  .LBB12_24: ; %Flow117
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    v_cmp_ngt_f32_e64 s0, |v3|, |v7|
; GFX11-NEXT:    ; implicit-def: $vgpr11
; GFX11-NEXT:    s_and_saveexec_b32 s1, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX11-NEXT:  ; %bb.25: ; %frem.else
; GFX11-NEXT:    v_and_b32_e32 v11, 0x80000000, v3
; GFX11-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v3|, |v7|
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT:    v_cndmask_b32_e32 v11, v3, v11, vcc_lo
; GFX11-NEXT:  ; %bb.26: ; %Flow112
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB12_32
; GFX11-NEXT:  ; %bb.27: ; %frem.compute
; GFX11-NEXT:    v_frexp_mant_f32_e64 v12, |v7|
; GFX11-NEXT:    v_frexp_mant_f32_e64 v11, |v3|
; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v16, v3
; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v17, v7
; GFX11-NEXT:    s_mov_b32 s1, exec_lo
; GFX11-NEXT:    v_ldexp_f32 v12, v12, 1
; GFX11-NEXT:    v_ldexp_f32 v14, v11, 12
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_add_nc_u32_e32 v11, -1, v17
; GFX11-NEXT:    v_div_scale_f32 v18, null, v12, v12, 1.0
; GFX11-NEXT:    v_div_scale_f32 v15, vcc_lo, 1.0, v12, 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_xad_u32 v13, v11, -1, v16
; GFX11-NEXT:    v_rcp_f32_e32 v19, v18
; GFX11-NEXT:    s_denorm_mode 15
; GFX11-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT:    v_fma_f32 v20, -v18, v19, 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fmac_f32_e32 v19, v20, v19
; GFX11-NEXT:    v_mul_f32_e32 v20, v15, v19
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v21, -v18, v20, v15
; GFX11-NEXT:    v_fmac_f32_e32 v20, v21, v19
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v15, -v18, v20, v15
; GFX11-NEXT:    s_denorm_mode 12
; GFX11-NEXT:    v_div_fmas_f32 v15, v15, v19, v20
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_div_fixup_f32 v15, v15, v12, 1.0
; GFX11-NEXT:    v_cmpx_lt_i32_e32 12, v13
; GFX11-NEXT:    s_cbranch_execz .LBB12_31
; GFX11-NEXT:  ; %bb.28: ; %frem.loop_body.preheader
; GFX11-NEXT:    v_sub_nc_u32_e32 v13, v16, v17
; GFX11-NEXT:    s_mov_b32 s2, 0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_add_nc_u32_e32 v13, 12, v13
; GFX11-NEXT:  .LBB12_29: ; %frem.loop_body
; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_dual_mov_b32 v16, v14 :: v_dual_add_nc_u32 v13, -12, v13
; GFX11-NEXT:    v_mul_f32_e32 v14, v16, v15
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_rndne_f32_e32 v14, v14
; GFX11-NEXT:    v_fma_f32 v14, -v14, v12, v16
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v14
; GFX11-NEXT:    v_add_f32_e32 v17, v14, v12
; GFX11-NEXT:    v_cndmask_b32_e32 v14, v14, v17, vcc_lo
; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v13
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT:    v_ldexp_f32 v14, v14, 12
; GFX11-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX11-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX11-NEXT:    s_cbranch_execnz .LBB12_29
; GFX11-NEXT:  ; %bb.30: ; %Flow
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX11-NEXT:    v_mov_b32_e32 v14, v16
; GFX11-NEXT:  .LBB12_31: ; %Flow111
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX11-NEXT:    v_add_nc_u32_e32 v13, -11, v13
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_ldexp_f32 v13, v14, v13
; GFX11-NEXT:    v_mul_f32_e32 v14, v13, v15
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_rndne_f32_e32 v14, v14
; GFX11-NEXT:    v_fma_f32 v13, -v14, v12, v13
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v13
; GFX11-NEXT:    v_add_f32_e32 v12, v13, v12
; GFX11-NEXT:    v_cndmask_b32_e32 v12, v13, v12, vcc_lo
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_ldexp_f32 v11, v12, v11
; GFX11-NEXT:    v_bfi_b32 v11, 0x7fffffff, v11, v3
; GFX11-NEXT:  .LBB12_32: ; %Flow113
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v4
; GFX11-NEXT:    v_cmp_nge_f32_e64 s0, |v0|, 0x7f800000
; GFX11-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX11-NEXT:    v_cmp_nge_f32_e64 s0, |v1|, 0x7f800000
; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v8, vcc_lo
; GFX11-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v5
; GFX11-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX11-NEXT:    v_cmp_nge_f32_e64 s0, |v2|, 0x7f800000
; GFX11-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v9, vcc_lo
; GFX11-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v6
; GFX11-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX11-NEXT:    v_cmp_nge_f32_e64 s0, |v3|, 0x7f800000
; GFX11-NEXT:    v_cndmask_b32_e32 v2, 0x7fc00000, v10, vcc_lo
; GFX11-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v7
; GFX11-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX11-NEXT:    v_cndmask_b32_e32 v3, 0x7fc00000, v11, vcc_lo
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-LABEL: frem_v4f32:
; GFX1150:       ; %bb.0:
; GFX1150-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-NEXT:    v_cmp_ngt_f32_e64 s0, |v0|, |v4|
; GFX1150-NEXT:    ; implicit-def: $vgpr8
; GFX1150-NEXT:    s_and_saveexec_b32 s1, s0
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX1150-NEXT:  ; %bb.1: ; %frem.else78
; GFX1150-NEXT:    v_and_b32_e32 v8, 0x80000000, v0
; GFX1150-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v0|, |v4|
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1150-NEXT:    v_cndmask_b32_e32 v8, v0, v8, vcc_lo
; GFX1150-NEXT:  ; %bb.2: ; %Flow124
; GFX1150-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1150-NEXT:    s_cbranch_execz .LBB12_8
; GFX1150-NEXT:  ; %bb.3: ; %frem.compute77
; GFX1150-NEXT:    v_frexp_mant_f32_e64 v9, |v4|
; GFX1150-NEXT:    v_frexp_mant_f32_e64 v8, |v0|
; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v13, v0
; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v14, v4
; GFX1150-NEXT:    s_mov_b32 s1, exec_lo
; GFX1150-NEXT:    v_ldexp_f32 v9, v9, 1
; GFX1150-NEXT:    v_ldexp_f32 v11, v8, 12
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_add_nc_u32_e32 v8, -1, v14
; GFX1150-NEXT:    v_div_scale_f32 v15, null, v9, v9, 1.0
; GFX1150-NEXT:    v_div_scale_f32 v12, vcc_lo, 1.0, v9, 1.0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_xad_u32 v10, v8, -1, v13
; GFX1150-NEXT:    v_rcp_f32_e32 v16, v15
; GFX1150-NEXT:    s_denorm_mode 15
; GFX1150-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f32 v17, -v15, v16, 1.0
; GFX1150-NEXT:    v_fmac_f32_e32 v16, v17, v16
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f32_e32 v17, v12, v16
; GFX1150-NEXT:    v_fma_f32 v18, -v15, v17, v12
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fmac_f32_e32 v17, v18, v16
; GFX1150-NEXT:    v_fma_f32 v12, -v15, v17, v12
; GFX1150-NEXT:    s_denorm_mode 12
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_div_fmas_f32 v12, v12, v16, v17
; GFX1150-NEXT:    v_div_fixup_f32 v12, v12, v9, 1.0
; GFX1150-NEXT:    v_cmpx_lt_i32_e32 12, v10
; GFX1150-NEXT:    s_cbranch_execz .LBB12_7
; GFX1150-NEXT:  ; %bb.4: ; %frem.loop_body85.preheader
; GFX1150-NEXT:    v_sub_nc_u32_e32 v10, v13, v14
; GFX1150-NEXT:    s_mov_b32 s2, 0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_add_nc_u32_e32 v10, 12, v10
; GFX1150-NEXT:  .LBB12_5: ; %frem.loop_body85
; GFX1150-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_dual_mov_b32 v13, v11 :: v_dual_add_nc_u32 v10, -12, v10
; GFX1150-NEXT:    v_mul_f32_e32 v11, v13, v12
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_rndne_f32_e32 v11, v11
; GFX1150-NEXT:    v_fma_f32 v11, -v11, v9, v13
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v11
; GFX1150-NEXT:    v_add_f32_e32 v14, v11, v9
; GFX1150-NEXT:    v_cndmask_b32_e32 v11, v11, v14, vcc_lo
; GFX1150-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v10
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT:    v_ldexp_f32 v11, v11, 12
; GFX1150-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1150-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1150-NEXT:    s_cbranch_execnz .LBB12_5
; GFX1150-NEXT:  ; %bb.6: ; %Flow122
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1150-NEXT:    v_mov_b32_e32 v11, v13
; GFX1150-NEXT:  .LBB12_7: ; %Flow123
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1150-NEXT:    v_add_nc_u32_e32 v10, -11, v10
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f32 v10, v11, v10
; GFX1150-NEXT:    v_mul_f32_e32 v11, v10, v12
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_rndne_f32_e32 v11, v11
; GFX1150-NEXT:    v_fma_f32 v10, -v11, v9, v10
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v10
; GFX1150-NEXT:    v_add_f32_e32 v9, v10, v9
; GFX1150-NEXT:    v_cndmask_b32_e32 v9, v10, v9, vcc_lo
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f32 v8, v9, v8
; GFX1150-NEXT:    v_bfi_b32 v8, 0x7fffffff, v8, v0
; GFX1150-NEXT:  .LBB12_8: ; %Flow125
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1150-NEXT:    v_cmp_ngt_f32_e64 s0, |v1|, |v5|
; GFX1150-NEXT:    ; implicit-def: $vgpr9
; GFX1150-NEXT:    s_and_saveexec_b32 s1, s0
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX1150-NEXT:  ; %bb.9: ; %frem.else47
; GFX1150-NEXT:    v_and_b32_e32 v9, 0x80000000, v1
; GFX1150-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v1|, |v5|
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1150-NEXT:    v_cndmask_b32_e32 v9, v1, v9, vcc_lo
; GFX1150-NEXT:  ; %bb.10: ; %Flow120
; GFX1150-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1150-NEXT:    s_cbranch_execz .LBB12_16
; GFX1150-NEXT:  ; %bb.11: ; %frem.compute46
; GFX1150-NEXT:    v_frexp_mant_f32_e64 v10, |v5|
; GFX1150-NEXT:    v_frexp_mant_f32_e64 v9, |v1|
; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v14, v1
; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v15, v5
; GFX1150-NEXT:    s_mov_b32 s1, exec_lo
; GFX1150-NEXT:    v_ldexp_f32 v10, v10, 1
; GFX1150-NEXT:    v_ldexp_f32 v12, v9, 12
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_add_nc_u32_e32 v9, -1, v15
; GFX1150-NEXT:    v_div_scale_f32 v16, null, v10, v10, 1.0
; GFX1150-NEXT:    v_div_scale_f32 v13, vcc_lo, 1.0, v10, 1.0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_xad_u32 v11, v9, -1, v14
; GFX1150-NEXT:    v_rcp_f32_e32 v17, v16
; GFX1150-NEXT:    s_denorm_mode 15
; GFX1150-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f32 v18, -v16, v17, 1.0
; GFX1150-NEXT:    v_fmac_f32_e32 v17, v18, v17
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f32_e32 v18, v13, v17
; GFX1150-NEXT:    v_fma_f32 v19, -v16, v18, v13
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fmac_f32_e32 v18, v19, v17
; GFX1150-NEXT:    v_fma_f32 v13, -v16, v18, v13
; GFX1150-NEXT:    s_denorm_mode 12
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_div_fmas_f32 v13, v13, v17, v18
; GFX1150-NEXT:    v_div_fixup_f32 v13, v13, v10, 1.0
; GFX1150-NEXT:    v_cmpx_lt_i32_e32 12, v11
; GFX1150-NEXT:    s_cbranch_execz .LBB12_15
; GFX1150-NEXT:  ; %bb.12: ; %frem.loop_body54.preheader
; GFX1150-NEXT:    v_sub_nc_u32_e32 v11, v14, v15
; GFX1150-NEXT:    s_mov_b32 s2, 0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_add_nc_u32_e32 v11, 12, v11
; GFX1150-NEXT:  .LBB12_13: ; %frem.loop_body54
; GFX1150-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_dual_mov_b32 v14, v12 :: v_dual_add_nc_u32 v11, -12, v11
; GFX1150-NEXT:    v_mul_f32_e32 v12, v14, v13
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_rndne_f32_e32 v12, v12
; GFX1150-NEXT:    v_fma_f32 v12, -v12, v10, v14
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v12
; GFX1150-NEXT:    v_add_f32_e32 v15, v12, v10
; GFX1150-NEXT:    v_cndmask_b32_e32 v12, v12, v15, vcc_lo
; GFX1150-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v11
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT:    v_ldexp_f32 v12, v12, 12
; GFX1150-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1150-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1150-NEXT:    s_cbranch_execnz .LBB12_13
; GFX1150-NEXT:  ; %bb.14: ; %Flow118
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1150-NEXT:    v_mov_b32_e32 v12, v14
; GFX1150-NEXT:  .LBB12_15: ; %Flow119
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1150-NEXT:    v_add_nc_u32_e32 v11, -11, v11
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f32 v11, v12, v11
; GFX1150-NEXT:    v_mul_f32_e32 v12, v11, v13
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_rndne_f32_e32 v12, v12
; GFX1150-NEXT:    v_fma_f32 v11, -v12, v10, v11
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v11
; GFX1150-NEXT:    v_add_f32_e32 v10, v11, v10
; GFX1150-NEXT:    v_cndmask_b32_e32 v10, v11, v10, vcc_lo
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f32 v9, v10, v9
; GFX1150-NEXT:    v_bfi_b32 v9, 0x7fffffff, v9, v1
; GFX1150-NEXT:  .LBB12_16: ; %Flow121
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1150-NEXT:    v_cmp_ngt_f32_e64 s0, |v2|, |v6|
; GFX1150-NEXT:    ; implicit-def: $vgpr10
; GFX1150-NEXT:    s_and_saveexec_b32 s1, s0
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX1150-NEXT:  ; %bb.17: ; %frem.else16
; GFX1150-NEXT:    v_and_b32_e32 v10, 0x80000000, v2
; GFX1150-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v2|, |v6|
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1150-NEXT:    v_cndmask_b32_e32 v10, v2, v10, vcc_lo
; GFX1150-NEXT:  ; %bb.18: ; %Flow116
; GFX1150-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1150-NEXT:    s_cbranch_execz .LBB12_24
; GFX1150-NEXT:  ; %bb.19: ; %frem.compute15
; GFX1150-NEXT:    v_frexp_mant_f32_e64 v11, |v6|
; GFX1150-NEXT:    v_frexp_mant_f32_e64 v10, |v2|
; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v15, v2
; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v16, v6
; GFX1150-NEXT:    s_mov_b32 s1, exec_lo
; GFX1150-NEXT:    v_ldexp_f32 v11, v11, 1
; GFX1150-NEXT:    v_ldexp_f32 v13, v10, 12
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_add_nc_u32_e32 v10, -1, v16
; GFX1150-NEXT:    v_div_scale_f32 v17, null, v11, v11, 1.0
; GFX1150-NEXT:    v_div_scale_f32 v14, vcc_lo, 1.0, v11, 1.0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_xad_u32 v12, v10, -1, v15
; GFX1150-NEXT:    v_rcp_f32_e32 v18, v17
; GFX1150-NEXT:    s_denorm_mode 15
; GFX1150-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f32 v19, -v17, v18, 1.0
; GFX1150-NEXT:    v_fmac_f32_e32 v18, v19, v18
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f32_e32 v19, v14, v18
; GFX1150-NEXT:    v_fma_f32 v20, -v17, v19, v14
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fmac_f32_e32 v19, v20, v18
; GFX1150-NEXT:    v_fma_f32 v14, -v17, v19, v14
; GFX1150-NEXT:    s_denorm_mode 12
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_div_fmas_f32 v14, v14, v18, v19
; GFX1150-NEXT:    v_div_fixup_f32 v14, v14, v11, 1.0
; GFX1150-NEXT:    v_cmpx_lt_i32_e32 12, v12
; GFX1150-NEXT:    s_cbranch_execz .LBB12_23
; GFX1150-NEXT:  ; %bb.20: ; %frem.loop_body23.preheader
; GFX1150-NEXT:    v_sub_nc_u32_e32 v12, v15, v16
; GFX1150-NEXT:    s_mov_b32 s2, 0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_add_nc_u32_e32 v12, 12, v12
; GFX1150-NEXT:  .LBB12_21: ; %frem.loop_body23
; GFX1150-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_dual_mov_b32 v15, v13 :: v_dual_add_nc_u32 v12, -12, v12
; GFX1150-NEXT:    v_mul_f32_e32 v13, v15, v14
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_rndne_f32_e32 v13, v13
; GFX1150-NEXT:    v_fma_f32 v13, -v13, v11, v15
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v13
; GFX1150-NEXT:    v_add_f32_e32 v16, v13, v11
; GFX1150-NEXT:    v_cndmask_b32_e32 v13, v13, v16, vcc_lo
; GFX1150-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v12
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT:    v_ldexp_f32 v13, v13, 12
; GFX1150-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1150-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1150-NEXT:    s_cbranch_execnz .LBB12_21
; GFX1150-NEXT:  ; %bb.22: ; %Flow114
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1150-NEXT:    v_mov_b32_e32 v13, v15
; GFX1150-NEXT:  .LBB12_23: ; %Flow115
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1150-NEXT:    v_add_nc_u32_e32 v12, -11, v12
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f32 v12, v13, v12
; GFX1150-NEXT:    v_mul_f32_e32 v13, v12, v14
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_rndne_f32_e32 v13, v13
; GFX1150-NEXT:    v_fma_f32 v12, -v13, v11, v12
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v12
; GFX1150-NEXT:    v_add_f32_e32 v11, v12, v11
; GFX1150-NEXT:    v_cndmask_b32_e32 v11, v12, v11, vcc_lo
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f32 v10, v11, v10
; GFX1150-NEXT:    v_bfi_b32 v10, 0x7fffffff, v10, v2
; GFX1150-NEXT:  .LBB12_24: ; %Flow117
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1150-NEXT:    v_cmp_ngt_f32_e64 s0, |v3|, |v7|
; GFX1150-NEXT:    ; implicit-def: $vgpr11
; GFX1150-NEXT:    s_and_saveexec_b32 s1, s0
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX1150-NEXT:  ; %bb.25: ; %frem.else
; GFX1150-NEXT:    v_and_b32_e32 v11, 0x80000000, v3
; GFX1150-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v3|, |v7|
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1150-NEXT:    v_cndmask_b32_e32 v11, v3, v11, vcc_lo
; GFX1150-NEXT:  ; %bb.26: ; %Flow112
; GFX1150-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1150-NEXT:    s_cbranch_execz .LBB12_32
; GFX1150-NEXT:  ; %bb.27: ; %frem.compute
; GFX1150-NEXT:    v_frexp_mant_f32_e64 v12, |v7|
; GFX1150-NEXT:    v_frexp_mant_f32_e64 v11, |v3|
; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v16, v3
; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v17, v7
; GFX1150-NEXT:    s_mov_b32 s1, exec_lo
; GFX1150-NEXT:    v_ldexp_f32 v12, v12, 1
; GFX1150-NEXT:    v_ldexp_f32 v14, v11, 12
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_add_nc_u32_e32 v11, -1, v17
; GFX1150-NEXT:    v_div_scale_f32 v18, null, v12, v12, 1.0
; GFX1150-NEXT:    v_div_scale_f32 v15, vcc_lo, 1.0, v12, 1.0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_xad_u32 v13, v11, -1, v16
; GFX1150-NEXT:    v_rcp_f32_e32 v19, v18
; GFX1150-NEXT:    s_denorm_mode 15
; GFX1150-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f32 v20, -v18, v19, 1.0
; GFX1150-NEXT:    v_fmac_f32_e32 v19, v20, v19
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f32_e32 v20, v15, v19
; GFX1150-NEXT:    v_fma_f32 v21, -v18, v20, v15
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fmac_f32_e32 v20, v21, v19
; GFX1150-NEXT:    v_fma_f32 v15, -v18, v20, v15
; GFX1150-NEXT:    s_denorm_mode 12
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_div_fmas_f32 v15, v15, v19, v20
; GFX1150-NEXT:    v_div_fixup_f32 v15, v15, v12, 1.0
; GFX1150-NEXT:    v_cmpx_lt_i32_e32 12, v13
; GFX1150-NEXT:    s_cbranch_execz .LBB12_31
; GFX1150-NEXT:  ; %bb.28: ; %frem.loop_body.preheader
; GFX1150-NEXT:    v_sub_nc_u32_e32 v13, v16, v17
; GFX1150-NEXT:    s_mov_b32 s2, 0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_add_nc_u32_e32 v13, 12, v13
; GFX1150-NEXT:  .LBB12_29: ; %frem.loop_body
; GFX1150-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_dual_mov_b32 v16, v14 :: v_dual_add_nc_u32 v13, -12, v13
; GFX1150-NEXT:    v_mul_f32_e32 v14, v16, v15
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_rndne_f32_e32 v14, v14
; GFX1150-NEXT:    v_fma_f32 v14, -v14, v12, v16
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v14
; GFX1150-NEXT:    v_add_f32_e32 v17, v14, v12
; GFX1150-NEXT:    v_cndmask_b32_e32 v14, v14, v17, vcc_lo
; GFX1150-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v13
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT:    v_ldexp_f32 v14, v14, 12
; GFX1150-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1150-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1150-NEXT:    s_cbranch_execnz .LBB12_29
; GFX1150-NEXT:  ; %bb.30: ; %Flow
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1150-NEXT:    v_mov_b32_e32 v14, v16
; GFX1150-NEXT:  .LBB12_31: ; %Flow111
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1150-NEXT:    v_add_nc_u32_e32 v13, -11, v13
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f32 v13, v14, v13
; GFX1150-NEXT:    v_mul_f32_e32 v14, v13, v15
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_rndne_f32_e32 v14, v14
; GFX1150-NEXT:    v_fma_f32 v13, -v14, v12, v13
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v13
; GFX1150-NEXT:    v_add_f32_e32 v12, v13, v12
; GFX1150-NEXT:    v_cndmask_b32_e32 v12, v13, v12, vcc_lo
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f32 v11, v12, v11
; GFX1150-NEXT:    v_bfi_b32 v11, 0x7fffffff, v11, v3
; GFX1150-NEXT:  .LBB12_32: ; %Flow113
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1150-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v4
; GFX1150-NEXT:    v_cmp_nge_f32_e64 s0, |v0|, 0x7f800000
; GFX1150-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1150-NEXT:    v_cmp_nge_f32_e64 s0, |v1|, 0x7f800000
; GFX1150-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v8, vcc_lo
; GFX1150-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v5
; GFX1150-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1150-NEXT:    v_cmp_nge_f32_e64 s0, |v2|, 0x7f800000
; GFX1150-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v9, vcc_lo
; GFX1150-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v6
; GFX1150-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1150-NEXT:    v_cmp_nge_f32_e64 s0, |v3|, 0x7f800000
; GFX1150-NEXT:    v_cndmask_b32_e32 v2, 0x7fc00000, v10, vcc_lo
; GFX1150-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v7
; GFX1150-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1150-NEXT:    v_cndmask_b32_e32 v3, 0x7fc00000, v11, vcc_lo
; GFX1150-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: frem_v4f32:
; GFX1200:       ; %bb.0:
; GFX1200-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT:    s_wait_expcnt 0x0
; GFX1200-NEXT:    s_wait_samplecnt 0x0
; GFX1200-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-NEXT:    s_wait_kmcnt 0x0
; GFX1200-NEXT:    v_cmp_ngt_f32_e64 s0, |v0|, |v4|
; GFX1200-NEXT:    ; implicit-def: $vgpr8
; GFX1200-NEXT:    s_and_saveexec_b32 s1, s0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX1200-NEXT:  ; %bb.1: ; %frem.else78
; GFX1200-NEXT:    v_and_b32_e32 v8, 0x80000000, v0
; GFX1200-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v0|, |v4|
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-NEXT:    v_cndmask_b32_e32 v8, v0, v8, vcc_lo
; GFX1200-NEXT:  ; %bb.2: ; %Flow124
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1200-NEXT:    s_cbranch_execz .LBB12_8
; GFX1200-NEXT:  ; %bb.3: ; %frem.compute77
; GFX1200-NEXT:    v_frexp_mant_f32_e64 v9, |v4|
; GFX1200-NEXT:    v_frexp_mant_f32_e64 v8, |v0|
; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v13, v0
; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v14, v4
; GFX1200-NEXT:    s_mov_b32 s1, exec_lo
; GFX1200-NEXT:    v_ldexp_f32 v9, v9, 1
; GFX1200-NEXT:    v_ldexp_f32 v11, v8, 12
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT:    v_div_scale_f32 v15, null, v9, v9, 1.0
; GFX1200-NEXT:    v_div_scale_f32 v12, vcc_lo, 1.0, v9, 1.0
; GFX1200-NEXT:    v_rcp_f32_e32 v16, v15
; GFX1200-NEXT:    s_denorm_mode 15
; GFX1200-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v17, -v15, v16, 1.0
; GFX1200-NEXT:    v_fmac_f32_e32 v16, v17, v16
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_dual_mul_f32 v17, v12, v16 :: v_dual_add_nc_u32 v8, -1, v14
; GFX1200-NEXT:    v_xad_u32 v10, v8, -1, v13
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v18, -v15, v17, v12
; GFX1200-NEXT:    v_fmac_f32_e32 v17, v18, v16
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v12, -v15, v17, v12
; GFX1200-NEXT:    s_denorm_mode 12
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_div_fmas_f32 v12, v12, v16, v17
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_div_fixup_f32 v12, v12, v9, 1.0
; GFX1200-NEXT:    v_cmpx_lt_i32_e32 12, v10
; GFX1200-NEXT:    s_cbranch_execz .LBB12_7
; GFX1200-NEXT:  ; %bb.4: ; %frem.loop_body85.preheader
; GFX1200-NEXT:    v_sub_nc_u32_e32 v10, v13, v14
; GFX1200-NEXT:    s_mov_b32 s2, 0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_add_nc_u32_e32 v10, 12, v10
; GFX1200-NEXT:  .LBB12_5: ; %frem.loop_body85
; GFX1200-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_dual_mov_b32 v13, v11 :: v_dual_add_nc_u32 v10, -12, v10
; GFX1200-NEXT:    v_mul_f32_e32 v11, v13, v12
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_rndne_f32_e32 v11, v11
; GFX1200-NEXT:    v_fma_f32 v11, -v11, v9, v13
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v11
; GFX1200-NEXT:    v_add_f32_e32 v14, v11, v9
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_cndmask_b32_e32 v11, v11, v14, vcc_lo
; GFX1200-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v10
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-NEXT:    v_ldexp_f32 v11, v11, 12
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1200-NEXT:    s_cbranch_execnz .LBB12_5
; GFX1200-NEXT:  ; %bb.6: ; %Flow122
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1200-NEXT:    v_mov_b32_e32 v11, v13
; GFX1200-NEXT:  .LBB12_7: ; %Flow123
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1200-NEXT:    v_add_nc_u32_e32 v10, -11, v10
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_ldexp_f32 v10, v11, v10
; GFX1200-NEXT:    v_mul_f32_e32 v11, v10, v12
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_rndne_f32_e32 v11, v11
; GFX1200-NEXT:    v_fma_f32 v10, -v11, v9, v10
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v10
; GFX1200-NEXT:    v_add_f32_e32 v9, v10, v9
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_cndmask_b32_e32 v9, v10, v9, vcc_lo
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_ldexp_f32 v8, v9, v8
; GFX1200-NEXT:    v_bfi_b32 v8, 0x7fffffff, v8, v0
; GFX1200-NEXT:  .LBB12_8: ; %Flow125
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1200-NEXT:    v_cmp_ngt_f32_e64 s0, |v1|, |v5|
; GFX1200-NEXT:    ; implicit-def: $vgpr9
; GFX1200-NEXT:    s_and_saveexec_b32 s1, s0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX1200-NEXT:  ; %bb.9: ; %frem.else47
; GFX1200-NEXT:    v_and_b32_e32 v9, 0x80000000, v1
; GFX1200-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v1|, |v5|
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-NEXT:    v_cndmask_b32_e32 v9, v1, v9, vcc_lo
; GFX1200-NEXT:  ; %bb.10: ; %Flow120
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1200-NEXT:    s_cbranch_execz .LBB12_16
; GFX1200-NEXT:  ; %bb.11: ; %frem.compute46
; GFX1200-NEXT:    v_frexp_mant_f32_e64 v10, |v5|
; GFX1200-NEXT:    v_frexp_mant_f32_e64 v9, |v1|
; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v14, v1
; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v15, v5
; GFX1200-NEXT:    s_mov_b32 s1, exec_lo
; GFX1200-NEXT:    v_ldexp_f32 v10, v10, 1
; GFX1200-NEXT:    v_ldexp_f32 v12, v9, 12
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT:    v_div_scale_f32 v16, null, v10, v10, 1.0
; GFX1200-NEXT:    v_div_scale_f32 v13, vcc_lo, 1.0, v10, 1.0
; GFX1200-NEXT:    v_rcp_f32_e32 v17, v16
; GFX1200-NEXT:    s_denorm_mode 15
; GFX1200-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v18, -v16, v17, 1.0
; GFX1200-NEXT:    v_fmac_f32_e32 v17, v18, v17
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_dual_mul_f32 v18, v13, v17 :: v_dual_add_nc_u32 v9, -1, v15
; GFX1200-NEXT:    v_xad_u32 v11, v9, -1, v14
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v19, -v16, v18, v13
; GFX1200-NEXT:    v_fmac_f32_e32 v18, v19, v17
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v13, -v16, v18, v13
; GFX1200-NEXT:    s_denorm_mode 12
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_div_fmas_f32 v13, v13, v17, v18
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_div_fixup_f32 v13, v13, v10, 1.0
; GFX1200-NEXT:    v_cmpx_lt_i32_e32 12, v11
; GFX1200-NEXT:    s_cbranch_execz .LBB12_15
; GFX1200-NEXT:  ; %bb.12: ; %frem.loop_body54.preheader
; GFX1200-NEXT:    v_sub_nc_u32_e32 v11, v14, v15
; GFX1200-NEXT:    s_mov_b32 s2, 0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_add_nc_u32_e32 v11, 12, v11
; GFX1200-NEXT:  .LBB12_13: ; %frem.loop_body54
; GFX1200-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_dual_mov_b32 v14, v12 :: v_dual_add_nc_u32 v11, -12, v11
; GFX1200-NEXT:    v_mul_f32_e32 v12, v14, v13
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_rndne_f32_e32 v12, v12
; GFX1200-NEXT:    v_fma_f32 v12, -v12, v10, v14
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v12
; GFX1200-NEXT:    v_add_f32_e32 v15, v12, v10
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_cndmask_b32_e32 v12, v12, v15, vcc_lo
; GFX1200-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v11
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-NEXT:    v_ldexp_f32 v12, v12, 12
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1200-NEXT:    s_cbranch_execnz .LBB12_13
; GFX1200-NEXT:  ; %bb.14: ; %Flow118
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1200-NEXT:    v_mov_b32_e32 v12, v14
; GFX1200-NEXT:  .LBB12_15: ; %Flow119
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1200-NEXT:    v_add_nc_u32_e32 v11, -11, v11
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_ldexp_f32 v11, v12, v11
; GFX1200-NEXT:    v_mul_f32_e32 v12, v11, v13
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_rndne_f32_e32 v12, v12
; GFX1200-NEXT:    v_fma_f32 v11, -v12, v10, v11
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v11
; GFX1200-NEXT:    v_add_f32_e32 v10, v11, v10
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_cndmask_b32_e32 v10, v11, v10, vcc_lo
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_ldexp_f32 v9, v10, v9
; GFX1200-NEXT:    v_bfi_b32 v9, 0x7fffffff, v9, v1
; GFX1200-NEXT:  .LBB12_16: ; %Flow121
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1200-NEXT:    v_cmp_ngt_f32_e64 s0, |v2|, |v6|
; GFX1200-NEXT:    ; implicit-def: $vgpr10
; GFX1200-NEXT:    s_and_saveexec_b32 s1, s0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX1200-NEXT:  ; %bb.17: ; %frem.else16
; GFX1200-NEXT:    v_and_b32_e32 v10, 0x80000000, v2
; GFX1200-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v2|, |v6|
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-NEXT:    v_cndmask_b32_e32 v10, v2, v10, vcc_lo
; GFX1200-NEXT:  ; %bb.18: ; %Flow116
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1200-NEXT:    s_cbranch_execz .LBB12_24
; GFX1200-NEXT:  ; %bb.19: ; %frem.compute15
; GFX1200-NEXT:    v_frexp_mant_f32_e64 v11, |v6|
; GFX1200-NEXT:    v_frexp_mant_f32_e64 v10, |v2|
; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v15, v2
; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v16, v6
; GFX1200-NEXT:    s_mov_b32 s1, exec_lo
; GFX1200-NEXT:    v_ldexp_f32 v11, v11, 1
; GFX1200-NEXT:    v_ldexp_f32 v13, v10, 12
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT:    v_div_scale_f32 v17, null, v11, v11, 1.0
; GFX1200-NEXT:    v_div_scale_f32 v14, vcc_lo, 1.0, v11, 1.0
; GFX1200-NEXT:    v_rcp_f32_e32 v18, v17
; GFX1200-NEXT:    s_denorm_mode 15
; GFX1200-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v19, -v17, v18, 1.0
; GFX1200-NEXT:    v_fmac_f32_e32 v18, v19, v18
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_dual_mul_f32 v19, v14, v18 :: v_dual_add_nc_u32 v10, -1, v16
; GFX1200-NEXT:    v_xad_u32 v12, v10, -1, v15
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v20, -v17, v19, v14
; GFX1200-NEXT:    v_fmac_f32_e32 v19, v20, v18
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v14, -v17, v19, v14
; GFX1200-NEXT:    s_denorm_mode 12
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_div_fmas_f32 v14, v14, v18, v19
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_div_fixup_f32 v14, v14, v11, 1.0
; GFX1200-NEXT:    v_cmpx_lt_i32_e32 12, v12
; GFX1200-NEXT:    s_cbranch_execz .LBB12_23
; GFX1200-NEXT:  ; %bb.20: ; %frem.loop_body23.preheader
; GFX1200-NEXT:    v_sub_nc_u32_e32 v12, v15, v16
; GFX1200-NEXT:    s_mov_b32 s2, 0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_add_nc_u32_e32 v12, 12, v12
; GFX1200-NEXT:  .LBB12_21: ; %frem.loop_body23
; GFX1200-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_dual_mov_b32 v15, v13 :: v_dual_add_nc_u32 v12, -12, v12
; GFX1200-NEXT:    v_mul_f32_e32 v13, v15, v14
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_rndne_f32_e32 v13, v13
; GFX1200-NEXT:    v_fma_f32 v13, -v13, v11, v15
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v13
; GFX1200-NEXT:    v_add_f32_e32 v16, v13, v11
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_cndmask_b32_e32 v13, v13, v16, vcc_lo
; GFX1200-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v12
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-NEXT:    v_ldexp_f32 v13, v13, 12
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1200-NEXT:    s_cbranch_execnz .LBB12_21
; GFX1200-NEXT:  ; %bb.22: ; %Flow114
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1200-NEXT:    v_mov_b32_e32 v13, v15
; GFX1200-NEXT:  .LBB12_23: ; %Flow115
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1200-NEXT:    v_add_nc_u32_e32 v12, -11, v12
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_ldexp_f32 v12, v13, v12
; GFX1200-NEXT:    v_mul_f32_e32 v13, v12, v14
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_rndne_f32_e32 v13, v13
; GFX1200-NEXT:    v_fma_f32 v12, -v13, v11, v12
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v12
; GFX1200-NEXT:    v_add_f32_e32 v11, v12, v11
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_cndmask_b32_e32 v11, v12, v11, vcc_lo
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_ldexp_f32 v10, v11, v10
; GFX1200-NEXT:    v_bfi_b32 v10, 0x7fffffff, v10, v2
; GFX1200-NEXT:  .LBB12_24: ; %Flow117
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1200-NEXT:    v_cmp_ngt_f32_e64 s0, |v3|, |v7|
; GFX1200-NEXT:    ; implicit-def: $vgpr11
; GFX1200-NEXT:    s_and_saveexec_b32 s1, s0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX1200-NEXT:  ; %bb.25: ; %frem.else
; GFX1200-NEXT:    v_and_b32_e32 v11, 0x80000000, v3
; GFX1200-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v3|, |v7|
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-NEXT:    v_cndmask_b32_e32 v11, v3, v11, vcc_lo
; GFX1200-NEXT:  ; %bb.26: ; %Flow112
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1200-NEXT:    s_cbranch_execz .LBB12_32
; GFX1200-NEXT:  ; %bb.27: ; %frem.compute
; GFX1200-NEXT:    v_frexp_mant_f32_e64 v12, |v7|
; GFX1200-NEXT:    v_frexp_mant_f32_e64 v11, |v3|
; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v16, v3
; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v17, v7
; GFX1200-NEXT:    s_mov_b32 s1, exec_lo
; GFX1200-NEXT:    v_ldexp_f32 v12, v12, 1
; GFX1200-NEXT:    v_ldexp_f32 v14, v11, 12
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT:    v_div_scale_f32 v18, null, v12, v12, 1.0
; GFX1200-NEXT:    v_div_scale_f32 v15, vcc_lo, 1.0, v12, 1.0
; GFX1200-NEXT:    v_rcp_f32_e32 v19, v18
; GFX1200-NEXT:    s_denorm_mode 15
; GFX1200-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v20, -v18, v19, 1.0
; GFX1200-NEXT:    v_fmac_f32_e32 v19, v20, v19
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_dual_mul_f32 v20, v15, v19 :: v_dual_add_nc_u32 v11, -1, v17
; GFX1200-NEXT:    v_xad_u32 v13, v11, -1, v16
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v21, -v18, v20, v15
; GFX1200-NEXT:    v_fmac_f32_e32 v20, v21, v19
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v15, -v18, v20, v15
; GFX1200-NEXT:    s_denorm_mode 12
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_div_fmas_f32 v15, v15, v19, v20
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_div_fixup_f32 v15, v15, v12, 1.0
; GFX1200-NEXT:    v_cmpx_lt_i32_e32 12, v13
; GFX1200-NEXT:    s_cbranch_execz .LBB12_31
; GFX1200-NEXT:  ; %bb.28: ; %frem.loop_body.preheader
; GFX1200-NEXT:    v_sub_nc_u32_e32 v13, v16, v17
; GFX1200-NEXT:    s_mov_b32 s2, 0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_add_nc_u32_e32 v13, 12, v13
; GFX1200-NEXT:  .LBB12_29: ; %frem.loop_body
; GFX1200-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_dual_mov_b32 v16, v14 :: v_dual_add_nc_u32 v13, -12, v13
; GFX1200-NEXT:    v_mul_f32_e32 v14, v16, v15
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_rndne_f32_e32 v14, v14
; GFX1200-NEXT:    v_fma_f32 v14, -v14, v12, v16
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v14
; GFX1200-NEXT:    v_add_f32_e32 v17, v14, v12
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_cndmask_b32_e32 v14, v14, v17, vcc_lo
; GFX1200-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v13
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-NEXT:    v_ldexp_f32 v14, v14, 12
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1200-NEXT:    s_cbranch_execnz .LBB12_29
; GFX1200-NEXT:  ; %bb.30: ; %Flow
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1200-NEXT:    v_mov_b32_e32 v14, v16
; GFX1200-NEXT:  .LBB12_31: ; %Flow111
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1200-NEXT:    v_add_nc_u32_e32 v13, -11, v13
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_ldexp_f32 v13, v14, v13
; GFX1200-NEXT:    v_mul_f32_e32 v14, v13, v15
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_rndne_f32_e32 v14, v14
; GFX1200-NEXT:    v_fma_f32 v13, -v14, v12, v13
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v13
; GFX1200-NEXT:    v_add_f32_e32 v12, v13, v12
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_cndmask_b32_e32 v12, v13, v12, vcc_lo
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_ldexp_f32 v11, v12, v11
; GFX1200-NEXT:    v_bfi_b32 v11, 0x7fffffff, v11, v3
; GFX1200-NEXT:  .LBB12_32: ; %Flow113
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1200-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v4
; GFX1200-NEXT:    v_cmp_nge_f32_e64 s0, |v0|, 0x7f800000
; GFX1200-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1200-NEXT:    v_cmp_nge_f32_e64 s0, |v1|, 0x7f800000
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v8, vcc_lo
; GFX1200-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v5
; GFX1200-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1200-NEXT:    v_cmp_nge_f32_e64 s0, |v2|, 0x7f800000
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v9, vcc_lo
; GFX1200-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v6
; GFX1200-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1200-NEXT:    v_cmp_nge_f32_e64 s0, |v3|, 0x7f800000
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    v_cndmask_b32_e32 v2, 0x7fc00000, v10, vcc_lo
; GFX1200-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v7
; GFX1200-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    v_cndmask_b32_e32 v3, 0x7fc00000, v11, vcc_lo
; GFX1200-NEXT:    s_setpc_b64 s[30:31]
   %r2 = frem <4 x float> %in1, %in2
  ret <4 x float> %r2
}

define <2 x double> @frem_v2f64(<2 x double> %in1, <2 x double> %in2) #0 {
; SI-LABEL: frem_v2f64:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cmp_ngt_f64_e64 s[4:5], |v[0:1]|, |v[4:5]|
; SI-NEXT:    ; implicit-def: $vgpr8_vgpr9
; SI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; SI-NEXT:  ; %bb.1: ; %frem.else16
; SI-NEXT:    v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[4:5]|
; SI-NEXT:    v_and_b32_e32 v8, 0x80000000, v1
; SI-NEXT:    v_cndmask_b32_e32 v9, v1, v8, vcc
; SI-NEXT:    v_cndmask_b32_e64 v8, v0, 0, vcc
; SI-NEXT:  ; %bb.2: ; %Flow50
; SI-NEXT:    s_andn2_saveexec_b64 s[6:7], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB13_8
; SI-NEXT:  ; %bb.3: ; %frem.compute15
; SI-NEXT:    v_and_b32_e32 v10, 0x7fffffff, v1
; SI-NEXT:    s_mov_b32 s4, 0x7ff00000
; SI-NEXT:    v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, s4, v10
; SI-NEXT:    v_cndmask_b32_e32 v9, v10, v9, vcc
; SI-NEXT:    v_frexp_exp_i32_f64_e32 v10, v[0:1]
; SI-NEXT:    v_cndmask_b32_e32 v8, v0, v8, vcc
; SI-NEXT:    v_cndmask_b32_e32 v14, 0, v10, vcc
; SI-NEXT:    v_ldexp_f64 v[12:13], v[8:9], 26
; SI-NEXT:    v_and_b32_e32 v10, 0x7fffffff, v5
; SI-NEXT:    v_frexp_mant_f64_e64 v[8:9], |v[4:5]|
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, s4, v10
; SI-NEXT:    v_cndmask_b32_e32 v9, v10, v9, vcc
; SI-NEXT:    v_frexp_exp_i32_f64_e32 v10, v[4:5]
; SI-NEXT:    v_cndmask_b32_e32 v8, v4, v8, vcc
; SI-NEXT:    v_cndmask_b32_e32 v15, 0, v10, vcc
; SI-NEXT:    v_add_i32_e32 v18, vcc, -1, v15
; SI-NEXT:    v_ldexp_f64 v[8:9], v[8:9], 1
; SI-NEXT:    v_not_b32_e32 v10, v18
; SI-NEXT:    v_add_i32_e32 v19, vcc, v10, v14
; SI-NEXT:    v_div_scale_f64 v[10:11], s[4:5], v[8:9], v[8:9], 1.0
; SI-NEXT:    s_brev_b32 s12, -2
; SI-NEXT:    s_mov_b32 s8, -1
; SI-NEXT:    v_rcp_f64_e32 v[16:17], v[10:11]
; SI-NEXT:    v_cmp_eq_u32_e32 vcc, v9, v11
; SI-NEXT:    v_fma_f64 v[20:21], -v[10:11], v[16:17], 1.0
; SI-NEXT:    v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
; SI-NEXT:    v_fma_f64 v[20:21], -v[10:11], v[16:17], 1.0
; SI-NEXT:    v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
; SI-NEXT:    v_div_scale_f64 v[20:21], s[4:5], 1.0, v[8:9], 1.0
; SI-NEXT:    s_mov_b32 s4, 0x3ff00000
; SI-NEXT:    v_mul_f64 v[22:23], v[20:21], v[16:17]
; SI-NEXT:    v_cmp_eq_u32_e64 s[4:5], s4, v21
; SI-NEXT:    v_fma_f64 v[24:25], -v[10:11], v[22:23], v[20:21]
; SI-NEXT:    s_xor_b64 vcc, s[4:5], vcc
; SI-NEXT:    v_div_fmas_f64 v[10:11], v[24:25], v[16:17], v[22:23]
; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v19
; SI-NEXT:    v_div_fixup_f64 v[10:11], v[10:11], v[8:9], 1.0
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_cbranch_execz .LBB13_7
; SI-NEXT:  ; %bb.4: ; %frem.loop_body23.preheader
; SI-NEXT:    v_sub_i32_e32 v14, vcc, v14, v15
; SI-NEXT:    v_add_i32_e32 v19, vcc, 26, v14
; SI-NEXT:    s_mov_b64 s[10:11], 0
; SI-NEXT:    s_mov_b32 s9, 0x432fffff
; SI-NEXT:    v_mov_b32_e32 v14, 0
; SI-NEXT:    v_mov_b32_e32 v20, 0x43300000
; SI-NEXT:  .LBB13_5: ; %frem.loop_body23
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v17, v13
; SI-NEXT:    v_mov_b32_e32 v16, v12
; SI-NEXT:    v_mul_f64 v[12:13], v[16:17], v[10:11]
; SI-NEXT:    v_bfi_b32 v15, s12, v20, v13
; SI-NEXT:    v_add_f64 v[21:22], v[12:13], v[14:15]
; SI-NEXT:    v_cmp_gt_f64_e64 vcc, |v[12:13]|, s[8:9]
; SI-NEXT:    v_add_f64 v[21:22], v[21:22], -v[14:15]
; SI-NEXT:    v_cndmask_b32_e32 v13, v22, v13, vcc
; SI-NEXT:    v_cndmask_b32_e32 v12, v21, v12, vcc
; SI-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[8:9], v[16:17]
; SI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[12:13]
; SI-NEXT:    v_add_f64 v[21:22], v[12:13], v[8:9]
; SI-NEXT:    v_cndmask_b32_e32 v13, v13, v22, vcc
; SI-NEXT:    v_cndmask_b32_e32 v12, v12, v21, vcc
; SI-NEXT:    v_subrev_i32_e32 v19, vcc, 26, v19
; SI-NEXT:    v_ldexp_f64 v[12:13], v[12:13], 26
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v19
; SI-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
; SI-NEXT:    s_andn2_b64 exec, exec, s[10:11]
; SI-NEXT:    s_cbranch_execnz .LBB13_5
; SI-NEXT:  ; %bb.6: ; %Flow48
; SI-NEXT:    s_or_b64 exec, exec, s[10:11]
; SI-NEXT:    v_mov_b32_e32 v12, v16
; SI-NEXT:    v_mov_b32_e32 v13, v17
; SI-NEXT:  .LBB13_7: ; %Flow49
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    v_subrev_i32_e32 v14, vcc, 25, v19
; SI-NEXT:    v_ldexp_f64 v[12:13], v[12:13], v14
; SI-NEXT:    s_mov_b32 s4, -1
; SI-NEXT:    v_mul_f64 v[10:11], v[12:13], v[10:11]
; SI-NEXT:    s_mov_b32 s5, 0x432fffff
; SI-NEXT:    v_cmp_gt_f64_e64 vcc, |v[10:11]|, s[4:5]
; SI-NEXT:    s_brev_b32 s4, -2
; SI-NEXT:    v_mov_b32_e32 v14, 0x43300000
; SI-NEXT:    v_bfi_b32 v15, s4, v14, v11
; SI-NEXT:    v_mov_b32_e32 v14, 0
; SI-NEXT:    v_add_f64 v[16:17], v[10:11], v[14:15]
; SI-NEXT:    v_add_f64 v[14:15], v[16:17], -v[14:15]
; SI-NEXT:    v_cndmask_b32_e32 v11, v15, v11, vcc
; SI-NEXT:    v_cndmask_b32_e32 v10, v14, v10, vcc
; SI-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[8:9], v[12:13]
; SI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[10:11]
; SI-NEXT:    v_add_f64 v[8:9], v[10:11], v[8:9]
; SI-NEXT:    v_cndmask_b32_e32 v9, v11, v9, vcc
; SI-NEXT:    v_cndmask_b32_e32 v8, v10, v8, vcc
; SI-NEXT:    v_ldexp_f64 v[8:9], v[8:9], v18
; SI-NEXT:    v_bfi_b32 v9, s4, v9, v1
; SI-NEXT:  .LBB13_8: ; %Flow51
; SI-NEXT:    s_or_b64 exec, exec, s[6:7]
; SI-NEXT:    v_cmp_ngt_f64_e64 s[4:5], |v[2:3]|, |v[6:7]|
; SI-NEXT:    ; implicit-def: $vgpr10_vgpr11
; SI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; SI-NEXT:  ; %bb.9: ; %frem.else
; SI-NEXT:    v_cmp_eq_f64_e64 vcc, |v[2:3]|, |v[6:7]|
; SI-NEXT:    v_and_b32_e32 v10, 0x80000000, v3
; SI-NEXT:    v_cndmask_b32_e32 v11, v3, v10, vcc
; SI-NEXT:    v_cndmask_b32_e64 v10, v2, 0, vcc
; SI-NEXT:  ; %bb.10: ; %Flow46
; SI-NEXT:    s_andn2_saveexec_b64 s[6:7], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB13_16
; SI-NEXT:  ; %bb.11: ; %frem.compute
; SI-NEXT:    v_and_b32_e32 v12, 0x7fffffff, v3
; SI-NEXT:    s_mov_b32 s4, 0x7ff00000
; SI-NEXT:    v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, s4, v12
; SI-NEXT:    v_cndmask_b32_e32 v11, v12, v11, vcc
; SI-NEXT:    v_frexp_exp_i32_f64_e32 v12, v[2:3]
; SI-NEXT:    v_cndmask_b32_e32 v10, v2, v10, vcc
; SI-NEXT:    v_cndmask_b32_e32 v16, 0, v12, vcc
; SI-NEXT:    v_ldexp_f64 v[14:15], v[10:11], 26
; SI-NEXT:    v_and_b32_e32 v12, 0x7fffffff, v7
; SI-NEXT:    v_frexp_mant_f64_e64 v[10:11], |v[6:7]|
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, s4, v12
; SI-NEXT:    v_cndmask_b32_e32 v11, v12, v11, vcc
; SI-NEXT:    v_frexp_exp_i32_f64_e32 v12, v[6:7]
; SI-NEXT:    v_cndmask_b32_e32 v10, v6, v10, vcc
; SI-NEXT:    v_cndmask_b32_e32 v17, 0, v12, vcc
; SI-NEXT:    v_add_i32_e32 v20, vcc, -1, v17
; SI-NEXT:    v_ldexp_f64 v[10:11], v[10:11], 1
; SI-NEXT:    v_not_b32_e32 v12, v20
; SI-NEXT:    v_add_i32_e32 v21, vcc, v12, v16
; SI-NEXT:    v_div_scale_f64 v[12:13], s[4:5], v[10:11], v[10:11], 1.0
; SI-NEXT:    s_brev_b32 s12, -2
; SI-NEXT:    s_mov_b32 s8, -1
; SI-NEXT:    v_rcp_f64_e32 v[18:19], v[12:13]
; SI-NEXT:    v_cmp_eq_u32_e32 vcc, v11, v13
; SI-NEXT:    v_fma_f64 v[22:23], -v[12:13], v[18:19], 1.0
; SI-NEXT:    v_fma_f64 v[18:19], v[18:19], v[22:23], v[18:19]
; SI-NEXT:    v_fma_f64 v[22:23], -v[12:13], v[18:19], 1.0
; SI-NEXT:    v_fma_f64 v[18:19], v[18:19], v[22:23], v[18:19]
; SI-NEXT:    v_div_scale_f64 v[22:23], s[4:5], 1.0, v[10:11], 1.0
; SI-NEXT:    s_mov_b32 s4, 0x3ff00000
; SI-NEXT:    v_mul_f64 v[24:25], v[22:23], v[18:19]
; SI-NEXT:    v_cmp_eq_u32_e64 s[4:5], s4, v23
; SI-NEXT:    v_fma_f64 v[26:27], -v[12:13], v[24:25], v[22:23]
; SI-NEXT:    s_xor_b64 vcc, s[4:5], vcc
; SI-NEXT:    v_div_fmas_f64 v[12:13], v[26:27], v[18:19], v[24:25]
; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v21
; SI-NEXT:    v_div_fixup_f64 v[12:13], v[12:13], v[10:11], 1.0
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_cbranch_execz .LBB13_15
; SI-NEXT:  ; %bb.12: ; %frem.loop_body.preheader
; SI-NEXT:    v_sub_i32_e32 v16, vcc, v16, v17
; SI-NEXT:    v_add_i32_e32 v21, vcc, 26, v16
; SI-NEXT:    s_mov_b64 s[10:11], 0
; SI-NEXT:    s_mov_b32 s9, 0x432fffff
; SI-NEXT:    v_mov_b32_e32 v16, 0
; SI-NEXT:    v_mov_b32_e32 v22, 0x43300000
; SI-NEXT:  .LBB13_13: ; %frem.loop_body
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v19, v15
; SI-NEXT:    v_mov_b32_e32 v18, v14
; SI-NEXT:    v_mul_f64 v[14:15], v[18:19], v[12:13]
; SI-NEXT:    v_bfi_b32 v17, s12, v22, v15
; SI-NEXT:    v_add_f64 v[23:24], v[14:15], v[16:17]
; SI-NEXT:    v_cmp_gt_f64_e64 vcc, |v[14:15]|, s[8:9]
; SI-NEXT:    v_add_f64 v[23:24], v[23:24], -v[16:17]
; SI-NEXT:    v_cndmask_b32_e32 v15, v24, v15, vcc
; SI-NEXT:    v_cndmask_b32_e32 v14, v23, v14, vcc
; SI-NEXT:    v_fma_f64 v[14:15], -v[14:15], v[10:11], v[18:19]
; SI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[14:15]
; SI-NEXT:    v_add_f64 v[23:24], v[14:15], v[10:11]
; SI-NEXT:    v_cndmask_b32_e32 v15, v15, v24, vcc
; SI-NEXT:    v_cndmask_b32_e32 v14, v14, v23, vcc
; SI-NEXT:    v_subrev_i32_e32 v21, vcc, 26, v21
; SI-NEXT:    v_ldexp_f64 v[14:15], v[14:15], 26
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v21
; SI-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
; SI-NEXT:    s_andn2_b64 exec, exec, s[10:11]
; SI-NEXT:    s_cbranch_execnz .LBB13_13
; SI-NEXT:  ; %bb.14: ; %Flow
; SI-NEXT:    s_or_b64 exec, exec, s[10:11]
; SI-NEXT:    v_mov_b32_e32 v14, v18
; SI-NEXT:    v_mov_b32_e32 v15, v19
; SI-NEXT:  .LBB13_15: ; %Flow45
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    v_subrev_i32_e32 v16, vcc, 25, v21
; SI-NEXT:    v_ldexp_f64 v[14:15], v[14:15], v16
; SI-NEXT:    s_mov_b32 s4, -1
; SI-NEXT:    v_mul_f64 v[12:13], v[14:15], v[12:13]
; SI-NEXT:    s_mov_b32 s5, 0x432fffff
; SI-NEXT:    v_cmp_gt_f64_e64 vcc, |v[12:13]|, s[4:5]
; SI-NEXT:    s_brev_b32 s4, -2
; SI-NEXT:    v_mov_b32_e32 v16, 0x43300000
; SI-NEXT:    v_bfi_b32 v17, s4, v16, v13
; SI-NEXT:    v_mov_b32_e32 v16, 0
; SI-NEXT:    v_add_f64 v[18:19], v[12:13], v[16:17]
; SI-NEXT:    v_add_f64 v[16:17], v[18:19], -v[16:17]
; SI-NEXT:    v_cndmask_b32_e32 v13, v17, v13, vcc
; SI-NEXT:    v_cndmask_b32_e32 v12, v16, v12, vcc
; SI-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[10:11], v[14:15]
; SI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[12:13]
; SI-NEXT:    v_add_f64 v[10:11], v[12:13], v[10:11]
; SI-NEXT:    v_cndmask_b32_e32 v11, v13, v11, vcc
; SI-NEXT:    v_cndmask_b32_e32 v10, v12, v10, vcc
; SI-NEXT:    v_ldexp_f64 v[10:11], v[10:11], v20
; SI-NEXT:    v_bfi_b32 v11, s4, v11, v3
; SI-NEXT:  .LBB13_16: ; %Flow47
; SI-NEXT:    s_or_b64 exec, exec, s[6:7]
; SI-NEXT:    s_mov_b32 s4, 0
; SI-NEXT:    s_mov_b32 s5, 0x7ff00000
; SI-NEXT:    v_cmp_lg_f64_e32 vcc, 0, v[4:5]
; SI-NEXT:    v_cmp_nge_f64_e64 s[6:7], |v[0:1]|, s[4:5]
; SI-NEXT:    v_mov_b32_e32 v4, 0x7ff80000
; SI-NEXT:    s_and_b64 vcc, s[6:7], vcc
; SI-NEXT:    v_cndmask_b32_e32 v0, 0, v8, vcc
; SI-NEXT:    v_cndmask_b32_e32 v1, v4, v9, vcc
; SI-NEXT:    v_cmp_lg_f64_e32 vcc, 0, v[6:7]
; SI-NEXT:    v_cmp_nge_f64_e64 s[4:5], |v[2:3]|, s[4:5]
; SI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; SI-NEXT:    v_cndmask_b32_e32 v2, 0, v10, vcc
; SI-NEXT:    v_cndmask_b32_e32 v3, v4, v11, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; CI-LABEL: frem_v2f64:
; CI:       ; %bb.0:
; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-NEXT:    v_cmp_ngt_f64_e64 s[4:5], |v[0:1]|, |v[4:5]|
; CI-NEXT:    ; implicit-def: $vgpr8_vgpr9
; CI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; CI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; CI-NEXT:    s_cbranch_execz .LBB13_2
; CI-NEXT:  ; %bb.1: ; %frem.else16
; CI-NEXT:    v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[4:5]|
; CI-NEXT:    v_and_b32_e32 v8, 0x80000000, v1
; CI-NEXT:    v_cndmask_b32_e32 v9, v1, v8, vcc
; CI-NEXT:    v_cndmask_b32_e64 v8, v0, 0, vcc
; CI-NEXT:  .LBB13_2: ; %Flow50
; CI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; CI-NEXT:    s_cbranch_execz .LBB13_8
; CI-NEXT:  ; %bb.3: ; %frem.compute15
; CI-NEXT:    v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
; CI-NEXT:    v_frexp_exp_i32_f64_e32 v15, v[4:5]
; CI-NEXT:    v_frexp_exp_i32_f64_e32 v14, v[0:1]
; CI-NEXT:    v_ldexp_f64 v[12:13], v[8:9], 26
; CI-NEXT:    v_frexp_mant_f64_e64 v[8:9], |v[4:5]|
; CI-NEXT:    v_add_i32_e32 v16, vcc, -1, v15
; CI-NEXT:    v_not_b32_e32 v10, v16
; CI-NEXT:    v_add_i32_e32 v17, vcc, v10, v14
; CI-NEXT:    v_ldexp_f64 v[8:9], v[8:9], 1
; CI-NEXT:    v_div_scale_f64 v[10:11], s[6:7], v[8:9], v[8:9], 1.0
; CI-NEXT:    v_rcp_f64_e32 v[18:19], v[10:11]
; CI-NEXT:    v_fma_f64 v[20:21], -v[10:11], v[18:19], 1.0
; CI-NEXT:    v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
; CI-NEXT:    v_fma_f64 v[20:21], -v[10:11], v[18:19], 1.0
; CI-NEXT:    v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
; CI-NEXT:    v_div_scale_f64 v[20:21], vcc, 1.0, v[8:9], 1.0
; CI-NEXT:    v_mul_f64 v[22:23], v[20:21], v[18:19]
; CI-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[22:23], v[20:21]
; CI-NEXT:    s_nop 1
; CI-NEXT:    v_div_fmas_f64 v[10:11], v[10:11], v[18:19], v[22:23]
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v17
; CI-NEXT:    v_div_fixup_f64 v[10:11], v[10:11], v[8:9], 1.0
; CI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; CI-NEXT:    s_cbranch_execz .LBB13_7
; CI-NEXT:  ; %bb.4: ; %frem.loop_body23.preheader
; CI-NEXT:    v_sub_i32_e32 v14, vcc, v14, v15
; CI-NEXT:    v_add_i32_e32 v17, vcc, 26, v14
; CI-NEXT:    s_mov_b64 s[8:9], 0
; CI-NEXT:  .LBB13_5: ; %frem.loop_body23
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v15, v13
; CI-NEXT:    v_mov_b32_e32 v14, v12
; CI-NEXT:    v_mul_f64 v[12:13], v[14:15], v[10:11]
; CI-NEXT:    v_rndne_f64_e32 v[12:13], v[12:13]
; CI-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[8:9], v[14:15]
; CI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[12:13]
; CI-NEXT:    v_add_f64 v[18:19], v[12:13], v[8:9]
; CI-NEXT:    v_cndmask_b32_e32 v13, v13, v19, vcc
; CI-NEXT:    v_cndmask_b32_e32 v12, v12, v18, vcc
; CI-NEXT:    v_ldexp_f64 v[12:13], v[12:13], 26
; CI-NEXT:    v_subrev_i32_e32 v17, vcc, 26, v17
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v17
; CI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; CI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; CI-NEXT:    s_cbranch_execnz .LBB13_5
; CI-NEXT:  ; %bb.6: ; %Flow48
; CI-NEXT:    s_or_b64 exec, exec, s[8:9]
; CI-NEXT:    v_mov_b32_e32 v12, v14
; CI-NEXT:    v_mov_b32_e32 v13, v15
; CI-NEXT:  .LBB13_7: ; %Flow49
; CI-NEXT:    s_or_b64 exec, exec, s[6:7]
; CI-NEXT:    v_subrev_i32_e32 v14, vcc, 25, v17
; CI-NEXT:    v_ldexp_f64 v[12:13], v[12:13], v14
; CI-NEXT:    s_brev_b32 s6, -2
; CI-NEXT:    v_mul_f64 v[10:11], v[12:13], v[10:11]
; CI-NEXT:    v_rndne_f64_e32 v[10:11], v[10:11]
; CI-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[8:9], v[12:13]
; CI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[10:11]
; CI-NEXT:    v_add_f64 v[8:9], v[10:11], v[8:9]
; CI-NEXT:    v_cndmask_b32_e32 v9, v11, v9, vcc
; CI-NEXT:    v_cndmask_b32_e32 v8, v10, v8, vcc
; CI-NEXT:    v_ldexp_f64 v[8:9], v[8:9], v16
; CI-NEXT:    v_bfi_b32 v9, s6, v9, v1
; CI-NEXT:  .LBB13_8: ; %Flow51
; CI-NEXT:    s_or_b64 exec, exec, s[4:5]
; CI-NEXT:    v_cmp_ngt_f64_e64 s[4:5], |v[2:3]|, |v[6:7]|
; CI-NEXT:    ; implicit-def: $vgpr10_vgpr11
; CI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; CI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; CI-NEXT:    s_cbranch_execz .LBB13_10
; CI-NEXT:  ; %bb.9: ; %frem.else
; CI-NEXT:    v_cmp_eq_f64_e64 vcc, |v[2:3]|, |v[6:7]|
; CI-NEXT:    v_and_b32_e32 v10, 0x80000000, v3
; CI-NEXT:    v_cndmask_b32_e32 v11, v3, v10, vcc
; CI-NEXT:    v_cndmask_b32_e64 v10, v2, 0, vcc
; CI-NEXT:  .LBB13_10: ; %Flow46
; CI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; CI-NEXT:    s_cbranch_execz .LBB13_16
; CI-NEXT:  ; %bb.11: ; %frem.compute
; CI-NEXT:    v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
; CI-NEXT:    v_frexp_exp_i32_f64_e32 v17, v[6:7]
; CI-NEXT:    v_frexp_exp_i32_f64_e32 v16, v[2:3]
; CI-NEXT:    v_ldexp_f64 v[14:15], v[10:11], 26
; CI-NEXT:    v_frexp_mant_f64_e64 v[10:11], |v[6:7]|
; CI-NEXT:    v_add_i32_e32 v18, vcc, -1, v17
; CI-NEXT:    v_not_b32_e32 v12, v18
; CI-NEXT:    v_add_i32_e32 v19, vcc, v12, v16
; CI-NEXT:    v_ldexp_f64 v[10:11], v[10:11], 1
; CI-NEXT:    v_div_scale_f64 v[12:13], s[6:7], v[10:11], v[10:11], 1.0
; CI-NEXT:    v_rcp_f64_e32 v[20:21], v[12:13]
; CI-NEXT:    v_fma_f64 v[22:23], -v[12:13], v[20:21], 1.0
; CI-NEXT:    v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21]
; CI-NEXT:    v_fma_f64 v[22:23], -v[12:13], v[20:21], 1.0
; CI-NEXT:    v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21]
; CI-NEXT:    v_div_scale_f64 v[22:23], vcc, 1.0, v[10:11], 1.0
; CI-NEXT:    v_mul_f64 v[24:25], v[22:23], v[20:21]
; CI-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[24:25], v[22:23]
; CI-NEXT:    s_nop 1
; CI-NEXT:    v_div_fmas_f64 v[12:13], v[12:13], v[20:21], v[24:25]
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v19
; CI-NEXT:    v_div_fixup_f64 v[12:13], v[12:13], v[10:11], 1.0
; CI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; CI-NEXT:    s_cbranch_execz .LBB13_15
; CI-NEXT:  ; %bb.12: ; %frem.loop_body.preheader
; CI-NEXT:    v_sub_i32_e32 v16, vcc, v16, v17
; CI-NEXT:    v_add_i32_e32 v19, vcc, 26, v16
; CI-NEXT:    s_mov_b64 s[8:9], 0
; CI-NEXT:  .LBB13_13: ; %frem.loop_body
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v17, v15
; CI-NEXT:    v_mov_b32_e32 v16, v14
; CI-NEXT:    v_mul_f64 v[14:15], v[16:17], v[12:13]
; CI-NEXT:    v_rndne_f64_e32 v[14:15], v[14:15]
; CI-NEXT:    v_fma_f64 v[14:15], -v[14:15], v[10:11], v[16:17]
; CI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[14:15]
; CI-NEXT:    v_add_f64 v[20:21], v[14:15], v[10:11]
; CI-NEXT:    v_cndmask_b32_e32 v15, v15, v21, vcc
; CI-NEXT:    v_cndmask_b32_e32 v14, v14, v20, vcc
; CI-NEXT:    v_ldexp_f64 v[14:15], v[14:15], 26
; CI-NEXT:    v_subrev_i32_e32 v19, vcc, 26, v19
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v19
; CI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; CI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; CI-NEXT:    s_cbranch_execnz .LBB13_13
; CI-NEXT:  ; %bb.14: ; %Flow
; CI-NEXT:    s_or_b64 exec, exec, s[8:9]
; CI-NEXT:    v_mov_b32_e32 v14, v16
; CI-NEXT:    v_mov_b32_e32 v15, v17
; CI-NEXT:  .LBB13_15: ; %Flow45
; CI-NEXT:    s_or_b64 exec, exec, s[6:7]
; CI-NEXT:    v_subrev_i32_e32 v16, vcc, 25, v19
; CI-NEXT:    v_ldexp_f64 v[14:15], v[14:15], v16
; CI-NEXT:    s_brev_b32 s6, -2
; CI-NEXT:    v_mul_f64 v[12:13], v[14:15], v[12:13]
; CI-NEXT:    v_rndne_f64_e32 v[12:13], v[12:13]
; CI-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[10:11], v[14:15]
; CI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[12:13]
; CI-NEXT:    v_add_f64 v[10:11], v[12:13], v[10:11]
; CI-NEXT:    v_cndmask_b32_e32 v11, v13, v11, vcc
; CI-NEXT:    v_cndmask_b32_e32 v10, v12, v10, vcc
; CI-NEXT:    v_ldexp_f64 v[10:11], v[10:11], v18
; CI-NEXT:    v_bfi_b32 v11, s6, v11, v3
; CI-NEXT:  .LBB13_16: ; %Flow47
; CI-NEXT:    s_or_b64 exec, exec, s[4:5]
; CI-NEXT:    s_mov_b32 s4, 0
; CI-NEXT:    s_mov_b32 s5, 0x7ff00000
; CI-NEXT:    v_cmp_lg_f64_e32 vcc, 0, v[4:5]
; CI-NEXT:    v_cmp_nge_f64_e64 s[6:7], |v[0:1]|, s[4:5]
; CI-NEXT:    v_mov_b32_e32 v4, 0x7ff80000
; CI-NEXT:    v_cmp_nge_f64_e64 s[4:5], |v[2:3]|, s[4:5]
; CI-NEXT:    s_and_b64 vcc, s[6:7], vcc
; CI-NEXT:    v_cndmask_b32_e32 v0, 0, v8, vcc
; CI-NEXT:    v_cndmask_b32_e32 v1, v4, v9, vcc
; CI-NEXT:    v_cmp_lg_f64_e32 vcc, 0, v[6:7]
; CI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; CI-NEXT:    v_cndmask_b32_e32 v2, 0, v10, vcc
; CI-NEXT:    v_cndmask_b32_e32 v3, v4, v11, vcc
; CI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: frem_v2f64:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ngt_f64_e64 s[4:5], |v[0:1]|, |v[4:5]|
; VI-NEXT:    ; implicit-def: $vgpr8_vgpr9
; VI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; VI-NEXT:    s_cbranch_execz .LBB13_2
; VI-NEXT:  ; %bb.1: ; %frem.else16
; VI-NEXT:    v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[4:5]|
; VI-NEXT:    v_and_b32_e32 v8, 0x80000000, v1
; VI-NEXT:    v_cndmask_b32_e32 v9, v1, v8, vcc
; VI-NEXT:    v_cndmask_b32_e64 v8, v0, 0, vcc
; VI-NEXT:  .LBB13_2: ; %Flow50
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB13_8
; VI-NEXT:  ; %bb.3: ; %frem.compute15
; VI-NEXT:    v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
; VI-NEXT:    v_frexp_exp_i32_f64_e32 v15, v[4:5]
; VI-NEXT:    v_frexp_exp_i32_f64_e32 v14, v[0:1]
; VI-NEXT:    v_ldexp_f64 v[12:13], v[8:9], 26
; VI-NEXT:    v_frexp_mant_f64_e64 v[8:9], |v[4:5]|
; VI-NEXT:    v_add_u32_e32 v16, vcc, -1, v15
; VI-NEXT:    v_not_b32_e32 v10, v16
; VI-NEXT:    v_add_u32_e32 v17, vcc, v10, v14
; VI-NEXT:    v_ldexp_f64 v[8:9], v[8:9], 1
; VI-NEXT:    v_div_scale_f64 v[10:11], s[6:7], v[8:9], v[8:9], 1.0
; VI-NEXT:    v_rcp_f64_e32 v[18:19], v[10:11]
; VI-NEXT:    v_fma_f64 v[20:21], -v[10:11], v[18:19], 1.0
; VI-NEXT:    v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
; VI-NEXT:    v_fma_f64 v[20:21], -v[10:11], v[18:19], 1.0
; VI-NEXT:    v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
; VI-NEXT:    v_div_scale_f64 v[20:21], vcc, 1.0, v[8:9], 1.0
; VI-NEXT:    v_mul_f64 v[22:23], v[20:21], v[18:19]
; VI-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[22:23], v[20:21]
; VI-NEXT:    s_nop 1
; VI-NEXT:    v_div_fmas_f64 v[10:11], v[10:11], v[18:19], v[22:23]
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v17
; VI-NEXT:    v_div_fixup_f64 v[10:11], v[10:11], v[8:9], 1.0
; VI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; VI-NEXT:    s_cbranch_execz .LBB13_7
; VI-NEXT:  ; %bb.4: ; %frem.loop_body23.preheader
; VI-NEXT:    v_sub_u32_e32 v14, vcc, v14, v15
; VI-NEXT:    v_add_u32_e32 v17, vcc, 26, v14
; VI-NEXT:    s_mov_b64 s[8:9], 0
; VI-NEXT:  .LBB13_5: ; %frem.loop_body23
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v15, v13
; VI-NEXT:    v_mov_b32_e32 v14, v12
; VI-NEXT:    v_mul_f64 v[12:13], v[14:15], v[10:11]
; VI-NEXT:    v_rndne_f64_e32 v[12:13], v[12:13]
; VI-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[8:9], v[14:15]
; VI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[12:13]
; VI-NEXT:    v_add_f64 v[18:19], v[12:13], v[8:9]
; VI-NEXT:    v_cndmask_b32_e32 v13, v13, v19, vcc
; VI-NEXT:    v_cndmask_b32_e32 v12, v12, v18, vcc
; VI-NEXT:    v_ldexp_f64 v[12:13], v[12:13], 26
; VI-NEXT:    v_subrev_u32_e32 v17, vcc, 26, v17
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v17
; VI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; VI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; VI-NEXT:    s_cbranch_execnz .LBB13_5
; VI-NEXT:  ; %bb.6: ; %Flow48
; VI-NEXT:    s_or_b64 exec, exec, s[8:9]
; VI-NEXT:    v_mov_b32_e32 v12, v14
; VI-NEXT:    v_mov_b32_e32 v13, v15
; VI-NEXT:  .LBB13_7: ; %Flow49
; VI-NEXT:    s_or_b64 exec, exec, s[6:7]
; VI-NEXT:    v_subrev_u32_e32 v14, vcc, 25, v17
; VI-NEXT:    v_ldexp_f64 v[12:13], v[12:13], v14
; VI-NEXT:    s_brev_b32 s6, -2
; VI-NEXT:    v_mul_f64 v[10:11], v[12:13], v[10:11]
; VI-NEXT:    v_rndne_f64_e32 v[10:11], v[10:11]
; VI-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[8:9], v[12:13]
; VI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[10:11]
; VI-NEXT:    v_add_f64 v[8:9], v[10:11], v[8:9]
; VI-NEXT:    v_cndmask_b32_e32 v9, v11, v9, vcc
; VI-NEXT:    v_cndmask_b32_e32 v8, v10, v8, vcc
; VI-NEXT:    v_ldexp_f64 v[8:9], v[8:9], v16
; VI-NEXT:    v_bfi_b32 v9, s6, v9, v1
; VI-NEXT:  .LBB13_8: ; %Flow51
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    v_cmp_ngt_f64_e64 s[4:5], |v[2:3]|, |v[6:7]|
; VI-NEXT:    ; implicit-def: $vgpr10_vgpr11
; VI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; VI-NEXT:    s_cbranch_execz .LBB13_10
; VI-NEXT:  ; %bb.9: ; %frem.else
; VI-NEXT:    v_cmp_eq_f64_e64 vcc, |v[2:3]|, |v[6:7]|
; VI-NEXT:    v_and_b32_e32 v10, 0x80000000, v3
; VI-NEXT:    v_cndmask_b32_e32 v11, v3, v10, vcc
; VI-NEXT:    v_cndmask_b32_e64 v10, v2, 0, vcc
; VI-NEXT:  .LBB13_10: ; %Flow46
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB13_16
; VI-NEXT:  ; %bb.11: ; %frem.compute
; VI-NEXT:    v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
; VI-NEXT:    v_frexp_exp_i32_f64_e32 v17, v[6:7]
; VI-NEXT:    v_frexp_exp_i32_f64_e32 v16, v[2:3]
; VI-NEXT:    v_ldexp_f64 v[14:15], v[10:11], 26
; VI-NEXT:    v_frexp_mant_f64_e64 v[10:11], |v[6:7]|
; VI-NEXT:    v_add_u32_e32 v18, vcc, -1, v17
; VI-NEXT:    v_not_b32_e32 v12, v18
; VI-NEXT:    v_add_u32_e32 v19, vcc, v12, v16
; VI-NEXT:    v_ldexp_f64 v[10:11], v[10:11], 1
; VI-NEXT:    v_div_scale_f64 v[12:13], s[6:7], v[10:11], v[10:11], 1.0
; VI-NEXT:    v_rcp_f64_e32 v[20:21], v[12:13]
; VI-NEXT:    v_fma_f64 v[22:23], -v[12:13], v[20:21], 1.0
; VI-NEXT:    v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21]
; VI-NEXT:    v_fma_f64 v[22:23], -v[12:13], v[20:21], 1.0
; VI-NEXT:    v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21]
; VI-NEXT:    v_div_scale_f64 v[22:23], vcc, 1.0, v[10:11], 1.0
; VI-NEXT:    v_mul_f64 v[24:25], v[22:23], v[20:21]
; VI-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[24:25], v[22:23]
; VI-NEXT:    s_nop 1
; VI-NEXT:    v_div_fmas_f64 v[12:13], v[12:13], v[20:21], v[24:25]
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v19
; VI-NEXT:    v_div_fixup_f64 v[12:13], v[12:13], v[10:11], 1.0
; VI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; VI-NEXT:    s_cbranch_execz .LBB13_15
; VI-NEXT:  ; %bb.12: ; %frem.loop_body.preheader
; VI-NEXT:    v_sub_u32_e32 v16, vcc, v16, v17
; VI-NEXT:    v_add_u32_e32 v19, vcc, 26, v16
; VI-NEXT:    s_mov_b64 s[8:9], 0
; VI-NEXT:  .LBB13_13: ; %frem.loop_body
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v17, v15
; VI-NEXT:    v_mov_b32_e32 v16, v14
; VI-NEXT:    v_mul_f64 v[14:15], v[16:17], v[12:13]
; VI-NEXT:    v_rndne_f64_e32 v[14:15], v[14:15]
; VI-NEXT:    v_fma_f64 v[14:15], -v[14:15], v[10:11], v[16:17]
; VI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[14:15]
; VI-NEXT:    v_add_f64 v[20:21], v[14:15], v[10:11]
; VI-NEXT:    v_cndmask_b32_e32 v15, v15, v21, vcc
; VI-NEXT:    v_cndmask_b32_e32 v14, v14, v20, vcc
; VI-NEXT:    v_ldexp_f64 v[14:15], v[14:15], 26
; VI-NEXT:    v_subrev_u32_e32 v19, vcc, 26, v19
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v19
; VI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; VI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; VI-NEXT:    s_cbranch_execnz .LBB13_13
; VI-NEXT:  ; %bb.14: ; %Flow
; VI-NEXT:    s_or_b64 exec, exec, s[8:9]
; VI-NEXT:    v_mov_b32_e32 v14, v16
; VI-NEXT:    v_mov_b32_e32 v15, v17
; VI-NEXT:  .LBB13_15: ; %Flow45
; VI-NEXT:    s_or_b64 exec, exec, s[6:7]
; VI-NEXT:    v_subrev_u32_e32 v16, vcc, 25, v19
; VI-NEXT:    v_ldexp_f64 v[14:15], v[14:15], v16
; VI-NEXT:    s_brev_b32 s6, -2
; VI-NEXT:    v_mul_f64 v[12:13], v[14:15], v[12:13]
; VI-NEXT:    v_rndne_f64_e32 v[12:13], v[12:13]
; VI-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[10:11], v[14:15]
; VI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[12:13]
; VI-NEXT:    v_add_f64 v[10:11], v[12:13], v[10:11]
; VI-NEXT:    v_cndmask_b32_e32 v11, v13, v11, vcc
; VI-NEXT:    v_cndmask_b32_e32 v10, v12, v10, vcc
; VI-NEXT:    v_ldexp_f64 v[10:11], v[10:11], v18
; VI-NEXT:    v_bfi_b32 v11, s6, v11, v3
; VI-NEXT:  .LBB13_16: ; %Flow47
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_mov_b32 s4, 0
; VI-NEXT:    s_mov_b32 s5, 0x7ff00000
; VI-NEXT:    v_cmp_lg_f64_e32 vcc, 0, v[4:5]
; VI-NEXT:    v_cmp_nge_f64_e64 s[6:7], |v[0:1]|, s[4:5]
; VI-NEXT:    v_mov_b32_e32 v4, 0x7ff80000
; VI-NEXT:    v_cmp_nge_f64_e64 s[4:5], |v[2:3]|, s[4:5]
; VI-NEXT:    s_and_b64 vcc, s[6:7], vcc
; VI-NEXT:    v_cndmask_b32_e32 v0, 0, v8, vcc
; VI-NEXT:    v_cndmask_b32_e32 v1, v4, v9, vcc
; VI-NEXT:    v_cmp_lg_f64_e32 vcc, 0, v[6:7]
; VI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; VI-NEXT:    v_cndmask_b32_e32 v2, 0, v10, vcc
; VI-NEXT:    v_cndmask_b32_e32 v3, v4, v11, vcc
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: frem_v2f64:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ngt_f64_e64 s[4:5], |v[0:1]|, |v[4:5]|
; GFX9-NEXT:    ; implicit-def: $vgpr8_vgpr9
; GFX9-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; GFX9-NEXT:    s_cbranch_execz .LBB13_2
; GFX9-NEXT:  ; %bb.1: ; %frem.else16
; GFX9-NEXT:    v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[4:5]|
; GFX9-NEXT:    v_and_b32_e32 v8, 0x80000000, v1
; GFX9-NEXT:    v_cndmask_b32_e32 v9, v1, v8, vcc
; GFX9-NEXT:    v_cndmask_b32_e64 v8, v0, 0, vcc
; GFX9-NEXT:  .LBB13_2: ; %Flow50
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB13_8
; GFX9-NEXT:  ; %bb.3: ; %frem.compute15
; GFX9-NEXT:    v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
; GFX9-NEXT:    v_frexp_exp_i32_f64_e32 v15, v[4:5]
; GFX9-NEXT:    v_frexp_exp_i32_f64_e32 v14, v[0:1]
; GFX9-NEXT:    v_ldexp_f64 v[12:13], v[8:9], 26
; GFX9-NEXT:    v_frexp_mant_f64_e64 v[8:9], |v[4:5]|
; GFX9-NEXT:    v_add_u32_e32 v16, -1, v15
; GFX9-NEXT:    v_xad_u32 v17, v16, -1, v14
; GFX9-NEXT:    v_ldexp_f64 v[8:9], v[8:9], 1
; GFX9-NEXT:    v_div_scale_f64 v[10:11], s[6:7], v[8:9], v[8:9], 1.0
; GFX9-NEXT:    v_rcp_f64_e32 v[18:19], v[10:11]
; GFX9-NEXT:    v_fma_f64 v[20:21], -v[10:11], v[18:19], 1.0
; GFX9-NEXT:    v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
; GFX9-NEXT:    v_fma_f64 v[20:21], -v[10:11], v[18:19], 1.0
; GFX9-NEXT:    v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
; GFX9-NEXT:    v_div_scale_f64 v[20:21], vcc, 1.0, v[8:9], 1.0
; GFX9-NEXT:    v_mul_f64 v[22:23], v[20:21], v[18:19]
; GFX9-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[22:23], v[20:21]
; GFX9-NEXT:    s_nop 1
; GFX9-NEXT:    v_div_fmas_f64 v[10:11], v[10:11], v[18:19], v[22:23]
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v17
; GFX9-NEXT:    v_div_fixup_f64 v[10:11], v[10:11], v[8:9], 1.0
; GFX9-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; GFX9-NEXT:    s_cbranch_execz .LBB13_7
; GFX9-NEXT:  ; %bb.4: ; %frem.loop_body23.preheader
; GFX9-NEXT:    v_sub_u32_e32 v14, v14, v15
; GFX9-NEXT:    v_add_u32_e32 v17, 26, v14
; GFX9-NEXT:    s_mov_b64 s[8:9], 0
; GFX9-NEXT:  .LBB13_5: ; %frem.loop_body23
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v15, v13
; GFX9-NEXT:    v_mov_b32_e32 v14, v12
; GFX9-NEXT:    v_mul_f64 v[12:13], v[14:15], v[10:11]
; GFX9-NEXT:    v_subrev_u32_e32 v17, 26, v17
; GFX9-NEXT:    v_rndne_f64_e32 v[12:13], v[12:13]
; GFX9-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[8:9], v[14:15]
; GFX9-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[12:13]
; GFX9-NEXT:    v_add_f64 v[18:19], v[12:13], v[8:9]
; GFX9-NEXT:    v_cndmask_b32_e32 v13, v13, v19, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v12, v12, v18, vcc
; GFX9-NEXT:    v_ldexp_f64 v[12:13], v[12:13], 26
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v17
; GFX9-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; GFX9-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; GFX9-NEXT:    s_cbranch_execnz .LBB13_5
; GFX9-NEXT:  ; %bb.6: ; %Flow48
; GFX9-NEXT:    s_or_b64 exec, exec, s[8:9]
; GFX9-NEXT:    v_mov_b32_e32 v12, v14
; GFX9-NEXT:    v_mov_b32_e32 v13, v15
; GFX9-NEXT:  .LBB13_7: ; %Flow49
; GFX9-NEXT:    s_or_b64 exec, exec, s[6:7]
; GFX9-NEXT:    v_subrev_u32_e32 v14, 25, v17
; GFX9-NEXT:    v_ldexp_f64 v[12:13], v[12:13], v14
; GFX9-NEXT:    s_brev_b32 s6, -2
; GFX9-NEXT:    v_mul_f64 v[10:11], v[12:13], v[10:11]
; GFX9-NEXT:    v_rndne_f64_e32 v[10:11], v[10:11]
; GFX9-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[8:9], v[12:13]
; GFX9-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[10:11]
; GFX9-NEXT:    v_add_f64 v[8:9], v[10:11], v[8:9]
; GFX9-NEXT:    v_cndmask_b32_e32 v9, v11, v9, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v8, v10, v8, vcc
; GFX9-NEXT:    v_ldexp_f64 v[8:9], v[8:9], v16
; GFX9-NEXT:    v_bfi_b32 v9, s6, v9, v1
; GFX9-NEXT:  .LBB13_8: ; %Flow51
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    v_cmp_ngt_f64_e64 s[4:5], |v[2:3]|, |v[6:7]|
; GFX9-NEXT:    ; implicit-def: $vgpr10_vgpr11
; GFX9-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; GFX9-NEXT:    s_cbranch_execz .LBB13_10
; GFX9-NEXT:  ; %bb.9: ; %frem.else
; GFX9-NEXT:    v_cmp_eq_f64_e64 vcc, |v[2:3]|, |v[6:7]|
; GFX9-NEXT:    v_and_b32_e32 v10, 0x80000000, v3
; GFX9-NEXT:    v_cndmask_b32_e32 v11, v3, v10, vcc
; GFX9-NEXT:    v_cndmask_b32_e64 v10, v2, 0, vcc
; GFX9-NEXT:  .LBB13_10: ; %Flow46
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB13_16
; GFX9-NEXT:  ; %bb.11: ; %frem.compute
; GFX9-NEXT:    v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
; GFX9-NEXT:    v_frexp_exp_i32_f64_e32 v17, v[6:7]
; GFX9-NEXT:    v_frexp_exp_i32_f64_e32 v16, v[2:3]
; GFX9-NEXT:    v_ldexp_f64 v[14:15], v[10:11], 26
; GFX9-NEXT:    v_frexp_mant_f64_e64 v[10:11], |v[6:7]|
; GFX9-NEXT:    v_add_u32_e32 v18, -1, v17
; GFX9-NEXT:    v_xad_u32 v19, v18, -1, v16
; GFX9-NEXT:    v_ldexp_f64 v[10:11], v[10:11], 1
; GFX9-NEXT:    v_div_scale_f64 v[12:13], s[6:7], v[10:11], v[10:11], 1.0
; GFX9-NEXT:    v_rcp_f64_e32 v[20:21], v[12:13]
; GFX9-NEXT:    v_fma_f64 v[22:23], -v[12:13], v[20:21], 1.0
; GFX9-NEXT:    v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21]
; GFX9-NEXT:    v_fma_f64 v[22:23], -v[12:13], v[20:21], 1.0
; GFX9-NEXT:    v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21]
; GFX9-NEXT:    v_div_scale_f64 v[22:23], vcc, 1.0, v[10:11], 1.0
; GFX9-NEXT:    v_mul_f64 v[24:25], v[22:23], v[20:21]
; GFX9-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[24:25], v[22:23]
; GFX9-NEXT:    s_nop 1
; GFX9-NEXT:    v_div_fmas_f64 v[12:13], v[12:13], v[20:21], v[24:25]
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v19
; GFX9-NEXT:    v_div_fixup_f64 v[12:13], v[12:13], v[10:11], 1.0
; GFX9-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; GFX9-NEXT:    s_cbranch_execz .LBB13_15
; GFX9-NEXT:  ; %bb.12: ; %frem.loop_body.preheader
; GFX9-NEXT:    v_sub_u32_e32 v16, v16, v17
; GFX9-NEXT:    v_add_u32_e32 v19, 26, v16
; GFX9-NEXT:    s_mov_b64 s[8:9], 0
; GFX9-NEXT:  .LBB13_13: ; %frem.loop_body
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v17, v15
; GFX9-NEXT:    v_mov_b32_e32 v16, v14
; GFX9-NEXT:    v_mul_f64 v[14:15], v[16:17], v[12:13]
; GFX9-NEXT:    v_subrev_u32_e32 v19, 26, v19
; GFX9-NEXT:    v_rndne_f64_e32 v[14:15], v[14:15]
; GFX9-NEXT:    v_fma_f64 v[14:15], -v[14:15], v[10:11], v[16:17]
; GFX9-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[14:15]
; GFX9-NEXT:    v_add_f64 v[20:21], v[14:15], v[10:11]
; GFX9-NEXT:    v_cndmask_b32_e32 v15, v15, v21, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v14, v14, v20, vcc
; GFX9-NEXT:    v_ldexp_f64 v[14:15], v[14:15], 26
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v19
; GFX9-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; GFX9-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; GFX9-NEXT:    s_cbranch_execnz .LBB13_13
; GFX9-NEXT:  ; %bb.14: ; %Flow
; GFX9-NEXT:    s_or_b64 exec, exec, s[8:9]
; GFX9-NEXT:    v_mov_b32_e32 v14, v16
; GFX9-NEXT:    v_mov_b32_e32 v15, v17
; GFX9-NEXT:  .LBB13_15: ; %Flow45
; GFX9-NEXT:    s_or_b64 exec, exec, s[6:7]
; GFX9-NEXT:    v_subrev_u32_e32 v16, 25, v19
; GFX9-NEXT:    v_ldexp_f64 v[14:15], v[14:15], v16
; GFX9-NEXT:    s_brev_b32 s6, -2
; GFX9-NEXT:    v_mul_f64 v[12:13], v[14:15], v[12:13]
; GFX9-NEXT:    v_rndne_f64_e32 v[12:13], v[12:13]
; GFX9-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[10:11], v[14:15]
; GFX9-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[12:13]
; GFX9-NEXT:    v_add_f64 v[10:11], v[12:13], v[10:11]
; GFX9-NEXT:    v_cndmask_b32_e32 v11, v13, v11, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v10, v12, v10, vcc
; GFX9-NEXT:    v_ldexp_f64 v[10:11], v[10:11], v18
; GFX9-NEXT:    v_bfi_b32 v11, s6, v11, v3
; GFX9-NEXT:  .LBB13_16: ; %Flow47
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_mov_b32 s4, 0
; GFX9-NEXT:    s_mov_b32 s5, 0x7ff00000
; GFX9-NEXT:    v_cmp_lg_f64_e32 vcc, 0, v[4:5]
; GFX9-NEXT:    v_cmp_nge_f64_e64 s[6:7], |v[0:1]|, s[4:5]
; GFX9-NEXT:    v_mov_b32_e32 v4, 0x7ff80000
; GFX9-NEXT:    v_cmp_nge_f64_e64 s[4:5], |v[2:3]|, s[4:5]
; GFX9-NEXT:    s_and_b64 vcc, s[6:7], vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v0, 0, v8, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v4, v9, vcc
; GFX9-NEXT:    v_cmp_lg_f64_e32 vcc, 0, v[6:7]
; GFX9-NEXT:    s_and_b64 vcc, s[4:5], vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v2, 0, v10, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v4, v11, vcc
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: frem_v2f64:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cmp_ngt_f64_e64 s4, |v[0:1]|, |v[4:5]|
; GFX10-NEXT:    ; implicit-def: $vgpr8_vgpr9
; GFX10-NEXT:    s_and_saveexec_b32 s5, s4
; GFX10-NEXT:    s_xor_b32 s4, exec_lo, s5
; GFX10-NEXT:    s_cbranch_execz .LBB13_2
; GFX10-NEXT:  ; %bb.1: ; %frem.else16
; GFX10-NEXT:    v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[4:5]|
; GFX10-NEXT:    v_and_b32_e32 v8, 0x80000000, v1
; GFX10-NEXT:    v_cndmask_b32_e32 v9, v1, v8, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e64 v8, v0, 0, vcc_lo
; GFX10-NEXT:  .LBB13_2: ; %Flow50
; GFX10-NEXT:    s_andn2_saveexec_b32 s4, s4
; GFX10-NEXT:    s_cbranch_execz .LBB13_8
; GFX10-NEXT:  ; %bb.3: ; %frem.compute15
; GFX10-NEXT:    v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
; GFX10-NEXT:    v_frexp_exp_i32_f64_e32 v15, v[4:5]
; GFX10-NEXT:    v_frexp_exp_i32_f64_e32 v14, v[0:1]
; GFX10-NEXT:    v_ldexp_f64 v[12:13], v[8:9], 26
; GFX10-NEXT:    v_frexp_mant_f64_e64 v[8:9], |v[4:5]|
; GFX10-NEXT:    v_add_nc_u32_e32 v16, -1, v15
; GFX10-NEXT:    v_xad_u32 v17, v16, -1, v14
; GFX10-NEXT:    v_ldexp_f64 v[8:9], v[8:9], 1
; GFX10-NEXT:    v_div_scale_f64 v[10:11], s5, v[8:9], v[8:9], 1.0
; GFX10-NEXT:    v_rcp_f64_e32 v[18:19], v[10:11]
; GFX10-NEXT:    v_fma_f64 v[20:21], -v[10:11], v[18:19], 1.0
; GFX10-NEXT:    v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
; GFX10-NEXT:    v_fma_f64 v[20:21], -v[10:11], v[18:19], 1.0
; GFX10-NEXT:    v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
; GFX10-NEXT:    v_div_scale_f64 v[20:21], vcc_lo, 1.0, v[8:9], 1.0
; GFX10-NEXT:    v_mul_f64 v[22:23], v[20:21], v[18:19]
; GFX10-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[22:23], v[20:21]
; GFX10-NEXT:    v_div_fmas_f64 v[10:11], v[10:11], v[18:19], v[22:23]
; GFX10-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 26, v17
; GFX10-NEXT:    v_div_fixup_f64 v[10:11], v[10:11], v[8:9], 1.0
; GFX10-NEXT:    s_and_saveexec_b32 s5, vcc_lo
; GFX10-NEXT:    s_cbranch_execz .LBB13_7
; GFX10-NEXT:  ; %bb.4: ; %frem.loop_body23.preheader
; GFX10-NEXT:    v_sub_nc_u32_e32 v14, v14, v15
; GFX10-NEXT:    s_mov_b32 s6, 0
; GFX10-NEXT:    v_add_nc_u32_e32 v17, 26, v14
; GFX10-NEXT:  .LBB13_5: ; %frem.loop_body23
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v15, v13
; GFX10-NEXT:    v_mov_b32_e32 v14, v12
; GFX10-NEXT:    v_subrev_nc_u32_e32 v17, 26, v17
; GFX10-NEXT:    v_mul_f64 v[12:13], v[14:15], v[10:11]
; GFX10-NEXT:    v_rndne_f64_e32 v[12:13], v[12:13]
; GFX10-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[8:9], v[14:15]
; GFX10-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
; GFX10-NEXT:    v_add_f64 v[18:19], v[12:13], v[8:9]
; GFX10-NEXT:    v_cndmask_b32_e32 v13, v13, v19, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v12, v12, v18, vcc_lo
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v17
; GFX10-NEXT:    v_ldexp_f64 v[12:13], v[12:13], 26
; GFX10-NEXT:    s_or_b32 s6, vcc_lo, s6
; GFX10-NEXT:    s_andn2_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    s_cbranch_execnz .LBB13_5
; GFX10-NEXT:  ; %bb.6: ; %Flow48
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    v_mov_b32_e32 v12, v14
; GFX10-NEXT:    v_mov_b32_e32 v13, v15
; GFX10-NEXT:  .LBB13_7: ; %Flow49
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s5
; GFX10-NEXT:    v_subrev_nc_u32_e32 v14, 25, v17
; GFX10-NEXT:    v_ldexp_f64 v[12:13], v[12:13], v14
; GFX10-NEXT:    v_mul_f64 v[10:11], v[12:13], v[10:11]
; GFX10-NEXT:    v_rndne_f64_e32 v[10:11], v[10:11]
; GFX10-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[8:9], v[12:13]
; GFX10-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[10:11]
; GFX10-NEXT:    v_add_f64 v[8:9], v[10:11], v[8:9]
; GFX10-NEXT:    v_cndmask_b32_e32 v9, v11, v9, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v8, v10, v8, vcc_lo
; GFX10-NEXT:    v_ldexp_f64 v[8:9], v[8:9], v16
; GFX10-NEXT:    v_bfi_b32 v9, 0x7fffffff, v9, v1
; GFX10-NEXT:  .LBB13_8: ; %Flow51
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT:    v_cmp_ngt_f64_e64 s4, |v[2:3]|, |v[6:7]|
; GFX10-NEXT:    ; implicit-def: $vgpr10_vgpr11
; GFX10-NEXT:    s_and_saveexec_b32 s5, s4
; GFX10-NEXT:    s_xor_b32 s4, exec_lo, s5
; GFX10-NEXT:    s_cbranch_execz .LBB13_10
; GFX10-NEXT:  ; %bb.9: ; %frem.else
; GFX10-NEXT:    v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
; GFX10-NEXT:    v_and_b32_e32 v10, 0x80000000, v3
; GFX10-NEXT:    v_cndmask_b32_e32 v11, v3, v10, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e64 v10, v2, 0, vcc_lo
; GFX10-NEXT:  .LBB13_10: ; %Flow46
; GFX10-NEXT:    s_andn2_saveexec_b32 s4, s4
; GFX10-NEXT:    s_cbranch_execz .LBB13_16
; GFX10-NEXT:  ; %bb.11: ; %frem.compute
; GFX10-NEXT:    v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
; GFX10-NEXT:    v_frexp_exp_i32_f64_e32 v17, v[6:7]
; GFX10-NEXT:    v_frexp_exp_i32_f64_e32 v16, v[2:3]
; GFX10-NEXT:    v_ldexp_f64 v[14:15], v[10:11], 26
; GFX10-NEXT:    v_frexp_mant_f64_e64 v[10:11], |v[6:7]|
; GFX10-NEXT:    v_add_nc_u32_e32 v18, -1, v17
; GFX10-NEXT:    v_xad_u32 v19, v18, -1, v16
; GFX10-NEXT:    v_ldexp_f64 v[10:11], v[10:11], 1
; GFX10-NEXT:    v_div_scale_f64 v[12:13], s5, v[10:11], v[10:11], 1.0
; GFX10-NEXT:    v_rcp_f64_e32 v[20:21], v[12:13]
; GFX10-NEXT:    v_fma_f64 v[22:23], -v[12:13], v[20:21], 1.0
; GFX10-NEXT:    v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21]
; GFX10-NEXT:    v_fma_f64 v[22:23], -v[12:13], v[20:21], 1.0
; GFX10-NEXT:    v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21]
; GFX10-NEXT:    v_div_scale_f64 v[22:23], vcc_lo, 1.0, v[10:11], 1.0
; GFX10-NEXT:    v_mul_f64 v[24:25], v[22:23], v[20:21]
; GFX10-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[24:25], v[22:23]
; GFX10-NEXT:    v_div_fmas_f64 v[12:13], v[12:13], v[20:21], v[24:25]
; GFX10-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 26, v19
; GFX10-NEXT:    v_div_fixup_f64 v[12:13], v[12:13], v[10:11], 1.0
; GFX10-NEXT:    s_and_saveexec_b32 s5, vcc_lo
; GFX10-NEXT:    s_cbranch_execz .LBB13_15
; GFX10-NEXT:  ; %bb.12: ; %frem.loop_body.preheader
; GFX10-NEXT:    v_sub_nc_u32_e32 v16, v16, v17
; GFX10-NEXT:    s_mov_b32 s6, 0
; GFX10-NEXT:    v_add_nc_u32_e32 v19, 26, v16
; GFX10-NEXT:  .LBB13_13: ; %frem.loop_body
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v17, v15
; GFX10-NEXT:    v_mov_b32_e32 v16, v14
; GFX10-NEXT:    v_subrev_nc_u32_e32 v19, 26, v19
; GFX10-NEXT:    v_mul_f64 v[14:15], v[16:17], v[12:13]
; GFX10-NEXT:    v_rndne_f64_e32 v[14:15], v[14:15]
; GFX10-NEXT:    v_fma_f64 v[14:15], -v[14:15], v[10:11], v[16:17]
; GFX10-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[14:15]
; GFX10-NEXT:    v_add_f64 v[20:21], v[14:15], v[10:11]
; GFX10-NEXT:    v_cndmask_b32_e32 v15, v15, v21, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v14, v14, v20, vcc_lo
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v19
; GFX10-NEXT:    v_ldexp_f64 v[14:15], v[14:15], 26
; GFX10-NEXT:    s_or_b32 s6, vcc_lo, s6
; GFX10-NEXT:    s_andn2_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    s_cbranch_execnz .LBB13_13
; GFX10-NEXT:  ; %bb.14: ; %Flow
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    v_mov_b32_e32 v14, v16
; GFX10-NEXT:    v_mov_b32_e32 v15, v17
; GFX10-NEXT:  .LBB13_15: ; %Flow45
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s5
; GFX10-NEXT:    v_subrev_nc_u32_e32 v16, 25, v19
; GFX10-NEXT:    v_ldexp_f64 v[14:15], v[14:15], v16
; GFX10-NEXT:    v_mul_f64 v[12:13], v[14:15], v[12:13]
; GFX10-NEXT:    v_rndne_f64_e32 v[12:13], v[12:13]
; GFX10-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[10:11], v[14:15]
; GFX10-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
; GFX10-NEXT:    v_add_f64 v[10:11], v[12:13], v[10:11]
; GFX10-NEXT:    v_cndmask_b32_e32 v11, v13, v11, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v10, v12, v10, vcc_lo
; GFX10-NEXT:    v_ldexp_f64 v[10:11], v[10:11], v18
; GFX10-NEXT:    v_bfi_b32 v11, 0x7fffffff, v11, v3
; GFX10-NEXT:  .LBB13_16: ; %Flow47
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT:    v_cmp_lg_f64_e32 vcc_lo, 0, v[4:5]
; GFX10-NEXT:    v_cmp_nge_f64_e64 s4, |v[0:1]|, 0x7ff00000
; GFX10-NEXT:    s_and_b32 vcc_lo, s4, vcc_lo
; GFX10-NEXT:    v_cmp_nge_f64_e64 s4, |v[2:3]|, 0x7ff00000
; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0, v8, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v1, 0x7ff80000, v9, vcc_lo
; GFX10-NEXT:    v_cmp_lg_f64_e32 vcc_lo, 0, v[6:7]
; GFX10-NEXT:    s_and_b32 vcc_lo, s4, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v2, 0, v10, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v3, 0x7ff80000, v11, vcc_lo
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: frem_v2f64:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cmp_ngt_f64_e64 s0, |v[0:1]|, |v[4:5]|
; GFX11-NEXT:    ; implicit-def: $vgpr8_vgpr9
; GFX11-NEXT:    s_and_saveexec_b32 s1, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX11-NEXT:    s_cbranch_execz .LBB13_2
; GFX11-NEXT:  ; %bb.1: ; %frem.else16
; GFX11-NEXT:    v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[4:5]|
; GFX11-NEXT:    v_and_b32_e32 v8, 0x80000000, v1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_cndmask_b32_e32 v9, v1, v8, vcc_lo
; GFX11-NEXT:    v_cndmask_b32_e64 v8, v0, 0, vcc_lo
; GFX11-NEXT:  .LBB13_2: ; %Flow50
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB13_8
; GFX11-NEXT:  ; %bb.3: ; %frem.compute15
; GFX11-NEXT:    v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
; GFX11-NEXT:    v_frexp_exp_i32_f64_e32 v15, v[4:5]
; GFX11-NEXT:    v_frexp_exp_i32_f64_e32 v14, v[0:1]
; GFX11-NEXT:    s_mov_b32 s1, exec_lo
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_ldexp_f64 v[12:13], v[8:9], 26
; GFX11-NEXT:    v_frexp_mant_f64_e64 v[8:9], |v[4:5]|
; GFX11-NEXT:    v_add_nc_u32_e32 v16, -1, v15
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_xad_u32 v17, v16, -1, v14
; GFX11-NEXT:    v_ldexp_f64 v[8:9], v[8:9], 1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_div_scale_f64 v[10:11], null, v[8:9], v[8:9], 1.0
; GFX11-NEXT:    v_rcp_f64_e32 v[18:19], v[10:11]
; GFX11-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT:    v_fma_f64 v[20:21], -v[10:11], v[18:19], 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
; GFX11-NEXT:    v_fma_f64 v[20:21], -v[10:11], v[18:19], 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
; GFX11-NEXT:    v_div_scale_f64 v[20:21], vcc_lo, 1.0, v[8:9], 1.0
; GFX11-NEXT:    v_mul_f64 v[22:23], v[20:21], v[18:19]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[22:23], v[20:21]
; GFX11-NEXT:    v_div_fmas_f64 v[10:11], v[10:11], v[18:19], v[22:23]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_div_fixup_f64 v[10:11], v[10:11], v[8:9], 1.0
; GFX11-NEXT:    v_cmpx_lt_i32_e32 26, v17
; GFX11-NEXT:    s_cbranch_execz .LBB13_7
; GFX11-NEXT:  ; %bb.4: ; %frem.loop_body23.preheader
; GFX11-NEXT:    v_sub_nc_u32_e32 v14, v14, v15
; GFX11-NEXT:    s_mov_b32 s2, 0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_add_nc_u32_e32 v17, 26, v14
; GFX11-NEXT:    .p2align 6
; GFX11-NEXT:  .LBB13_5: ; %frem.loop_body23
; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT:    v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12
; GFX11-NEXT:    v_subrev_nc_u32_e32 v17, 26, v17
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_mul_f64 v[12:13], v[14:15], v[10:11]
; GFX11-NEXT:    v_rndne_f64_e32 v[12:13], v[12:13]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[8:9], v[14:15]
; GFX11-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
; GFX11-NEXT:    v_add_f64 v[18:19], v[12:13], v[8:9]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT:    v_dual_cndmask_b32 v13, v13, v19 :: v_dual_cndmask_b32 v12, v12, v18
; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v17
; GFX11-NEXT:    v_ldexp_f64 v[12:13], v[12:13], 26
; GFX11-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX11-NEXT:    s_cbranch_execnz .LBB13_5
; GFX11-NEXT:  ; %bb.6: ; %Flow48
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX11-NEXT:    v_dual_mov_b32 v12, v14 :: v_dual_mov_b32 v13, v15
; GFX11-NEXT:  .LBB13_7: ; %Flow49
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX11-NEXT:    v_subrev_nc_u32_e32 v14, 25, v17
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_ldexp_f64 v[12:13], v[12:13], v14
; GFX11-NEXT:    v_mul_f64 v[10:11], v[12:13], v[10:11]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_rndne_f64_e32 v[10:11], v[10:11]
; GFX11-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[8:9], v[12:13]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[10:11]
; GFX11-NEXT:    v_add_f64 v[8:9], v[10:11], v[8:9]
; GFX11-NEXT:    v_dual_cndmask_b32 v9, v11, v9 :: v_dual_cndmask_b32 v8, v10, v8
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_ldexp_f64 v[8:9], v[8:9], v16
; GFX11-NEXT:    v_bfi_b32 v9, 0x7fffffff, v9, v1
; GFX11-NEXT:  .LBB13_8: ; %Flow51
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    v_cmp_ngt_f64_e64 s0, |v[2:3]|, |v[6:7]|
; GFX11-NEXT:    ; implicit-def: $vgpr10_vgpr11
; GFX11-NEXT:    s_and_saveexec_b32 s1, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX11-NEXT:    s_cbranch_execz .LBB13_10
; GFX11-NEXT:  ; %bb.9: ; %frem.else
; GFX11-NEXT:    v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
; GFX11-NEXT:    v_and_b32_e32 v10, 0x80000000, v3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_cndmask_b32_e32 v11, v3, v10, vcc_lo
; GFX11-NEXT:    v_cndmask_b32_e64 v10, v2, 0, vcc_lo
; GFX11-NEXT:  .LBB13_10: ; %Flow46
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB13_16
; GFX11-NEXT:  ; %bb.11: ; %frem.compute
; GFX11-NEXT:    v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
; GFX11-NEXT:    v_frexp_exp_i32_f64_e32 v17, v[6:7]
; GFX11-NEXT:    v_frexp_exp_i32_f64_e32 v16, v[2:3]
; GFX11-NEXT:    s_mov_b32 s1, exec_lo
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_ldexp_f64 v[14:15], v[10:11], 26
; GFX11-NEXT:    v_frexp_mant_f64_e64 v[10:11], |v[6:7]|
; GFX11-NEXT:    v_add_nc_u32_e32 v18, -1, v17
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_xad_u32 v19, v18, -1, v16
; GFX11-NEXT:    v_ldexp_f64 v[10:11], v[10:11], 1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_div_scale_f64 v[12:13], null, v[10:11], v[10:11], 1.0
; GFX11-NEXT:    v_rcp_f64_e32 v[20:21], v[12:13]
; GFX11-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT:    v_fma_f64 v[22:23], -v[12:13], v[20:21], 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21]
; GFX11-NEXT:    v_fma_f64 v[22:23], -v[12:13], v[20:21], 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21]
; GFX11-NEXT:    v_div_scale_f64 v[22:23], vcc_lo, 1.0, v[10:11], 1.0
; GFX11-NEXT:    v_mul_f64 v[24:25], v[22:23], v[20:21]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[24:25], v[22:23]
; GFX11-NEXT:    v_div_fmas_f64 v[12:13], v[12:13], v[20:21], v[24:25]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_div_fixup_f64 v[12:13], v[12:13], v[10:11], 1.0
; GFX11-NEXT:    v_cmpx_lt_i32_e32 26, v19
; GFX11-NEXT:    s_cbranch_execz .LBB13_15
; GFX11-NEXT:  ; %bb.12: ; %frem.loop_body.preheader
; GFX11-NEXT:    v_sub_nc_u32_e32 v16, v16, v17
; GFX11-NEXT:    s_mov_b32 s2, 0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_add_nc_u32_e32 v19, 26, v16
; GFX11-NEXT:    .p2align 6
; GFX11-NEXT:  .LBB13_13: ; %frem.loop_body
; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT:    v_dual_mov_b32 v17, v15 :: v_dual_mov_b32 v16, v14
; GFX11-NEXT:    v_subrev_nc_u32_e32 v19, 26, v19
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_mul_f64 v[14:15], v[16:17], v[12:13]
; GFX11-NEXT:    v_rndne_f64_e32 v[14:15], v[14:15]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f64 v[14:15], -v[14:15], v[10:11], v[16:17]
; GFX11-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[14:15]
; GFX11-NEXT:    v_add_f64 v[20:21], v[14:15], v[10:11]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT:    v_dual_cndmask_b32 v15, v15, v21 :: v_dual_cndmask_b32 v14, v14, v20
; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v19
; GFX11-NEXT:    v_ldexp_f64 v[14:15], v[14:15], 26
; GFX11-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX11-NEXT:    s_cbranch_execnz .LBB13_13
; GFX11-NEXT:  ; %bb.14: ; %Flow
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX11-NEXT:    v_dual_mov_b32 v14, v16 :: v_dual_mov_b32 v15, v17
; GFX11-NEXT:  .LBB13_15: ; %Flow45
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX11-NEXT:    v_subrev_nc_u32_e32 v16, 25, v19
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_ldexp_f64 v[14:15], v[14:15], v16
; GFX11-NEXT:    v_mul_f64 v[12:13], v[14:15], v[12:13]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_rndne_f64_e32 v[12:13], v[12:13]
; GFX11-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[10:11], v[14:15]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
; GFX11-NEXT:    v_add_f64 v[10:11], v[12:13], v[10:11]
; GFX11-NEXT:    v_dual_cndmask_b32 v11, v13, v11 :: v_dual_cndmask_b32 v10, v12, v10
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_ldexp_f64 v[10:11], v[10:11], v18
; GFX11-NEXT:    v_bfi_b32 v11, 0x7fffffff, v11, v3
; GFX11-NEXT:  .LBB13_16: ; %Flow47
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    v_cmp_lg_f64_e32 vcc_lo, 0, v[4:5]
; GFX11-NEXT:    v_cmp_nge_f64_e64 s0, |v[0:1]|, 0x7ff00000
; GFX11-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX11-NEXT:    v_cmp_nge_f64_e64 s0, |v[2:3]|, 0x7ff00000
; GFX11-NEXT:    v_dual_cndmask_b32 v0, 0, v8 :: v_dual_cndmask_b32 v1, 0x7ff80000, v9
; GFX11-NEXT:    v_cmp_lg_f64_e32 vcc_lo, 0, v[6:7]
; GFX11-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX11-NEXT:    v_dual_cndmask_b32 v2, 0, v10 :: v_dual_cndmask_b32 v3, 0x7ff80000, v11
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-LABEL: frem_v2f64:
; GFX1150:       ; %bb.0:
; GFX1150-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-NEXT:    v_cmp_ngt_f64_e64 s0, |v[0:1]|, |v[4:5]|
; GFX1150-NEXT:    ; implicit-def: $vgpr8_vgpr9
; GFX1150-NEXT:    s_and_saveexec_b32 s1, s0
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX1150-NEXT:    s_cbranch_execz .LBB13_2
; GFX1150-NEXT:  ; %bb.1: ; %frem.else16
; GFX1150-NEXT:    v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[4:5]|
; GFX1150-NEXT:    v_and_b32_e32 v8, 0x80000000, v1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_cndmask_b32_e32 v9, v1, v8, vcc_lo
; GFX1150-NEXT:    v_cndmask_b32_e64 v8, v0, 0, vcc_lo
; GFX1150-NEXT:  .LBB13_2: ; %Flow50
; GFX1150-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1150-NEXT:    s_cbranch_execz .LBB13_8
; GFX1150-NEXT:  ; %bb.3: ; %frem.compute15
; GFX1150-NEXT:    v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
; GFX1150-NEXT:    v_frexp_exp_i32_f64_e32 v15, v[4:5]
; GFX1150-NEXT:    v_frexp_exp_i32_f64_e32 v14, v[0:1]
; GFX1150-NEXT:    s_mov_b32 s1, exec_lo
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1150-NEXT:    v_ldexp_f64 v[12:13], v[8:9], 26
; GFX1150-NEXT:    v_frexp_mant_f64_e64 v[8:9], |v[4:5]|
; GFX1150-NEXT:    v_add_nc_u32_e32 v16, -1, v15
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_xad_u32 v17, v16, -1, v14
; GFX1150-NEXT:    v_ldexp_f64 v[8:9], v[8:9], 1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_div_scale_f64 v[10:11], null, v[8:9], v[8:9], 1.0
; GFX1150-NEXT:    v_rcp_f64_e32 v[18:19], v[10:11]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[20:21], -v[10:11], v[18:19], 1.0
; GFX1150-NEXT:    v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[20:21], -v[10:11], v[18:19], 1.0
; GFX1150-NEXT:    v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
; GFX1150-NEXT:    v_div_scale_f64 v[20:21], vcc_lo, 1.0, v[8:9], 1.0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f64 v[22:23], v[20:21], v[18:19]
; GFX1150-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[22:23], v[20:21]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_div_fmas_f64 v[10:11], v[10:11], v[18:19], v[22:23]
; GFX1150-NEXT:    v_div_fixup_f64 v[10:11], v[10:11], v[8:9], 1.0
; GFX1150-NEXT:    v_cmpx_lt_i32_e32 26, v17
; GFX1150-NEXT:    s_cbranch_execz .LBB13_7
; GFX1150-NEXT:  ; %bb.4: ; %frem.loop_body23.preheader
; GFX1150-NEXT:    v_sub_nc_u32_e32 v14, v14, v15
; GFX1150-NEXT:    s_mov_b32 s2, 0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_add_nc_u32_e32 v17, 26, v14
; GFX1150-NEXT:    .p2align 6
; GFX1150-NEXT:  .LBB13_5: ; %frem.loop_body23
; GFX1150-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1150-NEXT:    v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12
; GFX1150-NEXT:    v_subrev_nc_u32_e32 v17, 26, v17
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f64 v[12:13], v[14:15], v[10:11]
; GFX1150-NEXT:    v_rndne_f64_e32 v[12:13], v[12:13]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[8:9], v[14:15]
; GFX1150-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
; GFX1150-NEXT:    v_add_f64 v[18:19], v[12:13], v[8:9]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-NEXT:    v_dual_cndmask_b32 v13, v13, v19 :: v_dual_cndmask_b32 v12, v12, v18
; GFX1150-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v17
; GFX1150-NEXT:    v_ldexp_f64 v[12:13], v[12:13], 26
; GFX1150-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1150-NEXT:    s_cbranch_execnz .LBB13_5
; GFX1150-NEXT:  ; %bb.6: ; %Flow48
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1150-NEXT:    v_dual_mov_b32 v12, v14 :: v_dual_mov_b32 v13, v15
; GFX1150-NEXT:  .LBB13_7: ; %Flow49
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1150-NEXT:    v_subrev_nc_u32_e32 v14, 25, v17
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f64 v[12:13], v[12:13], v14
; GFX1150-NEXT:    v_mul_f64 v[10:11], v[12:13], v[10:11]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_rndne_f64_e32 v[10:11], v[10:11]
; GFX1150-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[8:9], v[12:13]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[10:11]
; GFX1150-NEXT:    v_add_f64 v[8:9], v[10:11], v[8:9]
; GFX1150-NEXT:    v_dual_cndmask_b32 v9, v11, v9 :: v_dual_cndmask_b32 v8, v10, v8
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f64 v[8:9], v[8:9], v16
; GFX1150-NEXT:    v_bfi_b32 v9, 0x7fffffff, v9, v1
; GFX1150-NEXT:  .LBB13_8: ; %Flow51
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1150-NEXT:    v_cmp_ngt_f64_e64 s0, |v[2:3]|, |v[6:7]|
; GFX1150-NEXT:    ; implicit-def: $vgpr10_vgpr11
; GFX1150-NEXT:    s_and_saveexec_b32 s1, s0
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX1150-NEXT:    s_cbranch_execz .LBB13_10
; GFX1150-NEXT:  ; %bb.9: ; %frem.else
; GFX1150-NEXT:    v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
; GFX1150-NEXT:    v_and_b32_e32 v10, 0x80000000, v3
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_cndmask_b32_e32 v11, v3, v10, vcc_lo
; GFX1150-NEXT:    v_cndmask_b32_e64 v10, v2, 0, vcc_lo
; GFX1150-NEXT:  .LBB13_10: ; %Flow46
; GFX1150-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1150-NEXT:    s_cbranch_execz .LBB13_16
; GFX1150-NEXT:  ; %bb.11: ; %frem.compute
; GFX1150-NEXT:    v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
; GFX1150-NEXT:    v_frexp_exp_i32_f64_e32 v17, v[6:7]
; GFX1150-NEXT:    v_frexp_exp_i32_f64_e32 v16, v[2:3]
; GFX1150-NEXT:    s_mov_b32 s1, exec_lo
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1150-NEXT:    v_ldexp_f64 v[14:15], v[10:11], 26
; GFX1150-NEXT:    v_frexp_mant_f64_e64 v[10:11], |v[6:7]|
; GFX1150-NEXT:    v_add_nc_u32_e32 v18, -1, v17
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_xad_u32 v19, v18, -1, v16
; GFX1150-NEXT:    v_ldexp_f64 v[10:11], v[10:11], 1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_div_scale_f64 v[12:13], null, v[10:11], v[10:11], 1.0
; GFX1150-NEXT:    v_rcp_f64_e32 v[20:21], v[12:13]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[22:23], -v[12:13], v[20:21], 1.0
; GFX1150-NEXT:    v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[22:23], -v[12:13], v[20:21], 1.0
; GFX1150-NEXT:    v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21]
; GFX1150-NEXT:    v_div_scale_f64 v[22:23], vcc_lo, 1.0, v[10:11], 1.0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f64 v[24:25], v[22:23], v[20:21]
; GFX1150-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[24:25], v[22:23]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_div_fmas_f64 v[12:13], v[12:13], v[20:21], v[24:25]
; GFX1150-NEXT:    v_div_fixup_f64 v[12:13], v[12:13], v[10:11], 1.0
; GFX1150-NEXT:    v_cmpx_lt_i32_e32 26, v19
; GFX1150-NEXT:    s_cbranch_execz .LBB13_15
; GFX1150-NEXT:  ; %bb.12: ; %frem.loop_body.preheader
; GFX1150-NEXT:    v_sub_nc_u32_e32 v16, v16, v17
; GFX1150-NEXT:    s_mov_b32 s2, 0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_add_nc_u32_e32 v19, 26, v16
; GFX1150-NEXT:    .p2align 6
; GFX1150-NEXT:  .LBB13_13: ; %frem.loop_body
; GFX1150-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1150-NEXT:    v_dual_mov_b32 v17, v15 :: v_dual_mov_b32 v16, v14
; GFX1150-NEXT:    v_subrev_nc_u32_e32 v19, 26, v19
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f64 v[14:15], v[16:17], v[12:13]
; GFX1150-NEXT:    v_rndne_f64_e32 v[14:15], v[14:15]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[14:15], -v[14:15], v[10:11], v[16:17]
; GFX1150-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[14:15]
; GFX1150-NEXT:    v_add_f64 v[20:21], v[14:15], v[10:11]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-NEXT:    v_dual_cndmask_b32 v15, v15, v21 :: v_dual_cndmask_b32 v14, v14, v20
; GFX1150-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v19
; GFX1150-NEXT:    v_ldexp_f64 v[14:15], v[14:15], 26
; GFX1150-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1150-NEXT:    s_cbranch_execnz .LBB13_13
; GFX1150-NEXT:  ; %bb.14: ; %Flow
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1150-NEXT:    v_dual_mov_b32 v14, v16 :: v_dual_mov_b32 v15, v17
; GFX1150-NEXT:  .LBB13_15: ; %Flow45
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1150-NEXT:    v_subrev_nc_u32_e32 v16, 25, v19
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f64 v[14:15], v[14:15], v16
; GFX1150-NEXT:    v_mul_f64 v[12:13], v[14:15], v[12:13]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_rndne_f64_e32 v[12:13], v[12:13]
; GFX1150-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[10:11], v[14:15]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
; GFX1150-NEXT:    v_add_f64 v[10:11], v[12:13], v[10:11]
; GFX1150-NEXT:    v_dual_cndmask_b32 v11, v13, v11 :: v_dual_cndmask_b32 v10, v12, v10
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f64 v[10:11], v[10:11], v18
; GFX1150-NEXT:    v_bfi_b32 v11, 0x7fffffff, v11, v3
; GFX1150-NEXT:  .LBB13_16: ; %Flow47
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1150-NEXT:    v_cmp_lg_f64_e32 vcc_lo, 0, v[4:5]
; GFX1150-NEXT:    v_cmp_nge_f64_e64 s0, |v[0:1]|, 0x7ff00000
; GFX1150-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1150-NEXT:    v_cmp_nge_f64_e64 s0, |v[2:3]|, 0x7ff00000
; GFX1150-NEXT:    v_dual_cndmask_b32 v0, 0, v8 :: v_dual_cndmask_b32 v1, 0x7ff80000, v9
; GFX1150-NEXT:    v_cmp_lg_f64_e32 vcc_lo, 0, v[6:7]
; GFX1150-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1150-NEXT:    v_dual_cndmask_b32 v2, 0, v10 :: v_dual_cndmask_b32 v3, 0x7ff80000, v11
; GFX1150-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: frem_v2f64:
; GFX1200:       ; %bb.0:
; GFX1200-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT:    s_wait_expcnt 0x0
; GFX1200-NEXT:    s_wait_samplecnt 0x0
; GFX1200-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-NEXT:    s_wait_kmcnt 0x0
; GFX1200-NEXT:    v_cmp_ngt_f64_e64 s0, |v[0:1]|, |v[4:5]|
; GFX1200-NEXT:    ; implicit-def: $vgpr8_vgpr9
; GFX1200-NEXT:    s_and_saveexec_b32 s1, s0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX1200-NEXT:    s_cbranch_execz .LBB13_2
; GFX1200-NEXT:  ; %bb.1: ; %frem.else16
; GFX1200-NEXT:    v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[4:5]|
; GFX1200-NEXT:    v_and_b32_e32 v8, 0x80000000, v1
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT:    v_cndmask_b32_e32 v9, v1, v8, vcc_lo
; GFX1200-NEXT:    v_cndmask_b32_e64 v8, v0, 0, vcc_lo
; GFX1200-NEXT:  .LBB13_2: ; %Flow50
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1200-NEXT:    s_cbranch_execz .LBB13_8
; GFX1200-NEXT:  ; %bb.3: ; %frem.compute15
; GFX1200-NEXT:    v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
; GFX1200-NEXT:    v_frexp_exp_i32_f64_e32 v15, v[4:5]
; GFX1200-NEXT:    v_frexp_exp_i32_f64_e32 v14, v[0:1]
; GFX1200-NEXT:    s_mov_b32 s1, exec_lo
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1200-NEXT:    v_ldexp_f64 v[12:13], v[8:9], 26
; GFX1200-NEXT:    v_frexp_mant_f64_e64 v[8:9], |v[4:5]|
; GFX1200-NEXT:    v_add_nc_u32_e32 v16, -1, v15
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT:    v_xad_u32 v17, v16, -1, v14
; GFX1200-NEXT:    v_ldexp_f64 v[8:9], v[8:9], 1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_div_scale_f64 v[10:11], null, v[8:9], v[8:9], 1.0
; GFX1200-NEXT:    v_rcp_f64_e32 v[18:19], v[10:11]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f64 v[20:21], -v[10:11], v[18:19], 1.0
; GFX1200-NEXT:    v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f64 v[20:21], -v[10:11], v[18:19], 1.0
; GFX1200-NEXT:    v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
; GFX1200-NEXT:    v_div_scale_f64 v[20:21], vcc_lo, 1.0, v[8:9], 1.0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_mul_f64_e32 v[22:23], v[20:21], v[18:19]
; GFX1200-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[22:23], v[20:21]
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_div_fmas_f64 v[10:11], v[10:11], v[18:19], v[22:23]
; GFX1200-NEXT:    v_div_fixup_f64 v[10:11], v[10:11], v[8:9], 1.0
; GFX1200-NEXT:    v_cmpx_lt_i32_e32 26, v17
; GFX1200-NEXT:    s_cbranch_execz .LBB13_7
; GFX1200-NEXT:  ; %bb.4: ; %frem.loop_body23.preheader
; GFX1200-NEXT:    v_sub_nc_u32_e32 v14, v14, v15
; GFX1200-NEXT:    s_mov_b32 s2, 0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_add_nc_u32_e32 v17, 26, v14
; GFX1200-NEXT:  .LBB13_5: ; %frem.loop_body23
; GFX1200-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT:    v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12
; GFX1200-NEXT:    v_subrev_nc_u32_e32 v17, 26, v17
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_mul_f64_e32 v[12:13], v[14:15], v[10:11]
; GFX1200-NEXT:    v_rndne_f64_e32 v[12:13], v[12:13]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[8:9], v[14:15]
; GFX1200-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
; GFX1200-NEXT:    v_add_f64_e32 v[18:19], v[12:13], v[8:9]
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT:    v_dual_cndmask_b32 v13, v13, v19 :: v_dual_cndmask_b32 v12, v12, v18
; GFX1200-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v17
; GFX1200-NEXT:    v_ldexp_f64 v[12:13], v[12:13], 26
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1200-NEXT:    s_cbranch_execnz .LBB13_5
; GFX1200-NEXT:  ; %bb.6: ; %Flow48
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1200-NEXT:    v_dual_mov_b32 v12, v14 :: v_dual_mov_b32 v13, v15
; GFX1200-NEXT:  .LBB13_7: ; %Flow49
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1200-NEXT:    v_subrev_nc_u32_e32 v14, 25, v17
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_ldexp_f64 v[12:13], v[12:13], v14
; GFX1200-NEXT:    v_mul_f64_e32 v[10:11], v[12:13], v[10:11]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_rndne_f64_e32 v[10:11], v[10:11]
; GFX1200-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[8:9], v[12:13]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[10:11]
; GFX1200-NEXT:    v_add_f64_e32 v[8:9], v[10:11], v[8:9]
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_dual_cndmask_b32 v9, v11, v9 :: v_dual_cndmask_b32 v8, v10, v8
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_ldexp_f64 v[8:9], v[8:9], v16
; GFX1200-NEXT:    v_bfi_b32 v9, 0x7fffffff, v9, v1
; GFX1200-NEXT:  .LBB13_8: ; %Flow51
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1200-NEXT:    v_cmp_ngt_f64_e64 s0, |v[2:3]|, |v[6:7]|
; GFX1200-NEXT:    ; implicit-def: $vgpr10_vgpr11
; GFX1200-NEXT:    s_and_saveexec_b32 s1, s0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX1200-NEXT:    s_cbranch_execz .LBB13_10
; GFX1200-NEXT:  ; %bb.9: ; %frem.else
; GFX1200-NEXT:    v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
; GFX1200-NEXT:    v_and_b32_e32 v10, 0x80000000, v3
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT:    v_cndmask_b32_e32 v11, v3, v10, vcc_lo
; GFX1200-NEXT:    v_cndmask_b32_e64 v10, v2, 0, vcc_lo
; GFX1200-NEXT:  .LBB13_10: ; %Flow46
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1200-NEXT:    s_cbranch_execz .LBB13_16
; GFX1200-NEXT:  ; %bb.11: ; %frem.compute
; GFX1200-NEXT:    v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
; GFX1200-NEXT:    v_frexp_exp_i32_f64_e32 v17, v[6:7]
; GFX1200-NEXT:    v_frexp_exp_i32_f64_e32 v16, v[2:3]
; GFX1200-NEXT:    s_mov_b32 s1, exec_lo
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1200-NEXT:    v_ldexp_f64 v[14:15], v[10:11], 26
; GFX1200-NEXT:    v_frexp_mant_f64_e64 v[10:11], |v[6:7]|
; GFX1200-NEXT:    v_add_nc_u32_e32 v18, -1, v17
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT:    v_xad_u32 v19, v18, -1, v16
; GFX1200-NEXT:    v_ldexp_f64 v[10:11], v[10:11], 1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_div_scale_f64 v[12:13], null, v[10:11], v[10:11], 1.0
; GFX1200-NEXT:    v_rcp_f64_e32 v[20:21], v[12:13]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f64 v[22:23], -v[12:13], v[20:21], 1.0
; GFX1200-NEXT:    v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f64 v[22:23], -v[12:13], v[20:21], 1.0
; GFX1200-NEXT:    v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21]
; GFX1200-NEXT:    v_div_scale_f64 v[22:23], vcc_lo, 1.0, v[10:11], 1.0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_mul_f64_e32 v[24:25], v[22:23], v[20:21]
; GFX1200-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[24:25], v[22:23]
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_div_fmas_f64 v[12:13], v[12:13], v[20:21], v[24:25]
; GFX1200-NEXT:    v_div_fixup_f64 v[12:13], v[12:13], v[10:11], 1.0
; GFX1200-NEXT:    v_cmpx_lt_i32_e32 26, v19
; GFX1200-NEXT:    s_cbranch_execz .LBB13_15
; GFX1200-NEXT:  ; %bb.12: ; %frem.loop_body.preheader
; GFX1200-NEXT:    v_sub_nc_u32_e32 v16, v16, v17
; GFX1200-NEXT:    s_mov_b32 s2, 0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_add_nc_u32_e32 v19, 26, v16
; GFX1200-NEXT:  .LBB13_13: ; %frem.loop_body
; GFX1200-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT:    v_dual_mov_b32 v17, v15 :: v_dual_mov_b32 v16, v14
; GFX1200-NEXT:    v_subrev_nc_u32_e32 v19, 26, v19
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_mul_f64_e32 v[14:15], v[16:17], v[12:13]
; GFX1200-NEXT:    v_rndne_f64_e32 v[14:15], v[14:15]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f64 v[14:15], -v[14:15], v[10:11], v[16:17]
; GFX1200-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[14:15]
; GFX1200-NEXT:    v_add_f64_e32 v[20:21], v[14:15], v[10:11]
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT:    v_dual_cndmask_b32 v15, v15, v21 :: v_dual_cndmask_b32 v14, v14, v20
; GFX1200-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v19
; GFX1200-NEXT:    v_ldexp_f64 v[14:15], v[14:15], 26
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1200-NEXT:    s_cbranch_execnz .LBB13_13
; GFX1200-NEXT:  ; %bb.14: ; %Flow
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1200-NEXT:    v_dual_mov_b32 v14, v16 :: v_dual_mov_b32 v15, v17
; GFX1200-NEXT:  .LBB13_15: ; %Flow45
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1200-NEXT:    v_subrev_nc_u32_e32 v16, 25, v19
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_ldexp_f64 v[14:15], v[14:15], v16
; GFX1200-NEXT:    v_mul_f64_e32 v[12:13], v[14:15], v[12:13]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_rndne_f64_e32 v[12:13], v[12:13]
; GFX1200-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[10:11], v[14:15]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
; GFX1200-NEXT:    v_add_f64_e32 v[10:11], v[12:13], v[10:11]
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_dual_cndmask_b32 v11, v13, v11 :: v_dual_cndmask_b32 v10, v12, v10
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_ldexp_f64 v[10:11], v[10:11], v18
; GFX1200-NEXT:    v_bfi_b32 v11, 0x7fffffff, v11, v3
; GFX1200-NEXT:  .LBB13_16: ; %Flow47
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1200-NEXT:    v_cmp_lg_f64_e32 vcc_lo, 0, v[4:5]
; GFX1200-NEXT:    v_cmp_nge_f64_e64 s0, |v[0:1]|, 0x7ff00000
; GFX1200-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1200-NEXT:    v_cmp_nge_f64_e64 s0, |v[2:3]|, 0x7ff00000
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    v_dual_cndmask_b32 v0, 0, v8 :: v_dual_cndmask_b32 v1, 0x7ff80000, v9
; GFX1200-NEXT:    v_cmp_lg_f64_e32 vcc_lo, 0, v[6:7]
; GFX1200-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    v_dual_cndmask_b32 v2, 0, v10 :: v_dual_cndmask_b32 v3, 0x7ff80000, v11
; GFX1200-NEXT:    s_setpc_b64 s[30:31]
   %r2 = frem <2 x double> %in1, %in2
  ret <2 x double> %r2
}


define <2 x double> @frem_v2f64_const_zero_num(<2 x double> %in) #0 {
; SI-LABEL: frem_v2f64_const_zero_num:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cmp_nlg_f64_e32 vcc, 0, v[0:1]
; SI-NEXT:    v_mov_b32_e32 v0, 0x7ff80000
; SI-NEXT:    v_cndmask_b32_e32 v1, 0, v0, vcc
; SI-NEXT:    v_cmp_nlg_f64_e32 vcc, 0, v[2:3]
; SI-NEXT:    v_mov_b32_e32 v2, 0
; SI-NEXT:    v_cndmask_b32_e32 v3, 0, v0, vcc
; SI-NEXT:    v_mov_b32_e32 v0, 0
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; CI-LABEL: frem_v2f64_const_zero_num:
; CI:       ; %bb.0:
; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-NEXT:    v_cmp_nlg_f64_e32 vcc, 0, v[0:1]
; CI-NEXT:    v_mov_b32_e32 v0, 0x7ff80000
; CI-NEXT:    v_cndmask_b32_e32 v1, 0, v0, vcc
; CI-NEXT:    v_cmp_nlg_f64_e32 vcc, 0, v[2:3]
; CI-NEXT:    v_mov_b32_e32 v2, 0
; CI-NEXT:    v_cndmask_b32_e32 v3, 0, v0, vcc
; CI-NEXT:    v_mov_b32_e32 v0, 0
; CI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: frem_v2f64_const_zero_num:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_nlg_f64_e32 vcc, 0, v[0:1]
; VI-NEXT:    v_mov_b32_e32 v0, 0x7ff80000
; VI-NEXT:    v_cndmask_b32_e32 v1, 0, v0, vcc
; VI-NEXT:    v_cmp_nlg_f64_e32 vcc, 0, v[2:3]
; VI-NEXT:    v_mov_b32_e32 v2, 0
; VI-NEXT:    v_cndmask_b32_e32 v3, 0, v0, vcc
; VI-NEXT:    v_mov_b32_e32 v0, 0
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: frem_v2f64_const_zero_num:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_nlg_f64_e32 vcc, 0, v[0:1]
; GFX9-NEXT:    v_mov_b32_e32 v0, 0x7ff80000
; GFX9-NEXT:    v_cndmask_b32_e32 v1, 0, v0, vcc
; GFX9-NEXT:    v_cmp_nlg_f64_e32 vcc, 0, v[2:3]
; GFX9-NEXT:    v_mov_b32_e32 v2, 0
; GFX9-NEXT:    v_cndmask_b32_e32 v3, 0, v0, vcc
; GFX9-NEXT:    v_mov_b32_e32 v0, 0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: frem_v2f64_const_zero_num:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cmp_nlg_f64_e32 vcc_lo, 0, v[0:1]
; GFX10-NEXT:    v_mov_b32_e32 v0, 0
; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 0x7ff80000, vcc_lo
; GFX10-NEXT:    v_cmp_nlg_f64_e32 vcc_lo, 0, v[2:3]
; GFX10-NEXT:    v_mov_b32_e32 v2, 0
; GFX10-NEXT:    v_cndmask_b32_e64 v3, 0, 0x7ff80000, vcc_lo
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: frem_v2f64_const_zero_num:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cmp_nlg_f64_e32 vcc_lo, 0, v[0:1]
; GFX11-NEXT:    v_mov_b32_e32 v0, 0
; GFX11-NEXT:    v_cndmask_b32_e64 v1, 0, 0x7ff80000, vcc_lo
; GFX11-NEXT:    v_cmp_nlg_f64_e32 vcc_lo, 0, v[2:3]
; GFX11-NEXT:    v_mov_b32_e32 v2, 0
; GFX11-NEXT:    v_cndmask_b32_e64 v3, 0, 0x7ff80000, vcc_lo
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-LABEL: frem_v2f64_const_zero_num:
; GFX1150:       ; %bb.0:
; GFX1150-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-NEXT:    v_cmp_nlg_f64_e32 vcc_lo, 0, v[0:1]
; GFX1150-NEXT:    v_mov_b32_e32 v0, 0
; GFX1150-NEXT:    v_cndmask_b32_e64 v1, 0, 0x7ff80000, vcc_lo
; GFX1150-NEXT:    v_cmp_nlg_f64_e32 vcc_lo, 0, v[2:3]
; GFX1150-NEXT:    v_mov_b32_e32 v2, 0
; GFX1150-NEXT:    v_cndmask_b32_e64 v3, 0, 0x7ff80000, vcc_lo
; GFX1150-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: frem_v2f64_const_zero_num:
; GFX1200:       ; %bb.0:
; GFX1200-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT:    s_wait_expcnt 0x0
; GFX1200-NEXT:    s_wait_samplecnt 0x0
; GFX1200-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-NEXT:    s_wait_kmcnt 0x0
; GFX1200-NEXT:    v_cmp_nlg_f64_e32 vcc_lo, 0, v[0:1]
; GFX1200-NEXT:    v_mov_b32_e32 v0, 0
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_cndmask_b32_e64 v1, 0, 0x7ff80000, vcc_lo
; GFX1200-NEXT:    v_cmp_nlg_f64_e32 vcc_lo, 0, v[2:3]
; GFX1200-NEXT:    v_mov_b32_e32 v2, 0
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_cndmask_b32_e64 v3, 0, 0x7ff80000, vcc_lo
; GFX1200-NEXT:    s_setpc_b64 s[30:31]
   %r1 = frem  <2 x double> <double 0.0, double 0.0>, %in
  ret <2 x double> %r1
}

define <2 x double> @frem_v2f64_const_one_denum(<2 x double> %in) #0 {
; SI-LABEL: frem_v2f64_const_one_denum:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cmp_ngt_f64_e64 s[4:5], |v[0:1]|, 1.0
; SI-NEXT:    ; implicit-def: $vgpr4_vgpr5
; SI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; SI-NEXT:  ; %bb.1: ; %frem.else16
; SI-NEXT:    v_cmp_eq_f64_e64 vcc, |v[0:1]|, 1.0
; SI-NEXT:    v_and_b32_e32 v4, 0x80000000, v1
; SI-NEXT:    v_cndmask_b32_e32 v5, v1, v4, vcc
; SI-NEXT:    v_cndmask_b32_e64 v4, v0, 0, vcc
; SI-NEXT:  ; %bb.2: ; %Flow50
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB15_8
; SI-NEXT:  ; %bb.3: ; %frem.compute15
; SI-NEXT:    v_and_b32_e32 v6, 0x7fffffff, v1
; SI-NEXT:    s_mov_b32 s6, 0x7ff00000
; SI-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, s6, v6
; SI-NEXT:    v_cndmask_b32_e32 v6, v6, v5, vcc
; SI-NEXT:    v_cndmask_b32_e32 v5, v0, v4, vcc
; SI-NEXT:    v_frexp_exp_i32_f64_e32 v4, v[0:1]
; SI-NEXT:    v_ldexp_f64 v[5:6], v[5:6], 26
; SI-NEXT:    v_cndmask_b32_e32 v4, 0, v4, vcc
; SI-NEXT:    v_add_i32_e32 v9, vcc, -1, v4
; SI-NEXT:    s_brev_b32 s12, -2
; SI-NEXT:    s_mov_b32 s8, -1
; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v9
; SI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; SI-NEXT:    s_cbranch_execz .LBB15_7
; SI-NEXT:  ; %bb.4: ; %frem.loop_body23.preheader
; SI-NEXT:    v_add_i32_e32 v9, vcc, 25, v4
; SI-NEXT:    s_mov_b64 s[10:11], 0
; SI-NEXT:    v_mov_b32_e32 v10, 0x43300000
; SI-NEXT:    v_mov_b32_e32 v4, 0
; SI-NEXT:    s_mov_b32 s9, 0x432fffff
; SI-NEXT:  .LBB15_5: ; %frem.loop_body23
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v8, v6
; SI-NEXT:    v_mov_b32_e32 v7, v5
; SI-NEXT:    v_bfi_b32 v5, s12, v10, v8
; SI-NEXT:    v_add_f64 v[11:12], v[7:8], v[4:5]
; SI-NEXT:    v_cmp_gt_f64_e64 vcc, |v[7:8]|, s[8:9]
; SI-NEXT:    v_add_f64 v[5:6], v[11:12], -v[4:5]
; SI-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc
; SI-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
; SI-NEXT:    v_add_f64 v[5:6], v[7:8], -v[5:6]
; SI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[5:6]
; SI-NEXT:    v_add_f64 v[11:12], v[5:6], 1.0
; SI-NEXT:    v_cndmask_b32_e32 v6, v6, v12, vcc
; SI-NEXT:    v_cndmask_b32_e32 v5, v5, v11, vcc
; SI-NEXT:    v_subrev_i32_e32 v9, vcc, 26, v9
; SI-NEXT:    v_ldexp_f64 v[5:6], v[5:6], 26
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v9
; SI-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
; SI-NEXT:    s_andn2_b64 exec, exec, s[10:11]
; SI-NEXT:    s_cbranch_execnz .LBB15_5
; SI-NEXT:  ; %bb.6: ; %Flow48
; SI-NEXT:    s_or_b64 exec, exec, s[10:11]
; SI-NEXT:    v_mov_b32_e32 v5, v7
; SI-NEXT:    v_mov_b32_e32 v6, v8
; SI-NEXT:  .LBB15_7: ; %Flow49
; SI-NEXT:    s_or_b64 exec, exec, s[6:7]
; SI-NEXT:    v_subrev_i32_e32 v4, vcc, 25, v9
; SI-NEXT:    v_ldexp_f64 v[4:5], v[5:6], v4
; SI-NEXT:    s_mov_b32 s6, -1
; SI-NEXT:    s_mov_b32 s7, 0x432fffff
; SI-NEXT:    v_cmp_gt_f64_e64 vcc, |v[4:5]|, s[6:7]
; SI-NEXT:    s_brev_b32 s6, -2
; SI-NEXT:    v_mov_b32_e32 v6, 0x43300000
; SI-NEXT:    v_bfi_b32 v7, s6, v6, v5
; SI-NEXT:    v_mov_b32_e32 v6, 0
; SI-NEXT:    v_add_f64 v[8:9], v[4:5], v[6:7]
; SI-NEXT:    v_add_f64 v[6:7], v[8:9], -v[6:7]
; SI-NEXT:    v_cndmask_b32_e32 v7, v7, v5, vcc
; SI-NEXT:    v_cndmask_b32_e32 v6, v6, v4, vcc
; SI-NEXT:    v_add_f64 v[4:5], v[4:5], -v[6:7]
; SI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[4:5]
; SI-NEXT:    v_add_f64 v[6:7], v[4:5], 1.0
; SI-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
; SI-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
; SI-NEXT:    v_bfi_b32 v5, s6, v5, v1
; SI-NEXT:  .LBB15_8: ; %Flow51
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    v_cmp_ngt_f64_e64 s[4:5], |v[2:3]|, 1.0
; SI-NEXT:    ; implicit-def: $vgpr6_vgpr7
; SI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; SI-NEXT:  ; %bb.9: ; %frem.else
; SI-NEXT:    v_cmp_eq_f64_e64 vcc, |v[2:3]|, 1.0
; SI-NEXT:    v_and_b32_e32 v6, 0x80000000, v3
; SI-NEXT:    v_cndmask_b32_e32 v7, v3, v6, vcc
; SI-NEXT:    v_cndmask_b32_e64 v6, v2, 0, vcc
; SI-NEXT:  ; %bb.10: ; %Flow46
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB15_16
; SI-NEXT:  ; %bb.11: ; %frem.compute
; SI-NEXT:    v_and_b32_e32 v8, 0x7fffffff, v3
; SI-NEXT:    s_mov_b32 s6, 0x7ff00000
; SI-NEXT:    v_frexp_mant_f64_e64 v[6:7], |v[2:3]|
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, s6, v8
; SI-NEXT:    v_cndmask_b32_e32 v8, v8, v7, vcc
; SI-NEXT:    v_cndmask_b32_e32 v7, v2, v6, vcc
; SI-NEXT:    v_frexp_exp_i32_f64_e32 v6, v[2:3]
; SI-NEXT:    v_ldexp_f64 v[7:8], v[7:8], 26
; SI-NEXT:    v_cndmask_b32_e32 v6, 0, v6, vcc
; SI-NEXT:    v_add_i32_e32 v11, vcc, -1, v6
; SI-NEXT:    s_brev_b32 s12, -2
; SI-NEXT:    s_mov_b32 s8, -1
; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v11
; SI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; SI-NEXT:    s_cbranch_execz .LBB15_15
; SI-NEXT:  ; %bb.12: ; %frem.loop_body.preheader
; SI-NEXT:    v_add_i32_e32 v11, vcc, 25, v6
; SI-NEXT:    s_mov_b64 s[10:11], 0
; SI-NEXT:    v_mov_b32_e32 v12, 0x43300000
; SI-NEXT:    v_mov_b32_e32 v6, 0
; SI-NEXT:    s_mov_b32 s9, 0x432fffff
; SI-NEXT:  .LBB15_13: ; %frem.loop_body
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v10, v8
; SI-NEXT:    v_mov_b32_e32 v9, v7
; SI-NEXT:    v_bfi_b32 v7, s12, v12, v10
; SI-NEXT:    v_add_f64 v[13:14], v[9:10], v[6:7]
; SI-NEXT:    v_cmp_gt_f64_e64 vcc, |v[9:10]|, s[8:9]
; SI-NEXT:    v_add_f64 v[7:8], v[13:14], -v[6:7]
; SI-NEXT:    v_cndmask_b32_e32 v8, v8, v10, vcc
; SI-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc
; SI-NEXT:    v_add_f64 v[7:8], v[9:10], -v[7:8]
; SI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[7:8]
; SI-NEXT:    v_add_f64 v[13:14], v[7:8], 1.0
; SI-NEXT:    v_cndmask_b32_e32 v8, v8, v14, vcc
; SI-NEXT:    v_cndmask_b32_e32 v7, v7, v13, vcc
; SI-NEXT:    v_subrev_i32_e32 v11, vcc, 26, v11
; SI-NEXT:    v_ldexp_f64 v[7:8], v[7:8], 26
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v11
; SI-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
; SI-NEXT:    s_andn2_b64 exec, exec, s[10:11]
; SI-NEXT:    s_cbranch_execnz .LBB15_13
; SI-NEXT:  ; %bb.14: ; %Flow
; SI-NEXT:    s_or_b64 exec, exec, s[10:11]
; SI-NEXT:    v_mov_b32_e32 v7, v9
; SI-NEXT:    v_mov_b32_e32 v8, v10
; SI-NEXT:  .LBB15_15: ; %Flow45
; SI-NEXT:    s_or_b64 exec, exec, s[6:7]
; SI-NEXT:    v_subrev_i32_e32 v6, vcc, 25, v11
; SI-NEXT:    v_ldexp_f64 v[6:7], v[7:8], v6
; SI-NEXT:    s_mov_b32 s6, -1
; SI-NEXT:    s_mov_b32 s7, 0x432fffff
; SI-NEXT:    v_cmp_gt_f64_e64 vcc, |v[6:7]|, s[6:7]
; SI-NEXT:    s_brev_b32 s6, -2
; SI-NEXT:    v_mov_b32_e32 v8, 0x43300000
; SI-NEXT:    v_bfi_b32 v9, s6, v8, v7
; SI-NEXT:    v_mov_b32_e32 v8, 0
; SI-NEXT:    v_add_f64 v[10:11], v[6:7], v[8:9]
; SI-NEXT:    v_add_f64 v[8:9], v[10:11], -v[8:9]
; SI-NEXT:    v_cndmask_b32_e32 v9, v9, v7, vcc
; SI-NEXT:    v_cndmask_b32_e32 v8, v8, v6, vcc
; SI-NEXT:    v_add_f64 v[6:7], v[6:7], -v[8:9]
; SI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[6:7]
; SI-NEXT:    v_add_f64 v[8:9], v[6:7], 1.0
; SI-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc
; SI-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc
; SI-NEXT:    v_bfi_b32 v7, s6, v7, v3
; SI-NEXT:  .LBB15_16: ; %Flow47
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    s_mov_b32 s4, 0
; SI-NEXT:    s_mov_b32 s5, 0x7ff00000
; SI-NEXT:    v_cmp_nge_f64_e64 vcc, |v[0:1]|, s[4:5]
; SI-NEXT:    v_cndmask_b32_e32 v0, 0, v4, vcc
; SI-NEXT:    v_mov_b32_e32 v4, 0x7ff80000
; SI-NEXT:    v_cndmask_b32_e32 v1, v4, v5, vcc
; SI-NEXT:    v_cmp_nge_f64_e64 vcc, |v[2:3]|, s[4:5]
; SI-NEXT:    v_cndmask_b32_e32 v2, 0, v6, vcc
; SI-NEXT:    v_cndmask_b32_e32 v3, v4, v7, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; CI-LABEL: frem_v2f64_const_one_denum:
; CI:       ; %bb.0:
; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-NEXT:    v_cmp_ngt_f64_e64 s[4:5], |v[0:1]|, 1.0
; CI-NEXT:    ; implicit-def: $vgpr4_vgpr5
; CI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; CI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; CI-NEXT:    s_cbranch_execz .LBB15_2
; CI-NEXT:  ; %bb.1: ; %frem.else16
; CI-NEXT:    v_cmp_eq_f64_e64 vcc, |v[0:1]|, 1.0
; CI-NEXT:    v_and_b32_e32 v4, 0x80000000, v1
; CI-NEXT:    v_cndmask_b32_e32 v5, v1, v4, vcc
; CI-NEXT:    v_cndmask_b32_e64 v4, v0, 0, vcc
; CI-NEXT:  .LBB15_2: ; %Flow50
; CI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; CI-NEXT:    s_cbranch_execz .LBB15_8
; CI-NEXT:  ; %bb.3: ; %frem.compute15
; CI-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; CI-NEXT:    v_frexp_exp_i32_f64_e32 v6, v[0:1]
; CI-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; CI-NEXT:    v_add_i32_e32 v8, vcc, -1, v6
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v8
; CI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; CI-NEXT:    s_cbranch_execz .LBB15_7
; CI-NEXT:  ; %bb.4: ; %frem.loop_body23.preheader
; CI-NEXT:    v_add_i32_e32 v8, vcc, 25, v6
; CI-NEXT:    s_mov_b64 s[8:9], 0
; CI-NEXT:  .LBB15_5: ; %frem.loop_body23
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v7, v5
; CI-NEXT:    v_mov_b32_e32 v6, v4
; CI-NEXT:    v_rndne_f64_e32 v[4:5], v[6:7]
; CI-NEXT:    v_add_f64 v[4:5], v[6:7], -v[4:5]
; CI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[4:5]
; CI-NEXT:    v_add_f64 v[9:10], v[4:5], 1.0
; CI-NEXT:    v_cndmask_b32_e32 v5, v5, v10, vcc
; CI-NEXT:    v_cndmask_b32_e32 v4, v4, v9, vcc
; CI-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; CI-NEXT:    v_subrev_i32_e32 v8, vcc, 26, v8
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v8
; CI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; CI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; CI-NEXT:    s_cbranch_execnz .LBB15_5
; CI-NEXT:  ; %bb.6: ; %Flow48
; CI-NEXT:    s_or_b64 exec, exec, s[8:9]
; CI-NEXT:    v_mov_b32_e32 v4, v6
; CI-NEXT:    v_mov_b32_e32 v5, v7
; CI-NEXT:  .LBB15_7: ; %Flow49
; CI-NEXT:    s_or_b64 exec, exec, s[6:7]
; CI-NEXT:    v_subrev_i32_e32 v6, vcc, 25, v8
; CI-NEXT:    v_ldexp_f64 v[4:5], v[4:5], v6
; CI-NEXT:    s_brev_b32 s6, -2
; CI-NEXT:    v_rndne_f64_e32 v[6:7], v[4:5]
; CI-NEXT:    v_add_f64 v[4:5], v[4:5], -v[6:7]
; CI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[4:5]
; CI-NEXT:    v_add_f64 v[6:7], v[4:5], 1.0
; CI-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
; CI-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
; CI-NEXT:    v_bfi_b32 v5, s6, v5, v1
; CI-NEXT:  .LBB15_8: ; %Flow51
; CI-NEXT:    s_or_b64 exec, exec, s[4:5]
; CI-NEXT:    v_cmp_ngt_f64_e64 s[4:5], |v[2:3]|, 1.0
; CI-NEXT:    ; implicit-def: $vgpr6_vgpr7
; CI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; CI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; CI-NEXT:    s_cbranch_execz .LBB15_10
; CI-NEXT:  ; %bb.9: ; %frem.else
; CI-NEXT:    v_cmp_eq_f64_e64 vcc, |v[2:3]|, 1.0
; CI-NEXT:    v_and_b32_e32 v6, 0x80000000, v3
; CI-NEXT:    v_cndmask_b32_e32 v7, v3, v6, vcc
; CI-NEXT:    v_cndmask_b32_e64 v6, v2, 0, vcc
; CI-NEXT:  .LBB15_10: ; %Flow46
; CI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; CI-NEXT:    s_cbranch_execz .LBB15_16
; CI-NEXT:  ; %bb.11: ; %frem.compute
; CI-NEXT:    v_frexp_mant_f64_e64 v[6:7], |v[2:3]|
; CI-NEXT:    v_frexp_exp_i32_f64_e32 v8, v[2:3]
; CI-NEXT:    v_ldexp_f64 v[6:7], v[6:7], 26
; CI-NEXT:    v_add_i32_e32 v10, vcc, -1, v8
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v10
; CI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; CI-NEXT:    s_cbranch_execz .LBB15_15
; CI-NEXT:  ; %bb.12: ; %frem.loop_body.preheader
; CI-NEXT:    v_add_i32_e32 v10, vcc, 25, v8
; CI-NEXT:    s_mov_b64 s[8:9], 0
; CI-NEXT:  .LBB15_13: ; %frem.loop_body
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v9, v7
; CI-NEXT:    v_mov_b32_e32 v8, v6
; CI-NEXT:    v_rndne_f64_e32 v[6:7], v[8:9]
; CI-NEXT:    v_add_f64 v[6:7], v[8:9], -v[6:7]
; CI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[6:7]
; CI-NEXT:    v_add_f64 v[11:12], v[6:7], 1.0
; CI-NEXT:    v_cndmask_b32_e32 v7, v7, v12, vcc
; CI-NEXT:    v_cndmask_b32_e32 v6, v6, v11, vcc
; CI-NEXT:    v_ldexp_f64 v[6:7], v[6:7], 26
; CI-NEXT:    v_subrev_i32_e32 v10, vcc, 26, v10
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v10
; CI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; CI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; CI-NEXT:    s_cbranch_execnz .LBB15_13
; CI-NEXT:  ; %bb.14: ; %Flow
; CI-NEXT:    s_or_b64 exec, exec, s[8:9]
; CI-NEXT:    v_mov_b32_e32 v6, v8
; CI-NEXT:    v_mov_b32_e32 v7, v9
; CI-NEXT:  .LBB15_15: ; %Flow45
; CI-NEXT:    s_or_b64 exec, exec, s[6:7]
; CI-NEXT:    v_subrev_i32_e32 v8, vcc, 25, v10
; CI-NEXT:    v_ldexp_f64 v[6:7], v[6:7], v8
; CI-NEXT:    s_brev_b32 s6, -2
; CI-NEXT:    v_rndne_f64_e32 v[8:9], v[6:7]
; CI-NEXT:    v_add_f64 v[6:7], v[6:7], -v[8:9]
; CI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[6:7]
; CI-NEXT:    v_add_f64 v[8:9], v[6:7], 1.0
; CI-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc
; CI-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc
; CI-NEXT:    v_bfi_b32 v7, s6, v7, v3
; CI-NEXT:  .LBB15_16: ; %Flow47
; CI-NEXT:    s_or_b64 exec, exec, s[4:5]
; CI-NEXT:    s_mov_b32 s4, 0
; CI-NEXT:    s_mov_b32 s5, 0x7ff00000
; CI-NEXT:    v_cmp_nge_f64_e64 vcc, |v[0:1]|, s[4:5]
; CI-NEXT:    v_cndmask_b32_e32 v0, 0, v4, vcc
; CI-NEXT:    v_mov_b32_e32 v4, 0x7ff80000
; CI-NEXT:    v_cndmask_b32_e32 v1, v4, v5, vcc
; CI-NEXT:    v_cmp_nge_f64_e64 vcc, |v[2:3]|, s[4:5]
; CI-NEXT:    v_cndmask_b32_e32 v2, 0, v6, vcc
; CI-NEXT:    v_cndmask_b32_e32 v3, v4, v7, vcc
; CI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: frem_v2f64_const_one_denum:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ngt_f64_e64 s[4:5], |v[0:1]|, 1.0
; VI-NEXT:    ; implicit-def: $vgpr4_vgpr5
; VI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; VI-NEXT:    s_cbranch_execz .LBB15_2
; VI-NEXT:  ; %bb.1: ; %frem.else16
; VI-NEXT:    v_cmp_eq_f64_e64 vcc, |v[0:1]|, 1.0
; VI-NEXT:    v_and_b32_e32 v4, 0x80000000, v1
; VI-NEXT:    v_cndmask_b32_e32 v5, v1, v4, vcc
; VI-NEXT:    v_cndmask_b32_e64 v4, v0, 0, vcc
; VI-NEXT:  .LBB15_2: ; %Flow50
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB15_8
; VI-NEXT:  ; %bb.3: ; %frem.compute15
; VI-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; VI-NEXT:    v_frexp_exp_i32_f64_e32 v6, v[0:1]
; VI-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; VI-NEXT:    v_add_u32_e32 v8, vcc, -1, v6
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v8
; VI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; VI-NEXT:    s_cbranch_execz .LBB15_7
; VI-NEXT:  ; %bb.4: ; %frem.loop_body23.preheader
; VI-NEXT:    v_add_u32_e32 v8, vcc, 25, v6
; VI-NEXT:    s_mov_b64 s[8:9], 0
; VI-NEXT:  .LBB15_5: ; %frem.loop_body23
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v7, v5
; VI-NEXT:    v_mov_b32_e32 v6, v4
; VI-NEXT:    v_rndne_f64_e32 v[4:5], v[6:7]
; VI-NEXT:    v_add_f64 v[4:5], v[6:7], -v[4:5]
; VI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[4:5]
; VI-NEXT:    v_add_f64 v[9:10], v[4:5], 1.0
; VI-NEXT:    v_cndmask_b32_e32 v5, v5, v10, vcc
; VI-NEXT:    v_cndmask_b32_e32 v4, v4, v9, vcc
; VI-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; VI-NEXT:    v_subrev_u32_e32 v8, vcc, 26, v8
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v8
; VI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; VI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; VI-NEXT:    s_cbranch_execnz .LBB15_5
; VI-NEXT:  ; %bb.6: ; %Flow48
; VI-NEXT:    s_or_b64 exec, exec, s[8:9]
; VI-NEXT:    v_mov_b32_e32 v4, v6
; VI-NEXT:    v_mov_b32_e32 v5, v7
; VI-NEXT:  .LBB15_7: ; %Flow49
; VI-NEXT:    s_or_b64 exec, exec, s[6:7]
; VI-NEXT:    v_subrev_u32_e32 v6, vcc, 25, v8
; VI-NEXT:    v_ldexp_f64 v[4:5], v[4:5], v6
; VI-NEXT:    s_brev_b32 s6, -2
; VI-NEXT:    v_rndne_f64_e32 v[6:7], v[4:5]
; VI-NEXT:    v_add_f64 v[4:5], v[4:5], -v[6:7]
; VI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[4:5]
; VI-NEXT:    v_add_f64 v[6:7], v[4:5], 1.0
; VI-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
; VI-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
; VI-NEXT:    v_bfi_b32 v5, s6, v5, v1
; VI-NEXT:  .LBB15_8: ; %Flow51
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    v_cmp_ngt_f64_e64 s[4:5], |v[2:3]|, 1.0
; VI-NEXT:    ; implicit-def: $vgpr6_vgpr7
; VI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; VI-NEXT:    s_cbranch_execz .LBB15_10
; VI-NEXT:  ; %bb.9: ; %frem.else
; VI-NEXT:    v_cmp_eq_f64_e64 vcc, |v[2:3]|, 1.0
; VI-NEXT:    v_and_b32_e32 v6, 0x80000000, v3
; VI-NEXT:    v_cndmask_b32_e32 v7, v3, v6, vcc
; VI-NEXT:    v_cndmask_b32_e64 v6, v2, 0, vcc
; VI-NEXT:  .LBB15_10: ; %Flow46
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB15_16
; VI-NEXT:  ; %bb.11: ; %frem.compute
; VI-NEXT:    v_frexp_mant_f64_e64 v[6:7], |v[2:3]|
; VI-NEXT:    v_frexp_exp_i32_f64_e32 v8, v[2:3]
; VI-NEXT:    v_ldexp_f64 v[6:7], v[6:7], 26
; VI-NEXT:    v_add_u32_e32 v10, vcc, -1, v8
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v10
; VI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; VI-NEXT:    s_cbranch_execz .LBB15_15
; VI-NEXT:  ; %bb.12: ; %frem.loop_body.preheader
; VI-NEXT:    v_add_u32_e32 v10, vcc, 25, v8
; VI-NEXT:    s_mov_b64 s[8:9], 0
; VI-NEXT:  .LBB15_13: ; %frem.loop_body
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v9, v7
; VI-NEXT:    v_mov_b32_e32 v8, v6
; VI-NEXT:    v_rndne_f64_e32 v[6:7], v[8:9]
; VI-NEXT:    v_add_f64 v[6:7], v[8:9], -v[6:7]
; VI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[6:7]
; VI-NEXT:    v_add_f64 v[11:12], v[6:7], 1.0
; VI-NEXT:    v_cndmask_b32_e32 v7, v7, v12, vcc
; VI-NEXT:    v_cndmask_b32_e32 v6, v6, v11, vcc
; VI-NEXT:    v_ldexp_f64 v[6:7], v[6:7], 26
; VI-NEXT:    v_subrev_u32_e32 v10, vcc, 26, v10
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v10
; VI-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; VI-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; VI-NEXT:    s_cbranch_execnz .LBB15_13
; VI-NEXT:  ; %bb.14: ; %Flow
; VI-NEXT:    s_or_b64 exec, exec, s[8:9]
; VI-NEXT:    v_mov_b32_e32 v6, v8
; VI-NEXT:    v_mov_b32_e32 v7, v9
; VI-NEXT:  .LBB15_15: ; %Flow45
; VI-NEXT:    s_or_b64 exec, exec, s[6:7]
; VI-NEXT:    v_subrev_u32_e32 v8, vcc, 25, v10
; VI-NEXT:    v_ldexp_f64 v[6:7], v[6:7], v8
; VI-NEXT:    s_brev_b32 s6, -2
; VI-NEXT:    v_rndne_f64_e32 v[8:9], v[6:7]
; VI-NEXT:    v_add_f64 v[6:7], v[6:7], -v[8:9]
; VI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[6:7]
; VI-NEXT:    v_add_f64 v[8:9], v[6:7], 1.0
; VI-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc
; VI-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc
; VI-NEXT:    v_bfi_b32 v7, s6, v7, v3
; VI-NEXT:  .LBB15_16: ; %Flow47
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_mov_b32 s4, 0
; VI-NEXT:    s_mov_b32 s5, 0x7ff00000
; VI-NEXT:    v_cmp_nge_f64_e64 vcc, |v[0:1]|, s[4:5]
; VI-NEXT:    v_cndmask_b32_e32 v0, 0, v4, vcc
; VI-NEXT:    v_mov_b32_e32 v4, 0x7ff80000
; VI-NEXT:    v_cndmask_b32_e32 v1, v4, v5, vcc
; VI-NEXT:    v_cmp_nge_f64_e64 vcc, |v[2:3]|, s[4:5]
; VI-NEXT:    v_cndmask_b32_e32 v2, 0, v6, vcc
; VI-NEXT:    v_cndmask_b32_e32 v3, v4, v7, vcc
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: frem_v2f64_const_one_denum:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ngt_f64_e64 s[4:5], |v[0:1]|, 1.0
; GFX9-NEXT:    ; implicit-def: $vgpr4_vgpr5
; GFX9-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; GFX9-NEXT:    s_cbranch_execz .LBB15_2
; GFX9-NEXT:  ; %bb.1: ; %frem.else16
; GFX9-NEXT:    v_cmp_eq_f64_e64 vcc, |v[0:1]|, 1.0
; GFX9-NEXT:    v_and_b32_e32 v4, 0x80000000, v1
; GFX9-NEXT:    v_cndmask_b32_e32 v5, v1, v4, vcc
; GFX9-NEXT:    v_cndmask_b32_e64 v4, v0, 0, vcc
; GFX9-NEXT:  .LBB15_2: ; %Flow50
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB15_8
; GFX9-NEXT:  ; %bb.3: ; %frem.compute15
; GFX9-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; GFX9-NEXT:    v_frexp_exp_i32_f64_e32 v6, v[0:1]
; GFX9-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; GFX9-NEXT:    v_add_u32_e32 v8, -1, v6
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v8
; GFX9-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; GFX9-NEXT:    s_cbranch_execz .LBB15_7
; GFX9-NEXT:  ; %bb.4: ; %frem.loop_body23.preheader
; GFX9-NEXT:    v_add_u32_e32 v8, 25, v6
; GFX9-NEXT:    s_mov_b64 s[8:9], 0
; GFX9-NEXT:  .LBB15_5: ; %frem.loop_body23
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v7, v5
; GFX9-NEXT:    v_mov_b32_e32 v6, v4
; GFX9-NEXT:    v_rndne_f64_e32 v[4:5], v[6:7]
; GFX9-NEXT:    v_subrev_u32_e32 v8, 26, v8
; GFX9-NEXT:    v_add_f64 v[4:5], v[6:7], -v[4:5]
; GFX9-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[4:5]
; GFX9-NEXT:    v_add_f64 v[9:10], v[4:5], 1.0
; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v10, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v9, vcc
; GFX9-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v8
; GFX9-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; GFX9-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; GFX9-NEXT:    s_cbranch_execnz .LBB15_5
; GFX9-NEXT:  ; %bb.6: ; %Flow48
; GFX9-NEXT:    s_or_b64 exec, exec, s[8:9]
; GFX9-NEXT:    v_mov_b32_e32 v4, v6
; GFX9-NEXT:    v_mov_b32_e32 v5, v7
; GFX9-NEXT:  .LBB15_7: ; %Flow49
; GFX9-NEXT:    s_or_b64 exec, exec, s[6:7]
; GFX9-NEXT:    v_subrev_u32_e32 v6, 25, v8
; GFX9-NEXT:    v_ldexp_f64 v[4:5], v[4:5], v6
; GFX9-NEXT:    s_brev_b32 s6, -2
; GFX9-NEXT:    v_rndne_f64_e32 v[6:7], v[4:5]
; GFX9-NEXT:    v_add_f64 v[4:5], v[4:5], -v[6:7]
; GFX9-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[4:5]
; GFX9-NEXT:    v_add_f64 v[6:7], v[4:5], 1.0
; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX9-NEXT:    v_bfi_b32 v5, s6, v5, v1
; GFX9-NEXT:  .LBB15_8: ; %Flow51
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    v_cmp_ngt_f64_e64 s[4:5], |v[2:3]|, 1.0
; GFX9-NEXT:    ; implicit-def: $vgpr6_vgpr7
; GFX9-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
; GFX9-NEXT:    s_cbranch_execz .LBB15_10
; GFX9-NEXT:  ; %bb.9: ; %frem.else
; GFX9-NEXT:    v_cmp_eq_f64_e64 vcc, |v[2:3]|, 1.0
; GFX9-NEXT:    v_and_b32_e32 v6, 0x80000000, v3
; GFX9-NEXT:    v_cndmask_b32_e32 v7, v3, v6, vcc
; GFX9-NEXT:    v_cndmask_b32_e64 v6, v2, 0, vcc
; GFX9-NEXT:  .LBB15_10: ; %Flow46
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB15_16
; GFX9-NEXT:  ; %bb.11: ; %frem.compute
; GFX9-NEXT:    v_frexp_mant_f64_e64 v[6:7], |v[2:3]|
; GFX9-NEXT:    v_frexp_exp_i32_f64_e32 v8, v[2:3]
; GFX9-NEXT:    v_ldexp_f64 v[6:7], v[6:7], 26
; GFX9-NEXT:    v_add_u32_e32 v10, -1, v8
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v10
; GFX9-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; GFX9-NEXT:    s_cbranch_execz .LBB15_15
; GFX9-NEXT:  ; %bb.12: ; %frem.loop_body.preheader
; GFX9-NEXT:    v_add_u32_e32 v10, 25, v8
; GFX9-NEXT:    s_mov_b64 s[8:9], 0
; GFX9-NEXT:  .LBB15_13: ; %frem.loop_body
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v9, v7
; GFX9-NEXT:    v_mov_b32_e32 v8, v6
; GFX9-NEXT:    v_rndne_f64_e32 v[6:7], v[8:9]
; GFX9-NEXT:    v_subrev_u32_e32 v10, 26, v10
; GFX9-NEXT:    v_add_f64 v[6:7], v[8:9], -v[6:7]
; GFX9-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[6:7]
; GFX9-NEXT:    v_add_f64 v[11:12], v[6:7], 1.0
; GFX9-NEXT:    v_cndmask_b32_e32 v7, v7, v12, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v6, v6, v11, vcc
; GFX9-NEXT:    v_ldexp_f64 v[6:7], v[6:7], 26
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v10
; GFX9-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
; GFX9-NEXT:    s_andn2_b64 exec, exec, s[8:9]
; GFX9-NEXT:    s_cbranch_execnz .LBB15_13
; GFX9-NEXT:  ; %bb.14: ; %Flow
; GFX9-NEXT:    s_or_b64 exec, exec, s[8:9]
; GFX9-NEXT:    v_mov_b32_e32 v6, v8
; GFX9-NEXT:    v_mov_b32_e32 v7, v9
; GFX9-NEXT:  .LBB15_15: ; %Flow45
; GFX9-NEXT:    s_or_b64 exec, exec, s[6:7]
; GFX9-NEXT:    v_subrev_u32_e32 v8, 25, v10
; GFX9-NEXT:    v_ldexp_f64 v[6:7], v[6:7], v8
; GFX9-NEXT:    s_brev_b32 s6, -2
; GFX9-NEXT:    v_rndne_f64_e32 v[8:9], v[6:7]
; GFX9-NEXT:    v_add_f64 v[6:7], v[6:7], -v[8:9]
; GFX9-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[6:7]
; GFX9-NEXT:    v_add_f64 v[8:9], v[6:7], 1.0
; GFX9-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc
; GFX9-NEXT:    v_bfi_b32 v7, s6, v7, v3
; GFX9-NEXT:  .LBB15_16: ; %Flow47
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_mov_b32 s4, 0
; GFX9-NEXT:    s_mov_b32 s5, 0x7ff00000
; GFX9-NEXT:    v_cmp_nge_f64_e64 vcc, |v[0:1]|, s[4:5]
; GFX9-NEXT:    v_cndmask_b32_e32 v0, 0, v4, vcc
; GFX9-NEXT:    v_mov_b32_e32 v4, 0x7ff80000
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v4, v5, vcc
; GFX9-NEXT:    v_cmp_nge_f64_e64 vcc, |v[2:3]|, s[4:5]
; GFX9-NEXT:    v_cndmask_b32_e32 v2, 0, v6, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v4, v7, vcc
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: frem_v2f64_const_one_denum:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cmp_ngt_f64_e64 s4, |v[0:1]|, 1.0
; GFX10-NEXT:    ; implicit-def: $vgpr4_vgpr5
; GFX10-NEXT:    s_and_saveexec_b32 s5, s4
; GFX10-NEXT:    s_xor_b32 s4, exec_lo, s5
; GFX10-NEXT:    s_cbranch_execz .LBB15_2
; GFX10-NEXT:  ; %bb.1: ; %frem.else16
; GFX10-NEXT:    v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, 1.0
; GFX10-NEXT:    v_and_b32_e32 v4, 0x80000000, v1
; GFX10-NEXT:    v_cndmask_b32_e32 v5, v1, v4, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e64 v4, v0, 0, vcc_lo
; GFX10-NEXT:  .LBB15_2: ; %Flow50
; GFX10-NEXT:    s_andn2_saveexec_b32 s4, s4
; GFX10-NEXT:    s_cbranch_execz .LBB15_8
; GFX10-NEXT:  ; %bb.3: ; %frem.compute15
; GFX10-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; GFX10-NEXT:    v_frexp_exp_i32_f64_e32 v6, v[0:1]
; GFX10-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; GFX10-NEXT:    v_add_nc_u32_e32 v8, -1, v6
; GFX10-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 26, v8
; GFX10-NEXT:    s_and_saveexec_b32 s5, vcc_lo
; GFX10-NEXT:    s_cbranch_execz .LBB15_7
; GFX10-NEXT:  ; %bb.4: ; %frem.loop_body23.preheader
; GFX10-NEXT:    v_add_nc_u32_e32 v8, 25, v6
; GFX10-NEXT:    s_mov_b32 s6, 0
; GFX10-NEXT:  .LBB15_5: ; %frem.loop_body23
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v7, v5
; GFX10-NEXT:    v_mov_b32_e32 v6, v4
; GFX10-NEXT:    v_subrev_nc_u32_e32 v8, 26, v8
; GFX10-NEXT:    v_rndne_f64_e32 v[4:5], v[6:7]
; GFX10-NEXT:    v_add_f64 v[4:5], v[6:7], -v[4:5]
; GFX10-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
; GFX10-NEXT:    v_add_f64 v[9:10], v[4:5], 1.0
; GFX10-NEXT:    v_cndmask_b32_e32 v5, v5, v10, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v4, v4, v9, vcc_lo
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v8
; GFX10-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; GFX10-NEXT:    s_or_b32 s6, vcc_lo, s6
; GFX10-NEXT:    s_andn2_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    s_cbranch_execnz .LBB15_5
; GFX10-NEXT:  ; %bb.6: ; %Flow48
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    v_mov_b32_e32 v4, v6
; GFX10-NEXT:    v_mov_b32_e32 v5, v7
; GFX10-NEXT:  .LBB15_7: ; %Flow49
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s5
; GFX10-NEXT:    v_subrev_nc_u32_e32 v6, 25, v8
; GFX10-NEXT:    v_ldexp_f64 v[4:5], v[4:5], v6
; GFX10-NEXT:    v_rndne_f64_e32 v[6:7], v[4:5]
; GFX10-NEXT:    v_add_f64 v[4:5], v[4:5], -v[6:7]
; GFX10-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
; GFX10-NEXT:    v_add_f64 v[6:7], v[4:5], 1.0
; GFX10-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX10-NEXT:    v_bfi_b32 v5, 0x7fffffff, v5, v1
; GFX10-NEXT:  .LBB15_8: ; %Flow51
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT:    v_cmp_ngt_f64_e64 s4, |v[2:3]|, 1.0
; GFX10-NEXT:    ; implicit-def: $vgpr6_vgpr7
; GFX10-NEXT:    s_and_saveexec_b32 s5, s4
; GFX10-NEXT:    s_xor_b32 s4, exec_lo, s5
; GFX10-NEXT:    s_cbranch_execz .LBB15_10
; GFX10-NEXT:  ; %bb.9: ; %frem.else
; GFX10-NEXT:    v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, 1.0
; GFX10-NEXT:    v_and_b32_e32 v6, 0x80000000, v3
; GFX10-NEXT:    v_cndmask_b32_e32 v7, v3, v6, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e64 v6, v2, 0, vcc_lo
; GFX10-NEXT:  .LBB15_10: ; %Flow46
; GFX10-NEXT:    s_andn2_saveexec_b32 s4, s4
; GFX10-NEXT:    s_cbranch_execz .LBB15_16
; GFX10-NEXT:  ; %bb.11: ; %frem.compute
; GFX10-NEXT:    v_frexp_mant_f64_e64 v[6:7], |v[2:3]|
; GFX10-NEXT:    v_frexp_exp_i32_f64_e32 v8, v[2:3]
; GFX10-NEXT:    v_ldexp_f64 v[6:7], v[6:7], 26
; GFX10-NEXT:    v_add_nc_u32_e32 v10, -1, v8
; GFX10-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 26, v10
; GFX10-NEXT:    s_and_saveexec_b32 s5, vcc_lo
; GFX10-NEXT:    s_cbranch_execz .LBB15_15
; GFX10-NEXT:  ; %bb.12: ; %frem.loop_body.preheader
; GFX10-NEXT:    v_add_nc_u32_e32 v10, 25, v8
; GFX10-NEXT:    s_mov_b32 s6, 0
; GFX10-NEXT:  .LBB15_13: ; %frem.loop_body
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v9, v7
; GFX10-NEXT:    v_mov_b32_e32 v8, v6
; GFX10-NEXT:    v_subrev_nc_u32_e32 v10, 26, v10
; GFX10-NEXT:    v_rndne_f64_e32 v[6:7], v[8:9]
; GFX10-NEXT:    v_add_f64 v[6:7], v[8:9], -v[6:7]
; GFX10-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX10-NEXT:    v_add_f64 v[11:12], v[6:7], 1.0
; GFX10-NEXT:    v_cndmask_b32_e32 v7, v7, v12, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v6, v6, v11, vcc_lo
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v10
; GFX10-NEXT:    v_ldexp_f64 v[6:7], v[6:7], 26
; GFX10-NEXT:    s_or_b32 s6, vcc_lo, s6
; GFX10-NEXT:    s_andn2_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    s_cbranch_execnz .LBB15_13
; GFX10-NEXT:  ; %bb.14: ; %Flow
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s6
; GFX10-NEXT:    v_mov_b32_e32 v6, v8
; GFX10-NEXT:    v_mov_b32_e32 v7, v9
; GFX10-NEXT:  .LBB15_15: ; %Flow45
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s5
; GFX10-NEXT:    v_subrev_nc_u32_e32 v8, 25, v10
; GFX10-NEXT:    v_ldexp_f64 v[6:7], v[6:7], v8
; GFX10-NEXT:    v_rndne_f64_e32 v[8:9], v[6:7]
; GFX10-NEXT:    v_add_f64 v[6:7], v[6:7], -v[8:9]
; GFX10-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX10-NEXT:    v_add_f64 v[8:9], v[6:7], 1.0
; GFX10-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX10-NEXT:    v_bfi_b32 v7, 0x7fffffff, v7, v3
; GFX10-NEXT:  .LBB15_16: ; %Flow47
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT:    v_cmp_nge_f64_e64 vcc_lo, |v[0:1]|, 0x7ff00000
; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0, v4, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v1, 0x7ff80000, v5, vcc_lo
; GFX10-NEXT:    v_cmp_nge_f64_e64 vcc_lo, |v[2:3]|, 0x7ff00000
; GFX10-NEXT:    v_cndmask_b32_e32 v2, 0, v6, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v3, 0x7ff80000, v7, vcc_lo
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: frem_v2f64_const_one_denum:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cmp_ngt_f64_e64 s0, |v[0:1]|, 1.0
; GFX11-NEXT:    ; implicit-def: $vgpr4_vgpr5
; GFX11-NEXT:    s_and_saveexec_b32 s1, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX11-NEXT:    s_cbranch_execz .LBB15_2
; GFX11-NEXT:  ; %bb.1: ; %frem.else16
; GFX11-NEXT:    v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, 1.0
; GFX11-NEXT:    v_and_b32_e32 v4, 0x80000000, v1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_cndmask_b32_e32 v5, v1, v4, vcc_lo
; GFX11-NEXT:    v_cndmask_b32_e64 v4, v0, 0, vcc_lo
; GFX11-NEXT:  .LBB15_2: ; %Flow50
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB15_8
; GFX11-NEXT:  ; %bb.3: ; %frem.compute15
; GFX11-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; GFX11-NEXT:    v_frexp_exp_i32_f64_e32 v6, v[0:1]
; GFX11-NEXT:    s_mov_b32 s1, exec_lo
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; GFX11-NEXT:    v_add_nc_u32_e32 v8, -1, v6
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_cmpx_lt_i32_e32 26, v8
; GFX11-NEXT:    s_cbranch_execz .LBB15_7
; GFX11-NEXT:  ; %bb.4: ; %frem.loop_body23.preheader
; GFX11-NEXT:    v_add_nc_u32_e32 v8, 25, v6
; GFX11-NEXT:    s_mov_b32 s2, 0
; GFX11-NEXT:    .p2align 6
; GFX11-NEXT:  .LBB15_5: ; %frem.loop_body23
; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT:    v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX11-NEXT:    v_subrev_nc_u32_e32 v8, 26, v8
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_rndne_f64_e32 v[4:5], v[6:7]
; GFX11-NEXT:    v_add_f64 v[4:5], v[6:7], -v[4:5]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
; GFX11-NEXT:    v_add_f64 v[9:10], v[4:5], 1.0
; GFX11-NEXT:    v_dual_cndmask_b32 v5, v5, v10 :: v_dual_cndmask_b32 v4, v4, v9
; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v8
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; GFX11-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX11-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX11-NEXT:    s_cbranch_execnz .LBB15_5
; GFX11-NEXT:  ; %bb.6: ; %Flow48
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX11-NEXT:    v_dual_mov_b32 v4, v6 :: v_dual_mov_b32 v5, v7
; GFX11-NEXT:  .LBB15_7: ; %Flow49
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX11-NEXT:    v_subrev_nc_u32_e32 v6, 25, v8
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_ldexp_f64 v[4:5], v[4:5], v6
; GFX11-NEXT:    v_rndne_f64_e32 v[6:7], v[4:5]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_add_f64 v[4:5], v[4:5], -v[6:7]
; GFX11-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
; GFX11-NEXT:    v_add_f64 v[6:7], v[4:5], 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_dual_cndmask_b32 v4, v4, v6 :: v_dual_cndmask_b32 v5, v5, v7
; GFX11-NEXT:    v_bfi_b32 v5, 0x7fffffff, v5, v1
; GFX11-NEXT:  .LBB15_8: ; %Flow51
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    v_cmp_ngt_f64_e64 s0, |v[2:3]|, 1.0
; GFX11-NEXT:    ; implicit-def: $vgpr6_vgpr7
; GFX11-NEXT:    s_and_saveexec_b32 s1, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX11-NEXT:    s_cbranch_execz .LBB15_10
; GFX11-NEXT:  ; %bb.9: ; %frem.else
; GFX11-NEXT:    v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, 1.0
; GFX11-NEXT:    v_and_b32_e32 v6, 0x80000000, v3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_cndmask_b32_e32 v7, v3, v6, vcc_lo
; GFX11-NEXT:    v_cndmask_b32_e64 v6, v2, 0, vcc_lo
; GFX11-NEXT:  .LBB15_10: ; %Flow46
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB15_16
; GFX11-NEXT:  ; %bb.11: ; %frem.compute
; GFX11-NEXT:    v_frexp_mant_f64_e64 v[6:7], |v[2:3]|
; GFX11-NEXT:    v_frexp_exp_i32_f64_e32 v8, v[2:3]
; GFX11-NEXT:    s_mov_b32 s1, exec_lo
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT:    v_ldexp_f64 v[6:7], v[6:7], 26
; GFX11-NEXT:    v_add_nc_u32_e32 v10, -1, v8
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_cmpx_lt_i32_e32 26, v10
; GFX11-NEXT:    s_cbranch_execz .LBB15_15
; GFX11-NEXT:  ; %bb.12: ; %frem.loop_body.preheader
; GFX11-NEXT:    v_add_nc_u32_e32 v10, 25, v8
; GFX11-NEXT:    s_mov_b32 s2, 0
; GFX11-NEXT:    .p2align 6
; GFX11-NEXT:  .LBB15_13: ; %frem.loop_body
; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT:    v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
; GFX11-NEXT:    v_subrev_nc_u32_e32 v10, 26, v10
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_rndne_f64_e32 v[6:7], v[8:9]
; GFX11-NEXT:    v_add_f64 v[6:7], v[8:9], -v[6:7]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX11-NEXT:    v_add_f64 v[11:12], v[6:7], 1.0
; GFX11-NEXT:    v_dual_cndmask_b32 v7, v7, v12 :: v_dual_cndmask_b32 v6, v6, v11
; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v10
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT:    v_ldexp_f64 v[6:7], v[6:7], 26
; GFX11-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX11-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX11-NEXT:    s_cbranch_execnz .LBB15_13
; GFX11-NEXT:  ; %bb.14: ; %Flow
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX11-NEXT:    v_dual_mov_b32 v6, v8 :: v_dual_mov_b32 v7, v9
; GFX11-NEXT:  .LBB15_15: ; %Flow45
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX11-NEXT:    v_subrev_nc_u32_e32 v8, 25, v10
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_ldexp_f64 v[6:7], v[6:7], v8
; GFX11-NEXT:    v_rndne_f64_e32 v[8:9], v[6:7]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_add_f64 v[6:7], v[6:7], -v[8:9]
; GFX11-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX11-NEXT:    v_add_f64 v[8:9], v[6:7], 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_dual_cndmask_b32 v6, v6, v8 :: v_dual_cndmask_b32 v7, v7, v9
; GFX11-NEXT:    v_bfi_b32 v7, 0x7fffffff, v7, v3
; GFX11-NEXT:  .LBB15_16: ; %Flow47
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    v_cmp_nge_f64_e64 vcc_lo, |v[0:1]|, 0x7ff00000
; GFX11-NEXT:    v_dual_cndmask_b32 v0, 0, v4 :: v_dual_cndmask_b32 v1, 0x7ff80000, v5
; GFX11-NEXT:    v_cmp_nge_f64_e64 vcc_lo, |v[2:3]|, 0x7ff00000
; GFX11-NEXT:    v_dual_cndmask_b32 v2, 0, v6 :: v_dual_cndmask_b32 v3, 0x7ff80000, v7
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-LABEL: frem_v2f64_const_one_denum:
; GFX1150:       ; %bb.0:
; GFX1150-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-NEXT:    v_cmp_ngt_f64_e64 s0, |v[0:1]|, 1.0
; GFX1150-NEXT:    ; implicit-def: $vgpr4_vgpr5
; GFX1150-NEXT:    s_and_saveexec_b32 s1, s0
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX1150-NEXT:    s_cbranch_execz .LBB15_2
; GFX1150-NEXT:  ; %bb.1: ; %frem.else16
; GFX1150-NEXT:    v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, 1.0
; GFX1150-NEXT:    v_and_b32_e32 v4, 0x80000000, v1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_cndmask_b32_e32 v5, v1, v4, vcc_lo
; GFX1150-NEXT:    v_cndmask_b32_e64 v4, v0, 0, vcc_lo
; GFX1150-NEXT:  .LBB15_2: ; %Flow50
; GFX1150-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1150-NEXT:    s_cbranch_execz .LBB15_8
; GFX1150-NEXT:  ; %bb.3: ; %frem.compute15
; GFX1150-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; GFX1150-NEXT:    v_frexp_exp_i32_f64_e32 v6, v[0:1]
; GFX1150-NEXT:    s_mov_b32 s1, exec_lo
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1150-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; GFX1150-NEXT:    v_add_nc_u32_e32 v8, -1, v6
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_cmpx_lt_i32_e32 26, v8
; GFX1150-NEXT:    s_cbranch_execz .LBB15_7
; GFX1150-NEXT:  ; %bb.4: ; %frem.loop_body23.preheader
; GFX1150-NEXT:    v_add_nc_u32_e32 v8, 25, v6
; GFX1150-NEXT:    s_mov_b32 s2, 0
; GFX1150-NEXT:    .p2align 6
; GFX1150-NEXT:  .LBB15_5: ; %frem.loop_body23
; GFX1150-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1150-NEXT:    v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX1150-NEXT:    v_subrev_nc_u32_e32 v8, 26, v8
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_rndne_f64_e32 v[4:5], v[6:7]
; GFX1150-NEXT:    v_add_f64 v[4:5], v[6:7], -v[4:5]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
; GFX1150-NEXT:    v_add_f64 v[9:10], v[4:5], 1.0
; GFX1150-NEXT:    v_dual_cndmask_b32 v5, v5, v10 :: v_dual_cndmask_b32 v4, v4, v9
; GFX1150-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v8
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; GFX1150-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1150-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1150-NEXT:    s_cbranch_execnz .LBB15_5
; GFX1150-NEXT:  ; %bb.6: ; %Flow48
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1150-NEXT:    v_dual_mov_b32 v4, v6 :: v_dual_mov_b32 v5, v7
; GFX1150-NEXT:  .LBB15_7: ; %Flow49
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1150-NEXT:    v_subrev_nc_u32_e32 v6, 25, v8
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f64 v[4:5], v[4:5], v6
; GFX1150-NEXT:    v_rndne_f64_e32 v[6:7], v[4:5]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_add_f64 v[4:5], v[4:5], -v[6:7]
; GFX1150-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
; GFX1150-NEXT:    v_add_f64 v[6:7], v[4:5], 1.0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_dual_cndmask_b32 v4, v4, v6 :: v_dual_cndmask_b32 v5, v5, v7
; GFX1150-NEXT:    v_bfi_b32 v5, 0x7fffffff, v5, v1
; GFX1150-NEXT:  .LBB15_8: ; %Flow51
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1150-NEXT:    v_cmp_ngt_f64_e64 s0, |v[2:3]|, 1.0
; GFX1150-NEXT:    ; implicit-def: $vgpr6_vgpr7
; GFX1150-NEXT:    s_and_saveexec_b32 s1, s0
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX1150-NEXT:    s_cbranch_execz .LBB15_10
; GFX1150-NEXT:  ; %bb.9: ; %frem.else
; GFX1150-NEXT:    v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, 1.0
; GFX1150-NEXT:    v_and_b32_e32 v6, 0x80000000, v3
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_cndmask_b32_e32 v7, v3, v6, vcc_lo
; GFX1150-NEXT:    v_cndmask_b32_e64 v6, v2, 0, vcc_lo
; GFX1150-NEXT:  .LBB15_10: ; %Flow46
; GFX1150-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1150-NEXT:    s_cbranch_execz .LBB15_16
; GFX1150-NEXT:  ; %bb.11: ; %frem.compute
; GFX1150-NEXT:    v_frexp_mant_f64_e64 v[6:7], |v[2:3]|
; GFX1150-NEXT:    v_frexp_exp_i32_f64_e32 v8, v[2:3]
; GFX1150-NEXT:    s_mov_b32 s1, exec_lo
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1150-NEXT:    v_ldexp_f64 v[6:7], v[6:7], 26
; GFX1150-NEXT:    v_add_nc_u32_e32 v10, -1, v8
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_cmpx_lt_i32_e32 26, v10
; GFX1150-NEXT:    s_cbranch_execz .LBB15_15
; GFX1150-NEXT:  ; %bb.12: ; %frem.loop_body.preheader
; GFX1150-NEXT:    v_add_nc_u32_e32 v10, 25, v8
; GFX1150-NEXT:    s_mov_b32 s2, 0
; GFX1150-NEXT:    .p2align 6
; GFX1150-NEXT:  .LBB15_13: ; %frem.loop_body
; GFX1150-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1150-NEXT:    v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
; GFX1150-NEXT:    v_subrev_nc_u32_e32 v10, 26, v10
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_rndne_f64_e32 v[6:7], v[8:9]
; GFX1150-NEXT:    v_add_f64 v[6:7], v[8:9], -v[6:7]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX1150-NEXT:    v_add_f64 v[11:12], v[6:7], 1.0
; GFX1150-NEXT:    v_dual_cndmask_b32 v7, v7, v12 :: v_dual_cndmask_b32 v6, v6, v11
; GFX1150-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v10
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT:    v_ldexp_f64 v[6:7], v[6:7], 26
; GFX1150-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1150-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1150-NEXT:    s_cbranch_execnz .LBB15_13
; GFX1150-NEXT:  ; %bb.14: ; %Flow
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1150-NEXT:    v_dual_mov_b32 v6, v8 :: v_dual_mov_b32 v7, v9
; GFX1150-NEXT:  .LBB15_15: ; %Flow45
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1150-NEXT:    v_subrev_nc_u32_e32 v8, 25, v10
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f64 v[6:7], v[6:7], v8
; GFX1150-NEXT:    v_rndne_f64_e32 v[8:9], v[6:7]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_add_f64 v[6:7], v[6:7], -v[8:9]
; GFX1150-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX1150-NEXT:    v_add_f64 v[8:9], v[6:7], 1.0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_dual_cndmask_b32 v6, v6, v8 :: v_dual_cndmask_b32 v7, v7, v9
; GFX1150-NEXT:    v_bfi_b32 v7, 0x7fffffff, v7, v3
; GFX1150-NEXT:  .LBB15_16: ; %Flow47
; GFX1150-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1150-NEXT:    v_cmp_nge_f64_e64 vcc_lo, |v[0:1]|, 0x7ff00000
; GFX1150-NEXT:    v_dual_cndmask_b32 v0, 0, v4 :: v_dual_cndmask_b32 v1, 0x7ff80000, v5
; GFX1150-NEXT:    v_cmp_nge_f64_e64 vcc_lo, |v[2:3]|, 0x7ff00000
; GFX1150-NEXT:    v_dual_cndmask_b32 v2, 0, v6 :: v_dual_cndmask_b32 v3, 0x7ff80000, v7
; GFX1150-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: frem_v2f64_const_one_denum:
; GFX1200:       ; %bb.0:
; GFX1200-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT:    s_wait_expcnt 0x0
; GFX1200-NEXT:    s_wait_samplecnt 0x0
; GFX1200-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-NEXT:    s_wait_kmcnt 0x0
; GFX1200-NEXT:    v_cmp_ngt_f64_e64 s0, |v[0:1]|, 1.0
; GFX1200-NEXT:    ; implicit-def: $vgpr4_vgpr5
; GFX1200-NEXT:    s_and_saveexec_b32 s1, s0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX1200-NEXT:    s_cbranch_execz .LBB15_2
; GFX1200-NEXT:  ; %bb.1: ; %frem.else16
; GFX1200-NEXT:    v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, 1.0
; GFX1200-NEXT:    v_and_b32_e32 v4, 0x80000000, v1
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT:    v_cndmask_b32_e32 v5, v1, v4, vcc_lo
; GFX1200-NEXT:    v_cndmask_b32_e64 v4, v0, 0, vcc_lo
; GFX1200-NEXT:  .LBB15_2: ; %Flow50
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1200-NEXT:    s_cbranch_execz .LBB15_8
; GFX1200-NEXT:  ; %bb.3: ; %frem.compute15
; GFX1200-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; GFX1200-NEXT:    v_frexp_exp_i32_f64_e32 v6, v[0:1]
; GFX1200-NEXT:    s_mov_b32 s1, exec_lo
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; GFX1200-NEXT:    v_add_nc_u32_e32 v8, -1, v6
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_cmpx_lt_i32_e32 26, v8
; GFX1200-NEXT:    s_cbranch_execz .LBB15_7
; GFX1200-NEXT:  ; %bb.4: ; %frem.loop_body23.preheader
; GFX1200-NEXT:    v_add_nc_u32_e32 v8, 25, v6
; GFX1200-NEXT:    s_mov_b32 s2, 0
; GFX1200-NEXT:  .LBB15_5: ; %frem.loop_body23
; GFX1200-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT:    v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX1200-NEXT:    v_subrev_nc_u32_e32 v8, 26, v8
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_rndne_f64_e32 v[4:5], v[6:7]
; GFX1200-NEXT:    v_add_f64_e64 v[4:5], v[6:7], -v[4:5]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
; GFX1200-NEXT:    v_add_f64_e32 v[9:10], 1.0, v[4:5]
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_dual_cndmask_b32 v5, v5, v10 :: v_dual_cndmask_b32 v4, v4, v9
; GFX1200-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v8
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1200-NEXT:    s_cbranch_execnz .LBB15_5
; GFX1200-NEXT:  ; %bb.6: ; %Flow48
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1200-NEXT:    v_dual_mov_b32 v4, v6 :: v_dual_mov_b32 v5, v7
; GFX1200-NEXT:  .LBB15_7: ; %Flow49
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1200-NEXT:    v_subrev_nc_u32_e32 v6, 25, v8
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_ldexp_f64 v[4:5], v[4:5], v6
; GFX1200-NEXT:    v_rndne_f64_e32 v[6:7], v[4:5]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_add_f64_e64 v[4:5], v[4:5], -v[6:7]
; GFX1200-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
; GFX1200-NEXT:    v_add_f64_e32 v[6:7], 1.0, v[4:5]
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_dual_cndmask_b32 v4, v4, v6 :: v_dual_cndmask_b32 v5, v5, v7
; GFX1200-NEXT:    v_bfi_b32 v5, 0x7fffffff, v5, v1
; GFX1200-NEXT:  .LBB15_8: ; %Flow51
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1200-NEXT:    v_cmp_ngt_f64_e64 s0, |v[2:3]|, 1.0
; GFX1200-NEXT:    ; implicit-def: $vgpr6_vgpr7
; GFX1200-NEXT:    s_and_saveexec_b32 s1, s0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_xor_b32 s0, exec_lo, s1
; GFX1200-NEXT:    s_cbranch_execz .LBB15_10
; GFX1200-NEXT:  ; %bb.9: ; %frem.else
; GFX1200-NEXT:    v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, 1.0
; GFX1200-NEXT:    v_and_b32_e32 v6, 0x80000000, v3
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT:    v_cndmask_b32_e32 v7, v3, v6, vcc_lo
; GFX1200-NEXT:    v_cndmask_b32_e64 v6, v2, 0, vcc_lo
; GFX1200-NEXT:  .LBB15_10: ; %Flow46
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX1200-NEXT:    s_cbranch_execz .LBB15_16
; GFX1200-NEXT:  ; %bb.11: ; %frem.compute
; GFX1200-NEXT:    v_frexp_mant_f64_e64 v[6:7], |v[2:3]|
; GFX1200-NEXT:    v_frexp_exp_i32_f64_e32 v8, v[2:3]
; GFX1200-NEXT:    s_mov_b32 s1, exec_lo
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT:    v_ldexp_f64 v[6:7], v[6:7], 26
; GFX1200-NEXT:    v_add_nc_u32_e32 v10, -1, v8
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_cmpx_lt_i32_e32 26, v10
; GFX1200-NEXT:    s_cbranch_execz .LBB15_15
; GFX1200-NEXT:  ; %bb.12: ; %frem.loop_body.preheader
; GFX1200-NEXT:    v_add_nc_u32_e32 v10, 25, v8
; GFX1200-NEXT:    s_mov_b32 s2, 0
; GFX1200-NEXT:  .LBB15_13: ; %frem.loop_body
; GFX1200-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT:    v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
; GFX1200-NEXT:    v_subrev_nc_u32_e32 v10, 26, v10
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_rndne_f64_e32 v[6:7], v[8:9]
; GFX1200-NEXT:    v_add_f64_e64 v[6:7], v[8:9], -v[6:7]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX1200-NEXT:    v_add_f64_e32 v[11:12], 1.0, v[6:7]
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_dual_cndmask_b32 v7, v7, v12 :: v_dual_cndmask_b32 v6, v6, v11
; GFX1200-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v10
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-NEXT:    v_ldexp_f64 v[6:7], v[6:7], 26
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s2
; GFX1200-NEXT:    s_cbranch_execnz .LBB15_13
; GFX1200-NEXT:  ; %bb.14: ; %Flow
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX1200-NEXT:    v_dual_mov_b32 v6, v8 :: v_dual_mov_b32 v7, v9
; GFX1200-NEXT:  .LBB15_15: ; %Flow45
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX1200-NEXT:    v_subrev_nc_u32_e32 v8, 25, v10
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_ldexp_f64 v[6:7], v[6:7], v8
; GFX1200-NEXT:    v_rndne_f64_e32 v[8:9], v[6:7]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_add_f64_e64 v[6:7], v[6:7], -v[8:9]
; GFX1200-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX1200-NEXT:    v_add_f64_e32 v[8:9], 1.0, v[6:7]
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_dual_cndmask_b32 v6, v6, v8 :: v_dual_cndmask_b32 v7, v7, v9
; GFX1200-NEXT:    v_bfi_b32 v7, 0x7fffffff, v7, v3
; GFX1200-NEXT:  .LBB15_16: ; %Flow47
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX1200-NEXT:    v_cmp_nge_f64_e64 vcc_lo, |v[0:1]|, 0x7ff00000
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_dual_cndmask_b32 v0, 0, v4 :: v_dual_cndmask_b32 v1, 0x7ff80000, v5
; GFX1200-NEXT:    v_cmp_nge_f64_e64 vcc_lo, |v[2:3]|, 0x7ff00000
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_dual_cndmask_b32 v2, 0, v6 :: v_dual_cndmask_b32 v3, 0x7ff80000, v7
; GFX1200-NEXT:    s_setpc_b64 s[30:31]
   %r1 = frem  <2 x double> %in, <double 1.0, double 1.0>
  ret <2 x double> %r1
}

define <2 x double> @frem_v2f64_const() #0 {
; SI-LABEL: frem_v2f64_const:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_mov_b32_e32 v0, 0
; SI-NEXT:    v_mov_b32_e32 v1, 0x3ff00000
; SI-NEXT:    v_mov_b32_e32 v2, 0
; SI-NEXT:    v_mov_b32_e32 v3, 0
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; CI-LABEL: frem_v2f64_const:
; CI:       ; %bb.0:
; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-NEXT:    v_mov_b32_e32 v0, 0
; CI-NEXT:    v_mov_b32_e32 v1, 0x3ff00000
; CI-NEXT:    v_mov_b32_e32 v2, 0
; CI-NEXT:    v_mov_b32_e32 v3, 0
; CI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: frem_v2f64_const:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_mov_b32_e32 v0, 0
; VI-NEXT:    v_mov_b32_e32 v1, 0x3ff00000
; VI-NEXT:    v_mov_b32_e32 v2, 0
; VI-NEXT:    v_mov_b32_e32 v3, 0
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: frem_v2f64_const:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v0, 0
; GFX9-NEXT:    v_mov_b32_e32 v1, 0x3ff00000
; GFX9-NEXT:    v_mov_b32_e32 v2, 0
; GFX9-NEXT:    v_mov_b32_e32 v3, 0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: frem_v2f64_const:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_mov_b32_e32 v0, 0
; GFX10-NEXT:    v_mov_b32_e32 v1, 0x3ff00000
; GFX10-NEXT:    v_mov_b32_e32 v2, 0
; GFX10-NEXT:    v_mov_b32_e32 v3, 0
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: frem_v2f64_const:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x3ff00000
; GFX11-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-LABEL: frem_v2f64_const:
; GFX1150:       ; %bb.0:
; GFX1150-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x3ff00000
; GFX1150-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
; GFX1150-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: frem_v2f64_const:
; GFX1200:       ; %bb.0:
; GFX1200-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT:    s_wait_expcnt 0x0
; GFX1200-NEXT:    s_wait_samplecnt 0x0
; GFX1200-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-NEXT:    s_wait_kmcnt 0x0
; GFX1200-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x3ff00000
; GFX1200-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
; GFX1200-NEXT:    s_setpc_b64 s[30:31]
   %r0 = frem  <2 x double> <double 1.0, double 1.0>, <double 2.0, double 1.0>
  ret <2 x double> %r0
}

define half @frem_f16_uniform(half inreg %in1, half inreg %in2) #0 {
; SI-LABEL: frem_f16_uniform:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cvt_f32_f16_e64 v1, |s16|
; SI-NEXT:    v_cvt_f32_f16_e64 v0, |s17|
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v0
; SI-NEXT:    s_cbranch_vccz .LBB17_4
; SI-NEXT:  ; %bb.1: ; %frem.compute
; SI-NEXT:    s_mov_b32 s7, 0x7f800000
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v1|, s7
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v2, v1
; SI-NEXT:    s_and_b64 s[4:5], vcc, exec
; SI-NEXT:    v_readfirstlane_b32 s4, v2
; SI-NEXT:    v_frexp_mant_f32_e32 v2, v1
; SI-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, s7
; SI-NEXT:    v_frexp_mant_f32_e32 v2, v0
; SI-NEXT:    s_cselect_b32 s6, s4, 0
; SI-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v0, v0
; SI-NEXT:    s_and_b64 s[4:5], vcc, exec
; SI-NEXT:    v_readfirstlane_b32 s4, v0
; SI-NEXT:    v_ldexp_f32_e64 v0, v2, 1
; SI-NEXT:    v_div_scale_f32 v3, s[8:9], v0, v0, 1.0
; SI-NEXT:    v_rcp_f32_e32 v4, v3
; SI-NEXT:    v_ldexp_f32_e64 v1, v1, 11
; SI-NEXT:    v_div_scale_f32 v2, vcc, 1.0, v0, 1.0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
; SI-NEXT:    v_fma_f32 v4, v5, v4, v4
; SI-NEXT:    v_mul_f32_e32 v5, v2, v4
; SI-NEXT:    s_cselect_b32 s7, s4, 0
; SI-NEXT:    v_fma_f32 v6, -v3, v5, v2
; SI-NEXT:    s_add_i32 s4, s7, -1
; SI-NEXT:    v_fma_f32 v5, v6, v4, v5
; SI-NEXT:    s_not_b32 s5, s4
; SI-NEXT:    v_fma_f32 v2, -v3, v5, v2
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    s_add_i32 s5, s5, s6
; SI-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
; SI-NEXT:    v_div_fixup_f32 v2, v2, v0, 1.0
; SI-NEXT:    s_cmp_lt_i32 s5, 12
; SI-NEXT:    s_cbranch_scc1 .LBB17_5
; SI-NEXT:  ; %bb.2: ; %frem.loop_body.preheader
; SI-NEXT:    s_sub_i32 s5, s6, s7
; SI-NEXT:    s_add_i32 s5, s5, 11
; SI-NEXT:  .LBB17_3: ; %frem.loop_body
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v3, v1
; SI-NEXT:    v_mul_f32_e32 v1, v3, v2
; SI-NEXT:    v_rndne_f32_e32 v1, v1
; SI-NEXT:    v_fma_f32 v1, -v1, v0, v3
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v1
; SI-NEXT:    v_add_f32_e32 v4, v1, v0
; SI-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
; SI-NEXT:    s_add_i32 s5, s5, -11
; SI-NEXT:    v_ldexp_f32_e64 v1, v1, 11
; SI-NEXT:    s_cmp_gt_i32 s5, 11
; SI-NEXT:    s_cbranch_scc1 .LBB17_3
; SI-NEXT:    s_branch .LBB17_6
; SI-NEXT:  .LBB17_4: ; %frem.else
; SI-NEXT:    s_and_b32 s6, s16, 0xffff8000
; SI-NEXT:    v_cmp_eq_f32_e32 vcc, v1, v0
; SI-NEXT:    s_and_b64 s[4:5], vcc, exec
; SI-NEXT:    s_cselect_b32 s4, s6, s16
; SI-NEXT:    v_mov_b32_e32 v0, s4
; SI-NEXT:    s_branch .LBB17_7
; SI-NEXT:  .LBB17_5:
; SI-NEXT:    v_mov_b32_e32 v3, v1
; SI-NEXT:  .LBB17_6: ; %frem.loop_exit
; SI-NEXT:    s_add_i32 s5, s5, -10
; SI-NEXT:    v_ldexp_f32_e64 v1, v3, s5
; SI-NEXT:    v_mul_f32_e32 v2, v1, v2
; SI-NEXT:    v_rndne_f32_e32 v2, v2
; SI-NEXT:    v_fma_f32 v1, -v2, v0, v1
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v1
; SI-NEXT:    v_add_f32_e32 v0, v1, v0
; SI-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; SI-NEXT:    v_ldexp_f32_e64 v0, v0, s4
; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-NEXT:    s_and_b32 s4, s16, 0xffff8000
; SI-NEXT:    v_and_b32_e32 v0, 0x7fff, v0
; SI-NEXT:    v_or_b32_e32 v0, s4, v0
; SI-NEXT:  .LBB17_7:
; SI-NEXT:    v_cvt_f32_f16_e32 v1, s17
; SI-NEXT:    s_mov_b32 s4, 0x7f800000
; SI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v1
; SI-NEXT:    v_cvt_f32_f16_e64 v1, |s16|
; SI-NEXT:    v_cmp_nle_f32_e64 s[4:5], s4, v1
; SI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; SI-NEXT:    v_mov_b32_e32 v1, 0x7e00
; SI-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; CI-LABEL: frem_f16_uniform:
; CI:       ; %bb.0:
; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-NEXT:    v_cvt_f32_f16_e64 v1, |s16|
; CI-NEXT:    v_cvt_f32_f16_e64 v0, |s17|
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v0
; CI-NEXT:    s_cbranch_vccz .LBB17_4
; CI-NEXT:  ; %bb.1: ; %frem.compute
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v5, v1
; CI-NEXT:    v_frexp_mant_f32_e32 v1, v1
; CI-NEXT:    v_ldexp_f32_e64 v4, v1, 11
; CI-NEXT:    v_frexp_mant_f32_e32 v1, v0
; CI-NEXT:    v_ldexp_f32_e64 v1, v1, 1
; CI-NEXT:    v_div_scale_f32 v7, s[4:5], v1, v1, 1.0
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v6, v0
; CI-NEXT:    v_add_i32_e32 v0, vcc, -1, v6
; CI-NEXT:    v_not_b32_e32 v2, v0
; CI-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
; CI-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v1, 1.0
; CI-NEXT:    v_rcp_f32_e32 v8, v7
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
; CI-NEXT:    v_fma_f32 v8, v9, v8, v8
; CI-NEXT:    v_mul_f32_e32 v9, v3, v8
; CI-NEXT:    v_fma_f32 v10, -v7, v9, v3
; CI-NEXT:    v_fma_f32 v9, v10, v8, v9
; CI-NEXT:    v_fma_f32 v3, -v7, v9, v3
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v3, v3, v8, v9
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v2
; CI-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; CI-NEXT:    s_cbranch_vccnz .LBB17_5
; CI-NEXT:  ; %bb.2: ; %frem.loop_body.preheader
; CI-NEXT:    v_sub_i32_e32 v2, vcc, v5, v6
; CI-NEXT:    v_add_i32_e32 v2, vcc, 11, v2
; CI-NEXT:  .LBB17_3: ; %frem.loop_body
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v5, v4
; CI-NEXT:    v_mul_f32_e32 v4, v5, v3
; CI-NEXT:    v_rndne_f32_e32 v4, v4
; CI-NEXT:    v_fma_f32 v4, -v4, v1, v5
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; CI-NEXT:    v_add_f32_e32 v6, v4, v1
; CI-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
; CI-NEXT:    v_add_i32_e32 v2, vcc, -11, v2
; CI-NEXT:    v_ldexp_f32_e64 v4, v4, 11
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v2
; CI-NEXT:    s_cbranch_vccnz .LBB17_3
; CI-NEXT:    s_branch .LBB17_6
; CI-NEXT:  .LBB17_4: ; %frem.else
; CI-NEXT:    s_and_b32 s6, s16, 0xffff8000
; CI-NEXT:    v_cmp_eq_f32_e32 vcc, v1, v0
; CI-NEXT:    s_and_b64 s[4:5], vcc, exec
; CI-NEXT:    s_cselect_b32 s4, s6, s16
; CI-NEXT:    v_mov_b32_e32 v0, s4
; CI-NEXT:    s_branch .LBB17_7
; CI-NEXT:  .LBB17_5:
; CI-NEXT:    v_mov_b32_e32 v5, v4
; CI-NEXT:  .LBB17_6: ; %frem.loop_exit
; CI-NEXT:    v_add_i32_e32 v2, vcc, -10, v2
; CI-NEXT:    v_ldexp_f32_e32 v2, v5, v2
; CI-NEXT:    v_mul_f32_e32 v3, v2, v3
; CI-NEXT:    v_rndne_f32_e32 v3, v3
; CI-NEXT:    v_fma_f32 v2, -v3, v1, v2
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v2
; CI-NEXT:    v_add_f32_e32 v1, v2, v1
; CI-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; CI-NEXT:    v_ldexp_f32_e32 v0, v1, v0
; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; CI-NEXT:    s_and_b32 s4, s16, 0xffff8000
; CI-NEXT:    v_and_b32_e32 v0, 0x7fff, v0
; CI-NEXT:    v_or_b32_e32 v0, s4, v0
; CI-NEXT:  .LBB17_7:
; CI-NEXT:    v_cvt_f32_f16_e32 v1, s17
; CI-NEXT:    s_mov_b32 s4, 0x7f800000
; CI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v1
; CI-NEXT:    v_cvt_f32_f16_e64 v1, |s16|
; CI-NEXT:    v_cmp_nle_f32_e64 s[4:5], s4, v1
; CI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; CI-NEXT:    v_mov_b32_e32 v1, 0x7e00
; CI-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; CI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: frem_f16_uniform:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cvt_f32_f16_e64 v1, |s16|
; VI-NEXT:    v_cvt_f32_f16_e64 v0, |s17|
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v0
; VI-NEXT:    s_cbranch_vccz .LBB17_4
; VI-NEXT:  ; %bb.1: ; %frem.compute
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v5, v1
; VI-NEXT:    v_frexp_mant_f32_e32 v1, v1
; VI-NEXT:    v_ldexp_f32 v4, v1, 11
; VI-NEXT:    v_frexp_mant_f32_e32 v1, v0
; VI-NEXT:    v_ldexp_f32 v1, v1, 1
; VI-NEXT:    v_div_scale_f32 v7, s[4:5], v1, v1, 1.0
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v6, v0
; VI-NEXT:    v_add_u32_e32 v0, vcc, -1, v6
; VI-NEXT:    v_not_b32_e32 v2, v0
; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v5
; VI-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v1, 1.0
; VI-NEXT:    v_rcp_f32_e32 v8, v7
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
; VI-NEXT:    v_fma_f32 v8, v9, v8, v8
; VI-NEXT:    v_mul_f32_e32 v9, v3, v8
; VI-NEXT:    v_fma_f32 v10, -v7, v9, v3
; VI-NEXT:    v_fma_f32 v9, v10, v8, v9
; VI-NEXT:    v_fma_f32 v3, -v7, v9, v3
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; VI-NEXT:    v_div_fmas_f32 v3, v3, v8, v9
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v2
; VI-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; VI-NEXT:    s_cbranch_vccnz .LBB17_5
; VI-NEXT:  ; %bb.2: ; %frem.loop_body.preheader
; VI-NEXT:    v_sub_u32_e32 v2, vcc, v5, v6
; VI-NEXT:    v_add_u32_e32 v2, vcc, 11, v2
; VI-NEXT:  .LBB17_3: ; %frem.loop_body
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v5, v4
; VI-NEXT:    v_mul_f32_e32 v4, v5, v3
; VI-NEXT:    v_rndne_f32_e32 v4, v4
; VI-NEXT:    v_fma_f32 v4, -v4, v1, v5
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; VI-NEXT:    v_add_f32_e32 v6, v4, v1
; VI-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
; VI-NEXT:    v_add_u32_e32 v2, vcc, -11, v2
; VI-NEXT:    v_ldexp_f32 v4, v4, 11
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v2
; VI-NEXT:    s_cbranch_vccnz .LBB17_3
; VI-NEXT:    s_branch .LBB17_6
; VI-NEXT:  .LBB17_4: ; %frem.else
; VI-NEXT:    s_and_b32 s4, 0x8000, s16
; VI-NEXT:    v_cmp_eq_f32_e32 vcc, v1, v0
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
; VI-NEXT:    s_branch .LBB17_7
; VI-NEXT:  .LBB17_5:
; VI-NEXT:    v_mov_b32_e32 v5, v4
; VI-NEXT:  .LBB17_6: ; %frem.loop_exit
; VI-NEXT:    v_add_u32_e32 v2, vcc, -10, v2
; VI-NEXT:    v_ldexp_f32 v2, v5, v2
; VI-NEXT:    v_mul_f32_e32 v3, v2, v3
; VI-NEXT:    v_rndne_f32_e32 v3, v3
; VI-NEXT:    v_fma_f32 v2, -v3, v1, v2
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v2
; VI-NEXT:    v_add_f32_e32 v1, v2, v1
; VI-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; VI-NEXT:    v_ldexp_f32 v0, v1, v0
; VI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; VI-NEXT:    s_movk_i32 s4, 0x7fff
; VI-NEXT:    v_mov_b32_e32 v1, s16
; VI-NEXT:    v_bfi_b32 v0, s4, v0, v1
; VI-NEXT:  .LBB17_7:
; VI-NEXT:    v_mov_b32_e32 v1, 0x7c00
; VI-NEXT:    v_cmp_lg_f16_e64 s[4:5], s17, 0
; VI-NEXT:    v_cmp_nge_f16_e64 s[6:7], |s16|, v1
; VI-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; VI-NEXT:    v_mov_b32_e32 v1, 0x7e00
; VI-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: frem_f16_uniform:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_f32_f16_e64 v1, |s16|
; GFX9-NEXT:    v_cvt_f32_f16_e64 v0, |s17|
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v0
; GFX9-NEXT:    s_cbranch_vccz .LBB17_4
; GFX9-NEXT:  ; %bb.1: ; %frem.compute
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v5, v1
; GFX9-NEXT:    v_frexp_mant_f32_e32 v1, v1
; GFX9-NEXT:    v_ldexp_f32 v4, v1, 11
; GFX9-NEXT:    v_frexp_mant_f32_e32 v1, v0
; GFX9-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX9-NEXT:    v_div_scale_f32 v7, s[4:5], v1, v1, 1.0
; GFX9-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v1, 1.0
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v6, v0
; GFX9-NEXT:    v_add_u32_e32 v0, -1, v6
; GFX9-NEXT:    v_not_b32_e32 v2, v0
; GFX9-NEXT:    v_add_u32_e32 v2, v2, v5
; GFX9-NEXT:    v_rcp_f32_e32 v8, v7
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
; GFX9-NEXT:    v_fma_f32 v8, v9, v8, v8
; GFX9-NEXT:    v_mul_f32_e32 v9, v3, v8
; GFX9-NEXT:    v_fma_f32 v10, -v7, v9, v3
; GFX9-NEXT:    v_fma_f32 v9, v10, v8, v9
; GFX9-NEXT:    v_fma_f32 v3, -v7, v9, v3
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX9-NEXT:    v_div_fmas_f32 v3, v3, v8, v9
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v2
; GFX9-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX9-NEXT:    s_cbranch_vccnz .LBB17_5
; GFX9-NEXT:  ; %bb.2: ; %frem.loop_body.preheader
; GFX9-NEXT:    v_sub_u32_e32 v2, v5, v6
; GFX9-NEXT:    v_add_u32_e32 v2, 11, v2
; GFX9-NEXT:  .LBB17_3: ; %frem.loop_body
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v5, v4
; GFX9-NEXT:    v_mul_f32_e32 v4, v5, v3
; GFX9-NEXT:    v_rndne_f32_e32 v4, v4
; GFX9-NEXT:    v_fma_f32 v4, -v4, v1, v5
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; GFX9-NEXT:    v_add_f32_e32 v6, v4, v1
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX9-NEXT:    v_add_u32_e32 v2, -11, v2
; GFX9-NEXT:    v_ldexp_f32 v4, v4, 11
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v2
; GFX9-NEXT:    s_cbranch_vccnz .LBB17_3
; GFX9-NEXT:    s_branch .LBB17_6
; GFX9-NEXT:  .LBB17_4: ; %frem.else
; GFX9-NEXT:    s_and_b32 s4, 0x8000, s16
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, v1, v0
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s4
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX9-NEXT:    s_branch .LBB17_7
; GFX9-NEXT:  .LBB17_5:
; GFX9-NEXT:    v_mov_b32_e32 v5, v4
; GFX9-NEXT:  .LBB17_6: ; %frem.loop_exit
; GFX9-NEXT:    v_add_u32_e32 v2, -10, v2
; GFX9-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX9-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX9-NEXT:    v_rndne_f32_e32 v3, v3
; GFX9-NEXT:    v_fma_f32 v2, -v3, v1, v2
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v2
; GFX9-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX9-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX9-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX9-NEXT:    s_movk_i32 s4, 0x7fff
; GFX9-NEXT:    v_mov_b32_e32 v1, s16
; GFX9-NEXT:    v_bfi_b32 v0, s4, v0, v1
; GFX9-NEXT:  .LBB17_7:
; GFX9-NEXT:    v_mov_b32_e32 v1, 0x7c00
; GFX9-NEXT:    v_cmp_lg_f16_e64 s[4:5], s17, 0
; GFX9-NEXT:    v_cmp_nge_f16_e64 s[6:7], |s16|, v1
; GFX9-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; GFX9-NEXT:    v_mov_b32_e32 v1, 0x7e00
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: frem_f16_uniform:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cvt_f32_f16_e64 v1, |s16|
; GFX10-NEXT:    v_cvt_f32_f16_e64 v0, |s17|
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v0
; GFX10-NEXT:    s_cbranch_vccz .LBB17_5
; GFX10-NEXT:  ; %bb.1: ; %frem.compute
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v3, v1
; GFX10-NEXT:    v_frexp_mant_f32_e32 v1, v1
; GFX10-NEXT:    v_readfirstlane_b32 s4, v3
; GFX10-NEXT:    v_ldexp_f32 v2, v1, 11
; GFX10-NEXT:    v_frexp_mant_f32_e32 v1, v0
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v0, v0
; GFX10-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX10-NEXT:    v_readfirstlane_b32 s5, v0
; GFX10-NEXT:    v_add_nc_u32_e32 v0, -1, v0
; GFX10-NEXT:    v_div_scale_f32 v5, s6, v1, v1, 1.0
; GFX10-NEXT:    v_not_b32_e32 v4, v0
; GFX10-NEXT:    v_rcp_f32_e32 v6, v5
; GFX10-NEXT:    v_add_nc_u32_e32 v4, v4, v3
; GFX10-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX10-NEXT:    s_denorm_mode 15
; GFX10-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
; GFX10-NEXT:    v_fmac_f32_e32 v6, v7, v6
; GFX10-NEXT:    v_mul_f32_e32 v7, v3, v6
; GFX10-NEXT:    v_fma_f32 v8, -v5, v7, v3
; GFX10-NEXT:    v_fmac_f32_e32 v7, v8, v6
; GFX10-NEXT:    v_fma_f32 v3, -v5, v7, v3
; GFX10-NEXT:    s_denorm_mode 12
; GFX10-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX10-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX10-NEXT:    s_cbranch_vccnz .LBB17_6
; GFX10-NEXT:  ; %bb.2: ; %frem.loop_body.preheader
; GFX10-NEXT:    s_sub_i32 s4, s4, s5
; GFX10-NEXT:    s_add_i32 s4, s4, 11
; GFX10-NEXT:  .LBB17_3: ; %frem.loop_body
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v5, v2
; GFX10-NEXT:    s_add_i32 s4, s4, -11
; GFX10-NEXT:    s_cmp_gt_i32 s4, 11
; GFX10-NEXT:    v_mul_f32_e32 v2, v5, v3
; GFX10-NEXT:    v_rndne_f32_e32 v2, v2
; GFX10-NEXT:    v_fma_f32 v2, -v2, v1, v5
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX10-NEXT:    v_add_f32_e32 v4, v2, v1
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v2, v2, 11
; GFX10-NEXT:    s_cbranch_scc1 .LBB17_3
; GFX10-NEXT:  ; %bb.4:
; GFX10-NEXT:    v_mov_b32_e32 v4, s4
; GFX10-NEXT:    s_branch .LBB17_7
; GFX10-NEXT:  .LBB17_5: ; %frem.else
; GFX10-NEXT:    s_and_b32 s4, 0x8000, s16
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v1, v0
; GFX10-NEXT:    v_mov_b32_e32 v0, s4
; GFX10-NEXT:    v_cndmask_b32_e32 v0, s16, v0, vcc_lo
; GFX10-NEXT:    s_branch .LBB17_8
; GFX10-NEXT:  .LBB17_6:
; GFX10-NEXT:    v_mov_b32_e32 v5, v2
; GFX10-NEXT:  .LBB17_7: ; %frem.loop_exit
; GFX10-NEXT:    v_add_nc_u32_e32 v2, -10, v4
; GFX10-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX10-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX10-NEXT:    v_rndne_f32_e32 v3, v3
; GFX10-NEXT:    v_fma_f32 v2, -v3, v1, v2
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX10-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX10-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX10-NEXT:    v_bfi_b32 v0, 0x7fff, v0, s16
; GFX10-NEXT:  .LBB17_8:
; GFX10-NEXT:    v_cmp_lg_f16_e64 s4, s17, 0
; GFX10-NEXT:    v_cmp_nge_f16_e64 s5, |s16|, 0x7c00
; GFX10-NEXT:    s_and_b32 vcc_lo, s5, s4
; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v0, vcc_lo
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: frem_f16_uniform:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v1, |s0|
; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v0, |s1|
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v0
; GFX11-TRUE16-NEXT:    s_cbranch_vccz .LBB17_5
; GFX11-TRUE16-NEXT:  ; %bb.1: ; %frem.compute
; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, v1
; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v1, v1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s2, v3
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v2, v1, 11
; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v1, v0
; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s3, v0
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v0, -1, v0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX11-TRUE16-NEXT:    v_not_b32_e32 v4, v0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v6, v5
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v4, v4, v3
; GFX11-TRUE16-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX11-TRUE16-NEXT:    s_denorm_mode 15
; GFX11-TRUE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v6, v7, v6
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v7, v3, v6
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v8, -v5, v7, v3
; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v7, v8, v6
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v3, -v5, v7, v3
; GFX11-TRUE16-NEXT:    s_denorm_mode 12
; GFX11-TRUE16-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
; GFX11-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB17_6
; GFX11-TRUE16-NEXT:  ; %bb.2: ; %frem.loop_body.preheader
; GFX11-TRUE16-NEXT:    s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT:    s_add_i32 s2, s2, 11
; GFX11-TRUE16-NEXT:  .LBB17_3: ; %frem.loop_body
; GFX11-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX11-TRUE16-NEXT:    s_add_i32 s2, s2, -11
; GFX11-TRUE16-NEXT:    s_cmp_gt_i32 s2, 11
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v2, v5, v3
; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v2, v2
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v2, -v2, v1, v5
; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX11-TRUE16-NEXT:    v_add_f32_e32 v4, v2, v1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v2, v2, 11
; GFX11-TRUE16-NEXT:    s_cbranch_scc1 .LBB17_3
; GFX11-TRUE16-NEXT:  ; %bb.4:
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v4, s2
; GFX11-TRUE16-NEXT:    s_branch .LBB17_7
; GFX11-TRUE16-NEXT:  .LBB17_5: ; %frem.else
; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0x8000, s0
; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v1, v0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, s0, v2.l, vcc_lo
; GFX11-TRUE16-NEXT:    s_branch .LBB17_8
; GFX11-TRUE16-NEXT:  .LBB17_6:
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX11-TRUE16-NEXT:  .LBB17_7: ; %frem.loop_exit
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, -10, v4
; GFX11-TRUE16-NEXT:    s_and_b32 s2, s0, 0x8000
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v3, v3
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v2, -v3, v1, v2
; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX11-TRUE16-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, s2, v0
; GFX11-TRUE16-NEXT:  .LBB17_8:
; GFX11-TRUE16-NEXT:    v_cmp_lg_f16_e64 s1, s1, 0
; GFX11-TRUE16-NEXT:    v_cmp_nge_f16_e64 s0, |s0|, 0x7c00
; GFX11-TRUE16-NEXT:    s_and_b32 s0, s0, s1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, s0
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: frem_f16_uniform:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v1, |s0|
; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v0, |s1|
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v0
; GFX11-FAKE16-NEXT:    s_cbranch_vccz .LBB17_5
; GFX11-FAKE16-NEXT:  ; %bb.1: ; %frem.compute
; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, v1
; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v1, v1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s2, v3
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v2, v1, 11
; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v1, v0
; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s3, v0
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v0, -1, v0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX11-FAKE16-NEXT:    v_not_b32_e32 v4, v0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v6, v5
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, v4, v3
; GFX11-FAKE16-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX11-FAKE16-NEXT:    s_denorm_mode 15
; GFX11-FAKE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v6, v7, v6
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v7, v3, v6
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v8, -v5, v7, v3
; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v7, v8, v6
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v3, -v5, v7, v3
; GFX11-FAKE16-NEXT:    s_denorm_mode 12
; GFX11-FAKE16-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
; GFX11-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB17_6
; GFX11-FAKE16-NEXT:  ; %bb.2: ; %frem.loop_body.preheader
; GFX11-FAKE16-NEXT:    s_sub_i32 s2, s2, s3
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT:    s_add_i32 s2, s2, 11
; GFX11-FAKE16-NEXT:  .LBB17_3: ; %frem.loop_body
; GFX11-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX11-FAKE16-NEXT:    s_add_i32 s2, s2, -11
; GFX11-FAKE16-NEXT:    s_cmp_gt_i32 s2, 11
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v2, v5, v3
; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v2, v2
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v2, -v2, v1, v5
; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX11-FAKE16-NEXT:    v_add_f32_e32 v4, v2, v1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v2, v2, 11
; GFX11-FAKE16-NEXT:    s_cbranch_scc1 .LBB17_3
; GFX11-FAKE16-NEXT:  ; %bb.4:
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, s2
; GFX11-FAKE16-NEXT:    s_branch .LBB17_7
; GFX11-FAKE16-NEXT:  .LBB17_5: ; %frem.else
; GFX11-FAKE16-NEXT:    s_and_b32 s2, 0x8000, s0
; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v1, v0
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, s2
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, s0, v0, vcc_lo
; GFX11-FAKE16-NEXT:    s_branch .LBB17_8
; GFX11-FAKE16-NEXT:  .LBB17_6:
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX11-FAKE16-NEXT:  .LBB17_7: ; %frem.loop_exit
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v2, -10, v4
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v3, v3
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v2, -v3, v1, v2
; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX11-FAKE16-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX11-FAKE16-NEXT:    v_bfi_b32 v0, 0x7fff, v0, s0
; GFX11-FAKE16-NEXT:  .LBB17_8:
; GFX11-FAKE16-NEXT:    v_cmp_lg_f16_e64 s1, s1, 0
; GFX11-FAKE16-NEXT:    v_cmp_nge_f16_e64 s0, |s0|, 0x7c00
; GFX11-FAKE16-NEXT:    s_and_b32 vcc_lo, s0, s1
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v0, vcc_lo
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-TRUE16-LABEL: frem_f16_uniform:
; GFX1150-TRUE16:       ; %bb.0:
; GFX1150-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-TRUE16-NEXT:    s_and_b32 s2, s0, 0x7fff
; GFX1150-TRUE16-NEXT:    s_and_b32 s4, s1, 0x7fff
; GFX1150-TRUE16-NEXT:    s_cvt_f32_f16 s3, s2
; GFX1150-TRUE16-NEXT:    s_cvt_f32_f16 s4, s4
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
; GFX1150-TRUE16-NEXT:    s_cmp_gt_f32 s3, s4
; GFX1150-TRUE16-NEXT:    s_cbranch_scc0 .LBB17_5
; GFX1150-TRUE16-NEXT:  ; %bb.1: ; %frem.compute
; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v1, s4
; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v0, s3
; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, s3
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v2, v0, 11
; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v0, s4
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s3, v3
; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s4, v0
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v0, -1, v0
; GFX1150-TRUE16-NEXT:    v_rcp_f32_e32 v6, v5
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_not_b32_e32 v4, v0
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v4, v4, v3
; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX1150-TRUE16-NEXT:    s_denorm_mode 15
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v6, v7, v6
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v7, v3, v6
; GFX1150-TRUE16-NEXT:    v_fma_f32 v8, -v5, v7, v3
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v7, v8, v6
; GFX1150-TRUE16-NEXT:    v_fma_f32 v3, -v5, v7, v3
; GFX1150-TRUE16-NEXT:    s_denorm_mode 12
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-TRUE16-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
; GFX1150-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1150-TRUE16-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX1150-TRUE16-NEXT:    s_cbranch_vccnz .LBB17_6
; GFX1150-TRUE16-NEXT:  ; %bb.2: ; %frem.loop_body.preheader
; GFX1150-TRUE16-NEXT:    s_sub_i32 s3, s3, s4
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    s_add_i32 s3, s3, 11
; GFX1150-TRUE16-NEXT:  .LBB17_3: ; %frem.loop_body
; GFX1150-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX1150-TRUE16-NEXT:    s_add_i32 s3, s3, -11
; GFX1150-TRUE16-NEXT:    s_cmp_gt_i32 s3, 11
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v2, v5, v3
; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v2, v2
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v2, 0x80000000, v2
; GFX1150-TRUE16-NEXT:    v_fma_f32 v2, v2, v1, v5
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v4, v2, v1
; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v2, v2, 11
; GFX1150-TRUE16-NEXT:    s_cbranch_scc1 .LBB17_3
; GFX1150-TRUE16-NEXT:  ; %bb.4:
; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v4, s3
; GFX1150-TRUE16-NEXT:    s_branch .LBB17_7
; GFX1150-TRUE16-NEXT:  .LBB17_5: ; %frem.else
; GFX1150-TRUE16-NEXT:    s_cmp_eq_f32 s3, s4
; GFX1150-TRUE16-NEXT:    v_and_b16 v0.l, 0x8000, s0
; GFX1150-TRUE16-NEXT:    s_cselect_b32 s3, -1, 0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v0.l, s0, v0.l, s3
; GFX1150-TRUE16-NEXT:    s_branch .LBB17_8
; GFX1150-TRUE16-NEXT:  .LBB17_6:
; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX1150-TRUE16-NEXT:  .LBB17_7: ; %frem.loop_exit
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v2, -10, v4
; GFX1150-TRUE16-NEXT:    s_and_b32 s0, s0, 0x8000
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v3, v3
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v2, v3, v1
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX1150-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_and_b32_e32 v0, 0x7fff, v0
; GFX1150-TRUE16-NEXT:    v_or_b32_e32 v0, s0, v0
; GFX1150-TRUE16-NEXT:  .LBB17_8:
; GFX1150-TRUE16-NEXT:    s_cmp_lg_f16 s1, 0
; GFX1150-TRUE16-NEXT:    s_cselect_b32 s0, -1, 0
; GFX1150-TRUE16-NEXT:    s_cmp_nge_f16 s2, 0x7c00
; GFX1150-TRUE16-NEXT:    s_cselect_b32 s1, -1, 0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    s_and_b32 s0, s1, s0
; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, s0
; GFX1150-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-FAKE16-LABEL: frem_f16_uniform:
; GFX1150-FAKE16:       ; %bb.0:
; GFX1150-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-FAKE16-NEXT:    s_and_b32 s2, s0, 0x7fff
; GFX1150-FAKE16-NEXT:    s_and_b32 s4, s1, 0x7fff
; GFX1150-FAKE16-NEXT:    s_cvt_f32_f16 s3, s2
; GFX1150-FAKE16-NEXT:    s_cvt_f32_f16 s4, s4
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
; GFX1150-FAKE16-NEXT:    s_cmp_gt_f32 s3, s4
; GFX1150-FAKE16-NEXT:    s_cbranch_scc0 .LBB17_5
; GFX1150-FAKE16-NEXT:  ; %bb.1: ; %frem.compute
; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v1, s4
; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v0, s3
; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, s3
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v2, v0, 11
; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v0, s4
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s3, v3
; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s4, v0
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v0, -1, v0
; GFX1150-FAKE16-NEXT:    v_rcp_f32_e32 v6, v5
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_not_b32_e32 v4, v0
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v4, v4, v3
; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX1150-FAKE16-NEXT:    s_denorm_mode 15
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v6, v7, v6
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v7, v3, v6
; GFX1150-FAKE16-NEXT:    v_fma_f32 v8, -v5, v7, v3
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v7, v8, v6
; GFX1150-FAKE16-NEXT:    v_fma_f32 v3, -v5, v7, v3
; GFX1150-FAKE16-NEXT:    s_denorm_mode 12
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-FAKE16-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
; GFX1150-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1150-FAKE16-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX1150-FAKE16-NEXT:    s_cbranch_vccnz .LBB17_6
; GFX1150-FAKE16-NEXT:  ; %bb.2: ; %frem.loop_body.preheader
; GFX1150-FAKE16-NEXT:    s_sub_i32 s3, s3, s4
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT:    s_add_i32 s3, s3, 11
; GFX1150-FAKE16-NEXT:  .LBB17_3: ; %frem.loop_body
; GFX1150-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX1150-FAKE16-NEXT:    s_add_i32 s3, s3, -11
; GFX1150-FAKE16-NEXT:    s_cmp_gt_i32 s3, 11
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v2, v5, v3
; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v2, v2
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v2, 0x80000000, v2
; GFX1150-FAKE16-NEXT:    v_fma_f32 v2, v2, v1, v5
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v4, v2, v1
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v2, v2, 11
; GFX1150-FAKE16-NEXT:    s_cbranch_scc1 .LBB17_3
; GFX1150-FAKE16-NEXT:  ; %bb.4:
; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v4, s3
; GFX1150-FAKE16-NEXT:    s_branch .LBB17_7
; GFX1150-FAKE16-NEXT:  .LBB17_5: ; %frem.else
; GFX1150-FAKE16-NEXT:    s_and_b32 s5, 0x8000, s0
; GFX1150-FAKE16-NEXT:    s_cmp_eq_f32 s3, s4
; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v0, s5
; GFX1150-FAKE16-NEXT:    s_cselect_b32 vcc_lo, -1, 0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v0, s0, v0, vcc_lo
; GFX1150-FAKE16-NEXT:    s_branch .LBB17_8
; GFX1150-FAKE16-NEXT:  .LBB17_6:
; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX1150-FAKE16-NEXT:  .LBB17_7: ; %frem.loop_exit
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v2, -10, v4
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v3, v3
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v2, v3, v1
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX1150-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_bfi_b32 v0, 0x7fff, v0, s0
; GFX1150-FAKE16-NEXT:  .LBB17_8:
; GFX1150-FAKE16-NEXT:    s_cmp_lg_f16 s1, 0
; GFX1150-FAKE16-NEXT:    s_cselect_b32 s0, -1, 0
; GFX1150-FAKE16-NEXT:    s_cmp_nge_f16 s2, 0x7c00
; GFX1150-FAKE16-NEXT:    s_cselect_b32 s1, -1, 0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT:    s_and_b32 vcc_lo, s1, s0
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v0, vcc_lo
; GFX1150-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-TRUE16-LABEL: frem_f16_uniform:
; GFX1200-TRUE16:       ; %bb.0:
; GFX1200-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1200-TRUE16-NEXT:    s_and_b32 s2, s0, 0x7fff
; GFX1200-TRUE16-NEXT:    s_and_b32 s4, s1, 0x7fff
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_cvt_f32_f16 s3, s2
; GFX1200-TRUE16-NEXT:    s_cvt_f32_f16 s4, s4
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_2)
; GFX1200-TRUE16-NEXT:    s_cmp_gt_f32 s3, s4
; GFX1200-TRUE16-NEXT:    s_cbranch_scc0 .LBB17_5
; GFX1200-TRUE16-NEXT:  ; %bb.1: ; %frem.compute
; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v1, s4
; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v0, s3
; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, s3
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v2, v0, 11
; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v0, s4
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s3, v3
; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s4, v0
; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v0, -1, v0
; GFX1200-TRUE16-NEXT:    v_rcp_f32_e32 v6, v5
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_not_b32_e32 v4, v0
; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v4, v4, v3
; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX1200-TRUE16-NEXT:    s_denorm_mode 15
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v6, v7, v6
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v7, v3, v6
; GFX1200-TRUE16-NEXT:    v_fma_f32 v8, -v5, v7, v3
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v7, v8, v6
; GFX1200-TRUE16-NEXT:    v_fma_f32 v3, -v5, v7, v3
; GFX1200-TRUE16-NEXT:    s_denorm_mode 12
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
; GFX1200-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1200-TRUE16-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX1200-TRUE16-NEXT:    s_cbranch_vccnz .LBB17_6
; GFX1200-TRUE16-NEXT:  ; %bb.2: ; %frem.loop_body.preheader
; GFX1200-TRUE16-NEXT:    s_sub_co_i32 s3, s3, s4
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_add_co_i32 s3, s3, 11
; GFX1200-TRUE16-NEXT:  .LBB17_3: ; %frem.loop_body
; GFX1200-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_add_co_i32 s3, s3, -11
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_cmp_gt_i32 s3, 11
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v2, v5, v3
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v2, v2
; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v2, 0x80000000, v2
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f32 v2, v2, v1, v5
; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v4, v2, v1
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v2, v2, 11
; GFX1200-TRUE16-NEXT:    s_cbranch_scc1 .LBB17_3
; GFX1200-TRUE16-NEXT:  ; %bb.4:
; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v4, s3
; GFX1200-TRUE16-NEXT:    s_branch .LBB17_7
; GFX1200-TRUE16-NEXT:  .LBB17_5: ; %frem.else
; GFX1200-TRUE16-NEXT:    s_cmp_eq_f32 s3, s4
; GFX1200-TRUE16-NEXT:    v_and_b16 v0.l, 0x8000, s0
; GFX1200-TRUE16-NEXT:    s_cselect_b32 s3, -1, 0
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v0.l, s0, v0.l, s3
; GFX1200-TRUE16-NEXT:    s_branch .LBB17_8
; GFX1200-TRUE16-NEXT:  .LBB17_6:
; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX1200-TRUE16-NEXT:  .LBB17_7: ; %frem.loop_exit
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v2, -10, v4
; GFX1200-TRUE16-NEXT:    s_and_b32 s0, s0, 0x8000
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v3, v3
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v2, v3, v1
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX1200-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_and_b32_e32 v0, 0x7fff, v0
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    v_or_b32_e32 v0, s0, v0
; GFX1200-TRUE16-NEXT:  .LBB17_8:
; GFX1200-TRUE16-NEXT:    s_cmp_lg_f16 s1, 0
; GFX1200-TRUE16-NEXT:    s_cselect_b32 s0, -1, 0
; GFX1200-TRUE16-NEXT:    s_cmp_nge_f16 s2, 0x7c00
; GFX1200-TRUE16-NEXT:    s_cselect_b32 s1, -1, 0
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_and_b32 s0, s1, s0
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, s0
; GFX1200-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-FAKE16-LABEL: frem_f16_uniform:
; GFX1200-FAKE16:       ; %bb.0:
; GFX1200-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1200-FAKE16-NEXT:    s_and_b32 s2, s0, 0x7fff
; GFX1200-FAKE16-NEXT:    s_and_b32 s4, s1, 0x7fff
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_cvt_f32_f16 s3, s2
; GFX1200-FAKE16-NEXT:    s_cvt_f32_f16 s4, s4
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_2)
; GFX1200-FAKE16-NEXT:    s_cmp_gt_f32 s3, s4
; GFX1200-FAKE16-NEXT:    s_cbranch_scc0 .LBB17_5
; GFX1200-FAKE16-NEXT:  ; %bb.1: ; %frem.compute
; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v1, s4
; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v0, s3
; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, s3
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v2, v0, 11
; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v0, s4
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s3, v3
; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s4, v0
; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v0, -1, v0
; GFX1200-FAKE16-NEXT:    v_rcp_f32_e32 v6, v5
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_not_b32_e32 v4, v0
; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v4, v4, v3
; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX1200-FAKE16-NEXT:    s_denorm_mode 15
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v6, v7, v6
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v7, v3, v6
; GFX1200-FAKE16-NEXT:    v_fma_f32 v8, -v5, v7, v3
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v7, v8, v6
; GFX1200-FAKE16-NEXT:    v_fma_f32 v3, -v5, v7, v3
; GFX1200-FAKE16-NEXT:    s_denorm_mode 12
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-FAKE16-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
; GFX1200-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1200-FAKE16-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX1200-FAKE16-NEXT:    s_cbranch_vccnz .LBB17_6
; GFX1200-FAKE16-NEXT:  ; %bb.2: ; %frem.loop_body.preheader
; GFX1200-FAKE16-NEXT:    s_sub_co_i32 s3, s3, s4
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_add_co_i32 s3, s3, 11
; GFX1200-FAKE16-NEXT:  .LBB17_3: ; %frem.loop_body
; GFX1200-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_add_co_i32 s3, s3, -11
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_cmp_gt_i32 s3, 11
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v2, v5, v3
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v2, v2
; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v2, 0x80000000, v2
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f32 v2, v2, v1, v5
; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v4, v2, v1
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v2, v2, 11
; GFX1200-FAKE16-NEXT:    s_cbranch_scc1 .LBB17_3
; GFX1200-FAKE16-NEXT:  ; %bb.4:
; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v4, s3
; GFX1200-FAKE16-NEXT:    s_branch .LBB17_7
; GFX1200-FAKE16-NEXT:  .LBB17_5: ; %frem.else
; GFX1200-FAKE16-NEXT:    s_and_b32 s5, 0x8000, s0
; GFX1200-FAKE16-NEXT:    s_cmp_eq_f32 s3, s4
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v0, s5
; GFX1200-FAKE16-NEXT:    s_cselect_b32 vcc_lo, -1, 0
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v0, s0, v0, vcc_lo
; GFX1200-FAKE16-NEXT:    s_branch .LBB17_8
; GFX1200-FAKE16-NEXT:  .LBB17_6:
; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX1200-FAKE16-NEXT:  .LBB17_7: ; %frem.loop_exit
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v2, -10, v4
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v3, v3
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v2, v3, v1
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX1200-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_bfi_b32 v0, 0x7fff, v0, s0
; GFX1200-FAKE16-NEXT:  .LBB17_8:
; GFX1200-FAKE16-NEXT:    s_cmp_lg_f16 s1, 0
; GFX1200-FAKE16-NEXT:    s_cselect_b32 s0, -1, 0
; GFX1200-FAKE16-NEXT:    s_cmp_nge_f16 s2, 0x7c00
; GFX1200-FAKE16-NEXT:    s_cselect_b32 s1, -1, 0
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_and_b32 vcc_lo, s1, s0
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v0, vcc_lo
; GFX1200-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %r2 = frem half %in1, %in2
  ret half %r2
}

define half @fast_frem_f16_uniform(half inreg %in1, half inreg %in2) #0 {
; SI-LABEL: fast_frem_f16_uniform:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cvt_f32_f16_e32 v4, s17
; SI-NEXT:    v_cvt_f32_f16_e32 v2, s16
; SI-NEXT:    v_div_scale_f32 v1, s[4:5], v4, v4, v2
; SI-NEXT:    v_rcp_f32_e32 v3, v1
; SI-NEXT:    v_div_scale_f32 v0, vcc, v2, v4, v2
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    v_fma_f32 v5, -v1, v3, 1.0
; SI-NEXT:    v_fma_f32 v3, v5, v3, v3
; SI-NEXT:    v_mul_f32_e32 v5, v0, v3
; SI-NEXT:    v_fma_f32 v6, -v1, v5, v0
; SI-NEXT:    v_fma_f32 v5, v6, v3, v5
; SI-NEXT:    v_fma_f32 v0, -v1, v5, v0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    v_div_fmas_f32 v0, v0, v3, v5
; SI-NEXT:    v_div_fixup_f32 v0, v0, v4, v2
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-NEXT:    v_cvt_f64_f32_e32 v[2:3], v2
; SI-NEXT:    v_cvt_f64_f32_e32 v[4:5], v4
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_trunc_f32_e32 v0, v0
; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-NEXT:    v_cvt_f32_f16_e64 v0, -v0
; SI-NEXT:    v_cvt_f64_f32_e32 v[0:1], v0
; SI-NEXT:    v_fma_f64 v[0:1], v[0:1], v[4:5], v[2:3]
; SI-NEXT:    v_readfirstlane_b32 s4, v1
; SI-NEXT:    s_and_b32 s5, s4, 0x1ff
; SI-NEXT:    v_readfirstlane_b32 s6, v0
; SI-NEXT:    s_or_b32 s5, s5, s6
; SI-NEXT:    s_cselect_b32 s5, 1, 0
; SI-NEXT:    s_lshr_b32 s6, s4, 8
; SI-NEXT:    s_bfe_u32 s7, s4, 0xb0014
; SI-NEXT:    s_and_b32 s6, s6, 0xffe
; SI-NEXT:    s_sub_i32 s8, 0x3f1, s7
; SI-NEXT:    s_or_b32 s5, s6, s5
; SI-NEXT:    v_med3_i32 v0, s8, 0, 13
; SI-NEXT:    s_or_b32 s6, s5, 0x1000
; SI-NEXT:    v_readfirstlane_b32 s8, v0
; SI-NEXT:    s_lshr_b32 s9, s6, s8
; SI-NEXT:    s_lshl_b32 s8, s9, s8
; SI-NEXT:    s_cmp_lg_u32 s8, s6
; SI-NEXT:    s_cselect_b32 s6, 1, 0
; SI-NEXT:    s_addk_i32 s7, 0xfc10
; SI-NEXT:    s_lshl_b32 s8, s7, 12
; SI-NEXT:    s_or_b32 s6, s9, s6
; SI-NEXT:    s_or_b32 s8, s5, s8
; SI-NEXT:    s_cmp_lt_i32 s7, 1
; SI-NEXT:    s_cselect_b32 s6, s6, s8
; SI-NEXT:    s_and_b32 s8, s6, 7
; SI-NEXT:    s_cmp_gt_i32 s8, 5
; SI-NEXT:    s_cselect_b32 s9, 1, 0
; SI-NEXT:    s_cmp_eq_u32 s8, 3
; SI-NEXT:    s_cselect_b32 s8, 1, 0
; SI-NEXT:    s_or_b32 s8, s8, s9
; SI-NEXT:    s_lshr_b32 s6, s6, 2
; SI-NEXT:    s_add_i32 s6, s6, s8
; SI-NEXT:    s_cmp_lt_i32 s7, 31
; SI-NEXT:    s_cselect_b32 s6, s6, 0x7c00
; SI-NEXT:    s_cmp_lg_u32 s5, 0
; SI-NEXT:    s_movk_i32 s5, 0x7e00
; SI-NEXT:    s_cselect_b32 s5, s5, 0x7c00
; SI-NEXT:    s_cmpk_eq_i32 s7, 0x40f
; SI-NEXT:    s_cselect_b32 s5, s5, s6
; SI-NEXT:    s_lshr_b32 s4, s4, 16
; SI-NEXT:    s_and_b32 s4, s4, 0x8000
; SI-NEXT:    s_or_b32 s4, s4, s5
; SI-NEXT:    v_mov_b32_e32 v0, s4
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; CI-LABEL: fast_frem_f16_uniform:
; CI:       ; %bb.0:
; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-NEXT:    v_cvt_f32_f16_e32 v4, s17
; CI-NEXT:    v_cvt_f32_f16_e32 v2, s16
; CI-NEXT:    v_div_scale_f32 v1, s[4:5], v4, v4, v2
; CI-NEXT:    v_div_scale_f32 v0, vcc, v2, v4, v2
; CI-NEXT:    v_rcp_f32_e32 v3, v1
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v5, -v1, v3, 1.0
; CI-NEXT:    v_fma_f32 v3, v5, v3, v3
; CI-NEXT:    v_mul_f32_e32 v5, v0, v3
; CI-NEXT:    v_fma_f32 v6, -v1, v5, v0
; CI-NEXT:    v_fma_f32 v5, v6, v3, v5
; CI-NEXT:    v_fma_f32 v0, -v1, v5, v0
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v0, v0, v3, v5
; CI-NEXT:    v_div_fixup_f32 v0, v0, v4, v2
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; CI-NEXT:    v_cvt_f64_f32_e32 v[2:3], v2
; CI-NEXT:    v_cvt_f64_f32_e32 v[4:5], v4
; CI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; CI-NEXT:    v_trunc_f32_e32 v0, v0
; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; CI-NEXT:    v_cvt_f32_f16_e64 v0, -v0
; CI-NEXT:    v_cvt_f64_f32_e32 v[0:1], v0
; CI-NEXT:    v_fma_f64 v[0:1], v[0:1], v[4:5], v[2:3]
; CI-NEXT:    v_readfirstlane_b32 s4, v1
; CI-NEXT:    s_and_b32 s5, s4, 0x1ff
; CI-NEXT:    v_readfirstlane_b32 s6, v0
; CI-NEXT:    s_or_b32 s5, s5, s6
; CI-NEXT:    s_cselect_b32 s5, 1, 0
; CI-NEXT:    s_lshr_b32 s6, s4, 8
; CI-NEXT:    s_bfe_u32 s7, s4, 0xb0014
; CI-NEXT:    s_and_b32 s6, s6, 0xffe
; CI-NEXT:    s_sub_i32 s8, 0x3f1, s7
; CI-NEXT:    s_or_b32 s5, s6, s5
; CI-NEXT:    v_med3_i32 v0, s8, 0, 13
; CI-NEXT:    s_or_b32 s6, s5, 0x1000
; CI-NEXT:    v_readfirstlane_b32 s8, v0
; CI-NEXT:    s_lshr_b32 s9, s6, s8
; CI-NEXT:    s_lshl_b32 s8, s9, s8
; CI-NEXT:    s_cmp_lg_u32 s8, s6
; CI-NEXT:    s_cselect_b32 s6, 1, 0
; CI-NEXT:    s_addk_i32 s7, 0xfc10
; CI-NEXT:    s_lshl_b32 s8, s7, 12
; CI-NEXT:    s_or_b32 s6, s9, s6
; CI-NEXT:    s_or_b32 s8, s5, s8
; CI-NEXT:    s_cmp_lt_i32 s7, 1
; CI-NEXT:    s_cselect_b32 s6, s6, s8
; CI-NEXT:    s_and_b32 s8, s6, 7
; CI-NEXT:    s_cmp_gt_i32 s8, 5
; CI-NEXT:    s_cselect_b32 s9, 1, 0
; CI-NEXT:    s_cmp_eq_u32 s8, 3
; CI-NEXT:    s_cselect_b32 s8, 1, 0
; CI-NEXT:    s_or_b32 s8, s8, s9
; CI-NEXT:    s_lshr_b32 s6, s6, 2
; CI-NEXT:    s_add_i32 s6, s6, s8
; CI-NEXT:    s_cmp_lt_i32 s7, 31
; CI-NEXT:    s_cselect_b32 s6, s6, 0x7c00
; CI-NEXT:    s_cmp_lg_u32 s5, 0
; CI-NEXT:    s_movk_i32 s5, 0x7e00
; CI-NEXT:    s_cselect_b32 s5, s5, 0x7c00
; CI-NEXT:    s_cmpk_eq_i32 s7, 0x40f
; CI-NEXT:    s_cselect_b32 s5, s5, s6
; CI-NEXT:    s_lshr_b32 s4, s4, 16
; CI-NEXT:    s_and_b32 s4, s4, 0x8000
; CI-NEXT:    s_or_b32 s4, s4, s5
; CI-NEXT:    v_mov_b32_e32 v0, s4
; CI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: fast_frem_f16_uniform:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cvt_f32_f16_e32 v1, s17
; VI-NEXT:    v_cvt_f32_f16_e32 v0, s16
; VI-NEXT:    v_rcp_f32_e32 v2, v1
; VI-NEXT:    v_mul_f32_e32 v3, v0, v2
; VI-NEXT:    v_mad_f32 v4, -v1, v3, v0
; VI-NEXT:    v_mac_f32_e32 v3, v4, v2
; VI-NEXT:    v_mad_f32 v0, -v1, v3, v0
; VI-NEXT:    v_mul_f32_e32 v0, v0, v2
; VI-NEXT:    v_and_b32_e32 v0, 0xff800000, v0
; VI-NEXT:    v_add_f32_e32 v0, v0, v3
; VI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; VI-NEXT:    v_mov_b32_e32 v1, s16
; VI-NEXT:    v_div_fixup_f16 v0, v0, s17, v1
; VI-NEXT:    v_trunc_f16_e32 v0, v0
; VI-NEXT:    v_fma_f16 v0, -v0, s17, v1
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: fast_frem_f16_uniform:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_f32_f16_e32 v0, s17
; GFX9-NEXT:    v_mov_b32_e32 v2, s16
; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
; GFX9-NEXT:    v_mad_mix_f32 v1, s16, v0, neg(0) op_sel_hi:[1,0,0]
; GFX9-NEXT:    v_mad_mix_f32 v3, -s17, v1, v2 op_sel_hi:[1,0,1]
; GFX9-NEXT:    v_mac_f32_e32 v1, v3, v0
; GFX9-NEXT:    v_mad_mix_f32 v3, -s17, v1, v2 op_sel_hi:[1,0,1]
; GFX9-NEXT:    v_mul_f32_e32 v0, v3, v0
; GFX9-NEXT:    v_and_b32_e32 v0, 0xff800000, v0
; GFX9-NEXT:    v_add_f32_e32 v0, v0, v1
; GFX9-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX9-NEXT:    v_div_fixup_f16 v0, v0, s17, v2
; GFX9-NEXT:    v_trunc_f16_e32 v0, v0
; GFX9-NEXT:    v_fma_f16 v0, -v0, s17, v2
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: fast_frem_f16_uniform:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cvt_f32_f16_e32 v0, s17
; GFX10-NEXT:    v_cvt_f32_f16_e32 v3, s16
; GFX10-NEXT:    v_rcp_f32_e32 v1, v0
; GFX10-NEXT:    v_fma_mix_f32 v2, s16, v1, neg(0) op_sel_hi:[1,0,0]
; GFX10-NEXT:    v_mad_f32 v4, -v0, v2, v3
; GFX10-NEXT:    v_mac_f32_e32 v2, v4, v1
; GFX10-NEXT:    v_mad_f32 v0, -v0, v2, v3
; GFX10-NEXT:    v_mul_f32_e32 v0, v0, v1
; GFX10-NEXT:    v_and_b32_e32 v0, 0xff800000, v0
; GFX10-NEXT:    v_fma_mixlo_f16 v0, v0, 1.0, v2 op_sel_hi:[0,1,0]
; GFX10-NEXT:    v_div_fixup_f16 v0, v0, s17, s16
; GFX10-NEXT:    v_trunc_f16_e32 v0, v0
; GFX10-NEXT:    v_fma_f16 v0, -v0, s17, s16
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: fast_frem_f16_uniform:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, s1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v0, v0
; GFX11-TRUE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v1, s0, v0, neg(0) op_sel_hi:[1,0,0]
; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v2, -s1, v1, s0 op_sel_hi:[1,0,1]
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v1, v2, v0
; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v2, -s1, v1, s0 op_sel_hi:[1,0,1]
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v0, v2, v0
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xff800000, v0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_mixlo_f16 v0, v0, 1.0, v1 op_sel_hi:[0,1,0]
; GFX11-TRUE16-NEXT:    v_div_fixup_f16 v0.l, v0.l, s1, s0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_trunc_f16_e32 v0.l, v0.l
; GFX11-TRUE16-NEXT:    v_fma_f16 v0.l, -v0.l, s1, s0
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fast_frem_f16_uniform:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, s1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v0, v0
; GFX11-FAKE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v1, s0, v0, neg(0) op_sel_hi:[1,0,0]
; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v2, -s1, v1, s0 op_sel_hi:[1,0,1]
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v1, v2, v0
; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v2, -s1, v1, s0 op_sel_hi:[1,0,1]
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v0, v2, v0
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff800000, v0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_mixlo_f16 v0, v0, 1.0, v1 op_sel_hi:[0,1,0]
; GFX11-FAKE16-NEXT:    v_div_fixup_f16 v0, v0, s1, s0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_trunc_f16_e32 v0, v0
; GFX11-FAKE16-NEXT:    v_fma_f16 v0, -v0, s1, s0
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-TRUE16-LABEL: fast_frem_f16_uniform:
; GFX1150-TRUE16:       ; %bb.0:
; GFX1150-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-TRUE16-NEXT:    s_cvt_f32_f16 s2, s1
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(TRANS32_DEP_1)
; GFX1150-TRUE16-NEXT:    v_rcp_f32_e32 v0, s2
; GFX1150-TRUE16-NEXT:    v_fma_mix_f32 v1, s0, v0, neg(0) op_sel_hi:[1,0,0]
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fma_mix_f32 v2, -s1, v1, s0 op_sel_hi:[1,0,1]
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v1, v2, v0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fma_mix_f32 v2, -s1, v1, s0 op_sel_hi:[1,0,1]
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v0, v2, v0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_and_b32_e32 v0, 0xff800000, v0
; GFX1150-TRUE16-NEXT:    v_fma_mixlo_f16 v0, v0, 1.0, v1 op_sel_hi:[0,1,0]
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_div_fixup_f16 v0.l, v0.l, s1, s0
; GFX1150-TRUE16-NEXT:    v_trunc_f16_e32 v0.l, v0.l
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v0, 0x8000, v0
; GFX1150-TRUE16-NEXT:    v_fma_f16 v0.l, v0.l, s1, s0
; GFX1150-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-FAKE16-LABEL: fast_frem_f16_uniform:
; GFX1150-FAKE16:       ; %bb.0:
; GFX1150-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-FAKE16-NEXT:    s_cvt_f32_f16 s2, s1
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(TRANS32_DEP_1)
; GFX1150-FAKE16-NEXT:    v_rcp_f32_e32 v0, s2
; GFX1150-FAKE16-NEXT:    v_fma_mix_f32 v1, s0, v0, neg(0) op_sel_hi:[1,0,0]
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fma_mix_f32 v2, -s1, v1, s0 op_sel_hi:[1,0,1]
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v1, v2, v0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fma_mix_f32 v2, -s1, v1, s0 op_sel_hi:[1,0,1]
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v0, v2, v0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff800000, v0
; GFX1150-FAKE16-NEXT:    v_fma_mixlo_f16 v0, v0, 1.0, v1 op_sel_hi:[0,1,0]
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_div_fixup_f16 v0, v0, s1, s0
; GFX1150-FAKE16-NEXT:    v_trunc_f16_e32 v0, v0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v0, 0x8000, v0
; GFX1150-FAKE16-NEXT:    v_fma_f16 v0, v0, s1, s0
; GFX1150-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-TRUE16-LABEL: fast_frem_f16_uniform:
; GFX1200-TRUE16:       ; %bb.0:
; GFX1200-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1200-TRUE16-NEXT:    s_cvt_f32_f16 s2, s1
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
; GFX1200-TRUE16-NEXT:    v_s_rcp_f32 s2, s2
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)
; GFX1200-TRUE16-NEXT:    v_fma_mix_f32 v0, s0, s2, neg(0) op_sel_hi:[1,0,0]
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_mix_f32 v1, -s1, v0, s0 op_sel_hi:[1,0,1]
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v0, s2, v1
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_mix_f32 v1, -s1, v0, s0 op_sel_hi:[1,0,1]
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v1, s2, v1
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_and_b32_e32 v1, 0xff800000, v1
; GFX1200-TRUE16-NEXT:    v_fma_mixlo_f16 v0, v1, 1.0, v0 op_sel_hi:[0,1,0]
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_div_fixup_f16 v0.l, v0.l, s1, s0
; GFX1200-TRUE16-NEXT:    v_trunc_f16_e32 v0.l, v0.l
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v0, 0x8000, v0
; GFX1200-TRUE16-NEXT:    v_fma_f16 v0.l, v0.l, s1, s0
; GFX1200-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-FAKE16-LABEL: fast_frem_f16_uniform:
; GFX1200-FAKE16:       ; %bb.0:
; GFX1200-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1200-FAKE16-NEXT:    s_cvt_f32_f16 s2, s1
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
; GFX1200-FAKE16-NEXT:    v_s_rcp_f32 s2, s2
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_sdst(0)
; GFX1200-FAKE16-NEXT:    v_fma_mix_f32 v0, s0, s2, neg(0) op_sel_hi:[1,0,0]
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_mix_f32 v1, -s1, v0, s0 op_sel_hi:[1,0,1]
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v0, s2, v1
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_mix_f32 v1, -s1, v0, s0 op_sel_hi:[1,0,1]
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v1, s2, v1
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff800000, v1
; GFX1200-FAKE16-NEXT:    v_fma_mixlo_f16 v0, v1, 1.0, v0 op_sel_hi:[0,1,0]
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_div_fixup_f16 v0, v0, s1, s0
; GFX1200-FAKE16-NEXT:    v_trunc_f16_e32 v0, v0
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v0, 0x8000, v0
; GFX1200-FAKE16-NEXT:    v_fma_f16 v0, v0, s1, s0
; GFX1200-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %r2 = frem fast half %in1, %in2
  ret half %r2
}

define half @unsafe_frem_f16_uniform(half inreg %in1, half inreg %in2) #0 {
; SI-LABEL: unsafe_frem_f16_uniform:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cvt_f32_f16_e32 v4, s17
; SI-NEXT:    v_cvt_f32_f16_e32 v2, s16
; SI-NEXT:    v_div_scale_f32 v1, s[4:5], v4, v4, v2
; SI-NEXT:    v_rcp_f32_e32 v3, v1
; SI-NEXT:    v_div_scale_f32 v0, vcc, v2, v4, v2
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    v_fma_f32 v5, -v1, v3, 1.0
; SI-NEXT:    v_fma_f32 v3, v5, v3, v3
; SI-NEXT:    v_mul_f32_e32 v5, v0, v3
; SI-NEXT:    v_fma_f32 v6, -v1, v5, v0
; SI-NEXT:    v_fma_f32 v5, v6, v3, v5
; SI-NEXT:    v_fma_f32 v0, -v1, v5, v0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    v_div_fmas_f32 v0, v0, v3, v5
; SI-NEXT:    v_div_fixup_f32 v0, v0, v4, v2
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-NEXT:    v_cvt_f64_f32_e32 v[2:3], v2
; SI-NEXT:    v_cvt_f64_f32_e32 v[4:5], v4
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_trunc_f32_e32 v0, v0
; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-NEXT:    v_cvt_f32_f16_e64 v0, -v0
; SI-NEXT:    v_cvt_f64_f32_e32 v[0:1], v0
; SI-NEXT:    v_fma_f64 v[0:1], v[0:1], v[4:5], v[2:3]
; SI-NEXT:    v_readfirstlane_b32 s4, v1
; SI-NEXT:    s_and_b32 s5, s4, 0x1ff
; SI-NEXT:    v_readfirstlane_b32 s6, v0
; SI-NEXT:    s_or_b32 s5, s5, s6
; SI-NEXT:    s_cselect_b32 s5, 1, 0
; SI-NEXT:    s_lshr_b32 s6, s4, 8
; SI-NEXT:    s_bfe_u32 s7, s4, 0xb0014
; SI-NEXT:    s_and_b32 s6, s6, 0xffe
; SI-NEXT:    s_sub_i32 s8, 0x3f1, s7
; SI-NEXT:    s_or_b32 s5, s6, s5
; SI-NEXT:    v_med3_i32 v0, s8, 0, 13
; SI-NEXT:    s_or_b32 s6, s5, 0x1000
; SI-NEXT:    v_readfirstlane_b32 s8, v0
; SI-NEXT:    s_lshr_b32 s9, s6, s8
; SI-NEXT:    s_lshl_b32 s8, s9, s8
; SI-NEXT:    s_cmp_lg_u32 s8, s6
; SI-NEXT:    s_cselect_b32 s6, 1, 0
; SI-NEXT:    s_addk_i32 s7, 0xfc10
; SI-NEXT:    s_lshl_b32 s8, s7, 12
; SI-NEXT:    s_or_b32 s6, s9, s6
; SI-NEXT:    s_or_b32 s8, s5, s8
; SI-NEXT:    s_cmp_lt_i32 s7, 1
; SI-NEXT:    s_cselect_b32 s6, s6, s8
; SI-NEXT:    s_and_b32 s8, s6, 7
; SI-NEXT:    s_cmp_gt_i32 s8, 5
; SI-NEXT:    s_cselect_b32 s9, 1, 0
; SI-NEXT:    s_cmp_eq_u32 s8, 3
; SI-NEXT:    s_cselect_b32 s8, 1, 0
; SI-NEXT:    s_or_b32 s8, s8, s9
; SI-NEXT:    s_lshr_b32 s6, s6, 2
; SI-NEXT:    s_add_i32 s6, s6, s8
; SI-NEXT:    s_cmp_lt_i32 s7, 31
; SI-NEXT:    s_cselect_b32 s6, s6, 0x7c00
; SI-NEXT:    s_cmp_lg_u32 s5, 0
; SI-NEXT:    s_movk_i32 s5, 0x7e00
; SI-NEXT:    s_cselect_b32 s5, s5, 0x7c00
; SI-NEXT:    s_cmpk_eq_i32 s7, 0x40f
; SI-NEXT:    s_cselect_b32 s5, s5, s6
; SI-NEXT:    s_lshr_b32 s4, s4, 16
; SI-NEXT:    s_and_b32 s4, s4, 0x8000
; SI-NEXT:    s_or_b32 s4, s4, s5
; SI-NEXT:    v_mov_b32_e32 v0, s4
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; CI-LABEL: unsafe_frem_f16_uniform:
; CI:       ; %bb.0:
; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-NEXT:    v_cvt_f32_f16_e32 v4, s17
; CI-NEXT:    v_cvt_f32_f16_e32 v2, s16
; CI-NEXT:    v_div_scale_f32 v1, s[4:5], v4, v4, v2
; CI-NEXT:    v_div_scale_f32 v0, vcc, v2, v4, v2
; CI-NEXT:    v_rcp_f32_e32 v3, v1
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v5, -v1, v3, 1.0
; CI-NEXT:    v_fma_f32 v3, v5, v3, v3
; CI-NEXT:    v_mul_f32_e32 v5, v0, v3
; CI-NEXT:    v_fma_f32 v6, -v1, v5, v0
; CI-NEXT:    v_fma_f32 v5, v6, v3, v5
; CI-NEXT:    v_fma_f32 v0, -v1, v5, v0
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v0, v0, v3, v5
; CI-NEXT:    v_div_fixup_f32 v0, v0, v4, v2
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; CI-NEXT:    v_cvt_f64_f32_e32 v[2:3], v2
; CI-NEXT:    v_cvt_f64_f32_e32 v[4:5], v4
; CI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; CI-NEXT:    v_trunc_f32_e32 v0, v0
; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; CI-NEXT:    v_cvt_f32_f16_e64 v0, -v0
; CI-NEXT:    v_cvt_f64_f32_e32 v[0:1], v0
; CI-NEXT:    v_fma_f64 v[0:1], v[0:1], v[4:5], v[2:3]
; CI-NEXT:    v_readfirstlane_b32 s4, v1
; CI-NEXT:    s_and_b32 s5, s4, 0x1ff
; CI-NEXT:    v_readfirstlane_b32 s6, v0
; CI-NEXT:    s_or_b32 s5, s5, s6
; CI-NEXT:    s_cselect_b32 s5, 1, 0
; CI-NEXT:    s_lshr_b32 s6, s4, 8
; CI-NEXT:    s_bfe_u32 s7, s4, 0xb0014
; CI-NEXT:    s_and_b32 s6, s6, 0xffe
; CI-NEXT:    s_sub_i32 s8, 0x3f1, s7
; CI-NEXT:    s_or_b32 s5, s6, s5
; CI-NEXT:    v_med3_i32 v0, s8, 0, 13
; CI-NEXT:    s_or_b32 s6, s5, 0x1000
; CI-NEXT:    v_readfirstlane_b32 s8, v0
; CI-NEXT:    s_lshr_b32 s9, s6, s8
; CI-NEXT:    s_lshl_b32 s8, s9, s8
; CI-NEXT:    s_cmp_lg_u32 s8, s6
; CI-NEXT:    s_cselect_b32 s6, 1, 0
; CI-NEXT:    s_addk_i32 s7, 0xfc10
; CI-NEXT:    s_lshl_b32 s8, s7, 12
; CI-NEXT:    s_or_b32 s6, s9, s6
; CI-NEXT:    s_or_b32 s8, s5, s8
; CI-NEXT:    s_cmp_lt_i32 s7, 1
; CI-NEXT:    s_cselect_b32 s6, s6, s8
; CI-NEXT:    s_and_b32 s8, s6, 7
; CI-NEXT:    s_cmp_gt_i32 s8, 5
; CI-NEXT:    s_cselect_b32 s9, 1, 0
; CI-NEXT:    s_cmp_eq_u32 s8, 3
; CI-NEXT:    s_cselect_b32 s8, 1, 0
; CI-NEXT:    s_or_b32 s8, s8, s9
; CI-NEXT:    s_lshr_b32 s6, s6, 2
; CI-NEXT:    s_add_i32 s6, s6, s8
; CI-NEXT:    s_cmp_lt_i32 s7, 31
; CI-NEXT:    s_cselect_b32 s6, s6, 0x7c00
; CI-NEXT:    s_cmp_lg_u32 s5, 0
; CI-NEXT:    s_movk_i32 s5, 0x7e00
; CI-NEXT:    s_cselect_b32 s5, s5, 0x7c00
; CI-NEXT:    s_cmpk_eq_i32 s7, 0x40f
; CI-NEXT:    s_cselect_b32 s5, s5, s6
; CI-NEXT:    s_lshr_b32 s4, s4, 16
; CI-NEXT:    s_and_b32 s4, s4, 0x8000
; CI-NEXT:    s_or_b32 s4, s4, s5
; CI-NEXT:    v_mov_b32_e32 v0, s4
; CI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: unsafe_frem_f16_uniform:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cvt_f32_f16_e32 v1, s17
; VI-NEXT:    v_cvt_f32_f16_e32 v0, s16
; VI-NEXT:    v_rcp_f32_e32 v2, v1
; VI-NEXT:    v_mul_f32_e32 v3, v0, v2
; VI-NEXT:    v_mad_f32 v4, -v1, v3, v0
; VI-NEXT:    v_mac_f32_e32 v3, v4, v2
; VI-NEXT:    v_mad_f32 v0, -v1, v3, v0
; VI-NEXT:    v_mul_f32_e32 v0, v0, v2
; VI-NEXT:    v_and_b32_e32 v0, 0xff800000, v0
; VI-NEXT:    v_add_f32_e32 v0, v0, v3
; VI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; VI-NEXT:    v_mov_b32_e32 v1, s16
; VI-NEXT:    v_div_fixup_f16 v0, v0, s17, v1
; VI-NEXT:    v_trunc_f16_e32 v0, v0
; VI-NEXT:    v_fma_f16 v0, -v0, s17, v1
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: unsafe_frem_f16_uniform:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_f32_f16_e32 v0, s17
; GFX9-NEXT:    v_mov_b32_e32 v2, s16
; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
; GFX9-NEXT:    v_mad_mix_f32 v1, s16, v0, neg(0) op_sel_hi:[1,0,0]
; GFX9-NEXT:    v_mad_mix_f32 v3, -s17, v1, v2 op_sel_hi:[1,0,1]
; GFX9-NEXT:    v_mac_f32_e32 v1, v3, v0
; GFX9-NEXT:    v_mad_mix_f32 v3, -s17, v1, v2 op_sel_hi:[1,0,1]
; GFX9-NEXT:    v_mul_f32_e32 v0, v3, v0
; GFX9-NEXT:    v_and_b32_e32 v0, 0xff800000, v0
; GFX9-NEXT:    v_add_f32_e32 v0, v0, v1
; GFX9-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX9-NEXT:    v_div_fixup_f16 v0, v0, s17, v2
; GFX9-NEXT:    v_trunc_f16_e32 v0, v0
; GFX9-NEXT:    v_fma_f16 v0, -v0, s17, v2
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: unsafe_frem_f16_uniform:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cvt_f32_f16_e32 v0, s17
; GFX10-NEXT:    v_cvt_f32_f16_e32 v3, s16
; GFX10-NEXT:    v_rcp_f32_e32 v1, v0
; GFX10-NEXT:    v_fma_mix_f32 v2, s16, v1, neg(0) op_sel_hi:[1,0,0]
; GFX10-NEXT:    v_mad_f32 v4, -v0, v2, v3
; GFX10-NEXT:    v_mac_f32_e32 v2, v4, v1
; GFX10-NEXT:    v_mad_f32 v0, -v0, v2, v3
; GFX10-NEXT:    v_mul_f32_e32 v0, v0, v1
; GFX10-NEXT:    v_and_b32_e32 v0, 0xff800000, v0
; GFX10-NEXT:    v_fma_mixlo_f16 v0, v0, 1.0, v2 op_sel_hi:[0,1,0]
; GFX10-NEXT:    v_div_fixup_f16 v0, v0, s17, s16
; GFX10-NEXT:    v_trunc_f16_e32 v0, v0
; GFX10-NEXT:    v_fma_f16 v0, -v0, s17, s16
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: unsafe_frem_f16_uniform:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, s1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v0, v0
; GFX11-TRUE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v1, s0, v0, neg(0) op_sel_hi:[1,0,0]
; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v2, -s1, v1, s0 op_sel_hi:[1,0,1]
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v1, v2, v0
; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v2, -s1, v1, s0 op_sel_hi:[1,0,1]
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v0, v2, v0
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xff800000, v0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_mixlo_f16 v0, v0, 1.0, v1 op_sel_hi:[0,1,0]
; GFX11-TRUE16-NEXT:    v_div_fixup_f16 v0.l, v0.l, s1, s0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_trunc_f16_e32 v0.l, v0.l
; GFX11-TRUE16-NEXT:    v_fma_f16 v0.l, -v0.l, s1, s0
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: unsafe_frem_f16_uniform:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, s1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v0, v0
; GFX11-FAKE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v1, s0, v0, neg(0) op_sel_hi:[1,0,0]
; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v2, -s1, v1, s0 op_sel_hi:[1,0,1]
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v1, v2, v0
; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v2, -s1, v1, s0 op_sel_hi:[1,0,1]
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v0, v2, v0
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff800000, v0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_mixlo_f16 v0, v0, 1.0, v1 op_sel_hi:[0,1,0]
; GFX11-FAKE16-NEXT:    v_div_fixup_f16 v0, v0, s1, s0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_trunc_f16_e32 v0, v0
; GFX11-FAKE16-NEXT:    v_fma_f16 v0, -v0, s1, s0
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-TRUE16-LABEL: unsafe_frem_f16_uniform:
; GFX1150-TRUE16:       ; %bb.0:
; GFX1150-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-TRUE16-NEXT:    s_cvt_f32_f16 s2, s1
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(TRANS32_DEP_1)
; GFX1150-TRUE16-NEXT:    v_rcp_f32_e32 v0, s2
; GFX1150-TRUE16-NEXT:    v_fma_mix_f32 v1, s0, v0, neg(0) op_sel_hi:[1,0,0]
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fma_mix_f32 v2, -s1, v1, s0 op_sel_hi:[1,0,1]
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v1, v2, v0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fma_mix_f32 v2, -s1, v1, s0 op_sel_hi:[1,0,1]
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v0, v2, v0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_and_b32_e32 v0, 0xff800000, v0
; GFX1150-TRUE16-NEXT:    v_fma_mixlo_f16 v0, v0, 1.0, v1 op_sel_hi:[0,1,0]
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_div_fixup_f16 v0.l, v0.l, s1, s0
; GFX1150-TRUE16-NEXT:    v_trunc_f16_e32 v0.l, v0.l
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v0, 0x8000, v0
; GFX1150-TRUE16-NEXT:    v_fma_f16 v0.l, v0.l, s1, s0
; GFX1150-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-FAKE16-LABEL: unsafe_frem_f16_uniform:
; GFX1150-FAKE16:       ; %bb.0:
; GFX1150-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-FAKE16-NEXT:    s_cvt_f32_f16 s2, s1
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(TRANS32_DEP_1)
; GFX1150-FAKE16-NEXT:    v_rcp_f32_e32 v0, s2
; GFX1150-FAKE16-NEXT:    v_fma_mix_f32 v1, s0, v0, neg(0) op_sel_hi:[1,0,0]
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fma_mix_f32 v2, -s1, v1, s0 op_sel_hi:[1,0,1]
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v1, v2, v0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fma_mix_f32 v2, -s1, v1, s0 op_sel_hi:[1,0,1]
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v0, v2, v0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff800000, v0
; GFX1150-FAKE16-NEXT:    v_fma_mixlo_f16 v0, v0, 1.0, v1 op_sel_hi:[0,1,0]
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_div_fixup_f16 v0, v0, s1, s0
; GFX1150-FAKE16-NEXT:    v_trunc_f16_e32 v0, v0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v0, 0x8000, v0
; GFX1150-FAKE16-NEXT:    v_fma_f16 v0, v0, s1, s0
; GFX1150-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-TRUE16-LABEL: unsafe_frem_f16_uniform:
; GFX1200-TRUE16:       ; %bb.0:
; GFX1200-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1200-TRUE16-NEXT:    s_cvt_f32_f16 s2, s1
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
; GFX1200-TRUE16-NEXT:    v_s_rcp_f32 s2, s2
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)
; GFX1200-TRUE16-NEXT:    v_fma_mix_f32 v0, s0, s2, neg(0) op_sel_hi:[1,0,0]
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_mix_f32 v1, -s1, v0, s0 op_sel_hi:[1,0,1]
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v0, s2, v1
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_mix_f32 v1, -s1, v0, s0 op_sel_hi:[1,0,1]
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v1, s2, v1
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_and_b32_e32 v1, 0xff800000, v1
; GFX1200-TRUE16-NEXT:    v_fma_mixlo_f16 v0, v1, 1.0, v0 op_sel_hi:[0,1,0]
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_div_fixup_f16 v0.l, v0.l, s1, s0
; GFX1200-TRUE16-NEXT:    v_trunc_f16_e32 v0.l, v0.l
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v0, 0x8000, v0
; GFX1200-TRUE16-NEXT:    v_fma_f16 v0.l, v0.l, s1, s0
; GFX1200-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-FAKE16-LABEL: unsafe_frem_f16_uniform:
; GFX1200-FAKE16:       ; %bb.0:
; GFX1200-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1200-FAKE16-NEXT:    s_cvt_f32_f16 s2, s1
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
; GFX1200-FAKE16-NEXT:    v_s_rcp_f32 s2, s2
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_sdst(0)
; GFX1200-FAKE16-NEXT:    v_fma_mix_f32 v0, s0, s2, neg(0) op_sel_hi:[1,0,0]
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_mix_f32 v1, -s1, v0, s0 op_sel_hi:[1,0,1]
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v0, s2, v1
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_mix_f32 v1, -s1, v0, s0 op_sel_hi:[1,0,1]
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v1, s2, v1
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff800000, v1
; GFX1200-FAKE16-NEXT:    v_fma_mixlo_f16 v0, v1, 1.0, v0 op_sel_hi:[0,1,0]
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_div_fixup_f16 v0, v0, s1, s0
; GFX1200-FAKE16-NEXT:    v_trunc_f16_e32 v0, v0
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v0, 0x8000, v0
; GFX1200-FAKE16-NEXT:    v_fma_f16 v0, v0, s1, s0
; GFX1200-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %r2 = frem afn half %in1, %in2
  ret half %r2
}

define float @frem_f32_uniform(float inreg %in1, float inreg %in2) #0 {
; SI-LABEL: frem_f32_uniform:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_mov_b32_e32 v0, s17
; SI-NEXT:    v_cmp_gt_f32_e64 vcc, |s16|, |v0|
; SI-NEXT:    s_cbranch_vccz .LBB20_4
; SI-NEXT:  ; %bb.1: ; %frem.compute
; SI-NEXT:    v_mov_b32_e32 v0, 0x7f800000
; SI-NEXT:    v_cmp_lt_f32_e64 s[4:5], |s16|, v0
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v1, s16
; SI-NEXT:    s_and_b64 s[6:7], s[4:5], exec
; SI-NEXT:    v_readfirstlane_b32 s6, v1
; SI-NEXT:    v_frexp_mant_f32_e64 v1, |s16|
; SI-NEXT:    v_mov_b32_e32 v2, s16
; SI-NEXT:    v_cndmask_b32_e64 v1, |v2|, v1, s[4:5]
; SI-NEXT:    v_cmp_lt_f32_e64 s[4:5], |s17|, v0
; SI-NEXT:    v_frexp_mant_f32_e64 v0, |s17|
; SI-NEXT:    v_mov_b32_e32 v2, s17
; SI-NEXT:    v_cndmask_b32_e64 v0, |v2|, v0, s[4:5]
; SI-NEXT:    v_ldexp_f32_e64 v0, v0, 1
; SI-NEXT:    v_div_scale_f32 v3, s[8:9], v0, v0, 1.0
; SI-NEXT:    v_rcp_f32_e32 v4, v3
; SI-NEXT:    s_cselect_b32 s6, s6, 0
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v2, s17
; SI-NEXT:    s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT:    v_ldexp_f32_e64 v1, v1, 12
; SI-NEXT:    v_readfirstlane_b32 s4, v2
; SI-NEXT:    v_div_scale_f32 v2, vcc, 1.0, v0, 1.0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
; SI-NEXT:    v_fma_f32 v4, v5, v4, v4
; SI-NEXT:    v_mul_f32_e32 v5, v2, v4
; SI-NEXT:    s_cselect_b32 s7, s4, 0
; SI-NEXT:    v_fma_f32 v6, -v3, v5, v2
; SI-NEXT:    s_add_i32 s4, s7, -1
; SI-NEXT:    v_fma_f32 v5, v6, v4, v5
; SI-NEXT:    s_not_b32 s5, s4
; SI-NEXT:    v_fma_f32 v2, -v3, v5, v2
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    s_add_i32 s5, s5, s6
; SI-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
; SI-NEXT:    v_div_fixup_f32 v2, v2, v0, 1.0
; SI-NEXT:    s_cmp_lt_i32 s5, 13
; SI-NEXT:    s_cbranch_scc1 .LBB20_5
; SI-NEXT:  ; %bb.2: ; %frem.loop_body.preheader
; SI-NEXT:    s_sub_i32 s5, s6, s7
; SI-NEXT:    s_add_i32 s5, s5, 12
; SI-NEXT:  .LBB20_3: ; %frem.loop_body
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v3, v1
; SI-NEXT:    v_mul_f32_e32 v1, v3, v2
; SI-NEXT:    v_rndne_f32_e32 v1, v1
; SI-NEXT:    v_fma_f32 v1, -v1, v0, v3
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v1
; SI-NEXT:    v_add_f32_e32 v4, v1, v0
; SI-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
; SI-NEXT:    s_add_i32 s5, s5, -12
; SI-NEXT:    v_ldexp_f32_e64 v1, v1, 12
; SI-NEXT:    s_cmp_gt_i32 s5, 12
; SI-NEXT:    s_cbranch_scc1 .LBB20_3
; SI-NEXT:    s_branch .LBB20_6
; SI-NEXT:  .LBB20_4: ; %frem.else
; SI-NEXT:    s_and_b32 s4, 0x80000000, s16
; SI-NEXT:    v_mov_b32_e32 v0, s17
; SI-NEXT:    v_cmp_eq_f32_e64 vcc, |s16|, |v0|
; SI-NEXT:    v_mov_b32_e32 v0, s16
; SI-NEXT:    v_mov_b32_e32 v1, s4
; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-NEXT:    s_branch .LBB20_7
; SI-NEXT:  .LBB20_5:
; SI-NEXT:    v_mov_b32_e32 v3, v1
; SI-NEXT:  .LBB20_6: ; %frem.loop_exit
; SI-NEXT:    s_add_i32 s5, s5, -11
; SI-NEXT:    v_ldexp_f32_e64 v1, v3, s5
; SI-NEXT:    v_mul_f32_e32 v2, v1, v2
; SI-NEXT:    v_rndne_f32_e32 v2, v2
; SI-NEXT:    v_fma_f32 v1, -v2, v0, v1
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v1
; SI-NEXT:    v_add_f32_e32 v0, v1, v0
; SI-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; SI-NEXT:    v_ldexp_f32_e64 v0, v0, s4
; SI-NEXT:    s_brev_b32 s4, -2
; SI-NEXT:    v_mov_b32_e32 v1, s16
; SI-NEXT:    v_bfi_b32 v0, s4, v0, v1
; SI-NEXT:  .LBB20_7:
; SI-NEXT:    v_mov_b32_e32 v1, 0x7f800000
; SI-NEXT:    v_cmp_lg_f32_e64 s[4:5], s17, 0
; SI-NEXT:    v_cmp_nge_f32_e64 s[6:7], |s16|, v1
; SI-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; SI-NEXT:    v_mov_b32_e32 v1, 0x7fc00000
; SI-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; CI-LABEL: frem_f32_uniform:
; CI:       ; %bb.0:
; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-NEXT:    v_mov_b32_e32 v0, s17
; CI-NEXT:    v_cmp_gt_f32_e64 vcc, |s16|, |v0|
; CI-NEXT:    s_cbranch_vccz .LBB20_4
; CI-NEXT:  ; %bb.1: ; %frem.compute
; CI-NEXT:    v_frexp_mant_f32_e64 v1, |s17|
; CI-NEXT:    v_ldexp_f32_e64 v1, v1, 1
; CI-NEXT:    v_div_scale_f32 v7, s[4:5], v1, v1, 1.0
; CI-NEXT:    v_frexp_mant_f32_e64 v0, |s16|
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v6, s17
; CI-NEXT:    v_ldexp_f32_e64 v4, v0, 12
; CI-NEXT:    v_add_i32_e32 v0, vcc, -1, v6
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v5, s16
; CI-NEXT:    v_not_b32_e32 v2, v0
; CI-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
; CI-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v1, 1.0
; CI-NEXT:    v_rcp_f32_e32 v8, v7
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
; CI-NEXT:    v_fma_f32 v8, v9, v8, v8
; CI-NEXT:    v_mul_f32_e32 v9, v3, v8
; CI-NEXT:    v_fma_f32 v10, -v7, v9, v3
; CI-NEXT:    v_fma_f32 v9, v10, v8, v9
; CI-NEXT:    v_fma_f32 v3, -v7, v9, v3
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v3, v3, v8, v9
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v2
; CI-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; CI-NEXT:    s_cbranch_vccnz .LBB20_5
; CI-NEXT:  ; %bb.2: ; %frem.loop_body.preheader
; CI-NEXT:    v_sub_i32_e32 v2, vcc, v5, v6
; CI-NEXT:    v_add_i32_e32 v2, vcc, 12, v2
; CI-NEXT:  .LBB20_3: ; %frem.loop_body
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v5, v4
; CI-NEXT:    v_mul_f32_e32 v4, v5, v3
; CI-NEXT:    v_rndne_f32_e32 v4, v4
; CI-NEXT:    v_fma_f32 v4, -v4, v1, v5
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; CI-NEXT:    v_add_f32_e32 v6, v4, v1
; CI-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
; CI-NEXT:    v_add_i32_e32 v2, vcc, -12, v2
; CI-NEXT:    v_ldexp_f32_e64 v4, v4, 12
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v2
; CI-NEXT:    s_cbranch_vccnz .LBB20_3
; CI-NEXT:    s_branch .LBB20_6
; CI-NEXT:  .LBB20_4: ; %frem.else
; CI-NEXT:    s_and_b32 s4, 0x80000000, s16
; CI-NEXT:    v_mov_b32_e32 v0, s17
; CI-NEXT:    v_cmp_eq_f32_e64 vcc, |s16|, |v0|
; CI-NEXT:    v_mov_b32_e32 v0, s16
; CI-NEXT:    v_mov_b32_e32 v1, s4
; CI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
; CI-NEXT:    s_branch .LBB20_7
; CI-NEXT:  .LBB20_5:
; CI-NEXT:    v_mov_b32_e32 v5, v4
; CI-NEXT:  .LBB20_6: ; %frem.loop_exit
; CI-NEXT:    v_add_i32_e32 v2, vcc, -11, v2
; CI-NEXT:    v_ldexp_f32_e32 v2, v5, v2
; CI-NEXT:    v_mul_f32_e32 v3, v2, v3
; CI-NEXT:    v_rndne_f32_e32 v3, v3
; CI-NEXT:    v_fma_f32 v2, -v3, v1, v2
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v2
; CI-NEXT:    v_add_f32_e32 v1, v2, v1
; CI-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; CI-NEXT:    v_ldexp_f32_e32 v0, v1, v0
; CI-NEXT:    s_brev_b32 s4, -2
; CI-NEXT:    v_mov_b32_e32 v1, s16
; CI-NEXT:    v_bfi_b32 v0, s4, v0, v1
; CI-NEXT:  .LBB20_7:
; CI-NEXT:    v_mov_b32_e32 v1, 0x7f800000
; CI-NEXT:    v_cmp_lg_f32_e64 s[4:5], s17, 0
; CI-NEXT:    v_cmp_nge_f32_e64 s[6:7], |s16|, v1
; CI-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; CI-NEXT:    v_mov_b32_e32 v1, 0x7fc00000
; CI-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; CI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: frem_f32_uniform:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_mov_b32_e32 v0, s17
; VI-NEXT:    v_cmp_gt_f32_e64 vcc, |s16|, |v0|
; VI-NEXT:    s_cbranch_vccz .LBB20_4
; VI-NEXT:  ; %bb.1: ; %frem.compute
; VI-NEXT:    v_frexp_mant_f32_e64 v1, |s17|
; VI-NEXT:    v_ldexp_f32 v1, v1, 1
; VI-NEXT:    v_div_scale_f32 v7, s[4:5], v1, v1, 1.0
; VI-NEXT:    v_frexp_mant_f32_e64 v0, |s16|
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v6, s17
; VI-NEXT:    v_ldexp_f32 v4, v0, 12
; VI-NEXT:    v_add_u32_e32 v0, vcc, -1, v6
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v5, s16
; VI-NEXT:    v_not_b32_e32 v2, v0
; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v5
; VI-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v1, 1.0
; VI-NEXT:    v_rcp_f32_e32 v8, v7
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
; VI-NEXT:    v_fma_f32 v8, v9, v8, v8
; VI-NEXT:    v_mul_f32_e32 v9, v3, v8
; VI-NEXT:    v_fma_f32 v10, -v7, v9, v3
; VI-NEXT:    v_fma_f32 v9, v10, v8, v9
; VI-NEXT:    v_fma_f32 v3, -v7, v9, v3
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; VI-NEXT:    v_div_fmas_f32 v3, v3, v8, v9
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v2
; VI-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; VI-NEXT:    s_cbranch_vccnz .LBB20_5
; VI-NEXT:  ; %bb.2: ; %frem.loop_body.preheader
; VI-NEXT:    v_sub_u32_e32 v2, vcc, v5, v6
; VI-NEXT:    v_add_u32_e32 v2, vcc, 12, v2
; VI-NEXT:  .LBB20_3: ; %frem.loop_body
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v5, v4
; VI-NEXT:    v_mul_f32_e32 v4, v5, v3
; VI-NEXT:    v_rndne_f32_e32 v4, v4
; VI-NEXT:    v_fma_f32 v4, -v4, v1, v5
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; VI-NEXT:    v_add_f32_e32 v6, v4, v1
; VI-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
; VI-NEXT:    v_add_u32_e32 v2, vcc, -12, v2
; VI-NEXT:    v_ldexp_f32 v4, v4, 12
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v2
; VI-NEXT:    s_cbranch_vccnz .LBB20_3
; VI-NEXT:    s_branch .LBB20_6
; VI-NEXT:  .LBB20_4: ; %frem.else
; VI-NEXT:    s_and_b32 s4, 0x80000000, s16
; VI-NEXT:    v_mov_b32_e32 v0, s17
; VI-NEXT:    v_cmp_eq_f32_e64 vcc, |s16|, |v0|
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
; VI-NEXT:    s_branch .LBB20_7
; VI-NEXT:  .LBB20_5:
; VI-NEXT:    v_mov_b32_e32 v5, v4
; VI-NEXT:  .LBB20_6: ; %frem.loop_exit
; VI-NEXT:    v_add_u32_e32 v2, vcc, -11, v2
; VI-NEXT:    v_ldexp_f32 v2, v5, v2
; VI-NEXT:    v_mul_f32_e32 v3, v2, v3
; VI-NEXT:    v_rndne_f32_e32 v3, v3
; VI-NEXT:    v_fma_f32 v2, -v3, v1, v2
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v2
; VI-NEXT:    v_add_f32_e32 v1, v2, v1
; VI-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; VI-NEXT:    v_ldexp_f32 v0, v1, v0
; VI-NEXT:    s_brev_b32 s4, -2
; VI-NEXT:    v_mov_b32_e32 v1, s16
; VI-NEXT:    v_bfi_b32 v0, s4, v0, v1
; VI-NEXT:  .LBB20_7:
; VI-NEXT:    v_mov_b32_e32 v1, 0x7f800000
; VI-NEXT:    v_cmp_lg_f32_e64 s[4:5], s17, 0
; VI-NEXT:    v_cmp_nge_f32_e64 s[6:7], |s16|, v1
; VI-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; VI-NEXT:    v_mov_b32_e32 v1, 0x7fc00000
; VI-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: frem_f32_uniform:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v0, s17
; GFX9-NEXT:    v_cmp_gt_f32_e64 vcc, |s16|, |v0|
; GFX9-NEXT:    s_cbranch_vccz .LBB20_4
; GFX9-NEXT:  ; %bb.1: ; %frem.compute
; GFX9-NEXT:    v_frexp_mant_f32_e64 v1, |s17|
; GFX9-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX9-NEXT:    v_div_scale_f32 v7, s[4:5], v1, v1, 1.0
; GFX9-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v1, 1.0
; GFX9-NEXT:    v_frexp_mant_f32_e64 v0, |s16|
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v5, s16
; GFX9-NEXT:    v_ldexp_f32 v4, v0, 12
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v6, s17
; GFX9-NEXT:    v_add_u32_e32 v0, -1, v6
; GFX9-NEXT:    v_not_b32_e32 v2, v0
; GFX9-NEXT:    v_add_u32_e32 v2, v2, v5
; GFX9-NEXT:    v_rcp_f32_e32 v8, v7
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
; GFX9-NEXT:    v_fma_f32 v8, v9, v8, v8
; GFX9-NEXT:    v_mul_f32_e32 v9, v3, v8
; GFX9-NEXT:    v_fma_f32 v10, -v7, v9, v3
; GFX9-NEXT:    v_fma_f32 v9, v10, v8, v9
; GFX9-NEXT:    v_fma_f32 v3, -v7, v9, v3
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX9-NEXT:    v_div_fmas_f32 v3, v3, v8, v9
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v2
; GFX9-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX9-NEXT:    s_cbranch_vccnz .LBB20_5
; GFX9-NEXT:  ; %bb.2: ; %frem.loop_body.preheader
; GFX9-NEXT:    v_sub_u32_e32 v2, v5, v6
; GFX9-NEXT:    v_add_u32_e32 v2, 12, v2
; GFX9-NEXT:  .LBB20_3: ; %frem.loop_body
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v5, v4
; GFX9-NEXT:    v_mul_f32_e32 v4, v5, v3
; GFX9-NEXT:    v_rndne_f32_e32 v4, v4
; GFX9-NEXT:    v_fma_f32 v4, -v4, v1, v5
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; GFX9-NEXT:    v_add_f32_e32 v6, v4, v1
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX9-NEXT:    v_add_u32_e32 v2, -12, v2
; GFX9-NEXT:    v_ldexp_f32 v4, v4, 12
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v2
; GFX9-NEXT:    s_cbranch_vccnz .LBB20_3
; GFX9-NEXT:    s_branch .LBB20_6
; GFX9-NEXT:  .LBB20_4: ; %frem.else
; GFX9-NEXT:    s_and_b32 s4, 0x80000000, s16
; GFX9-NEXT:    v_mov_b32_e32 v0, s17
; GFX9-NEXT:    v_cmp_eq_f32_e64 vcc, |s16|, |v0|
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s4
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX9-NEXT:    s_branch .LBB20_7
; GFX9-NEXT:  .LBB20_5:
; GFX9-NEXT:    v_mov_b32_e32 v5, v4
; GFX9-NEXT:  .LBB20_6: ; %frem.loop_exit
; GFX9-NEXT:    v_add_u32_e32 v2, -11, v2
; GFX9-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX9-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX9-NEXT:    v_rndne_f32_e32 v3, v3
; GFX9-NEXT:    v_fma_f32 v2, -v3, v1, v2
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v2
; GFX9-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX9-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX9-NEXT:    s_brev_b32 s4, -2
; GFX9-NEXT:    v_mov_b32_e32 v1, s16
; GFX9-NEXT:    v_bfi_b32 v0, s4, v0, v1
; GFX9-NEXT:  .LBB20_7:
; GFX9-NEXT:    v_mov_b32_e32 v1, 0x7f800000
; GFX9-NEXT:    v_cmp_lg_f32_e64 s[4:5], s17, 0
; GFX9-NEXT:    v_cmp_nge_f32_e64 s[6:7], |s16|, v1
; GFX9-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; GFX9-NEXT:    v_mov_b32_e32 v1, 0x7fc00000
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: frem_f32_uniform:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cmp_gt_f32_e64 vcc_lo, |s16|, |s17|
; GFX10-NEXT:    s_cbranch_vccz .LBB20_5
; GFX10-NEXT:  ; %bb.1: ; %frem.compute
; GFX10-NEXT:    v_frexp_mant_f32_e64 v1, |s17|
; GFX10-NEXT:    v_frexp_mant_f32_e64 v0, |s16|
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v3, s16
; GFX10-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX10-NEXT:    v_ldexp_f32 v2, v0, 12
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v0, s17
; GFX10-NEXT:    v_readfirstlane_b32 s4, v3
; GFX10-NEXT:    v_div_scale_f32 v5, s6, v1, v1, 1.0
; GFX10-NEXT:    v_readfirstlane_b32 s5, v0
; GFX10-NEXT:    v_add_nc_u32_e32 v0, -1, v0
; GFX10-NEXT:    v_rcp_f32_e32 v6, v5
; GFX10-NEXT:    v_not_b32_e32 v4, v0
; GFX10-NEXT:    v_add_nc_u32_e32 v4, v4, v3
; GFX10-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX10-NEXT:    s_denorm_mode 15
; GFX10-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
; GFX10-NEXT:    v_fmac_f32_e32 v6, v7, v6
; GFX10-NEXT:    v_mul_f32_e32 v7, v3, v6
; GFX10-NEXT:    v_fma_f32 v8, -v5, v7, v3
; GFX10-NEXT:    v_fmac_f32_e32 v7, v8, v6
; GFX10-NEXT:    v_fma_f32 v3, -v5, v7, v3
; GFX10-NEXT:    s_denorm_mode 12
; GFX10-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v4
; GFX10-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX10-NEXT:    s_cbranch_vccnz .LBB20_6
; GFX10-NEXT:  ; %bb.2: ; %frem.loop_body.preheader
; GFX10-NEXT:    s_sub_i32 s4, s4, s5
; GFX10-NEXT:    s_add_i32 s4, s4, 12
; GFX10-NEXT:  .LBB20_3: ; %frem.loop_body
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v5, v2
; GFX10-NEXT:    s_add_i32 s4, s4, -12
; GFX10-NEXT:    s_cmp_gt_i32 s4, 12
; GFX10-NEXT:    v_mul_f32_e32 v2, v5, v3
; GFX10-NEXT:    v_rndne_f32_e32 v2, v2
; GFX10-NEXT:    v_fma_f32 v2, -v2, v1, v5
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX10-NEXT:    v_add_f32_e32 v4, v2, v1
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v2, v2, 12
; GFX10-NEXT:    s_cbranch_scc1 .LBB20_3
; GFX10-NEXT:  ; %bb.4:
; GFX10-NEXT:    v_mov_b32_e32 v4, s4
; GFX10-NEXT:    s_branch .LBB20_7
; GFX10-NEXT:  .LBB20_5: ; %frem.else
; GFX10-NEXT:    s_and_b32 s4, 0x80000000, s16
; GFX10-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |s16|, |s17|
; GFX10-NEXT:    v_mov_b32_e32 v0, s4
; GFX10-NEXT:    v_cndmask_b32_e32 v0, s16, v0, vcc_lo
; GFX10-NEXT:    s_branch .LBB20_8
; GFX10-NEXT:  .LBB20_6:
; GFX10-NEXT:    v_mov_b32_e32 v5, v2
; GFX10-NEXT:  .LBB20_7: ; %frem.loop_exit
; GFX10-NEXT:    v_add_nc_u32_e32 v2, -11, v4
; GFX10-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX10-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX10-NEXT:    v_rndne_f32_e32 v3, v3
; GFX10-NEXT:    v_fma_f32 v2, -v3, v1, v2
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX10-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX10-NEXT:    v_bfi_b32 v0, 0x7fffffff, v0, s16
; GFX10-NEXT:  .LBB20_8:
; GFX10-NEXT:    v_cmp_lg_f32_e64 s4, s17, 0
; GFX10-NEXT:    v_cmp_nge_f32_e64 s5, |s16|, 0x7f800000
; GFX10-NEXT:    s_and_b32 vcc_lo, s5, s4
; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: frem_f32_uniform:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cmp_gt_f32_e64 vcc_lo, |s0|, |s1|
; GFX11-NEXT:    s_cbranch_vccz .LBB20_5
; GFX11-NEXT:  ; %bb.1: ; %frem.compute
; GFX11-NEXT:    v_frexp_mant_f32_e64 v1, |s1|
; GFX11-NEXT:    v_frexp_mant_f32_e64 v0, |s0|
; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v3, s0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX11-NEXT:    v_ldexp_f32 v2, v0, 12
; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v0, s1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_readfirstlane_b32 s2, v3
; GFX11-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_readfirstlane_b32 s3, v0
; GFX11-NEXT:    v_add_nc_u32_e32 v0, -1, v0
; GFX11-NEXT:    v_rcp_f32_e32 v6, v5
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_not_b32_e32 v4, v0
; GFX11-NEXT:    v_add_nc_u32_e32 v4, v4, v3
; GFX11-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX11-NEXT:    s_denorm_mode 15
; GFX11-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fmac_f32_e32 v6, v7, v6
; GFX11-NEXT:    v_mul_f32_e32 v7, v3, v6
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v8, -v5, v7, v3
; GFX11-NEXT:    v_fmac_f32_e32 v7, v8, v6
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v3, -v5, v7, v3
; GFX11-NEXT:    s_denorm_mode 12
; GFX11-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v4
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX11-NEXT:    s_cbranch_vccnz .LBB20_6
; GFX11-NEXT:  ; %bb.2: ; %frem.loop_body.preheader
; GFX11-NEXT:    s_sub_i32 s2, s2, s3
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_add_i32 s2, s2, 12
; GFX11-NEXT:  .LBB20_3: ; %frem.loop_body
; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT:    v_mov_b32_e32 v5, v2
; GFX11-NEXT:    s_add_i32 s2, s2, -12
; GFX11-NEXT:    s_cmp_gt_i32 s2, 12
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_mul_f32_e32 v2, v5, v3
; GFX11-NEXT:    v_rndne_f32_e32 v2, v2
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v2, -v2, v1, v5
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX11-NEXT:    v_add_f32_e32 v4, v2, v1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX11-NEXT:    v_ldexp_f32 v2, v2, 12
; GFX11-NEXT:    s_cbranch_scc1 .LBB20_3
; GFX11-NEXT:  ; %bb.4:
; GFX11-NEXT:    v_mov_b32_e32 v4, s2
; GFX11-NEXT:    s_branch .LBB20_7
; GFX11-NEXT:  .LBB20_5: ; %frem.else
; GFX11-NEXT:    s_and_b32 s2, 0x80000000, s0
; GFX11-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |s0|, |s1|
; GFX11-NEXT:    v_mov_b32_e32 v0, s2
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_cndmask_b32_e32 v0, s0, v0, vcc_lo
; GFX11-NEXT:    s_branch .LBB20_8
; GFX11-NEXT:  .LBB20_6:
; GFX11-NEXT:    v_mov_b32_e32 v5, v2
; GFX11-NEXT:  .LBB20_7: ; %frem.loop_exit
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_add_nc_u32_e32 v2, -11, v4
; GFX11-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX11-NEXT:    v_rndne_f32_e32 v3, v3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v2, -v3, v1, v2
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX11-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX11-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_bfi_b32 v0, 0x7fffffff, v0, s0
; GFX11-NEXT:  .LBB20_8:
; GFX11-NEXT:    v_cmp_lg_f32_e64 s1, s1, 0
; GFX11-NEXT:    v_cmp_nge_f32_e64 s0, |s0|, 0x7f800000
; GFX11-NEXT:    s_and_b32 vcc_lo, s0, s1
; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-LABEL: frem_f32_uniform:
; GFX1150:       ; %bb.0:
; GFX1150-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-NEXT:    s_and_b32 s2, s0, 0x7fffffff
; GFX1150-NEXT:    s_and_b32 s3, s1, 0x7fffffff
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_cmp_gt_f32 s2, s3
; GFX1150-NEXT:    s_cbranch_scc0 .LBB20_5
; GFX1150-NEXT:  ; %bb.1: ; %frem.compute
; GFX1150-NEXT:    v_frexp_mant_f32_e64 v1, |s1|
; GFX1150-NEXT:    v_frexp_mant_f32_e64 v0, |s0|
; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v3, s0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX1150-NEXT:    v_ldexp_f32 v2, v0, 12
; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v0, s1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1150-NEXT:    v_readfirstlane_b32 s3, v3
; GFX1150-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_readfirstlane_b32 s4, v0
; GFX1150-NEXT:    v_add_nc_u32_e32 v0, -1, v0
; GFX1150-NEXT:    v_rcp_f32_e32 v6, v5
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_not_b32_e32 v4, v0
; GFX1150-NEXT:    v_add_nc_u32_e32 v4, v4, v3
; GFX1150-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX1150-NEXT:    s_denorm_mode 15
; GFX1150-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
; GFX1150-NEXT:    v_fmac_f32_e32 v6, v7, v6
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f32_e32 v7, v3, v6
; GFX1150-NEXT:    v_fma_f32 v8, -v5, v7, v3
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fmac_f32_e32 v7, v8, v6
; GFX1150-NEXT:    v_fma_f32 v3, -v5, v7, v3
; GFX1150-NEXT:    s_denorm_mode 12
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
; GFX1150-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v4
; GFX1150-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX1150-NEXT:    s_cbranch_vccnz .LBB20_6
; GFX1150-NEXT:  ; %bb.2: ; %frem.loop_body.preheader
; GFX1150-NEXT:    s_sub_i32 s3, s3, s4
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_add_i32 s3, s3, 12
; GFX1150-NEXT:  .LBB20_3: ; %frem.loop_body
; GFX1150-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT:    v_mov_b32_e32 v5, v2
; GFX1150-NEXT:    s_add_i32 s3, s3, -12
; GFX1150-NEXT:    s_cmp_gt_i32 s3, 12
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f32_e32 v2, v5, v3
; GFX1150-NEXT:    v_rndne_f32_e32 v2, v2
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_xor_b32_e32 v2, 0x80000000, v2
; GFX1150-NEXT:    v_fma_f32 v2, v2, v1, v5
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1150-NEXT:    v_add_f32_e32 v4, v2, v1
; GFX1150-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f32 v2, v2, 12
; GFX1150-NEXT:    s_cbranch_scc1 .LBB20_3
; GFX1150-NEXT:  ; %bb.4:
; GFX1150-NEXT:    v_mov_b32_e32 v4, s3
; GFX1150-NEXT:    s_branch .LBB20_7
; GFX1150-NEXT:  .LBB20_5: ; %frem.else
; GFX1150-NEXT:    s_and_b32 s4, 0x80000000, s0
; GFX1150-NEXT:    s_cmp_eq_f32 s2, s3
; GFX1150-NEXT:    v_mov_b32_e32 v0, s4
; GFX1150-NEXT:    s_cselect_b32 vcc_lo, -1, 0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_cndmask_b32_e32 v0, s0, v0, vcc_lo
; GFX1150-NEXT:    s_branch .LBB20_8
; GFX1150-NEXT:  .LBB20_6:
; GFX1150-NEXT:    v_mov_b32_e32 v5, v2
; GFX1150-NEXT:  .LBB20_7: ; %frem.loop_exit
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_add_nc_u32_e32 v2, -11, v4
; GFX1150-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX1150-NEXT:    v_rndne_f32_e32 v3, v3
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
; GFX1150-NEXT:    v_fmac_f32_e32 v2, v3, v1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1150-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX1150-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX1150-NEXT:    v_bfi_b32 v0, 0x7fffffff, v0, s0
; GFX1150-NEXT:  .LBB20_8:
; GFX1150-NEXT:    s_cmp_lg_f32 s1, 0
; GFX1150-NEXT:    s_cselect_b32 s0, -1, 0
; GFX1150-NEXT:    s_cmp_nge_f32 s2, 0x7f800000
; GFX1150-NEXT:    s_cselect_b32 s1, -1, 0
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_and_b32 vcc_lo, s1, s0
; GFX1150-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
; GFX1150-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: frem_f32_uniform:
; GFX1200:       ; %bb.0:
; GFX1200-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT:    s_wait_expcnt 0x0
; GFX1200-NEXT:    s_wait_samplecnt 0x0
; GFX1200-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-NEXT:    s_wait_kmcnt 0x0
; GFX1200-NEXT:    s_and_b32 s2, s0, 0x7fffffff
; GFX1200-NEXT:    s_and_b32 s3, s1, 0x7fffffff
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_cmp_gt_f32 s2, s3
; GFX1200-NEXT:    s_cbranch_scc0 .LBB20_5
; GFX1200-NEXT:  ; %bb.1: ; %frem.compute
; GFX1200-NEXT:    v_frexp_mant_f32_e64 v1, |s1|
; GFX1200-NEXT:    v_frexp_mant_f32_e64 v0, |s0|
; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v3, s0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX1200-NEXT:    v_ldexp_f32 v2, v0, 12
; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v0, s1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-NEXT:    v_readfirstlane_b32 s3, v3
; GFX1200-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1200-NEXT:    v_readfirstlane_b32 s4, v0
; GFX1200-NEXT:    v_add_nc_u32_e32 v0, -1, v0
; GFX1200-NEXT:    v_rcp_f32_e32 v6, v5
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_not_b32_e32 v4, v0
; GFX1200-NEXT:    v_add_nc_u32_e32 v4, v4, v3
; GFX1200-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX1200-NEXT:    s_denorm_mode 15
; GFX1200-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
; GFX1200-NEXT:    v_fmac_f32_e32 v6, v7, v6
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_mul_f32_e32 v7, v3, v6
; GFX1200-NEXT:    v_fma_f32 v8, -v5, v7, v3
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fmac_f32_e32 v7, v8, v6
; GFX1200-NEXT:    v_fma_f32 v3, -v5, v7, v3
; GFX1200-NEXT:    s_denorm_mode 12
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
; GFX1200-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v4
; GFX1200-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX1200-NEXT:    s_cbranch_vccnz .LBB20_6
; GFX1200-NEXT:  ; %bb.2: ; %frem.loop_body.preheader
; GFX1200-NEXT:    s_sub_co_i32 s3, s3, s4
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_add_co_i32 s3, s3, 12
; GFX1200-NEXT:  .LBB20_3: ; %frem.loop_body
; GFX1200-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_mov_b32_e32 v5, v2
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_add_co_i32 s3, s3, -12
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_cmp_gt_i32 s3, 12
; GFX1200-NEXT:    v_mul_f32_e32 v2, v5, v3
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_rndne_f32_e32 v2, v2
; GFX1200-NEXT:    v_xor_b32_e32 v2, 0x80000000, v2
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v2, v2, v1, v5
; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1200-NEXT:    v_add_f32_e32 v4, v2, v1
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1200-NEXT:    v_ldexp_f32 v2, v2, 12
; GFX1200-NEXT:    s_cbranch_scc1 .LBB20_3
; GFX1200-NEXT:  ; %bb.4:
; GFX1200-NEXT:    v_mov_b32_e32 v4, s3
; GFX1200-NEXT:    s_branch .LBB20_7
; GFX1200-NEXT:  .LBB20_5: ; %frem.else
; GFX1200-NEXT:    s_and_b32 s4, 0x80000000, s0
; GFX1200-NEXT:    s_cmp_eq_f32 s2, s3
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_cselect_b32 s0, s4, s0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    v_mov_b32_e32 v0, s0
; GFX1200-NEXT:    s_branch .LBB20_8
; GFX1200-NEXT:  .LBB20_6:
; GFX1200-NEXT:    v_mov_b32_e32 v5, v2
; GFX1200-NEXT:  .LBB20_7: ; %frem.loop_exit
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_add_nc_u32_e32 v2, -11, v4
; GFX1200-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX1200-NEXT:    v_rndne_f32_e32 v3, v3
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
; GFX1200-NEXT:    v_fmac_f32_e32 v2, v3, v1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1200-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX1200-NEXT:    v_bfi_b32 v0, 0x7fffffff, v0, s0
; GFX1200-NEXT:  .LBB20_8:
; GFX1200-NEXT:    s_cmp_lg_f32 s1, 0
; GFX1200-NEXT:    s_cselect_b32 s0, -1, 0
; GFX1200-NEXT:    s_cmp_nge_f32 s2, 0x7f800000
; GFX1200-NEXT:    s_cselect_b32 s1, -1, 0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_and_b32 vcc_lo, s1, s0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
; GFX1200-NEXT:    s_setpc_b64 s[30:31]
   %r2 = frem float %in1, %in2
  ret float %r2
}

define float @fast_frem_f32_uniform(float inreg %in1, float inreg %in2) #0 {
; SI-LABEL: fast_frem_f32_uniform:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_mov_b32_e32 v1, s16
; SI-NEXT:    v_div_scale_f32 v2, s[4:5], s17, s17, v1
; SI-NEXT:    v_rcp_f32_e32 v3, v2
; SI-NEXT:    v_mov_b32_e32 v0, s17
; SI-NEXT:    v_div_scale_f32 v0, vcc, s16, v0, s16
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    v_fma_f32 v4, -v2, v3, 1.0
; SI-NEXT:    v_fma_f32 v3, v4, v3, v3
; SI-NEXT:    v_mul_f32_e32 v4, v0, v3
; SI-NEXT:    v_fma_f32 v5, -v2, v4, v0
; SI-NEXT:    v_fma_f32 v4, v5, v3, v4
; SI-NEXT:    v_fma_f32 v0, -v2, v4, v0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    v_div_fmas_f32 v0, v0, v3, v4
; SI-NEXT:    v_div_fixup_f32 v0, v0, s17, v1
; SI-NEXT:    v_trunc_f32_e32 v0, v0
; SI-NEXT:    v_fma_f32 v0, -v0, s17, v1
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; CI-LABEL: fast_frem_f32_uniform:
; CI:       ; %bb.0:
; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-NEXT:    v_mov_b32_e32 v1, s16
; CI-NEXT:    v_div_scale_f32 v2, s[4:5], s17, s17, v1
; CI-NEXT:    v_mov_b32_e32 v0, s17
; CI-NEXT:    v_div_scale_f32 v0, vcc, s16, v0, s16
; CI-NEXT:    v_rcp_f32_e32 v3, v2
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v4, -v2, v3, 1.0
; CI-NEXT:    v_fma_f32 v3, v4, v3, v3
; CI-NEXT:    v_mul_f32_e32 v4, v0, v3
; CI-NEXT:    v_fma_f32 v5, -v2, v4, v0
; CI-NEXT:    v_fma_f32 v4, v5, v3, v4
; CI-NEXT:    v_fma_f32 v0, -v2, v4, v0
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v0, v0, v3, v4
; CI-NEXT:    v_div_fixup_f32 v0, v0, s17, v1
; CI-NEXT:    v_trunc_f32_e32 v0, v0
; CI-NEXT:    v_fma_f32 v0, -v0, s17, v1
; CI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: fast_frem_f32_uniform:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_mov_b32_e32 v1, s16
; VI-NEXT:    v_div_scale_f32 v2, s[4:5], s17, s17, v1
; VI-NEXT:    v_mov_b32_e32 v0, s17
; VI-NEXT:    v_div_scale_f32 v0, vcc, s16, v0, s16
; VI-NEXT:    v_rcp_f32_e32 v3, v2
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT:    v_fma_f32 v4, -v2, v3, 1.0
; VI-NEXT:    v_fma_f32 v3, v4, v3, v3
; VI-NEXT:    v_mul_f32_e32 v4, v0, v3
; VI-NEXT:    v_fma_f32 v5, -v2, v4, v0
; VI-NEXT:    v_fma_f32 v4, v5, v3, v4
; VI-NEXT:    v_fma_f32 v0, -v2, v4, v0
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; VI-NEXT:    v_div_fmas_f32 v0, v0, v3, v4
; VI-NEXT:    v_div_fixup_f32 v0, v0, s17, v1
; VI-NEXT:    v_trunc_f32_e32 v0, v0
; VI-NEXT:    v_fma_f32 v0, -v0, s17, v1
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: fast_frem_f32_uniform:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v1, s16
; GFX9-NEXT:    v_div_scale_f32 v2, s[4:5], s17, s17, v1
; GFX9-NEXT:    v_mov_b32_e32 v0, s17
; GFX9-NEXT:    v_div_scale_f32 v0, vcc, s16, v0, s16
; GFX9-NEXT:    v_rcp_f32_e32 v3, v2
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT:    v_fma_f32 v4, -v2, v3, 1.0
; GFX9-NEXT:    v_fma_f32 v3, v4, v3, v3
; GFX9-NEXT:    v_mul_f32_e32 v4, v0, v3
; GFX9-NEXT:    v_fma_f32 v5, -v2, v4, v0
; GFX9-NEXT:    v_fma_f32 v4, v5, v3, v4
; GFX9-NEXT:    v_fma_f32 v0, -v2, v4, v0
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX9-NEXT:    v_div_fmas_f32 v0, v0, v3, v4
; GFX9-NEXT:    v_div_fixup_f32 v0, v0, s17, v1
; GFX9-NEXT:    v_trunc_f32_e32 v0, v0
; GFX9-NEXT:    v_fma_f32 v0, -v0, s17, v1
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: fast_frem_f32_uniform:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_div_scale_f32 v1, s4, s17, s17, s16
; GFX10-NEXT:    v_div_scale_f32 v0, vcc_lo, s16, s17, s16
; GFX10-NEXT:    v_rcp_f32_e32 v2, v1
; GFX10-NEXT:    s_denorm_mode 15
; GFX10-NEXT:    v_fma_f32 v3, -v1, v2, 1.0
; GFX10-NEXT:    v_fmac_f32_e32 v2, v3, v2
; GFX10-NEXT:    v_mul_f32_e32 v3, v0, v2
; GFX10-NEXT:    v_fma_f32 v4, -v1, v3, v0
; GFX10-NEXT:    v_fmac_f32_e32 v3, v4, v2
; GFX10-NEXT:    v_fma_f32 v0, -v1, v3, v0
; GFX10-NEXT:    s_denorm_mode 12
; GFX10-NEXT:    v_div_fmas_f32 v0, v0, v2, v3
; GFX10-NEXT:    v_div_fixup_f32 v0, v0, s17, s16
; GFX10-NEXT:    v_trunc_f32_e32 v0, v0
; GFX10-NEXT:    v_fma_f32 v0, -v0, s17, s16
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: fast_frem_f32_uniform:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_div_scale_f32 v1, null, s1, s1, s0
; GFX11-NEXT:    v_div_scale_f32 v0, vcc_lo, s0, s1, s0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_rcp_f32_e32 v2, v1
; GFX11-NEXT:    s_denorm_mode 15
; GFX11-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT:    v_fma_f32 v3, -v1, v2, 1.0
; GFX11-NEXT:    v_fmac_f32_e32 v2, v3, v2
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_mul_f32_e32 v3, v0, v2
; GFX11-NEXT:    v_fma_f32 v4, -v1, v3, v0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fmac_f32_e32 v3, v4, v2
; GFX11-NEXT:    v_fma_f32 v0, -v1, v3, v0
; GFX11-NEXT:    s_denorm_mode 12
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_div_fmas_f32 v0, v0, v2, v3
; GFX11-NEXT:    v_div_fixup_f32 v0, v0, s1, s0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_trunc_f32_e32 v0, v0
; GFX11-NEXT:    v_fma_f32 v0, -v0, s1, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-LABEL: fast_frem_f32_uniform:
; GFX1150:       ; %bb.0:
; GFX1150-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-NEXT:    v_div_scale_f32 v1, null, s1, s1, s0
; GFX1150-NEXT:    v_div_scale_f32 v0, vcc_lo, s0, s1, s0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
; GFX1150-NEXT:    v_rcp_f32_e32 v2, v1
; GFX1150-NEXT:    s_denorm_mode 15
; GFX1150-NEXT:    v_fma_f32 v3, -v1, v2, 1.0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fmac_f32_e32 v2, v3, v2
; GFX1150-NEXT:    v_mul_f32_e32 v3, v0, v2
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f32 v4, -v1, v3, v0
; GFX1150-NEXT:    v_fmac_f32_e32 v3, v4, v2
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f32 v0, -v1, v3, v0
; GFX1150-NEXT:    s_denorm_mode 12
; GFX1150-NEXT:    v_div_fmas_f32 v0, v0, v2, v3
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_div_fixup_f32 v0, v0, s1, s0
; GFX1150-NEXT:    v_trunc_f32_e32 v0, v0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0
; GFX1150-NEXT:    v_fma_f32 v0, v0, s1, s0
; GFX1150-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: fast_frem_f32_uniform:
; GFX1200:       ; %bb.0:
; GFX1200-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT:    s_wait_expcnt 0x0
; GFX1200-NEXT:    s_wait_samplecnt 0x0
; GFX1200-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-NEXT:    s_wait_kmcnt 0x0
; GFX1200-NEXT:    v_div_scale_f32 v1, null, s1, s1, s0
; GFX1200-NEXT:    v_div_scale_f32 v0, vcc_lo, s0, s1, s0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
; GFX1200-NEXT:    v_rcp_f32_e32 v2, v1
; GFX1200-NEXT:    s_denorm_mode 15
; GFX1200-NEXT:    v_fma_f32 v3, -v1, v2, 1.0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fmac_f32_e32 v2, v3, v2
; GFX1200-NEXT:    v_mul_f32_e32 v3, v0, v2
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v4, -v1, v3, v0
; GFX1200-NEXT:    v_fmac_f32_e32 v3, v4, v2
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v0, -v1, v3, v0
; GFX1200-NEXT:    s_denorm_mode 12
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_div_fmas_f32 v0, v0, v2, v3
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_div_fixup_f32 v0, v0, s1, s0
; GFX1200-NEXT:    v_trunc_f32_e32 v0, v0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0
; GFX1200-NEXT:    v_fma_f32 v0, v0, s1, s0
; GFX1200-NEXT:    s_setpc_b64 s[30:31]
   %r2 = frem fast float %in1, %in2
  ret float %r2
}

define float @unsafe_frem_f32_uniform(float inreg %in1, float inreg %in2) #0 {
; SI-LABEL: unsafe_frem_f32_uniform:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_mov_b32_e32 v1, s16
; SI-NEXT:    v_div_scale_f32 v2, s[4:5], s17, s17, v1
; SI-NEXT:    v_rcp_f32_e32 v3, v2
; SI-NEXT:    v_mov_b32_e32 v0, s17
; SI-NEXT:    v_div_scale_f32 v0, vcc, s16, v0, s16
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    v_fma_f32 v4, -v2, v3, 1.0
; SI-NEXT:    v_fma_f32 v3, v4, v3, v3
; SI-NEXT:    v_mul_f32_e32 v4, v0, v3
; SI-NEXT:    v_fma_f32 v5, -v2, v4, v0
; SI-NEXT:    v_fma_f32 v4, v5, v3, v4
; SI-NEXT:    v_fma_f32 v0, -v2, v4, v0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    v_div_fmas_f32 v0, v0, v3, v4
; SI-NEXT:    v_div_fixup_f32 v0, v0, s17, v1
; SI-NEXT:    v_trunc_f32_e32 v0, v0
; SI-NEXT:    v_fma_f32 v0, -v0, s17, v1
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; CI-LABEL: unsafe_frem_f32_uniform:
; CI:       ; %bb.0:
; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-NEXT:    v_mov_b32_e32 v1, s16
; CI-NEXT:    v_div_scale_f32 v2, s[4:5], s17, s17, v1
; CI-NEXT:    v_mov_b32_e32 v0, s17
; CI-NEXT:    v_div_scale_f32 v0, vcc, s16, v0, s16
; CI-NEXT:    v_rcp_f32_e32 v3, v2
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v4, -v2, v3, 1.0
; CI-NEXT:    v_fma_f32 v3, v4, v3, v3
; CI-NEXT:    v_mul_f32_e32 v4, v0, v3
; CI-NEXT:    v_fma_f32 v5, -v2, v4, v0
; CI-NEXT:    v_fma_f32 v4, v5, v3, v4
; CI-NEXT:    v_fma_f32 v0, -v2, v4, v0
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v0, v0, v3, v4
; CI-NEXT:    v_div_fixup_f32 v0, v0, s17, v1
; CI-NEXT:    v_trunc_f32_e32 v0, v0
; CI-NEXT:    v_fma_f32 v0, -v0, s17, v1
; CI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: unsafe_frem_f32_uniform:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_mov_b32_e32 v1, s16
; VI-NEXT:    v_div_scale_f32 v2, s[4:5], s17, s17, v1
; VI-NEXT:    v_mov_b32_e32 v0, s17
; VI-NEXT:    v_div_scale_f32 v0, vcc, s16, v0, s16
; VI-NEXT:    v_rcp_f32_e32 v3, v2
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT:    v_fma_f32 v4, -v2, v3, 1.0
; VI-NEXT:    v_fma_f32 v3, v4, v3, v3
; VI-NEXT:    v_mul_f32_e32 v4, v0, v3
; VI-NEXT:    v_fma_f32 v5, -v2, v4, v0
; VI-NEXT:    v_fma_f32 v4, v5, v3, v4
; VI-NEXT:    v_fma_f32 v0, -v2, v4, v0
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; VI-NEXT:    v_div_fmas_f32 v0, v0, v3, v4
; VI-NEXT:    v_div_fixup_f32 v0, v0, s17, v1
; VI-NEXT:    v_trunc_f32_e32 v0, v0
; VI-NEXT:    v_fma_f32 v0, -v0, s17, v1
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: unsafe_frem_f32_uniform:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v1, s16
; GFX9-NEXT:    v_div_scale_f32 v2, s[4:5], s17, s17, v1
; GFX9-NEXT:    v_mov_b32_e32 v0, s17
; GFX9-NEXT:    v_div_scale_f32 v0, vcc, s16, v0, s16
; GFX9-NEXT:    v_rcp_f32_e32 v3, v2
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT:    v_fma_f32 v4, -v2, v3, 1.0
; GFX9-NEXT:    v_fma_f32 v3, v4, v3, v3
; GFX9-NEXT:    v_mul_f32_e32 v4, v0, v3
; GFX9-NEXT:    v_fma_f32 v5, -v2, v4, v0
; GFX9-NEXT:    v_fma_f32 v4, v5, v3, v4
; GFX9-NEXT:    v_fma_f32 v0, -v2, v4, v0
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX9-NEXT:    v_div_fmas_f32 v0, v0, v3, v4
; GFX9-NEXT:    v_div_fixup_f32 v0, v0, s17, v1
; GFX9-NEXT:    v_trunc_f32_e32 v0, v0
; GFX9-NEXT:    v_fma_f32 v0, -v0, s17, v1
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: unsafe_frem_f32_uniform:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_div_scale_f32 v1, s4, s17, s17, s16
; GFX10-NEXT:    v_div_scale_f32 v0, vcc_lo, s16, s17, s16
; GFX10-NEXT:    v_rcp_f32_e32 v2, v1
; GFX10-NEXT:    s_denorm_mode 15
; GFX10-NEXT:    v_fma_f32 v3, -v1, v2, 1.0
; GFX10-NEXT:    v_fmac_f32_e32 v2, v3, v2
; GFX10-NEXT:    v_mul_f32_e32 v3, v0, v2
; GFX10-NEXT:    v_fma_f32 v4, -v1, v3, v0
; GFX10-NEXT:    v_fmac_f32_e32 v3, v4, v2
; GFX10-NEXT:    v_fma_f32 v0, -v1, v3, v0
; GFX10-NEXT:    s_denorm_mode 12
; GFX10-NEXT:    v_div_fmas_f32 v0, v0, v2, v3
; GFX10-NEXT:    v_div_fixup_f32 v0, v0, s17, s16
; GFX10-NEXT:    v_trunc_f32_e32 v0, v0
; GFX10-NEXT:    v_fma_f32 v0, -v0, s17, s16
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: unsafe_frem_f32_uniform:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_div_scale_f32 v1, null, s1, s1, s0
; GFX11-NEXT:    v_div_scale_f32 v0, vcc_lo, s0, s1, s0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_rcp_f32_e32 v2, v1
; GFX11-NEXT:    s_denorm_mode 15
; GFX11-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT:    v_fma_f32 v3, -v1, v2, 1.0
; GFX11-NEXT:    v_fmac_f32_e32 v2, v3, v2
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_mul_f32_e32 v3, v0, v2
; GFX11-NEXT:    v_fma_f32 v4, -v1, v3, v0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fmac_f32_e32 v3, v4, v2
; GFX11-NEXT:    v_fma_f32 v0, -v1, v3, v0
; GFX11-NEXT:    s_denorm_mode 12
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_div_fmas_f32 v0, v0, v2, v3
; GFX11-NEXT:    v_div_fixup_f32 v0, v0, s1, s0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_trunc_f32_e32 v0, v0
; GFX11-NEXT:    v_fma_f32 v0, -v0, s1, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-LABEL: unsafe_frem_f32_uniform:
; GFX1150:       ; %bb.0:
; GFX1150-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-NEXT:    v_div_scale_f32 v1, null, s1, s1, s0
; GFX1150-NEXT:    v_div_scale_f32 v0, vcc_lo, s0, s1, s0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
; GFX1150-NEXT:    v_rcp_f32_e32 v2, v1
; GFX1150-NEXT:    s_denorm_mode 15
; GFX1150-NEXT:    v_fma_f32 v3, -v1, v2, 1.0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fmac_f32_e32 v2, v3, v2
; GFX1150-NEXT:    v_mul_f32_e32 v3, v0, v2
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f32 v4, -v1, v3, v0
; GFX1150-NEXT:    v_fmac_f32_e32 v3, v4, v2
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f32 v0, -v1, v3, v0
; GFX1150-NEXT:    s_denorm_mode 12
; GFX1150-NEXT:    v_div_fmas_f32 v0, v0, v2, v3
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_div_fixup_f32 v0, v0, s1, s0
; GFX1150-NEXT:    v_trunc_f32_e32 v0, v0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0
; GFX1150-NEXT:    v_fma_f32 v0, v0, s1, s0
; GFX1150-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: unsafe_frem_f32_uniform:
; GFX1200:       ; %bb.0:
; GFX1200-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT:    s_wait_expcnt 0x0
; GFX1200-NEXT:    s_wait_samplecnt 0x0
; GFX1200-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-NEXT:    s_wait_kmcnt 0x0
; GFX1200-NEXT:    v_div_scale_f32 v1, null, s1, s1, s0
; GFX1200-NEXT:    v_div_scale_f32 v0, vcc_lo, s0, s1, s0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
; GFX1200-NEXT:    v_rcp_f32_e32 v2, v1
; GFX1200-NEXT:    s_denorm_mode 15
; GFX1200-NEXT:    v_fma_f32 v3, -v1, v2, 1.0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fmac_f32_e32 v2, v3, v2
; GFX1200-NEXT:    v_mul_f32_e32 v3, v0, v2
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v4, -v1, v3, v0
; GFX1200-NEXT:    v_fmac_f32_e32 v3, v4, v2
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v0, -v1, v3, v0
; GFX1200-NEXT:    s_denorm_mode 12
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_div_fmas_f32 v0, v0, v2, v3
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_div_fixup_f32 v0, v0, s1, s0
; GFX1200-NEXT:    v_trunc_f32_e32 v0, v0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0
; GFX1200-NEXT:    v_fma_f32 v0, v0, s1, s0
; GFX1200-NEXT:    s_setpc_b64 s[30:31]
   %r2 = frem afn float %in1, %in2
  ret float %r2
}

define double @frem_f64_uniform(double inreg %in1, double inreg %in2) #0 {
; SI-LABEL: frem_f64_uniform:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_mov_b32_e32 v0, s18
; SI-NEXT:    v_mov_b32_e32 v1, s19
; SI-NEXT:    v_cmp_gt_f64_e64 vcc, |s[16:17]|, |v[0:1]|
; SI-NEXT:    s_cbranch_vccz .LBB23_4
; SI-NEXT:  ; %bb.1: ; %frem.compute
; SI-NEXT:    s_and_b32 s4, s17, 0x7fffffff
; SI-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[16:17]|
; SI-NEXT:    s_cmp_lt_i32 s4, 0x7ff00000
; SI-NEXT:    s_cselect_b64 vcc, -1, 0
; SI-NEXT:    v_mov_b32_e32 v2, s4
; SI-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; SI-NEXT:    v_mov_b32_e32 v2, s16
; SI-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
; SI-NEXT:    v_frexp_exp_i32_f64_e32 v2, s[16:17]
; SI-NEXT:    v_ldexp_f64 v[4:5], v[0:1], 26
; SI-NEXT:    v_readfirstlane_b32 s4, v2
; SI-NEXT:    s_cselect_b32 s7, s4, 0
; SI-NEXT:    s_and_b32 s4, s19, 0x7fffffff
; SI-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[18:19]|
; SI-NEXT:    s_cmp_lt_i32 s4, 0x7ff00000
; SI-NEXT:    s_cselect_b64 vcc, -1, 0
; SI-NEXT:    v_mov_b32_e32 v2, s4
; SI-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; SI-NEXT:    v_mov_b32_e32 v2, s18
; SI-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
; SI-NEXT:    v_frexp_exp_i32_f64_e32 v2, s[18:19]
; SI-NEXT:    v_ldexp_f64 v[0:1], v[0:1], 1
; SI-NEXT:    v_readfirstlane_b32 s4, v2
; SI-NEXT:    s_cselect_b32 s11, s4, 0
; SI-NEXT:    s_add_i32 s9, s11, -1
; SI-NEXT:    s_not_b32 s4, s9
; SI-NEXT:    s_add_i32 s10, s4, s7
; SI-NEXT:    v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], 1.0
; SI-NEXT:    s_brev_b32 s8, -2
; SI-NEXT:    s_mov_b32 s6, -1
; SI-NEXT:    v_rcp_f64_e32 v[6:7], v[2:3]
; SI-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
; SI-NEXT:    v_fma_f64 v[8:9], -v[2:3], v[6:7], 1.0
; SI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; SI-NEXT:    v_fma_f64 v[8:9], -v[2:3], v[6:7], 1.0
; SI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; SI-NEXT:    v_div_scale_f64 v[8:9], s[4:5], 1.0, v[0:1], 1.0
; SI-NEXT:    s_mov_b32 s4, 0x3ff00000
; SI-NEXT:    v_mul_f64 v[10:11], v[8:9], v[6:7]
; SI-NEXT:    v_cmp_eq_u32_e64 s[4:5], s4, v9
; SI-NEXT:    v_fma_f64 v[12:13], -v[2:3], v[10:11], v[8:9]
; SI-NEXT:    s_xor_b64 vcc, s[4:5], vcc
; SI-NEXT:    v_div_fmas_f64 v[2:3], v[12:13], v[6:7], v[10:11]
; SI-NEXT:    s_cmp_lt_i32 s10, 27
; SI-NEXT:    v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0
; SI-NEXT:    s_cbranch_scc1 .LBB23_5
; SI-NEXT:  ; %bb.2: ; %frem.loop_body.preheader
; SI-NEXT:    s_sub_i32 s4, s7, s11
; SI-NEXT:    s_add_i32 s10, s4, 26
; SI-NEXT:    s_mov_b32 s7, 0x432fffff
; SI-NEXT:    v_mov_b32_e32 v10, 0x43300000
; SI-NEXT:    v_mov_b32_e32 v8, 0
; SI-NEXT:  .LBB23_3: ; %frem.loop_body
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v7, v5
; SI-NEXT:    v_mov_b32_e32 v6, v4
; SI-NEXT:    v_mul_f64 v[4:5], v[6:7], v[2:3]
; SI-NEXT:    s_sub_i32 s10, s10, 26
; SI-NEXT:    v_bfi_b32 v9, s8, v10, v5
; SI-NEXT:    v_add_f64 v[11:12], v[4:5], v[8:9]
; SI-NEXT:    v_cmp_gt_f64_e64 vcc, |v[4:5]|, s[6:7]
; SI-NEXT:    v_add_f64 v[11:12], v[11:12], -v[8:9]
; SI-NEXT:    s_cmp_gt_i32 s10, 26
; SI-NEXT:    v_cndmask_b32_e32 v5, v12, v5, vcc
; SI-NEXT:    v_cndmask_b32_e32 v4, v11, v4, vcc
; SI-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[0:1], v[6:7]
; SI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[4:5]
; SI-NEXT:    v_add_f64 v[11:12], v[4:5], v[0:1]
; SI-NEXT:    v_cndmask_b32_e32 v5, v5, v12, vcc
; SI-NEXT:    v_cndmask_b32_e32 v4, v4, v11, vcc
; SI-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; SI-NEXT:    s_cbranch_scc1 .LBB23_3
; SI-NEXT:    s_branch .LBB23_6
; SI-NEXT:  .LBB23_4: ; %frem.else
; SI-NEXT:    v_mov_b32_e32 v0, s18
; SI-NEXT:    v_mov_b32_e32 v1, s19
; SI-NEXT:    v_cmp_eq_f64_e64 s[4:5], |s[16:17]|, |v[0:1]|
; SI-NEXT:    s_and_b32 s6, s17, 0x80000000
; SI-NEXT:    s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT:    s_cselect_b32 s5, s6, s17
; SI-NEXT:    s_cselect_b32 s4, 0, s16
; SI-NEXT:    v_mov_b32_e32 v0, s4
; SI-NEXT:    v_mov_b32_e32 v1, s5
; SI-NEXT:    s_branch .LBB23_7
; SI-NEXT:  .LBB23_5:
; SI-NEXT:    v_mov_b32_e32 v7, v5
; SI-NEXT:    v_mov_b32_e32 v6, v4
; SI-NEXT:  .LBB23_6: ; %frem.loop_exit
; SI-NEXT:    s_sub_i32 s4, s10, 25
; SI-NEXT:    v_ldexp_f64 v[4:5], v[6:7], s4
; SI-NEXT:    v_mov_b32_e32 v6, 0x43300000
; SI-NEXT:    v_mul_f64 v[2:3], v[4:5], v[2:3]
; SI-NEXT:    s_mov_b32 s7, 0x432fffff
; SI-NEXT:    v_bfi_b32 v7, s8, v6, v3
; SI-NEXT:    v_mov_b32_e32 v6, 0
; SI-NEXT:    v_add_f64 v[8:9], v[2:3], v[6:7]
; SI-NEXT:    v_cmp_gt_f64_e64 vcc, |v[2:3]|, s[6:7]
; SI-NEXT:    v_add_f64 v[6:7], v[8:9], -v[6:7]
; SI-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
; SI-NEXT:    v_cndmask_b32_e32 v2, v6, v2, vcc
; SI-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[0:1], v[4:5]
; SI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[2:3]
; SI-NEXT:    v_add_f64 v[0:1], v[2:3], v[0:1]
; SI-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
; SI-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
; SI-NEXT:    v_ldexp_f64 v[0:1], v[0:1], s9
; SI-NEXT:    v_mov_b32_e32 v2, s17
; SI-NEXT:    v_bfi_b32 v1, s8, v1, v2
; SI-NEXT:  .LBB23_7:
; SI-NEXT:    v_mov_b32_e32 v2, 0
; SI-NEXT:    v_mov_b32_e32 v3, 0x7ff00000
; SI-NEXT:    v_cmp_lg_f64_e64 s[4:5], s[18:19], 0
; SI-NEXT:    v_cmp_nge_f64_e64 s[6:7], |s[16:17]|, v[2:3]
; SI-NEXT:    v_mov_b32_e32 v2, 0x7ff80000
; SI-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; SI-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
; SI-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; CI-LABEL: frem_f64_uniform:
; CI:       ; %bb.0:
; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-NEXT:    v_mov_b32_e32 v0, s18
; CI-NEXT:    v_mov_b32_e32 v1, s19
; CI-NEXT:    v_cmp_gt_f64_e64 vcc, |s[16:17]|, |v[0:1]|
; CI-NEXT:    s_cbranch_vccz .LBB23_4
; CI-NEXT:  ; %bb.1: ; %frem.compute
; CI-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[16:17]|
; CI-NEXT:    v_frexp_exp_i32_f64_e32 v7, s[18:19]
; CI-NEXT:    v_frexp_exp_i32_f64_e32 v6, s[16:17]
; CI-NEXT:    v_ldexp_f64 v[4:5], v[0:1], 26
; CI-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[18:19]|
; CI-NEXT:    v_add_i32_e32 v8, vcc, -1, v7
; CI-NEXT:    v_not_b32_e32 v2, v8
; CI-NEXT:    v_add_i32_e32 v9, vcc, v2, v6
; CI-NEXT:    v_ldexp_f64 v[0:1], v[0:1], 1
; CI-NEXT:    v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], 1.0
; CI-NEXT:    v_rcp_f64_e32 v[10:11], v[2:3]
; CI-NEXT:    v_fma_f64 v[12:13], -v[2:3], v[10:11], 1.0
; CI-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
; CI-NEXT:    v_fma_f64 v[12:13], -v[2:3], v[10:11], 1.0
; CI-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
; CI-NEXT:    v_div_scale_f64 v[12:13], vcc, 1.0, v[0:1], 1.0
; CI-NEXT:    v_mul_f64 v[14:15], v[12:13], v[10:11]
; CI-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[14:15], v[12:13]
; CI-NEXT:    s_nop 1
; CI-NEXT:    v_div_fmas_f64 v[2:3], v[2:3], v[10:11], v[14:15]
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v9
; CI-NEXT:    v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0
; CI-NEXT:    s_cbranch_vccnz .LBB23_5
; CI-NEXT:  ; %bb.2: ; %frem.loop_body.preheader
; CI-NEXT:    v_sub_i32_e32 v6, vcc, v6, v7
; CI-NEXT:    v_add_i32_e32 v9, vcc, 26, v6
; CI-NEXT:  .LBB23_3: ; %frem.loop_body
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v7, v5
; CI-NEXT:    v_mov_b32_e32 v6, v4
; CI-NEXT:    v_mul_f64 v[4:5], v[6:7], v[2:3]
; CI-NEXT:    v_rndne_f64_e32 v[4:5], v[4:5]
; CI-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[0:1], v[6:7]
; CI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[4:5]
; CI-NEXT:    v_add_f64 v[10:11], v[4:5], v[0:1]
; CI-NEXT:    v_cndmask_b32_e32 v5, v5, v11, vcc
; CI-NEXT:    v_cndmask_b32_e32 v4, v4, v10, vcc
; CI-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; CI-NEXT:    v_subrev_i32_e32 v9, vcc, 26, v9
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v9
; CI-NEXT:    s_cbranch_vccnz .LBB23_3
; CI-NEXT:    s_branch .LBB23_6
; CI-NEXT:  .LBB23_4: ; %frem.else
; CI-NEXT:    v_mov_b32_e32 v0, s18
; CI-NEXT:    v_mov_b32_e32 v1, s19
; CI-NEXT:    v_cmp_eq_f64_e64 s[4:5], |s[16:17]|, |v[0:1]|
; CI-NEXT:    s_and_b32 s6, s17, 0x80000000
; CI-NEXT:    s_and_b64 s[4:5], s[4:5], exec
; CI-NEXT:    s_cselect_b32 s5, s6, s17
; CI-NEXT:    s_cselect_b32 s4, 0, s16
; CI-NEXT:    v_mov_b32_e32 v0, s4
; CI-NEXT:    v_mov_b32_e32 v1, s5
; CI-NEXT:    s_branch .LBB23_7
; CI-NEXT:  .LBB23_5:
; CI-NEXT:    v_mov_b32_e32 v7, v5
; CI-NEXT:    v_mov_b32_e32 v6, v4
; CI-NEXT:  .LBB23_6: ; %frem.loop_exit
; CI-NEXT:    v_subrev_i32_e32 v4, vcc, 25, v9
; CI-NEXT:    v_ldexp_f64 v[4:5], v[6:7], v4
; CI-NEXT:    s_brev_b32 s4, -2
; CI-NEXT:    v_mul_f64 v[2:3], v[4:5], v[2:3]
; CI-NEXT:    v_rndne_f64_e32 v[2:3], v[2:3]
; CI-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[0:1], v[4:5]
; CI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[2:3]
; CI-NEXT:    v_add_f64 v[0:1], v[2:3], v[0:1]
; CI-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
; CI-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
; CI-NEXT:    v_ldexp_f64 v[0:1], v[0:1], v8
; CI-NEXT:    v_mov_b32_e32 v2, s17
; CI-NEXT:    v_bfi_b32 v1, s4, v1, v2
; CI-NEXT:  .LBB23_7:
; CI-NEXT:    v_mov_b32_e32 v2, 0
; CI-NEXT:    v_mov_b32_e32 v3, 0x7ff00000
; CI-NEXT:    v_cmp_lg_f64_e64 s[4:5], s[18:19], 0
; CI-NEXT:    v_cmp_nge_f64_e64 s[6:7], |s[16:17]|, v[2:3]
; CI-NEXT:    v_mov_b32_e32 v2, 0x7ff80000
; CI-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; CI-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
; CI-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; CI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: frem_f64_uniform:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_mov_b32_e32 v0, s18
; VI-NEXT:    v_mov_b32_e32 v1, s19
; VI-NEXT:    v_cmp_gt_f64_e64 vcc, |s[16:17]|, |v[0:1]|
; VI-NEXT:    s_cbranch_vccz .LBB23_4
; VI-NEXT:  ; %bb.1: ; %frem.compute
; VI-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[16:17]|
; VI-NEXT:    v_frexp_exp_i32_f64_e32 v7, s[18:19]
; VI-NEXT:    v_frexp_exp_i32_f64_e32 v6, s[16:17]
; VI-NEXT:    v_ldexp_f64 v[4:5], v[0:1], 26
; VI-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[18:19]|
; VI-NEXT:    v_add_u32_e32 v8, vcc, -1, v7
; VI-NEXT:    v_not_b32_e32 v2, v8
; VI-NEXT:    v_add_u32_e32 v9, vcc, v2, v6
; VI-NEXT:    v_ldexp_f64 v[0:1], v[0:1], 1
; VI-NEXT:    v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], 1.0
; VI-NEXT:    v_rcp_f64_e32 v[10:11], v[2:3]
; VI-NEXT:    v_fma_f64 v[12:13], -v[2:3], v[10:11], 1.0
; VI-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
; VI-NEXT:    v_fma_f64 v[12:13], -v[2:3], v[10:11], 1.0
; VI-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
; VI-NEXT:    v_div_scale_f64 v[12:13], vcc, 1.0, v[0:1], 1.0
; VI-NEXT:    v_mul_f64 v[14:15], v[12:13], v[10:11]
; VI-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[14:15], v[12:13]
; VI-NEXT:    s_nop 1
; VI-NEXT:    v_div_fmas_f64 v[2:3], v[2:3], v[10:11], v[14:15]
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v9
; VI-NEXT:    v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0
; VI-NEXT:    s_cbranch_vccnz .LBB23_5
; VI-NEXT:  ; %bb.2: ; %frem.loop_body.preheader
; VI-NEXT:    v_sub_u32_e32 v6, vcc, v6, v7
; VI-NEXT:    v_add_u32_e32 v9, vcc, 26, v6
; VI-NEXT:  .LBB23_3: ; %frem.loop_body
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v7, v5
; VI-NEXT:    v_mov_b32_e32 v6, v4
; VI-NEXT:    v_mul_f64 v[4:5], v[6:7], v[2:3]
; VI-NEXT:    v_rndne_f64_e32 v[4:5], v[4:5]
; VI-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[0:1], v[6:7]
; VI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[4:5]
; VI-NEXT:    v_add_f64 v[10:11], v[4:5], v[0:1]
; VI-NEXT:    v_cndmask_b32_e32 v5, v5, v11, vcc
; VI-NEXT:    v_cndmask_b32_e32 v4, v4, v10, vcc
; VI-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; VI-NEXT:    v_subrev_u32_e32 v9, vcc, 26, v9
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v9
; VI-NEXT:    s_cbranch_vccnz .LBB23_3
; VI-NEXT:    s_branch .LBB23_6
; VI-NEXT:  .LBB23_4: ; %frem.else
; VI-NEXT:    v_mov_b32_e32 v0, s18
; VI-NEXT:    v_mov_b32_e32 v1, s19
; VI-NEXT:    v_cmp_eq_f64_e64 s[4:5], |s[16:17]|, |v[0:1]|
; VI-NEXT:    s_and_b32 s6, s17, 0x80000000
; VI-NEXT:    s_cmp_lg_u64 s[4:5], 0
; VI-NEXT:    s_cselect_b32 s5, s6, s17
; VI-NEXT:    s_cselect_b32 s4, 0, s16
; VI-NEXT:    v_mov_b32_e32 v0, s4
; VI-NEXT:    v_mov_b32_e32 v1, s5
; VI-NEXT:    s_branch .LBB23_7
; VI-NEXT:  .LBB23_5:
; VI-NEXT:    v_mov_b32_e32 v7, v5
; VI-NEXT:    v_mov_b32_e32 v6, v4
; VI-NEXT:  .LBB23_6: ; %frem.loop_exit
; VI-NEXT:    v_subrev_u32_e32 v4, vcc, 25, v9
; VI-NEXT:    v_ldexp_f64 v[4:5], v[6:7], v4
; VI-NEXT:    s_brev_b32 s4, -2
; VI-NEXT:    v_mul_f64 v[2:3], v[4:5], v[2:3]
; VI-NEXT:    v_rndne_f64_e32 v[2:3], v[2:3]
; VI-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[0:1], v[4:5]
; VI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[2:3]
; VI-NEXT:    v_add_f64 v[0:1], v[2:3], v[0:1]
; VI-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-NEXT:    v_ldexp_f64 v[0:1], v[0:1], v8
; VI-NEXT:    v_mov_b32_e32 v2, s17
; VI-NEXT:    v_bfi_b32 v1, s4, v1, v2
; VI-NEXT:  .LBB23_7:
; VI-NEXT:    v_mov_b32_e32 v2, 0
; VI-NEXT:    v_mov_b32_e32 v3, 0x7ff00000
; VI-NEXT:    v_cmp_lg_f64_e64 s[4:5], s[18:19], 0
; VI-NEXT:    v_cmp_nge_f64_e64 s[6:7], |s[16:17]|, v[2:3]
; VI-NEXT:    v_mov_b32_e32 v2, 0x7ff80000
; VI-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; VI-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
; VI-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: frem_f64_uniform:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v0, s18
; GFX9-NEXT:    v_mov_b32_e32 v1, s19
; GFX9-NEXT:    v_cmp_gt_f64_e64 vcc, |s[16:17]|, |v[0:1]|
; GFX9-NEXT:    s_cbranch_vccz .LBB23_4
; GFX9-NEXT:  ; %bb.1: ; %frem.compute
; GFX9-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[16:17]|
; GFX9-NEXT:    v_frexp_exp_i32_f64_e32 v7, s[18:19]
; GFX9-NEXT:    v_frexp_exp_i32_f64_e32 v6, s[16:17]
; GFX9-NEXT:    v_ldexp_f64 v[4:5], v[0:1], 26
; GFX9-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[18:19]|
; GFX9-NEXT:    v_add_u32_e32 v8, -1, v7
; GFX9-NEXT:    v_not_b32_e32 v2, v8
; GFX9-NEXT:    v_add_u32_e32 v9, v2, v6
; GFX9-NEXT:    v_ldexp_f64 v[0:1], v[0:1], 1
; GFX9-NEXT:    v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], 1.0
; GFX9-NEXT:    v_rcp_f64_e32 v[10:11], v[2:3]
; GFX9-NEXT:    v_fma_f64 v[12:13], -v[2:3], v[10:11], 1.0
; GFX9-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
; GFX9-NEXT:    v_fma_f64 v[12:13], -v[2:3], v[10:11], 1.0
; GFX9-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
; GFX9-NEXT:    v_div_scale_f64 v[12:13], vcc, 1.0, v[0:1], 1.0
; GFX9-NEXT:    v_mul_f64 v[14:15], v[12:13], v[10:11]
; GFX9-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[14:15], v[12:13]
; GFX9-NEXT:    s_nop 1
; GFX9-NEXT:    v_div_fmas_f64 v[2:3], v[2:3], v[10:11], v[14:15]
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v9
; GFX9-NEXT:    v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0
; GFX9-NEXT:    s_cbranch_vccnz .LBB23_5
; GFX9-NEXT:  ; %bb.2: ; %frem.loop_body.preheader
; GFX9-NEXT:    v_sub_u32_e32 v6, v6, v7
; GFX9-NEXT:    v_add_u32_e32 v9, 26, v6
; GFX9-NEXT:  .LBB23_3: ; %frem.loop_body
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v7, v5
; GFX9-NEXT:    v_mov_b32_e32 v6, v4
; GFX9-NEXT:    v_mul_f64 v[4:5], v[6:7], v[2:3]
; GFX9-NEXT:    v_subrev_u32_e32 v9, 26, v9
; GFX9-NEXT:    v_rndne_f64_e32 v[4:5], v[4:5]
; GFX9-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[0:1], v[6:7]
; GFX9-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[4:5]
; GFX9-NEXT:    v_add_f64 v[10:11], v[4:5], v[0:1]
; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v11, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v10, vcc
; GFX9-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v9
; GFX9-NEXT:    s_cbranch_vccnz .LBB23_3
; GFX9-NEXT:    s_branch .LBB23_6
; GFX9-NEXT:  .LBB23_4: ; %frem.else
; GFX9-NEXT:    v_mov_b32_e32 v0, s18
; GFX9-NEXT:    v_mov_b32_e32 v1, s19
; GFX9-NEXT:    v_cmp_eq_f64_e64 s[4:5], |s[16:17]|, |v[0:1]|
; GFX9-NEXT:    s_and_b32 s6, s17, 0x80000000
; GFX9-NEXT:    s_cmp_lg_u64 s[4:5], 0
; GFX9-NEXT:    s_cselect_b32 s5, s6, s17
; GFX9-NEXT:    s_cselect_b32 s4, 0, s16
; GFX9-NEXT:    v_mov_b32_e32 v0, s4
; GFX9-NEXT:    v_mov_b32_e32 v1, s5
; GFX9-NEXT:    s_branch .LBB23_7
; GFX9-NEXT:  .LBB23_5:
; GFX9-NEXT:    v_mov_b32_e32 v7, v5
; GFX9-NEXT:    v_mov_b32_e32 v6, v4
; GFX9-NEXT:  .LBB23_6: ; %frem.loop_exit
; GFX9-NEXT:    v_subrev_u32_e32 v4, 25, v9
; GFX9-NEXT:    v_ldexp_f64 v[4:5], v[6:7], v4
; GFX9-NEXT:    s_brev_b32 s4, -2
; GFX9-NEXT:    v_mul_f64 v[2:3], v[4:5], v[2:3]
; GFX9-NEXT:    v_rndne_f64_e32 v[2:3], v[2:3]
; GFX9-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[0:1], v[4:5]
; GFX9-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[2:3]
; GFX9-NEXT:    v_add_f64 v[0:1], v[2:3], v[0:1]
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX9-NEXT:    v_ldexp_f64 v[0:1], v[0:1], v8
; GFX9-NEXT:    v_mov_b32_e32 v2, s17
; GFX9-NEXT:    v_bfi_b32 v1, s4, v1, v2
; GFX9-NEXT:  .LBB23_7:
; GFX9-NEXT:    v_mov_b32_e32 v2, 0
; GFX9-NEXT:    v_mov_b32_e32 v3, 0x7ff00000
; GFX9-NEXT:    v_cmp_lg_f64_e64 s[4:5], s[18:19], 0
; GFX9-NEXT:    v_cmp_nge_f64_e64 s[6:7], |s[16:17]|, v[2:3]
; GFX9-NEXT:    v_mov_b32_e32 v2, 0x7ff80000
; GFX9-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; GFX9-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: frem_f64_uniform:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cmp_gt_f64_e64 vcc_lo, |s[16:17]|, |s[18:19]|
; GFX10-NEXT:    s_cbranch_vccz .LBB23_5
; GFX10-NEXT:  ; %bb.1: ; %frem.compute
; GFX10-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[16:17]|
; GFX10-NEXT:    v_frexp_exp_i32_f64_e32 v3, s[18:19]
; GFX10-NEXT:    v_frexp_exp_i32_f64_e32 v2, s[16:17]
; GFX10-NEXT:    v_ldexp_f64 v[4:5], v[0:1], 26
; GFX10-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[18:19]|
; GFX10-NEXT:    v_add_nc_u32_e32 v8, -1, v3
; GFX10-NEXT:    v_readfirstlane_b32 s5, v3
; GFX10-NEXT:    v_readfirstlane_b32 s4, v2
; GFX10-NEXT:    v_not_b32_e32 v3, v8
; GFX10-NEXT:    v_add_nc_u32_e32 v9, v3, v2
; GFX10-NEXT:    v_ldexp_f64 v[0:1], v[0:1], 1
; GFX10-NEXT:    v_div_scale_f64 v[2:3], s6, v[0:1], v[0:1], 1.0
; GFX10-NEXT:    v_rcp_f64_e32 v[6:7], v[2:3]
; GFX10-NEXT:    v_fma_f64 v[10:11], -v[2:3], v[6:7], 1.0
; GFX10-NEXT:    v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
; GFX10-NEXT:    v_fma_f64 v[10:11], -v[2:3], v[6:7], 1.0
; GFX10-NEXT:    v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
; GFX10-NEXT:    v_div_scale_f64 v[10:11], vcc_lo, 1.0, v[0:1], 1.0
; GFX10-NEXT:    v_mul_f64 v[12:13], v[10:11], v[6:7]
; GFX10-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[12:13], v[10:11]
; GFX10-NEXT:    v_div_fmas_f64 v[2:3], v[2:3], v[6:7], v[12:13]
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v9
; GFX10-NEXT:    v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0
; GFX10-NEXT:    s_cbranch_vccnz .LBB23_6
; GFX10-NEXT:  ; %bb.2: ; %frem.loop_body.preheader
; GFX10-NEXT:    s_sub_i32 s4, s4, s5
; GFX10-NEXT:    s_add_i32 s4, s4, 26
; GFX10-NEXT:  .LBB23_3: ; %frem.loop_body
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v7, v5
; GFX10-NEXT:    v_mov_b32_e32 v6, v4
; GFX10-NEXT:    s_sub_i32 s4, s4, 26
; GFX10-NEXT:    s_cmp_gt_i32 s4, 26
; GFX10-NEXT:    v_mul_f64 v[4:5], v[6:7], v[2:3]
; GFX10-NEXT:    v_rndne_f64_e32 v[4:5], v[4:5]
; GFX10-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[0:1], v[6:7]
; GFX10-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
; GFX10-NEXT:    v_add_f64 v[9:10], v[4:5], v[0:1]
; GFX10-NEXT:    v_cndmask_b32_e32 v5, v5, v10, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v4, v4, v9, vcc_lo
; GFX10-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; GFX10-NEXT:    s_cbranch_scc1 .LBB23_3
; GFX10-NEXT:  ; %bb.4:
; GFX10-NEXT:    v_mov_b32_e32 v9, s4
; GFX10-NEXT:    s_branch .LBB23_7
; GFX10-NEXT:  .LBB23_5: ; %frem.else
; GFX10-NEXT:    v_cmp_eq_f64_e64 s5, |s[16:17]|, |s[18:19]|
; GFX10-NEXT:    s_and_b32 s4, s17, 0x80000000
; GFX10-NEXT:    s_cmp_lg_u32 s5, 0
; GFX10-NEXT:    s_cselect_b32 s5, s4, s17
; GFX10-NEXT:    s_cselect_b32 s4, 0, s16
; GFX10-NEXT:    v_mov_b32_e32 v1, s5
; GFX10-NEXT:    v_mov_b32_e32 v0, s4
; GFX10-NEXT:    s_branch .LBB23_8
; GFX10-NEXT:  .LBB23_6:
; GFX10-NEXT:    v_mov_b32_e32 v7, v5
; GFX10-NEXT:    v_mov_b32_e32 v6, v4
; GFX10-NEXT:  .LBB23_7: ; %frem.loop_exit
; GFX10-NEXT:    v_subrev_nc_u32_e32 v4, 25, v9
; GFX10-NEXT:    v_ldexp_f64 v[4:5], v[6:7], v4
; GFX10-NEXT:    v_mul_f64 v[2:3], v[4:5], v[2:3]
; GFX10-NEXT:    v_rndne_f64_e32 v[2:3], v[2:3]
; GFX10-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[0:1], v[4:5]
; GFX10-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[2:3]
; GFX10-NEXT:    v_add_f64 v[0:1], v[2:3], v[0:1]
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-NEXT:    v_ldexp_f64 v[0:1], v[0:1], v8
; GFX10-NEXT:    v_bfi_b32 v1, 0x7fffffff, v1, s17
; GFX10-NEXT:  .LBB23_8:
; GFX10-NEXT:    v_cmp_lg_f64_e64 s4, s[18:19], 0
; GFX10-NEXT:    v_cmp_nge_f64_e64 s5, |s[16:17]|, 0x7ff00000
; GFX10-NEXT:    s_and_b32 vcc_lo, s5, s4
; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v1, 0x7ff80000, v1, vcc_lo
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: frem_f64_uniform:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cmp_gt_f64_e64 vcc_lo, |s[0:1]|, |s[2:3]|
; GFX11-NEXT:    s_cbranch_vccz .LBB23_5
; GFX11-NEXT:  ; %bb.1: ; %frem.compute
; GFX11-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[0:1]|
; GFX11-NEXT:    v_frexp_exp_i32_f64_e32 v3, s[2:3]
; GFX11-NEXT:    v_frexp_exp_i32_f64_e32 v2, s[0:1]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_ldexp_f64 v[4:5], v[0:1], 26
; GFX11-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[2:3]|
; GFX11-NEXT:    v_add_nc_u32_e32 v8, -1, v3
; GFX11-NEXT:    v_readfirstlane_b32 s5, v3
; GFX11-NEXT:    v_readfirstlane_b32 s4, v2
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_not_b32_e32 v3, v8
; GFX11-NEXT:    v_add_nc_u32_e32 v9, v3, v2
; GFX11-NEXT:    v_ldexp_f64 v[0:1], v[0:1], 1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_div_scale_f64 v[2:3], null, v[0:1], v[0:1], 1.0
; GFX11-NEXT:    v_rcp_f64_e32 v[6:7], v[2:3]
; GFX11-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT:    v_fma_f64 v[10:11], -v[2:3], v[6:7], 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
; GFX11-NEXT:    v_fma_f64 v[10:11], -v[2:3], v[6:7], 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
; GFX11-NEXT:    v_div_scale_f64 v[10:11], vcc_lo, 1.0, v[0:1], 1.0
; GFX11-NEXT:    v_mul_f64 v[12:13], v[10:11], v[6:7]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[12:13], v[10:11]
; GFX11-NEXT:    v_div_fmas_f64 v[2:3], v[2:3], v[6:7], v[12:13]
; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v9
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT:    v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0
; GFX11-NEXT:    s_cbranch_vccnz .LBB23_6
; GFX11-NEXT:  ; %bb.2: ; %frem.loop_body.preheader
; GFX11-NEXT:    s_sub_i32 s4, s4, s5
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_add_i32 s4, s4, 26
; GFX11-NEXT:    .p2align 6
; GFX11-NEXT:  .LBB23_3: ; %frem.loop_body
; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT:    v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX11-NEXT:    s_sub_i32 s4, s4, 26
; GFX11-NEXT:    s_cmp_gt_i32 s4, 26
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_mul_f64 v[4:5], v[6:7], v[2:3]
; GFX11-NEXT:    v_rndne_f64_e32 v[4:5], v[4:5]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[0:1], v[6:7]
; GFX11-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
; GFX11-NEXT:    v_add_f64 v[9:10], v[4:5], v[0:1]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_dual_cndmask_b32 v5, v5, v10 :: v_dual_cndmask_b32 v4, v4, v9
; GFX11-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; GFX11-NEXT:    s_cbranch_scc1 .LBB23_3
; GFX11-NEXT:  ; %bb.4:
; GFX11-NEXT:    v_mov_b32_e32 v9, s4
; GFX11-NEXT:    s_branch .LBB23_7
; GFX11-NEXT:  .LBB23_5: ; %frem.else
; GFX11-NEXT:    v_cmp_eq_f64_e64 s5, |s[0:1]|, |s[2:3]|
; GFX11-NEXT:    s_and_b32 s4, s1, 0x80000000
; GFX11-NEXT:    s_cmp_lg_u32 s5, 0
; GFX11-NEXT:    s_cselect_b32 s5, s4, s1
; GFX11-NEXT:    s_cselect_b32 s4, 0, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v0, s4
; GFX11-NEXT:    s_branch .LBB23_8
; GFX11-NEXT:  .LBB23_6:
; GFX11-NEXT:    v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX11-NEXT:  .LBB23_7: ; %frem.loop_exit
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_subrev_nc_u32_e32 v4, 25, v9
; GFX11-NEXT:    v_ldexp_f64 v[4:5], v[6:7], v4
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_mul_f64 v[2:3], v[4:5], v[2:3]
; GFX11-NEXT:    v_rndne_f64_e32 v[2:3], v[2:3]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[0:1], v[4:5]
; GFX11-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[2:3]
; GFX11-NEXT:    v_add_f64 v[0:1], v[2:3], v[0:1]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_dual_cndmask_b32 v1, v3, v1 :: v_dual_cndmask_b32 v0, v2, v0
; GFX11-NEXT:    v_ldexp_f64 v[0:1], v[0:1], v8
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_bfi_b32 v1, 0x7fffffff, v1, s1
; GFX11-NEXT:  .LBB23_8:
; GFX11-NEXT:    v_cmp_lg_f64_e64 s2, s[2:3], 0
; GFX11-NEXT:    v_cmp_nge_f64_e64 s0, |s[0:1]|, 0x7ff00000
; GFX11-NEXT:    s_and_b32 vcc_lo, s0, s2
; GFX11-NEXT:    v_dual_cndmask_b32 v0, 0, v0 :: v_dual_cndmask_b32 v1, 0x7ff80000, v1
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-LABEL: frem_f64_uniform:
; GFX1150:       ; %bb.0:
; GFX1150-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-NEXT:    v_cmp_gt_f64_e64 vcc_lo, |s[0:1]|, |s[2:3]|
; GFX1150-NEXT:    s_cbranch_vccz .LBB23_5
; GFX1150-NEXT:  ; %bb.1: ; %frem.compute
; GFX1150-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[0:1]|
; GFX1150-NEXT:    v_frexp_exp_i32_f64_e32 v3, s[2:3]
; GFX1150-NEXT:    v_frexp_exp_i32_f64_e32 v2, s[0:1]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1150-NEXT:    v_ldexp_f64 v[4:5], v[0:1], 26
; GFX1150-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[2:3]|
; GFX1150-NEXT:    v_add_nc_u32_e32 v8, -1, v3
; GFX1150-NEXT:    v_readfirstlane_b32 s5, v3
; GFX1150-NEXT:    v_readfirstlane_b32 s4, v2
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_not_b32_e32 v3, v8
; GFX1150-NEXT:    v_add_nc_u32_e32 v9, v3, v2
; GFX1150-NEXT:    v_ldexp_f64 v[0:1], v[0:1], 1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_div_scale_f64 v[2:3], null, v[0:1], v[0:1], 1.0
; GFX1150-NEXT:    v_rcp_f64_e32 v[6:7], v[2:3]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[10:11], -v[2:3], v[6:7], 1.0
; GFX1150-NEXT:    v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[10:11], -v[2:3], v[6:7], 1.0
; GFX1150-NEXT:    v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
; GFX1150-NEXT:    v_div_scale_f64 v[10:11], vcc_lo, 1.0, v[0:1], 1.0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f64 v[12:13], v[10:11], v[6:7]
; GFX1150-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[12:13], v[10:11]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-NEXT:    v_div_fmas_f64 v[2:3], v[2:3], v[6:7], v[12:13]
; GFX1150-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v9
; GFX1150-NEXT:    v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0
; GFX1150-NEXT:    s_cbranch_vccnz .LBB23_6
; GFX1150-NEXT:  ; %bb.2: ; %frem.loop_body.preheader
; GFX1150-NEXT:    s_sub_i32 s4, s4, s5
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_add_i32 s4, s4, 26
; GFX1150-NEXT:    .p2align 6
; GFX1150-NEXT:  .LBB23_3: ; %frem.loop_body
; GFX1150-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT:    v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX1150-NEXT:    s_sub_i32 s4, s4, 26
; GFX1150-NEXT:    s_cmp_gt_i32 s4, 26
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f64 v[4:5], v[6:7], v[2:3]
; GFX1150-NEXT:    v_rndne_f64_e32 v[4:5], v[4:5]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[0:1], v[6:7]
; GFX1150-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
; GFX1150-NEXT:    v_add_f64 v[9:10], v[4:5], v[0:1]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_dual_cndmask_b32 v5, v5, v10 :: v_dual_cndmask_b32 v4, v4, v9
; GFX1150-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; GFX1150-NEXT:    s_cbranch_scc1 .LBB23_3
; GFX1150-NEXT:  ; %bb.4:
; GFX1150-NEXT:    v_mov_b32_e32 v9, s4
; GFX1150-NEXT:    s_branch .LBB23_7
; GFX1150-NEXT:  .LBB23_5: ; %frem.else
; GFX1150-NEXT:    v_cmp_eq_f64_e64 s5, |s[0:1]|, |s[2:3]|
; GFX1150-NEXT:    s_and_b32 s4, s1, 0x80000000
; GFX1150-NEXT:    s_cmp_lg_u32 s5, 0
; GFX1150-NEXT:    s_cselect_b32 s5, s4, s1
; GFX1150-NEXT:    s_cselect_b32 s4, 0, s0
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v0, s4
; GFX1150-NEXT:    s_branch .LBB23_8
; GFX1150-NEXT:  .LBB23_6:
; GFX1150-NEXT:    v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX1150-NEXT:  .LBB23_7: ; %frem.loop_exit
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_subrev_nc_u32_e32 v4, 25, v9
; GFX1150-NEXT:    v_ldexp_f64 v[4:5], v[6:7], v4
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f64 v[2:3], v[4:5], v[2:3]
; GFX1150-NEXT:    v_rndne_f64_e32 v[2:3], v[2:3]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[0:1], v[4:5]
; GFX1150-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[2:3]
; GFX1150-NEXT:    v_add_f64 v[0:1], v[2:3], v[0:1]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_dual_cndmask_b32 v1, v3, v1 :: v_dual_cndmask_b32 v0, v2, v0
; GFX1150-NEXT:    v_ldexp_f64 v[0:1], v[0:1], v8
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_bfi_b32 v1, 0x7fffffff, v1, s1
; GFX1150-NEXT:  .LBB23_8:
; GFX1150-NEXT:    v_cmp_lg_f64_e64 s2, s[2:3], 0
; GFX1150-NEXT:    v_cmp_nge_f64_e64 s0, |s[0:1]|, 0x7ff00000
; GFX1150-NEXT:    s_and_b32 vcc_lo, s0, s2
; GFX1150-NEXT:    v_dual_cndmask_b32 v0, 0, v0 :: v_dual_cndmask_b32 v1, 0x7ff80000, v1
; GFX1150-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: frem_f64_uniform:
; GFX1200:       ; %bb.0:
; GFX1200-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT:    s_wait_expcnt 0x0
; GFX1200-NEXT:    s_wait_samplecnt 0x0
; GFX1200-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-NEXT:    s_wait_kmcnt 0x0
; GFX1200-NEXT:    v_cmp_gt_f64_e64 vcc_lo, |s[0:1]|, |s[2:3]|
; GFX1200-NEXT:    s_cbranch_vccz .LBB23_5
; GFX1200-NEXT:  ; %bb.1: ; %frem.compute
; GFX1200-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[0:1]|
; GFX1200-NEXT:    v_frexp_exp_i32_f64_e32 v3, s[2:3]
; GFX1200-NEXT:    v_frexp_exp_i32_f64_e32 v2, s[0:1]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1200-NEXT:    v_ldexp_f64 v[4:5], v[0:1], 26
; GFX1200-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[2:3]|
; GFX1200-NEXT:    v_add_nc_u32_e32 v8, -1, v3
; GFX1200-NEXT:    v_readfirstlane_b32 s5, v3
; GFX1200-NEXT:    v_readfirstlane_b32 s4, v2
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_not_b32_e32 v3, v8
; GFX1200-NEXT:    v_add_nc_u32_e32 v9, v3, v2
; GFX1200-NEXT:    v_ldexp_f64 v[0:1], v[0:1], 1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_div_scale_f64 v[2:3], null, v[0:1], v[0:1], 1.0
; GFX1200-NEXT:    v_rcp_f64_e32 v[6:7], v[2:3]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f64 v[10:11], -v[2:3], v[6:7], 1.0
; GFX1200-NEXT:    v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f64 v[10:11], -v[2:3], v[6:7], 1.0
; GFX1200-NEXT:    v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
; GFX1200-NEXT:    v_div_scale_f64 v[10:11], vcc_lo, 1.0, v[0:1], 1.0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_mul_f64_e32 v[12:13], v[10:11], v[6:7]
; GFX1200-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[12:13], v[10:11]
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT:    v_div_fmas_f64 v[2:3], v[2:3], v[6:7], v[12:13]
; GFX1200-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v9
; GFX1200-NEXT:    v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0
; GFX1200-NEXT:    s_cbranch_vccnz .LBB23_6
; GFX1200-NEXT:  ; %bb.2: ; %frem.loop_body.preheader
; GFX1200-NEXT:    s_sub_co_i32 s4, s4, s5
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_add_co_i32 s4, s4, 26
; GFX1200-NEXT:  .LBB23_3: ; %frem.loop_body
; GFX1200-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX1200-NEXT:    v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_sub_co_i32 s4, s4, 26
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_cmp_gt_i32 s4, 26
; GFX1200-NEXT:    v_mul_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_rndne_f64_e32 v[4:5], v[4:5]
; GFX1200-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[0:1], v[6:7]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
; GFX1200-NEXT:    v_add_f64_e32 v[9:10], v[4:5], v[0:1]
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_dual_cndmask_b32 v5, v5, v10 :: v_dual_cndmask_b32 v4, v4, v9
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; GFX1200-NEXT:    s_cbranch_scc1 .LBB23_3
; GFX1200-NEXT:  ; %bb.4:
; GFX1200-NEXT:    v_mov_b32_e32 v9, s4
; GFX1200-NEXT:    s_branch .LBB23_7
; GFX1200-NEXT:  .LBB23_5: ; %frem.else
; GFX1200-NEXT:    v_cmp_eq_f64_e64 s5, |s[0:1]|, |s[2:3]|
; GFX1200-NEXT:    s_and_b32 s4, s1, 0x80000000
; GFX1200-NEXT:    s_cmp_lg_u32 s5, 0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_cselect_b32 s5, s4, s1
; GFX1200-NEXT:    s_cselect_b32 s4, 0, s0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v0, s4
; GFX1200-NEXT:    s_branch .LBB23_8
; GFX1200-NEXT:  .LBB23_6:
; GFX1200-NEXT:    v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX1200-NEXT:  .LBB23_7: ; %frem.loop_exit
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_subrev_nc_u32_e32 v4, 25, v9
; GFX1200-NEXT:    v_ldexp_f64 v[4:5], v[6:7], v4
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_mul_f64_e32 v[2:3], v[4:5], v[2:3]
; GFX1200-NEXT:    v_rndne_f64_e32 v[2:3], v[2:3]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[0:1], v[4:5]
; GFX1200-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[2:3]
; GFX1200-NEXT:    v_add_f64_e32 v[0:1], v[2:3], v[0:1]
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_dual_cndmask_b32 v1, v3, v1 :: v_dual_cndmask_b32 v0, v2, v0
; GFX1200-NEXT:    v_ldexp_f64 v[0:1], v[0:1], v8
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_bfi_b32 v1, 0x7fffffff, v1, s1
; GFX1200-NEXT:  .LBB23_8:
; GFX1200-NEXT:    v_cmp_lg_f64_e64 s2, s[2:3], 0
; GFX1200-NEXT:    v_cmp_nge_f64_e64 s0, |s[0:1]|, 0x7ff00000
; GFX1200-NEXT:    s_and_b32 vcc_lo, s0, s2
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    v_dual_cndmask_b32 v0, 0, v0 :: v_dual_cndmask_b32 v1, 0x7ff80000, v1
; GFX1200-NEXT:    s_setpc_b64 s[30:31]
   %r2 = frem double %in1, %in2
  ret double %r2
}

define double @fast_frem_f64_uniform(double inreg %in1, double inreg %in2) #0 {
; SI-LABEL: fast_frem_f64_uniform:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_mov_b32_e32 v0, s16
; SI-NEXT:    v_mov_b32_e32 v1, s17
; SI-NEXT:    v_div_scale_f64 v[2:3], s[4:5], s[18:19], s[18:19], v[0:1]
; SI-NEXT:    s_mov_b32 s7, 0xfffff
; SI-NEXT:    v_rcp_f64_e32 v[4:5], v[2:3]
; SI-NEXT:    v_cmp_eq_u32_e32 vcc, s19, v3
; SI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
; SI-NEXT:    v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; SI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
; SI-NEXT:    v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; SI-NEXT:    v_mov_b32_e32 v6, s18
; SI-NEXT:    v_mov_b32_e32 v7, s19
; SI-NEXT:    v_div_scale_f64 v[8:9], s[4:5], s[16:17], v[6:7], s[16:17]
; SI-NEXT:    v_mul_f64 v[10:11], v[8:9], v[4:5]
; SI-NEXT:    v_cmp_eq_u32_e64 s[4:5], s17, v9
; SI-NEXT:    v_fma_f64 v[12:13], -v[2:3], v[10:11], v[8:9]
; SI-NEXT:    s_xor_b64 vcc, s[4:5], vcc
; SI-NEXT:    v_div_fmas_f64 v[2:3], v[12:13], v[4:5], v[10:11]
; SI-NEXT:    v_div_fixup_f64 v[2:3], v[2:3], s[18:19], v[0:1]
; SI-NEXT:    v_readfirstlane_b32 s5, v3
; SI-NEXT:    s_bfe_u32 s6, s5, 0xb0014
; SI-NEXT:    s_add_i32 s8, s6, 0xfffffc01
; SI-NEXT:    s_mov_b32 s6, -1
; SI-NEXT:    v_readfirstlane_b32 s4, v2
; SI-NEXT:    s_lshr_b64 s[6:7], s[6:7], s8
; SI-NEXT:    s_andn2_b64 s[6:7], s[4:5], s[6:7]
; SI-NEXT:    s_and_b32 s9, s5, 0x80000000
; SI-NEXT:    s_cmp_lt_i32 s8, 0
; SI-NEXT:    s_cselect_b32 s6, 0, s6
; SI-NEXT:    s_cselect_b32 s7, s9, s7
; SI-NEXT:    s_cmp_gt_i32 s8, 51
; SI-NEXT:    s_cselect_b32 s5, s5, s7
; SI-NEXT:    s_cselect_b32 s4, s4, s6
; SI-NEXT:    v_fma_f64 v[0:1], -s[4:5], v[6:7], v[0:1]
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; CI-LABEL: fast_frem_f64_uniform:
; CI:       ; %bb.0:
; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-NEXT:    v_mov_b32_e32 v0, s16
; CI-NEXT:    v_mov_b32_e32 v1, s17
; CI-NEXT:    v_div_scale_f64 v[2:3], s[4:5], s[18:19], s[18:19], v[0:1]
; CI-NEXT:    v_rcp_f64_e32 v[4:5], v[2:3]
; CI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
; CI-NEXT:    v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; CI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
; CI-NEXT:    v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; CI-NEXT:    v_mov_b32_e32 v6, s18
; CI-NEXT:    v_mov_b32_e32 v7, s19
; CI-NEXT:    v_div_scale_f64 v[6:7], vcc, s[16:17], v[6:7], s[16:17]
; CI-NEXT:    v_mul_f64 v[8:9], v[6:7], v[4:5]
; CI-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[8:9], v[6:7]
; CI-NEXT:    s_nop 1
; CI-NEXT:    v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[8:9]
; CI-NEXT:    v_div_fixup_f64 v[2:3], v[2:3], s[18:19], v[0:1]
; CI-NEXT:    v_trunc_f64_e32 v[2:3], v[2:3]
; CI-NEXT:    v_fma_f64 v[0:1], -v[2:3], s[18:19], v[0:1]
; CI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: fast_frem_f64_uniform:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s17
; VI-NEXT:    v_div_scale_f64 v[2:3], s[4:5], s[18:19], s[18:19], v[0:1]
; VI-NEXT:    v_rcp_f64_e32 v[4:5], v[2:3]
; VI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
; VI-NEXT:    v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; VI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
; VI-NEXT:    v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; VI-NEXT:    v_mov_b32_e32 v6, s18
; VI-NEXT:    v_mov_b32_e32 v7, s19
; VI-NEXT:    v_div_scale_f64 v[6:7], vcc, s[16:17], v[6:7], s[16:17]
; VI-NEXT:    v_mul_f64 v[8:9], v[6:7], v[4:5]
; VI-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[8:9], v[6:7]
; VI-NEXT:    s_nop 1
; VI-NEXT:    v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[8:9]
; VI-NEXT:    v_div_fixup_f64 v[2:3], v[2:3], s[18:19], v[0:1]
; VI-NEXT:    v_trunc_f64_e32 v[2:3], v[2:3]
; VI-NEXT:    v_fma_f64 v[0:1], -v[2:3], s[18:19], v[0:1]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: fast_frem_f64_uniform:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s17
; GFX9-NEXT:    v_div_scale_f64 v[2:3], s[4:5], s[18:19], s[18:19], v[0:1]
; GFX9-NEXT:    v_rcp_f64_e32 v[4:5], v[2:3]
; GFX9-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
; GFX9-NEXT:    v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; GFX9-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
; GFX9-NEXT:    v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; GFX9-NEXT:    v_mov_b32_e32 v6, s18
; GFX9-NEXT:    v_mov_b32_e32 v7, s19
; GFX9-NEXT:    v_div_scale_f64 v[6:7], vcc, s[16:17], v[6:7], s[16:17]
; GFX9-NEXT:    v_mul_f64 v[8:9], v[6:7], v[4:5]
; GFX9-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[8:9], v[6:7]
; GFX9-NEXT:    s_nop 1
; GFX9-NEXT:    v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[8:9]
; GFX9-NEXT:    v_div_fixup_f64 v[2:3], v[2:3], s[18:19], v[0:1]
; GFX9-NEXT:    v_trunc_f64_e32 v[2:3], v[2:3]
; GFX9-NEXT:    v_fma_f64 v[0:1], -v[2:3], s[18:19], v[0:1]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: fast_frem_f64_uniform:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_div_scale_f64 v[0:1], s4, s[18:19], s[18:19], s[16:17]
; GFX10-NEXT:    v_rcp_f64_e32 v[2:3], v[0:1]
; GFX10-NEXT:    v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; GFX10-NEXT:    v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
; GFX10-NEXT:    v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; GFX10-NEXT:    v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
; GFX10-NEXT:    v_div_scale_f64 v[4:5], vcc_lo, s[16:17], s[18:19], s[16:17]
; GFX10-NEXT:    v_mul_f64 v[6:7], v[4:5], v[2:3]
; GFX10-NEXT:    v_fma_f64 v[0:1], -v[0:1], v[6:7], v[4:5]
; GFX10-NEXT:    v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[6:7]
; GFX10-NEXT:    v_div_fixup_f64 v[0:1], v[0:1], s[18:19], s[16:17]
; GFX10-NEXT:    v_trunc_f64_e32 v[0:1], v[0:1]
; GFX10-NEXT:    v_fma_f64 v[0:1], -v[0:1], s[18:19], s[16:17]
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: fast_frem_f64_uniform:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_div_scale_f64 v[0:1], null, s[2:3], s[2:3], s[0:1]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_rcp_f64_e32 v[2:3], v[0:1]
; GFX11-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT:    v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; GFX11-NEXT:    v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; GFX11-NEXT:    v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
; GFX11-NEXT:    v_div_scale_f64 v[4:5], vcc_lo, s[0:1], s[2:3], s[0:1]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_mul_f64 v[6:7], v[4:5], v[2:3]
; GFX11-NEXT:    v_fma_f64 v[0:1], -v[0:1], v[6:7], v[4:5]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[6:7]
; GFX11-NEXT:    v_div_fixup_f64 v[0:1], v[0:1], s[2:3], s[0:1]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_trunc_f64_e32 v[0:1], v[0:1]
; GFX11-NEXT:    v_fma_f64 v[0:1], -v[0:1], s[2:3], s[0:1]
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-LABEL: fast_frem_f64_uniform:
; GFX1150:       ; %bb.0:
; GFX1150-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-NEXT:    v_div_scale_f64 v[0:1], null, s[2:3], s[2:3], s[0:1]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_rcp_f64_e32 v[2:3], v[0:1]
; GFX1150-NEXT:    v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
; GFX1150-NEXT:    v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
; GFX1150-NEXT:    v_div_scale_f64 v[4:5], vcc_lo, s[0:1], s[2:3], s[0:1]
; GFX1150-NEXT:    v_mul_f64 v[6:7], v[4:5], v[2:3]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[0:1], -v[0:1], v[6:7], v[4:5]
; GFX1150-NEXT:    v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[6:7]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_div_fixup_f64 v[0:1], v[0:1], s[2:3], s[0:1]
; GFX1150-NEXT:    v_trunc_f64_e32 v[0:1], v[0:1]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[0:1], -v[0:1], s[2:3], s[0:1]
; GFX1150-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: fast_frem_f64_uniform:
; GFX1200:       ; %bb.0:
; GFX1200-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT:    s_wait_expcnt 0x0
; GFX1200-NEXT:    s_wait_samplecnt 0x0
; GFX1200-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-NEXT:    s_wait_kmcnt 0x0
; GFX1200-NEXT:    v_div_scale_f64 v[0:1], null, s[2:3], s[2:3], s[0:1]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_rcp_f64_e32 v[2:3], v[0:1]
; GFX1200-NEXT:    v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
; GFX1200-NEXT:    v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
; GFX1200-NEXT:    v_div_scale_f64 v[4:5], vcc_lo, s[0:1], s[2:3], s[0:1]
; GFX1200-NEXT:    v_mul_f64_e32 v[6:7], v[4:5], v[2:3]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f64 v[0:1], -v[0:1], v[6:7], v[4:5]
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[6:7]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_div_fixup_f64 v[0:1], v[0:1], s[2:3], s[0:1]
; GFX1200-NEXT:    v_trunc_f64_e32 v[0:1], v[0:1]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f64 v[0:1], -v[0:1], s[2:3], s[0:1]
; GFX1200-NEXT:    s_setpc_b64 s[30:31]
   %r2 = frem fast double %in1, %in2
  ret double %r2
}

define double @unsafe_frem_f64_uniform(double inreg %in1, double inreg %in2) #0 {
; SI-LABEL: unsafe_frem_f64_uniform:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_mov_b32_e32 v0, s16
; SI-NEXT:    v_mov_b32_e32 v1, s17
; SI-NEXT:    v_div_scale_f64 v[2:3], s[4:5], s[18:19], s[18:19], v[0:1]
; SI-NEXT:    s_mov_b32 s7, 0xfffff
; SI-NEXT:    v_rcp_f64_e32 v[4:5], v[2:3]
; SI-NEXT:    v_cmp_eq_u32_e32 vcc, s19, v3
; SI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
; SI-NEXT:    v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; SI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
; SI-NEXT:    v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; SI-NEXT:    v_mov_b32_e32 v6, s18
; SI-NEXT:    v_mov_b32_e32 v7, s19
; SI-NEXT:    v_div_scale_f64 v[8:9], s[4:5], s[16:17], v[6:7], s[16:17]
; SI-NEXT:    v_mul_f64 v[10:11], v[8:9], v[4:5]
; SI-NEXT:    v_cmp_eq_u32_e64 s[4:5], s17, v9
; SI-NEXT:    v_fma_f64 v[12:13], -v[2:3], v[10:11], v[8:9]
; SI-NEXT:    s_xor_b64 vcc, s[4:5], vcc
; SI-NEXT:    v_div_fmas_f64 v[2:3], v[12:13], v[4:5], v[10:11]
; SI-NEXT:    v_div_fixup_f64 v[2:3], v[2:3], s[18:19], v[0:1]
; SI-NEXT:    v_readfirstlane_b32 s5, v3
; SI-NEXT:    s_bfe_u32 s6, s5, 0xb0014
; SI-NEXT:    s_add_i32 s8, s6, 0xfffffc01
; SI-NEXT:    s_mov_b32 s6, -1
; SI-NEXT:    v_readfirstlane_b32 s4, v2
; SI-NEXT:    s_lshr_b64 s[6:7], s[6:7], s8
; SI-NEXT:    s_andn2_b64 s[6:7], s[4:5], s[6:7]
; SI-NEXT:    s_and_b32 s9, s5, 0x80000000
; SI-NEXT:    s_cmp_lt_i32 s8, 0
; SI-NEXT:    s_cselect_b32 s6, 0, s6
; SI-NEXT:    s_cselect_b32 s7, s9, s7
; SI-NEXT:    s_cmp_gt_i32 s8, 51
; SI-NEXT:    s_cselect_b32 s5, s5, s7
; SI-NEXT:    s_cselect_b32 s4, s4, s6
; SI-NEXT:    v_fma_f64 v[0:1], -s[4:5], v[6:7], v[0:1]
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; CI-LABEL: unsafe_frem_f64_uniform:
; CI:       ; %bb.0:
; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-NEXT:    v_mov_b32_e32 v0, s16
; CI-NEXT:    v_mov_b32_e32 v1, s17
; CI-NEXT:    v_div_scale_f64 v[2:3], s[4:5], s[18:19], s[18:19], v[0:1]
; CI-NEXT:    v_rcp_f64_e32 v[4:5], v[2:3]
; CI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
; CI-NEXT:    v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; CI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
; CI-NEXT:    v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; CI-NEXT:    v_mov_b32_e32 v6, s18
; CI-NEXT:    v_mov_b32_e32 v7, s19
; CI-NEXT:    v_div_scale_f64 v[6:7], vcc, s[16:17], v[6:7], s[16:17]
; CI-NEXT:    v_mul_f64 v[8:9], v[6:7], v[4:5]
; CI-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[8:9], v[6:7]
; CI-NEXT:    s_nop 1
; CI-NEXT:    v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[8:9]
; CI-NEXT:    v_div_fixup_f64 v[2:3], v[2:3], s[18:19], v[0:1]
; CI-NEXT:    v_trunc_f64_e32 v[2:3], v[2:3]
; CI-NEXT:    v_fma_f64 v[0:1], -v[2:3], s[18:19], v[0:1]
; CI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: unsafe_frem_f64_uniform:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s17
; VI-NEXT:    v_div_scale_f64 v[2:3], s[4:5], s[18:19], s[18:19], v[0:1]
; VI-NEXT:    v_rcp_f64_e32 v[4:5], v[2:3]
; VI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
; VI-NEXT:    v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; VI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
; VI-NEXT:    v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; VI-NEXT:    v_mov_b32_e32 v6, s18
; VI-NEXT:    v_mov_b32_e32 v7, s19
; VI-NEXT:    v_div_scale_f64 v[6:7], vcc, s[16:17], v[6:7], s[16:17]
; VI-NEXT:    v_mul_f64 v[8:9], v[6:7], v[4:5]
; VI-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[8:9], v[6:7]
; VI-NEXT:    s_nop 1
; VI-NEXT:    v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[8:9]
; VI-NEXT:    v_div_fixup_f64 v[2:3], v[2:3], s[18:19], v[0:1]
; VI-NEXT:    v_trunc_f64_e32 v[2:3], v[2:3]
; VI-NEXT:    v_fma_f64 v[0:1], -v[2:3], s[18:19], v[0:1]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: unsafe_frem_f64_uniform:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s17
; GFX9-NEXT:    v_div_scale_f64 v[2:3], s[4:5], s[18:19], s[18:19], v[0:1]
; GFX9-NEXT:    v_rcp_f64_e32 v[4:5], v[2:3]
; GFX9-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
; GFX9-NEXT:    v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; GFX9-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
; GFX9-NEXT:    v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; GFX9-NEXT:    v_mov_b32_e32 v6, s18
; GFX9-NEXT:    v_mov_b32_e32 v7, s19
; GFX9-NEXT:    v_div_scale_f64 v[6:7], vcc, s[16:17], v[6:7], s[16:17]
; GFX9-NEXT:    v_mul_f64 v[8:9], v[6:7], v[4:5]
; GFX9-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[8:9], v[6:7]
; GFX9-NEXT:    s_nop 1
; GFX9-NEXT:    v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[8:9]
; GFX9-NEXT:    v_div_fixup_f64 v[2:3], v[2:3], s[18:19], v[0:1]
; GFX9-NEXT:    v_trunc_f64_e32 v[2:3], v[2:3]
; GFX9-NEXT:    v_fma_f64 v[0:1], -v[2:3], s[18:19], v[0:1]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: unsafe_frem_f64_uniform:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_div_scale_f64 v[0:1], s4, s[18:19], s[18:19], s[16:17]
; GFX10-NEXT:    v_rcp_f64_e32 v[2:3], v[0:1]
; GFX10-NEXT:    v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; GFX10-NEXT:    v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
; GFX10-NEXT:    v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; GFX10-NEXT:    v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
; GFX10-NEXT:    v_div_scale_f64 v[4:5], vcc_lo, s[16:17], s[18:19], s[16:17]
; GFX10-NEXT:    v_mul_f64 v[6:7], v[4:5], v[2:3]
; GFX10-NEXT:    v_fma_f64 v[0:1], -v[0:1], v[6:7], v[4:5]
; GFX10-NEXT:    v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[6:7]
; GFX10-NEXT:    v_div_fixup_f64 v[0:1], v[0:1], s[18:19], s[16:17]
; GFX10-NEXT:    v_trunc_f64_e32 v[0:1], v[0:1]
; GFX10-NEXT:    v_fma_f64 v[0:1], -v[0:1], s[18:19], s[16:17]
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: unsafe_frem_f64_uniform:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_div_scale_f64 v[0:1], null, s[2:3], s[2:3], s[0:1]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_rcp_f64_e32 v[2:3], v[0:1]
; GFX11-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT:    v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; GFX11-NEXT:    v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; GFX11-NEXT:    v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
; GFX11-NEXT:    v_div_scale_f64 v[4:5], vcc_lo, s[0:1], s[2:3], s[0:1]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_mul_f64 v[6:7], v[4:5], v[2:3]
; GFX11-NEXT:    v_fma_f64 v[0:1], -v[0:1], v[6:7], v[4:5]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[6:7]
; GFX11-NEXT:    v_div_fixup_f64 v[0:1], v[0:1], s[2:3], s[0:1]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_trunc_f64_e32 v[0:1], v[0:1]
; GFX11-NEXT:    v_fma_f64 v[0:1], -v[0:1], s[2:3], s[0:1]
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-LABEL: unsafe_frem_f64_uniform:
; GFX1150:       ; %bb.0:
; GFX1150-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-NEXT:    v_div_scale_f64 v[0:1], null, s[2:3], s[2:3], s[0:1]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_rcp_f64_e32 v[2:3], v[0:1]
; GFX1150-NEXT:    v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
; GFX1150-NEXT:    v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
; GFX1150-NEXT:    v_div_scale_f64 v[4:5], vcc_lo, s[0:1], s[2:3], s[0:1]
; GFX1150-NEXT:    v_mul_f64 v[6:7], v[4:5], v[2:3]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[0:1], -v[0:1], v[6:7], v[4:5]
; GFX1150-NEXT:    v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[6:7]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_div_fixup_f64 v[0:1], v[0:1], s[2:3], s[0:1]
; GFX1150-NEXT:    v_trunc_f64_e32 v[0:1], v[0:1]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[0:1], -v[0:1], s[2:3], s[0:1]
; GFX1150-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: unsafe_frem_f64_uniform:
; GFX1200:       ; %bb.0:
; GFX1200-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT:    s_wait_expcnt 0x0
; GFX1200-NEXT:    s_wait_samplecnt 0x0
; GFX1200-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-NEXT:    s_wait_kmcnt 0x0
; GFX1200-NEXT:    v_div_scale_f64 v[0:1], null, s[2:3], s[2:3], s[0:1]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_rcp_f64_e32 v[2:3], v[0:1]
; GFX1200-NEXT:    v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
; GFX1200-NEXT:    v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
; GFX1200-NEXT:    v_div_scale_f64 v[4:5], vcc_lo, s[0:1], s[2:3], s[0:1]
; GFX1200-NEXT:    v_mul_f64_e32 v[6:7], v[4:5], v[2:3]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f64 v[0:1], -v[0:1], v[6:7], v[4:5]
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[6:7]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_div_fixup_f64 v[0:1], v[0:1], s[2:3], s[0:1]
; GFX1200-NEXT:    v_trunc_f64_e32 v[0:1], v[0:1]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f64 v[0:1], -v[0:1], s[2:3], s[0:1]
; GFX1200-NEXT:    s_setpc_b64 s[30:31]
   %r2 = frem afn double %in1, %in2
  ret double %r2
}

define <2 x half> @frem_v2f16_uniform(<2 x half> inreg %in1, <2 x half> inreg %in2) #0 {
; SI-LABEL: frem_v2f16_uniform:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cvt_f32_f16_e64 v1, |s16|
; SI-NEXT:    v_cvt_f32_f16_e64 v0, |s17|
; SI-NEXT:    s_lshr_b32 s7, s17, 16
; SI-NEXT:    s_lshr_b32 s6, s16, 16
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v0
; SI-NEXT:    s_cbranch_vccz .LBB26_4
; SI-NEXT:  ; %bb.1: ; %frem.compute19
; SI-NEXT:    s_mov_b32 s9, 0x7f800000
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v1|, s9
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v2, v1
; SI-NEXT:    s_and_b64 s[4:5], vcc, exec
; SI-NEXT:    v_readfirstlane_b32 s4, v2
; SI-NEXT:    v_frexp_mant_f32_e32 v2, v1
; SI-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, s9
; SI-NEXT:    v_frexp_mant_f32_e32 v2, v0
; SI-NEXT:    s_cselect_b32 s8, s4, 0
; SI-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v0, v0
; SI-NEXT:    s_and_b64 s[4:5], vcc, exec
; SI-NEXT:    v_readfirstlane_b32 s4, v0
; SI-NEXT:    v_ldexp_f32_e64 v0, v2, 1
; SI-NEXT:    v_div_scale_f32 v3, s[10:11], v0, v0, 1.0
; SI-NEXT:    v_rcp_f32_e32 v4, v3
; SI-NEXT:    v_ldexp_f32_e64 v1, v1, 11
; SI-NEXT:    v_div_scale_f32 v2, vcc, 1.0, v0, 1.0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
; SI-NEXT:    v_fma_f32 v4, v5, v4, v4
; SI-NEXT:    v_mul_f32_e32 v5, v2, v4
; SI-NEXT:    s_cselect_b32 s9, s4, 0
; SI-NEXT:    v_fma_f32 v6, -v3, v5, v2
; SI-NEXT:    s_add_i32 s4, s9, -1
; SI-NEXT:    v_fma_f32 v5, v6, v4, v5
; SI-NEXT:    s_not_b32 s5, s4
; SI-NEXT:    v_fma_f32 v2, -v3, v5, v2
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    s_add_i32 s5, s5, s8
; SI-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
; SI-NEXT:    v_div_fixup_f32 v2, v2, v0, 1.0
; SI-NEXT:    s_cmp_lt_i32 s5, 12
; SI-NEXT:    s_cbranch_scc1 .LBB26_5
; SI-NEXT:  ; %bb.2: ; %frem.loop_body27.preheader
; SI-NEXT:    s_sub_i32 s5, s8, s9
; SI-NEXT:    s_add_i32 s5, s5, 11
; SI-NEXT:  .LBB26_3: ; %frem.loop_body27
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v3, v1
; SI-NEXT:    v_mul_f32_e32 v1, v3, v2
; SI-NEXT:    v_rndne_f32_e32 v1, v1
; SI-NEXT:    v_fma_f32 v1, -v1, v0, v3
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v1
; SI-NEXT:    v_add_f32_e32 v4, v1, v0
; SI-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
; SI-NEXT:    s_add_i32 s5, s5, -11
; SI-NEXT:    v_ldexp_f32_e64 v1, v1, 11
; SI-NEXT:    s_cmp_gt_i32 s5, 11
; SI-NEXT:    s_cbranch_scc1 .LBB26_3
; SI-NEXT:    s_branch .LBB26_6
; SI-NEXT:  .LBB26_4: ; %frem.else20
; SI-NEXT:    s_and_b32 s8, s16, 0xffff8000
; SI-NEXT:    v_cmp_eq_f32_e32 vcc, v1, v0
; SI-NEXT:    s_and_b64 s[4:5], vcc, exec
; SI-NEXT:    s_cselect_b32 s4, s8, s16
; SI-NEXT:    v_mov_b32_e32 v0, s4
; SI-NEXT:    s_branch .LBB26_7
; SI-NEXT:  .LBB26_5:
; SI-NEXT:    v_mov_b32_e32 v3, v1
; SI-NEXT:  .LBB26_6: ; %frem.loop_exit28
; SI-NEXT:    s_add_i32 s5, s5, -10
; SI-NEXT:    v_ldexp_f32_e64 v1, v3, s5
; SI-NEXT:    v_mul_f32_e32 v2, v1, v2
; SI-NEXT:    v_rndne_f32_e32 v2, v2
; SI-NEXT:    v_fma_f32 v1, -v2, v0, v1
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v1
; SI-NEXT:    v_add_f32_e32 v0, v1, v0
; SI-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; SI-NEXT:    v_ldexp_f32_e64 v0, v0, s4
; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-NEXT:    s_and_b32 s4, s16, 0xffff8000
; SI-NEXT:    v_and_b32_e32 v0, 0x7fff, v0
; SI-NEXT:    v_or_b32_e32 v0, s4, v0
; SI-NEXT:  .LBB26_7:
; SI-NEXT:    v_cvt_f32_f16_e64 v2, |s6|
; SI-NEXT:    v_cvt_f32_f16_e64 v1, |s7|
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v1
; SI-NEXT:    s_cbranch_vccz .LBB26_11
; SI-NEXT:  ; %bb.8: ; %frem.compute
; SI-NEXT:    s_mov_b32 s9, 0x7f800000
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v2|, s9
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v3, v2
; SI-NEXT:    s_and_b64 s[4:5], vcc, exec
; SI-NEXT:    v_readfirstlane_b32 s4, v3
; SI-NEXT:    v_frexp_mant_f32_e32 v3, v2
; SI-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v1|, s9
; SI-NEXT:    v_frexp_mant_f32_e32 v3, v1
; SI-NEXT:    s_cselect_b32 s8, s4, 0
; SI-NEXT:    v_cndmask_b32_e32 v3, v1, v3, vcc
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v1, v1
; SI-NEXT:    s_and_b64 s[4:5], vcc, exec
; SI-NEXT:    v_readfirstlane_b32 s4, v1
; SI-NEXT:    v_ldexp_f32_e64 v1, v3, 1
; SI-NEXT:    v_div_scale_f32 v4, s[10:11], v1, v1, 1.0
; SI-NEXT:    v_rcp_f32_e32 v5, v4
; SI-NEXT:    v_ldexp_f32_e64 v2, v2, 11
; SI-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v1, 1.0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    v_fma_f32 v6, -v4, v5, 1.0
; SI-NEXT:    v_fma_f32 v5, v6, v5, v5
; SI-NEXT:    v_mul_f32_e32 v6, v3, v5
; SI-NEXT:    s_cselect_b32 s9, s4, 0
; SI-NEXT:    v_fma_f32 v7, -v4, v6, v3
; SI-NEXT:    s_add_i32 s4, s9, -1
; SI-NEXT:    v_fma_f32 v6, v7, v5, v6
; SI-NEXT:    s_not_b32 s5, s4
; SI-NEXT:    v_fma_f32 v3, -v4, v6, v3
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    s_add_i32 s5, s5, s8
; SI-NEXT:    v_div_fmas_f32 v3, v3, v5, v6
; SI-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; SI-NEXT:    s_cmp_lt_i32 s5, 12
; SI-NEXT:    s_cbranch_scc1 .LBB26_12
; SI-NEXT:  ; %bb.9: ; %frem.loop_body.preheader
; SI-NEXT:    s_sub_i32 s5, s8, s9
; SI-NEXT:    s_add_i32 s5, s5, 11
; SI-NEXT:  .LBB26_10: ; %frem.loop_body
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v4, v2
; SI-NEXT:    v_mul_f32_e32 v2, v4, v3
; SI-NEXT:    v_rndne_f32_e32 v2, v2
; SI-NEXT:    v_fma_f32 v2, -v2, v1, v4
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v2
; SI-NEXT:    v_add_f32_e32 v5, v2, v1
; SI-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
; SI-NEXT:    s_add_i32 s5, s5, -11
; SI-NEXT:    v_ldexp_f32_e64 v2, v2, 11
; SI-NEXT:    s_cmp_gt_i32 s5, 11
; SI-NEXT:    s_cbranch_scc1 .LBB26_10
; SI-NEXT:    s_branch .LBB26_13
; SI-NEXT:  .LBB26_11: ; %frem.else
; SI-NEXT:    s_and_b32 s8, s6, 0x8000
; SI-NEXT:    v_cmp_eq_f32_e32 vcc, v2, v1
; SI-NEXT:    s_and_b64 s[4:5], vcc, exec
; SI-NEXT:    s_cselect_b32 s4, s8, s6
; SI-NEXT:    v_mov_b32_e32 v1, s4
; SI-NEXT:    s_branch .LBB26_14
; SI-NEXT:  .LBB26_12:
; SI-NEXT:    v_mov_b32_e32 v4, v2
; SI-NEXT:  .LBB26_13: ; %frem.loop_exit
; SI-NEXT:    s_add_i32 s5, s5, -10
; SI-NEXT:    v_ldexp_f32_e64 v2, v4, s5
; SI-NEXT:    v_mul_f32_e32 v3, v2, v3
; SI-NEXT:    v_rndne_f32_e32 v3, v3
; SI-NEXT:    v_fma_f32 v2, -v3, v1, v2
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v2
; SI-NEXT:    v_add_f32_e32 v1, v2, v1
; SI-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; SI-NEXT:    v_ldexp_f32_e64 v1, v1, s4
; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1
; SI-NEXT:    s_and_b32 s4, s6, 0x8000
; SI-NEXT:    v_and_b32_e32 v1, 0x7fff, v1
; SI-NEXT:    v_or_b32_e32 v1, s4, v1
; SI-NEXT:  .LBB26_14:
; SI-NEXT:    v_cvt_f32_f16_e32 v2, s17
; SI-NEXT:    v_cvt_f32_f16_e32 v3, s7
; SI-NEXT:    s_mov_b32 s8, 0x7f800000
; SI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v2
; SI-NEXT:    v_cvt_f32_f16_e64 v2, |s16|
; SI-NEXT:    v_cmp_nle_f32_e64 s[4:5], s8, v2
; SI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; SI-NEXT:    v_mov_b32_e32 v2, 0x7e00
; SI-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
; SI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v3
; SI-NEXT:    v_cvt_f32_f16_e64 v3, |s6|
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_cmp_nle_f32_e64 s[4:5], s8, v3
; SI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; SI-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT:    v_or_b32_e32 v0, v0, v1
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; CI-LABEL: frem_v2f16_uniform:
; CI:       ; %bb.0:
; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-NEXT:    v_cvt_f32_f16_e64 v1, |s16|
; CI-NEXT:    v_cvt_f32_f16_e64 v0, |s17|
; CI-NEXT:    s_lshr_b32 s7, s17, 16
; CI-NEXT:    s_lshr_b32 s6, s16, 16
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v0
; CI-NEXT:    s_cbranch_vccz .LBB26_4
; CI-NEXT:  ; %bb.1: ; %frem.compute19
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v5, v1
; CI-NEXT:    v_frexp_mant_f32_e32 v1, v1
; CI-NEXT:    v_ldexp_f32_e64 v4, v1, 11
; CI-NEXT:    v_frexp_mant_f32_e32 v1, v0
; CI-NEXT:    v_ldexp_f32_e64 v1, v1, 1
; CI-NEXT:    v_div_scale_f32 v7, s[4:5], v1, v1, 1.0
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v6, v0
; CI-NEXT:    v_add_i32_e32 v0, vcc, -1, v6
; CI-NEXT:    v_not_b32_e32 v2, v0
; CI-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
; CI-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v1, 1.0
; CI-NEXT:    v_rcp_f32_e32 v8, v7
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
; CI-NEXT:    v_fma_f32 v8, v9, v8, v8
; CI-NEXT:    v_mul_f32_e32 v9, v3, v8
; CI-NEXT:    v_fma_f32 v10, -v7, v9, v3
; CI-NEXT:    v_fma_f32 v9, v10, v8, v9
; CI-NEXT:    v_fma_f32 v3, -v7, v9, v3
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v3, v3, v8, v9
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v2
; CI-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; CI-NEXT:    s_cbranch_vccnz .LBB26_5
; CI-NEXT:  ; %bb.2: ; %frem.loop_body27.preheader
; CI-NEXT:    v_sub_i32_e32 v2, vcc, v5, v6
; CI-NEXT:    v_add_i32_e32 v2, vcc, 11, v2
; CI-NEXT:  .LBB26_3: ; %frem.loop_body27
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v5, v4
; CI-NEXT:    v_mul_f32_e32 v4, v5, v3
; CI-NEXT:    v_rndne_f32_e32 v4, v4
; CI-NEXT:    v_fma_f32 v4, -v4, v1, v5
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; CI-NEXT:    v_add_f32_e32 v6, v4, v1
; CI-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
; CI-NEXT:    v_add_i32_e32 v2, vcc, -11, v2
; CI-NEXT:    v_ldexp_f32_e64 v4, v4, 11
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v2
; CI-NEXT:    s_cbranch_vccnz .LBB26_3
; CI-NEXT:    s_branch .LBB26_6
; CI-NEXT:  .LBB26_4: ; %frem.else20
; CI-NEXT:    s_and_b32 s8, s16, 0xffff8000
; CI-NEXT:    v_cmp_eq_f32_e32 vcc, v1, v0
; CI-NEXT:    s_and_b64 s[4:5], vcc, exec
; CI-NEXT:    s_cselect_b32 s4, s8, s16
; CI-NEXT:    v_mov_b32_e32 v0, s4
; CI-NEXT:    s_branch .LBB26_7
; CI-NEXT:  .LBB26_5:
; CI-NEXT:    v_mov_b32_e32 v5, v4
; CI-NEXT:  .LBB26_6: ; %frem.loop_exit28
; CI-NEXT:    v_add_i32_e32 v2, vcc, -10, v2
; CI-NEXT:    v_ldexp_f32_e32 v2, v5, v2
; CI-NEXT:    v_mul_f32_e32 v3, v2, v3
; CI-NEXT:    v_rndne_f32_e32 v3, v3
; CI-NEXT:    v_fma_f32 v2, -v3, v1, v2
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v2
; CI-NEXT:    v_add_f32_e32 v1, v2, v1
; CI-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; CI-NEXT:    v_ldexp_f32_e32 v0, v1, v0
; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; CI-NEXT:    s_and_b32 s4, s16, 0xffff8000
; CI-NEXT:    v_and_b32_e32 v0, 0x7fff, v0
; CI-NEXT:    v_or_b32_e32 v0, s4, v0
; CI-NEXT:  .LBB26_7:
; CI-NEXT:    v_cvt_f32_f16_e64 v2, |s6|
; CI-NEXT:    v_cvt_f32_f16_e64 v1, |s7|
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v1
; CI-NEXT:    s_cbranch_vccz .LBB26_11
; CI-NEXT:  ; %bb.8: ; %frem.compute
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v6, v2
; CI-NEXT:    v_frexp_mant_f32_e32 v2, v2
; CI-NEXT:    v_ldexp_f32_e64 v5, v2, 11
; CI-NEXT:    v_frexp_mant_f32_e32 v2, v1
; CI-NEXT:    v_ldexp_f32_e64 v2, v2, 1
; CI-NEXT:    v_div_scale_f32 v8, s[4:5], v2, v2, 1.0
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v7, v1
; CI-NEXT:    v_add_i32_e32 v1, vcc, -1, v7
; CI-NEXT:    v_not_b32_e32 v3, v1
; CI-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
; CI-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v2, 1.0
; CI-NEXT:    v_rcp_f32_e32 v9, v8
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
; CI-NEXT:    v_fma_f32 v9, v10, v9, v9
; CI-NEXT:    v_mul_f32_e32 v10, v4, v9
; CI-NEXT:    v_fma_f32 v11, -v8, v10, v4
; CI-NEXT:    v_fma_f32 v10, v11, v9, v10
; CI-NEXT:    v_fma_f32 v4, -v8, v10, v4
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v4, v4, v9, v10
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v3
; CI-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; CI-NEXT:    s_cbranch_vccnz .LBB26_12
; CI-NEXT:  ; %bb.9: ; %frem.loop_body.preheader
; CI-NEXT:    v_sub_i32_e32 v3, vcc, v6, v7
; CI-NEXT:    v_add_i32_e32 v3, vcc, 11, v3
; CI-NEXT:  .LBB26_10: ; %frem.loop_body
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v6, v5
; CI-NEXT:    v_mul_f32_e32 v5, v6, v4
; CI-NEXT:    v_rndne_f32_e32 v5, v5
; CI-NEXT:    v_fma_f32 v5, -v5, v2, v6
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
; CI-NEXT:    v_add_f32_e32 v7, v5, v2
; CI-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
; CI-NEXT:    v_add_i32_e32 v3, vcc, -11, v3
; CI-NEXT:    v_ldexp_f32_e64 v5, v5, 11
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v3
; CI-NEXT:    s_cbranch_vccnz .LBB26_10
; CI-NEXT:    s_branch .LBB26_13
; CI-NEXT:  .LBB26_11: ; %frem.else
; CI-NEXT:    s_and_b32 s8, s6, 0x8000
; CI-NEXT:    v_cmp_eq_f32_e32 vcc, v2, v1
; CI-NEXT:    s_and_b64 s[4:5], vcc, exec
; CI-NEXT:    s_cselect_b32 s4, s8, s6
; CI-NEXT:    v_mov_b32_e32 v1, s4
; CI-NEXT:    s_branch .LBB26_14
; CI-NEXT:  .LBB26_12:
; CI-NEXT:    v_mov_b32_e32 v6, v5
; CI-NEXT:  .LBB26_13: ; %frem.loop_exit
; CI-NEXT:    v_add_i32_e32 v3, vcc, -10, v3
; CI-NEXT:    v_ldexp_f32_e32 v3, v6, v3
; CI-NEXT:    v_mul_f32_e32 v4, v3, v4
; CI-NEXT:    v_rndne_f32_e32 v4, v4
; CI-NEXT:    v_fma_f32 v3, -v4, v2, v3
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v3
; CI-NEXT:    v_add_f32_e32 v2, v3, v2
; CI-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; CI-NEXT:    v_ldexp_f32_e32 v1, v2, v1
; CI-NEXT:    v_cvt_f16_f32_e32 v1, v1
; CI-NEXT:    s_and_b32 s4, s6, 0x8000
; CI-NEXT:    v_and_b32_e32 v1, 0x7fff, v1
; CI-NEXT:    v_or_b32_e32 v1, s4, v1
; CI-NEXT:  .LBB26_14:
; CI-NEXT:    v_cvt_f32_f16_e32 v2, s17
; CI-NEXT:    v_cvt_f32_f16_e32 v3, s7
; CI-NEXT:    s_mov_b32 s8, 0x7f800000
; CI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v2
; CI-NEXT:    v_cvt_f32_f16_e64 v2, |s16|
; CI-NEXT:    v_cmp_nle_f32_e64 s[4:5], s8, v2
; CI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; CI-NEXT:    v_mov_b32_e32 v2, 0x7e00
; CI-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
; CI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v3
; CI-NEXT:    v_cvt_f32_f16_e64 v3, |s6|
; CI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; CI-NEXT:    v_cmp_nle_f32_e64 s[4:5], s8, v3
; CI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; CI-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; CI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; CI-NEXT:    v_or_b32_e32 v0, v0, v1
; CI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: frem_v2f16_uniform:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cvt_f32_f16_e64 v1, |s16|
; VI-NEXT:    v_cvt_f32_f16_e64 v0, |s17|
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v0
; VI-NEXT:    s_cbranch_vccz .LBB26_4
; VI-NEXT:  ; %bb.1: ; %frem.compute19
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v5, v1
; VI-NEXT:    v_frexp_mant_f32_e32 v1, v1
; VI-NEXT:    v_ldexp_f32 v4, v1, 11
; VI-NEXT:    v_frexp_mant_f32_e32 v1, v0
; VI-NEXT:    v_ldexp_f32 v1, v1, 1
; VI-NEXT:    v_div_scale_f32 v7, s[4:5], v1, v1, 1.0
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v6, v0
; VI-NEXT:    v_add_u32_e32 v0, vcc, -1, v6
; VI-NEXT:    v_not_b32_e32 v2, v0
; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v5
; VI-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v1, 1.0
; VI-NEXT:    v_rcp_f32_e32 v8, v7
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
; VI-NEXT:    v_fma_f32 v8, v9, v8, v8
; VI-NEXT:    v_mul_f32_e32 v9, v3, v8
; VI-NEXT:    v_fma_f32 v10, -v7, v9, v3
; VI-NEXT:    v_fma_f32 v9, v10, v8, v9
; VI-NEXT:    v_fma_f32 v3, -v7, v9, v3
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; VI-NEXT:    v_div_fmas_f32 v3, v3, v8, v9
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v2
; VI-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; VI-NEXT:    s_cbranch_vccnz .LBB26_5
; VI-NEXT:  ; %bb.2: ; %frem.loop_body27.preheader
; VI-NEXT:    v_sub_u32_e32 v2, vcc, v5, v6
; VI-NEXT:    v_add_u32_e32 v2, vcc, 11, v2
; VI-NEXT:  .LBB26_3: ; %frem.loop_body27
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v5, v4
; VI-NEXT:    v_mul_f32_e32 v4, v5, v3
; VI-NEXT:    v_rndne_f32_e32 v4, v4
; VI-NEXT:    v_fma_f32 v4, -v4, v1, v5
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; VI-NEXT:    v_add_f32_e32 v6, v4, v1
; VI-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
; VI-NEXT:    v_add_u32_e32 v2, vcc, -11, v2
; VI-NEXT:    v_ldexp_f32 v4, v4, 11
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v2
; VI-NEXT:    s_cbranch_vccnz .LBB26_3
; VI-NEXT:    s_branch .LBB26_6
; VI-NEXT:  .LBB26_4: ; %frem.else20
; VI-NEXT:    s_and_b32 s4, 0x8000, s16
; VI-NEXT:    v_cmp_eq_f32_e32 vcc, v1, v0
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
; VI-NEXT:    s_branch .LBB26_7
; VI-NEXT:  .LBB26_5:
; VI-NEXT:    v_mov_b32_e32 v5, v4
; VI-NEXT:  .LBB26_6: ; %frem.loop_exit28
; VI-NEXT:    v_add_u32_e32 v2, vcc, -10, v2
; VI-NEXT:    v_ldexp_f32 v2, v5, v2
; VI-NEXT:    v_mul_f32_e32 v3, v2, v3
; VI-NEXT:    v_rndne_f32_e32 v3, v3
; VI-NEXT:    v_fma_f32 v2, -v3, v1, v2
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v2
; VI-NEXT:    v_add_f32_e32 v1, v2, v1
; VI-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; VI-NEXT:    v_ldexp_f32 v0, v1, v0
; VI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; VI-NEXT:    s_movk_i32 s4, 0x7fff
; VI-NEXT:    v_mov_b32_e32 v1, s16
; VI-NEXT:    v_bfi_b32 v0, s4, v0, v1
; VI-NEXT:  .LBB26_7:
; VI-NEXT:    s_lshr_b32 s4, s16, 16
; VI-NEXT:    s_lshr_b32 s5, s17, 16
; VI-NEXT:    v_cvt_f32_f16_e64 v2, |s4|
; VI-NEXT:    v_cvt_f32_f16_e64 v1, |s5|
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v1
; VI-NEXT:    s_cbranch_vccz .LBB26_11
; VI-NEXT:  ; %bb.8: ; %frem.compute
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v6, v2
; VI-NEXT:    v_frexp_mant_f32_e32 v2, v2
; VI-NEXT:    v_ldexp_f32 v5, v2, 11
; VI-NEXT:    v_frexp_mant_f32_e32 v2, v1
; VI-NEXT:    v_ldexp_f32 v2, v2, 1
; VI-NEXT:    v_div_scale_f32 v8, s[6:7], v2, v2, 1.0
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v7, v1
; VI-NEXT:    v_add_u32_e32 v1, vcc, -1, v7
; VI-NEXT:    v_not_b32_e32 v3, v1
; VI-NEXT:    v_add_u32_e32 v3, vcc, v3, v6
; VI-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v2, 1.0
; VI-NEXT:    v_rcp_f32_e32 v9, v8
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
; VI-NEXT:    v_fma_f32 v9, v10, v9, v9
; VI-NEXT:    v_mul_f32_e32 v10, v4, v9
; VI-NEXT:    v_fma_f32 v11, -v8, v10, v4
; VI-NEXT:    v_fma_f32 v10, v11, v9, v10
; VI-NEXT:    v_fma_f32 v4, -v8, v10, v4
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; VI-NEXT:    v_div_fmas_f32 v4, v4, v9, v10
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v3
; VI-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; VI-NEXT:    s_cbranch_vccnz .LBB26_12
; VI-NEXT:  ; %bb.9: ; %frem.loop_body.preheader
; VI-NEXT:    v_sub_u32_e32 v3, vcc, v6, v7
; VI-NEXT:    v_add_u32_e32 v3, vcc, 11, v3
; VI-NEXT:  .LBB26_10: ; %frem.loop_body
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v6, v5
; VI-NEXT:    v_mul_f32_e32 v5, v6, v4
; VI-NEXT:    v_rndne_f32_e32 v5, v5
; VI-NEXT:    v_fma_f32 v5, -v5, v2, v6
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
; VI-NEXT:    v_add_f32_e32 v7, v5, v2
; VI-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
; VI-NEXT:    v_add_u32_e32 v3, vcc, -11, v3
; VI-NEXT:    v_ldexp_f32 v5, v5, 11
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v3
; VI-NEXT:    s_cbranch_vccnz .LBB26_10
; VI-NEXT:    s_branch .LBB26_13
; VI-NEXT:  .LBB26_11: ; %frem.else
; VI-NEXT:    s_and_b32 s6, 0x8000, s4
; VI-NEXT:    v_cmp_eq_f32_e32 vcc, v2, v1
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_mov_b32_e32 v2, s6
; VI-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
; VI-NEXT:    s_branch .LBB26_14
; VI-NEXT:  .LBB26_12:
; VI-NEXT:    v_mov_b32_e32 v6, v5
; VI-NEXT:  .LBB26_13: ; %frem.loop_exit
; VI-NEXT:    v_add_u32_e32 v3, vcc, -10, v3
; VI-NEXT:    v_ldexp_f32 v3, v6, v3
; VI-NEXT:    v_mul_f32_e32 v4, v3, v4
; VI-NEXT:    v_rndne_f32_e32 v4, v4
; VI-NEXT:    v_fma_f32 v3, -v4, v2, v3
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v3
; VI-NEXT:    v_add_f32_e32 v2, v3, v2
; VI-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; VI-NEXT:    v_ldexp_f32 v1, v2, v1
; VI-NEXT:    v_cvt_f16_f32_e32 v1, v1
; VI-NEXT:    s_movk_i32 s6, 0x7fff
; VI-NEXT:    v_mov_b32_e32 v2, s4
; VI-NEXT:    v_bfi_b32 v1, s6, v1, v2
; VI-NEXT:  .LBB26_14:
; VI-NEXT:    v_mov_b32_e32 v2, 0x7c00
; VI-NEXT:    v_cmp_lg_f16_e64 s[6:7], s17, 0
; VI-NEXT:    v_cmp_nge_f16_e64 s[8:9], |s16|, v2
; VI-NEXT:    s_and_b64 vcc, s[8:9], s[6:7]
; VI-NEXT:    v_mov_b32_e32 v3, 0x7e00
; VI-NEXT:    v_cmp_lg_f16_e64 s[6:7], s5, 0
; VI-NEXT:    v_cmp_nge_f16_e64 s[4:5], |s4|, v2
; VI-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc
; VI-NEXT:    s_and_b64 vcc, s[4:5], s[6:7]
; VI-NEXT:    v_cndmask_b32_sdwa v1, v3, v1, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: frem_v2f16_uniform:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_f32_f16_e64 v1, |s16|
; GFX9-NEXT:    v_cvt_f32_f16_e64 v0, |s17|
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v0
; GFX9-NEXT:    s_cbranch_vccz .LBB26_4
; GFX9-NEXT:  ; %bb.1: ; %frem.compute19
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v5, v1
; GFX9-NEXT:    v_frexp_mant_f32_e32 v1, v1
; GFX9-NEXT:    v_ldexp_f32 v4, v1, 11
; GFX9-NEXT:    v_frexp_mant_f32_e32 v1, v0
; GFX9-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX9-NEXT:    v_div_scale_f32 v7, s[4:5], v1, v1, 1.0
; GFX9-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v1, 1.0
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v6, v0
; GFX9-NEXT:    v_add_u32_e32 v0, -1, v6
; GFX9-NEXT:    v_not_b32_e32 v2, v0
; GFX9-NEXT:    v_add_u32_e32 v2, v2, v5
; GFX9-NEXT:    v_rcp_f32_e32 v8, v7
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
; GFX9-NEXT:    v_fma_f32 v8, v9, v8, v8
; GFX9-NEXT:    v_mul_f32_e32 v9, v3, v8
; GFX9-NEXT:    v_fma_f32 v10, -v7, v9, v3
; GFX9-NEXT:    v_fma_f32 v9, v10, v8, v9
; GFX9-NEXT:    v_fma_f32 v3, -v7, v9, v3
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX9-NEXT:    v_div_fmas_f32 v3, v3, v8, v9
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v2
; GFX9-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX9-NEXT:    s_cbranch_vccnz .LBB26_5
; GFX9-NEXT:  ; %bb.2: ; %frem.loop_body27.preheader
; GFX9-NEXT:    v_sub_u32_e32 v2, v5, v6
; GFX9-NEXT:    v_add_u32_e32 v2, 11, v2
; GFX9-NEXT:  .LBB26_3: ; %frem.loop_body27
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v5, v4
; GFX9-NEXT:    v_mul_f32_e32 v4, v5, v3
; GFX9-NEXT:    v_rndne_f32_e32 v4, v4
; GFX9-NEXT:    v_fma_f32 v4, -v4, v1, v5
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; GFX9-NEXT:    v_add_f32_e32 v6, v4, v1
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX9-NEXT:    v_add_u32_e32 v2, -11, v2
; GFX9-NEXT:    v_ldexp_f32 v4, v4, 11
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v2
; GFX9-NEXT:    s_cbranch_vccnz .LBB26_3
; GFX9-NEXT:    s_branch .LBB26_6
; GFX9-NEXT:  .LBB26_4: ; %frem.else20
; GFX9-NEXT:    s_and_b32 s4, 0x8000, s16
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, v1, v0
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s4
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX9-NEXT:    s_branch .LBB26_7
; GFX9-NEXT:  .LBB26_5:
; GFX9-NEXT:    v_mov_b32_e32 v5, v4
; GFX9-NEXT:  .LBB26_6: ; %frem.loop_exit28
; GFX9-NEXT:    v_add_u32_e32 v2, -10, v2
; GFX9-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX9-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX9-NEXT:    v_rndne_f32_e32 v3, v3
; GFX9-NEXT:    v_fma_f32 v2, -v3, v1, v2
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v2
; GFX9-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX9-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX9-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX9-NEXT:    s_movk_i32 s4, 0x7fff
; GFX9-NEXT:    v_mov_b32_e32 v1, s16
; GFX9-NEXT:    v_bfi_b32 v0, s4, v0, v1
; GFX9-NEXT:  .LBB26_7:
; GFX9-NEXT:    s_lshr_b32 s4, s16, 16
; GFX9-NEXT:    s_lshr_b32 s5, s17, 16
; GFX9-NEXT:    v_cvt_f32_f16_e64 v2, |s4|
; GFX9-NEXT:    v_cvt_f32_f16_e64 v1, |s5|
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v1
; GFX9-NEXT:    s_cbranch_vccz .LBB26_11
; GFX9-NEXT:  ; %bb.8: ; %frem.compute
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v6, v2
; GFX9-NEXT:    v_frexp_mant_f32_e32 v2, v2
; GFX9-NEXT:    v_ldexp_f32 v5, v2, 11
; GFX9-NEXT:    v_frexp_mant_f32_e32 v2, v1
; GFX9-NEXT:    v_ldexp_f32 v2, v2, 1
; GFX9-NEXT:    v_div_scale_f32 v8, s[6:7], v2, v2, 1.0
; GFX9-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v2, 1.0
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v7, v1
; GFX9-NEXT:    v_add_u32_e32 v1, -1, v7
; GFX9-NEXT:    v_not_b32_e32 v3, v1
; GFX9-NEXT:    v_add_u32_e32 v3, v3, v6
; GFX9-NEXT:    v_rcp_f32_e32 v9, v8
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
; GFX9-NEXT:    v_fma_f32 v9, v10, v9, v9
; GFX9-NEXT:    v_mul_f32_e32 v10, v4, v9
; GFX9-NEXT:    v_fma_f32 v11, -v8, v10, v4
; GFX9-NEXT:    v_fma_f32 v10, v11, v9, v10
; GFX9-NEXT:    v_fma_f32 v4, -v8, v10, v4
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX9-NEXT:    v_div_fmas_f32 v4, v4, v9, v10
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v3
; GFX9-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; GFX9-NEXT:    s_cbranch_vccnz .LBB26_12
; GFX9-NEXT:  ; %bb.9: ; %frem.loop_body.preheader
; GFX9-NEXT:    v_sub_u32_e32 v3, v6, v7
; GFX9-NEXT:    v_add_u32_e32 v3, 11, v3
; GFX9-NEXT:  .LBB26_10: ; %frem.loop_body
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v6, v5
; GFX9-NEXT:    v_mul_f32_e32 v5, v6, v4
; GFX9-NEXT:    v_rndne_f32_e32 v5, v5
; GFX9-NEXT:    v_fma_f32 v5, -v5, v2, v6
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
; GFX9-NEXT:    v_add_f32_e32 v7, v5, v2
; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
; GFX9-NEXT:    v_add_u32_e32 v3, -11, v3
; GFX9-NEXT:    v_ldexp_f32 v5, v5, 11
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v3
; GFX9-NEXT:    s_cbranch_vccnz .LBB26_10
; GFX9-NEXT:    s_branch .LBB26_13
; GFX9-NEXT:  .LBB26_11: ; %frem.else
; GFX9-NEXT:    s_and_b32 s6, 0x8000, s4
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, v2, v1
; GFX9-NEXT:    v_mov_b32_e32 v1, s4
; GFX9-NEXT:    v_mov_b32_e32 v2, s6
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX9-NEXT:    s_branch .LBB26_14
; GFX9-NEXT:  .LBB26_12:
; GFX9-NEXT:    v_mov_b32_e32 v6, v5
; GFX9-NEXT:  .LBB26_13: ; %frem.loop_exit
; GFX9-NEXT:    v_add_u32_e32 v3, -10, v3
; GFX9-NEXT:    v_ldexp_f32 v3, v6, v3
; GFX9-NEXT:    v_mul_f32_e32 v4, v3, v4
; GFX9-NEXT:    v_rndne_f32_e32 v4, v4
; GFX9-NEXT:    v_fma_f32 v3, -v4, v2, v3
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v3
; GFX9-NEXT:    v_add_f32_e32 v2, v3, v2
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX9-NEXT:    v_ldexp_f32 v1, v2, v1
; GFX9-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX9-NEXT:    s_movk_i32 s6, 0x7fff
; GFX9-NEXT:    v_mov_b32_e32 v2, s4
; GFX9-NEXT:    v_bfi_b32 v1, s6, v1, v2
; GFX9-NEXT:  .LBB26_14:
; GFX9-NEXT:    v_mov_b32_e32 v2, 0x7c00
; GFX9-NEXT:    v_cmp_lg_f16_e64 s[6:7], s17, 0
; GFX9-NEXT:    v_cmp_nge_f16_e64 s[8:9], |s16|, v2
; GFX9-NEXT:    s_and_b64 vcc, s[8:9], s[6:7]
; GFX9-NEXT:    v_mov_b32_e32 v3, 0x7e00
; GFX9-NEXT:    v_cmp_lg_f16_e64 s[6:7], s5, 0
; GFX9-NEXT:    v_cmp_nge_f16_e64 s[4:5], |s4|, v2
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc
; GFX9-NEXT:    s_and_b64 vcc, s[4:5], s[6:7]
; GFX9-NEXT:    v_cndmask_b32_sdwa v1, v3, v1, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: frem_v2f16_uniform:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cvt_f32_f16_e64 v1, |s16|
; GFX10-NEXT:    v_cvt_f32_f16_e64 v0, |s17|
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v0
; GFX10-NEXT:    s_cbranch_vccz .LBB26_5
; GFX10-NEXT:  ; %bb.1: ; %frem.compute19
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v3, v1
; GFX10-NEXT:    v_frexp_mant_f32_e32 v1, v1
; GFX10-NEXT:    v_readfirstlane_b32 s4, v3
; GFX10-NEXT:    v_ldexp_f32 v2, v1, 11
; GFX10-NEXT:    v_frexp_mant_f32_e32 v1, v0
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v0, v0
; GFX10-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX10-NEXT:    v_readfirstlane_b32 s5, v0
; GFX10-NEXT:    v_add_nc_u32_e32 v0, -1, v0
; GFX10-NEXT:    v_div_scale_f32 v5, s6, v1, v1, 1.0
; GFX10-NEXT:    v_not_b32_e32 v4, v0
; GFX10-NEXT:    v_rcp_f32_e32 v6, v5
; GFX10-NEXT:    v_add_nc_u32_e32 v4, v4, v3
; GFX10-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX10-NEXT:    s_denorm_mode 15
; GFX10-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
; GFX10-NEXT:    v_fmac_f32_e32 v6, v7, v6
; GFX10-NEXT:    v_mul_f32_e32 v7, v3, v6
; GFX10-NEXT:    v_fma_f32 v8, -v5, v7, v3
; GFX10-NEXT:    v_fmac_f32_e32 v7, v8, v6
; GFX10-NEXT:    v_fma_f32 v3, -v5, v7, v3
; GFX10-NEXT:    s_denorm_mode 12
; GFX10-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX10-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX10-NEXT:    s_cbranch_vccnz .LBB26_6
; GFX10-NEXT:  ; %bb.2: ; %frem.loop_body27.preheader
; GFX10-NEXT:    s_sub_i32 s4, s4, s5
; GFX10-NEXT:    s_add_i32 s4, s4, 11
; GFX10-NEXT:  .LBB26_3: ; %frem.loop_body27
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v5, v2
; GFX10-NEXT:    s_add_i32 s4, s4, -11
; GFX10-NEXT:    s_cmp_gt_i32 s4, 11
; GFX10-NEXT:    v_mul_f32_e32 v2, v5, v3
; GFX10-NEXT:    v_rndne_f32_e32 v2, v2
; GFX10-NEXT:    v_fma_f32 v2, -v2, v1, v5
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX10-NEXT:    v_add_f32_e32 v4, v2, v1
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v2, v2, 11
; GFX10-NEXT:    s_cbranch_scc1 .LBB26_3
; GFX10-NEXT:  ; %bb.4:
; GFX10-NEXT:    v_mov_b32_e32 v4, s4
; GFX10-NEXT:    s_branch .LBB26_7
; GFX10-NEXT:  .LBB26_5: ; %frem.else20
; GFX10-NEXT:    s_and_b32 s4, 0x8000, s16
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v1, v0
; GFX10-NEXT:    v_mov_b32_e32 v0, s4
; GFX10-NEXT:    v_cndmask_b32_e32 v0, s16, v0, vcc_lo
; GFX10-NEXT:    s_branch .LBB26_8
; GFX10-NEXT:  .LBB26_6:
; GFX10-NEXT:    v_mov_b32_e32 v5, v2
; GFX10-NEXT:  .LBB26_7: ; %frem.loop_exit28
; GFX10-NEXT:    v_add_nc_u32_e32 v2, -10, v4
; GFX10-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX10-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX10-NEXT:    v_rndne_f32_e32 v3, v3
; GFX10-NEXT:    v_fma_f32 v2, -v3, v1, v2
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX10-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX10-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX10-NEXT:    v_bfi_b32 v0, 0x7fff, v0, s16
; GFX10-NEXT:  .LBB26_8:
; GFX10-NEXT:    s_lshr_b32 s4, s16, 16
; GFX10-NEXT:    s_lshr_b32 s5, s17, 16
; GFX10-NEXT:    v_cvt_f32_f16_e64 v2, |s4|
; GFX10-NEXT:    v_cvt_f32_f16_e64 v1, |s5|
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v1
; GFX10-NEXT:    s_cbranch_vccz .LBB26_13
; GFX10-NEXT:  ; %bb.9: ; %frem.compute
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v4, v2
; GFX10-NEXT:    v_frexp_mant_f32_e32 v2, v2
; GFX10-NEXT:    v_readfirstlane_b32 s6, v4
; GFX10-NEXT:    v_ldexp_f32 v3, v2, 11
; GFX10-NEXT:    v_frexp_mant_f32_e32 v2, v1
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v1, v1
; GFX10-NEXT:    v_ldexp_f32 v2, v2, 1
; GFX10-NEXT:    v_readfirstlane_b32 s7, v1
; GFX10-NEXT:    v_add_nc_u32_e32 v1, -1, v1
; GFX10-NEXT:    v_div_scale_f32 v6, s8, v2, v2, 1.0
; GFX10-NEXT:    v_not_b32_e32 v5, v1
; GFX10-NEXT:    v_rcp_f32_e32 v7, v6
; GFX10-NEXT:    v_add_nc_u32_e32 v5, v5, v4
; GFX10-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
; GFX10-NEXT:    s_denorm_mode 15
; GFX10-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
; GFX10-NEXT:    v_fmac_f32_e32 v7, v8, v7
; GFX10-NEXT:    v_mul_f32_e32 v8, v4, v7
; GFX10-NEXT:    v_fma_f32 v9, -v6, v8, v4
; GFX10-NEXT:    v_fmac_f32_e32 v8, v9, v7
; GFX10-NEXT:    v_fma_f32 v4, -v6, v8, v4
; GFX10-NEXT:    s_denorm_mode 12
; GFX10-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX10-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; GFX10-NEXT:    s_cbranch_vccnz .LBB26_14
; GFX10-NEXT:  ; %bb.10: ; %frem.loop_body.preheader
; GFX10-NEXT:    s_sub_i32 s6, s6, s7
; GFX10-NEXT:    s_add_i32 s6, s6, 11
; GFX10-NEXT:  .LBB26_11: ; %frem.loop_body
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v6, v3
; GFX10-NEXT:    s_add_i32 s6, s6, -11
; GFX10-NEXT:    s_cmp_gt_i32 s6, 11
; GFX10-NEXT:    v_mul_f32_e32 v3, v6, v4
; GFX10-NEXT:    v_rndne_f32_e32 v3, v3
; GFX10-NEXT:    v_fma_f32 v3, -v3, v2, v6
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX10-NEXT:    v_add_f32_e32 v5, v3, v2
; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v3, v3, 11
; GFX10-NEXT:    s_cbranch_scc1 .LBB26_11
; GFX10-NEXT:  ; %bb.12:
; GFX10-NEXT:    v_mov_b32_e32 v5, s6
; GFX10-NEXT:    s_branch .LBB26_15
; GFX10-NEXT:  .LBB26_13: ; %frem.else
; GFX10-NEXT:    s_and_b32 s6, 0x8000, s4
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v2, v1
; GFX10-NEXT:    v_mov_b32_e32 v1, s6
; GFX10-NEXT:    v_cndmask_b32_e32 v1, s4, v1, vcc_lo
; GFX10-NEXT:    s_branch .LBB26_16
; GFX10-NEXT:  .LBB26_14:
; GFX10-NEXT:    v_mov_b32_e32 v6, v3
; GFX10-NEXT:  .LBB26_15: ; %frem.loop_exit
; GFX10-NEXT:    v_add_nc_u32_e32 v3, -10, v5
; GFX10-NEXT:    v_ldexp_f32 v3, v6, v3
; GFX10-NEXT:    v_mul_f32_e32 v4, v3, v4
; GFX10-NEXT:    v_rndne_f32_e32 v4, v4
; GFX10-NEXT:    v_fma_f32 v3, -v4, v2, v3
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX10-NEXT:    v_add_f32_e32 v2, v3, v2
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v1, v2, v1
; GFX10-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX10-NEXT:    v_bfi_b32 v1, 0x7fff, v1, s4
; GFX10-NEXT:  .LBB26_16:
; GFX10-NEXT:    v_cmp_lg_f16_e64 s6, s17, 0
; GFX10-NEXT:    v_cmp_nge_f16_e64 s7, |s16|, 0x7c00
; GFX10-NEXT:    v_cmp_lg_f16_e64 s5, s5, 0
; GFX10-NEXT:    v_cmp_nge_f16_e64 s4, |s4|, 0x7c00
; GFX10-NEXT:    v_mov_b32_e32 v2, 0x7e00
; GFX10-NEXT:    s_and_b32 vcc_lo, s7, s6
; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v0, vcc_lo
; GFX10-NEXT:    s_and_b32 vcc_lo, s4, s5
; GFX10-NEXT:    v_cndmask_b32_sdwa v1, v2, v1, vcc_lo dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: frem_v2f16_uniform:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v1, |s0|
; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v0, |s1|
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v0
; GFX11-TRUE16-NEXT:    s_cbranch_vccz .LBB26_5
; GFX11-TRUE16-NEXT:  ; %bb.1: ; %frem.compute19
; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, v1
; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v1, v1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s2, v3
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v2, v1, 11
; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v1, v0
; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s3, v0
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v0, -1, v0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX11-TRUE16-NEXT:    v_not_b32_e32 v4, v0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v6, v5
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v4, v4, v3
; GFX11-TRUE16-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX11-TRUE16-NEXT:    s_denorm_mode 15
; GFX11-TRUE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v6, v7, v6
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v7, v3, v6
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v8, -v5, v7, v3
; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v7, v8, v6
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v3, -v5, v7, v3
; GFX11-TRUE16-NEXT:    s_denorm_mode 12
; GFX11-TRUE16-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
; GFX11-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB26_6
; GFX11-TRUE16-NEXT:  ; %bb.2: ; %frem.loop_body27.preheader
; GFX11-TRUE16-NEXT:    s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT:    s_add_i32 s2, s2, 11
; GFX11-TRUE16-NEXT:  .LBB26_3: ; %frem.loop_body27
; GFX11-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX11-TRUE16-NEXT:    s_add_i32 s2, s2, -11
; GFX11-TRUE16-NEXT:    s_cmp_gt_i32 s2, 11
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v2, v5, v3
; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v2, v2
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v2, -v2, v1, v5
; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX11-TRUE16-NEXT:    v_add_f32_e32 v4, v2, v1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v2, v2, 11
; GFX11-TRUE16-NEXT:    s_cbranch_scc1 .LBB26_3
; GFX11-TRUE16-NEXT:  ; %bb.4:
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v4, s2
; GFX11-TRUE16-NEXT:    s_branch .LBB26_7
; GFX11-TRUE16-NEXT:  .LBB26_5: ; %frem.else20
; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0x8000, s0
; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v1, v0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, s0, v2.l, vcc_lo
; GFX11-TRUE16-NEXT:    s_branch .LBB26_8
; GFX11-TRUE16-NEXT:  .LBB26_6:
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX11-TRUE16-NEXT:  .LBB26_7: ; %frem.loop_exit28
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, -10, v4
; GFX11-TRUE16-NEXT:    s_and_b32 s2, s0, 0x8000
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v3, v3
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v2, -v3, v1, v2
; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX11-TRUE16-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, s2, v0
; GFX11-TRUE16-NEXT:  .LBB26_8:
; GFX11-TRUE16-NEXT:    s_lshr_b32 s2, s0, 16
; GFX11-TRUE16-NEXT:    s_lshr_b32 s3, s1, 16
; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v2, |s2|
; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v1, |s3|
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v1
; GFX11-TRUE16-NEXT:    s_cbranch_vccz .LBB26_13
; GFX11-TRUE16-NEXT:  ; %bb.9: ; %frem.compute
; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v4, v2
; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v2, v2
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s4, v4
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v3, v2, 11
; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v2, v1
; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v1, v1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v2, v2, 1
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s5, v1
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v1, -1, v1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_div_scale_f32 v6, null, v2, v2, 1.0
; GFX11-TRUE16-NEXT:    v_not_b32_e32 v5, v1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v7, v6
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
; GFX11-TRUE16-NEXT:    s_denorm_mode 15
; GFX11-TRUE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v7, v8, v7
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v8, v4, v7
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v9, -v6, v8, v4
; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v8, v9, v7
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v4, -v6, v8, v4
; GFX11-TRUE16-NEXT:    s_denorm_mode 12
; GFX11-TRUE16-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
; GFX11-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB26_14
; GFX11-TRUE16-NEXT:  ; %bb.10: ; %frem.loop_body.preheader
; GFX11-TRUE16-NEXT:    s_sub_i32 s4, s4, s5
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT:    s_add_i32 s4, s4, 11
; GFX11-TRUE16-NEXT:  .LBB26_11: ; %frem.loop_body
; GFX11-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT:    s_add_i32 s4, s4, -11
; GFX11-TRUE16-NEXT:    s_cmp_gt_i32 s4, 11
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v3, v6, v4
; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v3, v3
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v3, -v3, v2, v6
; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX11-TRUE16-NEXT:    v_add_f32_e32 v5, v3, v2
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v3, v3, 11
; GFX11-TRUE16-NEXT:    s_cbranch_scc1 .LBB26_11
; GFX11-TRUE16-NEXT:  ; %bb.12:
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v5, s4
; GFX11-TRUE16-NEXT:    s_branch .LBB26_15
; GFX11-TRUE16-NEXT:  .LBB26_13: ; %frem.else
; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0x8000, s2
; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v2, v1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, s2, v0.h, vcc_lo
; GFX11-TRUE16-NEXT:    s_branch .LBB26_16
; GFX11-TRUE16-NEXT:  .LBB26_14:
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT:  .LBB26_15: ; %frem.loop_exit
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v3, -10, v5
; GFX11-TRUE16-NEXT:    s_and_b32 s4, s2, 0x8000
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v3, v6, v3
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v4, v3, v4
; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v4, v4
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v3, -v4, v2, v3
; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, v3, v2
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v1, v2, v1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v1.l, v1
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, s4, v1
; GFX11-TRUE16-NEXT:  .LBB26_16:
; GFX11-TRUE16-NEXT:    v_cmp_lg_f16_e64 s1, s1, 0
; GFX11-TRUE16-NEXT:    v_cmp_nge_f16_e64 s0, |s0|, 0x7c00
; GFX11-TRUE16-NEXT:    s_and_b32 s0, s0, s1
; GFX11-TRUE16-NEXT:    v_cmp_nge_f16_e64 s1, |s2|, 0x7c00
; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, s0
; GFX11-TRUE16-NEXT:    v_cmp_lg_f16_e64 s0, s3, 0
; GFX11-TRUE16-NEXT:    s_and_b32 s0, s1, s0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, 0x7e00, v1.l, s0
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: frem_v2f16_uniform:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v1, |s0|
; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v0, |s1|
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v0
; GFX11-FAKE16-NEXT:    s_cbranch_vccz .LBB26_5
; GFX11-FAKE16-NEXT:  ; %bb.1: ; %frem.compute19
; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, v1
; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v1, v1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s2, v3
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v2, v1, 11
; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v1, v0
; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s3, v0
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v0, -1, v0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX11-FAKE16-NEXT:    v_not_b32_e32 v4, v0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v6, v5
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, v4, v3
; GFX11-FAKE16-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX11-FAKE16-NEXT:    s_denorm_mode 15
; GFX11-FAKE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v6, v7, v6
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v7, v3, v6
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v8, -v5, v7, v3
; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v7, v8, v6
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v3, -v5, v7, v3
; GFX11-FAKE16-NEXT:    s_denorm_mode 12
; GFX11-FAKE16-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
; GFX11-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB26_6
; GFX11-FAKE16-NEXT:  ; %bb.2: ; %frem.loop_body27.preheader
; GFX11-FAKE16-NEXT:    s_sub_i32 s2, s2, s3
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT:    s_add_i32 s2, s2, 11
; GFX11-FAKE16-NEXT:  .LBB26_3: ; %frem.loop_body27
; GFX11-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX11-FAKE16-NEXT:    s_add_i32 s2, s2, -11
; GFX11-FAKE16-NEXT:    s_cmp_gt_i32 s2, 11
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v2, v5, v3
; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v2, v2
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v2, -v2, v1, v5
; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX11-FAKE16-NEXT:    v_add_f32_e32 v4, v2, v1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v2, v2, 11
; GFX11-FAKE16-NEXT:    s_cbranch_scc1 .LBB26_3
; GFX11-FAKE16-NEXT:  ; %bb.4:
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, s2
; GFX11-FAKE16-NEXT:    s_branch .LBB26_7
; GFX11-FAKE16-NEXT:  .LBB26_5: ; %frem.else20
; GFX11-FAKE16-NEXT:    s_and_b32 s2, 0x8000, s0
; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v1, v0
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, s2
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, s0, v0, vcc_lo
; GFX11-FAKE16-NEXT:    s_branch .LBB26_8
; GFX11-FAKE16-NEXT:  .LBB26_6:
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX11-FAKE16-NEXT:  .LBB26_7: ; %frem.loop_exit28
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v2, -10, v4
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v3, v3
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v2, -v3, v1, v2
; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX11-FAKE16-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX11-FAKE16-NEXT:    v_bfi_b32 v0, 0x7fff, v0, s0
; GFX11-FAKE16-NEXT:  .LBB26_8:
; GFX11-FAKE16-NEXT:    s_lshr_b32 s2, s0, 16
; GFX11-FAKE16-NEXT:    s_lshr_b32 s3, s1, 16
; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v2, |s2|
; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v1, |s3|
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v1
; GFX11-FAKE16-NEXT:    s_cbranch_vccz .LBB26_13
; GFX11-FAKE16-NEXT:  ; %bb.9: ; %frem.compute
; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v4, v2
; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v2, v2
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s4, v4
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v3, v2, 11
; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v2, v1
; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v1, v1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v2, v2, 1
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s5, v1
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v1, -1, v1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_div_scale_f32 v6, null, v2, v2, 1.0
; GFX11-FAKE16-NEXT:    v_not_b32_e32 v5, v1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v7, v6
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v5, v5, v4
; GFX11-FAKE16-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
; GFX11-FAKE16-NEXT:    s_denorm_mode 15
; GFX11-FAKE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v8, v4, v7
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v9, -v6, v8, v4
; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v8, v9, v7
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v4, -v6, v8, v4
; GFX11-FAKE16-NEXT:    s_denorm_mode 12
; GFX11-FAKE16-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
; GFX11-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB26_14
; GFX11-FAKE16-NEXT:  ; %bb.10: ; %frem.loop_body.preheader
; GFX11-FAKE16-NEXT:    s_sub_i32 s4, s4, s5
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT:    s_add_i32 s4, s4, 11
; GFX11-FAKE16-NEXT:  .LBB26_11: ; %frem.loop_body
; GFX11-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v6, v3
; GFX11-FAKE16-NEXT:    s_add_i32 s4, s4, -11
; GFX11-FAKE16-NEXT:    s_cmp_gt_i32 s4, 11
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v3, v6, v4
; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v3, v3
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v3, -v3, v2, v6
; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX11-FAKE16-NEXT:    v_add_f32_e32 v5, v3, v2
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v3, v3, 11
; GFX11-FAKE16-NEXT:    s_cbranch_scc1 .LBB26_11
; GFX11-FAKE16-NEXT:  ; %bb.12:
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, s4
; GFX11-FAKE16-NEXT:    s_branch .LBB26_15
; GFX11-FAKE16-NEXT:  .LBB26_13: ; %frem.else
; GFX11-FAKE16-NEXT:    s_and_b32 s4, 0x8000, s2
; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v2, v1
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, s4
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, s2, v1, vcc_lo
; GFX11-FAKE16-NEXT:    s_branch .LBB26_16
; GFX11-FAKE16-NEXT:  .LBB26_14:
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v6, v3
; GFX11-FAKE16-NEXT:  .LBB26_15: ; %frem.loop_exit
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v3, -10, v5
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v3, v6, v3
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v4, v3, v4
; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v4, v4
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v3, -v4, v2, v3
; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX11-FAKE16-NEXT:    v_add_f32_e32 v2, v3, v2
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v1, v2, v1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX11-FAKE16-NEXT:    v_bfi_b32 v1, 0x7fff, v1, s2
; GFX11-FAKE16-NEXT:  .LBB26_16:
; GFX11-FAKE16-NEXT:    v_cmp_lg_f16_e64 s1, s1, 0
; GFX11-FAKE16-NEXT:    v_cmp_nge_f16_e64 s0, |s0|, 0x7c00
; GFX11-FAKE16-NEXT:    s_and_b32 vcc_lo, s0, s1
; GFX11-FAKE16-NEXT:    v_cmp_lg_f16_e64 s0, s3, 0
; GFX11-FAKE16-NEXT:    v_cmp_nge_f16_e64 s1, |s2|, 0x7c00
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v0, vcc_lo
; GFX11-FAKE16-NEXT:    s_and_b32 vcc_lo, s1, s0
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x7e00, v1, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-TRUE16-LABEL: frem_v2f16_uniform:
; GFX1150-TRUE16:       ; %bb.0:
; GFX1150-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-TRUE16-NEXT:    s_and_b32 s2, s0, 0x7fff
; GFX1150-TRUE16-NEXT:    s_and_b32 s4, s1, 0x7fff
; GFX1150-TRUE16-NEXT:    s_cvt_f32_f16 s3, s2
; GFX1150-TRUE16-NEXT:    s_cvt_f32_f16 s4, s4
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
; GFX1150-TRUE16-NEXT:    s_cmp_gt_f32 s3, s4
; GFX1150-TRUE16-NEXT:    s_cbranch_scc0 .LBB26_5
; GFX1150-TRUE16-NEXT:  ; %bb.1: ; %frem.compute19
; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v1, s4
; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v0, s3
; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, s3
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v2, v0, 11
; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v0, s4
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s3, v3
; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s4, v0
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v0, -1, v0
; GFX1150-TRUE16-NEXT:    v_rcp_f32_e32 v6, v5
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_not_b32_e32 v4, v0
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v4, v4, v3
; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX1150-TRUE16-NEXT:    s_denorm_mode 15
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v6, v7, v6
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v7, v3, v6
; GFX1150-TRUE16-NEXT:    v_fma_f32 v8, -v5, v7, v3
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v7, v8, v6
; GFX1150-TRUE16-NEXT:    v_fma_f32 v3, -v5, v7, v3
; GFX1150-TRUE16-NEXT:    s_denorm_mode 12
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-TRUE16-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
; GFX1150-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1150-TRUE16-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX1150-TRUE16-NEXT:    s_cbranch_vccnz .LBB26_6
; GFX1150-TRUE16-NEXT:  ; %bb.2: ; %frem.loop_body27.preheader
; GFX1150-TRUE16-NEXT:    s_sub_i32 s3, s3, s4
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    s_add_i32 s3, s3, 11
; GFX1150-TRUE16-NEXT:  .LBB26_3: ; %frem.loop_body27
; GFX1150-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX1150-TRUE16-NEXT:    s_add_i32 s3, s3, -11
; GFX1150-TRUE16-NEXT:    s_cmp_gt_i32 s3, 11
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v2, v5, v3
; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v2, v2
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v2, 0x80000000, v2
; GFX1150-TRUE16-NEXT:    v_fma_f32 v2, v2, v1, v5
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v4, v2, v1
; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v2, v2, 11
; GFX1150-TRUE16-NEXT:    s_cbranch_scc1 .LBB26_3
; GFX1150-TRUE16-NEXT:  ; %bb.4:
; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v4, s3
; GFX1150-TRUE16-NEXT:    s_branch .LBB26_7
; GFX1150-TRUE16-NEXT:  .LBB26_5: ; %frem.else20
; GFX1150-TRUE16-NEXT:    s_cmp_eq_f32 s3, s4
; GFX1150-TRUE16-NEXT:    v_and_b16 v0.l, 0x8000, s0
; GFX1150-TRUE16-NEXT:    s_cselect_b32 s3, -1, 0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v0.l, s0, v0.l, s3
; GFX1150-TRUE16-NEXT:    s_branch .LBB26_8
; GFX1150-TRUE16-NEXT:  .LBB26_6:
; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX1150-TRUE16-NEXT:  .LBB26_7: ; %frem.loop_exit28
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v2, -10, v4
; GFX1150-TRUE16-NEXT:    s_and_b32 s3, s0, 0x8000
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v3, v3
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v2, v3, v1
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX1150-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_and_b32_e32 v0, 0x7fff, v0
; GFX1150-TRUE16-NEXT:    v_or_b32_e32 v0, s3, v0
; GFX1150-TRUE16-NEXT:  .LBB26_8:
; GFX1150-TRUE16-NEXT:    s_lshr_b32 s4, s0, 16
; GFX1150-TRUE16-NEXT:    s_lshr_b32 s3, s1, 16
; GFX1150-TRUE16-NEXT:    s_and_b32 s0, s4, 0x7fff
; GFX1150-TRUE16-NEXT:    s_and_b32 s6, s3, 0x7fff
; GFX1150-TRUE16-NEXT:    s_cvt_f32_f16 s5, s0
; GFX1150-TRUE16-NEXT:    s_cvt_f32_f16 s6, s6
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
; GFX1150-TRUE16-NEXT:    s_cmp_gt_f32 s5, s6
; GFX1150-TRUE16-NEXT:    s_cbranch_scc0 .LBB26_13
; GFX1150-TRUE16-NEXT:  ; %bb.9: ; %frem.compute
; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v2, s6
; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v1, s5
; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v4, s5
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v2, v2, 1
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v3, v1, 11
; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v1, s6
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s5, v4
; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v6, null, v2, v2, 1.0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s6, v1
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v1, -1, v1
; GFX1150-TRUE16-NEXT:    v_rcp_f32_e32 v7, v6
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_not_b32_e32 v5, v1
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v5, v5, v4
; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
; GFX1150-TRUE16-NEXT:    s_denorm_mode 15
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v7, v8, v7
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v8, v4, v7
; GFX1150-TRUE16-NEXT:    v_fma_f32 v9, -v6, v8, v4
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v8, v9, v7
; GFX1150-TRUE16-NEXT:    v_fma_f32 v4, -v6, v8, v4
; GFX1150-TRUE16-NEXT:    s_denorm_mode 12
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-TRUE16-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
; GFX1150-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX1150-TRUE16-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; GFX1150-TRUE16-NEXT:    s_cbranch_vccnz .LBB26_14
; GFX1150-TRUE16-NEXT:  ; %bb.10: ; %frem.loop_body.preheader
; GFX1150-TRUE16-NEXT:    s_sub_i32 s5, s5, s6
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    s_add_i32 s5, s5, 11
; GFX1150-TRUE16-NEXT:  .LBB26_11: ; %frem.loop_body
; GFX1150-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v6, v3
; GFX1150-TRUE16-NEXT:    s_add_i32 s5, s5, -11
; GFX1150-TRUE16-NEXT:    s_cmp_gt_i32 s5, 11
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v3, v6, v4
; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v3, v3
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
; GFX1150-TRUE16-NEXT:    v_fma_f32 v3, v3, v2, v6
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v5, v3, v2
; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v3, v3, 11
; GFX1150-TRUE16-NEXT:    s_cbranch_scc1 .LBB26_11
; GFX1150-TRUE16-NEXT:  ; %bb.12:
; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v5, s5
; GFX1150-TRUE16-NEXT:    s_branch .LBB26_15
; GFX1150-TRUE16-NEXT:  .LBB26_13: ; %frem.else
; GFX1150-TRUE16-NEXT:    s_cmp_eq_f32 s5, s6
; GFX1150-TRUE16-NEXT:    v_and_b16 v0.h, 0x8000, s4
; GFX1150-TRUE16-NEXT:    s_cselect_b32 s5, -1, 0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v1.l, s4, v0.h, s5
; GFX1150-TRUE16-NEXT:    s_branch .LBB26_16
; GFX1150-TRUE16-NEXT:  .LBB26_14:
; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v6, v3
; GFX1150-TRUE16-NEXT:  .LBB26_15: ; %frem.loop_exit
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v3, -10, v5
; GFX1150-TRUE16-NEXT:    s_and_b32 s4, s4, 0x8000
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v3, v6, v3
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v4, v3, v4
; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v4, v4
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v3, v4, v2
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v2, v3, v2
; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v1, v2, v1
; GFX1150-TRUE16-NEXT:    v_cvt_f16_f32_e32 v1.l, v1
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_and_b32_e32 v1, 0x7fff, v1
; GFX1150-TRUE16-NEXT:    v_or_b32_e32 v1, s4, v1
; GFX1150-TRUE16-NEXT:  .LBB26_16:
; GFX1150-TRUE16-NEXT:    s_cmp_lg_f16 s1, 0
; GFX1150-TRUE16-NEXT:    s_cselect_b32 s1, -1, 0
; GFX1150-TRUE16-NEXT:    s_cmp_nge_f16 s2, 0x7c00
; GFX1150-TRUE16-NEXT:    s_cselect_b32 s2, -1, 0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    s_and_b32 s1, s2, s1
; GFX1150-TRUE16-NEXT:    s_cmp_lg_f16 s3, 0
; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, s1
; GFX1150-TRUE16-NEXT:    s_cselect_b32 s1, -1, 0
; GFX1150-TRUE16-NEXT:    s_cmp_nge_f16 s0, 0x7c00
; GFX1150-TRUE16-NEXT:    s_cselect_b32 s0, -1, 0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    s_and_b32 s0, s0, s1
; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v0.h, 0x7e00, v1.l, s0
; GFX1150-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-FAKE16-LABEL: frem_v2f16_uniform:
; GFX1150-FAKE16:       ; %bb.0:
; GFX1150-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-FAKE16-NEXT:    s_and_b32 s2, s0, 0x7fff
; GFX1150-FAKE16-NEXT:    s_and_b32 s4, s1, 0x7fff
; GFX1150-FAKE16-NEXT:    s_cvt_f32_f16 s3, s2
; GFX1150-FAKE16-NEXT:    s_cvt_f32_f16 s4, s4
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
; GFX1150-FAKE16-NEXT:    s_cmp_gt_f32 s3, s4
; GFX1150-FAKE16-NEXT:    s_cbranch_scc0 .LBB26_5
; GFX1150-FAKE16-NEXT:  ; %bb.1: ; %frem.compute19
; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v1, s4
; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v0, s3
; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, s3
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v2, v0, 11
; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v0, s4
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s3, v3
; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s4, v0
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v0, -1, v0
; GFX1150-FAKE16-NEXT:    v_rcp_f32_e32 v6, v5
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_not_b32_e32 v4, v0
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v4, v4, v3
; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX1150-FAKE16-NEXT:    s_denorm_mode 15
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v6, v7, v6
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v7, v3, v6
; GFX1150-FAKE16-NEXT:    v_fma_f32 v8, -v5, v7, v3
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v7, v8, v6
; GFX1150-FAKE16-NEXT:    v_fma_f32 v3, -v5, v7, v3
; GFX1150-FAKE16-NEXT:    s_denorm_mode 12
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-FAKE16-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
; GFX1150-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1150-FAKE16-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX1150-FAKE16-NEXT:    s_cbranch_vccnz .LBB26_6
; GFX1150-FAKE16-NEXT:  ; %bb.2: ; %frem.loop_body27.preheader
; GFX1150-FAKE16-NEXT:    s_sub_i32 s3, s3, s4
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT:    s_add_i32 s3, s3, 11
; GFX1150-FAKE16-NEXT:  .LBB26_3: ; %frem.loop_body27
; GFX1150-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX1150-FAKE16-NEXT:    s_add_i32 s3, s3, -11
; GFX1150-FAKE16-NEXT:    s_cmp_gt_i32 s3, 11
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v2, v5, v3
; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v2, v2
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v2, 0x80000000, v2
; GFX1150-FAKE16-NEXT:    v_fma_f32 v2, v2, v1, v5
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v4, v2, v1
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v2, v2, 11
; GFX1150-FAKE16-NEXT:    s_cbranch_scc1 .LBB26_3
; GFX1150-FAKE16-NEXT:  ; %bb.4:
; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v4, s3
; GFX1150-FAKE16-NEXT:    s_branch .LBB26_7
; GFX1150-FAKE16-NEXT:  .LBB26_5: ; %frem.else20
; GFX1150-FAKE16-NEXT:    s_and_b32 s5, 0x8000, s0
; GFX1150-FAKE16-NEXT:    s_cmp_eq_f32 s3, s4
; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v0, s5
; GFX1150-FAKE16-NEXT:    s_cselect_b32 vcc_lo, -1, 0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v0, s0, v0, vcc_lo
; GFX1150-FAKE16-NEXT:    s_branch .LBB26_8
; GFX1150-FAKE16-NEXT:  .LBB26_6:
; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX1150-FAKE16-NEXT:  .LBB26_7: ; %frem.loop_exit28
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v2, -10, v4
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v3, v3
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v2, v3, v1
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX1150-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_bfi_b32 v0, 0x7fff, v0, s0
; GFX1150-FAKE16-NEXT:  .LBB26_8:
; GFX1150-FAKE16-NEXT:    s_lshr_b32 s4, s0, 16
; GFX1150-FAKE16-NEXT:    s_lshr_b32 s3, s1, 16
; GFX1150-FAKE16-NEXT:    s_and_b32 s0, s4, 0x7fff
; GFX1150-FAKE16-NEXT:    s_and_b32 s6, s3, 0x7fff
; GFX1150-FAKE16-NEXT:    s_cvt_f32_f16 s5, s0
; GFX1150-FAKE16-NEXT:    s_cvt_f32_f16 s6, s6
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
; GFX1150-FAKE16-NEXT:    s_cmp_gt_f32 s5, s6
; GFX1150-FAKE16-NEXT:    s_cbranch_scc0 .LBB26_13
; GFX1150-FAKE16-NEXT:  ; %bb.9: ; %frem.compute
; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v2, s6
; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v1, s5
; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v4, s5
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v2, v2, 1
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v3, v1, 11
; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v1, s6
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s5, v4
; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v6, null, v2, v2, 1.0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s6, v1
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v1, -1, v1
; GFX1150-FAKE16-NEXT:    v_rcp_f32_e32 v7, v6
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_not_b32_e32 v5, v1
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v5, v5, v4
; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
; GFX1150-FAKE16-NEXT:    s_denorm_mode 15
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v7, v8, v7
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v8, v4, v7
; GFX1150-FAKE16-NEXT:    v_fma_f32 v9, -v6, v8, v4
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v8, v9, v7
; GFX1150-FAKE16-NEXT:    v_fma_f32 v4, -v6, v8, v4
; GFX1150-FAKE16-NEXT:    s_denorm_mode 12
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-FAKE16-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
; GFX1150-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX1150-FAKE16-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; GFX1150-FAKE16-NEXT:    s_cbranch_vccnz .LBB26_14
; GFX1150-FAKE16-NEXT:  ; %bb.10: ; %frem.loop_body.preheader
; GFX1150-FAKE16-NEXT:    s_sub_i32 s5, s5, s6
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT:    s_add_i32 s5, s5, 11
; GFX1150-FAKE16-NEXT:  .LBB26_11: ; %frem.loop_body
; GFX1150-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v6, v3
; GFX1150-FAKE16-NEXT:    s_add_i32 s5, s5, -11
; GFX1150-FAKE16-NEXT:    s_cmp_gt_i32 s5, 11
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v3, v6, v4
; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v3, v3
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
; GFX1150-FAKE16-NEXT:    v_fma_f32 v3, v3, v2, v6
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v5, v3, v2
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v3, v3, 11
; GFX1150-FAKE16-NEXT:    s_cbranch_scc1 .LBB26_11
; GFX1150-FAKE16-NEXT:  ; %bb.12:
; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v5, s5
; GFX1150-FAKE16-NEXT:    s_branch .LBB26_15
; GFX1150-FAKE16-NEXT:  .LBB26_13: ; %frem.else
; GFX1150-FAKE16-NEXT:    s_and_b32 s7, 0x8000, s4
; GFX1150-FAKE16-NEXT:    s_cmp_eq_f32 s5, s6
; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v1, s7
; GFX1150-FAKE16-NEXT:    s_cselect_b32 vcc_lo, -1, 0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v1, s4, v1, vcc_lo
; GFX1150-FAKE16-NEXT:    s_branch .LBB26_16
; GFX1150-FAKE16-NEXT:  .LBB26_14:
; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v6, v3
; GFX1150-FAKE16-NEXT:  .LBB26_15: ; %frem.loop_exit
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v3, -10, v5
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v3, v6, v3
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v4, v3, v4
; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v4, v4
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v3, v4, v2
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v2, v3, v2
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v1, v2, v1
; GFX1150-FAKE16-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_bfi_b32 v1, 0x7fff, v1, s4
; GFX1150-FAKE16-NEXT:  .LBB26_16:
; GFX1150-FAKE16-NEXT:    s_cmp_lg_f16 s1, 0
; GFX1150-FAKE16-NEXT:    s_cselect_b32 s1, -1, 0
; GFX1150-FAKE16-NEXT:    s_cmp_nge_f16 s2, 0x7c00
; GFX1150-FAKE16-NEXT:    s_cselect_b32 s2, -1, 0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT:    s_and_b32 vcc_lo, s2, s1
; GFX1150-FAKE16-NEXT:    s_cmp_lg_f16 s3, 0
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v0, vcc_lo
; GFX1150-FAKE16-NEXT:    s_cselect_b32 s1, -1, 0
; GFX1150-FAKE16-NEXT:    s_cmp_nge_f16 s0, 0x7c00
; GFX1150-FAKE16-NEXT:    s_cselect_b32 s0, -1, 0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    s_and_b32 vcc_lo, s0, s1
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x7e00, v1, vcc_lo
; GFX1150-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; GFX1150-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
; GFX1150-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-TRUE16-LABEL: frem_v2f16_uniform:
; GFX1200-TRUE16:       ; %bb.0:
; GFX1200-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1200-TRUE16-NEXT:    s_and_b32 s2, s0, 0x7fff
; GFX1200-TRUE16-NEXT:    s_and_b32 s4, s1, 0x7fff
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_cvt_f32_f16 s3, s2
; GFX1200-TRUE16-NEXT:    s_cvt_f32_f16 s4, s4
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_2)
; GFX1200-TRUE16-NEXT:    s_cmp_gt_f32 s3, s4
; GFX1200-TRUE16-NEXT:    s_cbranch_scc0 .LBB26_5
; GFX1200-TRUE16-NEXT:  ; %bb.1: ; %frem.compute19
; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v1, s4
; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v0, s3
; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, s3
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v2, v0, 11
; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v0, s4
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s3, v3
; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s4, v0
; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v0, -1, v0
; GFX1200-TRUE16-NEXT:    v_rcp_f32_e32 v6, v5
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_not_b32_e32 v4, v0
; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v4, v4, v3
; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX1200-TRUE16-NEXT:    s_denorm_mode 15
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v6, v7, v6
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v7, v3, v6
; GFX1200-TRUE16-NEXT:    v_fma_f32 v8, -v5, v7, v3
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v7, v8, v6
; GFX1200-TRUE16-NEXT:    v_fma_f32 v3, -v5, v7, v3
; GFX1200-TRUE16-NEXT:    s_denorm_mode 12
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
; GFX1200-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1200-TRUE16-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX1200-TRUE16-NEXT:    s_cbranch_vccnz .LBB26_6
; GFX1200-TRUE16-NEXT:  ; %bb.2: ; %frem.loop_body27.preheader
; GFX1200-TRUE16-NEXT:    s_sub_co_i32 s3, s3, s4
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_add_co_i32 s3, s3, 11
; GFX1200-TRUE16-NEXT:  .LBB26_3: ; %frem.loop_body27
; GFX1200-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_add_co_i32 s3, s3, -11
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_cmp_gt_i32 s3, 11
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v2, v5, v3
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v2, v2
; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v2, 0x80000000, v2
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f32 v2, v2, v1, v5
; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v4, v2, v1
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v2, v2, 11
; GFX1200-TRUE16-NEXT:    s_cbranch_scc1 .LBB26_3
; GFX1200-TRUE16-NEXT:  ; %bb.4:
; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v4, s3
; GFX1200-TRUE16-NEXT:    s_branch .LBB26_7
; GFX1200-TRUE16-NEXT:  .LBB26_5: ; %frem.else20
; GFX1200-TRUE16-NEXT:    s_cmp_eq_f32 s3, s4
; GFX1200-TRUE16-NEXT:    v_and_b16 v0.l, 0x8000, s0
; GFX1200-TRUE16-NEXT:    s_cselect_b32 s3, -1, 0
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v0.l, s0, v0.l, s3
; GFX1200-TRUE16-NEXT:    s_branch .LBB26_8
; GFX1200-TRUE16-NEXT:  .LBB26_6:
; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX1200-TRUE16-NEXT:  .LBB26_7: ; %frem.loop_exit28
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v2, -10, v4
; GFX1200-TRUE16-NEXT:    s_and_b32 s3, s0, 0x8000
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v3, v3
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v2, v3, v1
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX1200-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_and_b32_e32 v0, 0x7fff, v0
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    v_or_b32_e32 v0, s3, v0
; GFX1200-TRUE16-NEXT:  .LBB26_8:
; GFX1200-TRUE16-NEXT:    s_lshr_b32 s4, s0, 16
; GFX1200-TRUE16-NEXT:    s_lshr_b32 s3, s1, 16
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_and_b32 s0, s4, 0x7fff
; GFX1200-TRUE16-NEXT:    s_and_b32 s6, s3, 0x7fff
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_cvt_f32_f16 s5, s0
; GFX1200-TRUE16-NEXT:    s_cvt_f32_f16 s6, s6
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_2)
; GFX1200-TRUE16-NEXT:    s_cmp_gt_f32 s5, s6
; GFX1200-TRUE16-NEXT:    s_cbranch_scc0 .LBB26_13
; GFX1200-TRUE16-NEXT:  ; %bb.9: ; %frem.compute
; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v2, s6
; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v1, s5
; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v4, s5
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v2, v2, 1
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v3, v1, 11
; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v1, s6
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s5, v4
; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v6, null, v2, v2, 1.0
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s6, v1
; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v1, -1, v1
; GFX1200-TRUE16-NEXT:    v_rcp_f32_e32 v7, v6
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_not_b32_e32 v5, v1
; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v5, v5, v4
; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
; GFX1200-TRUE16-NEXT:    s_denorm_mode 15
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v7, v8, v7
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v8, v4, v7
; GFX1200-TRUE16-NEXT:    v_fma_f32 v9, -v6, v8, v4
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v8, v9, v7
; GFX1200-TRUE16-NEXT:    v_fma_f32 v4, -v6, v8, v4
; GFX1200-TRUE16-NEXT:    s_denorm_mode 12
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
; GFX1200-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX1200-TRUE16-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; GFX1200-TRUE16-NEXT:    s_cbranch_vccnz .LBB26_14
; GFX1200-TRUE16-NEXT:  ; %bb.10: ; %frem.loop_body.preheader
; GFX1200-TRUE16-NEXT:    s_sub_co_i32 s5, s5, s6
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_add_co_i32 s5, s5, 11
; GFX1200-TRUE16-NEXT:  .LBB26_11: ; %frem.loop_body
; GFX1200-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v6, v3
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_add_co_i32 s5, s5, -11
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_cmp_gt_i32 s5, 11
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v3, v6, v4
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v3, v3
; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f32 v3, v3, v2, v6
; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v5, v3, v2
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v3, v3, 11
; GFX1200-TRUE16-NEXT:    s_cbranch_scc1 .LBB26_11
; GFX1200-TRUE16-NEXT:  ; %bb.12:
; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v5, s5
; GFX1200-TRUE16-NEXT:    s_branch .LBB26_15
; GFX1200-TRUE16-NEXT:  .LBB26_13: ; %frem.else
; GFX1200-TRUE16-NEXT:    s_cmp_eq_f32 s5, s6
; GFX1200-TRUE16-NEXT:    v_and_b16 v0.h, 0x8000, s4
; GFX1200-TRUE16-NEXT:    s_cselect_b32 s5, -1, 0
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v1.l, s4, v0.h, s5
; GFX1200-TRUE16-NEXT:    s_branch .LBB26_16
; GFX1200-TRUE16-NEXT:  .LBB26_14:
; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v6, v3
; GFX1200-TRUE16-NEXT:  .LBB26_15: ; %frem.loop_exit
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v3, -10, v5
; GFX1200-TRUE16-NEXT:    s_and_b32 s4, s4, 0x8000
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v3, v6, v3
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v4, v3, v4
; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v4, v4
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v3, v4, v2
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v2, v3, v2
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v1, v2, v1
; GFX1200-TRUE16-NEXT:    v_cvt_f16_f32_e32 v1.l, v1
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_and_b32_e32 v1, 0x7fff, v1
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    v_or_b32_e32 v1, s4, v1
; GFX1200-TRUE16-NEXT:  .LBB26_16:
; GFX1200-TRUE16-NEXT:    s_cmp_lg_f16 s1, 0
; GFX1200-TRUE16-NEXT:    s_cselect_b32 s1, -1, 0
; GFX1200-TRUE16-NEXT:    s_cmp_nge_f16 s2, 0x7c00
; GFX1200-TRUE16-NEXT:    s_cselect_b32 s2, -1, 0
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_and_b32 s1, s2, s1
; GFX1200-TRUE16-NEXT:    s_cmp_lg_f16 s3, 0
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, s1
; GFX1200-TRUE16-NEXT:    s_cselect_b32 s1, -1, 0
; GFX1200-TRUE16-NEXT:    s_cmp_nge_f16 s0, 0x7c00
; GFX1200-TRUE16-NEXT:    s_cselect_b32 s0, -1, 0
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_and_b32 s0, s0, s1
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v0.h, 0x7e00, v1.l, s0
; GFX1200-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-FAKE16-LABEL: frem_v2f16_uniform:
; GFX1200-FAKE16:       ; %bb.0:
; GFX1200-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1200-FAKE16-NEXT:    s_and_b32 s2, s0, 0x7fff
; GFX1200-FAKE16-NEXT:    s_and_b32 s4, s1, 0x7fff
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_cvt_f32_f16 s3, s2
; GFX1200-FAKE16-NEXT:    s_cvt_f32_f16 s4, s4
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_2)
; GFX1200-FAKE16-NEXT:    s_cmp_gt_f32 s3, s4
; GFX1200-FAKE16-NEXT:    s_cbranch_scc0 .LBB26_5
; GFX1200-FAKE16-NEXT:  ; %bb.1: ; %frem.compute19
; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v1, s4
; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v0, s3
; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, s3
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v2, v0, 11
; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v0, s4
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s3, v3
; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s4, v0
; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v0, -1, v0
; GFX1200-FAKE16-NEXT:    v_rcp_f32_e32 v6, v5
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_not_b32_e32 v4, v0
; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v4, v4, v3
; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX1200-FAKE16-NEXT:    s_denorm_mode 15
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v6, v7, v6
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v7, v3, v6
; GFX1200-FAKE16-NEXT:    v_fma_f32 v8, -v5, v7, v3
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v7, v8, v6
; GFX1200-FAKE16-NEXT:    v_fma_f32 v3, -v5, v7, v3
; GFX1200-FAKE16-NEXT:    s_denorm_mode 12
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-FAKE16-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
; GFX1200-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1200-FAKE16-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX1200-FAKE16-NEXT:    s_cbranch_vccnz .LBB26_6
; GFX1200-FAKE16-NEXT:  ; %bb.2: ; %frem.loop_body27.preheader
; GFX1200-FAKE16-NEXT:    s_sub_co_i32 s3, s3, s4
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_add_co_i32 s3, s3, 11
; GFX1200-FAKE16-NEXT:  .LBB26_3: ; %frem.loop_body27
; GFX1200-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_add_co_i32 s3, s3, -11
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_cmp_gt_i32 s3, 11
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v2, v5, v3
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v2, v2
; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v2, 0x80000000, v2
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f32 v2, v2, v1, v5
; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v4, v2, v1
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v2, v2, 11
; GFX1200-FAKE16-NEXT:    s_cbranch_scc1 .LBB26_3
; GFX1200-FAKE16-NEXT:  ; %bb.4:
; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v4, s3
; GFX1200-FAKE16-NEXT:    s_branch .LBB26_7
; GFX1200-FAKE16-NEXT:  .LBB26_5: ; %frem.else20
; GFX1200-FAKE16-NEXT:    s_and_b32 s5, 0x8000, s0
; GFX1200-FAKE16-NEXT:    s_cmp_eq_f32 s3, s4
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v0, s5
; GFX1200-FAKE16-NEXT:    s_cselect_b32 vcc_lo, -1, 0
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v0, s0, v0, vcc_lo
; GFX1200-FAKE16-NEXT:    s_branch .LBB26_8
; GFX1200-FAKE16-NEXT:  .LBB26_6:
; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX1200-FAKE16-NEXT:  .LBB26_7: ; %frem.loop_exit28
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v2, -10, v4
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v3, v3
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v2, v3, v1
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX1200-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_bfi_b32 v0, 0x7fff, v0, s0
; GFX1200-FAKE16-NEXT:  .LBB26_8:
; GFX1200-FAKE16-NEXT:    s_lshr_b32 s4, s0, 16
; GFX1200-FAKE16-NEXT:    s_lshr_b32 s3, s1, 16
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_and_b32 s0, s4, 0x7fff
; GFX1200-FAKE16-NEXT:    s_and_b32 s6, s3, 0x7fff
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_cvt_f32_f16 s5, s0
; GFX1200-FAKE16-NEXT:    s_cvt_f32_f16 s6, s6
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_2)
; GFX1200-FAKE16-NEXT:    s_cmp_gt_f32 s5, s6
; GFX1200-FAKE16-NEXT:    s_cbranch_scc0 .LBB26_13
; GFX1200-FAKE16-NEXT:  ; %bb.9: ; %frem.compute
; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v2, s6
; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v1, s5
; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v4, s5
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v2, v2, 1
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v3, v1, 11
; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v1, s6
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s5, v4
; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v6, null, v2, v2, 1.0
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s6, v1
; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v1, -1, v1
; GFX1200-FAKE16-NEXT:    v_rcp_f32_e32 v7, v6
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_not_b32_e32 v5, v1
; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v5, v5, v4
; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
; GFX1200-FAKE16-NEXT:    s_denorm_mode 15
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v7, v8, v7
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v8, v4, v7
; GFX1200-FAKE16-NEXT:    v_fma_f32 v9, -v6, v8, v4
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v8, v9, v7
; GFX1200-FAKE16-NEXT:    v_fma_f32 v4, -v6, v8, v4
; GFX1200-FAKE16-NEXT:    s_denorm_mode 12
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-FAKE16-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
; GFX1200-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX1200-FAKE16-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; GFX1200-FAKE16-NEXT:    s_cbranch_vccnz .LBB26_14
; GFX1200-FAKE16-NEXT:  ; %bb.10: ; %frem.loop_body.preheader
; GFX1200-FAKE16-NEXT:    s_sub_co_i32 s5, s5, s6
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_add_co_i32 s5, s5, 11
; GFX1200-FAKE16-NEXT:  .LBB26_11: ; %frem.loop_body
; GFX1200-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v6, v3
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_add_co_i32 s5, s5, -11
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_cmp_gt_i32 s5, 11
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v3, v6, v4
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v3, v3
; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f32 v3, v3, v2, v6
; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v5, v3, v2
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v3, v3, 11
; GFX1200-FAKE16-NEXT:    s_cbranch_scc1 .LBB26_11
; GFX1200-FAKE16-NEXT:  ; %bb.12:
; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v5, s5
; GFX1200-FAKE16-NEXT:    s_branch .LBB26_15
; GFX1200-FAKE16-NEXT:  .LBB26_13: ; %frem.else
; GFX1200-FAKE16-NEXT:    s_and_b32 s7, 0x8000, s4
; GFX1200-FAKE16-NEXT:    s_cmp_eq_f32 s5, s6
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v1, s7
; GFX1200-FAKE16-NEXT:    s_cselect_b32 vcc_lo, -1, 0
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v1, s4, v1, vcc_lo
; GFX1200-FAKE16-NEXT:    s_branch .LBB26_16
; GFX1200-FAKE16-NEXT:  .LBB26_14:
; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v6, v3
; GFX1200-FAKE16-NEXT:  .LBB26_15: ; %frem.loop_exit
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v3, -10, v5
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v3, v6, v3
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v4, v3, v4
; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v4, v4
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v3, v4, v2
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v2, v3, v2
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v1, v2, v1
; GFX1200-FAKE16-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_bfi_b32 v1, 0x7fff, v1, s4
; GFX1200-FAKE16-NEXT:  .LBB26_16:
; GFX1200-FAKE16-NEXT:    s_cmp_lg_f16 s1, 0
; GFX1200-FAKE16-NEXT:    s_cselect_b32 s1, -1, 0
; GFX1200-FAKE16-NEXT:    s_cmp_nge_f16 s2, 0x7c00
; GFX1200-FAKE16-NEXT:    s_cselect_b32 s2, -1, 0
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_and_b32 vcc_lo, s2, s1
; GFX1200-FAKE16-NEXT:    s_cmp_lg_f16 s3, 0
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v0, vcc_lo
; GFX1200-FAKE16-NEXT:    s_cselect_b32 s1, -1, 0
; GFX1200-FAKE16-NEXT:    s_cmp_nge_f16 s0, 0x7c00
; GFX1200-FAKE16-NEXT:    s_cselect_b32 s0, -1, 0
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_and_b32 vcc_lo, s0, s1
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x7e00, v1, vcc_lo
; GFX1200-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
; GFX1200-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %r2 = frem <2 x half> %in1, %in2
  ret <2 x half> %r2
}

define <4 x half> @frem_v4f16_uniform(<4 x half> inreg %in1, <4 x half> inreg %in2) #0 {
; SI-LABEL: frem_v4f16_uniform:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cvt_f32_f16_e64 v1, |s16|
; SI-NEXT:    v_cvt_f32_f16_e64 v0, |s18|
; SI-NEXT:    s_lshr_b32 s7, s18, 16
; SI-NEXT:    s_lshr_b32 s6, s16, 16
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v0
; SI-NEXT:    s_cbranch_vccz .LBB27_4
; SI-NEXT:  ; %bb.1: ; %frem.compute85
; SI-NEXT:    s_mov_b32 s9, 0x7f800000
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v1|, s9
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v2, v1
; SI-NEXT:    s_and_b64 s[4:5], vcc, exec
; SI-NEXT:    v_readfirstlane_b32 s4, v2
; SI-NEXT:    v_frexp_mant_f32_e32 v2, v1
; SI-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, s9
; SI-NEXT:    v_frexp_mant_f32_e32 v2, v0
; SI-NEXT:    s_cselect_b32 s8, s4, 0
; SI-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v0, v0
; SI-NEXT:    s_and_b64 s[4:5], vcc, exec
; SI-NEXT:    v_readfirstlane_b32 s4, v0
; SI-NEXT:    v_ldexp_f32_e64 v0, v2, 1
; SI-NEXT:    v_div_scale_f32 v3, s[10:11], v0, v0, 1.0
; SI-NEXT:    v_rcp_f32_e32 v4, v3
; SI-NEXT:    v_ldexp_f32_e64 v1, v1, 11
; SI-NEXT:    v_div_scale_f32 v2, vcc, 1.0, v0, 1.0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
; SI-NEXT:    v_fma_f32 v4, v5, v4, v4
; SI-NEXT:    v_mul_f32_e32 v5, v2, v4
; SI-NEXT:    s_cselect_b32 s9, s4, 0
; SI-NEXT:    v_fma_f32 v6, -v3, v5, v2
; SI-NEXT:    s_add_i32 s4, s9, -1
; SI-NEXT:    v_fma_f32 v5, v6, v4, v5
; SI-NEXT:    s_not_b32 s5, s4
; SI-NEXT:    v_fma_f32 v2, -v3, v5, v2
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    s_add_i32 s5, s5, s8
; SI-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
; SI-NEXT:    v_div_fixup_f32 v2, v2, v0, 1.0
; SI-NEXT:    s_cmp_lt_i32 s5, 12
; SI-NEXT:    s_cbranch_scc1 .LBB27_5
; SI-NEXT:  ; %bb.2: ; %frem.loop_body93.preheader
; SI-NEXT:    s_sub_i32 s5, s8, s9
; SI-NEXT:    s_add_i32 s5, s5, 11
; SI-NEXT:  .LBB27_3: ; %frem.loop_body93
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v3, v1
; SI-NEXT:    v_mul_f32_e32 v1, v3, v2
; SI-NEXT:    v_rndne_f32_e32 v1, v1
; SI-NEXT:    v_fma_f32 v1, -v1, v0, v3
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v1
; SI-NEXT:    v_add_f32_e32 v4, v1, v0
; SI-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
; SI-NEXT:    s_add_i32 s5, s5, -11
; SI-NEXT:    v_ldexp_f32_e64 v1, v1, 11
; SI-NEXT:    s_cmp_gt_i32 s5, 11
; SI-NEXT:    s_cbranch_scc1 .LBB27_3
; SI-NEXT:    s_branch .LBB27_6
; SI-NEXT:  .LBB27_4: ; %frem.else86
; SI-NEXT:    s_and_b32 s8, s16, 0xffff8000
; SI-NEXT:    v_cmp_eq_f32_e32 vcc, v1, v0
; SI-NEXT:    s_and_b64 s[4:5], vcc, exec
; SI-NEXT:    s_cselect_b32 s4, s8, s16
; SI-NEXT:    v_mov_b32_e32 v0, s4
; SI-NEXT:    s_branch .LBB27_7
; SI-NEXT:  .LBB27_5:
; SI-NEXT:    v_mov_b32_e32 v3, v1
; SI-NEXT:  .LBB27_6: ; %frem.loop_exit94
; SI-NEXT:    s_add_i32 s5, s5, -10
; SI-NEXT:    v_ldexp_f32_e64 v1, v3, s5
; SI-NEXT:    v_mul_f32_e32 v2, v1, v2
; SI-NEXT:    v_rndne_f32_e32 v2, v2
; SI-NEXT:    v_fma_f32 v1, -v2, v0, v1
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v1
; SI-NEXT:    v_add_f32_e32 v0, v1, v0
; SI-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; SI-NEXT:    v_ldexp_f32_e64 v0, v0, s4
; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-NEXT:    s_and_b32 s4, s16, 0xffff8000
; SI-NEXT:    v_and_b32_e32 v0, 0x7fff, v0
; SI-NEXT:    v_or_b32_e32 v0, s4, v0
; SI-NEXT:  .LBB27_7:
; SI-NEXT:    v_cvt_f32_f16_e64 v2, |s6|
; SI-NEXT:    v_cvt_f32_f16_e64 v1, |s7|
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v1
; SI-NEXT:    s_cbranch_vccz .LBB27_11
; SI-NEXT:  ; %bb.8: ; %frem.compute52
; SI-NEXT:    s_mov_b32 s9, 0x7f800000
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v2|, s9
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v3, v2
; SI-NEXT:    s_and_b64 s[4:5], vcc, exec
; SI-NEXT:    v_readfirstlane_b32 s4, v3
; SI-NEXT:    v_frexp_mant_f32_e32 v3, v2
; SI-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v1|, s9
; SI-NEXT:    v_frexp_mant_f32_e32 v3, v1
; SI-NEXT:    s_cselect_b32 s8, s4, 0
; SI-NEXT:    v_cndmask_b32_e32 v3, v1, v3, vcc
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v1, v1
; SI-NEXT:    s_and_b64 s[4:5], vcc, exec
; SI-NEXT:    v_readfirstlane_b32 s4, v1
; SI-NEXT:    v_ldexp_f32_e64 v1, v3, 1
; SI-NEXT:    v_div_scale_f32 v4, s[10:11], v1, v1, 1.0
; SI-NEXT:    v_rcp_f32_e32 v5, v4
; SI-NEXT:    v_ldexp_f32_e64 v2, v2, 11
; SI-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v1, 1.0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    v_fma_f32 v6, -v4, v5, 1.0
; SI-NEXT:    v_fma_f32 v5, v6, v5, v5
; SI-NEXT:    v_mul_f32_e32 v6, v3, v5
; SI-NEXT:    s_cselect_b32 s9, s4, 0
; SI-NEXT:    v_fma_f32 v7, -v4, v6, v3
; SI-NEXT:    s_add_i32 s4, s9, -1
; SI-NEXT:    v_fma_f32 v6, v7, v5, v6
; SI-NEXT:    s_not_b32 s5, s4
; SI-NEXT:    v_fma_f32 v3, -v4, v6, v3
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    s_add_i32 s5, s5, s8
; SI-NEXT:    v_div_fmas_f32 v3, v3, v5, v6
; SI-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; SI-NEXT:    s_cmp_lt_i32 s5, 12
; SI-NEXT:    s_cbranch_scc1 .LBB27_12
; SI-NEXT:  ; %bb.9: ; %frem.loop_body60.preheader
; SI-NEXT:    s_sub_i32 s5, s8, s9
; SI-NEXT:    s_add_i32 s5, s5, 11
; SI-NEXT:  .LBB27_10: ; %frem.loop_body60
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v4, v2
; SI-NEXT:    v_mul_f32_e32 v2, v4, v3
; SI-NEXT:    v_rndne_f32_e32 v2, v2
; SI-NEXT:    v_fma_f32 v2, -v2, v1, v4
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v2
; SI-NEXT:    v_add_f32_e32 v5, v2, v1
; SI-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
; SI-NEXT:    s_add_i32 s5, s5, -11
; SI-NEXT:    v_ldexp_f32_e64 v2, v2, 11
; SI-NEXT:    s_cmp_gt_i32 s5, 11
; SI-NEXT:    s_cbranch_scc1 .LBB27_10
; SI-NEXT:    s_branch .LBB27_13
; SI-NEXT:  .LBB27_11: ; %frem.else53
; SI-NEXT:    s_and_b32 s8, s6, 0x8000
; SI-NEXT:    v_cmp_eq_f32_e32 vcc, v2, v1
; SI-NEXT:    s_and_b64 s[4:5], vcc, exec
; SI-NEXT:    s_cselect_b32 s4, s8, s6
; SI-NEXT:    v_mov_b32_e32 v1, s4
; SI-NEXT:    s_branch .LBB27_14
; SI-NEXT:  .LBB27_12:
; SI-NEXT:    v_mov_b32_e32 v4, v2
; SI-NEXT:  .LBB27_13: ; %frem.loop_exit61
; SI-NEXT:    s_add_i32 s5, s5, -10
; SI-NEXT:    v_ldexp_f32_e64 v2, v4, s5
; SI-NEXT:    v_mul_f32_e32 v3, v2, v3
; SI-NEXT:    v_rndne_f32_e32 v3, v3
; SI-NEXT:    v_fma_f32 v2, -v3, v1, v2
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v2
; SI-NEXT:    v_add_f32_e32 v1, v2, v1
; SI-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; SI-NEXT:    v_ldexp_f32_e64 v1, v1, s4
; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1
; SI-NEXT:    s_and_b32 s4, s6, 0x8000
; SI-NEXT:    v_and_b32_e32 v1, 0x7fff, v1
; SI-NEXT:    v_or_b32_e32 v1, s4, v1
; SI-NEXT:  .LBB27_14:
; SI-NEXT:    v_cvt_f32_f16_e64 v3, |s17|
; SI-NEXT:    v_cvt_f32_f16_e64 v2, |s19|
; SI-NEXT:    s_lshr_b32 s9, s19, 16
; SI-NEXT:    s_lshr_b32 s8, s17, 16
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, v3, v2
; SI-NEXT:    s_cbranch_vccz .LBB27_18
; SI-NEXT:  ; %bb.15: ; %frem.compute19
; SI-NEXT:    s_mov_b32 s11, 0x7f800000
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v3|, s11
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v4, v3
; SI-NEXT:    s_and_b64 s[4:5], vcc, exec
; SI-NEXT:    v_readfirstlane_b32 s4, v4
; SI-NEXT:    v_frexp_mant_f32_e32 v4, v3
; SI-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v2|, s11
; SI-NEXT:    v_frexp_mant_f32_e32 v4, v2
; SI-NEXT:    s_cselect_b32 s10, s4, 0
; SI-NEXT:    v_cndmask_b32_e32 v4, v2, v4, vcc
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v2, v2
; SI-NEXT:    s_and_b64 s[4:5], vcc, exec
; SI-NEXT:    v_readfirstlane_b32 s4, v2
; SI-NEXT:    v_ldexp_f32_e64 v2, v4, 1
; SI-NEXT:    v_div_scale_f32 v5, s[12:13], v2, v2, 1.0
; SI-NEXT:    v_rcp_f32_e32 v6, v5
; SI-NEXT:    v_ldexp_f32_e64 v3, v3, 11
; SI-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v2, 1.0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
; SI-NEXT:    v_fma_f32 v6, v7, v6, v6
; SI-NEXT:    v_mul_f32_e32 v7, v4, v6
; SI-NEXT:    s_cselect_b32 s11, s4, 0
; SI-NEXT:    v_fma_f32 v8, -v5, v7, v4
; SI-NEXT:    s_add_i32 s4, s11, -1
; SI-NEXT:    v_fma_f32 v7, v8, v6, v7
; SI-NEXT:    s_not_b32 s5, s4
; SI-NEXT:    v_fma_f32 v4, -v5, v7, v4
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    s_add_i32 s5, s5, s10
; SI-NEXT:    v_div_fmas_f32 v4, v4, v6, v7
; SI-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; SI-NEXT:    s_cmp_lt_i32 s5, 12
; SI-NEXT:    s_cbranch_scc1 .LBB27_19
; SI-NEXT:  ; %bb.16: ; %frem.loop_body27.preheader
; SI-NEXT:    s_sub_i32 s5, s10, s11
; SI-NEXT:    s_add_i32 s5, s5, 11
; SI-NEXT:  .LBB27_17: ; %frem.loop_body27
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v5, v3
; SI-NEXT:    v_mul_f32_e32 v3, v5, v4
; SI-NEXT:    v_rndne_f32_e32 v3, v3
; SI-NEXT:    v_fma_f32 v3, -v3, v2, v5
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v3
; SI-NEXT:    v_add_f32_e32 v6, v3, v2
; SI-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc
; SI-NEXT:    s_add_i32 s5, s5, -11
; SI-NEXT:    v_ldexp_f32_e64 v3, v3, 11
; SI-NEXT:    s_cmp_gt_i32 s5, 11
; SI-NEXT:    s_cbranch_scc1 .LBB27_17
; SI-NEXT:    s_branch .LBB27_20
; SI-NEXT:  .LBB27_18: ; %frem.else20
; SI-NEXT:    s_and_b32 s10, s17, 0xffff8000
; SI-NEXT:    v_cmp_eq_f32_e32 vcc, v3, v2
; SI-NEXT:    s_and_b64 s[4:5], vcc, exec
; SI-NEXT:    s_cselect_b32 s4, s10, s17
; SI-NEXT:    v_mov_b32_e32 v2, s4
; SI-NEXT:    s_branch .LBB27_21
; SI-NEXT:  .LBB27_19:
; SI-NEXT:    v_mov_b32_e32 v5, v3
; SI-NEXT:  .LBB27_20: ; %frem.loop_exit28
; SI-NEXT:    s_add_i32 s5, s5, -10
; SI-NEXT:    v_ldexp_f32_e64 v3, v5, s5
; SI-NEXT:    v_mul_f32_e32 v4, v3, v4
; SI-NEXT:    v_rndne_f32_e32 v4, v4
; SI-NEXT:    v_fma_f32 v3, -v4, v2, v3
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v3
; SI-NEXT:    v_add_f32_e32 v2, v3, v2
; SI-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; SI-NEXT:    v_ldexp_f32_e64 v2, v2, s4
; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; SI-NEXT:    s_and_b32 s4, s17, 0xffff8000
; SI-NEXT:    v_and_b32_e32 v2, 0x7fff, v2
; SI-NEXT:    v_or_b32_e32 v2, s4, v2
; SI-NEXT:  .LBB27_21:
; SI-NEXT:    v_cvt_f32_f16_e64 v4, |s8|
; SI-NEXT:    v_cvt_f32_f16_e64 v3, |s9|
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, v4, v3
; SI-NEXT:    s_cbranch_vccz .LBB27_25
; SI-NEXT:  ; %bb.22: ; %frem.compute
; SI-NEXT:    s_mov_b32 s11, 0x7f800000
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v4|, s11
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v5, v4
; SI-NEXT:    s_and_b64 s[4:5], vcc, exec
; SI-NEXT:    v_readfirstlane_b32 s4, v5
; SI-NEXT:    v_frexp_mant_f32_e32 v5, v4
; SI-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc
; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v3|, s11
; SI-NEXT:    v_frexp_mant_f32_e32 v5, v3
; SI-NEXT:    s_cselect_b32 s10, s4, 0
; SI-NEXT:    v_cndmask_b32_e32 v5, v3, v5, vcc
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v3, v3
; SI-NEXT:    s_and_b64 s[4:5], vcc, exec
; SI-NEXT:    v_readfirstlane_b32 s4, v3
; SI-NEXT:    v_ldexp_f32_e64 v3, v5, 1
; SI-NEXT:    v_div_scale_f32 v6, s[12:13], v3, v3, 1.0
; SI-NEXT:    v_rcp_f32_e32 v7, v6
; SI-NEXT:    v_ldexp_f32_e64 v4, v4, 11
; SI-NEXT:    v_div_scale_f32 v5, vcc, 1.0, v3, 1.0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
; SI-NEXT:    v_fma_f32 v7, v8, v7, v7
; SI-NEXT:    v_mul_f32_e32 v8, v5, v7
; SI-NEXT:    s_cselect_b32 s11, s4, 0
; SI-NEXT:    v_fma_f32 v9, -v6, v8, v5
; SI-NEXT:    s_add_i32 s4, s11, -1
; SI-NEXT:    v_fma_f32 v8, v9, v7, v8
; SI-NEXT:    s_not_b32 s5, s4
; SI-NEXT:    v_fma_f32 v5, -v6, v8, v5
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    s_add_i32 s5, s5, s10
; SI-NEXT:    v_div_fmas_f32 v5, v5, v7, v8
; SI-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
; SI-NEXT:    s_cmp_lt_i32 s5, 12
; SI-NEXT:    s_cbranch_scc1 .LBB27_26
; SI-NEXT:  ; %bb.23: ; %frem.loop_body.preheader
; SI-NEXT:    s_sub_i32 s5, s10, s11
; SI-NEXT:    s_add_i32 s5, s5, 11
; SI-NEXT:  .LBB27_24: ; %frem.loop_body
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v6, v4
; SI-NEXT:    v_mul_f32_e32 v4, v6, v5
; SI-NEXT:    v_rndne_f32_e32 v4, v4
; SI-NEXT:    v_fma_f32 v4, -v4, v3, v6
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; SI-NEXT:    v_add_f32_e32 v7, v4, v3
; SI-NEXT:    v_cndmask_b32_e32 v4, v4, v7, vcc
; SI-NEXT:    s_add_i32 s5, s5, -11
; SI-NEXT:    v_ldexp_f32_e64 v4, v4, 11
; SI-NEXT:    s_cmp_gt_i32 s5, 11
; SI-NEXT:    s_cbranch_scc1 .LBB27_24
; SI-NEXT:    s_branch .LBB27_27
; SI-NEXT:  .LBB27_25: ; %frem.else
; SI-NEXT:    s_and_b32 s10, s8, 0x8000
; SI-NEXT:    v_cmp_eq_f32_e32 vcc, v4, v3
; SI-NEXT:    s_and_b64 s[4:5], vcc, exec
; SI-NEXT:    s_cselect_b32 s4, s10, s8
; SI-NEXT:    v_mov_b32_e32 v3, s4
; SI-NEXT:    s_branch .LBB27_28
; SI-NEXT:  .LBB27_26:
; SI-NEXT:    v_mov_b32_e32 v6, v4
; SI-NEXT:  .LBB27_27: ; %frem.loop_exit
; SI-NEXT:    s_add_i32 s5, s5, -10
; SI-NEXT:    v_ldexp_f32_e64 v4, v6, s5
; SI-NEXT:    v_mul_f32_e32 v5, v4, v5
; SI-NEXT:    v_rndne_f32_e32 v5, v5
; SI-NEXT:    v_fma_f32 v4, -v5, v3, v4
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; SI-NEXT:    v_add_f32_e32 v3, v4, v3
; SI-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; SI-NEXT:    v_ldexp_f32_e64 v3, v3, s4
; SI-NEXT:    v_cvt_f16_f32_e32 v3, v3
; SI-NEXT:    s_and_b32 s4, s8, 0x8000
; SI-NEXT:    v_and_b32_e32 v3, 0x7fff, v3
; SI-NEXT:    v_or_b32_e32 v3, s4, v3
; SI-NEXT:  .LBB27_28:
; SI-NEXT:    v_cvt_f32_f16_e32 v4, s18
; SI-NEXT:    v_cvt_f32_f16_e32 v5, s7
; SI-NEXT:    s_mov_b32 s10, 0x7f800000
; SI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v4
; SI-NEXT:    v_cvt_f32_f16_e64 v4, |s16|
; SI-NEXT:    v_cmp_nle_f32_e64 s[4:5], s10, v4
; SI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; SI-NEXT:    v_mov_b32_e32 v4, 0x7e00
; SI-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
; SI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v5
; SI-NEXT:    v_cvt_f32_f16_e64 v5, |s6|
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_cmp_nle_f32_e64 s[4:5], s10, v5
; SI-NEXT:    v_cvt_f32_f16_e32 v5, s19
; SI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; SI-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v5
; SI-NEXT:    v_cvt_f32_f16_e64 v5, |s17|
; SI-NEXT:    v_or_b32_e32 v0, v0, v1
; SI-NEXT:    v_cmp_nle_f32_e64 s[4:5], s10, v5
; SI-NEXT:    v_cvt_f32_f16_e32 v5, s9
; SI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; SI-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v5
; SI-NEXT:    v_cvt_f32_f16_e64 v5, |s8|
; SI-NEXT:    v_cmp_nle_f32_e64 s[4:5], s10, v5
; SI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; SI-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v3
; SI-NEXT:    v_or_b32_e32 v1, v2, v1
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; CI-LABEL: frem_v4f16_uniform:
; CI:       ; %bb.0:
; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-NEXT:    v_cvt_f32_f16_e64 v1, |s16|
; CI-NEXT:    v_cvt_f32_f16_e64 v0, |s18|
; CI-NEXT:    s_lshr_b32 s7, s18, 16
; CI-NEXT:    s_lshr_b32 s6, s16, 16
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v0
; CI-NEXT:    s_cbranch_vccz .LBB27_4
; CI-NEXT:  ; %bb.1: ; %frem.compute85
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v5, v1
; CI-NEXT:    v_frexp_mant_f32_e32 v1, v1
; CI-NEXT:    v_ldexp_f32_e64 v4, v1, 11
; CI-NEXT:    v_frexp_mant_f32_e32 v1, v0
; CI-NEXT:    v_ldexp_f32_e64 v1, v1, 1
; CI-NEXT:    v_div_scale_f32 v7, s[4:5], v1, v1, 1.0
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v6, v0
; CI-NEXT:    v_add_i32_e32 v0, vcc, -1, v6
; CI-NEXT:    v_not_b32_e32 v2, v0
; CI-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
; CI-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v1, 1.0
; CI-NEXT:    v_rcp_f32_e32 v8, v7
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
; CI-NEXT:    v_fma_f32 v8, v9, v8, v8
; CI-NEXT:    v_mul_f32_e32 v9, v3, v8
; CI-NEXT:    v_fma_f32 v10, -v7, v9, v3
; CI-NEXT:    v_fma_f32 v9, v10, v8, v9
; CI-NEXT:    v_fma_f32 v3, -v7, v9, v3
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v3, v3, v8, v9
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v2
; CI-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; CI-NEXT:    s_cbranch_vccnz .LBB27_5
; CI-NEXT:  ; %bb.2: ; %frem.loop_body93.preheader
; CI-NEXT:    v_sub_i32_e32 v2, vcc, v5, v6
; CI-NEXT:    v_add_i32_e32 v2, vcc, 11, v2
; CI-NEXT:  .LBB27_3: ; %frem.loop_body93
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v5, v4
; CI-NEXT:    v_mul_f32_e32 v4, v5, v3
; CI-NEXT:    v_rndne_f32_e32 v4, v4
; CI-NEXT:    v_fma_f32 v4, -v4, v1, v5
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; CI-NEXT:    v_add_f32_e32 v6, v4, v1
; CI-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
; CI-NEXT:    v_add_i32_e32 v2, vcc, -11, v2
; CI-NEXT:    v_ldexp_f32_e64 v4, v4, 11
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v2
; CI-NEXT:    s_cbranch_vccnz .LBB27_3
; CI-NEXT:    s_branch .LBB27_6
; CI-NEXT:  .LBB27_4: ; %frem.else86
; CI-NEXT:    s_and_b32 s8, s16, 0xffff8000
; CI-NEXT:    v_cmp_eq_f32_e32 vcc, v1, v0
; CI-NEXT:    s_and_b64 s[4:5], vcc, exec
; CI-NEXT:    s_cselect_b32 s4, s8, s16
; CI-NEXT:    v_mov_b32_e32 v0, s4
; CI-NEXT:    s_branch .LBB27_7
; CI-NEXT:  .LBB27_5:
; CI-NEXT:    v_mov_b32_e32 v5, v4
; CI-NEXT:  .LBB27_6: ; %frem.loop_exit94
; CI-NEXT:    v_add_i32_e32 v2, vcc, -10, v2
; CI-NEXT:    v_ldexp_f32_e32 v2, v5, v2
; CI-NEXT:    v_mul_f32_e32 v3, v2, v3
; CI-NEXT:    v_rndne_f32_e32 v3, v3
; CI-NEXT:    v_fma_f32 v2, -v3, v1, v2
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v2
; CI-NEXT:    v_add_f32_e32 v1, v2, v1
; CI-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; CI-NEXT:    v_ldexp_f32_e32 v0, v1, v0
; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; CI-NEXT:    s_and_b32 s4, s16, 0xffff8000
; CI-NEXT:    v_and_b32_e32 v0, 0x7fff, v0
; CI-NEXT:    v_or_b32_e32 v0, s4, v0
; CI-NEXT:  .LBB27_7:
; CI-NEXT:    v_cvt_f32_f16_e64 v2, |s6|
; CI-NEXT:    v_cvt_f32_f16_e64 v1, |s7|
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v1
; CI-NEXT:    s_cbranch_vccz .LBB27_11
; CI-NEXT:  ; %bb.8: ; %frem.compute52
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v6, v2
; CI-NEXT:    v_frexp_mant_f32_e32 v2, v2
; CI-NEXT:    v_ldexp_f32_e64 v5, v2, 11
; CI-NEXT:    v_frexp_mant_f32_e32 v2, v1
; CI-NEXT:    v_ldexp_f32_e64 v2, v2, 1
; CI-NEXT:    v_div_scale_f32 v8, s[4:5], v2, v2, 1.0
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v7, v1
; CI-NEXT:    v_add_i32_e32 v1, vcc, -1, v7
; CI-NEXT:    v_not_b32_e32 v3, v1
; CI-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
; CI-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v2, 1.0
; CI-NEXT:    v_rcp_f32_e32 v9, v8
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
; CI-NEXT:    v_fma_f32 v9, v10, v9, v9
; CI-NEXT:    v_mul_f32_e32 v10, v4, v9
; CI-NEXT:    v_fma_f32 v11, -v8, v10, v4
; CI-NEXT:    v_fma_f32 v10, v11, v9, v10
; CI-NEXT:    v_fma_f32 v4, -v8, v10, v4
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v4, v4, v9, v10
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v3
; CI-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; CI-NEXT:    s_cbranch_vccnz .LBB27_12
; CI-NEXT:  ; %bb.9: ; %frem.loop_body60.preheader
; CI-NEXT:    v_sub_i32_e32 v3, vcc, v6, v7
; CI-NEXT:    v_add_i32_e32 v3, vcc, 11, v3
; CI-NEXT:  .LBB27_10: ; %frem.loop_body60
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v6, v5
; CI-NEXT:    v_mul_f32_e32 v5, v6, v4
; CI-NEXT:    v_rndne_f32_e32 v5, v5
; CI-NEXT:    v_fma_f32 v5, -v5, v2, v6
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
; CI-NEXT:    v_add_f32_e32 v7, v5, v2
; CI-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
; CI-NEXT:    v_add_i32_e32 v3, vcc, -11, v3
; CI-NEXT:    v_ldexp_f32_e64 v5, v5, 11
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v3
; CI-NEXT:    s_cbranch_vccnz .LBB27_10
; CI-NEXT:    s_branch .LBB27_13
; CI-NEXT:  .LBB27_11: ; %frem.else53
; CI-NEXT:    s_and_b32 s8, s6, 0x8000
; CI-NEXT:    v_cmp_eq_f32_e32 vcc, v2, v1
; CI-NEXT:    s_and_b64 s[4:5], vcc, exec
; CI-NEXT:    s_cselect_b32 s4, s8, s6
; CI-NEXT:    v_mov_b32_e32 v1, s4
; CI-NEXT:    s_branch .LBB27_14
; CI-NEXT:  .LBB27_12:
; CI-NEXT:    v_mov_b32_e32 v6, v5
; CI-NEXT:  .LBB27_13: ; %frem.loop_exit61
; CI-NEXT:    v_add_i32_e32 v3, vcc, -10, v3
; CI-NEXT:    v_ldexp_f32_e32 v3, v6, v3
; CI-NEXT:    v_mul_f32_e32 v4, v3, v4
; CI-NEXT:    v_rndne_f32_e32 v4, v4
; CI-NEXT:    v_fma_f32 v3, -v4, v2, v3
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v3
; CI-NEXT:    v_add_f32_e32 v2, v3, v2
; CI-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; CI-NEXT:    v_ldexp_f32_e32 v1, v2, v1
; CI-NEXT:    v_cvt_f16_f32_e32 v1, v1
; CI-NEXT:    s_and_b32 s4, s6, 0x8000
; CI-NEXT:    v_and_b32_e32 v1, 0x7fff, v1
; CI-NEXT:    v_or_b32_e32 v1, s4, v1
; CI-NEXT:  .LBB27_14:
; CI-NEXT:    v_cvt_f32_f16_e64 v3, |s17|
; CI-NEXT:    v_cvt_f32_f16_e64 v2, |s19|
; CI-NEXT:    s_lshr_b32 s9, s19, 16
; CI-NEXT:    s_lshr_b32 s8, s17, 16
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, v3, v2
; CI-NEXT:    s_cbranch_vccz .LBB27_18
; CI-NEXT:  ; %bb.15: ; %frem.compute19
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v7, v3
; CI-NEXT:    v_frexp_mant_f32_e32 v3, v3
; CI-NEXT:    v_ldexp_f32_e64 v6, v3, 11
; CI-NEXT:    v_frexp_mant_f32_e32 v3, v2
; CI-NEXT:    v_ldexp_f32_e64 v3, v3, 1
; CI-NEXT:    v_div_scale_f32 v9, s[4:5], v3, v3, 1.0
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v8, v2
; CI-NEXT:    v_add_i32_e32 v2, vcc, -1, v8
; CI-NEXT:    v_not_b32_e32 v4, v2
; CI-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
; CI-NEXT:    v_div_scale_f32 v5, vcc, 1.0, v3, 1.0
; CI-NEXT:    v_rcp_f32_e32 v10, v9
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; CI-NEXT:    v_fma_f32 v10, v11, v10, v10
; CI-NEXT:    v_mul_f32_e32 v11, v5, v10
; CI-NEXT:    v_fma_f32 v12, -v9, v11, v5
; CI-NEXT:    v_fma_f32 v11, v12, v10, v11
; CI-NEXT:    v_fma_f32 v5, -v9, v11, v5
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v5, v5, v10, v11
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v4
; CI-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
; CI-NEXT:    s_cbranch_vccnz .LBB27_19
; CI-NEXT:  ; %bb.16: ; %frem.loop_body27.preheader
; CI-NEXT:    v_sub_i32_e32 v4, vcc, v7, v8
; CI-NEXT:    v_add_i32_e32 v4, vcc, 11, v4
; CI-NEXT:  .LBB27_17: ; %frem.loop_body27
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v7, v6
; CI-NEXT:    v_mul_f32_e32 v6, v7, v5
; CI-NEXT:    v_rndne_f32_e32 v6, v6
; CI-NEXT:    v_fma_f32 v6, -v6, v3, v7
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v6
; CI-NEXT:    v_add_f32_e32 v8, v6, v3
; CI-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc
; CI-NEXT:    v_add_i32_e32 v4, vcc, -11, v4
; CI-NEXT:    v_ldexp_f32_e64 v6, v6, 11
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v4
; CI-NEXT:    s_cbranch_vccnz .LBB27_17
; CI-NEXT:    s_branch .LBB27_20
; CI-NEXT:  .LBB27_18: ; %frem.else20
; CI-NEXT:    s_and_b32 s10, s17, 0xffff8000
; CI-NEXT:    v_cmp_eq_f32_e32 vcc, v3, v2
; CI-NEXT:    s_and_b64 s[4:5], vcc, exec
; CI-NEXT:    s_cselect_b32 s4, s10, s17
; CI-NEXT:    v_mov_b32_e32 v2, s4
; CI-NEXT:    s_branch .LBB27_21
; CI-NEXT:  .LBB27_19:
; CI-NEXT:    v_mov_b32_e32 v7, v6
; CI-NEXT:  .LBB27_20: ; %frem.loop_exit28
; CI-NEXT:    v_add_i32_e32 v4, vcc, -10, v4
; CI-NEXT:    v_ldexp_f32_e32 v4, v7, v4
; CI-NEXT:    v_mul_f32_e32 v5, v4, v5
; CI-NEXT:    v_rndne_f32_e32 v5, v5
; CI-NEXT:    v_fma_f32 v4, -v5, v3, v4
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; CI-NEXT:    v_add_f32_e32 v3, v4, v3
; CI-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; CI-NEXT:    v_ldexp_f32_e32 v2, v3, v2
; CI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; CI-NEXT:    s_and_b32 s4, s17, 0xffff8000
; CI-NEXT:    v_and_b32_e32 v2, 0x7fff, v2
; CI-NEXT:    v_or_b32_e32 v2, s4, v2
; CI-NEXT:  .LBB27_21:
; CI-NEXT:    v_cvt_f32_f16_e64 v4, |s8|
; CI-NEXT:    v_cvt_f32_f16_e64 v3, |s9|
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, v4, v3
; CI-NEXT:    s_cbranch_vccz .LBB27_25
; CI-NEXT:  ; %bb.22: ; %frem.compute
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v8, v4
; CI-NEXT:    v_frexp_mant_f32_e32 v4, v4
; CI-NEXT:    v_ldexp_f32_e64 v7, v4, 11
; CI-NEXT:    v_frexp_mant_f32_e32 v4, v3
; CI-NEXT:    v_ldexp_f32_e64 v4, v4, 1
; CI-NEXT:    v_div_scale_f32 v10, s[4:5], v4, v4, 1.0
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v9, v3
; CI-NEXT:    v_add_i32_e32 v3, vcc, -1, v9
; CI-NEXT:    v_not_b32_e32 v5, v3
; CI-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
; CI-NEXT:    v_div_scale_f32 v6, vcc, 1.0, v4, 1.0
; CI-NEXT:    v_rcp_f32_e32 v11, v10
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v12, -v10, v11, 1.0
; CI-NEXT:    v_fma_f32 v11, v12, v11, v11
; CI-NEXT:    v_mul_f32_e32 v12, v6, v11
; CI-NEXT:    v_fma_f32 v13, -v10, v12, v6
; CI-NEXT:    v_fma_f32 v12, v13, v11, v12
; CI-NEXT:    v_fma_f32 v6, -v10, v12, v6
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v6, v6, v11, v12
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v5
; CI-NEXT:    v_div_fixup_f32 v6, v6, v4, 1.0
; CI-NEXT:    s_cbranch_vccnz .LBB27_26
; CI-NEXT:  ; %bb.23: ; %frem.loop_body.preheader
; CI-NEXT:    v_sub_i32_e32 v5, vcc, v8, v9
; CI-NEXT:    v_add_i32_e32 v5, vcc, 11, v5
; CI-NEXT:  .LBB27_24: ; %frem.loop_body
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v8, v7
; CI-NEXT:    v_mul_f32_e32 v7, v8, v6
; CI-NEXT:    v_rndne_f32_e32 v7, v7
; CI-NEXT:    v_fma_f32 v7, -v7, v4, v8
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v7
; CI-NEXT:    v_add_f32_e32 v9, v7, v4
; CI-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc
; CI-NEXT:    v_add_i32_e32 v5, vcc, -11, v5
; CI-NEXT:    v_ldexp_f32_e64 v7, v7, 11
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v5
; CI-NEXT:    s_cbranch_vccnz .LBB27_24
; CI-NEXT:    s_branch .LBB27_27
; CI-NEXT:  .LBB27_25: ; %frem.else
; CI-NEXT:    s_and_b32 s10, s8, 0x8000
; CI-NEXT:    v_cmp_eq_f32_e32 vcc, v4, v3
; CI-NEXT:    s_and_b64 s[4:5], vcc, exec
; CI-NEXT:    s_cselect_b32 s4, s10, s8
; CI-NEXT:    v_mov_b32_e32 v3, s4
; CI-NEXT:    s_branch .LBB27_28
; CI-NEXT:  .LBB27_26:
; CI-NEXT:    v_mov_b32_e32 v8, v7
; CI-NEXT:  .LBB27_27: ; %frem.loop_exit
; CI-NEXT:    v_add_i32_e32 v5, vcc, -10, v5
; CI-NEXT:    v_ldexp_f32_e32 v5, v8, v5
; CI-NEXT:    v_mul_f32_e32 v6, v5, v6
; CI-NEXT:    v_rndne_f32_e32 v6, v6
; CI-NEXT:    v_fma_f32 v5, -v6, v4, v5
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
; CI-NEXT:    v_add_f32_e32 v4, v5, v4
; CI-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc
; CI-NEXT:    v_ldexp_f32_e32 v3, v4, v3
; CI-NEXT:    v_cvt_f16_f32_e32 v3, v3
; CI-NEXT:    s_and_b32 s4, s8, 0x8000
; CI-NEXT:    v_and_b32_e32 v3, 0x7fff, v3
; CI-NEXT:    v_or_b32_e32 v3, s4, v3
; CI-NEXT:  .LBB27_28:
; CI-NEXT:    v_cvt_f32_f16_e32 v4, s18
; CI-NEXT:    v_cvt_f32_f16_e32 v5, s7
; CI-NEXT:    s_mov_b32 s10, 0x7f800000
; CI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v4
; CI-NEXT:    v_cvt_f32_f16_e64 v4, |s16|
; CI-NEXT:    v_cmp_nle_f32_e64 s[4:5], s10, v4
; CI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; CI-NEXT:    v_mov_b32_e32 v4, 0x7e00
; CI-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
; CI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v5
; CI-NEXT:    v_cvt_f32_f16_e64 v5, |s6|
; CI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; CI-NEXT:    v_cmp_nle_f32_e64 s[4:5], s10, v5
; CI-NEXT:    v_cvt_f32_f16_e32 v5, s19
; CI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; CI-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
; CI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; CI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v5
; CI-NEXT:    v_cvt_f32_f16_e64 v5, |s17|
; CI-NEXT:    v_or_b32_e32 v0, v0, v1
; CI-NEXT:    v_cmp_nle_f32_e64 s[4:5], s10, v5
; CI-NEXT:    v_cvt_f32_f16_e32 v5, s9
; CI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; CI-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; CI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; CI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v5
; CI-NEXT:    v_cvt_f32_f16_e64 v5, |s8|
; CI-NEXT:    v_cmp_nle_f32_e64 s[4:5], s10, v5
; CI-NEXT:    s_and_b64 vcc, s[4:5], vcc
; CI-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; CI-NEXT:    v_lshlrev_b32_e32 v1, 16, v3
; CI-NEXT:    v_or_b32_e32 v1, v2, v1
; CI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: frem_v4f16_uniform:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cvt_f32_f16_e64 v1, |s16|
; VI-NEXT:    v_cvt_f32_f16_e64 v0, |s18|
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v0
; VI-NEXT:    s_cbranch_vccz .LBB27_4
; VI-NEXT:  ; %bb.1: ; %frem.compute85
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v5, v1
; VI-NEXT:    v_frexp_mant_f32_e32 v1, v1
; VI-NEXT:    v_ldexp_f32 v4, v1, 11
; VI-NEXT:    v_frexp_mant_f32_e32 v1, v0
; VI-NEXT:    v_ldexp_f32 v1, v1, 1
; VI-NEXT:    v_div_scale_f32 v7, s[4:5], v1, v1, 1.0
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v6, v0
; VI-NEXT:    v_add_u32_e32 v0, vcc, -1, v6
; VI-NEXT:    v_not_b32_e32 v2, v0
; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v5
; VI-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v1, 1.0
; VI-NEXT:    v_rcp_f32_e32 v8, v7
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
; VI-NEXT:    v_fma_f32 v8, v9, v8, v8
; VI-NEXT:    v_mul_f32_e32 v9, v3, v8
; VI-NEXT:    v_fma_f32 v10, -v7, v9, v3
; VI-NEXT:    v_fma_f32 v9, v10, v8, v9
; VI-NEXT:    v_fma_f32 v3, -v7, v9, v3
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; VI-NEXT:    v_div_fmas_f32 v3, v3, v8, v9
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v2
; VI-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; VI-NEXT:    s_cbranch_vccnz .LBB27_5
; VI-NEXT:  ; %bb.2: ; %frem.loop_body93.preheader
; VI-NEXT:    v_sub_u32_e32 v2, vcc, v5, v6
; VI-NEXT:    v_add_u32_e32 v2, vcc, 11, v2
; VI-NEXT:  .LBB27_3: ; %frem.loop_body93
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v5, v4
; VI-NEXT:    v_mul_f32_e32 v4, v5, v3
; VI-NEXT:    v_rndne_f32_e32 v4, v4
; VI-NEXT:    v_fma_f32 v4, -v4, v1, v5
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; VI-NEXT:    v_add_f32_e32 v6, v4, v1
; VI-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
; VI-NEXT:    v_add_u32_e32 v2, vcc, -11, v2
; VI-NEXT:    v_ldexp_f32 v4, v4, 11
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v2
; VI-NEXT:    s_cbranch_vccnz .LBB27_3
; VI-NEXT:    s_branch .LBB27_6
; VI-NEXT:  .LBB27_4: ; %frem.else86
; VI-NEXT:    s_and_b32 s4, 0x8000, s16
; VI-NEXT:    v_cmp_eq_f32_e32 vcc, v1, v0
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
; VI-NEXT:    s_branch .LBB27_7
; VI-NEXT:  .LBB27_5:
; VI-NEXT:    v_mov_b32_e32 v5, v4
; VI-NEXT:  .LBB27_6: ; %frem.loop_exit94
; VI-NEXT:    v_add_u32_e32 v2, vcc, -10, v2
; VI-NEXT:    v_ldexp_f32 v2, v5, v2
; VI-NEXT:    v_mul_f32_e32 v3, v2, v3
; VI-NEXT:    v_rndne_f32_e32 v3, v3
; VI-NEXT:    v_fma_f32 v2, -v3, v1, v2
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v2
; VI-NEXT:    v_add_f32_e32 v1, v2, v1
; VI-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; VI-NEXT:    v_ldexp_f32 v0, v1, v0
; VI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; VI-NEXT:    s_movk_i32 s4, 0x7fff
; VI-NEXT:    v_mov_b32_e32 v1, s16
; VI-NEXT:    v_bfi_b32 v0, s4, v0, v1
; VI-NEXT:  .LBB27_7:
; VI-NEXT:    s_lshr_b32 s4, s16, 16
; VI-NEXT:    s_lshr_b32 s5, s18, 16
; VI-NEXT:    v_cvt_f32_f16_e64 v2, |s4|
; VI-NEXT:    v_cvt_f32_f16_e64 v1, |s5|
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v1
; VI-NEXT:    s_cbranch_vccz .LBB27_11
; VI-NEXT:  ; %bb.8: ; %frem.compute52
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v6, v2
; VI-NEXT:    v_frexp_mant_f32_e32 v2, v2
; VI-NEXT:    v_ldexp_f32 v5, v2, 11
; VI-NEXT:    v_frexp_mant_f32_e32 v2, v1
; VI-NEXT:    v_ldexp_f32 v2, v2, 1
; VI-NEXT:    v_div_scale_f32 v8, s[6:7], v2, v2, 1.0
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v7, v1
; VI-NEXT:    v_add_u32_e32 v1, vcc, -1, v7
; VI-NEXT:    v_not_b32_e32 v3, v1
; VI-NEXT:    v_add_u32_e32 v3, vcc, v3, v6
; VI-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v2, 1.0
; VI-NEXT:    v_rcp_f32_e32 v9, v8
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
; VI-NEXT:    v_fma_f32 v9, v10, v9, v9
; VI-NEXT:    v_mul_f32_e32 v10, v4, v9
; VI-NEXT:    v_fma_f32 v11, -v8, v10, v4
; VI-NEXT:    v_fma_f32 v10, v11, v9, v10
; VI-NEXT:    v_fma_f32 v4, -v8, v10, v4
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; VI-NEXT:    v_div_fmas_f32 v4, v4, v9, v10
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v3
; VI-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; VI-NEXT:    s_cbranch_vccnz .LBB27_12
; VI-NEXT:  ; %bb.9: ; %frem.loop_body60.preheader
; VI-NEXT:    v_sub_u32_e32 v3, vcc, v6, v7
; VI-NEXT:    v_add_u32_e32 v3, vcc, 11, v3
; VI-NEXT:  .LBB27_10: ; %frem.loop_body60
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v6, v5
; VI-NEXT:    v_mul_f32_e32 v5, v6, v4
; VI-NEXT:    v_rndne_f32_e32 v5, v5
; VI-NEXT:    v_fma_f32 v5, -v5, v2, v6
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
; VI-NEXT:    v_add_f32_e32 v7, v5, v2
; VI-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
; VI-NEXT:    v_add_u32_e32 v3, vcc, -11, v3
; VI-NEXT:    v_ldexp_f32 v5, v5, 11
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v3
; VI-NEXT:    s_cbranch_vccnz .LBB27_10
; VI-NEXT:    s_branch .LBB27_13
; VI-NEXT:  .LBB27_11: ; %frem.else53
; VI-NEXT:    s_and_b32 s6, 0x8000, s4
; VI-NEXT:    v_cmp_eq_f32_e32 vcc, v2, v1
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_mov_b32_e32 v2, s6
; VI-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
; VI-NEXT:    s_branch .LBB27_14
; VI-NEXT:  .LBB27_12:
; VI-NEXT:    v_mov_b32_e32 v6, v5
; VI-NEXT:  .LBB27_13: ; %frem.loop_exit61
; VI-NEXT:    v_add_u32_e32 v3, vcc, -10, v3
; VI-NEXT:    v_ldexp_f32 v3, v6, v3
; VI-NEXT:    v_mul_f32_e32 v4, v3, v4
; VI-NEXT:    v_rndne_f32_e32 v4, v4
; VI-NEXT:    v_fma_f32 v3, -v4, v2, v3
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v3
; VI-NEXT:    v_add_f32_e32 v2, v3, v2
; VI-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; VI-NEXT:    v_ldexp_f32 v1, v2, v1
; VI-NEXT:    v_cvt_f16_f32_e32 v1, v1
; VI-NEXT:    s_movk_i32 s6, 0x7fff
; VI-NEXT:    v_mov_b32_e32 v2, s4
; VI-NEXT:    v_bfi_b32 v1, s6, v1, v2
; VI-NEXT:  .LBB27_14:
; VI-NEXT:    v_cvt_f32_f16_e64 v3, |s17|
; VI-NEXT:    v_cvt_f32_f16_e64 v2, |s19|
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, v3, v2
; VI-NEXT:    s_cbranch_vccz .LBB27_18
; VI-NEXT:  ; %bb.15: ; %frem.compute19
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v7, v3
; VI-NEXT:    v_frexp_mant_f32_e32 v3, v3
; VI-NEXT:    v_ldexp_f32 v6, v3, 11
; VI-NEXT:    v_frexp_mant_f32_e32 v3, v2
; VI-NEXT:    v_ldexp_f32 v3, v3, 1
; VI-NEXT:    v_div_scale_f32 v9, s[6:7], v3, v3, 1.0
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v8, v2
; VI-NEXT:    v_add_u32_e32 v2, vcc, -1, v8
; VI-NEXT:    v_not_b32_e32 v4, v2
; VI-NEXT:    v_add_u32_e32 v4, vcc, v4, v7
; VI-NEXT:    v_div_scale_f32 v5, vcc, 1.0, v3, 1.0
; VI-NEXT:    v_rcp_f32_e32 v10, v9
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; VI-NEXT:    v_fma_f32 v10, v11, v10, v10
; VI-NEXT:    v_mul_f32_e32 v11, v5, v10
; VI-NEXT:    v_fma_f32 v12, -v9, v11, v5
; VI-NEXT:    v_fma_f32 v11, v12, v10, v11
; VI-NEXT:    v_fma_f32 v5, -v9, v11, v5
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; VI-NEXT:    v_div_fmas_f32 v5, v5, v10, v11
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v4
; VI-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
; VI-NEXT:    s_cbranch_vccnz .LBB27_19
; VI-NEXT:  ; %bb.16: ; %frem.loop_body27.preheader
; VI-NEXT:    v_sub_u32_e32 v4, vcc, v7, v8
; VI-NEXT:    v_add_u32_e32 v4, vcc, 11, v4
; VI-NEXT:  .LBB27_17: ; %frem.loop_body27
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v7, v6
; VI-NEXT:    v_mul_f32_e32 v6, v7, v5
; VI-NEXT:    v_rndne_f32_e32 v6, v6
; VI-NEXT:    v_fma_f32 v6, -v6, v3, v7
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v6
; VI-NEXT:    v_add_f32_e32 v8, v6, v3
; VI-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc
; VI-NEXT:    v_add_u32_e32 v4, vcc, -11, v4
; VI-NEXT:    v_ldexp_f32 v6, v6, 11
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v4
; VI-NEXT:    s_cbranch_vccnz .LBB27_17
; VI-NEXT:    s_branch .LBB27_20
; VI-NEXT:  .LBB27_18: ; %frem.else20
; VI-NEXT:    s_and_b32 s6, 0x8000, s17
; VI-NEXT:    v_cmp_eq_f32_e32 vcc, v3, v2
; VI-NEXT:    v_mov_b32_e32 v2, s17
; VI-NEXT:    v_mov_b32_e32 v3, s6
; VI-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
; VI-NEXT:    s_branch .LBB27_21
; VI-NEXT:  .LBB27_19:
; VI-NEXT:    v_mov_b32_e32 v7, v6
; VI-NEXT:  .LBB27_20: ; %frem.loop_exit28
; VI-NEXT:    v_add_u32_e32 v4, vcc, -10, v4
; VI-NEXT:    v_ldexp_f32 v4, v7, v4
; VI-NEXT:    v_mul_f32_e32 v5, v4, v5
; VI-NEXT:    v_rndne_f32_e32 v5, v5
; VI-NEXT:    v_fma_f32 v4, -v5, v3, v4
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; VI-NEXT:    v_add_f32_e32 v3, v4, v3
; VI-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; VI-NEXT:    v_ldexp_f32 v2, v3, v2
; VI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; VI-NEXT:    s_movk_i32 s6, 0x7fff
; VI-NEXT:    v_mov_b32_e32 v3, s17
; VI-NEXT:    v_bfi_b32 v2, s6, v2, v3
; VI-NEXT:  .LBB27_21:
; VI-NEXT:    s_lshr_b32 s6, s17, 16
; VI-NEXT:    s_lshr_b32 s7, s19, 16
; VI-NEXT:    v_cvt_f32_f16_e64 v4, |s6|
; VI-NEXT:    v_cvt_f32_f16_e64 v3, |s7|
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, v4, v3
; VI-NEXT:    s_cbranch_vccz .LBB27_25
; VI-NEXT:  ; %bb.22: ; %frem.compute
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v8, v4
; VI-NEXT:    v_frexp_mant_f32_e32 v4, v4
; VI-NEXT:    v_ldexp_f32 v7, v4, 11
; VI-NEXT:    v_frexp_mant_f32_e32 v4, v3
; VI-NEXT:    v_ldexp_f32 v4, v4, 1
; VI-NEXT:    v_div_scale_f32 v10, s[8:9], v4, v4, 1.0
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v9, v3
; VI-NEXT:    v_add_u32_e32 v3, vcc, -1, v9
; VI-NEXT:    v_not_b32_e32 v5, v3
; VI-NEXT:    v_add_u32_e32 v5, vcc, v5, v8
; VI-NEXT:    v_div_scale_f32 v6, vcc, 1.0, v4, 1.0
; VI-NEXT:    v_rcp_f32_e32 v11, v10
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT:    v_fma_f32 v12, -v10, v11, 1.0
; VI-NEXT:    v_fma_f32 v11, v12, v11, v11
; VI-NEXT:    v_mul_f32_e32 v12, v6, v11
; VI-NEXT:    v_fma_f32 v13, -v10, v12, v6
; VI-NEXT:    v_fma_f32 v12, v13, v11, v12
; VI-NEXT:    v_fma_f32 v6, -v10, v12, v6
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; VI-NEXT:    v_div_fmas_f32 v6, v6, v11, v12
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v5
; VI-NEXT:    v_div_fixup_f32 v6, v6, v4, 1.0
; VI-NEXT:    s_cbranch_vccnz .LBB27_26
; VI-NEXT:  ; %bb.23: ; %frem.loop_body.preheader
; VI-NEXT:    v_sub_u32_e32 v5, vcc, v8, v9
; VI-NEXT:    v_add_u32_e32 v5, vcc, 11, v5
; VI-NEXT:  .LBB27_24: ; %frem.loop_body
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v8, v7
; VI-NEXT:    v_mul_f32_e32 v7, v8, v6
; VI-NEXT:    v_rndne_f32_e32 v7, v7
; VI-NEXT:    v_fma_f32 v7, -v7, v4, v8
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v7
; VI-NEXT:    v_add_f32_e32 v9, v7, v4
; VI-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc
; VI-NEXT:    v_add_u32_e32 v5, vcc, -11, v5
; VI-NEXT:    v_ldexp_f32 v7, v7, 11
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v5
; VI-NEXT:    s_cbranch_vccnz .LBB27_24
; VI-NEXT:    s_branch .LBB27_27
; VI-NEXT:  .LBB27_25: ; %frem.else
; VI-NEXT:    s_and_b32 s8, 0x8000, s6
; VI-NEXT:    v_cmp_eq_f32_e32 vcc, v4, v3
; VI-NEXT:    v_mov_b32_e32 v3, s6
; VI-NEXT:    v_mov_b32_e32 v4, s8
; VI-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
; VI-NEXT:    s_branch .LBB27_28
; VI-NEXT:  .LBB27_26:
; VI-NEXT:    v_mov_b32_e32 v8, v7
; VI-NEXT:  .LBB27_27: ; %frem.loop_exit
; VI-NEXT:    v_add_u32_e32 v5, vcc, -10, v5
; VI-NEXT:    v_ldexp_f32 v5, v8, v5
; VI-NEXT:    v_mul_f32_e32 v6, v5, v6
; VI-NEXT:    v_rndne_f32_e32 v6, v6
; VI-NEXT:    v_fma_f32 v5, -v6, v4, v5
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
; VI-NEXT:    v_add_f32_e32 v4, v5, v4
; VI-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc
; VI-NEXT:    v_ldexp_f32 v3, v4, v3
; VI-NEXT:    v_cvt_f16_f32_e32 v3, v3
; VI-NEXT:    s_movk_i32 s8, 0x7fff
; VI-NEXT:    v_mov_b32_e32 v4, s6
; VI-NEXT:    v_bfi_b32 v3, s8, v3, v4
; VI-NEXT:  .LBB27_28:
; VI-NEXT:    v_mov_b32_e32 v4, 0x7c00
; VI-NEXT:    v_cmp_lg_f16_e64 s[8:9], s18, 0
; VI-NEXT:    v_cmp_nge_f16_e64 s[10:11], |s16|, v4
; VI-NEXT:    s_and_b64 vcc, s[10:11], s[8:9]
; VI-NEXT:    v_mov_b32_e32 v5, 0x7e00
; VI-NEXT:    v_cmp_lg_f16_e64 s[8:9], s5, 0
; VI-NEXT:    v_cmp_nge_f16_e64 s[4:5], |s4|, v4
; VI-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc
; VI-NEXT:    s_and_b64 vcc, s[4:5], s[8:9]
; VI-NEXT:    v_cmp_lg_f16_e64 s[4:5], s19, 0
; VI-NEXT:    v_cmp_nge_f16_e64 s[8:9], |s17|, v4
; VI-NEXT:    v_cndmask_b32_sdwa v1, v5, v1, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    s_and_b64 vcc, s[8:9], s[4:5]
; VI-NEXT:    v_cmp_lg_f16_e64 s[4:5], s7, 0
; VI-NEXT:    v_cmp_nge_f16_e64 s[6:7], |s6|, v4
; VI-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
; VI-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; VI-NEXT:    v_cndmask_b32_sdwa v3, v5, v3, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT:    v_or_b32_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: frem_v4f16_uniform:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_f32_f16_e64 v1, |s16|
; GFX9-NEXT:    v_cvt_f32_f16_e64 v0, |s18|
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v0
; GFX9-NEXT:    s_cbranch_vccz .LBB27_4
; GFX9-NEXT:  ; %bb.1: ; %frem.compute85
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v5, v1
; GFX9-NEXT:    v_frexp_mant_f32_e32 v1, v1
; GFX9-NEXT:    v_ldexp_f32 v4, v1, 11
; GFX9-NEXT:    v_frexp_mant_f32_e32 v1, v0
; GFX9-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX9-NEXT:    v_div_scale_f32 v7, s[4:5], v1, v1, 1.0
; GFX9-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v1, 1.0
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v6, v0
; GFX9-NEXT:    v_add_u32_e32 v0, -1, v6
; GFX9-NEXT:    v_not_b32_e32 v2, v0
; GFX9-NEXT:    v_add_u32_e32 v2, v2, v5
; GFX9-NEXT:    v_rcp_f32_e32 v8, v7
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
; GFX9-NEXT:    v_fma_f32 v8, v9, v8, v8
; GFX9-NEXT:    v_mul_f32_e32 v9, v3, v8
; GFX9-NEXT:    v_fma_f32 v10, -v7, v9, v3
; GFX9-NEXT:    v_fma_f32 v9, v10, v8, v9
; GFX9-NEXT:    v_fma_f32 v3, -v7, v9, v3
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX9-NEXT:    v_div_fmas_f32 v3, v3, v8, v9
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v2
; GFX9-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX9-NEXT:    s_cbranch_vccnz .LBB27_5
; GFX9-NEXT:  ; %bb.2: ; %frem.loop_body93.preheader
; GFX9-NEXT:    v_sub_u32_e32 v2, v5, v6
; GFX9-NEXT:    v_add_u32_e32 v2, 11, v2
; GFX9-NEXT:  .LBB27_3: ; %frem.loop_body93
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v5, v4
; GFX9-NEXT:    v_mul_f32_e32 v4, v5, v3
; GFX9-NEXT:    v_rndne_f32_e32 v4, v4
; GFX9-NEXT:    v_fma_f32 v4, -v4, v1, v5
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; GFX9-NEXT:    v_add_f32_e32 v6, v4, v1
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX9-NEXT:    v_add_u32_e32 v2, -11, v2
; GFX9-NEXT:    v_ldexp_f32 v4, v4, 11
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v2
; GFX9-NEXT:    s_cbranch_vccnz .LBB27_3
; GFX9-NEXT:    s_branch .LBB27_6
; GFX9-NEXT:  .LBB27_4: ; %frem.else86
; GFX9-NEXT:    s_and_b32 s4, 0x8000, s16
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, v1, v0
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s4
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX9-NEXT:    s_branch .LBB27_7
; GFX9-NEXT:  .LBB27_5:
; GFX9-NEXT:    v_mov_b32_e32 v5, v4
; GFX9-NEXT:  .LBB27_6: ; %frem.loop_exit94
; GFX9-NEXT:    v_add_u32_e32 v2, -10, v2
; GFX9-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX9-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX9-NEXT:    v_rndne_f32_e32 v3, v3
; GFX9-NEXT:    v_fma_f32 v2, -v3, v1, v2
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v2
; GFX9-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX9-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX9-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX9-NEXT:    s_movk_i32 s4, 0x7fff
; GFX9-NEXT:    v_mov_b32_e32 v1, s16
; GFX9-NEXT:    v_bfi_b32 v0, s4, v0, v1
; GFX9-NEXT:  .LBB27_7:
; GFX9-NEXT:    s_lshr_b32 s4, s16, 16
; GFX9-NEXT:    s_lshr_b32 s5, s18, 16
; GFX9-NEXT:    v_cvt_f32_f16_e64 v2, |s4|
; GFX9-NEXT:    v_cvt_f32_f16_e64 v1, |s5|
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v1
; GFX9-NEXT:    s_cbranch_vccz .LBB27_11
; GFX9-NEXT:  ; %bb.8: ; %frem.compute52
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v6, v2
; GFX9-NEXT:    v_frexp_mant_f32_e32 v2, v2
; GFX9-NEXT:    v_ldexp_f32 v5, v2, 11
; GFX9-NEXT:    v_frexp_mant_f32_e32 v2, v1
; GFX9-NEXT:    v_ldexp_f32 v2, v2, 1
; GFX9-NEXT:    v_div_scale_f32 v8, s[6:7], v2, v2, 1.0
; GFX9-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v2, 1.0
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v7, v1
; GFX9-NEXT:    v_add_u32_e32 v1, -1, v7
; GFX9-NEXT:    v_not_b32_e32 v3, v1
; GFX9-NEXT:    v_add_u32_e32 v3, v3, v6
; GFX9-NEXT:    v_rcp_f32_e32 v9, v8
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
; GFX9-NEXT:    v_fma_f32 v9, v10, v9, v9
; GFX9-NEXT:    v_mul_f32_e32 v10, v4, v9
; GFX9-NEXT:    v_fma_f32 v11, -v8, v10, v4
; GFX9-NEXT:    v_fma_f32 v10, v11, v9, v10
; GFX9-NEXT:    v_fma_f32 v4, -v8, v10, v4
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX9-NEXT:    v_div_fmas_f32 v4, v4, v9, v10
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v3
; GFX9-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; GFX9-NEXT:    s_cbranch_vccnz .LBB27_12
; GFX9-NEXT:  ; %bb.9: ; %frem.loop_body60.preheader
; GFX9-NEXT:    v_sub_u32_e32 v3, v6, v7
; GFX9-NEXT:    v_add_u32_e32 v3, 11, v3
; GFX9-NEXT:  .LBB27_10: ; %frem.loop_body60
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v6, v5
; GFX9-NEXT:    v_mul_f32_e32 v5, v6, v4
; GFX9-NEXT:    v_rndne_f32_e32 v5, v5
; GFX9-NEXT:    v_fma_f32 v5, -v5, v2, v6
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
; GFX9-NEXT:    v_add_f32_e32 v7, v5, v2
; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
; GFX9-NEXT:    v_add_u32_e32 v3, -11, v3
; GFX9-NEXT:    v_ldexp_f32 v5, v5, 11
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v3
; GFX9-NEXT:    s_cbranch_vccnz .LBB27_10
; GFX9-NEXT:    s_branch .LBB27_13
; GFX9-NEXT:  .LBB27_11: ; %frem.else53
; GFX9-NEXT:    s_and_b32 s6, 0x8000, s4
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, v2, v1
; GFX9-NEXT:    v_mov_b32_e32 v1, s4
; GFX9-NEXT:    v_mov_b32_e32 v2, s6
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX9-NEXT:    s_branch .LBB27_14
; GFX9-NEXT:  .LBB27_12:
; GFX9-NEXT:    v_mov_b32_e32 v6, v5
; GFX9-NEXT:  .LBB27_13: ; %frem.loop_exit61
; GFX9-NEXT:    v_add_u32_e32 v3, -10, v3
; GFX9-NEXT:    v_ldexp_f32 v3, v6, v3
; GFX9-NEXT:    v_mul_f32_e32 v4, v3, v4
; GFX9-NEXT:    v_rndne_f32_e32 v4, v4
; GFX9-NEXT:    v_fma_f32 v3, -v4, v2, v3
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v3
; GFX9-NEXT:    v_add_f32_e32 v2, v3, v2
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX9-NEXT:    v_ldexp_f32 v1, v2, v1
; GFX9-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX9-NEXT:    s_movk_i32 s6, 0x7fff
; GFX9-NEXT:    v_mov_b32_e32 v2, s4
; GFX9-NEXT:    v_bfi_b32 v1, s6, v1, v2
; GFX9-NEXT:  .LBB27_14:
; GFX9-NEXT:    v_cvt_f32_f16_e64 v3, |s17|
; GFX9-NEXT:    v_cvt_f32_f16_e64 v2, |s19|
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v3, v2
; GFX9-NEXT:    s_cbranch_vccz .LBB27_18
; GFX9-NEXT:  ; %bb.15: ; %frem.compute19
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v7, v3
; GFX9-NEXT:    v_frexp_mant_f32_e32 v3, v3
; GFX9-NEXT:    v_ldexp_f32 v6, v3, 11
; GFX9-NEXT:    v_frexp_mant_f32_e32 v3, v2
; GFX9-NEXT:    v_ldexp_f32 v3, v3, 1
; GFX9-NEXT:    v_div_scale_f32 v9, s[6:7], v3, v3, 1.0
; GFX9-NEXT:    v_div_scale_f32 v5, vcc, 1.0, v3, 1.0
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v8, v2
; GFX9-NEXT:    v_add_u32_e32 v2, -1, v8
; GFX9-NEXT:    v_not_b32_e32 v4, v2
; GFX9-NEXT:    v_add_u32_e32 v4, v4, v7
; GFX9-NEXT:    v_rcp_f32_e32 v10, v9
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; GFX9-NEXT:    v_fma_f32 v10, v11, v10, v10
; GFX9-NEXT:    v_mul_f32_e32 v11, v5, v10
; GFX9-NEXT:    v_fma_f32 v12, -v9, v11, v5
; GFX9-NEXT:    v_fma_f32 v11, v12, v10, v11
; GFX9-NEXT:    v_fma_f32 v5, -v9, v11, v5
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX9-NEXT:    v_div_fmas_f32 v5, v5, v10, v11
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v4
; GFX9-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
; GFX9-NEXT:    s_cbranch_vccnz .LBB27_19
; GFX9-NEXT:  ; %bb.16: ; %frem.loop_body27.preheader
; GFX9-NEXT:    v_sub_u32_e32 v4, v7, v8
; GFX9-NEXT:    v_add_u32_e32 v4, 11, v4
; GFX9-NEXT:  .LBB27_17: ; %frem.loop_body27
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v7, v6
; GFX9-NEXT:    v_mul_f32_e32 v6, v7, v5
; GFX9-NEXT:    v_rndne_f32_e32 v6, v6
; GFX9-NEXT:    v_fma_f32 v6, -v6, v3, v7
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v6
; GFX9-NEXT:    v_add_f32_e32 v8, v6, v3
; GFX9-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc
; GFX9-NEXT:    v_add_u32_e32 v4, -11, v4
; GFX9-NEXT:    v_ldexp_f32 v6, v6, 11
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v4
; GFX9-NEXT:    s_cbranch_vccnz .LBB27_17
; GFX9-NEXT:    s_branch .LBB27_20
; GFX9-NEXT:  .LBB27_18: ; %frem.else20
; GFX9-NEXT:    s_and_b32 s6, 0x8000, s17
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, v3, v2
; GFX9-NEXT:    v_mov_b32_e32 v2, s17
; GFX9-NEXT:    v_mov_b32_e32 v3, s6
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX9-NEXT:    s_branch .LBB27_21
; GFX9-NEXT:  .LBB27_19:
; GFX9-NEXT:    v_mov_b32_e32 v7, v6
; GFX9-NEXT:  .LBB27_20: ; %frem.loop_exit28
; GFX9-NEXT:    v_add_u32_e32 v4, -10, v4
; GFX9-NEXT:    v_ldexp_f32 v4, v7, v4
; GFX9-NEXT:    v_mul_f32_e32 v5, v4, v5
; GFX9-NEXT:    v_rndne_f32_e32 v5, v5
; GFX9-NEXT:    v_fma_f32 v4, -v5, v3, v4
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; GFX9-NEXT:    v_add_f32_e32 v3, v4, v3
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX9-NEXT:    v_ldexp_f32 v2, v3, v2
; GFX9-NEXT:    v_cvt_f16_f32_e32 v2, v2
; GFX9-NEXT:    s_movk_i32 s6, 0x7fff
; GFX9-NEXT:    v_mov_b32_e32 v3, s17
; GFX9-NEXT:    v_bfi_b32 v2, s6, v2, v3
; GFX9-NEXT:  .LBB27_21:
; GFX9-NEXT:    s_lshr_b32 s6, s17, 16
; GFX9-NEXT:    s_lshr_b32 s7, s19, 16
; GFX9-NEXT:    v_cvt_f32_f16_e64 v4, |s6|
; GFX9-NEXT:    v_cvt_f32_f16_e64 v3, |s7|
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v4, v3
; GFX9-NEXT:    s_cbranch_vccz .LBB27_25
; GFX9-NEXT:  ; %bb.22: ; %frem.compute
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v8, v4
; GFX9-NEXT:    v_frexp_mant_f32_e32 v4, v4
; GFX9-NEXT:    v_ldexp_f32 v7, v4, 11
; GFX9-NEXT:    v_frexp_mant_f32_e32 v4, v3
; GFX9-NEXT:    v_ldexp_f32 v4, v4, 1
; GFX9-NEXT:    v_div_scale_f32 v10, s[8:9], v4, v4, 1.0
; GFX9-NEXT:    v_div_scale_f32 v6, vcc, 1.0, v4, 1.0
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v9, v3
; GFX9-NEXT:    v_add_u32_e32 v3, -1, v9
; GFX9-NEXT:    v_not_b32_e32 v5, v3
; GFX9-NEXT:    v_add_u32_e32 v5, v5, v8
; GFX9-NEXT:    v_rcp_f32_e32 v11, v10
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT:    v_fma_f32 v12, -v10, v11, 1.0
; GFX9-NEXT:    v_fma_f32 v11, v12, v11, v11
; GFX9-NEXT:    v_mul_f32_e32 v12, v6, v11
; GFX9-NEXT:    v_fma_f32 v13, -v10, v12, v6
; GFX9-NEXT:    v_fma_f32 v12, v13, v11, v12
; GFX9-NEXT:    v_fma_f32 v6, -v10, v12, v6
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX9-NEXT:    v_div_fmas_f32 v6, v6, v11, v12
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v5
; GFX9-NEXT:    v_div_fixup_f32 v6, v6, v4, 1.0
; GFX9-NEXT:    s_cbranch_vccnz .LBB27_26
; GFX9-NEXT:  ; %bb.23: ; %frem.loop_body.preheader
; GFX9-NEXT:    v_sub_u32_e32 v5, v8, v9
; GFX9-NEXT:    v_add_u32_e32 v5, 11, v5
; GFX9-NEXT:  .LBB27_24: ; %frem.loop_body
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v8, v7
; GFX9-NEXT:    v_mul_f32_e32 v7, v8, v6
; GFX9-NEXT:    v_rndne_f32_e32 v7, v7
; GFX9-NEXT:    v_fma_f32 v7, -v7, v4, v8
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v7
; GFX9-NEXT:    v_add_f32_e32 v9, v7, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc
; GFX9-NEXT:    v_add_u32_e32 v5, -11, v5
; GFX9-NEXT:    v_ldexp_f32 v7, v7, 11
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v5
; GFX9-NEXT:    s_cbranch_vccnz .LBB27_24
; GFX9-NEXT:    s_branch .LBB27_27
; GFX9-NEXT:  .LBB27_25: ; %frem.else
; GFX9-NEXT:    s_and_b32 s8, 0x8000, s6
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, v4, v3
; GFX9-NEXT:    v_mov_b32_e32 v3, s6
; GFX9-NEXT:    v_mov_b32_e32 v4, s8
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX9-NEXT:    s_branch .LBB27_28
; GFX9-NEXT:  .LBB27_26:
; GFX9-NEXT:    v_mov_b32_e32 v8, v7
; GFX9-NEXT:  .LBB27_27: ; %frem.loop_exit
; GFX9-NEXT:    v_add_u32_e32 v5, -10, v5
; GFX9-NEXT:    v_ldexp_f32 v5, v8, v5
; GFX9-NEXT:    v_mul_f32_e32 v6, v5, v6
; GFX9-NEXT:    v_rndne_f32_e32 v6, v6
; GFX9-NEXT:    v_fma_f32 v5, -v6, v4, v5
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
; GFX9-NEXT:    v_add_f32_e32 v4, v5, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc
; GFX9-NEXT:    v_ldexp_f32 v3, v4, v3
; GFX9-NEXT:    v_cvt_f16_f32_e32 v3, v3
; GFX9-NEXT:    s_movk_i32 s8, 0x7fff
; GFX9-NEXT:    v_mov_b32_e32 v4, s6
; GFX9-NEXT:    v_bfi_b32 v3, s8, v3, v4
; GFX9-NEXT:  .LBB27_28:
; GFX9-NEXT:    v_mov_b32_e32 v4, 0x7c00
; GFX9-NEXT:    v_cmp_lg_f16_e64 s[8:9], s18, 0
; GFX9-NEXT:    v_cmp_nge_f16_e64 s[10:11], |s16|, v4
; GFX9-NEXT:    s_and_b64 vcc, s[10:11], s[8:9]
; GFX9-NEXT:    v_mov_b32_e32 v5, 0x7e00
; GFX9-NEXT:    v_cmp_lg_f16_e64 s[8:9], s5, 0
; GFX9-NEXT:    v_cmp_nge_f16_e64 s[4:5], |s4|, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc
; GFX9-NEXT:    s_and_b64 vcc, s[4:5], s[8:9]
; GFX9-NEXT:    v_cmp_lg_f16_e64 s[4:5], s19, 0
; GFX9-NEXT:    v_cmp_nge_f16_e64 s[8:9], |s17|, v4
; GFX9-NEXT:    v_cndmask_b32_sdwa v1, v5, v1, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    s_and_b64 vcc, s[8:9], s[4:5]
; GFX9-NEXT:    v_cmp_lg_f16_e64 s[4:5], s7, 0
; GFX9-NEXT:    v_cmp_nge_f16_e64 s[6:7], |s6|, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
; GFX9-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; GFX9-NEXT:    v_cndmask_b32_sdwa v3, v5, v3, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_or_b32_sdwa v1, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: frem_v4f16_uniform:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cvt_f32_f16_e64 v1, |s16|
; GFX10-NEXT:    v_cvt_f32_f16_e64 v0, |s18|
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v0
; GFX10-NEXT:    s_cbranch_vccz .LBB27_5
; GFX10-NEXT:  ; %bb.1: ; %frem.compute85
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v3, v1
; GFX10-NEXT:    v_frexp_mant_f32_e32 v1, v1
; GFX10-NEXT:    v_readfirstlane_b32 s4, v3
; GFX10-NEXT:    v_ldexp_f32 v2, v1, 11
; GFX10-NEXT:    v_frexp_mant_f32_e32 v1, v0
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v0, v0
; GFX10-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX10-NEXT:    v_readfirstlane_b32 s5, v0
; GFX10-NEXT:    v_add_nc_u32_e32 v0, -1, v0
; GFX10-NEXT:    v_div_scale_f32 v5, s6, v1, v1, 1.0
; GFX10-NEXT:    v_not_b32_e32 v4, v0
; GFX10-NEXT:    v_rcp_f32_e32 v6, v5
; GFX10-NEXT:    v_add_nc_u32_e32 v4, v4, v3
; GFX10-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX10-NEXT:    s_denorm_mode 15
; GFX10-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
; GFX10-NEXT:    v_fmac_f32_e32 v6, v7, v6
; GFX10-NEXT:    v_mul_f32_e32 v7, v3, v6
; GFX10-NEXT:    v_fma_f32 v8, -v5, v7, v3
; GFX10-NEXT:    v_fmac_f32_e32 v7, v8, v6
; GFX10-NEXT:    v_fma_f32 v3, -v5, v7, v3
; GFX10-NEXT:    s_denorm_mode 12
; GFX10-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX10-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX10-NEXT:    s_cbranch_vccnz .LBB27_6
; GFX10-NEXT:  ; %bb.2: ; %frem.loop_body93.preheader
; GFX10-NEXT:    s_sub_i32 s4, s4, s5
; GFX10-NEXT:    s_add_i32 s4, s4, 11
; GFX10-NEXT:  .LBB27_3: ; %frem.loop_body93
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v5, v2
; GFX10-NEXT:    s_add_i32 s4, s4, -11
; GFX10-NEXT:    s_cmp_gt_i32 s4, 11
; GFX10-NEXT:    v_mul_f32_e32 v2, v5, v3
; GFX10-NEXT:    v_rndne_f32_e32 v2, v2
; GFX10-NEXT:    v_fma_f32 v2, -v2, v1, v5
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX10-NEXT:    v_add_f32_e32 v4, v2, v1
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v2, v2, 11
; GFX10-NEXT:    s_cbranch_scc1 .LBB27_3
; GFX10-NEXT:  ; %bb.4:
; GFX10-NEXT:    v_mov_b32_e32 v4, s4
; GFX10-NEXT:    s_branch .LBB27_7
; GFX10-NEXT:  .LBB27_5: ; %frem.else86
; GFX10-NEXT:    s_and_b32 s4, 0x8000, s16
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v1, v0
; GFX10-NEXT:    v_mov_b32_e32 v0, s4
; GFX10-NEXT:    v_cndmask_b32_e32 v0, s16, v0, vcc_lo
; GFX10-NEXT:    s_branch .LBB27_8
; GFX10-NEXT:  .LBB27_6:
; GFX10-NEXT:    v_mov_b32_e32 v5, v2
; GFX10-NEXT:  .LBB27_7: ; %frem.loop_exit94
; GFX10-NEXT:    v_add_nc_u32_e32 v2, -10, v4
; GFX10-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX10-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX10-NEXT:    v_rndne_f32_e32 v3, v3
; GFX10-NEXT:    v_fma_f32 v2, -v3, v1, v2
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX10-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX10-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX10-NEXT:    v_bfi_b32 v0, 0x7fff, v0, s16
; GFX10-NEXT:  .LBB27_8:
; GFX10-NEXT:    s_lshr_b32 s4, s16, 16
; GFX10-NEXT:    s_lshr_b32 s5, s18, 16
; GFX10-NEXT:    v_cvt_f32_f16_e64 v2, |s4|
; GFX10-NEXT:    v_cvt_f32_f16_e64 v1, |s5|
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v1
; GFX10-NEXT:    s_cbranch_vccz .LBB27_13
; GFX10-NEXT:  ; %bb.9: ; %frem.compute52
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v4, v2
; GFX10-NEXT:    v_frexp_mant_f32_e32 v2, v2
; GFX10-NEXT:    v_readfirstlane_b32 s6, v4
; GFX10-NEXT:    v_ldexp_f32 v3, v2, 11
; GFX10-NEXT:    v_frexp_mant_f32_e32 v2, v1
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v1, v1
; GFX10-NEXT:    v_ldexp_f32 v2, v2, 1
; GFX10-NEXT:    v_readfirstlane_b32 s7, v1
; GFX10-NEXT:    v_add_nc_u32_e32 v1, -1, v1
; GFX10-NEXT:    v_div_scale_f32 v6, s8, v2, v2, 1.0
; GFX10-NEXT:    v_not_b32_e32 v5, v1
; GFX10-NEXT:    v_rcp_f32_e32 v7, v6
; GFX10-NEXT:    v_add_nc_u32_e32 v5, v5, v4
; GFX10-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
; GFX10-NEXT:    s_denorm_mode 15
; GFX10-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
; GFX10-NEXT:    v_fmac_f32_e32 v7, v8, v7
; GFX10-NEXT:    v_mul_f32_e32 v8, v4, v7
; GFX10-NEXT:    v_fma_f32 v9, -v6, v8, v4
; GFX10-NEXT:    v_fmac_f32_e32 v8, v9, v7
; GFX10-NEXT:    v_fma_f32 v4, -v6, v8, v4
; GFX10-NEXT:    s_denorm_mode 12
; GFX10-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX10-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; GFX10-NEXT:    s_cbranch_vccnz .LBB27_14
; GFX10-NEXT:  ; %bb.10: ; %frem.loop_body60.preheader
; GFX10-NEXT:    s_sub_i32 s6, s6, s7
; GFX10-NEXT:    s_add_i32 s6, s6, 11
; GFX10-NEXT:  .LBB27_11: ; %frem.loop_body60
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v6, v3
; GFX10-NEXT:    s_add_i32 s6, s6, -11
; GFX10-NEXT:    s_cmp_gt_i32 s6, 11
; GFX10-NEXT:    v_mul_f32_e32 v3, v6, v4
; GFX10-NEXT:    v_rndne_f32_e32 v3, v3
; GFX10-NEXT:    v_fma_f32 v3, -v3, v2, v6
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX10-NEXT:    v_add_f32_e32 v5, v3, v2
; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v3, v3, 11
; GFX10-NEXT:    s_cbranch_scc1 .LBB27_11
; GFX10-NEXT:  ; %bb.12:
; GFX10-NEXT:    v_mov_b32_e32 v5, s6
; GFX10-NEXT:    s_branch .LBB27_15
; GFX10-NEXT:  .LBB27_13: ; %frem.else53
; GFX10-NEXT:    s_and_b32 s6, 0x8000, s4
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v2, v1
; GFX10-NEXT:    v_mov_b32_e32 v1, s6
; GFX10-NEXT:    v_cndmask_b32_e32 v1, s4, v1, vcc_lo
; GFX10-NEXT:    s_branch .LBB27_16
; GFX10-NEXT:  .LBB27_14:
; GFX10-NEXT:    v_mov_b32_e32 v6, v3
; GFX10-NEXT:  .LBB27_15: ; %frem.loop_exit61
; GFX10-NEXT:    v_add_nc_u32_e32 v3, -10, v5
; GFX10-NEXT:    v_ldexp_f32 v3, v6, v3
; GFX10-NEXT:    v_mul_f32_e32 v4, v3, v4
; GFX10-NEXT:    v_rndne_f32_e32 v4, v4
; GFX10-NEXT:    v_fma_f32 v3, -v4, v2, v3
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX10-NEXT:    v_add_f32_e32 v2, v3, v2
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v1, v2, v1
; GFX10-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX10-NEXT:    v_bfi_b32 v1, 0x7fff, v1, s4
; GFX10-NEXT:  .LBB27_16:
; GFX10-NEXT:    v_cvt_f32_f16_e64 v3, |s17|
; GFX10-NEXT:    v_cvt_f32_f16_e64 v2, |s19|
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v3, v2
; GFX10-NEXT:    s_cbranch_vccz .LBB27_21
; GFX10-NEXT:  ; %bb.17: ; %frem.compute19
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v5, v3
; GFX10-NEXT:    v_frexp_mant_f32_e32 v3, v3
; GFX10-NEXT:    v_readfirstlane_b32 s6, v5
; GFX10-NEXT:    v_ldexp_f32 v4, v3, 11
; GFX10-NEXT:    v_frexp_mant_f32_e32 v3, v2
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v2, v2
; GFX10-NEXT:    v_ldexp_f32 v3, v3, 1
; GFX10-NEXT:    v_readfirstlane_b32 s7, v2
; GFX10-NEXT:    v_add_nc_u32_e32 v2, -1, v2
; GFX10-NEXT:    v_div_scale_f32 v7, s8, v3, v3, 1.0
; GFX10-NEXT:    v_not_b32_e32 v6, v2
; GFX10-NEXT:    v_rcp_f32_e32 v8, v7
; GFX10-NEXT:    v_add_nc_u32_e32 v6, v6, v5
; GFX10-NEXT:    v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX10-NEXT:    s_denorm_mode 15
; GFX10-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
; GFX10-NEXT:    v_fmac_f32_e32 v8, v9, v8
; GFX10-NEXT:    v_mul_f32_e32 v9, v5, v8
; GFX10-NEXT:    v_fma_f32 v10, -v7, v9, v5
; GFX10-NEXT:    v_fmac_f32_e32 v9, v10, v8
; GFX10-NEXT:    v_fma_f32 v5, -v7, v9, v5
; GFX10-NEXT:    s_denorm_mode 12
; GFX10-NEXT:    v_div_fmas_f32 v5, v5, v8, v9
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX10-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
; GFX10-NEXT:    s_cbranch_vccnz .LBB27_22
; GFX10-NEXT:  ; %bb.18: ; %frem.loop_body27.preheader
; GFX10-NEXT:    s_sub_i32 s6, s6, s7
; GFX10-NEXT:    s_add_i32 s6, s6, 11
; GFX10-NEXT:  .LBB27_19: ; %frem.loop_body27
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v7, v4
; GFX10-NEXT:    s_add_i32 s6, s6, -11
; GFX10-NEXT:    s_cmp_gt_i32 s6, 11
; GFX10-NEXT:    v_mul_f32_e32 v4, v7, v5
; GFX10-NEXT:    v_rndne_f32_e32 v4, v4
; GFX10-NEXT:    v_fma_f32 v4, -v4, v3, v7
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX10-NEXT:    v_add_f32_e32 v6, v4, v3
; GFX10-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v4, v4, 11
; GFX10-NEXT:    s_cbranch_scc1 .LBB27_19
; GFX10-NEXT:  ; %bb.20:
; GFX10-NEXT:    v_mov_b32_e32 v6, s6
; GFX10-NEXT:    s_branch .LBB27_23
; GFX10-NEXT:  .LBB27_21: ; %frem.else20
; GFX10-NEXT:    s_and_b32 s6, 0x8000, s17
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v3, v2
; GFX10-NEXT:    v_mov_b32_e32 v2, s6
; GFX10-NEXT:    v_cndmask_b32_e32 v2, s17, v2, vcc_lo
; GFX10-NEXT:    s_branch .LBB27_24
; GFX10-NEXT:  .LBB27_22:
; GFX10-NEXT:    v_mov_b32_e32 v7, v4
; GFX10-NEXT:  .LBB27_23: ; %frem.loop_exit28
; GFX10-NEXT:    v_add_nc_u32_e32 v4, -10, v6
; GFX10-NEXT:    v_ldexp_f32 v4, v7, v4
; GFX10-NEXT:    v_mul_f32_e32 v5, v4, v5
; GFX10-NEXT:    v_rndne_f32_e32 v5, v5
; GFX10-NEXT:    v_fma_f32 v4, -v5, v3, v4
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX10-NEXT:    v_add_f32_e32 v3, v4, v3
; GFX10-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v2, v3, v2
; GFX10-NEXT:    v_cvt_f16_f32_e32 v2, v2
; GFX10-NEXT:    v_bfi_b32 v2, 0x7fff, v2, s17
; GFX10-NEXT:  .LBB27_24:
; GFX10-NEXT:    s_lshr_b32 s6, s17, 16
; GFX10-NEXT:    s_lshr_b32 s7, s19, 16
; GFX10-NEXT:    v_cvt_f32_f16_e64 v4, |s6|
; GFX10-NEXT:    v_cvt_f32_f16_e64 v3, |s7|
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v4, v3
; GFX10-NEXT:    s_cbranch_vccz .LBB27_29
; GFX10-NEXT:  ; %bb.25: ; %frem.compute
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v6, v4
; GFX10-NEXT:    v_frexp_mant_f32_e32 v4, v4
; GFX10-NEXT:    v_readfirstlane_b32 s8, v6
; GFX10-NEXT:    v_ldexp_f32 v5, v4, 11
; GFX10-NEXT:    v_frexp_mant_f32_e32 v4, v3
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v3, v3
; GFX10-NEXT:    v_ldexp_f32 v4, v4, 1
; GFX10-NEXT:    v_readfirstlane_b32 s9, v3
; GFX10-NEXT:    v_add_nc_u32_e32 v3, -1, v3
; GFX10-NEXT:    v_div_scale_f32 v8, s10, v4, v4, 1.0
; GFX10-NEXT:    v_not_b32_e32 v7, v3
; GFX10-NEXT:    v_rcp_f32_e32 v9, v8
; GFX10-NEXT:    v_add_nc_u32_e32 v7, v7, v6
; GFX10-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v4, 1.0
; GFX10-NEXT:    s_denorm_mode 15
; GFX10-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
; GFX10-NEXT:    v_fmac_f32_e32 v9, v10, v9
; GFX10-NEXT:    v_mul_f32_e32 v10, v6, v9
; GFX10-NEXT:    v_fma_f32 v11, -v8, v10, v6
; GFX10-NEXT:    v_fmac_f32_e32 v10, v11, v9
; GFX10-NEXT:    v_fma_f32 v6, -v8, v10, v6
; GFX10-NEXT:    s_denorm_mode 12
; GFX10-NEXT:    v_div_fmas_f32 v6, v6, v9, v10
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v7
; GFX10-NEXT:    v_div_fixup_f32 v6, v6, v4, 1.0
; GFX10-NEXT:    s_cbranch_vccnz .LBB27_30
; GFX10-NEXT:  ; %bb.26: ; %frem.loop_body.preheader
; GFX10-NEXT:    s_sub_i32 s8, s8, s9
; GFX10-NEXT:    s_add_i32 s8, s8, 11
; GFX10-NEXT:  .LBB27_27: ; %frem.loop_body
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v8, v5
; GFX10-NEXT:    s_add_i32 s8, s8, -11
; GFX10-NEXT:    s_cmp_gt_i32 s8, 11
; GFX10-NEXT:    v_mul_f32_e32 v5, v8, v6
; GFX10-NEXT:    v_rndne_f32_e32 v5, v5
; GFX10-NEXT:    v_fma_f32 v5, -v5, v4, v8
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX10-NEXT:    v_add_f32_e32 v7, v5, v4
; GFX10-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v5, v5, 11
; GFX10-NEXT:    s_cbranch_scc1 .LBB27_27
; GFX10-NEXT:  ; %bb.28:
; GFX10-NEXT:    v_mov_b32_e32 v7, s8
; GFX10-NEXT:    s_branch .LBB27_31
; GFX10-NEXT:  .LBB27_29: ; %frem.else
; GFX10-NEXT:    s_and_b32 s8, 0x8000, s6
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v4, v3
; GFX10-NEXT:    v_mov_b32_e32 v3, s8
; GFX10-NEXT:    v_cndmask_b32_e32 v3, s6, v3, vcc_lo
; GFX10-NEXT:    s_branch .LBB27_32
; GFX10-NEXT:  .LBB27_30:
; GFX10-NEXT:    v_mov_b32_e32 v8, v5
; GFX10-NEXT:  .LBB27_31: ; %frem.loop_exit
; GFX10-NEXT:    v_add_nc_u32_e32 v5, -10, v7
; GFX10-NEXT:    v_ldexp_f32 v5, v8, v5
; GFX10-NEXT:    v_mul_f32_e32 v6, v5, v6
; GFX10-NEXT:    v_rndne_f32_e32 v6, v6
; GFX10-NEXT:    v_fma_f32 v5, -v6, v4, v5
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX10-NEXT:    v_add_f32_e32 v4, v5, v4
; GFX10-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v3, v4, v3
; GFX10-NEXT:    v_cvt_f16_f32_e32 v3, v3
; GFX10-NEXT:    v_bfi_b32 v3, 0x7fff, v3, s6
; GFX10-NEXT:  .LBB27_32:
; GFX10-NEXT:    v_cmp_lg_f16_e64 s8, s18, 0
; GFX10-NEXT:    v_cmp_nge_f16_e64 s9, |s16|, 0x7c00
; GFX10-NEXT:    v_cmp_lg_f16_e64 s5, s5, 0
; GFX10-NEXT:    v_cmp_nge_f16_e64 s4, |s4|, 0x7c00
; GFX10-NEXT:    v_mov_b32_e32 v4, 0x7e00
; GFX10-NEXT:    s_and_b32 vcc_lo, s9, s8
; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v0, vcc_lo
; GFX10-NEXT:    s_and_b32 vcc_lo, s4, s5
; GFX10-NEXT:    v_cmp_lg_f16_e64 s4, s19, 0
; GFX10-NEXT:    v_cmp_nge_f16_e64 s5, |s17|, 0x7c00
; GFX10-NEXT:    v_cndmask_b32_sdwa v1, v4, v1, vcc_lo dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT:    s_and_b32 vcc_lo, s5, s4
; GFX10-NEXT:    v_cmp_lg_f16_e64 s4, s7, 0
; GFX10-NEXT:    v_cmp_nge_f16_e64 s5, |s6|, 0x7c00
; GFX10-NEXT:    v_cndmask_b32_e32 v2, 0x7e00, v2, vcc_lo
; GFX10-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX10-NEXT:    s_and_b32 vcc_lo, s5, s4
; GFX10-NEXT:    v_cndmask_b32_sdwa v3, v4, v3, vcc_lo dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT:    v_or_b32_sdwa v1, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: frem_v4f16_uniform:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v1, |s0|
; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v0, |s2|
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v0
; GFX11-TRUE16-NEXT:    s_cbranch_vccz .LBB27_5
; GFX11-TRUE16-NEXT:  ; %bb.1: ; %frem.compute85
; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, v1
; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v1, v1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s4, v3
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v2, v1, 11
; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v1, v0
; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s5, v0
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v0, -1, v0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX11-TRUE16-NEXT:    v_not_b32_e32 v4, v0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v6, v5
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v4, v4, v3
; GFX11-TRUE16-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX11-TRUE16-NEXT:    s_denorm_mode 15
; GFX11-TRUE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v6, v7, v6
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v7, v3, v6
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v8, -v5, v7, v3
; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v7, v8, v6
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v3, -v5, v7, v3
; GFX11-TRUE16-NEXT:    s_denorm_mode 12
; GFX11-TRUE16-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
; GFX11-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB27_6
; GFX11-TRUE16-NEXT:  ; %bb.2: ; %frem.loop_body93.preheader
; GFX11-TRUE16-NEXT:    s_sub_i32 s4, s4, s5
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT:    s_add_i32 s4, s4, 11
; GFX11-TRUE16-NEXT:  .LBB27_3: ; %frem.loop_body93
; GFX11-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX11-TRUE16-NEXT:    s_add_i32 s4, s4, -11
; GFX11-TRUE16-NEXT:    s_cmp_gt_i32 s4, 11
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v2, v5, v3
; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v2, v2
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v2, -v2, v1, v5
; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX11-TRUE16-NEXT:    v_add_f32_e32 v4, v2, v1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v2, v2, 11
; GFX11-TRUE16-NEXT:    s_cbranch_scc1 .LBB27_3
; GFX11-TRUE16-NEXT:  ; %bb.4:
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v4, s4
; GFX11-TRUE16-NEXT:    s_branch .LBB27_7
; GFX11-TRUE16-NEXT:  .LBB27_5: ; %frem.else86
; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0x8000, s0
; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v1, v0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, s0, v2.l, vcc_lo
; GFX11-TRUE16-NEXT:    s_branch .LBB27_8
; GFX11-TRUE16-NEXT:  .LBB27_6:
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX11-TRUE16-NEXT:  .LBB27_7: ; %frem.loop_exit94
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, -10, v4
; GFX11-TRUE16-NEXT:    s_and_b32 s4, s0, 0x8000
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v3, v3
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v2, -v3, v1, v2
; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX11-TRUE16-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, s4, v0
; GFX11-TRUE16-NEXT:  .LBB27_8:
; GFX11-TRUE16-NEXT:    s_lshr_b32 s4, s0, 16
; GFX11-TRUE16-NEXT:    s_lshr_b32 s5, s2, 16
; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v2, |s4|
; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v1, |s5|
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v1
; GFX11-TRUE16-NEXT:    s_cbranch_vccz .LBB27_13
; GFX11-TRUE16-NEXT:  ; %bb.9: ; %frem.compute52
; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v4, v2
; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v2, v2
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s6, v4
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v3, v2, 11
; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v2, v1
; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v1, v1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v2, v2, 1
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s7, v1
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v1, -1, v1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_div_scale_f32 v6, null, v2, v2, 1.0
; GFX11-TRUE16-NEXT:    v_not_b32_e32 v5, v1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v7, v6
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
; GFX11-TRUE16-NEXT:    s_denorm_mode 15
; GFX11-TRUE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v7, v8, v7
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v8, v4, v7
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v9, -v6, v8, v4
; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v8, v9, v7
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v4, -v6, v8, v4
; GFX11-TRUE16-NEXT:    s_denorm_mode 12
; GFX11-TRUE16-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
; GFX11-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB27_14
; GFX11-TRUE16-NEXT:  ; %bb.10: ; %frem.loop_body60.preheader
; GFX11-TRUE16-NEXT:    s_sub_i32 s6, s6, s7
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT:    s_add_i32 s6, s6, 11
; GFX11-TRUE16-NEXT:  .LBB27_11: ; %frem.loop_body60
; GFX11-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT:    s_add_i32 s6, s6, -11
; GFX11-TRUE16-NEXT:    s_cmp_gt_i32 s6, 11
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v3, v6, v4
; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v3, v3
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v3, -v3, v2, v6
; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX11-TRUE16-NEXT:    v_add_f32_e32 v5, v3, v2
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v3, v3, 11
; GFX11-TRUE16-NEXT:    s_cbranch_scc1 .LBB27_11
; GFX11-TRUE16-NEXT:  ; %bb.12:
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v5, s6
; GFX11-TRUE16-NEXT:    s_branch .LBB27_15
; GFX11-TRUE16-NEXT:  .LBB27_13: ; %frem.else53
; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0x8000, s4
; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v2, v1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, s4, v0.h, vcc_lo
; GFX11-TRUE16-NEXT:    s_branch .LBB27_16
; GFX11-TRUE16-NEXT:  .LBB27_14:
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT:  .LBB27_15: ; %frem.loop_exit61
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v3, -10, v5
; GFX11-TRUE16-NEXT:    s_and_b32 s6, s4, 0x8000
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v3, v6, v3
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v4, v3, v4
; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v4, v4
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v3, -v4, v2, v3
; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, v3, v2
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v1, v2, v1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v1.l, v1
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, s6, v1
; GFX11-TRUE16-NEXT:  .LBB27_16:
; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v3, |s1|
; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v2, |s3|
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v3, v2
; GFX11-TRUE16-NEXT:    s_cbranch_vccz .LBB27_21
; GFX11-TRUE16-NEXT:  ; %bb.17: ; %frem.compute19
; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v5, v3
; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v3, v3
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s6, v5
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v4, v3, 11
; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v3, v2
; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v2, v2
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v3, v3, 1
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s7, v2
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, -1, v2
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_div_scale_f32 v7, null, v3, v3, 1.0
; GFX11-TRUE16-NEXT:    v_not_b32_e32 v6, v2
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v8, v7
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v6, v6, v5
; GFX11-TRUE16-NEXT:    v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX11-TRUE16-NEXT:    s_denorm_mode 15
; GFX11-TRUE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v8, v9, v8
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v9, v5, v8
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v10, -v7, v9, v5
; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v9, v10, v8
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v5, -v7, v9, v5
; GFX11-TRUE16-NEXT:    s_denorm_mode 12
; GFX11-TRUE16-NEXT:    v_div_fmas_f32 v5, v5, v8, v9
; GFX11-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB27_22
; GFX11-TRUE16-NEXT:  ; %bb.18: ; %frem.loop_body27.preheader
; GFX11-TRUE16-NEXT:    s_sub_i32 s6, s6, s7
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT:    s_add_i32 s6, s6, 11
; GFX11-TRUE16-NEXT:  .LBB27_19: ; %frem.loop_body27
; GFX11-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v7, v4
; GFX11-TRUE16-NEXT:    s_add_i32 s6, s6, -11
; GFX11-TRUE16-NEXT:    s_cmp_gt_i32 s6, 11
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v4, v7, v5
; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v4, v4
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v4, -v4, v3, v7
; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX11-TRUE16-NEXT:    v_add_f32_e32 v6, v4, v3
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v4, v4, 11
; GFX11-TRUE16-NEXT:    s_cbranch_scc1 .LBB27_19
; GFX11-TRUE16-NEXT:  ; %bb.20:
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v6, s6
; GFX11-TRUE16-NEXT:    s_branch .LBB27_23
; GFX11-TRUE16-NEXT:  .LBB27_21: ; %frem.else20
; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0x8000, s1
; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v3, v2
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.l, s1, v0.h, vcc_lo
; GFX11-TRUE16-NEXT:    s_branch .LBB27_24
; GFX11-TRUE16-NEXT:  .LBB27_22:
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v7, v4
; GFX11-TRUE16-NEXT:  .LBB27_23: ; %frem.loop_exit28
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v4, -10, v6
; GFX11-TRUE16-NEXT:    s_and_b32 s6, s1, 0x8000
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v4, v7, v4
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v5, v4, v5
; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v4, -v5, v3, v4
; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, v4, v3
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v2, v3, v2
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v2.l, v2
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, s6, v2
; GFX11-TRUE16-NEXT:  .LBB27_24:
; GFX11-TRUE16-NEXT:    s_lshr_b32 s6, s1, 16
; GFX11-TRUE16-NEXT:    s_lshr_b32 s7, s3, 16
; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v4, |s6|
; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v3, |s7|
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v4, v3
; GFX11-TRUE16-NEXT:    s_cbranch_vccz .LBB27_29
; GFX11-TRUE16-NEXT:  ; %bb.25: ; %frem.compute
; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v6, v4
; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v4, v4
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s8, v6
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v5, v4, 11
; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v4, v3
; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, v3
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v4, v4, 1
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s9, v3
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v3, -1, v3
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_div_scale_f32 v8, null, v4, v4, 1.0
; GFX11-TRUE16-NEXT:    v_not_b32_e32 v7, v3
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v9, v8
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v7, v7, v6
; GFX11-TRUE16-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v4, 1.0
; GFX11-TRUE16-NEXT:    s_denorm_mode 15
; GFX11-TRUE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v9, v10, v9
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v10, v6, v9
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v11, -v8, v10, v6
; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v10, v11, v9
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v6, -v8, v10, v6
; GFX11-TRUE16-NEXT:    s_denorm_mode 12
; GFX11-TRUE16-NEXT:    v_div_fmas_f32 v6, v6, v9, v10
; GFX11-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v7
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_div_fixup_f32 v6, v6, v4, 1.0
; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB27_30
; GFX11-TRUE16-NEXT:  ; %bb.26: ; %frem.loop_body.preheader
; GFX11-TRUE16-NEXT:    s_sub_i32 s8, s8, s9
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT:    s_add_i32 s8, s8, 11
; GFX11-TRUE16-NEXT:  .LBB27_27: ; %frem.loop_body
; GFX11-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v8, v5
; GFX11-TRUE16-NEXT:    s_add_i32 s8, s8, -11
; GFX11-TRUE16-NEXT:    s_cmp_gt_i32 s8, 11
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v5, v8, v6
; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v5, -v5, v4, v8
; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX11-TRUE16-NEXT:    v_add_f32_e32 v7, v5, v4
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v5, v5, 11
; GFX11-TRUE16-NEXT:    s_cbranch_scc1 .LBB27_27
; GFX11-TRUE16-NEXT:  ; %bb.28:
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v7, s8
; GFX11-TRUE16-NEXT:    s_branch .LBB27_31
; GFX11-TRUE16-NEXT:  .LBB27_29: ; %frem.else
; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0x8000, s6
; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v4, v3
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_cndmask_b16 v3.l, s6, v0.h, vcc_lo
; GFX11-TRUE16-NEXT:    s_branch .LBB27_32
; GFX11-TRUE16-NEXT:  .LBB27_30:
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v8, v5
; GFX11-TRUE16-NEXT:  .LBB27_31: ; %frem.loop_exit
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v5, -10, v7
; GFX11-TRUE16-NEXT:    s_and_b32 s8, s6, 0x8000
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v5, v8, v5
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v6, v5, v6
; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v6, v6
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_fma_f32 v5, -v6, v4, v5
; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX11-TRUE16-NEXT:    v_add_f32_e32 v4, v5, v4
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc_lo
; GFX11-TRUE16-NEXT:    v_ldexp_f32 v3, v4, v3
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v3.l, v3
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v3, 0x7fff, v3
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, s8, v3
; GFX11-TRUE16-NEXT:  .LBB27_32:
; GFX11-TRUE16-NEXT:    v_cmp_lg_f16_e64 s2, s2, 0
; GFX11-TRUE16-NEXT:    v_cmp_nge_f16_e64 s0, |s0|, 0x7c00
; GFX11-TRUE16-NEXT:    v_cmp_nge_f16_e64 s1, |s1|, 0x7c00
; GFX11-TRUE16-NEXT:    s_and_b32 s0, s0, s2
; GFX11-TRUE16-NEXT:    v_cmp_nge_f16_e64 s2, |s4|, 0x7c00
; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, s0
; GFX11-TRUE16-NEXT:    v_cmp_lg_f16_e64 s0, s5, 0
; GFX11-TRUE16-NEXT:    s_and_b32 s0, s2, s0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, 0x7e00, v1.l, s0
; GFX11-TRUE16-NEXT:    v_cmp_lg_f16_e64 s0, s3, 0
; GFX11-TRUE16-NEXT:    s_and_b32 s0, s1, s0
; GFX11-TRUE16-NEXT:    v_cmp_nge_f16_e64 s1, |s6|, 0x7c00
; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, 0x7e00, v2.l, s0
; GFX11-TRUE16-NEXT:    v_cmp_lg_f16_e64 s0, s7, 0
; GFX11-TRUE16-NEXT:    s_and_b32 s0, s1, s0
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, 0x7e00, v3.l, s0
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: frem_v4f16_uniform:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v1, |s0|
; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v0, |s2|
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v0
; GFX11-FAKE16-NEXT:    s_cbranch_vccz .LBB27_5
; GFX11-FAKE16-NEXT:  ; %bb.1: ; %frem.compute85
; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, v1
; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v1, v1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s4, v3
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v2, v1, 11
; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v1, v0
; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s5, v0
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v0, -1, v0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX11-FAKE16-NEXT:    v_not_b32_e32 v4, v0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v6, v5
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, v4, v3
; GFX11-FAKE16-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX11-FAKE16-NEXT:    s_denorm_mode 15
; GFX11-FAKE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v6, v7, v6
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v7, v3, v6
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v8, -v5, v7, v3
; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v7, v8, v6
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v3, -v5, v7, v3
; GFX11-FAKE16-NEXT:    s_denorm_mode 12
; GFX11-FAKE16-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
; GFX11-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB27_6
; GFX11-FAKE16-NEXT:  ; %bb.2: ; %frem.loop_body93.preheader
; GFX11-FAKE16-NEXT:    s_sub_i32 s4, s4, s5
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT:    s_add_i32 s4, s4, 11
; GFX11-FAKE16-NEXT:  .LBB27_3: ; %frem.loop_body93
; GFX11-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX11-FAKE16-NEXT:    s_add_i32 s4, s4, -11
; GFX11-FAKE16-NEXT:    s_cmp_gt_i32 s4, 11
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v2, v5, v3
; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v2, v2
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v2, -v2, v1, v5
; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX11-FAKE16-NEXT:    v_add_f32_e32 v4, v2, v1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v2, v2, 11
; GFX11-FAKE16-NEXT:    s_cbranch_scc1 .LBB27_3
; GFX11-FAKE16-NEXT:  ; %bb.4:
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, s4
; GFX11-FAKE16-NEXT:    s_branch .LBB27_7
; GFX11-FAKE16-NEXT:  .LBB27_5: ; %frem.else86
; GFX11-FAKE16-NEXT:    s_and_b32 s4, 0x8000, s0
; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v1, v0
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, s4
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, s0, v0, vcc_lo
; GFX11-FAKE16-NEXT:    s_branch .LBB27_8
; GFX11-FAKE16-NEXT:  .LBB27_6:
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX11-FAKE16-NEXT:  .LBB27_7: ; %frem.loop_exit94
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v2, -10, v4
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v3, v3
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v2, -v3, v1, v2
; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX11-FAKE16-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX11-FAKE16-NEXT:    v_bfi_b32 v0, 0x7fff, v0, s0
; GFX11-FAKE16-NEXT:  .LBB27_8:
; GFX11-FAKE16-NEXT:    s_lshr_b32 s4, s0, 16
; GFX11-FAKE16-NEXT:    s_lshr_b32 s5, s2, 16
; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v2, |s4|
; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v1, |s5|
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v1
; GFX11-FAKE16-NEXT:    s_cbranch_vccz .LBB27_13
; GFX11-FAKE16-NEXT:  ; %bb.9: ; %frem.compute52
; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v4, v2
; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v2, v2
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s6, v4
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v3, v2, 11
; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v2, v1
; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v1, v1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v2, v2, 1
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s7, v1
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v1, -1, v1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_div_scale_f32 v6, null, v2, v2, 1.0
; GFX11-FAKE16-NEXT:    v_not_b32_e32 v5, v1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v7, v6
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v5, v5, v4
; GFX11-FAKE16-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
; GFX11-FAKE16-NEXT:    s_denorm_mode 15
; GFX11-FAKE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v8, v4, v7
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v9, -v6, v8, v4
; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v8, v9, v7
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v4, -v6, v8, v4
; GFX11-FAKE16-NEXT:    s_denorm_mode 12
; GFX11-FAKE16-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
; GFX11-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB27_14
; GFX11-FAKE16-NEXT:  ; %bb.10: ; %frem.loop_body60.preheader
; GFX11-FAKE16-NEXT:    s_sub_i32 s6, s6, s7
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT:    s_add_i32 s6, s6, 11
; GFX11-FAKE16-NEXT:  .LBB27_11: ; %frem.loop_body60
; GFX11-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v6, v3
; GFX11-FAKE16-NEXT:    s_add_i32 s6, s6, -11
; GFX11-FAKE16-NEXT:    s_cmp_gt_i32 s6, 11
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v3, v6, v4
; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v3, v3
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v3, -v3, v2, v6
; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX11-FAKE16-NEXT:    v_add_f32_e32 v5, v3, v2
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v3, v3, 11
; GFX11-FAKE16-NEXT:    s_cbranch_scc1 .LBB27_11
; GFX11-FAKE16-NEXT:  ; %bb.12:
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, s6
; GFX11-FAKE16-NEXT:    s_branch .LBB27_15
; GFX11-FAKE16-NEXT:  .LBB27_13: ; %frem.else53
; GFX11-FAKE16-NEXT:    s_and_b32 s6, 0x8000, s4
; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v2, v1
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, s6
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, s4, v1, vcc_lo
; GFX11-FAKE16-NEXT:    s_branch .LBB27_16
; GFX11-FAKE16-NEXT:  .LBB27_14:
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v6, v3
; GFX11-FAKE16-NEXT:  .LBB27_15: ; %frem.loop_exit61
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v3, -10, v5
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v3, v6, v3
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v4, v3, v4
; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v4, v4
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v3, -v4, v2, v3
; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX11-FAKE16-NEXT:    v_add_f32_e32 v2, v3, v2
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v1, v2, v1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX11-FAKE16-NEXT:    v_bfi_b32 v1, 0x7fff, v1, s4
; GFX11-FAKE16-NEXT:  .LBB27_16:
; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v3, |s1|
; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v2, |s3|
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v3, v2
; GFX11-FAKE16-NEXT:    s_cbranch_vccz .LBB27_21
; GFX11-FAKE16-NEXT:  ; %bb.17: ; %frem.compute19
; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v5, v3
; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v3, v3
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s6, v5
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v4, v3, 11
; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v3, v2
; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v2, v2
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v3, v3, 1
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s7, v2
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v2, -1, v2
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_div_scale_f32 v7, null, v3, v3, 1.0
; GFX11-FAKE16-NEXT:    v_not_b32_e32 v6, v2
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v8, v7
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v6, v6, v5
; GFX11-FAKE16-NEXT:    v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX11-FAKE16-NEXT:    s_denorm_mode 15
; GFX11-FAKE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v8, v9, v8
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v9, v5, v8
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v10, -v7, v9, v5
; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v9, v10, v8
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v5, -v7, v9, v5
; GFX11-FAKE16-NEXT:    s_denorm_mode 12
; GFX11-FAKE16-NEXT:    v_div_fmas_f32 v5, v5, v8, v9
; GFX11-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB27_22
; GFX11-FAKE16-NEXT:  ; %bb.18: ; %frem.loop_body27.preheader
; GFX11-FAKE16-NEXT:    s_sub_i32 s6, s6, s7
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT:    s_add_i32 s6, s6, 11
; GFX11-FAKE16-NEXT:  .LBB27_19: ; %frem.loop_body27
; GFX11-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v7, v4
; GFX11-FAKE16-NEXT:    s_add_i32 s6, s6, -11
; GFX11-FAKE16-NEXT:    s_cmp_gt_i32 s6, 11
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v4, v7, v5
; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v4, v4
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v4, -v4, v3, v7
; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX11-FAKE16-NEXT:    v_add_f32_e32 v6, v4, v3
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v4, v4, 11
; GFX11-FAKE16-NEXT:    s_cbranch_scc1 .LBB27_19
; GFX11-FAKE16-NEXT:  ; %bb.20:
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v6, s6
; GFX11-FAKE16-NEXT:    s_branch .LBB27_23
; GFX11-FAKE16-NEXT:  .LBB27_21: ; %frem.else20
; GFX11-FAKE16-NEXT:    s_and_b32 s6, 0x8000, s1
; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v3, v2
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, s6
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, s1, v2, vcc_lo
; GFX11-FAKE16-NEXT:    s_branch .LBB27_24
; GFX11-FAKE16-NEXT:  .LBB27_22:
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v7, v4
; GFX11-FAKE16-NEXT:  .LBB27_23: ; %frem.loop_exit28
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, -10, v6
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v4, v7, v4
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v5, v4, v5
; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v4, -v5, v3, v4
; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, v4, v3
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v2, v3, v2
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v2, v2
; GFX11-FAKE16-NEXT:    v_bfi_b32 v2, 0x7fff, v2, s1
; GFX11-FAKE16-NEXT:  .LBB27_24:
; GFX11-FAKE16-NEXT:    s_lshr_b32 s6, s1, 16
; GFX11-FAKE16-NEXT:    s_lshr_b32 s7, s3, 16
; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v4, |s6|
; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v3, |s7|
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v4, v3
; GFX11-FAKE16-NEXT:    s_cbranch_vccz .LBB27_29
; GFX11-FAKE16-NEXT:  ; %bb.25: ; %frem.compute
; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v6, v4
; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v4, v4
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s8, v6
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v5, v4, 11
; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v4, v3
; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, v3
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v4, v4, 1
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s9, v3
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v3, -1, v3
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_div_scale_f32 v8, null, v4, v4, 1.0
; GFX11-FAKE16-NEXT:    v_not_b32_e32 v7, v3
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v9, v8
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v7, v7, v6
; GFX11-FAKE16-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v4, 1.0
; GFX11-FAKE16-NEXT:    s_denorm_mode 15
; GFX11-FAKE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v9, v10, v9
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v10, v6, v9
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v11, -v8, v10, v6
; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v10, v11, v9
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v6, -v8, v10, v6
; GFX11-FAKE16-NEXT:    s_denorm_mode 12
; GFX11-FAKE16-NEXT:    v_div_fmas_f32 v6, v6, v9, v10
; GFX11-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v7
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT:    v_div_fixup_f32 v6, v6, v4, 1.0
; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB27_30
; GFX11-FAKE16-NEXT:  ; %bb.26: ; %frem.loop_body.preheader
; GFX11-FAKE16-NEXT:    s_sub_i32 s8, s8, s9
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT:    s_add_i32 s8, s8, 11
; GFX11-FAKE16-NEXT:  .LBB27_27: ; %frem.loop_body
; GFX11-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, v5
; GFX11-FAKE16-NEXT:    s_add_i32 s8, s8, -11
; GFX11-FAKE16-NEXT:    s_cmp_gt_i32 s8, 11
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v5, v8, v6
; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v5, -v5, v4, v8
; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX11-FAKE16-NEXT:    v_add_f32_e32 v7, v5, v4
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v5, v5, 11
; GFX11-FAKE16-NEXT:    s_cbranch_scc1 .LBB27_27
; GFX11-FAKE16-NEXT:  ; %bb.28:
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v7, s8
; GFX11-FAKE16-NEXT:    s_branch .LBB27_31
; GFX11-FAKE16-NEXT:  .LBB27_29: ; %frem.else
; GFX11-FAKE16-NEXT:    s_and_b32 s8, 0x8000, s6
; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v4, v3
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v3, s8
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, s6, v3, vcc_lo
; GFX11-FAKE16-NEXT:    s_branch .LBB27_32
; GFX11-FAKE16-NEXT:  .LBB27_30:
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, v5
; GFX11-FAKE16-NEXT:  .LBB27_31: ; %frem.loop_exit
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v5, -10, v7
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v5, v8, v5
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v6, v5, v6
; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v6, v6
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_fma_f32 v5, -v6, v4, v5
; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX11-FAKE16-NEXT:    v_add_f32_e32 v4, v5, v4
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc_lo
; GFX11-FAKE16-NEXT:    v_ldexp_f32 v3, v4, v3
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v3, v3
; GFX11-FAKE16-NEXT:    v_bfi_b32 v3, 0x7fff, v3, s6
; GFX11-FAKE16-NEXT:  .LBB27_32:
; GFX11-FAKE16-NEXT:    v_cmp_lg_f16_e64 s2, s2, 0
; GFX11-FAKE16-NEXT:    v_cmp_nge_f16_e64 s0, |s0|, 0x7c00
; GFX11-FAKE16-NEXT:    v_cmp_nge_f16_e64 s1, |s1|, 0x7c00
; GFX11-FAKE16-NEXT:    s_and_b32 vcc_lo, s0, s2
; GFX11-FAKE16-NEXT:    v_cmp_lg_f16_e64 s0, s5, 0
; GFX11-FAKE16-NEXT:    v_cmp_nge_f16_e64 s2, |s4|, 0x7c00
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v0, vcc_lo
; GFX11-FAKE16-NEXT:    s_and_b32 vcc_lo, s2, s0
; GFX11-FAKE16-NEXT:    v_cmp_lg_f16_e64 s0, s3, 0
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x7e00, v1, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT:    s_and_b32 vcc_lo, s1, s0
; GFX11-FAKE16-NEXT:    v_cmp_lg_f16_e64 s0, s7, 0
; GFX11-FAKE16-NEXT:    v_cmp_nge_f16_e64 s1, |s6|, 0x7c00
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, 0x7e00, v2, vcc_lo
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT:    s_and_b32 vcc_lo, s1, s0
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, 0x7e00, v3, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v2
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v3, 16, v1
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-TRUE16-LABEL: frem_v4f16_uniform:
; GFX1150-TRUE16:       ; %bb.0:
; GFX1150-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-TRUE16-NEXT:    s_and_b32 s4, s0, 0x7fff
; GFX1150-TRUE16-NEXT:    s_and_b32 s6, s2, 0x7fff
; GFX1150-TRUE16-NEXT:    s_cvt_f32_f16 s5, s4
; GFX1150-TRUE16-NEXT:    s_cvt_f32_f16 s6, s6
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
; GFX1150-TRUE16-NEXT:    s_cmp_gt_f32 s5, s6
; GFX1150-TRUE16-NEXT:    s_cbranch_scc0 .LBB27_5
; GFX1150-TRUE16-NEXT:  ; %bb.1: ; %frem.compute85
; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v1, s6
; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v0, s5
; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, s5
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v2, v0, 11
; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v0, s6
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s5, v3
; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s6, v0
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v0, -1, v0
; GFX1150-TRUE16-NEXT:    v_rcp_f32_e32 v6, v5
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_not_b32_e32 v4, v0
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v4, v4, v3
; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX1150-TRUE16-NEXT:    s_denorm_mode 15
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v6, v7, v6
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v7, v3, v6
; GFX1150-TRUE16-NEXT:    v_fma_f32 v8, -v5, v7, v3
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v7, v8, v6
; GFX1150-TRUE16-NEXT:    v_fma_f32 v3, -v5, v7, v3
; GFX1150-TRUE16-NEXT:    s_denorm_mode 12
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-TRUE16-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
; GFX1150-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1150-TRUE16-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX1150-TRUE16-NEXT:    s_cbranch_vccnz .LBB27_6
; GFX1150-TRUE16-NEXT:  ; %bb.2: ; %frem.loop_body93.preheader
; GFX1150-TRUE16-NEXT:    s_sub_i32 s5, s5, s6
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    s_add_i32 s5, s5, 11
; GFX1150-TRUE16-NEXT:  .LBB27_3: ; %frem.loop_body93
; GFX1150-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX1150-TRUE16-NEXT:    s_add_i32 s5, s5, -11
; GFX1150-TRUE16-NEXT:    s_cmp_gt_i32 s5, 11
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v2, v5, v3
; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v2, v2
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v2, 0x80000000, v2
; GFX1150-TRUE16-NEXT:    v_fma_f32 v2, v2, v1, v5
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v4, v2, v1
; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v2, v2, 11
; GFX1150-TRUE16-NEXT:    s_cbranch_scc1 .LBB27_3
; GFX1150-TRUE16-NEXT:  ; %bb.4:
; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v4, s5
; GFX1150-TRUE16-NEXT:    s_branch .LBB27_7
; GFX1150-TRUE16-NEXT:  .LBB27_5: ; %frem.else86
; GFX1150-TRUE16-NEXT:    s_cmp_eq_f32 s5, s6
; GFX1150-TRUE16-NEXT:    v_and_b16 v0.l, 0x8000, s0
; GFX1150-TRUE16-NEXT:    s_cselect_b32 s5, -1, 0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v0.l, s0, v0.l, s5
; GFX1150-TRUE16-NEXT:    s_branch .LBB27_8
; GFX1150-TRUE16-NEXT:  .LBB27_6:
; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX1150-TRUE16-NEXT:  .LBB27_7: ; %frem.loop_exit94
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v2, -10, v4
; GFX1150-TRUE16-NEXT:    s_and_b32 s5, s0, 0x8000
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v3, v3
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v2, v3, v1
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX1150-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_and_b32_e32 v0, 0x7fff, v0
; GFX1150-TRUE16-NEXT:    v_or_b32_e32 v0, s5, v0
; GFX1150-TRUE16-NEXT:  .LBB27_8:
; GFX1150-TRUE16-NEXT:    s_lshr_b32 s6, s0, 16
; GFX1150-TRUE16-NEXT:    s_lshr_b32 s5, s2, 16
; GFX1150-TRUE16-NEXT:    s_and_b32 s0, s6, 0x7fff
; GFX1150-TRUE16-NEXT:    s_and_b32 s8, s5, 0x7fff
; GFX1150-TRUE16-NEXT:    s_cvt_f32_f16 s7, s0
; GFX1150-TRUE16-NEXT:    s_cvt_f32_f16 s8, s8
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
; GFX1150-TRUE16-NEXT:    s_cmp_gt_f32 s7, s8
; GFX1150-TRUE16-NEXT:    s_cbranch_scc0 .LBB27_13
; GFX1150-TRUE16-NEXT:  ; %bb.9: ; %frem.compute52
; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v2, s8
; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v1, s7
; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v4, s7
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v2, v2, 1
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v3, v1, 11
; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v1, s8
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s7, v4
; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v6, null, v2, v2, 1.0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s8, v1
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v1, -1, v1
; GFX1150-TRUE16-NEXT:    v_rcp_f32_e32 v7, v6
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_not_b32_e32 v5, v1
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v5, v5, v4
; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
; GFX1150-TRUE16-NEXT:    s_denorm_mode 15
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v7, v8, v7
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v8, v4, v7
; GFX1150-TRUE16-NEXT:    v_fma_f32 v9, -v6, v8, v4
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v8, v9, v7
; GFX1150-TRUE16-NEXT:    v_fma_f32 v4, -v6, v8, v4
; GFX1150-TRUE16-NEXT:    s_denorm_mode 12
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-TRUE16-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
; GFX1150-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX1150-TRUE16-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; GFX1150-TRUE16-NEXT:    s_cbranch_vccnz .LBB27_14
; GFX1150-TRUE16-NEXT:  ; %bb.10: ; %frem.loop_body60.preheader
; GFX1150-TRUE16-NEXT:    s_sub_i32 s7, s7, s8
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    s_add_i32 s7, s7, 11
; GFX1150-TRUE16-NEXT:  .LBB27_11: ; %frem.loop_body60
; GFX1150-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v6, v3
; GFX1150-TRUE16-NEXT:    s_add_i32 s7, s7, -11
; GFX1150-TRUE16-NEXT:    s_cmp_gt_i32 s7, 11
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v3, v6, v4
; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v3, v3
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
; GFX1150-TRUE16-NEXT:    v_fma_f32 v3, v3, v2, v6
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v5, v3, v2
; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v3, v3, 11
; GFX1150-TRUE16-NEXT:    s_cbranch_scc1 .LBB27_11
; GFX1150-TRUE16-NEXT:  ; %bb.12:
; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v5, s7
; GFX1150-TRUE16-NEXT:    s_branch .LBB27_15
; GFX1150-TRUE16-NEXT:  .LBB27_13: ; %frem.else53
; GFX1150-TRUE16-NEXT:    s_cmp_eq_f32 s7, s8
; GFX1150-TRUE16-NEXT:    v_and_b16 v0.h, 0x8000, s6
; GFX1150-TRUE16-NEXT:    s_cselect_b32 s7, -1, 0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v1.l, s6, v0.h, s7
; GFX1150-TRUE16-NEXT:    s_branch .LBB27_16
; GFX1150-TRUE16-NEXT:  .LBB27_14:
; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v6, v3
; GFX1150-TRUE16-NEXT:  .LBB27_15: ; %frem.loop_exit61
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v3, -10, v5
; GFX1150-TRUE16-NEXT:    s_and_b32 s6, s6, 0x8000
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v3, v6, v3
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v4, v3, v4
; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v4, v4
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v3, v4, v2
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v2, v3, v2
; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v1, v2, v1
; GFX1150-TRUE16-NEXT:    v_cvt_f16_f32_e32 v1.l, v1
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_and_b32_e32 v1, 0x7fff, v1
; GFX1150-TRUE16-NEXT:    v_or_b32_e32 v1, s6, v1
; GFX1150-TRUE16-NEXT:  .LBB27_16:
; GFX1150-TRUE16-NEXT:    s_and_b32 s6, s1, 0x7fff
; GFX1150-TRUE16-NEXT:    s_and_b32 s8, s3, 0x7fff
; GFX1150-TRUE16-NEXT:    s_cvt_f32_f16 s7, s6
; GFX1150-TRUE16-NEXT:    s_cvt_f32_f16 s8, s8
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
; GFX1150-TRUE16-NEXT:    s_cmp_gt_f32 s7, s8
; GFX1150-TRUE16-NEXT:    s_cbranch_scc0 .LBB27_21
; GFX1150-TRUE16-NEXT:  ; %bb.17: ; %frem.compute19
; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v3, s8
; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v2, s7
; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v5, s7
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v3, v3, 1
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v4, v2, 11
; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v2, s8
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s7, v5
; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v7, null, v3, v3, 1.0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s8, v2
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v2, -1, v2
; GFX1150-TRUE16-NEXT:    v_rcp_f32_e32 v8, v7
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_not_b32_e32 v6, v2
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v6, v6, v5
; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX1150-TRUE16-NEXT:    s_denorm_mode 15
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v8, v9, v8
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v9, v5, v8
; GFX1150-TRUE16-NEXT:    v_fma_f32 v10, -v7, v9, v5
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v9, v10, v8
; GFX1150-TRUE16-NEXT:    v_fma_f32 v5, -v7, v9, v5
; GFX1150-TRUE16-NEXT:    s_denorm_mode 12
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-TRUE16-NEXT:    v_div_fmas_f32 v5, v5, v8, v9
; GFX1150-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX1150-TRUE16-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
; GFX1150-TRUE16-NEXT:    s_cbranch_vccnz .LBB27_22
; GFX1150-TRUE16-NEXT:  ; %bb.18: ; %frem.loop_body27.preheader
; GFX1150-TRUE16-NEXT:    s_sub_i32 s7, s7, s8
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    s_add_i32 s7, s7, 11
; GFX1150-TRUE16-NEXT:  .LBB27_19: ; %frem.loop_body27
; GFX1150-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v7, v4
; GFX1150-TRUE16-NEXT:    s_add_i32 s7, s7, -11
; GFX1150-TRUE16-NEXT:    s_cmp_gt_i32 s7, 11
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v4, v7, v5
; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v4, v4
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
; GFX1150-TRUE16-NEXT:    v_fma_f32 v4, v4, v3, v7
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v6, v4, v3
; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v4, v4, 11
; GFX1150-TRUE16-NEXT:    s_cbranch_scc1 .LBB27_19
; GFX1150-TRUE16-NEXT:  ; %bb.20:
; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v6, s7
; GFX1150-TRUE16-NEXT:    s_branch .LBB27_23
; GFX1150-TRUE16-NEXT:  .LBB27_21: ; %frem.else20
; GFX1150-TRUE16-NEXT:    s_cmp_eq_f32 s7, s8
; GFX1150-TRUE16-NEXT:    v_and_b16 v0.h, 0x8000, s1
; GFX1150-TRUE16-NEXT:    s_cselect_b32 s7, -1, 0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v2.l, s1, v0.h, s7
; GFX1150-TRUE16-NEXT:    s_branch .LBB27_24
; GFX1150-TRUE16-NEXT:  .LBB27_22:
; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v7, v4
; GFX1150-TRUE16-NEXT:  .LBB27_23: ; %frem.loop_exit28
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v4, -10, v6
; GFX1150-TRUE16-NEXT:    s_and_b32 s7, s1, 0x8000
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v4, v7, v4
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v5, v4, v5
; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v5, 0x80000000, v5
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v4, v5, v3
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v3, v4, v3
; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v2, v3, v2
; GFX1150-TRUE16-NEXT:    v_cvt_f16_f32_e32 v2.l, v2
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_and_b32_e32 v2, 0x7fff, v2
; GFX1150-TRUE16-NEXT:    v_or_b32_e32 v2, s7, v2
; GFX1150-TRUE16-NEXT:  .LBB27_24:
; GFX1150-TRUE16-NEXT:    s_lshr_b32 s8, s1, 16
; GFX1150-TRUE16-NEXT:    s_lshr_b32 s7, s3, 16
; GFX1150-TRUE16-NEXT:    s_and_b32 s1, s8, 0x7fff
; GFX1150-TRUE16-NEXT:    s_and_b32 s10, s7, 0x7fff
; GFX1150-TRUE16-NEXT:    s_cvt_f32_f16 s9, s1
; GFX1150-TRUE16-NEXT:    s_cvt_f32_f16 s10, s10
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
; GFX1150-TRUE16-NEXT:    s_cmp_gt_f32 s9, s10
; GFX1150-TRUE16-NEXT:    s_cbranch_scc0 .LBB27_29
; GFX1150-TRUE16-NEXT:  ; %bb.25: ; %frem.compute
; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v4, s10
; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v3, s9
; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v6, s9
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v4, v4, 1
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v5, v3, 11
; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, s10
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s9, v6
; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v8, null, v4, v4, 1.0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s10, v3
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v3, -1, v3
; GFX1150-TRUE16-NEXT:    v_rcp_f32_e32 v9, v8
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_not_b32_e32 v7, v3
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v7, v7, v6
; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v4, 1.0
; GFX1150-TRUE16-NEXT:    s_denorm_mode 15
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v9, v10, v9
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v10, v6, v9
; GFX1150-TRUE16-NEXT:    v_fma_f32 v11, -v8, v10, v6
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v10, v11, v9
; GFX1150-TRUE16-NEXT:    v_fma_f32 v6, -v8, v10, v6
; GFX1150-TRUE16-NEXT:    s_denorm_mode 12
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-TRUE16-NEXT:    v_div_fmas_f32 v6, v6, v9, v10
; GFX1150-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v7
; GFX1150-TRUE16-NEXT:    v_div_fixup_f32 v6, v6, v4, 1.0
; GFX1150-TRUE16-NEXT:    s_cbranch_vccnz .LBB27_30
; GFX1150-TRUE16-NEXT:  ; %bb.26: ; %frem.loop_body.preheader
; GFX1150-TRUE16-NEXT:    s_sub_i32 s9, s9, s10
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    s_add_i32 s9, s9, 11
; GFX1150-TRUE16-NEXT:  .LBB27_27: ; %frem.loop_body
; GFX1150-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v8, v5
; GFX1150-TRUE16-NEXT:    s_add_i32 s9, s9, -11
; GFX1150-TRUE16-NEXT:    s_cmp_gt_i32 s9, 11
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v5, v8, v6
; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v5, 0x80000000, v5
; GFX1150-TRUE16-NEXT:    v_fma_f32 v5, v5, v4, v8
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v7, v5, v4
; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v5, v5, 11
; GFX1150-TRUE16-NEXT:    s_cbranch_scc1 .LBB27_27
; GFX1150-TRUE16-NEXT:  ; %bb.28:
; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v7, s9
; GFX1150-TRUE16-NEXT:    s_branch .LBB27_31
; GFX1150-TRUE16-NEXT:  .LBB27_29: ; %frem.else
; GFX1150-TRUE16-NEXT:    s_cmp_eq_f32 s9, s10
; GFX1150-TRUE16-NEXT:    v_and_b16 v0.h, 0x8000, s8
; GFX1150-TRUE16-NEXT:    s_cselect_b32 s9, -1, 0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v3.l, s8, v0.h, s9
; GFX1150-TRUE16-NEXT:    s_branch .LBB27_32
; GFX1150-TRUE16-NEXT:  .LBB27_30:
; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v8, v5
; GFX1150-TRUE16-NEXT:  .LBB27_31: ; %frem.loop_exit
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v5, -10, v7
; GFX1150-TRUE16-NEXT:    s_and_b32 s8, s8, 0x8000
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v5, v8, v5
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v6, v5, v6
; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v6, v6
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v6, 0x80000000, v6
; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v5, v6, v4
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v4, v5, v4
; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc_lo
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v3, v4, v3
; GFX1150-TRUE16-NEXT:    v_cvt_f16_f32_e32 v3.l, v3
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT:    v_and_b32_e32 v3, 0x7fff, v3
; GFX1150-TRUE16-NEXT:    v_or_b32_e32 v3, s8, v3
; GFX1150-TRUE16-NEXT:  .LBB27_32:
; GFX1150-TRUE16-NEXT:    s_cmp_lg_f16 s2, 0
; GFX1150-TRUE16-NEXT:    s_cselect_b32 s2, -1, 0
; GFX1150-TRUE16-NEXT:    s_cmp_nge_f16 s4, 0x7c00
; GFX1150-TRUE16-NEXT:    s_cselect_b32 s4, -1, 0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    s_and_b32 s2, s4, s2
; GFX1150-TRUE16-NEXT:    s_cmp_lg_f16 s5, 0
; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, s2
; GFX1150-TRUE16-NEXT:    s_cselect_b32 s2, -1, 0
; GFX1150-TRUE16-NEXT:    s_cmp_nge_f16 s0, 0x7c00
; GFX1150-TRUE16-NEXT:    s_cselect_b32 s0, -1, 0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    s_and_b32 s0, s0, s2
; GFX1150-TRUE16-NEXT:    s_cmp_lg_f16 s3, 0
; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v0.h, 0x7e00, v1.l, s0
; GFX1150-TRUE16-NEXT:    s_cselect_b32 s0, -1, 0
; GFX1150-TRUE16-NEXT:    s_cmp_nge_f16 s6, 0x7c00
; GFX1150-TRUE16-NEXT:    s_cselect_b32 s2, -1, 0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    s_and_b32 s0, s2, s0
; GFX1150-TRUE16-NEXT:    s_cmp_lg_f16 s7, 0
; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v1.l, 0x7e00, v2.l, s0
; GFX1150-TRUE16-NEXT:    s_cselect_b32 s0, -1, 0
; GFX1150-TRUE16-NEXT:    s_cmp_nge_f16 s1, 0x7c00
; GFX1150-TRUE16-NEXT:    s_cselect_b32 s1, -1, 0
; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT:    s_and_b32 s0, s1, s0
; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v1.h, 0x7e00, v3.l, s0
; GFX1150-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-FAKE16-LABEL: frem_v4f16_uniform:
; GFX1150-FAKE16:       ; %bb.0:
; GFX1150-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-FAKE16-NEXT:    s_and_b32 s4, s0, 0x7fff
; GFX1150-FAKE16-NEXT:    s_and_b32 s6, s2, 0x7fff
; GFX1150-FAKE16-NEXT:    s_cvt_f32_f16 s5, s4
; GFX1150-FAKE16-NEXT:    s_cvt_f32_f16 s6, s6
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
; GFX1150-FAKE16-NEXT:    s_cmp_gt_f32 s5, s6
; GFX1150-FAKE16-NEXT:    s_cbranch_scc0 .LBB27_5
; GFX1150-FAKE16-NEXT:  ; %bb.1: ; %frem.compute85
; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v1, s6
; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v0, s5
; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, s5
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v2, v0, 11
; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v0, s6
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s5, v3
; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s6, v0
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v0, -1, v0
; GFX1150-FAKE16-NEXT:    v_rcp_f32_e32 v6, v5
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_not_b32_e32 v4, v0
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v4, v4, v3
; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX1150-FAKE16-NEXT:    s_denorm_mode 15
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v6, v7, v6
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v7, v3, v6
; GFX1150-FAKE16-NEXT:    v_fma_f32 v8, -v5, v7, v3
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v7, v8, v6
; GFX1150-FAKE16-NEXT:    v_fma_f32 v3, -v5, v7, v3
; GFX1150-FAKE16-NEXT:    s_denorm_mode 12
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-FAKE16-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
; GFX1150-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1150-FAKE16-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX1150-FAKE16-NEXT:    s_cbranch_vccnz .LBB27_6
; GFX1150-FAKE16-NEXT:  ; %bb.2: ; %frem.loop_body93.preheader
; GFX1150-FAKE16-NEXT:    s_sub_i32 s5, s5, s6
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT:    s_add_i32 s5, s5, 11
; GFX1150-FAKE16-NEXT:  .LBB27_3: ; %frem.loop_body93
; GFX1150-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX1150-FAKE16-NEXT:    s_add_i32 s5, s5, -11
; GFX1150-FAKE16-NEXT:    s_cmp_gt_i32 s5, 11
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v2, v5, v3
; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v2, v2
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v2, 0x80000000, v2
; GFX1150-FAKE16-NEXT:    v_fma_f32 v2, v2, v1, v5
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v4, v2, v1
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v2, v2, 11
; GFX1150-FAKE16-NEXT:    s_cbranch_scc1 .LBB27_3
; GFX1150-FAKE16-NEXT:  ; %bb.4:
; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v4, s5
; GFX1150-FAKE16-NEXT:    s_branch .LBB27_7
; GFX1150-FAKE16-NEXT:  .LBB27_5: ; %frem.else86
; GFX1150-FAKE16-NEXT:    s_and_b32 s7, 0x8000, s0
; GFX1150-FAKE16-NEXT:    s_cmp_eq_f32 s5, s6
; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v0, s7
; GFX1150-FAKE16-NEXT:    s_cselect_b32 vcc_lo, -1, 0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v0, s0, v0, vcc_lo
; GFX1150-FAKE16-NEXT:    s_branch .LBB27_8
; GFX1150-FAKE16-NEXT:  .LBB27_6:
; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX1150-FAKE16-NEXT:  .LBB27_7: ; %frem.loop_exit94
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v2, -10, v4
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v3, v3
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v2, v3, v1
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX1150-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_bfi_b32 v0, 0x7fff, v0, s0
; GFX1150-FAKE16-NEXT:  .LBB27_8:
; GFX1150-FAKE16-NEXT:    s_lshr_b32 s6, s0, 16
; GFX1150-FAKE16-NEXT:    s_lshr_b32 s5, s2, 16
; GFX1150-FAKE16-NEXT:    s_and_b32 s0, s6, 0x7fff
; GFX1150-FAKE16-NEXT:    s_and_b32 s8, s5, 0x7fff
; GFX1150-FAKE16-NEXT:    s_cvt_f32_f16 s7, s0
; GFX1150-FAKE16-NEXT:    s_cvt_f32_f16 s8, s8
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
; GFX1150-FAKE16-NEXT:    s_cmp_gt_f32 s7, s8
; GFX1150-FAKE16-NEXT:    s_cbranch_scc0 .LBB27_13
; GFX1150-FAKE16-NEXT:  ; %bb.9: ; %frem.compute52
; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v2, s8
; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v1, s7
; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v4, s7
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v2, v2, 1
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v3, v1, 11
; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v1, s8
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s7, v4
; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v6, null, v2, v2, 1.0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s8, v1
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v1, -1, v1
; GFX1150-FAKE16-NEXT:    v_rcp_f32_e32 v7, v6
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_not_b32_e32 v5, v1
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v5, v5, v4
; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
; GFX1150-FAKE16-NEXT:    s_denorm_mode 15
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v7, v8, v7
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v8, v4, v7
; GFX1150-FAKE16-NEXT:    v_fma_f32 v9, -v6, v8, v4
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v8, v9, v7
; GFX1150-FAKE16-NEXT:    v_fma_f32 v4, -v6, v8, v4
; GFX1150-FAKE16-NEXT:    s_denorm_mode 12
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-FAKE16-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
; GFX1150-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX1150-FAKE16-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; GFX1150-FAKE16-NEXT:    s_cbranch_vccnz .LBB27_14
; GFX1150-FAKE16-NEXT:  ; %bb.10: ; %frem.loop_body60.preheader
; GFX1150-FAKE16-NEXT:    s_sub_i32 s7, s7, s8
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT:    s_add_i32 s7, s7, 11
; GFX1150-FAKE16-NEXT:  .LBB27_11: ; %frem.loop_body60
; GFX1150-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v6, v3
; GFX1150-FAKE16-NEXT:    s_add_i32 s7, s7, -11
; GFX1150-FAKE16-NEXT:    s_cmp_gt_i32 s7, 11
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v3, v6, v4
; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v3, v3
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
; GFX1150-FAKE16-NEXT:    v_fma_f32 v3, v3, v2, v6
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v5, v3, v2
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v3, v3, 11
; GFX1150-FAKE16-NEXT:    s_cbranch_scc1 .LBB27_11
; GFX1150-FAKE16-NEXT:  ; %bb.12:
; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v5, s7
; GFX1150-FAKE16-NEXT:    s_branch .LBB27_15
; GFX1150-FAKE16-NEXT:  .LBB27_13: ; %frem.else53
; GFX1150-FAKE16-NEXT:    s_and_b32 s9, 0x8000, s6
; GFX1150-FAKE16-NEXT:    s_cmp_eq_f32 s7, s8
; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v1, s9
; GFX1150-FAKE16-NEXT:    s_cselect_b32 vcc_lo, -1, 0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v1, s6, v1, vcc_lo
; GFX1150-FAKE16-NEXT:    s_branch .LBB27_16
; GFX1150-FAKE16-NEXT:  .LBB27_14:
; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v6, v3
; GFX1150-FAKE16-NEXT:  .LBB27_15: ; %frem.loop_exit61
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v3, -10, v5
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v3, v6, v3
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v4, v3, v4
; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v4, v4
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v3, v4, v2
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v2, v3, v2
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v1, v2, v1
; GFX1150-FAKE16-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_bfi_b32 v1, 0x7fff, v1, s6
; GFX1150-FAKE16-NEXT:  .LBB27_16:
; GFX1150-FAKE16-NEXT:    s_and_b32 s6, s1, 0x7fff
; GFX1150-FAKE16-NEXT:    s_and_b32 s8, s3, 0x7fff
; GFX1150-FAKE16-NEXT:    s_cvt_f32_f16 s7, s6
; GFX1150-FAKE16-NEXT:    s_cvt_f32_f16 s8, s8
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
; GFX1150-FAKE16-NEXT:    s_cmp_gt_f32 s7, s8
; GFX1150-FAKE16-NEXT:    s_cbranch_scc0 .LBB27_21
; GFX1150-FAKE16-NEXT:  ; %bb.17: ; %frem.compute19
; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v3, s8
; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v2, s7
; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v5, s7
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v3, v3, 1
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v4, v2, 11
; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v2, s8
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s7, v5
; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v7, null, v3, v3, 1.0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s8, v2
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v2, -1, v2
; GFX1150-FAKE16-NEXT:    v_rcp_f32_e32 v8, v7
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_not_b32_e32 v6, v2
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v6, v6, v5
; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX1150-FAKE16-NEXT:    s_denorm_mode 15
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v8, v9, v8
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v9, v5, v8
; GFX1150-FAKE16-NEXT:    v_fma_f32 v10, -v7, v9, v5
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v9, v10, v8
; GFX1150-FAKE16-NEXT:    v_fma_f32 v5, -v7, v9, v5
; GFX1150-FAKE16-NEXT:    s_denorm_mode 12
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-FAKE16-NEXT:    v_div_fmas_f32 v5, v5, v8, v9
; GFX1150-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX1150-FAKE16-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
; GFX1150-FAKE16-NEXT:    s_cbranch_vccnz .LBB27_22
; GFX1150-FAKE16-NEXT:  ; %bb.18: ; %frem.loop_body27.preheader
; GFX1150-FAKE16-NEXT:    s_sub_i32 s7, s7, s8
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT:    s_add_i32 s7, s7, 11
; GFX1150-FAKE16-NEXT:  .LBB27_19: ; %frem.loop_body27
; GFX1150-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v7, v4
; GFX1150-FAKE16-NEXT:    s_add_i32 s7, s7, -11
; GFX1150-FAKE16-NEXT:    s_cmp_gt_i32 s7, 11
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v4, v7, v5
; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v4, v4
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
; GFX1150-FAKE16-NEXT:    v_fma_f32 v4, v4, v3, v7
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v6, v4, v3
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v4, v4, 11
; GFX1150-FAKE16-NEXT:    s_cbranch_scc1 .LBB27_19
; GFX1150-FAKE16-NEXT:  ; %bb.20:
; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v6, s7
; GFX1150-FAKE16-NEXT:    s_branch .LBB27_23
; GFX1150-FAKE16-NEXT:  .LBB27_21: ; %frem.else20
; GFX1150-FAKE16-NEXT:    s_and_b32 s9, 0x8000, s1
; GFX1150-FAKE16-NEXT:    s_cmp_eq_f32 s7, s8
; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v2, s9
; GFX1150-FAKE16-NEXT:    s_cselect_b32 vcc_lo, -1, 0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v2, s1, v2, vcc_lo
; GFX1150-FAKE16-NEXT:    s_branch .LBB27_24
; GFX1150-FAKE16-NEXT:  .LBB27_22:
; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v7, v4
; GFX1150-FAKE16-NEXT:  .LBB27_23: ; %frem.loop_exit28
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v4, -10, v6
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v4, v7, v4
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v5, v4, v5
; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v5, 0x80000000, v5
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v4, v5, v3
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v3, v4, v3
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v2, v3, v2
; GFX1150-FAKE16-NEXT:    v_cvt_f16_f32_e32 v2, v2
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_bfi_b32 v2, 0x7fff, v2, s1
; GFX1150-FAKE16-NEXT:  .LBB27_24:
; GFX1150-FAKE16-NEXT:    s_lshr_b32 s8, s1, 16
; GFX1150-FAKE16-NEXT:    s_lshr_b32 s7, s3, 16
; GFX1150-FAKE16-NEXT:    s_and_b32 s1, s8, 0x7fff
; GFX1150-FAKE16-NEXT:    s_and_b32 s10, s7, 0x7fff
; GFX1150-FAKE16-NEXT:    s_cvt_f32_f16 s9, s1
; GFX1150-FAKE16-NEXT:    s_cvt_f32_f16 s10, s10
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
; GFX1150-FAKE16-NEXT:    s_cmp_gt_f32 s9, s10
; GFX1150-FAKE16-NEXT:    s_cbranch_scc0 .LBB27_29
; GFX1150-FAKE16-NEXT:  ; %bb.25: ; %frem.compute
; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v4, s10
; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v3, s9
; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v6, s9
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v4, v4, 1
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v5, v3, 11
; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, s10
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s9, v6
; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v8, null, v4, v4, 1.0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s10, v3
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v3, -1, v3
; GFX1150-FAKE16-NEXT:    v_rcp_f32_e32 v9, v8
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_not_b32_e32 v7, v3
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v7, v7, v6
; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v4, 1.0
; GFX1150-FAKE16-NEXT:    s_denorm_mode 15
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v9, v10, v9
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v10, v6, v9
; GFX1150-FAKE16-NEXT:    v_fma_f32 v11, -v8, v10, v6
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v10, v11, v9
; GFX1150-FAKE16-NEXT:    v_fma_f32 v6, -v8, v10, v6
; GFX1150-FAKE16-NEXT:    s_denorm_mode 12
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-FAKE16-NEXT:    v_div_fmas_f32 v6, v6, v9, v10
; GFX1150-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v7
; GFX1150-FAKE16-NEXT:    v_div_fixup_f32 v6, v6, v4, 1.0
; GFX1150-FAKE16-NEXT:    s_cbranch_vccnz .LBB27_30
; GFX1150-FAKE16-NEXT:  ; %bb.26: ; %frem.loop_body.preheader
; GFX1150-FAKE16-NEXT:    s_sub_i32 s9, s9, s10
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT:    s_add_i32 s9, s9, 11
; GFX1150-FAKE16-NEXT:  .LBB27_27: ; %frem.loop_body
; GFX1150-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v8, v5
; GFX1150-FAKE16-NEXT:    s_add_i32 s9, s9, -11
; GFX1150-FAKE16-NEXT:    s_cmp_gt_i32 s9, 11
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v5, v8, v6
; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v5, 0x80000000, v5
; GFX1150-FAKE16-NEXT:    v_fma_f32 v5, v5, v4, v8
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v7, v5, v4
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v5, v5, 11
; GFX1150-FAKE16-NEXT:    s_cbranch_scc1 .LBB27_27
; GFX1150-FAKE16-NEXT:  ; %bb.28:
; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v7, s9
; GFX1150-FAKE16-NEXT:    s_branch .LBB27_31
; GFX1150-FAKE16-NEXT:  .LBB27_29: ; %frem.else
; GFX1150-FAKE16-NEXT:    s_and_b32 s11, 0x8000, s8
; GFX1150-FAKE16-NEXT:    s_cmp_eq_f32 s9, s10
; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v3, s11
; GFX1150-FAKE16-NEXT:    s_cselect_b32 vcc_lo, -1, 0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v3, s8, v3, vcc_lo
; GFX1150-FAKE16-NEXT:    s_branch .LBB27_32
; GFX1150-FAKE16-NEXT:  .LBB27_30:
; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v8, v5
; GFX1150-FAKE16-NEXT:  .LBB27_31: ; %frem.loop_exit
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v5, -10, v7
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v5, v8, v5
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v6, v5, v6
; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v6, v6
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v6, 0x80000000, v6
; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v5, v6, v4
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v4, v5, v4
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc_lo
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v3, v4, v3
; GFX1150-FAKE16-NEXT:    v_cvt_f16_f32_e32 v3, v3
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    v_bfi_b32 v3, 0x7fff, v3, s8
; GFX1150-FAKE16-NEXT:  .LBB27_32:
; GFX1150-FAKE16-NEXT:    s_cmp_lg_f16 s2, 0
; GFX1150-FAKE16-NEXT:    s_cselect_b32 s2, -1, 0
; GFX1150-FAKE16-NEXT:    s_cmp_nge_f16 s4, 0x7c00
; GFX1150-FAKE16-NEXT:    s_cselect_b32 s4, -1, 0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT:    s_and_b32 vcc_lo, s4, s2
; GFX1150-FAKE16-NEXT:    s_cmp_lg_f16 s5, 0
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v0, vcc_lo
; GFX1150-FAKE16-NEXT:    s_cselect_b32 s2, -1, 0
; GFX1150-FAKE16-NEXT:    s_cmp_nge_f16 s0, 0x7c00
; GFX1150-FAKE16-NEXT:    s_cselect_b32 s0, -1, 0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT:    s_and_b32 vcc_lo, s0, s2
; GFX1150-FAKE16-NEXT:    s_cmp_lg_f16 s3, 0
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x7e00, v1, vcc_lo
; GFX1150-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; GFX1150-FAKE16-NEXT:    s_cselect_b32 s0, -1, 0
; GFX1150-FAKE16-NEXT:    s_cmp_nge_f16 s6, 0x7c00
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
; GFX1150-FAKE16-NEXT:    s_cselect_b32 s2, -1, 0
; GFX1150-FAKE16-NEXT:    s_and_b32 vcc_lo, s2, s0
; GFX1150-FAKE16-NEXT:    s_cmp_lg_f16 s7, 0
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v2, 0x7e00, v2, vcc_lo
; GFX1150-FAKE16-NEXT:    s_cselect_b32 s0, -1, 0
; GFX1150-FAKE16-NEXT:    s_cmp_nge_f16 s1, 0x7c00
; GFX1150-FAKE16-NEXT:    s_cselect_b32 s1, -1, 0
; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT:    s_and_b32 vcc_lo, s1, s0
; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v3, 0x7e00, v3, vcc_lo
; GFX1150-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v2
; GFX1150-FAKE16-NEXT:    v_lshl_or_b32 v1, v3, 16, v1
; GFX1150-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-TRUE16-LABEL: frem_v4f16_uniform:
; GFX1200-TRUE16:       ; %bb.0:
; GFX1200-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1200-TRUE16-NEXT:    s_and_b32 s4, s0, 0x7fff
; GFX1200-TRUE16-NEXT:    s_and_b32 s6, s2, 0x7fff
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_cvt_f32_f16 s5, s4
; GFX1200-TRUE16-NEXT:    s_cvt_f32_f16 s6, s6
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_2)
; GFX1200-TRUE16-NEXT:    s_cmp_gt_f32 s5, s6
; GFX1200-TRUE16-NEXT:    s_cbranch_scc0 .LBB27_5
; GFX1200-TRUE16-NEXT:  ; %bb.1: ; %frem.compute85
; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v1, s6
; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v0, s5
; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, s5
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v2, v0, 11
; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v0, s6
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s5, v3
; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s6, v0
; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v0, -1, v0
; GFX1200-TRUE16-NEXT:    v_rcp_f32_e32 v6, v5
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_not_b32_e32 v4, v0
; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v4, v4, v3
; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX1200-TRUE16-NEXT:    s_denorm_mode 15
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v6, v7, v6
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v7, v3, v6
; GFX1200-TRUE16-NEXT:    v_fma_f32 v8, -v5, v7, v3
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v7, v8, v6
; GFX1200-TRUE16-NEXT:    v_fma_f32 v3, -v5, v7, v3
; GFX1200-TRUE16-NEXT:    s_denorm_mode 12
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
; GFX1200-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1200-TRUE16-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX1200-TRUE16-NEXT:    s_cbranch_vccnz .LBB27_6
; GFX1200-TRUE16-NEXT:  ; %bb.2: ; %frem.loop_body93.preheader
; GFX1200-TRUE16-NEXT:    s_sub_co_i32 s5, s5, s6
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_add_co_i32 s5, s5, 11
; GFX1200-TRUE16-NEXT:  .LBB27_3: ; %frem.loop_body93
; GFX1200-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_add_co_i32 s5, s5, -11
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_cmp_gt_i32 s5, 11
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v2, v5, v3
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v2, v2
; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v2, 0x80000000, v2
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f32 v2, v2, v1, v5
; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v4, v2, v1
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v2, v2, 11
; GFX1200-TRUE16-NEXT:    s_cbranch_scc1 .LBB27_3
; GFX1200-TRUE16-NEXT:  ; %bb.4:
; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v4, s5
; GFX1200-TRUE16-NEXT:    s_branch .LBB27_7
; GFX1200-TRUE16-NEXT:  .LBB27_5: ; %frem.else86
; GFX1200-TRUE16-NEXT:    s_cmp_eq_f32 s5, s6
; GFX1200-TRUE16-NEXT:    v_and_b16 v0.l, 0x8000, s0
; GFX1200-TRUE16-NEXT:    s_cselect_b32 s5, -1, 0
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v0.l, s0, v0.l, s5
; GFX1200-TRUE16-NEXT:    s_branch .LBB27_8
; GFX1200-TRUE16-NEXT:  .LBB27_6:
; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX1200-TRUE16-NEXT:  .LBB27_7: ; %frem.loop_exit94
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v2, -10, v4
; GFX1200-TRUE16-NEXT:    s_and_b32 s5, s0, 0x8000
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v3, v3
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v2, v3, v1
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX1200-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_and_b32_e32 v0, 0x7fff, v0
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    v_or_b32_e32 v0, s5, v0
; GFX1200-TRUE16-NEXT:  .LBB27_8:
; GFX1200-TRUE16-NEXT:    s_lshr_b32 s6, s0, 16
; GFX1200-TRUE16-NEXT:    s_lshr_b32 s5, s2, 16
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_and_b32 s0, s6, 0x7fff
; GFX1200-TRUE16-NEXT:    s_and_b32 s8, s5, 0x7fff
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_cvt_f32_f16 s7, s0
; GFX1200-TRUE16-NEXT:    s_cvt_f32_f16 s8, s8
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_2)
; GFX1200-TRUE16-NEXT:    s_cmp_gt_f32 s7, s8
; GFX1200-TRUE16-NEXT:    s_cbranch_scc0 .LBB27_13
; GFX1200-TRUE16-NEXT:  ; %bb.9: ; %frem.compute52
; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v2, s8
; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v1, s7
; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v4, s7
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v2, v2, 1
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v3, v1, 11
; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v1, s8
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s7, v4
; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v6, null, v2, v2, 1.0
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s8, v1
; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v1, -1, v1
; GFX1200-TRUE16-NEXT:    v_rcp_f32_e32 v7, v6
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_not_b32_e32 v5, v1
; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v5, v5, v4
; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
; GFX1200-TRUE16-NEXT:    s_denorm_mode 15
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v7, v8, v7
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v8, v4, v7
; GFX1200-TRUE16-NEXT:    v_fma_f32 v9, -v6, v8, v4
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v8, v9, v7
; GFX1200-TRUE16-NEXT:    v_fma_f32 v4, -v6, v8, v4
; GFX1200-TRUE16-NEXT:    s_denorm_mode 12
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
; GFX1200-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX1200-TRUE16-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; GFX1200-TRUE16-NEXT:    s_cbranch_vccnz .LBB27_14
; GFX1200-TRUE16-NEXT:  ; %bb.10: ; %frem.loop_body60.preheader
; GFX1200-TRUE16-NEXT:    s_sub_co_i32 s7, s7, s8
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_add_co_i32 s7, s7, 11
; GFX1200-TRUE16-NEXT:  .LBB27_11: ; %frem.loop_body60
; GFX1200-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v6, v3
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_add_co_i32 s7, s7, -11
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_cmp_gt_i32 s7, 11
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v3, v6, v4
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v3, v3
; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f32 v3, v3, v2, v6
; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v5, v3, v2
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v3, v3, 11
; GFX1200-TRUE16-NEXT:    s_cbranch_scc1 .LBB27_11
; GFX1200-TRUE16-NEXT:  ; %bb.12:
; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v5, s7
; GFX1200-TRUE16-NEXT:    s_branch .LBB27_15
; GFX1200-TRUE16-NEXT:  .LBB27_13: ; %frem.else53
; GFX1200-TRUE16-NEXT:    s_cmp_eq_f32 s7, s8
; GFX1200-TRUE16-NEXT:    v_and_b16 v0.h, 0x8000, s6
; GFX1200-TRUE16-NEXT:    s_cselect_b32 s7, -1, 0
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v1.l, s6, v0.h, s7
; GFX1200-TRUE16-NEXT:    s_branch .LBB27_16
; GFX1200-TRUE16-NEXT:  .LBB27_14:
; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v6, v3
; GFX1200-TRUE16-NEXT:  .LBB27_15: ; %frem.loop_exit61
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v3, -10, v5
; GFX1200-TRUE16-NEXT:    s_and_b32 s6, s6, 0x8000
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v3, v6, v3
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v4, v3, v4
; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v4, v4
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v3, v4, v2
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v2, v3, v2
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v1, v2, v1
; GFX1200-TRUE16-NEXT:    v_cvt_f16_f32_e32 v1.l, v1
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_and_b32_e32 v1, 0x7fff, v1
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    v_or_b32_e32 v1, s6, v1
; GFX1200-TRUE16-NEXT:  .LBB27_16:
; GFX1200-TRUE16-NEXT:    s_and_b32 s6, s1, 0x7fff
; GFX1200-TRUE16-NEXT:    s_and_b32 s8, s3, 0x7fff
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_cvt_f32_f16 s7, s6
; GFX1200-TRUE16-NEXT:    s_cvt_f32_f16 s8, s8
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_2)
; GFX1200-TRUE16-NEXT:    s_cmp_gt_f32 s7, s8
; GFX1200-TRUE16-NEXT:    s_cbranch_scc0 .LBB27_21
; GFX1200-TRUE16-NEXT:  ; %bb.17: ; %frem.compute19
; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v3, s8
; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v2, s7
; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v5, s7
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v3, v3, 1
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v4, v2, 11
; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v2, s8
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s7, v5
; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v7, null, v3, v3, 1.0
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s8, v2
; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v2, -1, v2
; GFX1200-TRUE16-NEXT:    v_rcp_f32_e32 v8, v7
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_not_b32_e32 v6, v2
; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v6, v6, v5
; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX1200-TRUE16-NEXT:    s_denorm_mode 15
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v8, v9, v8
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v9, v5, v8
; GFX1200-TRUE16-NEXT:    v_fma_f32 v10, -v7, v9, v5
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v9, v10, v8
; GFX1200-TRUE16-NEXT:    v_fma_f32 v5, -v7, v9, v5
; GFX1200-TRUE16-NEXT:    s_denorm_mode 12
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT:    v_div_fmas_f32 v5, v5, v8, v9
; GFX1200-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX1200-TRUE16-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
; GFX1200-TRUE16-NEXT:    s_cbranch_vccnz .LBB27_22
; GFX1200-TRUE16-NEXT:  ; %bb.18: ; %frem.loop_body27.preheader
; GFX1200-TRUE16-NEXT:    s_sub_co_i32 s7, s7, s8
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_add_co_i32 s7, s7, 11
; GFX1200-TRUE16-NEXT:  .LBB27_19: ; %frem.loop_body27
; GFX1200-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v7, v4
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_add_co_i32 s7, s7, -11
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_cmp_gt_i32 s7, 11
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v4, v7, v5
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v4, v4
; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f32 v4, v4, v3, v7
; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v6, v4, v3
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v4, v4, 11
; GFX1200-TRUE16-NEXT:    s_cbranch_scc1 .LBB27_19
; GFX1200-TRUE16-NEXT:  ; %bb.20:
; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v6, s7
; GFX1200-TRUE16-NEXT:    s_branch .LBB27_23
; GFX1200-TRUE16-NEXT:  .LBB27_21: ; %frem.else20
; GFX1200-TRUE16-NEXT:    s_cmp_eq_f32 s7, s8
; GFX1200-TRUE16-NEXT:    v_and_b16 v0.h, 0x8000, s1
; GFX1200-TRUE16-NEXT:    s_cselect_b32 s7, -1, 0
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v2.l, s1, v0.h, s7
; GFX1200-TRUE16-NEXT:    s_branch .LBB27_24
; GFX1200-TRUE16-NEXT:  .LBB27_22:
; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v7, v4
; GFX1200-TRUE16-NEXT:  .LBB27_23: ; %frem.loop_exit28
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v4, -10, v6
; GFX1200-TRUE16-NEXT:    s_and_b32 s7, s1, 0x8000
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v4, v7, v4
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v5, v4, v5
; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v5, 0x80000000, v5
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v4, v5, v3
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v3, v4, v3
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v2, v3, v2
; GFX1200-TRUE16-NEXT:    v_cvt_f16_f32_e32 v2.l, v2
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_and_b32_e32 v2, 0x7fff, v2
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    v_or_b32_e32 v2, s7, v2
; GFX1200-TRUE16-NEXT:  .LBB27_24:
; GFX1200-TRUE16-NEXT:    s_lshr_b32 s8, s1, 16
; GFX1200-TRUE16-NEXT:    s_lshr_b32 s7, s3, 16
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_and_b32 s1, s8, 0x7fff
; GFX1200-TRUE16-NEXT:    s_and_b32 s10, s7, 0x7fff
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_cvt_f32_f16 s9, s1
; GFX1200-TRUE16-NEXT:    s_cvt_f32_f16 s10, s10
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_2)
; GFX1200-TRUE16-NEXT:    s_cmp_gt_f32 s9, s10
; GFX1200-TRUE16-NEXT:    s_cbranch_scc0 .LBB27_29
; GFX1200-TRUE16-NEXT:  ; %bb.25: ; %frem.compute
; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v4, s10
; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v3, s9
; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v6, s9
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v4, v4, 1
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v5, v3, 11
; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, s10
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s9, v6
; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v8, null, v4, v4, 1.0
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s10, v3
; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v3, -1, v3
; GFX1200-TRUE16-NEXT:    v_rcp_f32_e32 v9, v8
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_not_b32_e32 v7, v3
; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v7, v7, v6
; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v4, 1.0
; GFX1200-TRUE16-NEXT:    s_denorm_mode 15
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v9, v10, v9
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v10, v6, v9
; GFX1200-TRUE16-NEXT:    v_fma_f32 v11, -v8, v10, v6
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v10, v11, v9
; GFX1200-TRUE16-NEXT:    v_fma_f32 v6, -v8, v10, v6
; GFX1200-TRUE16-NEXT:    s_denorm_mode 12
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT:    v_div_fmas_f32 v6, v6, v9, v10
; GFX1200-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v7
; GFX1200-TRUE16-NEXT:    v_div_fixup_f32 v6, v6, v4, 1.0
; GFX1200-TRUE16-NEXT:    s_cbranch_vccnz .LBB27_30
; GFX1200-TRUE16-NEXT:  ; %bb.26: ; %frem.loop_body.preheader
; GFX1200-TRUE16-NEXT:    s_sub_co_i32 s9, s9, s10
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_add_co_i32 s9, s9, 11
; GFX1200-TRUE16-NEXT:  .LBB27_27: ; %frem.loop_body
; GFX1200-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v8, v5
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_add_co_i32 s9, s9, -11
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_cmp_gt_i32 s9, 11
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v5, v8, v6
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v5, 0x80000000, v5
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_fma_f32 v5, v5, v4, v8
; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v7, v5, v4
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v5, v5, 11
; GFX1200-TRUE16-NEXT:    s_cbranch_scc1 .LBB27_27
; GFX1200-TRUE16-NEXT:  ; %bb.28:
; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v7, s9
; GFX1200-TRUE16-NEXT:    s_branch .LBB27_31
; GFX1200-TRUE16-NEXT:  .LBB27_29: ; %frem.else
; GFX1200-TRUE16-NEXT:    s_cmp_eq_f32 s9, s10
; GFX1200-TRUE16-NEXT:    v_and_b16 v0.h, 0x8000, s8
; GFX1200-TRUE16-NEXT:    s_cselect_b32 s9, -1, 0
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v3.l, s8, v0.h, s9
; GFX1200-TRUE16-NEXT:    s_branch .LBB27_32
; GFX1200-TRUE16-NEXT:  .LBB27_30:
; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v8, v5
; GFX1200-TRUE16-NEXT:  .LBB27_31: ; %frem.loop_exit
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v5, -10, v7
; GFX1200-TRUE16-NEXT:    s_and_b32 s8, s8, 0x8000
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v5, v8, v5
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v6, v5, v6
; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v6, v6
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v6, 0x80000000, v6
; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v5, v6, v4
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v4, v5, v4
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc_lo
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v3, v4, v3
; GFX1200-TRUE16-NEXT:    v_cvt_f16_f32_e32 v3.l, v3
; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT:    v_and_b32_e32 v3, 0x7fff, v3
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    v_or_b32_e32 v3, s8, v3
; GFX1200-TRUE16-NEXT:  .LBB27_32:
; GFX1200-TRUE16-NEXT:    s_cmp_lg_f16 s2, 0
; GFX1200-TRUE16-NEXT:    s_cselect_b32 s2, -1, 0
; GFX1200-TRUE16-NEXT:    s_cmp_nge_f16 s4, 0x7c00
; GFX1200-TRUE16-NEXT:    s_cselect_b32 s4, -1, 0
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_and_b32 s2, s4, s2
; GFX1200-TRUE16-NEXT:    s_cmp_lg_f16 s5, 0
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, s2
; GFX1200-TRUE16-NEXT:    s_cselect_b32 s2, -1, 0
; GFX1200-TRUE16-NEXT:    s_cmp_nge_f16 s0, 0x7c00
; GFX1200-TRUE16-NEXT:    s_cselect_b32 s0, -1, 0
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_and_b32 s0, s0, s2
; GFX1200-TRUE16-NEXT:    s_cmp_lg_f16 s3, 0
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v0.h, 0x7e00, v1.l, s0
; GFX1200-TRUE16-NEXT:    s_cselect_b32 s0, -1, 0
; GFX1200-TRUE16-NEXT:    s_cmp_nge_f16 s6, 0x7c00
; GFX1200-TRUE16-NEXT:    s_cselect_b32 s2, -1, 0
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_and_b32 s0, s2, s0
; GFX1200-TRUE16-NEXT:    s_cmp_lg_f16 s7, 0
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v1.l, 0x7e00, v2.l, s0
; GFX1200-TRUE16-NEXT:    s_cselect_b32 s0, -1, 0
; GFX1200-TRUE16-NEXT:    s_cmp_nge_f16 s1, 0x7c00
; GFX1200-TRUE16-NEXT:    s_cselect_b32 s1, -1, 0
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    s_and_b32 s0, s1, s0
; GFX1200-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v1.h, 0x7e00, v3.l, s0
; GFX1200-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-FAKE16-LABEL: frem_v4f16_uniform:
; GFX1200-FAKE16:       ; %bb.0:
; GFX1200-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1200-FAKE16-NEXT:    s_and_b32 s4, s0, 0x7fff
; GFX1200-FAKE16-NEXT:    s_and_b32 s6, s2, 0x7fff
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_cvt_f32_f16 s5, s4
; GFX1200-FAKE16-NEXT:    s_cvt_f32_f16 s6, s6
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_2)
; GFX1200-FAKE16-NEXT:    s_cmp_gt_f32 s5, s6
; GFX1200-FAKE16-NEXT:    s_cbranch_scc0 .LBB27_5
; GFX1200-FAKE16-NEXT:  ; %bb.1: ; %frem.compute85
; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v1, s6
; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v0, s5
; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, s5
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v2, v0, 11
; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v0, s6
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s5, v3
; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s6, v0
; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v0, -1, v0
; GFX1200-FAKE16-NEXT:    v_rcp_f32_e32 v6, v5
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_not_b32_e32 v4, v0
; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v4, v4, v3
; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX1200-FAKE16-NEXT:    s_denorm_mode 15
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v6, v7, v6
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v7, v3, v6
; GFX1200-FAKE16-NEXT:    v_fma_f32 v8, -v5, v7, v3
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v7, v8, v6
; GFX1200-FAKE16-NEXT:    v_fma_f32 v3, -v5, v7, v3
; GFX1200-FAKE16-NEXT:    s_denorm_mode 12
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-FAKE16-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
; GFX1200-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1200-FAKE16-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX1200-FAKE16-NEXT:    s_cbranch_vccnz .LBB27_6
; GFX1200-FAKE16-NEXT:  ; %bb.2: ; %frem.loop_body93.preheader
; GFX1200-FAKE16-NEXT:    s_sub_co_i32 s5, s5, s6
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_add_co_i32 s5, s5, 11
; GFX1200-FAKE16-NEXT:  .LBB27_3: ; %frem.loop_body93
; GFX1200-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_add_co_i32 s5, s5, -11
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_cmp_gt_i32 s5, 11
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v2, v5, v3
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v2, v2
; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v2, 0x80000000, v2
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f32 v2, v2, v1, v5
; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v4, v2, v1
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v2, v2, 11
; GFX1200-FAKE16-NEXT:    s_cbranch_scc1 .LBB27_3
; GFX1200-FAKE16-NEXT:  ; %bb.4:
; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v4, s5
; GFX1200-FAKE16-NEXT:    s_branch .LBB27_7
; GFX1200-FAKE16-NEXT:  .LBB27_5: ; %frem.else86
; GFX1200-FAKE16-NEXT:    s_and_b32 s7, 0x8000, s0
; GFX1200-FAKE16-NEXT:    s_cmp_eq_f32 s5, s6
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v0, s7
; GFX1200-FAKE16-NEXT:    s_cselect_b32 vcc_lo, -1, 0
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v0, s0, v0, vcc_lo
; GFX1200-FAKE16-NEXT:    s_branch .LBB27_8
; GFX1200-FAKE16-NEXT:  .LBB27_6:
; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v5, v2
; GFX1200-FAKE16-NEXT:  .LBB27_7: ; %frem.loop_exit94
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v2, -10, v4
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v3, v3
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v2, v3, v1
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX1200-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_bfi_b32 v0, 0x7fff, v0, s0
; GFX1200-FAKE16-NEXT:  .LBB27_8:
; GFX1200-FAKE16-NEXT:    s_lshr_b32 s6, s0, 16
; GFX1200-FAKE16-NEXT:    s_lshr_b32 s5, s2, 16
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_and_b32 s0, s6, 0x7fff
; GFX1200-FAKE16-NEXT:    s_and_b32 s8, s5, 0x7fff
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_cvt_f32_f16 s7, s0
; GFX1200-FAKE16-NEXT:    s_cvt_f32_f16 s8, s8
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_2)
; GFX1200-FAKE16-NEXT:    s_cmp_gt_f32 s7, s8
; GFX1200-FAKE16-NEXT:    s_cbranch_scc0 .LBB27_13
; GFX1200-FAKE16-NEXT:  ; %bb.9: ; %frem.compute52
; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v2, s8
; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v1, s7
; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v4, s7
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v2, v2, 1
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v3, v1, 11
; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v1, s8
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s7, v4
; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v6, null, v2, v2, 1.0
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s8, v1
; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v1, -1, v1
; GFX1200-FAKE16-NEXT:    v_rcp_f32_e32 v7, v6
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_not_b32_e32 v5, v1
; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v5, v5, v4
; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
; GFX1200-FAKE16-NEXT:    s_denorm_mode 15
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v7, v8, v7
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v8, v4, v7
; GFX1200-FAKE16-NEXT:    v_fma_f32 v9, -v6, v8, v4
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v8, v9, v7
; GFX1200-FAKE16-NEXT:    v_fma_f32 v4, -v6, v8, v4
; GFX1200-FAKE16-NEXT:    s_denorm_mode 12
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-FAKE16-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
; GFX1200-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX1200-FAKE16-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; GFX1200-FAKE16-NEXT:    s_cbranch_vccnz .LBB27_14
; GFX1200-FAKE16-NEXT:  ; %bb.10: ; %frem.loop_body60.preheader
; GFX1200-FAKE16-NEXT:    s_sub_co_i32 s7, s7, s8
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_add_co_i32 s7, s7, 11
; GFX1200-FAKE16-NEXT:  .LBB27_11: ; %frem.loop_body60
; GFX1200-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v6, v3
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_add_co_i32 s7, s7, -11
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_cmp_gt_i32 s7, 11
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v3, v6, v4
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v3, v3
; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f32 v3, v3, v2, v6
; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v5, v3, v2
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v3, v3, 11
; GFX1200-FAKE16-NEXT:    s_cbranch_scc1 .LBB27_11
; GFX1200-FAKE16-NEXT:  ; %bb.12:
; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v5, s7
; GFX1200-FAKE16-NEXT:    s_branch .LBB27_15
; GFX1200-FAKE16-NEXT:  .LBB27_13: ; %frem.else53
; GFX1200-FAKE16-NEXT:    s_and_b32 s9, 0x8000, s6
; GFX1200-FAKE16-NEXT:    s_cmp_eq_f32 s7, s8
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v1, s9
; GFX1200-FAKE16-NEXT:    s_cselect_b32 vcc_lo, -1, 0
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v1, s6, v1, vcc_lo
; GFX1200-FAKE16-NEXT:    s_branch .LBB27_16
; GFX1200-FAKE16-NEXT:  .LBB27_14:
; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v6, v3
; GFX1200-FAKE16-NEXT:  .LBB27_15: ; %frem.loop_exit61
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v3, -10, v5
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v3, v6, v3
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v4, v3, v4
; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v4, v4
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v3, v4, v2
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v2, v3, v2
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v1, v2, v1
; GFX1200-FAKE16-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_bfi_b32 v1, 0x7fff, v1, s6
; GFX1200-FAKE16-NEXT:  .LBB27_16:
; GFX1200-FAKE16-NEXT:    s_and_b32 s6, s1, 0x7fff
; GFX1200-FAKE16-NEXT:    s_and_b32 s8, s3, 0x7fff
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_cvt_f32_f16 s7, s6
; GFX1200-FAKE16-NEXT:    s_cvt_f32_f16 s8, s8
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_2)
; GFX1200-FAKE16-NEXT:    s_cmp_gt_f32 s7, s8
; GFX1200-FAKE16-NEXT:    s_cbranch_scc0 .LBB27_21
; GFX1200-FAKE16-NEXT:  ; %bb.17: ; %frem.compute19
; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v3, s8
; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v2, s7
; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v5, s7
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v3, v3, 1
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v4, v2, 11
; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v2, s8
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s7, v5
; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v7, null, v3, v3, 1.0
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s8, v2
; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v2, -1, v2
; GFX1200-FAKE16-NEXT:    v_rcp_f32_e32 v8, v7
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_not_b32_e32 v6, v2
; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v6, v6, v5
; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX1200-FAKE16-NEXT:    s_denorm_mode 15
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v8, v9, v8
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v9, v5, v8
; GFX1200-FAKE16-NEXT:    v_fma_f32 v10, -v7, v9, v5
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v9, v10, v8
; GFX1200-FAKE16-NEXT:    v_fma_f32 v5, -v7, v9, v5
; GFX1200-FAKE16-NEXT:    s_denorm_mode 12
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-FAKE16-NEXT:    v_div_fmas_f32 v5, v5, v8, v9
; GFX1200-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX1200-FAKE16-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
; GFX1200-FAKE16-NEXT:    s_cbranch_vccnz .LBB27_22
; GFX1200-FAKE16-NEXT:  ; %bb.18: ; %frem.loop_body27.preheader
; GFX1200-FAKE16-NEXT:    s_sub_co_i32 s7, s7, s8
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_add_co_i32 s7, s7, 11
; GFX1200-FAKE16-NEXT:  .LBB27_19: ; %frem.loop_body27
; GFX1200-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v7, v4
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_add_co_i32 s7, s7, -11
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_cmp_gt_i32 s7, 11
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v4, v7, v5
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v4, v4
; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f32 v4, v4, v3, v7
; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v6, v4, v3
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v4, v4, 11
; GFX1200-FAKE16-NEXT:    s_cbranch_scc1 .LBB27_19
; GFX1200-FAKE16-NEXT:  ; %bb.20:
; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v6, s7
; GFX1200-FAKE16-NEXT:    s_branch .LBB27_23
; GFX1200-FAKE16-NEXT:  .LBB27_21: ; %frem.else20
; GFX1200-FAKE16-NEXT:    s_and_b32 s9, 0x8000, s1
; GFX1200-FAKE16-NEXT:    s_cmp_eq_f32 s7, s8
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v2, s9
; GFX1200-FAKE16-NEXT:    s_cselect_b32 vcc_lo, -1, 0
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v2, s1, v2, vcc_lo
; GFX1200-FAKE16-NEXT:    s_branch .LBB27_24
; GFX1200-FAKE16-NEXT:  .LBB27_22:
; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v7, v4
; GFX1200-FAKE16-NEXT:  .LBB27_23: ; %frem.loop_exit28
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v4, -10, v6
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v4, v7, v4
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v5, v4, v5
; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v5, 0x80000000, v5
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v4, v5, v3
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v3, v4, v3
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v2, v3, v2
; GFX1200-FAKE16-NEXT:    v_cvt_f16_f32_e32 v2, v2
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_bfi_b32 v2, 0x7fff, v2, s1
; GFX1200-FAKE16-NEXT:  .LBB27_24:
; GFX1200-FAKE16-NEXT:    s_lshr_b32 s8, s1, 16
; GFX1200-FAKE16-NEXT:    s_lshr_b32 s7, s3, 16
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_and_b32 s1, s8, 0x7fff
; GFX1200-FAKE16-NEXT:    s_and_b32 s10, s7, 0x7fff
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_cvt_f32_f16 s9, s1
; GFX1200-FAKE16-NEXT:    s_cvt_f32_f16 s10, s10
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_2)
; GFX1200-FAKE16-NEXT:    s_cmp_gt_f32 s9, s10
; GFX1200-FAKE16-NEXT:    s_cbranch_scc0 .LBB27_29
; GFX1200-FAKE16-NEXT:  ; %bb.25: ; %frem.compute
; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v4, s10
; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v3, s9
; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v6, s9
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v4, v4, 1
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v5, v3, 11
; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, s10
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s9, v6
; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v8, null, v4, v4, 1.0
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s10, v3
; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v3, -1, v3
; GFX1200-FAKE16-NEXT:    v_rcp_f32_e32 v9, v8
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_not_b32_e32 v7, v3
; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v7, v7, v6
; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v4, 1.0
; GFX1200-FAKE16-NEXT:    s_denorm_mode 15
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v9, v10, v9
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v10, v6, v9
; GFX1200-FAKE16-NEXT:    v_fma_f32 v11, -v8, v10, v6
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v10, v11, v9
; GFX1200-FAKE16-NEXT:    v_fma_f32 v6, -v8, v10, v6
; GFX1200-FAKE16-NEXT:    s_denorm_mode 12
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-FAKE16-NEXT:    v_div_fmas_f32 v6, v6, v9, v10
; GFX1200-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v7
; GFX1200-FAKE16-NEXT:    v_div_fixup_f32 v6, v6, v4, 1.0
; GFX1200-FAKE16-NEXT:    s_cbranch_vccnz .LBB27_30
; GFX1200-FAKE16-NEXT:  ; %bb.26: ; %frem.loop_body.preheader
; GFX1200-FAKE16-NEXT:    s_sub_co_i32 s9, s9, s10
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_add_co_i32 s9, s9, 11
; GFX1200-FAKE16-NEXT:  .LBB27_27: ; %frem.loop_body
; GFX1200-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v8, v5
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_add_co_i32 s9, s9, -11
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_cmp_gt_i32 s9, 11
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v5, v8, v6
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v5, v5
; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v5, 0x80000000, v5
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_fma_f32 v5, v5, v4, v8
; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v7, v5, v4
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v5, v5, 11
; GFX1200-FAKE16-NEXT:    s_cbranch_scc1 .LBB27_27
; GFX1200-FAKE16-NEXT:  ; %bb.28:
; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v7, s9
; GFX1200-FAKE16-NEXT:    s_branch .LBB27_31
; GFX1200-FAKE16-NEXT:  .LBB27_29: ; %frem.else
; GFX1200-FAKE16-NEXT:    s_and_b32 s11, 0x8000, s8
; GFX1200-FAKE16-NEXT:    s_cmp_eq_f32 s9, s10
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v3, s11
; GFX1200-FAKE16-NEXT:    s_cselect_b32 vcc_lo, -1, 0
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v3, s8, v3, vcc_lo
; GFX1200-FAKE16-NEXT:    s_branch .LBB27_32
; GFX1200-FAKE16-NEXT:  .LBB27_30:
; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v8, v5
; GFX1200-FAKE16-NEXT:  .LBB27_31: ; %frem.loop_exit
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v5, -10, v7
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v5, v8, v5
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v6, v5, v6
; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v6, v6
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v6, 0x80000000, v6
; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v5, v6, v4
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v4, v5, v4
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc_lo
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v3, v4, v3
; GFX1200-FAKE16-NEXT:    v_cvt_f16_f32_e32 v3, v3
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_bfi_b32 v3, 0x7fff, v3, s8
; GFX1200-FAKE16-NEXT:  .LBB27_32:
; GFX1200-FAKE16-NEXT:    s_cmp_lg_f16 s2, 0
; GFX1200-FAKE16-NEXT:    s_cselect_b32 s2, -1, 0
; GFX1200-FAKE16-NEXT:    s_cmp_nge_f16 s4, 0x7c00
; GFX1200-FAKE16-NEXT:    s_cselect_b32 s4, -1, 0
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_and_b32 vcc_lo, s4, s2
; GFX1200-FAKE16-NEXT:    s_cmp_lg_f16 s5, 0
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v0, vcc_lo
; GFX1200-FAKE16-NEXT:    s_cselect_b32 s2, -1, 0
; GFX1200-FAKE16-NEXT:    s_cmp_nge_f16 s0, 0x7c00
; GFX1200-FAKE16-NEXT:    s_cselect_b32 s0, -1, 0
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_and_b32 vcc_lo, s0, s2
; GFX1200-FAKE16-NEXT:    s_cmp_lg_f16 s3, 0
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x7e00, v1, vcc_lo
; GFX1200-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; GFX1200-FAKE16-NEXT:    s_cselect_b32 s0, -1, 0
; GFX1200-FAKE16-NEXT:    s_cmp_nge_f16 s6, 0x7c00
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
; GFX1200-FAKE16-NEXT:    s_cselect_b32 s2, -1, 0
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_and_b32 vcc_lo, s2, s0
; GFX1200-FAKE16-NEXT:    s_cmp_lg_f16 s7, 0
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v2, 0x7e00, v2, vcc_lo
; GFX1200-FAKE16-NEXT:    s_cselect_b32 s0, -1, 0
; GFX1200-FAKE16-NEXT:    s_cmp_nge_f16 s1, 0x7c00
; GFX1200-FAKE16-NEXT:    s_cselect_b32 s1, -1, 0
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    s_and_b32 vcc_lo, s1, s0
; GFX1200-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v3, 0x7e00, v3, vcc_lo
; GFX1200-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v2
; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT:    v_lshl_or_b32 v1, v3, 16, v1
; GFX1200-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %r2 = frem <4 x half> %in1, %in2
  ret <4 x half> %r2
}

define <2 x float> @frem_v2f32_uniform(<2 x float> inreg %in1, <2 x float> inreg %in2) #0 {
; SI-LABEL: frem_v2f32_uniform:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_mov_b32_e32 v0, s18
; SI-NEXT:    v_cmp_gt_f32_e64 vcc, |s16|, |v0|
; SI-NEXT:    s_cbranch_vccz .LBB28_4
; SI-NEXT:  ; %bb.1: ; %frem.compute15
; SI-NEXT:    v_mov_b32_e32 v0, 0x7f800000
; SI-NEXT:    v_cmp_lt_f32_e64 s[4:5], |s16|, v0
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v1, s16
; SI-NEXT:    s_and_b64 s[6:7], s[4:5], exec
; SI-NEXT:    v_readfirstlane_b32 s6, v1
; SI-NEXT:    v_frexp_mant_f32_e64 v1, |s16|
; SI-NEXT:    v_mov_b32_e32 v2, s16
; SI-NEXT:    v_cndmask_b32_e64 v1, |v2|, v1, s[4:5]
; SI-NEXT:    v_cmp_lt_f32_e64 s[4:5], |s18|, v0
; SI-NEXT:    v_frexp_mant_f32_e64 v0, |s18|
; SI-NEXT:    v_mov_b32_e32 v2, s18
; SI-NEXT:    v_cndmask_b32_e64 v0, |v2|, v0, s[4:5]
; SI-NEXT:    v_ldexp_f32_e64 v0, v0, 1
; SI-NEXT:    v_div_scale_f32 v3, s[8:9], v0, v0, 1.0
; SI-NEXT:    v_rcp_f32_e32 v4, v3
; SI-NEXT:    s_cselect_b32 s6, s6, 0
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v2, s18
; SI-NEXT:    s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT:    v_ldexp_f32_e64 v1, v1, 12
; SI-NEXT:    v_readfirstlane_b32 s4, v2
; SI-NEXT:    v_div_scale_f32 v2, vcc, 1.0, v0, 1.0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
; SI-NEXT:    v_fma_f32 v4, v5, v4, v4
; SI-NEXT:    v_mul_f32_e32 v5, v2, v4
; SI-NEXT:    s_cselect_b32 s7, s4, 0
; SI-NEXT:    v_fma_f32 v6, -v3, v5, v2
; SI-NEXT:    s_add_i32 s4, s7, -1
; SI-NEXT:    v_fma_f32 v5, v6, v4, v5
; SI-NEXT:    s_not_b32 s5, s4
; SI-NEXT:    v_fma_f32 v2, -v3, v5, v2
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    s_add_i32 s5, s5, s6
; SI-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
; SI-NEXT:    v_div_fixup_f32 v2, v2, v0, 1.0
; SI-NEXT:    s_cmp_lt_i32 s5, 13
; SI-NEXT:    s_cbranch_scc1 .LBB28_5
; SI-NEXT:  ; %bb.2: ; %frem.loop_body23.preheader
; SI-NEXT:    s_sub_i32 s5, s6, s7
; SI-NEXT:    s_add_i32 s5, s5, 12
; SI-NEXT:  .LBB28_3: ; %frem.loop_body23
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v3, v1
; SI-NEXT:    v_mul_f32_e32 v1, v3, v2
; SI-NEXT:    v_rndne_f32_e32 v1, v1
; SI-NEXT:    v_fma_f32 v1, -v1, v0, v3
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v1
; SI-NEXT:    v_add_f32_e32 v4, v1, v0
; SI-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
; SI-NEXT:    s_add_i32 s5, s5, -12
; SI-NEXT:    v_ldexp_f32_e64 v1, v1, 12
; SI-NEXT:    s_cmp_gt_i32 s5, 12
; SI-NEXT:    s_cbranch_scc1 .LBB28_3
; SI-NEXT:    s_branch .LBB28_6
; SI-NEXT:  .LBB28_4: ; %frem.else16
; SI-NEXT:    s_and_b32 s4, 0x80000000, s16
; SI-NEXT:    v_mov_b32_e32 v0, s18
; SI-NEXT:    v_cmp_eq_f32_e64 vcc, |s16|, |v0|
; SI-NEXT:    v_mov_b32_e32 v0, s16
; SI-NEXT:    v_mov_b32_e32 v1, s4
; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-NEXT:    s_branch .LBB28_7
; SI-NEXT:  .LBB28_5:
; SI-NEXT:    v_mov_b32_e32 v3, v1
; SI-NEXT:  .LBB28_6: ; %frem.loop_exit24
; SI-NEXT:    s_add_i32 s5, s5, -11
; SI-NEXT:    v_ldexp_f32_e64 v1, v3, s5
; SI-NEXT:    v_mul_f32_e32 v2, v1, v2
; SI-NEXT:    v_rndne_f32_e32 v2, v2
; SI-NEXT:    v_fma_f32 v1, -v2, v0, v1
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v1
; SI-NEXT:    v_add_f32_e32 v0, v1, v0
; SI-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; SI-NEXT:    v_ldexp_f32_e64 v0, v0, s4
; SI-NEXT:    s_brev_b32 s4, -2
; SI-NEXT:    v_mov_b32_e32 v1, s16
; SI-NEXT:    v_bfi_b32 v0, s4, v0, v1
; SI-NEXT:  .LBB28_7:
; SI-NEXT:    v_mov_b32_e32 v1, s19
; SI-NEXT:    v_cmp_gt_f32_e64 vcc, |s17|, |v1|
; SI-NEXT:    s_cbranch_vccz .LBB28_11
; SI-NEXT:  ; %bb.8: ; %frem.compute
; SI-NEXT:    v_mov_b32_e32 v1, 0x7f800000
; SI-NEXT:    v_cmp_lt_f32_e64 s[4:5], |s17|, v1
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v2, s17
; SI-NEXT:    s_and_b64 s[6:7], s[4:5], exec
; SI-NEXT:    v_readfirstlane_b32 s6, v2
; SI-NEXT:    v_frexp_mant_f32_e64 v2, |s17|
; SI-NEXT:    v_mov_b32_e32 v3, s17
; SI-NEXT:    v_cndmask_b32_e64 v2, |v3|, v2, s[4:5]
; SI-NEXT:    v_cmp_lt_f32_e64 s[4:5], |s19|, v1
; SI-NEXT:    v_frexp_mant_f32_e64 v1, |s19|
; SI-NEXT:    v_mov_b32_e32 v3, s19
; SI-NEXT:    v_cndmask_b32_e64 v1, |v3|, v1, s[4:5]
; SI-NEXT:    v_ldexp_f32_e64 v1, v1, 1
; SI-NEXT:    v_div_scale_f32 v4, s[8:9], v1, v1, 1.0
; SI-NEXT:    v_rcp_f32_e32 v5, v4
; SI-NEXT:    s_cselect_b32 s6, s6, 0
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v3, s19
; SI-NEXT:    s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT:    v_ldexp_f32_e64 v2, v2, 12
; SI-NEXT:    v_readfirstlane_b32 s4, v3
; SI-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v1, 1.0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    v_fma_f32 v6, -v4, v5, 1.0
; SI-NEXT:    v_fma_f32 v5, v6, v5, v5
; SI-NEXT:    v_mul_f32_e32 v6, v3, v5
; SI-NEXT:    s_cselect_b32 s7, s4, 0
; SI-NEXT:    v_fma_f32 v7, -v4, v6, v3
; SI-NEXT:    s_add_i32 s4, s7, -1
; SI-NEXT:    v_fma_f32 v6, v7, v5, v6
; SI-NEXT:    s_not_b32 s5, s4
; SI-NEXT:    v_fma_f32 v3, -v4, v6, v3
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    s_add_i32 s5, s5, s6
; SI-NEXT:    v_div_fmas_f32 v3, v3, v5, v6
; SI-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; SI-NEXT:    s_cmp_lt_i32 s5, 13
; SI-NEXT:    s_cbranch_scc1 .LBB28_12
; SI-NEXT:  ; %bb.9: ; %frem.loop_body.preheader
; SI-NEXT:    s_sub_i32 s5, s6, s7
; SI-NEXT:    s_add_i32 s5, s5, 12
; SI-NEXT:  .LBB28_10: ; %frem.loop_body
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v4, v2
; SI-NEXT:    v_mul_f32_e32 v2, v4, v3
; SI-NEXT:    v_rndne_f32_e32 v2, v2
; SI-NEXT:    v_fma_f32 v2, -v2, v1, v4
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v2
; SI-NEXT:    v_add_f32_e32 v5, v2, v1
; SI-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
; SI-NEXT:    s_add_i32 s5, s5, -12
; SI-NEXT:    v_ldexp_f32_e64 v2, v2, 12
; SI-NEXT:    s_cmp_gt_i32 s5, 12
; SI-NEXT:    s_cbranch_scc1 .LBB28_10
; SI-NEXT:    s_branch .LBB28_13
; SI-NEXT:  .LBB28_11: ; %frem.else
; SI-NEXT:    s_and_b32 s4, 0x80000000, s17
; SI-NEXT:    v_mov_b32_e32 v1, s19
; SI-NEXT:    v_cmp_eq_f32_e64 vcc, |s17|, |v1|
; SI-NEXT:    v_mov_b32_e32 v1, s17
; SI-NEXT:    v_mov_b32_e32 v2, s4
; SI-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
; SI-NEXT:    s_branch .LBB28_14
; SI-NEXT:  .LBB28_12:
; SI-NEXT:    v_mov_b32_e32 v4, v2
; SI-NEXT:  .LBB28_13: ; %frem.loop_exit
; SI-NEXT:    s_add_i32 s5, s5, -11
; SI-NEXT:    v_ldexp_f32_e64 v2, v4, s5
; SI-NEXT:    v_mul_f32_e32 v3, v2, v3
; SI-NEXT:    v_rndne_f32_e32 v3, v3
; SI-NEXT:    v_fma_f32 v2, -v3, v1, v2
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v2
; SI-NEXT:    v_add_f32_e32 v1, v2, v1
; SI-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; SI-NEXT:    v_ldexp_f32_e64 v1, v1, s4
; SI-NEXT:    s_brev_b32 s4, -2
; SI-NEXT:    v_mov_b32_e32 v2, s17
; SI-NEXT:    v_bfi_b32 v1, s4, v1, v2
; SI-NEXT:  .LBB28_14:
; SI-NEXT:    v_mov_b32_e32 v2, 0x7f800000
; SI-NEXT:    v_cmp_lg_f32_e64 s[4:5], s18, 0
; SI-NEXT:    v_cmp_nge_f32_e64 s[6:7], |s16|, v2
; SI-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; SI-NEXT:    v_mov_b32_e32 v3, 0x7fc00000
; SI-NEXT:    v_cmp_lg_f32_e64 s[4:5], s19, 0
; SI-NEXT:    v_cmp_nge_f32_e64 s[6:7], |s17|, v2
; SI-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc
; SI-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; SI-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; CI-LABEL: frem_v2f32_uniform:
; CI:       ; %bb.0:
; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-NEXT:    v_mov_b32_e32 v0, s18
; CI-NEXT:    v_cmp_gt_f32_e64 vcc, |s16|, |v0|
; CI-NEXT:    s_cbranch_vccz .LBB28_4
; CI-NEXT:  ; %bb.1: ; %frem.compute15
; CI-NEXT:    v_frexp_mant_f32_e64 v1, |s18|
; CI-NEXT:    v_ldexp_f32_e64 v1, v1, 1
; CI-NEXT:    v_div_scale_f32 v7, s[4:5], v1, v1, 1.0
; CI-NEXT:    v_frexp_mant_f32_e64 v0, |s16|
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v6, s18
; CI-NEXT:    v_ldexp_f32_e64 v4, v0, 12
; CI-NEXT:    v_add_i32_e32 v0, vcc, -1, v6
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v5, s16
; CI-NEXT:    v_not_b32_e32 v2, v0
; CI-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
; CI-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v1, 1.0
; CI-NEXT:    v_rcp_f32_e32 v8, v7
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
; CI-NEXT:    v_fma_f32 v8, v9, v8, v8
; CI-NEXT:    v_mul_f32_e32 v9, v3, v8
; CI-NEXT:    v_fma_f32 v10, -v7, v9, v3
; CI-NEXT:    v_fma_f32 v9, v10, v8, v9
; CI-NEXT:    v_fma_f32 v3, -v7, v9, v3
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v3, v3, v8, v9
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v2
; CI-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; CI-NEXT:    s_cbranch_vccnz .LBB28_5
; CI-NEXT:  ; %bb.2: ; %frem.loop_body23.preheader
; CI-NEXT:    v_sub_i32_e32 v2, vcc, v5, v6
; CI-NEXT:    v_add_i32_e32 v2, vcc, 12, v2
; CI-NEXT:  .LBB28_3: ; %frem.loop_body23
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v5, v4
; CI-NEXT:    v_mul_f32_e32 v4, v5, v3
; CI-NEXT:    v_rndne_f32_e32 v4, v4
; CI-NEXT:    v_fma_f32 v4, -v4, v1, v5
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; CI-NEXT:    v_add_f32_e32 v6, v4, v1
; CI-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
; CI-NEXT:    v_add_i32_e32 v2, vcc, -12, v2
; CI-NEXT:    v_ldexp_f32_e64 v4, v4, 12
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v2
; CI-NEXT:    s_cbranch_vccnz .LBB28_3
; CI-NEXT:    s_branch .LBB28_6
; CI-NEXT:  .LBB28_4: ; %frem.else16
; CI-NEXT:    s_and_b32 s4, 0x80000000, s16
; CI-NEXT:    v_mov_b32_e32 v0, s18
; CI-NEXT:    v_cmp_eq_f32_e64 vcc, |s16|, |v0|
; CI-NEXT:    v_mov_b32_e32 v0, s16
; CI-NEXT:    v_mov_b32_e32 v1, s4
; CI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
; CI-NEXT:    s_branch .LBB28_7
; CI-NEXT:  .LBB28_5:
; CI-NEXT:    v_mov_b32_e32 v5, v4
; CI-NEXT:  .LBB28_6: ; %frem.loop_exit24
; CI-NEXT:    v_add_i32_e32 v2, vcc, -11, v2
; CI-NEXT:    v_ldexp_f32_e32 v2, v5, v2
; CI-NEXT:    v_mul_f32_e32 v3, v2, v3
; CI-NEXT:    v_rndne_f32_e32 v3, v3
; CI-NEXT:    v_fma_f32 v2, -v3, v1, v2
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v2
; CI-NEXT:    v_add_f32_e32 v1, v2, v1
; CI-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; CI-NEXT:    v_ldexp_f32_e32 v0, v1, v0
; CI-NEXT:    s_brev_b32 s4, -2
; CI-NEXT:    v_mov_b32_e32 v1, s16
; CI-NEXT:    v_bfi_b32 v0, s4, v0, v1
; CI-NEXT:  .LBB28_7:
; CI-NEXT:    v_mov_b32_e32 v1, s19
; CI-NEXT:    v_cmp_gt_f32_e64 vcc, |s17|, |v1|
; CI-NEXT:    s_cbranch_vccz .LBB28_11
; CI-NEXT:  ; %bb.8: ; %frem.compute
; CI-NEXT:    v_frexp_mant_f32_e64 v2, |s19|
; CI-NEXT:    v_ldexp_f32_e64 v2, v2, 1
; CI-NEXT:    v_div_scale_f32 v8, s[4:5], v2, v2, 1.0
; CI-NEXT:    v_frexp_mant_f32_e64 v1, |s17|
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v7, s19
; CI-NEXT:    v_ldexp_f32_e64 v5, v1, 12
; CI-NEXT:    v_add_i32_e32 v1, vcc, -1, v7
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v6, s17
; CI-NEXT:    v_not_b32_e32 v3, v1
; CI-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
; CI-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v2, 1.0
; CI-NEXT:    v_rcp_f32_e32 v9, v8
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
; CI-NEXT:    v_fma_f32 v9, v10, v9, v9
; CI-NEXT:    v_mul_f32_e32 v10, v4, v9
; CI-NEXT:    v_fma_f32 v11, -v8, v10, v4
; CI-NEXT:    v_fma_f32 v10, v11, v9, v10
; CI-NEXT:    v_fma_f32 v4, -v8, v10, v4
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v4, v4, v9, v10
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v3
; CI-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; CI-NEXT:    s_cbranch_vccnz .LBB28_12
; CI-NEXT:  ; %bb.9: ; %frem.loop_body.preheader
; CI-NEXT:    v_sub_i32_e32 v3, vcc, v6, v7
; CI-NEXT:    v_add_i32_e32 v3, vcc, 12, v3
; CI-NEXT:  .LBB28_10: ; %frem.loop_body
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v6, v5
; CI-NEXT:    v_mul_f32_e32 v5, v6, v4
; CI-NEXT:    v_rndne_f32_e32 v5, v5
; CI-NEXT:    v_fma_f32 v5, -v5, v2, v6
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
; CI-NEXT:    v_add_f32_e32 v7, v5, v2
; CI-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
; CI-NEXT:    v_add_i32_e32 v3, vcc, -12, v3
; CI-NEXT:    v_ldexp_f32_e64 v5, v5, 12
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v3
; CI-NEXT:    s_cbranch_vccnz .LBB28_10
; CI-NEXT:    s_branch .LBB28_13
; CI-NEXT:  .LBB28_11: ; %frem.else
; CI-NEXT:    s_and_b32 s4, 0x80000000, s17
; CI-NEXT:    v_mov_b32_e32 v1, s19
; CI-NEXT:    v_cmp_eq_f32_e64 vcc, |s17|, |v1|
; CI-NEXT:    v_mov_b32_e32 v1, s17
; CI-NEXT:    v_mov_b32_e32 v2, s4
; CI-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
; CI-NEXT:    s_branch .LBB28_14
; CI-NEXT:  .LBB28_12:
; CI-NEXT:    v_mov_b32_e32 v6, v5
; CI-NEXT:  .LBB28_13: ; %frem.loop_exit
; CI-NEXT:    v_add_i32_e32 v3, vcc, -11, v3
; CI-NEXT:    v_ldexp_f32_e32 v3, v6, v3
; CI-NEXT:    v_mul_f32_e32 v4, v3, v4
; CI-NEXT:    v_rndne_f32_e32 v4, v4
; CI-NEXT:    v_fma_f32 v3, -v4, v2, v3
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v3
; CI-NEXT:    v_add_f32_e32 v2, v3, v2
; CI-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; CI-NEXT:    v_ldexp_f32_e32 v1, v2, v1
; CI-NEXT:    s_brev_b32 s4, -2
; CI-NEXT:    v_mov_b32_e32 v2, s17
; CI-NEXT:    v_bfi_b32 v1, s4, v1, v2
; CI-NEXT:  .LBB28_14:
; CI-NEXT:    v_mov_b32_e32 v2, 0x7f800000
; CI-NEXT:    v_cmp_lg_f32_e64 s[4:5], s18, 0
; CI-NEXT:    v_cmp_nge_f32_e64 s[6:7], |s16|, v2
; CI-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; CI-NEXT:    v_mov_b32_e32 v3, 0x7fc00000
; CI-NEXT:    v_cmp_lg_f32_e64 s[4:5], s19, 0
; CI-NEXT:    v_cmp_nge_f32_e64 s[6:7], |s17|, v2
; CI-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc
; CI-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; CI-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
; CI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: frem_v2f32_uniform:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_mov_b32_e32 v0, s18
; VI-NEXT:    v_cmp_gt_f32_e64 vcc, |s16|, |v0|
; VI-NEXT:    s_cbranch_vccz .LBB28_4
; VI-NEXT:  ; %bb.1: ; %frem.compute15
; VI-NEXT:    v_frexp_mant_f32_e64 v1, |s18|
; VI-NEXT:    v_ldexp_f32 v1, v1, 1
; VI-NEXT:    v_div_scale_f32 v7, s[4:5], v1, v1, 1.0
; VI-NEXT:    v_frexp_mant_f32_e64 v0, |s16|
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v6, s18
; VI-NEXT:    v_ldexp_f32 v4, v0, 12
; VI-NEXT:    v_add_u32_e32 v0, vcc, -1, v6
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v5, s16
; VI-NEXT:    v_not_b32_e32 v2, v0
; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v5
; VI-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v1, 1.0
; VI-NEXT:    v_rcp_f32_e32 v8, v7
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
; VI-NEXT:    v_fma_f32 v8, v9, v8, v8
; VI-NEXT:    v_mul_f32_e32 v9, v3, v8
; VI-NEXT:    v_fma_f32 v10, -v7, v9, v3
; VI-NEXT:    v_fma_f32 v9, v10, v8, v9
; VI-NEXT:    v_fma_f32 v3, -v7, v9, v3
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; VI-NEXT:    v_div_fmas_f32 v3, v3, v8, v9
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v2
; VI-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; VI-NEXT:    s_cbranch_vccnz .LBB28_5
; VI-NEXT:  ; %bb.2: ; %frem.loop_body23.preheader
; VI-NEXT:    v_sub_u32_e32 v2, vcc, v5, v6
; VI-NEXT:    v_add_u32_e32 v2, vcc, 12, v2
; VI-NEXT:  .LBB28_3: ; %frem.loop_body23
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v5, v4
; VI-NEXT:    v_mul_f32_e32 v4, v5, v3
; VI-NEXT:    v_rndne_f32_e32 v4, v4
; VI-NEXT:    v_fma_f32 v4, -v4, v1, v5
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; VI-NEXT:    v_add_f32_e32 v6, v4, v1
; VI-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
; VI-NEXT:    v_add_u32_e32 v2, vcc, -12, v2
; VI-NEXT:    v_ldexp_f32 v4, v4, 12
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v2
; VI-NEXT:    s_cbranch_vccnz .LBB28_3
; VI-NEXT:    s_branch .LBB28_6
; VI-NEXT:  .LBB28_4: ; %frem.else16
; VI-NEXT:    s_and_b32 s4, 0x80000000, s16
; VI-NEXT:    v_mov_b32_e32 v0, s18
; VI-NEXT:    v_cmp_eq_f32_e64 vcc, |s16|, |v0|
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
; VI-NEXT:    s_branch .LBB28_7
; VI-NEXT:  .LBB28_5:
; VI-NEXT:    v_mov_b32_e32 v5, v4
; VI-NEXT:  .LBB28_6: ; %frem.loop_exit24
; VI-NEXT:    v_add_u32_e32 v2, vcc, -11, v2
; VI-NEXT:    v_ldexp_f32 v2, v5, v2
; VI-NEXT:    v_mul_f32_e32 v3, v2, v3
; VI-NEXT:    v_rndne_f32_e32 v3, v3
; VI-NEXT:    v_fma_f32 v2, -v3, v1, v2
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v2
; VI-NEXT:    v_add_f32_e32 v1, v2, v1
; VI-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; VI-NEXT:    v_ldexp_f32 v0, v1, v0
; VI-NEXT:    s_brev_b32 s4, -2
; VI-NEXT:    v_mov_b32_e32 v1, s16
; VI-NEXT:    v_bfi_b32 v0, s4, v0, v1
; VI-NEXT:  .LBB28_7:
; VI-NEXT:    v_mov_b32_e32 v1, s19
; VI-NEXT:    v_cmp_gt_f32_e64 vcc, |s17|, |v1|
; VI-NEXT:    s_cbranch_vccz .LBB28_11
; VI-NEXT:  ; %bb.8: ; %frem.compute
; VI-NEXT:    v_frexp_mant_f32_e64 v2, |s19|
; VI-NEXT:    v_ldexp_f32 v2, v2, 1
; VI-NEXT:    v_div_scale_f32 v8, s[4:5], v2, v2, 1.0
; VI-NEXT:    v_frexp_mant_f32_e64 v1, |s17|
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v7, s19
; VI-NEXT:    v_ldexp_f32 v5, v1, 12
; VI-NEXT:    v_add_u32_e32 v1, vcc, -1, v7
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v6, s17
; VI-NEXT:    v_not_b32_e32 v3, v1
; VI-NEXT:    v_add_u32_e32 v3, vcc, v3, v6
; VI-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v2, 1.0
; VI-NEXT:    v_rcp_f32_e32 v9, v8
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
; VI-NEXT:    v_fma_f32 v9, v10, v9, v9
; VI-NEXT:    v_mul_f32_e32 v10, v4, v9
; VI-NEXT:    v_fma_f32 v11, -v8, v10, v4
; VI-NEXT:    v_fma_f32 v10, v11, v9, v10
; VI-NEXT:    v_fma_f32 v4, -v8, v10, v4
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; VI-NEXT:    v_div_fmas_f32 v4, v4, v9, v10
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v3
; VI-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; VI-NEXT:    s_cbranch_vccnz .LBB28_12
; VI-NEXT:  ; %bb.9: ; %frem.loop_body.preheader
; VI-NEXT:    v_sub_u32_e32 v3, vcc, v6, v7
; VI-NEXT:    v_add_u32_e32 v3, vcc, 12, v3
; VI-NEXT:  .LBB28_10: ; %frem.loop_body
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v6, v5
; VI-NEXT:    v_mul_f32_e32 v5, v6, v4
; VI-NEXT:    v_rndne_f32_e32 v5, v5
; VI-NEXT:    v_fma_f32 v5, -v5, v2, v6
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
; VI-NEXT:    v_add_f32_e32 v7, v5, v2
; VI-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
; VI-NEXT:    v_add_u32_e32 v3, vcc, -12, v3
; VI-NEXT:    v_ldexp_f32 v5, v5, 12
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v3
; VI-NEXT:    s_cbranch_vccnz .LBB28_10
; VI-NEXT:    s_branch .LBB28_13
; VI-NEXT:  .LBB28_11: ; %frem.else
; VI-NEXT:    s_and_b32 s4, 0x80000000, s17
; VI-NEXT:    v_mov_b32_e32 v1, s19
; VI-NEXT:    v_cmp_eq_f32_e64 vcc, |s17|, |v1|
; VI-NEXT:    v_mov_b32_e32 v1, s17
; VI-NEXT:    v_mov_b32_e32 v2, s4
; VI-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
; VI-NEXT:    s_branch .LBB28_14
; VI-NEXT:  .LBB28_12:
; VI-NEXT:    v_mov_b32_e32 v6, v5
; VI-NEXT:  .LBB28_13: ; %frem.loop_exit
; VI-NEXT:    v_add_u32_e32 v3, vcc, -11, v3
; VI-NEXT:    v_ldexp_f32 v3, v6, v3
; VI-NEXT:    v_mul_f32_e32 v4, v3, v4
; VI-NEXT:    v_rndne_f32_e32 v4, v4
; VI-NEXT:    v_fma_f32 v3, -v4, v2, v3
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v3
; VI-NEXT:    v_add_f32_e32 v2, v3, v2
; VI-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; VI-NEXT:    v_ldexp_f32 v1, v2, v1
; VI-NEXT:    s_brev_b32 s4, -2
; VI-NEXT:    v_mov_b32_e32 v2, s17
; VI-NEXT:    v_bfi_b32 v1, s4, v1, v2
; VI-NEXT:  .LBB28_14:
; VI-NEXT:    v_mov_b32_e32 v2, 0x7f800000
; VI-NEXT:    v_cmp_lg_f32_e64 s[4:5], s18, 0
; VI-NEXT:    v_cmp_nge_f32_e64 s[6:7], |s16|, v2
; VI-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; VI-NEXT:    v_mov_b32_e32 v3, 0x7fc00000
; VI-NEXT:    v_cmp_lg_f32_e64 s[4:5], s19, 0
; VI-NEXT:    v_cmp_nge_f32_e64 s[6:7], |s17|, v2
; VI-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc
; VI-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; VI-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: frem_v2f32_uniform:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v0, s18
; GFX9-NEXT:    v_cmp_gt_f32_e64 vcc, |s16|, |v0|
; GFX9-NEXT:    s_cbranch_vccz .LBB28_4
; GFX9-NEXT:  ; %bb.1: ; %frem.compute15
; GFX9-NEXT:    v_frexp_mant_f32_e64 v1, |s18|
; GFX9-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX9-NEXT:    v_div_scale_f32 v7, s[4:5], v1, v1, 1.0
; GFX9-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v1, 1.0
; GFX9-NEXT:    v_frexp_mant_f32_e64 v0, |s16|
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v5, s16
; GFX9-NEXT:    v_ldexp_f32 v4, v0, 12
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v6, s18
; GFX9-NEXT:    v_add_u32_e32 v0, -1, v6
; GFX9-NEXT:    v_not_b32_e32 v2, v0
; GFX9-NEXT:    v_add_u32_e32 v2, v2, v5
; GFX9-NEXT:    v_rcp_f32_e32 v8, v7
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
; GFX9-NEXT:    v_fma_f32 v8, v9, v8, v8
; GFX9-NEXT:    v_mul_f32_e32 v9, v3, v8
; GFX9-NEXT:    v_fma_f32 v10, -v7, v9, v3
; GFX9-NEXT:    v_fma_f32 v9, v10, v8, v9
; GFX9-NEXT:    v_fma_f32 v3, -v7, v9, v3
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX9-NEXT:    v_div_fmas_f32 v3, v3, v8, v9
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v2
; GFX9-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX9-NEXT:    s_cbranch_vccnz .LBB28_5
; GFX9-NEXT:  ; %bb.2: ; %frem.loop_body23.preheader
; GFX9-NEXT:    v_sub_u32_e32 v2, v5, v6
; GFX9-NEXT:    v_add_u32_e32 v2, 12, v2
; GFX9-NEXT:  .LBB28_3: ; %frem.loop_body23
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v5, v4
; GFX9-NEXT:    v_mul_f32_e32 v4, v5, v3
; GFX9-NEXT:    v_rndne_f32_e32 v4, v4
; GFX9-NEXT:    v_fma_f32 v4, -v4, v1, v5
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; GFX9-NEXT:    v_add_f32_e32 v6, v4, v1
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX9-NEXT:    v_add_u32_e32 v2, -12, v2
; GFX9-NEXT:    v_ldexp_f32 v4, v4, 12
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v2
; GFX9-NEXT:    s_cbranch_vccnz .LBB28_3
; GFX9-NEXT:    s_branch .LBB28_6
; GFX9-NEXT:  .LBB28_4: ; %frem.else16
; GFX9-NEXT:    s_and_b32 s4, 0x80000000, s16
; GFX9-NEXT:    v_mov_b32_e32 v0, s18
; GFX9-NEXT:    v_cmp_eq_f32_e64 vcc, |s16|, |v0|
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s4
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX9-NEXT:    s_branch .LBB28_7
; GFX9-NEXT:  .LBB28_5:
; GFX9-NEXT:    v_mov_b32_e32 v5, v4
; GFX9-NEXT:  .LBB28_6: ; %frem.loop_exit24
; GFX9-NEXT:    v_add_u32_e32 v2, -11, v2
; GFX9-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX9-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX9-NEXT:    v_rndne_f32_e32 v3, v3
; GFX9-NEXT:    v_fma_f32 v2, -v3, v1, v2
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v2
; GFX9-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX9-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX9-NEXT:    s_brev_b32 s4, -2
; GFX9-NEXT:    v_mov_b32_e32 v1, s16
; GFX9-NEXT:    v_bfi_b32 v0, s4, v0, v1
; GFX9-NEXT:  .LBB28_7:
; GFX9-NEXT:    v_mov_b32_e32 v1, s19
; GFX9-NEXT:    v_cmp_gt_f32_e64 vcc, |s17|, |v1|
; GFX9-NEXT:    s_cbranch_vccz .LBB28_11
; GFX9-NEXT:  ; %bb.8: ; %frem.compute
; GFX9-NEXT:    v_frexp_mant_f32_e64 v2, |s19|
; GFX9-NEXT:    v_ldexp_f32 v2, v2, 1
; GFX9-NEXT:    v_div_scale_f32 v8, s[4:5], v2, v2, 1.0
; GFX9-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v2, 1.0
; GFX9-NEXT:    v_frexp_mant_f32_e64 v1, |s17|
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v6, s17
; GFX9-NEXT:    v_ldexp_f32 v5, v1, 12
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v7, s19
; GFX9-NEXT:    v_add_u32_e32 v1, -1, v7
; GFX9-NEXT:    v_not_b32_e32 v3, v1
; GFX9-NEXT:    v_add_u32_e32 v3, v3, v6
; GFX9-NEXT:    v_rcp_f32_e32 v9, v8
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
; GFX9-NEXT:    v_fma_f32 v9, v10, v9, v9
; GFX9-NEXT:    v_mul_f32_e32 v10, v4, v9
; GFX9-NEXT:    v_fma_f32 v11, -v8, v10, v4
; GFX9-NEXT:    v_fma_f32 v10, v11, v9, v10
; GFX9-NEXT:    v_fma_f32 v4, -v8, v10, v4
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX9-NEXT:    v_div_fmas_f32 v4, v4, v9, v10
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v3
; GFX9-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; GFX9-NEXT:    s_cbranch_vccnz .LBB28_12
; GFX9-NEXT:  ; %bb.9: ; %frem.loop_body.preheader
; GFX9-NEXT:    v_sub_u32_e32 v3, v6, v7
; GFX9-NEXT:    v_add_u32_e32 v3, 12, v3
; GFX9-NEXT:  .LBB28_10: ; %frem.loop_body
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v6, v5
; GFX9-NEXT:    v_mul_f32_e32 v5, v6, v4
; GFX9-NEXT:    v_rndne_f32_e32 v5, v5
; GFX9-NEXT:    v_fma_f32 v5, -v5, v2, v6
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
; GFX9-NEXT:    v_add_f32_e32 v7, v5, v2
; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
; GFX9-NEXT:    v_add_u32_e32 v3, -12, v3
; GFX9-NEXT:    v_ldexp_f32 v5, v5, 12
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v3
; GFX9-NEXT:    s_cbranch_vccnz .LBB28_10
; GFX9-NEXT:    s_branch .LBB28_13
; GFX9-NEXT:  .LBB28_11: ; %frem.else
; GFX9-NEXT:    s_and_b32 s4, 0x80000000, s17
; GFX9-NEXT:    v_mov_b32_e32 v1, s19
; GFX9-NEXT:    v_cmp_eq_f32_e64 vcc, |s17|, |v1|
; GFX9-NEXT:    v_mov_b32_e32 v1, s17
; GFX9-NEXT:    v_mov_b32_e32 v2, s4
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX9-NEXT:    s_branch .LBB28_14
; GFX9-NEXT:  .LBB28_12:
; GFX9-NEXT:    v_mov_b32_e32 v6, v5
; GFX9-NEXT:  .LBB28_13: ; %frem.loop_exit
; GFX9-NEXT:    v_add_u32_e32 v3, -11, v3
; GFX9-NEXT:    v_ldexp_f32 v3, v6, v3
; GFX9-NEXT:    v_mul_f32_e32 v4, v3, v4
; GFX9-NEXT:    v_rndne_f32_e32 v4, v4
; GFX9-NEXT:    v_fma_f32 v3, -v4, v2, v3
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v3
; GFX9-NEXT:    v_add_f32_e32 v2, v3, v2
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX9-NEXT:    v_ldexp_f32 v1, v2, v1
; GFX9-NEXT:    s_brev_b32 s4, -2
; GFX9-NEXT:    v_mov_b32_e32 v2, s17
; GFX9-NEXT:    v_bfi_b32 v1, s4, v1, v2
; GFX9-NEXT:  .LBB28_14:
; GFX9-NEXT:    v_mov_b32_e32 v2, 0x7f800000
; GFX9-NEXT:    v_cmp_lg_f32_e64 s[4:5], s18, 0
; GFX9-NEXT:    v_cmp_nge_f32_e64 s[6:7], |s16|, v2
; GFX9-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; GFX9-NEXT:    v_mov_b32_e32 v3, 0x7fc00000
; GFX9-NEXT:    v_cmp_lg_f32_e64 s[4:5], s19, 0
; GFX9-NEXT:    v_cmp_nge_f32_e64 s[6:7], |s17|, v2
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc
; GFX9-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: frem_v2f32_uniform:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cmp_gt_f32_e64 vcc_lo, |s16|, |s18|
; GFX10-NEXT:    s_cbranch_vccz .LBB28_5
; GFX10-NEXT:  ; %bb.1: ; %frem.compute15
; GFX10-NEXT:    v_frexp_mant_f32_e64 v1, |s18|
; GFX10-NEXT:    v_frexp_mant_f32_e64 v0, |s16|
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v3, s16
; GFX10-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX10-NEXT:    v_ldexp_f32 v2, v0, 12
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v0, s18
; GFX10-NEXT:    v_readfirstlane_b32 s4, v3
; GFX10-NEXT:    v_div_scale_f32 v5, s6, v1, v1, 1.0
; GFX10-NEXT:    v_readfirstlane_b32 s5, v0
; GFX10-NEXT:    v_add_nc_u32_e32 v0, -1, v0
; GFX10-NEXT:    v_rcp_f32_e32 v6, v5
; GFX10-NEXT:    v_not_b32_e32 v4, v0
; GFX10-NEXT:    v_add_nc_u32_e32 v4, v4, v3
; GFX10-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX10-NEXT:    s_denorm_mode 15
; GFX10-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
; GFX10-NEXT:    v_fmac_f32_e32 v6, v7, v6
; GFX10-NEXT:    v_mul_f32_e32 v7, v3, v6
; GFX10-NEXT:    v_fma_f32 v8, -v5, v7, v3
; GFX10-NEXT:    v_fmac_f32_e32 v7, v8, v6
; GFX10-NEXT:    v_fma_f32 v3, -v5, v7, v3
; GFX10-NEXT:    s_denorm_mode 12
; GFX10-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v4
; GFX10-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX10-NEXT:    s_cbranch_vccnz .LBB28_7
; GFX10-NEXT:  ; %bb.2: ; %frem.loop_body23.preheader
; GFX10-NEXT:    s_sub_i32 s4, s4, s5
; GFX10-NEXT:    s_add_i32 s4, s4, 12
; GFX10-NEXT:  .LBB28_3: ; %frem.loop_body23
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v5, v2
; GFX10-NEXT:    s_add_i32 s4, s4, -12
; GFX10-NEXT:    s_cmp_gt_i32 s4, 12
; GFX10-NEXT:    v_mul_f32_e32 v2, v5, v3
; GFX10-NEXT:    v_rndne_f32_e32 v2, v2
; GFX10-NEXT:    v_fma_f32 v2, -v2, v1, v5
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX10-NEXT:    v_add_f32_e32 v4, v2, v1
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v2, v2, 12
; GFX10-NEXT:    s_cbranch_scc1 .LBB28_3
; GFX10-NEXT:  ; %bb.4:
; GFX10-NEXT:    v_mov_b32_e32 v4, s4
; GFX10-NEXT:    s_branch .LBB28_8
; GFX10-NEXT:  .LBB28_5: ; %frem.else16
; GFX10-NEXT:    s_and_b32 s4, 0x80000000, s16
; GFX10-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |s16|, |s18|
; GFX10-NEXT:    v_mov_b32_e32 v0, s4
; GFX10-NEXT:    v_cndmask_b32_e32 v0, s16, v0, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e64 vcc_lo, |s17|, |s19|
; GFX10-NEXT:    s_cbranch_vccnz .LBB28_9
; GFX10-NEXT:  .LBB28_6: ; %frem.else
; GFX10-NEXT:    s_and_b32 s4, 0x80000000, s17
; GFX10-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |s17|, |s19|
; GFX10-NEXT:    v_mov_b32_e32 v1, s4
; GFX10-NEXT:    v_cndmask_b32_e32 v1, s17, v1, vcc_lo
; GFX10-NEXT:    s_branch .LBB28_15
; GFX10-NEXT:  .LBB28_7:
; GFX10-NEXT:    v_mov_b32_e32 v5, v2
; GFX10-NEXT:  .LBB28_8: ; %frem.loop_exit24
; GFX10-NEXT:    v_add_nc_u32_e32 v2, -11, v4
; GFX10-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX10-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX10-NEXT:    v_rndne_f32_e32 v3, v3
; GFX10-NEXT:    v_fma_f32 v2, -v3, v1, v2
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX10-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX10-NEXT:    v_bfi_b32 v0, 0x7fffffff, v0, s16
; GFX10-NEXT:    v_cmp_gt_f32_e64 vcc_lo, |s17|, |s19|
; GFX10-NEXT:    s_cbranch_vccz .LBB28_6
; GFX10-NEXT:  .LBB28_9: ; %frem.compute
; GFX10-NEXT:    v_frexp_mant_f32_e64 v2, |s19|
; GFX10-NEXT:    v_frexp_mant_f32_e64 v1, |s17|
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v4, s17
; GFX10-NEXT:    v_ldexp_f32 v2, v2, 1
; GFX10-NEXT:    v_ldexp_f32 v3, v1, 12
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v1, s19
; GFX10-NEXT:    v_readfirstlane_b32 s4, v4
; GFX10-NEXT:    v_div_scale_f32 v6, s6, v2, v2, 1.0
; GFX10-NEXT:    v_readfirstlane_b32 s5, v1
; GFX10-NEXT:    v_add_nc_u32_e32 v1, -1, v1
; GFX10-NEXT:    v_rcp_f32_e32 v7, v6
; GFX10-NEXT:    v_not_b32_e32 v5, v1
; GFX10-NEXT:    v_add_nc_u32_e32 v5, v5, v4
; GFX10-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
; GFX10-NEXT:    s_denorm_mode 15
; GFX10-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
; GFX10-NEXT:    v_fmac_f32_e32 v7, v8, v7
; GFX10-NEXT:    v_mul_f32_e32 v8, v4, v7
; GFX10-NEXT:    v_fma_f32 v9, -v6, v8, v4
; GFX10-NEXT:    v_fmac_f32_e32 v8, v9, v7
; GFX10-NEXT:    v_fma_f32 v4, -v6, v8, v4
; GFX10-NEXT:    s_denorm_mode 12
; GFX10-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v5
; GFX10-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; GFX10-NEXT:    s_cbranch_vccnz .LBB28_13
; GFX10-NEXT:  ; %bb.10: ; %frem.loop_body.preheader
; GFX10-NEXT:    s_sub_i32 s4, s4, s5
; GFX10-NEXT:    s_add_i32 s4, s4, 12
; GFX10-NEXT:  .LBB28_11: ; %frem.loop_body
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v6, v3
; GFX10-NEXT:    s_add_i32 s4, s4, -12
; GFX10-NEXT:    s_cmp_gt_i32 s4, 12
; GFX10-NEXT:    v_mul_f32_e32 v3, v6, v4
; GFX10-NEXT:    v_rndne_f32_e32 v3, v3
; GFX10-NEXT:    v_fma_f32 v3, -v3, v2, v6
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX10-NEXT:    v_add_f32_e32 v5, v3, v2
; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v3, v3, 12
; GFX10-NEXT:    s_cbranch_scc1 .LBB28_11
; GFX10-NEXT:  ; %bb.12:
; GFX10-NEXT:    v_mov_b32_e32 v5, s4
; GFX10-NEXT:    s_branch .LBB28_14
; GFX10-NEXT:  .LBB28_13:
; GFX10-NEXT:    v_mov_b32_e32 v6, v3
; GFX10-NEXT:  .LBB28_14: ; %frem.loop_exit
; GFX10-NEXT:    v_add_nc_u32_e32 v3, -11, v5
; GFX10-NEXT:    v_ldexp_f32 v3, v6, v3
; GFX10-NEXT:    v_mul_f32_e32 v4, v3, v4
; GFX10-NEXT:    v_rndne_f32_e32 v4, v4
; GFX10-NEXT:    v_fma_f32 v3, -v4, v2, v3
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX10-NEXT:    v_add_f32_e32 v2, v3, v2
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v1, v2, v1
; GFX10-NEXT:    v_bfi_b32 v1, 0x7fffffff, v1, s17
; GFX10-NEXT:  .LBB28_15:
; GFX10-NEXT:    v_cmp_lg_f32_e64 s4, s18, 0
; GFX10-NEXT:    v_cmp_nge_f32_e64 s5, |s16|, 0x7f800000
; GFX10-NEXT:    s_and_b32 vcc_lo, s5, s4
; GFX10-NEXT:    v_cmp_lg_f32_e64 s4, s19, 0
; GFX10-NEXT:    v_cmp_nge_f32_e64 s5, |s17|, 0x7f800000
; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
; GFX10-NEXT:    s_and_b32 vcc_lo, s5, s4
; GFX10-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v1, vcc_lo
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: frem_v2f32_uniform:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cmp_gt_f32_e64 vcc_lo, |s0|, |s2|
; GFX11-NEXT:    s_cbranch_vccz .LBB28_5
; GFX11-NEXT:  ; %bb.1: ; %frem.compute15
; GFX11-NEXT:    v_frexp_mant_f32_e64 v1, |s2|
; GFX11-NEXT:    v_frexp_mant_f32_e64 v0, |s0|
; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v3, s0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX11-NEXT:    v_ldexp_f32 v2, v0, 12
; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v0, s2
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_readfirstlane_b32 s4, v3
; GFX11-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_readfirstlane_b32 s5, v0
; GFX11-NEXT:    v_add_nc_u32_e32 v0, -1, v0
; GFX11-NEXT:    v_rcp_f32_e32 v6, v5
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_not_b32_e32 v4, v0
; GFX11-NEXT:    v_add_nc_u32_e32 v4, v4, v3
; GFX11-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX11-NEXT:    s_denorm_mode 15
; GFX11-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fmac_f32_e32 v6, v7, v6
; GFX11-NEXT:    v_mul_f32_e32 v7, v3, v6
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v8, -v5, v7, v3
; GFX11-NEXT:    v_fmac_f32_e32 v7, v8, v6
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v3, -v5, v7, v3
; GFX11-NEXT:    s_denorm_mode 12
; GFX11-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v4
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX11-NEXT:    s_cbranch_vccnz .LBB28_7
; GFX11-NEXT:  ; %bb.2: ; %frem.loop_body23.preheader
; GFX11-NEXT:    s_sub_i32 s4, s4, s5
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_add_i32 s4, s4, 12
; GFX11-NEXT:  .LBB28_3: ; %frem.loop_body23
; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT:    v_mov_b32_e32 v5, v2
; GFX11-NEXT:    s_add_i32 s4, s4, -12
; GFX11-NEXT:    s_cmp_gt_i32 s4, 12
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_mul_f32_e32 v2, v5, v3
; GFX11-NEXT:    v_rndne_f32_e32 v2, v2
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v2, -v2, v1, v5
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX11-NEXT:    v_add_f32_e32 v4, v2, v1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX11-NEXT:    v_ldexp_f32 v2, v2, 12
; GFX11-NEXT:    s_cbranch_scc1 .LBB28_3
; GFX11-NEXT:  ; %bb.4:
; GFX11-NEXT:    v_mov_b32_e32 v4, s4
; GFX11-NEXT:    s_branch .LBB28_8
; GFX11-NEXT:  .LBB28_5: ; %frem.else16
; GFX11-NEXT:    s_and_b32 s4, 0x80000000, s0
; GFX11-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |s0|, |s2|
; GFX11-NEXT:    v_mov_b32_e32 v0, s4
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_cndmask_b32_e32 v0, s0, v0, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e64 vcc_lo, |s1|, |s3|
; GFX11-NEXT:    s_cbranch_vccnz .LBB28_9
; GFX11-NEXT:  .LBB28_6: ; %frem.else
; GFX11-NEXT:    s_and_b32 s4, 0x80000000, s1
; GFX11-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |s1|, |s3|
; GFX11-NEXT:    v_mov_b32_e32 v1, s4
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_cndmask_b32_e32 v1, s1, v1, vcc_lo
; GFX11-NEXT:    s_branch .LBB28_15
; GFX11-NEXT:  .LBB28_7:
; GFX11-NEXT:    v_mov_b32_e32 v5, v2
; GFX11-NEXT:  .LBB28_8: ; %frem.loop_exit24
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_add_nc_u32_e32 v2, -11, v4
; GFX11-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX11-NEXT:    v_rndne_f32_e32 v3, v3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v2, -v3, v1, v2
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX11-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX11-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_bfi_b32 v0, 0x7fffffff, v0, s0
; GFX11-NEXT:    v_cmp_gt_f32_e64 vcc_lo, |s1|, |s3|
; GFX11-NEXT:    s_cbranch_vccz .LBB28_6
; GFX11-NEXT:  .LBB28_9: ; %frem.compute
; GFX11-NEXT:    v_frexp_mant_f32_e64 v2, |s3|
; GFX11-NEXT:    v_frexp_mant_f32_e64 v1, |s1|
; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v4, s1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_ldexp_f32 v2, v2, 1
; GFX11-NEXT:    v_ldexp_f32 v3, v1, 12
; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v1, s3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_readfirstlane_b32 s4, v4
; GFX11-NEXT:    v_div_scale_f32 v6, null, v2, v2, 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_readfirstlane_b32 s5, v1
; GFX11-NEXT:    v_add_nc_u32_e32 v1, -1, v1
; GFX11-NEXT:    v_rcp_f32_e32 v7, v6
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_not_b32_e32 v5, v1
; GFX11-NEXT:    v_add_nc_u32_e32 v5, v5, v4
; GFX11-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
; GFX11-NEXT:    s_denorm_mode 15
; GFX11-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fmac_f32_e32 v7, v8, v7
; GFX11-NEXT:    v_mul_f32_e32 v8, v4, v7
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v9, -v6, v8, v4
; GFX11-NEXT:    v_fmac_f32_e32 v8, v9, v7
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v4, -v6, v8, v4
; GFX11-NEXT:    s_denorm_mode 12
; GFX11-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v5
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; GFX11-NEXT:    s_cbranch_vccnz .LBB28_13
; GFX11-NEXT:  ; %bb.10: ; %frem.loop_body.preheader
; GFX11-NEXT:    s_sub_i32 s4, s4, s5
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_add_i32 s4, s4, 12
; GFX11-NEXT:  .LBB28_11: ; %frem.loop_body
; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT:    v_mov_b32_e32 v6, v3
; GFX11-NEXT:    s_add_i32 s4, s4, -12
; GFX11-NEXT:    s_cmp_gt_i32 s4, 12
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_mul_f32_e32 v3, v6, v4
; GFX11-NEXT:    v_rndne_f32_e32 v3, v3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v3, -v3, v2, v6
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX11-NEXT:    v_add_f32_e32 v5, v3, v2
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX11-NEXT:    v_ldexp_f32 v3, v3, 12
; GFX11-NEXT:    s_cbranch_scc1 .LBB28_11
; GFX11-NEXT:  ; %bb.12:
; GFX11-NEXT:    v_mov_b32_e32 v5, s4
; GFX11-NEXT:    s_branch .LBB28_14
; GFX11-NEXT:  .LBB28_13:
; GFX11-NEXT:    v_mov_b32_e32 v6, v3
; GFX11-NEXT:  .LBB28_14: ; %frem.loop_exit
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_add_nc_u32_e32 v3, -11, v5
; GFX11-NEXT:    v_ldexp_f32 v3, v6, v3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_mul_f32_e32 v4, v3, v4
; GFX11-NEXT:    v_rndne_f32_e32 v4, v4
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v3, -v4, v2, v3
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX11-NEXT:    v_add_f32_e32 v2, v3, v2
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX11-NEXT:    v_ldexp_f32 v1, v2, v1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_bfi_b32 v1, 0x7fffffff, v1, s1
; GFX11-NEXT:  .LBB28_15:
; GFX11-NEXT:    v_cmp_lg_f32_e64 s2, s2, 0
; GFX11-NEXT:    v_cmp_nge_f32_e64 s0, |s0|, 0x7f800000
; GFX11-NEXT:    v_cmp_nge_f32_e64 s1, |s1|, 0x7f800000
; GFX11-NEXT:    s_and_b32 vcc_lo, s0, s2
; GFX11-NEXT:    v_cmp_lg_f32_e64 s0, s3, 0
; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
; GFX11-NEXT:    s_and_b32 vcc_lo, s1, s0
; GFX11-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v1, vcc_lo
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-LABEL: frem_v2f32_uniform:
; GFX1150:       ; %bb.0:
; GFX1150-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-NEXT:    s_and_b32 s4, s0, 0x7fffffff
; GFX1150-NEXT:    s_and_b32 s5, s2, 0x7fffffff
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_cmp_gt_f32 s4, s5
; GFX1150-NEXT:    s_cbranch_scc0 .LBB28_5
; GFX1150-NEXT:  ; %bb.1: ; %frem.compute15
; GFX1150-NEXT:    v_frexp_mant_f32_e64 v1, |s2|
; GFX1150-NEXT:    v_frexp_mant_f32_e64 v0, |s0|
; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v3, s0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX1150-NEXT:    v_ldexp_f32 v2, v0, 12
; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v0, s2
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1150-NEXT:    v_readfirstlane_b32 s5, v3
; GFX1150-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_readfirstlane_b32 s6, v0
; GFX1150-NEXT:    v_add_nc_u32_e32 v0, -1, v0
; GFX1150-NEXT:    v_rcp_f32_e32 v6, v5
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_not_b32_e32 v4, v0
; GFX1150-NEXT:    v_add_nc_u32_e32 v4, v4, v3
; GFX1150-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX1150-NEXT:    s_denorm_mode 15
; GFX1150-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
; GFX1150-NEXT:    v_fmac_f32_e32 v6, v7, v6
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f32_e32 v7, v3, v6
; GFX1150-NEXT:    v_fma_f32 v8, -v5, v7, v3
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fmac_f32_e32 v7, v8, v6
; GFX1150-NEXT:    v_fma_f32 v3, -v5, v7, v3
; GFX1150-NEXT:    s_denorm_mode 12
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
; GFX1150-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v4
; GFX1150-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX1150-NEXT:    s_cbranch_vccnz .LBB28_6
; GFX1150-NEXT:  ; %bb.2: ; %frem.loop_body23.preheader
; GFX1150-NEXT:    s_sub_i32 s5, s5, s6
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_add_i32 s5, s5, 12
; GFX1150-NEXT:  .LBB28_3: ; %frem.loop_body23
; GFX1150-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT:    v_mov_b32_e32 v5, v2
; GFX1150-NEXT:    s_add_i32 s5, s5, -12
; GFX1150-NEXT:    s_cmp_gt_i32 s5, 12
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f32_e32 v2, v5, v3
; GFX1150-NEXT:    v_rndne_f32_e32 v2, v2
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_xor_b32_e32 v2, 0x80000000, v2
; GFX1150-NEXT:    v_fma_f32 v2, v2, v1, v5
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1150-NEXT:    v_add_f32_e32 v4, v2, v1
; GFX1150-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f32 v2, v2, 12
; GFX1150-NEXT:    s_cbranch_scc1 .LBB28_3
; GFX1150-NEXT:  ; %bb.4:
; GFX1150-NEXT:    v_mov_b32_e32 v4, s5
; GFX1150-NEXT:    s_branch .LBB28_7
; GFX1150-NEXT:  .LBB28_5: ; %frem.else16
; GFX1150-NEXT:    s_and_b32 s6, 0x80000000, s0
; GFX1150-NEXT:    s_cmp_eq_f32 s4, s5
; GFX1150-NEXT:    v_mov_b32_e32 v0, s6
; GFX1150-NEXT:    s_cselect_b32 vcc_lo, -1, 0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_cndmask_b32_e32 v0, s0, v0, vcc_lo
; GFX1150-NEXT:    s_branch .LBB28_8
; GFX1150-NEXT:  .LBB28_6:
; GFX1150-NEXT:    v_mov_b32_e32 v5, v2
; GFX1150-NEXT:  .LBB28_7: ; %frem.loop_exit24
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_add_nc_u32_e32 v2, -11, v4
; GFX1150-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX1150-NEXT:    v_rndne_f32_e32 v3, v3
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
; GFX1150-NEXT:    v_fmac_f32_e32 v2, v3, v1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1150-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX1150-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX1150-NEXT:    v_bfi_b32 v0, 0x7fffffff, v0, s0
; GFX1150-NEXT:  .LBB28_8:
; GFX1150-NEXT:    s_and_b32 s0, s1, 0x7fffffff
; GFX1150-NEXT:    s_and_b32 s5, s3, 0x7fffffff
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_cmp_gt_f32 s0, s5
; GFX1150-NEXT:    s_cbranch_scc0 .LBB28_13
; GFX1150-NEXT:  ; %bb.9: ; %frem.compute
; GFX1150-NEXT:    v_frexp_mant_f32_e64 v2, |s3|
; GFX1150-NEXT:    v_frexp_mant_f32_e64 v1, |s1|
; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v4, s1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_ldexp_f32 v2, v2, 1
; GFX1150-NEXT:    v_ldexp_f32 v3, v1, 12
; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v1, s3
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1150-NEXT:    v_readfirstlane_b32 s5, v4
; GFX1150-NEXT:    v_div_scale_f32 v6, null, v2, v2, 1.0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_readfirstlane_b32 s6, v1
; GFX1150-NEXT:    v_add_nc_u32_e32 v1, -1, v1
; GFX1150-NEXT:    v_rcp_f32_e32 v7, v6
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_not_b32_e32 v5, v1
; GFX1150-NEXT:    v_add_nc_u32_e32 v5, v5, v4
; GFX1150-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
; GFX1150-NEXT:    s_denorm_mode 15
; GFX1150-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
; GFX1150-NEXT:    v_fmac_f32_e32 v7, v8, v7
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f32_e32 v8, v4, v7
; GFX1150-NEXT:    v_fma_f32 v9, -v6, v8, v4
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fmac_f32_e32 v8, v9, v7
; GFX1150-NEXT:    v_fma_f32 v4, -v6, v8, v4
; GFX1150-NEXT:    s_denorm_mode 12
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
; GFX1150-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v5
; GFX1150-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; GFX1150-NEXT:    s_cbranch_vccnz .LBB28_14
; GFX1150-NEXT:  ; %bb.10: ; %frem.loop_body.preheader
; GFX1150-NEXT:    s_sub_i32 s5, s5, s6
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_add_i32 s5, s5, 12
; GFX1150-NEXT:  .LBB28_11: ; %frem.loop_body
; GFX1150-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT:    v_mov_b32_e32 v6, v3
; GFX1150-NEXT:    s_add_i32 s5, s5, -12
; GFX1150-NEXT:    s_cmp_gt_i32 s5, 12
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f32_e32 v3, v6, v4
; GFX1150-NEXT:    v_rndne_f32_e32 v3, v3
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
; GFX1150-NEXT:    v_fma_f32 v3, v3, v2, v6
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1150-NEXT:    v_add_f32_e32 v5, v3, v2
; GFX1150-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f32 v3, v3, 12
; GFX1150-NEXT:    s_cbranch_scc1 .LBB28_11
; GFX1150-NEXT:  ; %bb.12:
; GFX1150-NEXT:    v_mov_b32_e32 v5, s5
; GFX1150-NEXT:    s_branch .LBB28_15
; GFX1150-NEXT:  .LBB28_13: ; %frem.else
; GFX1150-NEXT:    s_and_b32 s6, 0x80000000, s1
; GFX1150-NEXT:    s_cmp_eq_f32 s0, s5
; GFX1150-NEXT:    v_mov_b32_e32 v1, s6
; GFX1150-NEXT:    s_cselect_b32 vcc_lo, -1, 0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_cndmask_b32_e32 v1, s1, v1, vcc_lo
; GFX1150-NEXT:    s_branch .LBB28_16
; GFX1150-NEXT:  .LBB28_14:
; GFX1150-NEXT:    v_mov_b32_e32 v6, v3
; GFX1150-NEXT:  .LBB28_15: ; %frem.loop_exit
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_add_nc_u32_e32 v3, -11, v5
; GFX1150-NEXT:    v_ldexp_f32 v3, v6, v3
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f32_e32 v4, v3, v4
; GFX1150-NEXT:    v_rndne_f32_e32 v4, v4
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
; GFX1150-NEXT:    v_fmac_f32_e32 v3, v4, v2
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1150-NEXT:    v_add_f32_e32 v2, v3, v2
; GFX1150-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f32 v1, v2, v1
; GFX1150-NEXT:    v_bfi_b32 v1, 0x7fffffff, v1, s1
; GFX1150-NEXT:  .LBB28_16:
; GFX1150-NEXT:    s_cmp_lg_f32 s2, 0
; GFX1150-NEXT:    s_cselect_b32 s1, -1, 0
; GFX1150-NEXT:    s_cmp_nge_f32 s4, 0x7f800000
; GFX1150-NEXT:    s_cselect_b32 s2, -1, 0
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_and_b32 vcc_lo, s2, s1
; GFX1150-NEXT:    s_cmp_lg_f32 s3, 0
; GFX1150-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
; GFX1150-NEXT:    s_cselect_b32 s1, -1, 0
; GFX1150-NEXT:    s_cmp_nge_f32 s0, 0x7f800000
; GFX1150-NEXT:    s_cselect_b32 s0, -1, 0
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_and_b32 vcc_lo, s0, s1
; GFX1150-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v1, vcc_lo
; GFX1150-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: frem_v2f32_uniform:
; GFX1200:       ; %bb.0:
; GFX1200-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT:    s_wait_expcnt 0x0
; GFX1200-NEXT:    s_wait_samplecnt 0x0
; GFX1200-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-NEXT:    s_wait_kmcnt 0x0
; GFX1200-NEXT:    s_and_b32 s4, s0, 0x7fffffff
; GFX1200-NEXT:    s_and_b32 s5, s2, 0x7fffffff
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_cmp_gt_f32 s4, s5
; GFX1200-NEXT:    s_cbranch_scc0 .LBB28_5
; GFX1200-NEXT:  ; %bb.1: ; %frem.compute15
; GFX1200-NEXT:    v_frexp_mant_f32_e64 v1, |s2|
; GFX1200-NEXT:    v_frexp_mant_f32_e64 v0, |s0|
; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v3, s0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX1200-NEXT:    v_ldexp_f32 v2, v0, 12
; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v0, s2
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-NEXT:    v_readfirstlane_b32 s5, v3
; GFX1200-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1200-NEXT:    v_readfirstlane_b32 s6, v0
; GFX1200-NEXT:    v_add_nc_u32_e32 v0, -1, v0
; GFX1200-NEXT:    v_rcp_f32_e32 v6, v5
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_not_b32_e32 v4, v0
; GFX1200-NEXT:    v_add_nc_u32_e32 v4, v4, v3
; GFX1200-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX1200-NEXT:    s_denorm_mode 15
; GFX1200-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
; GFX1200-NEXT:    v_fmac_f32_e32 v6, v7, v6
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_mul_f32_e32 v7, v3, v6
; GFX1200-NEXT:    v_fma_f32 v8, -v5, v7, v3
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fmac_f32_e32 v7, v8, v6
; GFX1200-NEXT:    v_fma_f32 v3, -v5, v7, v3
; GFX1200-NEXT:    s_denorm_mode 12
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
; GFX1200-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v4
; GFX1200-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX1200-NEXT:    s_cbranch_vccnz .LBB28_6
; GFX1200-NEXT:  ; %bb.2: ; %frem.loop_body23.preheader
; GFX1200-NEXT:    s_sub_co_i32 s5, s5, s6
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_add_co_i32 s5, s5, 12
; GFX1200-NEXT:  .LBB28_3: ; %frem.loop_body23
; GFX1200-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_mov_b32_e32 v5, v2
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_add_co_i32 s5, s5, -12
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_cmp_gt_i32 s5, 12
; GFX1200-NEXT:    v_mul_f32_e32 v2, v5, v3
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_rndne_f32_e32 v2, v2
; GFX1200-NEXT:    v_xor_b32_e32 v2, 0x80000000, v2
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v2, v2, v1, v5
; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1200-NEXT:    v_add_f32_e32 v4, v2, v1
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1200-NEXT:    v_ldexp_f32 v2, v2, 12
; GFX1200-NEXT:    s_cbranch_scc1 .LBB28_3
; GFX1200-NEXT:  ; %bb.4:
; GFX1200-NEXT:    v_mov_b32_e32 v4, s5
; GFX1200-NEXT:    s_branch .LBB28_7
; GFX1200-NEXT:  .LBB28_5: ; %frem.else16
; GFX1200-NEXT:    s_and_b32 s6, 0x80000000, s0
; GFX1200-NEXT:    s_cmp_eq_f32 s4, s5
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_cselect_b32 s0, s6, s0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    v_mov_b32_e32 v0, s0
; GFX1200-NEXT:    s_branch .LBB28_8
; GFX1200-NEXT:  .LBB28_6:
; GFX1200-NEXT:    v_mov_b32_e32 v5, v2
; GFX1200-NEXT:  .LBB28_7: ; %frem.loop_exit24
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_add_nc_u32_e32 v2, -11, v4
; GFX1200-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX1200-NEXT:    v_rndne_f32_e32 v3, v3
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
; GFX1200-NEXT:    v_fmac_f32_e32 v2, v3, v1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1200-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX1200-NEXT:    v_bfi_b32 v0, 0x7fffffff, v0, s0
; GFX1200-NEXT:  .LBB28_8:
; GFX1200-NEXT:    s_and_b32 s0, s1, 0x7fffffff
; GFX1200-NEXT:    s_and_b32 s5, s3, 0x7fffffff
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_cmp_gt_f32 s0, s5
; GFX1200-NEXT:    s_cbranch_scc0 .LBB28_13
; GFX1200-NEXT:  ; %bb.9: ; %frem.compute
; GFX1200-NEXT:    v_frexp_mant_f32_e64 v2, |s3|
; GFX1200-NEXT:    v_frexp_mant_f32_e64 v1, |s1|
; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v4, s1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT:    v_ldexp_f32 v2, v2, 1
; GFX1200-NEXT:    v_ldexp_f32 v3, v1, 12
; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v1, s3
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-NEXT:    v_readfirstlane_b32 s5, v4
; GFX1200-NEXT:    v_div_scale_f32 v6, null, v2, v2, 1.0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1200-NEXT:    v_readfirstlane_b32 s6, v1
; GFX1200-NEXT:    v_add_nc_u32_e32 v1, -1, v1
; GFX1200-NEXT:    v_rcp_f32_e32 v7, v6
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_not_b32_e32 v5, v1
; GFX1200-NEXT:    v_add_nc_u32_e32 v5, v5, v4
; GFX1200-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
; GFX1200-NEXT:    s_denorm_mode 15
; GFX1200-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
; GFX1200-NEXT:    v_fmac_f32_e32 v7, v8, v7
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_mul_f32_e32 v8, v4, v7
; GFX1200-NEXT:    v_fma_f32 v9, -v6, v8, v4
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fmac_f32_e32 v8, v9, v7
; GFX1200-NEXT:    v_fma_f32 v4, -v6, v8, v4
; GFX1200-NEXT:    s_denorm_mode 12
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
; GFX1200-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v5
; GFX1200-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; GFX1200-NEXT:    s_cbranch_vccnz .LBB28_14
; GFX1200-NEXT:  ; %bb.10: ; %frem.loop_body.preheader
; GFX1200-NEXT:    s_sub_co_i32 s5, s5, s6
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_add_co_i32 s5, s5, 12
; GFX1200-NEXT:  .LBB28_11: ; %frem.loop_body
; GFX1200-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_mov_b32_e32 v6, v3
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_add_co_i32 s5, s5, -12
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_cmp_gt_i32 s5, 12
; GFX1200-NEXT:    v_mul_f32_e32 v3, v6, v4
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_rndne_f32_e32 v3, v3
; GFX1200-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v3, v3, v2, v6
; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1200-NEXT:    v_add_f32_e32 v5, v3, v2
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1200-NEXT:    v_ldexp_f32 v3, v3, 12
; GFX1200-NEXT:    s_cbranch_scc1 .LBB28_11
; GFX1200-NEXT:  ; %bb.12:
; GFX1200-NEXT:    v_mov_b32_e32 v5, s5
; GFX1200-NEXT:    s_branch .LBB28_15
; GFX1200-NEXT:  .LBB28_13: ; %frem.else
; GFX1200-NEXT:    s_and_b32 s6, 0x80000000, s1
; GFX1200-NEXT:    s_cmp_eq_f32 s0, s5
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_cselect_b32 s1, s6, s1
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    v_mov_b32_e32 v1, s1
; GFX1200-NEXT:    s_branch .LBB28_16
; GFX1200-NEXT:  .LBB28_14:
; GFX1200-NEXT:    v_mov_b32_e32 v6, v3
; GFX1200-NEXT:  .LBB28_15: ; %frem.loop_exit
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_add_nc_u32_e32 v3, -11, v5
; GFX1200-NEXT:    v_ldexp_f32 v3, v6, v3
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_mul_f32_e32 v4, v3, v4
; GFX1200-NEXT:    v_rndne_f32_e32 v4, v4
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
; GFX1200-NEXT:    v_fmac_f32_e32 v3, v4, v2
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1200-NEXT:    v_add_f32_e32 v2, v3, v2
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_ldexp_f32 v1, v2, v1
; GFX1200-NEXT:    v_bfi_b32 v1, 0x7fffffff, v1, s1
; GFX1200-NEXT:  .LBB28_16:
; GFX1200-NEXT:    s_cmp_lg_f32 s2, 0
; GFX1200-NEXT:    s_cselect_b32 s1, -1, 0
; GFX1200-NEXT:    s_cmp_nge_f32 s4, 0x7f800000
; GFX1200-NEXT:    s_cselect_b32 s2, -1, 0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_and_b32 vcc_lo, s2, s1
; GFX1200-NEXT:    s_cmp_lg_f32 s3, 0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
; GFX1200-NEXT:    s_cselect_b32 s1, -1, 0
; GFX1200-NEXT:    s_cmp_nge_f32 s0, 0x7f800000
; GFX1200-NEXT:    s_cselect_b32 s0, -1, 0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_and_b32 vcc_lo, s0, s1
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v1, vcc_lo
; GFX1200-NEXT:    s_setpc_b64 s[30:31]
   %r2 = frem <2 x float> %in1, %in2
  ret <2 x float> %r2
}

define <4 x float> @frem_v4f32_uniform(<4 x float> inreg %in1, <4 x float> inreg %in2) #0 {
; SI-LABEL: frem_v4f32_uniform:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_mov_b32_e32 v0, s20
; SI-NEXT:    v_cmp_gt_f32_e64 vcc, |s16|, |v0|
; SI-NEXT:    s_cbranch_vccz .LBB29_4
; SI-NEXT:  ; %bb.1: ; %frem.compute77
; SI-NEXT:    v_mov_b32_e32 v0, 0x7f800000
; SI-NEXT:    v_cmp_lt_f32_e64 s[4:5], |s16|, v0
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v1, s16
; SI-NEXT:    s_and_b64 s[6:7], s[4:5], exec
; SI-NEXT:    v_readfirstlane_b32 s6, v1
; SI-NEXT:    v_frexp_mant_f32_e64 v1, |s16|
; SI-NEXT:    v_mov_b32_e32 v2, s16
; SI-NEXT:    v_cndmask_b32_e64 v1, |v2|, v1, s[4:5]
; SI-NEXT:    v_cmp_lt_f32_e64 s[4:5], |s20|, v0
; SI-NEXT:    v_frexp_mant_f32_e64 v0, |s20|
; SI-NEXT:    v_mov_b32_e32 v2, s20
; SI-NEXT:    v_cndmask_b32_e64 v0, |v2|, v0, s[4:5]
; SI-NEXT:    v_ldexp_f32_e64 v0, v0, 1
; SI-NEXT:    v_div_scale_f32 v3, s[8:9], v0, v0, 1.0
; SI-NEXT:    v_rcp_f32_e32 v4, v3
; SI-NEXT:    s_cselect_b32 s6, s6, 0
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v2, s20
; SI-NEXT:    s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT:    v_ldexp_f32_e64 v1, v1, 12
; SI-NEXT:    v_readfirstlane_b32 s4, v2
; SI-NEXT:    v_div_scale_f32 v2, vcc, 1.0, v0, 1.0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
; SI-NEXT:    v_fma_f32 v4, v5, v4, v4
; SI-NEXT:    v_mul_f32_e32 v5, v2, v4
; SI-NEXT:    s_cselect_b32 s7, s4, 0
; SI-NEXT:    v_fma_f32 v6, -v3, v5, v2
; SI-NEXT:    s_add_i32 s4, s7, -1
; SI-NEXT:    v_fma_f32 v5, v6, v4, v5
; SI-NEXT:    s_not_b32 s5, s4
; SI-NEXT:    v_fma_f32 v2, -v3, v5, v2
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    s_add_i32 s5, s5, s6
; SI-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
; SI-NEXT:    v_div_fixup_f32 v2, v2, v0, 1.0
; SI-NEXT:    s_cmp_lt_i32 s5, 13
; SI-NEXT:    s_cbranch_scc1 .LBB29_5
; SI-NEXT:  ; %bb.2: ; %frem.loop_body85.preheader
; SI-NEXT:    s_sub_i32 s5, s6, s7
; SI-NEXT:    s_add_i32 s5, s5, 12
; SI-NEXT:  .LBB29_3: ; %frem.loop_body85
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v3, v1
; SI-NEXT:    v_mul_f32_e32 v1, v3, v2
; SI-NEXT:    v_rndne_f32_e32 v1, v1
; SI-NEXT:    v_fma_f32 v1, -v1, v0, v3
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v1
; SI-NEXT:    v_add_f32_e32 v4, v1, v0
; SI-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
; SI-NEXT:    s_add_i32 s5, s5, -12
; SI-NEXT:    v_ldexp_f32_e64 v1, v1, 12
; SI-NEXT:    s_cmp_gt_i32 s5, 12
; SI-NEXT:    s_cbranch_scc1 .LBB29_3
; SI-NEXT:    s_branch .LBB29_6
; SI-NEXT:  .LBB29_4: ; %frem.else78
; SI-NEXT:    s_and_b32 s4, 0x80000000, s16
; SI-NEXT:    v_mov_b32_e32 v0, s20
; SI-NEXT:    v_cmp_eq_f32_e64 vcc, |s16|, |v0|
; SI-NEXT:    v_mov_b32_e32 v0, s16
; SI-NEXT:    v_mov_b32_e32 v1, s4
; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-NEXT:    s_branch .LBB29_7
; SI-NEXT:  .LBB29_5:
; SI-NEXT:    v_mov_b32_e32 v3, v1
; SI-NEXT:  .LBB29_6: ; %frem.loop_exit86
; SI-NEXT:    s_add_i32 s5, s5, -11
; SI-NEXT:    v_ldexp_f32_e64 v1, v3, s5
; SI-NEXT:    v_mul_f32_e32 v2, v1, v2
; SI-NEXT:    v_rndne_f32_e32 v2, v2
; SI-NEXT:    v_fma_f32 v1, -v2, v0, v1
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v1
; SI-NEXT:    v_add_f32_e32 v0, v1, v0
; SI-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; SI-NEXT:    v_ldexp_f32_e64 v0, v0, s4
; SI-NEXT:    s_brev_b32 s4, -2
; SI-NEXT:    v_mov_b32_e32 v1, s16
; SI-NEXT:    v_bfi_b32 v0, s4, v0, v1
; SI-NEXT:  .LBB29_7:
; SI-NEXT:    v_mov_b32_e32 v1, s21
; SI-NEXT:    v_cmp_gt_f32_e64 vcc, |s17|, |v1|
; SI-NEXT:    s_cbranch_vccz .LBB29_11
; SI-NEXT:  ; %bb.8: ; %frem.compute46
; SI-NEXT:    v_mov_b32_e32 v1, 0x7f800000
; SI-NEXT:    v_cmp_lt_f32_e64 s[4:5], |s17|, v1
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v2, s17
; SI-NEXT:    s_and_b64 s[6:7], s[4:5], exec
; SI-NEXT:    v_readfirstlane_b32 s6, v2
; SI-NEXT:    v_frexp_mant_f32_e64 v2, |s17|
; SI-NEXT:    v_mov_b32_e32 v3, s17
; SI-NEXT:    v_cndmask_b32_e64 v2, |v3|, v2, s[4:5]
; SI-NEXT:    v_cmp_lt_f32_e64 s[4:5], |s21|, v1
; SI-NEXT:    v_frexp_mant_f32_e64 v1, |s21|
; SI-NEXT:    v_mov_b32_e32 v3, s21
; SI-NEXT:    v_cndmask_b32_e64 v1, |v3|, v1, s[4:5]
; SI-NEXT:    v_ldexp_f32_e64 v1, v1, 1
; SI-NEXT:    v_div_scale_f32 v4, s[8:9], v1, v1, 1.0
; SI-NEXT:    v_rcp_f32_e32 v5, v4
; SI-NEXT:    s_cselect_b32 s6, s6, 0
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v3, s21
; SI-NEXT:    s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT:    v_ldexp_f32_e64 v2, v2, 12
; SI-NEXT:    v_readfirstlane_b32 s4, v3
; SI-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v1, 1.0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    v_fma_f32 v6, -v4, v5, 1.0
; SI-NEXT:    v_fma_f32 v5, v6, v5, v5
; SI-NEXT:    v_mul_f32_e32 v6, v3, v5
; SI-NEXT:    s_cselect_b32 s7, s4, 0
; SI-NEXT:    v_fma_f32 v7, -v4, v6, v3
; SI-NEXT:    s_add_i32 s4, s7, -1
; SI-NEXT:    v_fma_f32 v6, v7, v5, v6
; SI-NEXT:    s_not_b32 s5, s4
; SI-NEXT:    v_fma_f32 v3, -v4, v6, v3
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    s_add_i32 s5, s5, s6
; SI-NEXT:    v_div_fmas_f32 v3, v3, v5, v6
; SI-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; SI-NEXT:    s_cmp_lt_i32 s5, 13
; SI-NEXT:    s_cbranch_scc1 .LBB29_12
; SI-NEXT:  ; %bb.9: ; %frem.loop_body54.preheader
; SI-NEXT:    s_sub_i32 s5, s6, s7
; SI-NEXT:    s_add_i32 s5, s5, 12
; SI-NEXT:  .LBB29_10: ; %frem.loop_body54
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v4, v2
; SI-NEXT:    v_mul_f32_e32 v2, v4, v3
; SI-NEXT:    v_rndne_f32_e32 v2, v2
; SI-NEXT:    v_fma_f32 v2, -v2, v1, v4
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v2
; SI-NEXT:    v_add_f32_e32 v5, v2, v1
; SI-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
; SI-NEXT:    s_add_i32 s5, s5, -12
; SI-NEXT:    v_ldexp_f32_e64 v2, v2, 12
; SI-NEXT:    s_cmp_gt_i32 s5, 12
; SI-NEXT:    s_cbranch_scc1 .LBB29_10
; SI-NEXT:    s_branch .LBB29_13
; SI-NEXT:  .LBB29_11: ; %frem.else47
; SI-NEXT:    s_and_b32 s4, 0x80000000, s17
; SI-NEXT:    v_mov_b32_e32 v1, s21
; SI-NEXT:    v_cmp_eq_f32_e64 vcc, |s17|, |v1|
; SI-NEXT:    v_mov_b32_e32 v1, s17
; SI-NEXT:    v_mov_b32_e32 v2, s4
; SI-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
; SI-NEXT:    s_branch .LBB29_14
; SI-NEXT:  .LBB29_12:
; SI-NEXT:    v_mov_b32_e32 v4, v2
; SI-NEXT:  .LBB29_13: ; %frem.loop_exit55
; SI-NEXT:    s_add_i32 s5, s5, -11
; SI-NEXT:    v_ldexp_f32_e64 v2, v4, s5
; SI-NEXT:    v_mul_f32_e32 v3, v2, v3
; SI-NEXT:    v_rndne_f32_e32 v3, v3
; SI-NEXT:    v_fma_f32 v2, -v3, v1, v2
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v2
; SI-NEXT:    v_add_f32_e32 v1, v2, v1
; SI-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; SI-NEXT:    v_ldexp_f32_e64 v1, v1, s4
; SI-NEXT:    s_brev_b32 s4, -2
; SI-NEXT:    v_mov_b32_e32 v2, s17
; SI-NEXT:    v_bfi_b32 v1, s4, v1, v2
; SI-NEXT:  .LBB29_14:
; SI-NEXT:    v_mov_b32_e32 v2, s22
; SI-NEXT:    v_cmp_gt_f32_e64 vcc, |s18|, |v2|
; SI-NEXT:    s_cbranch_vccz .LBB29_18
; SI-NEXT:  ; %bb.15: ; %frem.compute15
; SI-NEXT:    v_mov_b32_e32 v2, 0x7f800000
; SI-NEXT:    v_cmp_lt_f32_e64 s[4:5], |s18|, v2
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v3, s18
; SI-NEXT:    s_and_b64 s[6:7], s[4:5], exec
; SI-NEXT:    v_readfirstlane_b32 s6, v3
; SI-NEXT:    v_frexp_mant_f32_e64 v3, |s18|
; SI-NEXT:    v_mov_b32_e32 v4, s18
; SI-NEXT:    v_cndmask_b32_e64 v3, |v4|, v3, s[4:5]
; SI-NEXT:    v_cmp_lt_f32_e64 s[4:5], |s22|, v2
; SI-NEXT:    v_frexp_mant_f32_e64 v2, |s22|
; SI-NEXT:    v_mov_b32_e32 v4, s22
; SI-NEXT:    v_cndmask_b32_e64 v2, |v4|, v2, s[4:5]
; SI-NEXT:    v_ldexp_f32_e64 v2, v2, 1
; SI-NEXT:    v_div_scale_f32 v5, s[8:9], v2, v2, 1.0
; SI-NEXT:    v_rcp_f32_e32 v6, v5
; SI-NEXT:    s_cselect_b32 s6, s6, 0
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v4, s22
; SI-NEXT:    s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT:    v_ldexp_f32_e64 v3, v3, 12
; SI-NEXT:    v_readfirstlane_b32 s4, v4
; SI-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v2, 1.0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
; SI-NEXT:    v_fma_f32 v6, v7, v6, v6
; SI-NEXT:    v_mul_f32_e32 v7, v4, v6
; SI-NEXT:    s_cselect_b32 s7, s4, 0
; SI-NEXT:    v_fma_f32 v8, -v5, v7, v4
; SI-NEXT:    s_add_i32 s4, s7, -1
; SI-NEXT:    v_fma_f32 v7, v8, v6, v7
; SI-NEXT:    s_not_b32 s5, s4
; SI-NEXT:    v_fma_f32 v4, -v5, v7, v4
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    s_add_i32 s5, s5, s6
; SI-NEXT:    v_div_fmas_f32 v4, v4, v6, v7
; SI-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; SI-NEXT:    s_cmp_lt_i32 s5, 13
; SI-NEXT:    s_cbranch_scc1 .LBB29_19
; SI-NEXT:  ; %bb.16: ; %frem.loop_body23.preheader
; SI-NEXT:    s_sub_i32 s5, s6, s7
; SI-NEXT:    s_add_i32 s5, s5, 12
; SI-NEXT:  .LBB29_17: ; %frem.loop_body23
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v5, v3
; SI-NEXT:    v_mul_f32_e32 v3, v5, v4
; SI-NEXT:    v_rndne_f32_e32 v3, v3
; SI-NEXT:    v_fma_f32 v3, -v3, v2, v5
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v3
; SI-NEXT:    v_add_f32_e32 v6, v3, v2
; SI-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc
; SI-NEXT:    s_add_i32 s5, s5, -12
; SI-NEXT:    v_ldexp_f32_e64 v3, v3, 12
; SI-NEXT:    s_cmp_gt_i32 s5, 12
; SI-NEXT:    s_cbranch_scc1 .LBB29_17
; SI-NEXT:    s_branch .LBB29_20
; SI-NEXT:  .LBB29_18: ; %frem.else16
; SI-NEXT:    s_and_b32 s4, 0x80000000, s18
; SI-NEXT:    v_mov_b32_e32 v2, s22
; SI-NEXT:    v_cmp_eq_f32_e64 vcc, |s18|, |v2|
; SI-NEXT:    v_mov_b32_e32 v2, s18
; SI-NEXT:    v_mov_b32_e32 v3, s4
; SI-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
; SI-NEXT:    s_branch .LBB29_21
; SI-NEXT:  .LBB29_19:
; SI-NEXT:    v_mov_b32_e32 v5, v3
; SI-NEXT:  .LBB29_20: ; %frem.loop_exit24
; SI-NEXT:    s_add_i32 s5, s5, -11
; SI-NEXT:    v_ldexp_f32_e64 v3, v5, s5
; SI-NEXT:    v_mul_f32_e32 v4, v3, v4
; SI-NEXT:    v_rndne_f32_e32 v4, v4
; SI-NEXT:    v_fma_f32 v3, -v4, v2, v3
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v3
; SI-NEXT:    v_add_f32_e32 v2, v3, v2
; SI-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; SI-NEXT:    v_ldexp_f32_e64 v2, v2, s4
; SI-NEXT:    s_brev_b32 s4, -2
; SI-NEXT:    v_mov_b32_e32 v3, s18
; SI-NEXT:    v_bfi_b32 v2, s4, v2, v3
; SI-NEXT:  .LBB29_21:
; SI-NEXT:    v_mov_b32_e32 v3, s23
; SI-NEXT:    v_cmp_gt_f32_e64 vcc, |s19|, |v3|
; SI-NEXT:    s_cbranch_vccz .LBB29_25
; SI-NEXT:  ; %bb.22: ; %frem.compute
; SI-NEXT:    v_mov_b32_e32 v3, 0x7f800000
; SI-NEXT:    v_cmp_lt_f32_e64 s[4:5], |s19|, v3
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v4, s19
; SI-NEXT:    s_and_b64 s[6:7], s[4:5], exec
; SI-NEXT:    v_readfirstlane_b32 s6, v4
; SI-NEXT:    v_frexp_mant_f32_e64 v4, |s19|
; SI-NEXT:    v_mov_b32_e32 v5, s19
; SI-NEXT:    v_cndmask_b32_e64 v4, |v5|, v4, s[4:5]
; SI-NEXT:    v_cmp_lt_f32_e64 s[4:5], |s23|, v3
; SI-NEXT:    v_frexp_mant_f32_e64 v3, |s23|
; SI-NEXT:    v_mov_b32_e32 v5, s23
; SI-NEXT:    v_cndmask_b32_e64 v3, |v5|, v3, s[4:5]
; SI-NEXT:    v_ldexp_f32_e64 v3, v3, 1
; SI-NEXT:    v_div_scale_f32 v6, s[8:9], v3, v3, 1.0
; SI-NEXT:    v_rcp_f32_e32 v7, v6
; SI-NEXT:    s_cselect_b32 s6, s6, 0
; SI-NEXT:    v_frexp_exp_i32_f32_e32 v5, s23
; SI-NEXT:    s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT:    v_ldexp_f32_e64 v4, v4, 12
; SI-NEXT:    v_readfirstlane_b32 s4, v5
; SI-NEXT:    v_div_scale_f32 v5, vcc, 1.0, v3, 1.0
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
; SI-NEXT:    v_fma_f32 v7, v8, v7, v7
; SI-NEXT:    v_mul_f32_e32 v8, v5, v7
; SI-NEXT:    s_cselect_b32 s7, s4, 0
; SI-NEXT:    v_fma_f32 v9, -v6, v8, v5
; SI-NEXT:    s_add_i32 s4, s7, -1
; SI-NEXT:    v_fma_f32 v8, v9, v7, v8
; SI-NEXT:    s_not_b32 s5, s4
; SI-NEXT:    v_fma_f32 v5, -v6, v8, v5
; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT:    s_add_i32 s5, s5, s6
; SI-NEXT:    v_div_fmas_f32 v5, v5, v7, v8
; SI-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
; SI-NEXT:    s_cmp_lt_i32 s5, 13
; SI-NEXT:    s_cbranch_scc1 .LBB29_26
; SI-NEXT:  ; %bb.23: ; %frem.loop_body.preheader
; SI-NEXT:    s_sub_i32 s5, s6, s7
; SI-NEXT:    s_add_i32 s5, s5, 12
; SI-NEXT:  .LBB29_24: ; %frem.loop_body
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v6, v4
; SI-NEXT:    v_mul_f32_e32 v4, v6, v5
; SI-NEXT:    v_rndne_f32_e32 v4, v4
; SI-NEXT:    v_fma_f32 v4, -v4, v3, v6
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; SI-NEXT:    v_add_f32_e32 v7, v4, v3
; SI-NEXT:    v_cndmask_b32_e32 v4, v4, v7, vcc
; SI-NEXT:    s_add_i32 s5, s5, -12
; SI-NEXT:    v_ldexp_f32_e64 v4, v4, 12
; SI-NEXT:    s_cmp_gt_i32 s5, 12
; SI-NEXT:    s_cbranch_scc1 .LBB29_24
; SI-NEXT:    s_branch .LBB29_27
; SI-NEXT:  .LBB29_25: ; %frem.else
; SI-NEXT:    s_and_b32 s4, 0x80000000, s19
; SI-NEXT:    v_mov_b32_e32 v3, s23
; SI-NEXT:    v_cmp_eq_f32_e64 vcc, |s19|, |v3|
; SI-NEXT:    v_mov_b32_e32 v3, s19
; SI-NEXT:    v_mov_b32_e32 v4, s4
; SI-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
; SI-NEXT:    s_branch .LBB29_28
; SI-NEXT:  .LBB29_26:
; SI-NEXT:    v_mov_b32_e32 v6, v4
; SI-NEXT:  .LBB29_27: ; %frem.loop_exit
; SI-NEXT:    s_add_i32 s5, s5, -11
; SI-NEXT:    v_ldexp_f32_e64 v4, v6, s5
; SI-NEXT:    v_mul_f32_e32 v5, v4, v5
; SI-NEXT:    v_rndne_f32_e32 v5, v5
; SI-NEXT:    v_fma_f32 v4, -v5, v3, v4
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; SI-NEXT:    v_add_f32_e32 v3, v4, v3
; SI-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; SI-NEXT:    v_ldexp_f32_e64 v3, v3, s4
; SI-NEXT:    s_brev_b32 s4, -2
; SI-NEXT:    v_mov_b32_e32 v4, s19
; SI-NEXT:    v_bfi_b32 v3, s4, v3, v4
; SI-NEXT:  .LBB29_28:
; SI-NEXT:    v_mov_b32_e32 v4, 0x7f800000
; SI-NEXT:    v_cmp_lg_f32_e64 s[4:5], s20, 0
; SI-NEXT:    v_cmp_nge_f32_e64 s[6:7], |s16|, v4
; SI-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; SI-NEXT:    v_mov_b32_e32 v5, 0x7fc00000
; SI-NEXT:    v_cmp_lg_f32_e64 s[4:5], s21, 0
; SI-NEXT:    v_cmp_nge_f32_e64 s[6:7], |s17|, v4
; SI-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc
; SI-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; SI-NEXT:    v_cmp_lg_f32_e64 s[4:5], s22, 0
; SI-NEXT:    v_cmp_nge_f32_e64 s[6:7], |s18|, v4
; SI-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
; SI-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; SI-NEXT:    v_cmp_lg_f32_e64 s[4:5], s23, 0
; SI-NEXT:    v_cmp_nge_f32_e64 s[6:7], |s19|, v4
; SI-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
; SI-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; SI-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; CI-LABEL: frem_v4f32_uniform:
; CI:       ; %bb.0:
; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-NEXT:    v_mov_b32_e32 v0, s20
; CI-NEXT:    v_cmp_gt_f32_e64 vcc, |s16|, |v0|
; CI-NEXT:    s_cbranch_vccz .LBB29_4
; CI-NEXT:  ; %bb.1: ; %frem.compute77
; CI-NEXT:    v_frexp_mant_f32_e64 v1, |s20|
; CI-NEXT:    v_ldexp_f32_e64 v1, v1, 1
; CI-NEXT:    v_div_scale_f32 v7, s[4:5], v1, v1, 1.0
; CI-NEXT:    v_frexp_mant_f32_e64 v0, |s16|
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v6, s20
; CI-NEXT:    v_ldexp_f32_e64 v4, v0, 12
; CI-NEXT:    v_add_i32_e32 v0, vcc, -1, v6
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v5, s16
; CI-NEXT:    v_not_b32_e32 v2, v0
; CI-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
; CI-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v1, 1.0
; CI-NEXT:    v_rcp_f32_e32 v8, v7
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
; CI-NEXT:    v_fma_f32 v8, v9, v8, v8
; CI-NEXT:    v_mul_f32_e32 v9, v3, v8
; CI-NEXT:    v_fma_f32 v10, -v7, v9, v3
; CI-NEXT:    v_fma_f32 v9, v10, v8, v9
; CI-NEXT:    v_fma_f32 v3, -v7, v9, v3
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v3, v3, v8, v9
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v2
; CI-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; CI-NEXT:    s_cbranch_vccnz .LBB29_5
; CI-NEXT:  ; %bb.2: ; %frem.loop_body85.preheader
; CI-NEXT:    v_sub_i32_e32 v2, vcc, v5, v6
; CI-NEXT:    v_add_i32_e32 v2, vcc, 12, v2
; CI-NEXT:  .LBB29_3: ; %frem.loop_body85
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v5, v4
; CI-NEXT:    v_mul_f32_e32 v4, v5, v3
; CI-NEXT:    v_rndne_f32_e32 v4, v4
; CI-NEXT:    v_fma_f32 v4, -v4, v1, v5
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; CI-NEXT:    v_add_f32_e32 v6, v4, v1
; CI-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
; CI-NEXT:    v_add_i32_e32 v2, vcc, -12, v2
; CI-NEXT:    v_ldexp_f32_e64 v4, v4, 12
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v2
; CI-NEXT:    s_cbranch_vccnz .LBB29_3
; CI-NEXT:    s_branch .LBB29_6
; CI-NEXT:  .LBB29_4: ; %frem.else78
; CI-NEXT:    s_and_b32 s4, 0x80000000, s16
; CI-NEXT:    v_mov_b32_e32 v0, s20
; CI-NEXT:    v_cmp_eq_f32_e64 vcc, |s16|, |v0|
; CI-NEXT:    v_mov_b32_e32 v0, s16
; CI-NEXT:    v_mov_b32_e32 v1, s4
; CI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
; CI-NEXT:    s_branch .LBB29_7
; CI-NEXT:  .LBB29_5:
; CI-NEXT:    v_mov_b32_e32 v5, v4
; CI-NEXT:  .LBB29_6: ; %frem.loop_exit86
; CI-NEXT:    v_add_i32_e32 v2, vcc, -11, v2
; CI-NEXT:    v_ldexp_f32_e32 v2, v5, v2
; CI-NEXT:    v_mul_f32_e32 v3, v2, v3
; CI-NEXT:    v_rndne_f32_e32 v3, v3
; CI-NEXT:    v_fma_f32 v2, -v3, v1, v2
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v2
; CI-NEXT:    v_add_f32_e32 v1, v2, v1
; CI-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; CI-NEXT:    v_ldexp_f32_e32 v0, v1, v0
; CI-NEXT:    s_brev_b32 s4, -2
; CI-NEXT:    v_mov_b32_e32 v1, s16
; CI-NEXT:    v_bfi_b32 v0, s4, v0, v1
; CI-NEXT:  .LBB29_7:
; CI-NEXT:    v_mov_b32_e32 v1, s21
; CI-NEXT:    v_cmp_gt_f32_e64 vcc, |s17|, |v1|
; CI-NEXT:    s_cbranch_vccz .LBB29_11
; CI-NEXT:  ; %bb.8: ; %frem.compute46
; CI-NEXT:    v_frexp_mant_f32_e64 v2, |s21|
; CI-NEXT:    v_ldexp_f32_e64 v2, v2, 1
; CI-NEXT:    v_div_scale_f32 v8, s[4:5], v2, v2, 1.0
; CI-NEXT:    v_frexp_mant_f32_e64 v1, |s17|
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v7, s21
; CI-NEXT:    v_ldexp_f32_e64 v5, v1, 12
; CI-NEXT:    v_add_i32_e32 v1, vcc, -1, v7
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v6, s17
; CI-NEXT:    v_not_b32_e32 v3, v1
; CI-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
; CI-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v2, 1.0
; CI-NEXT:    v_rcp_f32_e32 v9, v8
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
; CI-NEXT:    v_fma_f32 v9, v10, v9, v9
; CI-NEXT:    v_mul_f32_e32 v10, v4, v9
; CI-NEXT:    v_fma_f32 v11, -v8, v10, v4
; CI-NEXT:    v_fma_f32 v10, v11, v9, v10
; CI-NEXT:    v_fma_f32 v4, -v8, v10, v4
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v4, v4, v9, v10
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v3
; CI-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; CI-NEXT:    s_cbranch_vccnz .LBB29_12
; CI-NEXT:  ; %bb.9: ; %frem.loop_body54.preheader
; CI-NEXT:    v_sub_i32_e32 v3, vcc, v6, v7
; CI-NEXT:    v_add_i32_e32 v3, vcc, 12, v3
; CI-NEXT:  .LBB29_10: ; %frem.loop_body54
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v6, v5
; CI-NEXT:    v_mul_f32_e32 v5, v6, v4
; CI-NEXT:    v_rndne_f32_e32 v5, v5
; CI-NEXT:    v_fma_f32 v5, -v5, v2, v6
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
; CI-NEXT:    v_add_f32_e32 v7, v5, v2
; CI-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
; CI-NEXT:    v_add_i32_e32 v3, vcc, -12, v3
; CI-NEXT:    v_ldexp_f32_e64 v5, v5, 12
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v3
; CI-NEXT:    s_cbranch_vccnz .LBB29_10
; CI-NEXT:    s_branch .LBB29_13
; CI-NEXT:  .LBB29_11: ; %frem.else47
; CI-NEXT:    s_and_b32 s4, 0x80000000, s17
; CI-NEXT:    v_mov_b32_e32 v1, s21
; CI-NEXT:    v_cmp_eq_f32_e64 vcc, |s17|, |v1|
; CI-NEXT:    v_mov_b32_e32 v1, s17
; CI-NEXT:    v_mov_b32_e32 v2, s4
; CI-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
; CI-NEXT:    s_branch .LBB29_14
; CI-NEXT:  .LBB29_12:
; CI-NEXT:    v_mov_b32_e32 v6, v5
; CI-NEXT:  .LBB29_13: ; %frem.loop_exit55
; CI-NEXT:    v_add_i32_e32 v3, vcc, -11, v3
; CI-NEXT:    v_ldexp_f32_e32 v3, v6, v3
; CI-NEXT:    v_mul_f32_e32 v4, v3, v4
; CI-NEXT:    v_rndne_f32_e32 v4, v4
; CI-NEXT:    v_fma_f32 v3, -v4, v2, v3
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v3
; CI-NEXT:    v_add_f32_e32 v2, v3, v2
; CI-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; CI-NEXT:    v_ldexp_f32_e32 v1, v2, v1
; CI-NEXT:    s_brev_b32 s4, -2
; CI-NEXT:    v_mov_b32_e32 v2, s17
; CI-NEXT:    v_bfi_b32 v1, s4, v1, v2
; CI-NEXT:  .LBB29_14:
; CI-NEXT:    v_mov_b32_e32 v2, s22
; CI-NEXT:    v_cmp_gt_f32_e64 vcc, |s18|, |v2|
; CI-NEXT:    s_cbranch_vccz .LBB29_18
; CI-NEXT:  ; %bb.15: ; %frem.compute15
; CI-NEXT:    v_frexp_mant_f32_e64 v3, |s22|
; CI-NEXT:    v_ldexp_f32_e64 v3, v3, 1
; CI-NEXT:    v_div_scale_f32 v9, s[4:5], v3, v3, 1.0
; CI-NEXT:    v_frexp_mant_f32_e64 v2, |s18|
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v8, s22
; CI-NEXT:    v_ldexp_f32_e64 v6, v2, 12
; CI-NEXT:    v_add_i32_e32 v2, vcc, -1, v8
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v7, s18
; CI-NEXT:    v_not_b32_e32 v4, v2
; CI-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
; CI-NEXT:    v_div_scale_f32 v5, vcc, 1.0, v3, 1.0
; CI-NEXT:    v_rcp_f32_e32 v10, v9
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; CI-NEXT:    v_fma_f32 v10, v11, v10, v10
; CI-NEXT:    v_mul_f32_e32 v11, v5, v10
; CI-NEXT:    v_fma_f32 v12, -v9, v11, v5
; CI-NEXT:    v_fma_f32 v11, v12, v10, v11
; CI-NEXT:    v_fma_f32 v5, -v9, v11, v5
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v5, v5, v10, v11
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v4
; CI-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
; CI-NEXT:    s_cbranch_vccnz .LBB29_19
; CI-NEXT:  ; %bb.16: ; %frem.loop_body23.preheader
; CI-NEXT:    v_sub_i32_e32 v4, vcc, v7, v8
; CI-NEXT:    v_add_i32_e32 v4, vcc, 12, v4
; CI-NEXT:  .LBB29_17: ; %frem.loop_body23
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v7, v6
; CI-NEXT:    v_mul_f32_e32 v6, v7, v5
; CI-NEXT:    v_rndne_f32_e32 v6, v6
; CI-NEXT:    v_fma_f32 v6, -v6, v3, v7
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v6
; CI-NEXT:    v_add_f32_e32 v8, v6, v3
; CI-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc
; CI-NEXT:    v_add_i32_e32 v4, vcc, -12, v4
; CI-NEXT:    v_ldexp_f32_e64 v6, v6, 12
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v4
; CI-NEXT:    s_cbranch_vccnz .LBB29_17
; CI-NEXT:    s_branch .LBB29_20
; CI-NEXT:  .LBB29_18: ; %frem.else16
; CI-NEXT:    s_and_b32 s4, 0x80000000, s18
; CI-NEXT:    v_mov_b32_e32 v2, s22
; CI-NEXT:    v_cmp_eq_f32_e64 vcc, |s18|, |v2|
; CI-NEXT:    v_mov_b32_e32 v2, s18
; CI-NEXT:    v_mov_b32_e32 v3, s4
; CI-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
; CI-NEXT:    s_branch .LBB29_21
; CI-NEXT:  .LBB29_19:
; CI-NEXT:    v_mov_b32_e32 v7, v6
; CI-NEXT:  .LBB29_20: ; %frem.loop_exit24
; CI-NEXT:    v_add_i32_e32 v4, vcc, -11, v4
; CI-NEXT:    v_ldexp_f32_e32 v4, v7, v4
; CI-NEXT:    v_mul_f32_e32 v5, v4, v5
; CI-NEXT:    v_rndne_f32_e32 v5, v5
; CI-NEXT:    v_fma_f32 v4, -v5, v3, v4
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; CI-NEXT:    v_add_f32_e32 v3, v4, v3
; CI-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; CI-NEXT:    v_ldexp_f32_e32 v2, v3, v2
; CI-NEXT:    s_brev_b32 s4, -2
; CI-NEXT:    v_mov_b32_e32 v3, s18
; CI-NEXT:    v_bfi_b32 v2, s4, v2, v3
; CI-NEXT:  .LBB29_21:
; CI-NEXT:    v_mov_b32_e32 v3, s23
; CI-NEXT:    v_cmp_gt_f32_e64 vcc, |s19|, |v3|
; CI-NEXT:    s_cbranch_vccz .LBB29_25
; CI-NEXT:  ; %bb.22: ; %frem.compute
; CI-NEXT:    v_frexp_mant_f32_e64 v4, |s23|
; CI-NEXT:    v_ldexp_f32_e64 v4, v4, 1
; CI-NEXT:    v_div_scale_f32 v10, s[4:5], v4, v4, 1.0
; CI-NEXT:    v_frexp_mant_f32_e64 v3, |s19|
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v9, s23
; CI-NEXT:    v_ldexp_f32_e64 v7, v3, 12
; CI-NEXT:    v_add_i32_e32 v3, vcc, -1, v9
; CI-NEXT:    v_frexp_exp_i32_f32_e32 v8, s19
; CI-NEXT:    v_not_b32_e32 v5, v3
; CI-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
; CI-NEXT:    v_div_scale_f32 v6, vcc, 1.0, v4, 1.0
; CI-NEXT:    v_rcp_f32_e32 v11, v10
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT:    v_fma_f32 v12, -v10, v11, 1.0
; CI-NEXT:    v_fma_f32 v11, v12, v11, v11
; CI-NEXT:    v_mul_f32_e32 v12, v6, v11
; CI-NEXT:    v_fma_f32 v13, -v10, v12, v6
; CI-NEXT:    v_fma_f32 v12, v13, v11, v12
; CI-NEXT:    v_fma_f32 v6, -v10, v12, v6
; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; CI-NEXT:    v_div_fmas_f32 v6, v6, v11, v12
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v5
; CI-NEXT:    v_div_fixup_f32 v6, v6, v4, 1.0
; CI-NEXT:    s_cbranch_vccnz .LBB29_26
; CI-NEXT:  ; %bb.23: ; %frem.loop_body.preheader
; CI-NEXT:    v_sub_i32_e32 v5, vcc, v8, v9
; CI-NEXT:    v_add_i32_e32 v5, vcc, 12, v5
; CI-NEXT:  .LBB29_24: ; %frem.loop_body
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v8, v7
; CI-NEXT:    v_mul_f32_e32 v7, v8, v6
; CI-NEXT:    v_rndne_f32_e32 v7, v7
; CI-NEXT:    v_fma_f32 v7, -v7, v4, v8
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v7
; CI-NEXT:    v_add_f32_e32 v9, v7, v4
; CI-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc
; CI-NEXT:    v_add_i32_e32 v5, vcc, -12, v5
; CI-NEXT:    v_ldexp_f32_e64 v7, v7, 12
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v5
; CI-NEXT:    s_cbranch_vccnz .LBB29_24
; CI-NEXT:    s_branch .LBB29_27
; CI-NEXT:  .LBB29_25: ; %frem.else
; CI-NEXT:    s_and_b32 s4, 0x80000000, s19
; CI-NEXT:    v_mov_b32_e32 v3, s23
; CI-NEXT:    v_cmp_eq_f32_e64 vcc, |s19|, |v3|
; CI-NEXT:    v_mov_b32_e32 v3, s19
; CI-NEXT:    v_mov_b32_e32 v4, s4
; CI-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
; CI-NEXT:    s_branch .LBB29_28
; CI-NEXT:  .LBB29_26:
; CI-NEXT:    v_mov_b32_e32 v8, v7
; CI-NEXT:  .LBB29_27: ; %frem.loop_exit
; CI-NEXT:    v_add_i32_e32 v5, vcc, -11, v5
; CI-NEXT:    v_ldexp_f32_e32 v5, v8, v5
; CI-NEXT:    v_mul_f32_e32 v6, v5, v6
; CI-NEXT:    v_rndne_f32_e32 v6, v6
; CI-NEXT:    v_fma_f32 v5, -v6, v4, v5
; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
; CI-NEXT:    v_add_f32_e32 v4, v5, v4
; CI-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc
; CI-NEXT:    v_ldexp_f32_e32 v3, v4, v3
; CI-NEXT:    s_brev_b32 s4, -2
; CI-NEXT:    v_mov_b32_e32 v4, s19
; CI-NEXT:    v_bfi_b32 v3, s4, v3, v4
; CI-NEXT:  .LBB29_28:
; CI-NEXT:    v_mov_b32_e32 v4, 0x7f800000
; CI-NEXT:    v_cmp_lg_f32_e64 s[4:5], s20, 0
; CI-NEXT:    v_cmp_nge_f32_e64 s[6:7], |s16|, v4
; CI-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; CI-NEXT:    v_mov_b32_e32 v5, 0x7fc00000
; CI-NEXT:    v_cmp_lg_f32_e64 s[4:5], s21, 0
; CI-NEXT:    v_cmp_nge_f32_e64 s[6:7], |s17|, v4
; CI-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc
; CI-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; CI-NEXT:    v_cmp_lg_f32_e64 s[4:5], s22, 0
; CI-NEXT:    v_cmp_nge_f32_e64 s[6:7], |s18|, v4
; CI-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
; CI-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; CI-NEXT:    v_cmp_lg_f32_e64 s[4:5], s23, 0
; CI-NEXT:    v_cmp_nge_f32_e64 s[6:7], |s19|, v4
; CI-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
; CI-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; CI-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
; CI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: frem_v4f32_uniform:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_mov_b32_e32 v0, s20
; VI-NEXT:    v_cmp_gt_f32_e64 vcc, |s16|, |v0|
; VI-NEXT:    s_cbranch_vccz .LBB29_4
; VI-NEXT:  ; %bb.1: ; %frem.compute77
; VI-NEXT:    v_frexp_mant_f32_e64 v1, |s20|
; VI-NEXT:    v_ldexp_f32 v1, v1, 1
; VI-NEXT:    v_div_scale_f32 v7, s[4:5], v1, v1, 1.0
; VI-NEXT:    v_frexp_mant_f32_e64 v0, |s16|
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v6, s20
; VI-NEXT:    v_ldexp_f32 v4, v0, 12
; VI-NEXT:    v_add_u32_e32 v0, vcc, -1, v6
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v5, s16
; VI-NEXT:    v_not_b32_e32 v2, v0
; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v5
; VI-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v1, 1.0
; VI-NEXT:    v_rcp_f32_e32 v8, v7
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
; VI-NEXT:    v_fma_f32 v8, v9, v8, v8
; VI-NEXT:    v_mul_f32_e32 v9, v3, v8
; VI-NEXT:    v_fma_f32 v10, -v7, v9, v3
; VI-NEXT:    v_fma_f32 v9, v10, v8, v9
; VI-NEXT:    v_fma_f32 v3, -v7, v9, v3
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; VI-NEXT:    v_div_fmas_f32 v3, v3, v8, v9
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v2
; VI-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; VI-NEXT:    s_cbranch_vccnz .LBB29_5
; VI-NEXT:  ; %bb.2: ; %frem.loop_body85.preheader
; VI-NEXT:    v_sub_u32_e32 v2, vcc, v5, v6
; VI-NEXT:    v_add_u32_e32 v2, vcc, 12, v2
; VI-NEXT:  .LBB29_3: ; %frem.loop_body85
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v5, v4
; VI-NEXT:    v_mul_f32_e32 v4, v5, v3
; VI-NEXT:    v_rndne_f32_e32 v4, v4
; VI-NEXT:    v_fma_f32 v4, -v4, v1, v5
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; VI-NEXT:    v_add_f32_e32 v6, v4, v1
; VI-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
; VI-NEXT:    v_add_u32_e32 v2, vcc, -12, v2
; VI-NEXT:    v_ldexp_f32 v4, v4, 12
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v2
; VI-NEXT:    s_cbranch_vccnz .LBB29_3
; VI-NEXT:    s_branch .LBB29_6
; VI-NEXT:  .LBB29_4: ; %frem.else78
; VI-NEXT:    s_and_b32 s4, 0x80000000, s16
; VI-NEXT:    v_mov_b32_e32 v0, s20
; VI-NEXT:    v_cmp_eq_f32_e64 vcc, |s16|, |v0|
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
; VI-NEXT:    s_branch .LBB29_7
; VI-NEXT:  .LBB29_5:
; VI-NEXT:    v_mov_b32_e32 v5, v4
; VI-NEXT:  .LBB29_6: ; %frem.loop_exit86
; VI-NEXT:    v_add_u32_e32 v2, vcc, -11, v2
; VI-NEXT:    v_ldexp_f32 v2, v5, v2
; VI-NEXT:    v_mul_f32_e32 v3, v2, v3
; VI-NEXT:    v_rndne_f32_e32 v3, v3
; VI-NEXT:    v_fma_f32 v2, -v3, v1, v2
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v2
; VI-NEXT:    v_add_f32_e32 v1, v2, v1
; VI-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; VI-NEXT:    v_ldexp_f32 v0, v1, v0
; VI-NEXT:    s_brev_b32 s4, -2
; VI-NEXT:    v_mov_b32_e32 v1, s16
; VI-NEXT:    v_bfi_b32 v0, s4, v0, v1
; VI-NEXT:  .LBB29_7:
; VI-NEXT:    v_mov_b32_e32 v1, s21
; VI-NEXT:    v_cmp_gt_f32_e64 vcc, |s17|, |v1|
; VI-NEXT:    s_cbranch_vccz .LBB29_11
; VI-NEXT:  ; %bb.8: ; %frem.compute46
; VI-NEXT:    v_frexp_mant_f32_e64 v2, |s21|
; VI-NEXT:    v_ldexp_f32 v2, v2, 1
; VI-NEXT:    v_div_scale_f32 v8, s[4:5], v2, v2, 1.0
; VI-NEXT:    v_frexp_mant_f32_e64 v1, |s17|
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v7, s21
; VI-NEXT:    v_ldexp_f32 v5, v1, 12
; VI-NEXT:    v_add_u32_e32 v1, vcc, -1, v7
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v6, s17
; VI-NEXT:    v_not_b32_e32 v3, v1
; VI-NEXT:    v_add_u32_e32 v3, vcc, v3, v6
; VI-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v2, 1.0
; VI-NEXT:    v_rcp_f32_e32 v9, v8
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
; VI-NEXT:    v_fma_f32 v9, v10, v9, v9
; VI-NEXT:    v_mul_f32_e32 v10, v4, v9
; VI-NEXT:    v_fma_f32 v11, -v8, v10, v4
; VI-NEXT:    v_fma_f32 v10, v11, v9, v10
; VI-NEXT:    v_fma_f32 v4, -v8, v10, v4
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; VI-NEXT:    v_div_fmas_f32 v4, v4, v9, v10
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v3
; VI-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; VI-NEXT:    s_cbranch_vccnz .LBB29_12
; VI-NEXT:  ; %bb.9: ; %frem.loop_body54.preheader
; VI-NEXT:    v_sub_u32_e32 v3, vcc, v6, v7
; VI-NEXT:    v_add_u32_e32 v3, vcc, 12, v3
; VI-NEXT:  .LBB29_10: ; %frem.loop_body54
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v6, v5
; VI-NEXT:    v_mul_f32_e32 v5, v6, v4
; VI-NEXT:    v_rndne_f32_e32 v5, v5
; VI-NEXT:    v_fma_f32 v5, -v5, v2, v6
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
; VI-NEXT:    v_add_f32_e32 v7, v5, v2
; VI-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
; VI-NEXT:    v_add_u32_e32 v3, vcc, -12, v3
; VI-NEXT:    v_ldexp_f32 v5, v5, 12
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v3
; VI-NEXT:    s_cbranch_vccnz .LBB29_10
; VI-NEXT:    s_branch .LBB29_13
; VI-NEXT:  .LBB29_11: ; %frem.else47
; VI-NEXT:    s_and_b32 s4, 0x80000000, s17
; VI-NEXT:    v_mov_b32_e32 v1, s21
; VI-NEXT:    v_cmp_eq_f32_e64 vcc, |s17|, |v1|
; VI-NEXT:    v_mov_b32_e32 v1, s17
; VI-NEXT:    v_mov_b32_e32 v2, s4
; VI-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
; VI-NEXT:    s_branch .LBB29_14
; VI-NEXT:  .LBB29_12:
; VI-NEXT:    v_mov_b32_e32 v6, v5
; VI-NEXT:  .LBB29_13: ; %frem.loop_exit55
; VI-NEXT:    v_add_u32_e32 v3, vcc, -11, v3
; VI-NEXT:    v_ldexp_f32 v3, v6, v3
; VI-NEXT:    v_mul_f32_e32 v4, v3, v4
; VI-NEXT:    v_rndne_f32_e32 v4, v4
; VI-NEXT:    v_fma_f32 v3, -v4, v2, v3
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v3
; VI-NEXT:    v_add_f32_e32 v2, v3, v2
; VI-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; VI-NEXT:    v_ldexp_f32 v1, v2, v1
; VI-NEXT:    s_brev_b32 s4, -2
; VI-NEXT:    v_mov_b32_e32 v2, s17
; VI-NEXT:    v_bfi_b32 v1, s4, v1, v2
; VI-NEXT:  .LBB29_14:
; VI-NEXT:    v_mov_b32_e32 v2, s22
; VI-NEXT:    v_cmp_gt_f32_e64 vcc, |s18|, |v2|
; VI-NEXT:    s_cbranch_vccz .LBB29_18
; VI-NEXT:  ; %bb.15: ; %frem.compute15
; VI-NEXT:    v_frexp_mant_f32_e64 v3, |s22|
; VI-NEXT:    v_ldexp_f32 v3, v3, 1
; VI-NEXT:    v_div_scale_f32 v9, s[4:5], v3, v3, 1.0
; VI-NEXT:    v_frexp_mant_f32_e64 v2, |s18|
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v8, s22
; VI-NEXT:    v_ldexp_f32 v6, v2, 12
; VI-NEXT:    v_add_u32_e32 v2, vcc, -1, v8
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v7, s18
; VI-NEXT:    v_not_b32_e32 v4, v2
; VI-NEXT:    v_add_u32_e32 v4, vcc, v4, v7
; VI-NEXT:    v_div_scale_f32 v5, vcc, 1.0, v3, 1.0
; VI-NEXT:    v_rcp_f32_e32 v10, v9
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; VI-NEXT:    v_fma_f32 v10, v11, v10, v10
; VI-NEXT:    v_mul_f32_e32 v11, v5, v10
; VI-NEXT:    v_fma_f32 v12, -v9, v11, v5
; VI-NEXT:    v_fma_f32 v11, v12, v10, v11
; VI-NEXT:    v_fma_f32 v5, -v9, v11, v5
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; VI-NEXT:    v_div_fmas_f32 v5, v5, v10, v11
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v4
; VI-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
; VI-NEXT:    s_cbranch_vccnz .LBB29_19
; VI-NEXT:  ; %bb.16: ; %frem.loop_body23.preheader
; VI-NEXT:    v_sub_u32_e32 v4, vcc, v7, v8
; VI-NEXT:    v_add_u32_e32 v4, vcc, 12, v4
; VI-NEXT:  .LBB29_17: ; %frem.loop_body23
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v7, v6
; VI-NEXT:    v_mul_f32_e32 v6, v7, v5
; VI-NEXT:    v_rndne_f32_e32 v6, v6
; VI-NEXT:    v_fma_f32 v6, -v6, v3, v7
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v6
; VI-NEXT:    v_add_f32_e32 v8, v6, v3
; VI-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc
; VI-NEXT:    v_add_u32_e32 v4, vcc, -12, v4
; VI-NEXT:    v_ldexp_f32 v6, v6, 12
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v4
; VI-NEXT:    s_cbranch_vccnz .LBB29_17
; VI-NEXT:    s_branch .LBB29_20
; VI-NEXT:  .LBB29_18: ; %frem.else16
; VI-NEXT:    s_and_b32 s4, 0x80000000, s18
; VI-NEXT:    v_mov_b32_e32 v2, s22
; VI-NEXT:    v_cmp_eq_f32_e64 vcc, |s18|, |v2|
; VI-NEXT:    v_mov_b32_e32 v2, s18
; VI-NEXT:    v_mov_b32_e32 v3, s4
; VI-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
; VI-NEXT:    s_branch .LBB29_21
; VI-NEXT:  .LBB29_19:
; VI-NEXT:    v_mov_b32_e32 v7, v6
; VI-NEXT:  .LBB29_20: ; %frem.loop_exit24
; VI-NEXT:    v_add_u32_e32 v4, vcc, -11, v4
; VI-NEXT:    v_ldexp_f32 v4, v7, v4
; VI-NEXT:    v_mul_f32_e32 v5, v4, v5
; VI-NEXT:    v_rndne_f32_e32 v5, v5
; VI-NEXT:    v_fma_f32 v4, -v5, v3, v4
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; VI-NEXT:    v_add_f32_e32 v3, v4, v3
; VI-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; VI-NEXT:    v_ldexp_f32 v2, v3, v2
; VI-NEXT:    s_brev_b32 s4, -2
; VI-NEXT:    v_mov_b32_e32 v3, s18
; VI-NEXT:    v_bfi_b32 v2, s4, v2, v3
; VI-NEXT:  .LBB29_21:
; VI-NEXT:    v_mov_b32_e32 v3, s23
; VI-NEXT:    v_cmp_gt_f32_e64 vcc, |s19|, |v3|
; VI-NEXT:    s_cbranch_vccz .LBB29_25
; VI-NEXT:  ; %bb.22: ; %frem.compute
; VI-NEXT:    v_frexp_mant_f32_e64 v4, |s23|
; VI-NEXT:    v_ldexp_f32 v4, v4, 1
; VI-NEXT:    v_div_scale_f32 v10, s[4:5], v4, v4, 1.0
; VI-NEXT:    v_frexp_mant_f32_e64 v3, |s19|
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v9, s23
; VI-NEXT:    v_ldexp_f32 v7, v3, 12
; VI-NEXT:    v_add_u32_e32 v3, vcc, -1, v9
; VI-NEXT:    v_frexp_exp_i32_f32_e32 v8, s19
; VI-NEXT:    v_not_b32_e32 v5, v3
; VI-NEXT:    v_add_u32_e32 v5, vcc, v5, v8
; VI-NEXT:    v_div_scale_f32 v6, vcc, 1.0, v4, 1.0
; VI-NEXT:    v_rcp_f32_e32 v11, v10
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT:    v_fma_f32 v12, -v10, v11, 1.0
; VI-NEXT:    v_fma_f32 v11, v12, v11, v11
; VI-NEXT:    v_mul_f32_e32 v12, v6, v11
; VI-NEXT:    v_fma_f32 v13, -v10, v12, v6
; VI-NEXT:    v_fma_f32 v12, v13, v11, v12
; VI-NEXT:    v_fma_f32 v6, -v10, v12, v6
; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; VI-NEXT:    v_div_fmas_f32 v6, v6, v11, v12
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v5
; VI-NEXT:    v_div_fixup_f32 v6, v6, v4, 1.0
; VI-NEXT:    s_cbranch_vccnz .LBB29_26
; VI-NEXT:  ; %bb.23: ; %frem.loop_body.preheader
; VI-NEXT:    v_sub_u32_e32 v5, vcc, v8, v9
; VI-NEXT:    v_add_u32_e32 v5, vcc, 12, v5
; VI-NEXT:  .LBB29_24: ; %frem.loop_body
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v8, v7
; VI-NEXT:    v_mul_f32_e32 v7, v8, v6
; VI-NEXT:    v_rndne_f32_e32 v7, v7
; VI-NEXT:    v_fma_f32 v7, -v7, v4, v8
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v7
; VI-NEXT:    v_add_f32_e32 v9, v7, v4
; VI-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc
; VI-NEXT:    v_add_u32_e32 v5, vcc, -12, v5
; VI-NEXT:    v_ldexp_f32 v7, v7, 12
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v5
; VI-NEXT:    s_cbranch_vccnz .LBB29_24
; VI-NEXT:    s_branch .LBB29_27
; VI-NEXT:  .LBB29_25: ; %frem.else
; VI-NEXT:    s_and_b32 s4, 0x80000000, s19
; VI-NEXT:    v_mov_b32_e32 v3, s23
; VI-NEXT:    v_cmp_eq_f32_e64 vcc, |s19|, |v3|
; VI-NEXT:    v_mov_b32_e32 v3, s19
; VI-NEXT:    v_mov_b32_e32 v4, s4
; VI-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
; VI-NEXT:    s_branch .LBB29_28
; VI-NEXT:  .LBB29_26:
; VI-NEXT:    v_mov_b32_e32 v8, v7
; VI-NEXT:  .LBB29_27: ; %frem.loop_exit
; VI-NEXT:    v_add_u32_e32 v5, vcc, -11, v5
; VI-NEXT:    v_ldexp_f32 v5, v8, v5
; VI-NEXT:    v_mul_f32_e32 v6, v5, v6
; VI-NEXT:    v_rndne_f32_e32 v6, v6
; VI-NEXT:    v_fma_f32 v5, -v6, v4, v5
; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
; VI-NEXT:    v_add_f32_e32 v4, v5, v4
; VI-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc
; VI-NEXT:    v_ldexp_f32 v3, v4, v3
; VI-NEXT:    s_brev_b32 s4, -2
; VI-NEXT:    v_mov_b32_e32 v4, s19
; VI-NEXT:    v_bfi_b32 v3, s4, v3, v4
; VI-NEXT:  .LBB29_28:
; VI-NEXT:    v_mov_b32_e32 v4, 0x7f800000
; VI-NEXT:    v_cmp_lg_f32_e64 s[4:5], s20, 0
; VI-NEXT:    v_cmp_nge_f32_e64 s[6:7], |s16|, v4
; VI-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; VI-NEXT:    v_mov_b32_e32 v5, 0x7fc00000
; VI-NEXT:    v_cmp_lg_f32_e64 s[4:5], s21, 0
; VI-NEXT:    v_cmp_nge_f32_e64 s[6:7], |s17|, v4
; VI-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc
; VI-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; VI-NEXT:    v_cmp_lg_f32_e64 s[4:5], s22, 0
; VI-NEXT:    v_cmp_nge_f32_e64 s[6:7], |s18|, v4
; VI-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
; VI-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; VI-NEXT:    v_cmp_lg_f32_e64 s[4:5], s23, 0
; VI-NEXT:    v_cmp_nge_f32_e64 s[6:7], |s19|, v4
; VI-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
; VI-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; VI-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: frem_v4f32_uniform:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v0, s20
; GFX9-NEXT:    v_cmp_gt_f32_e64 vcc, |s16|, |v0|
; GFX9-NEXT:    s_cbranch_vccz .LBB29_4
; GFX9-NEXT:  ; %bb.1: ; %frem.compute77
; GFX9-NEXT:    v_frexp_mant_f32_e64 v1, |s20|
; GFX9-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX9-NEXT:    v_div_scale_f32 v7, s[4:5], v1, v1, 1.0
; GFX9-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v1, 1.0
; GFX9-NEXT:    v_frexp_mant_f32_e64 v0, |s16|
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v5, s16
; GFX9-NEXT:    v_ldexp_f32 v4, v0, 12
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v6, s20
; GFX9-NEXT:    v_add_u32_e32 v0, -1, v6
; GFX9-NEXT:    v_not_b32_e32 v2, v0
; GFX9-NEXT:    v_add_u32_e32 v2, v2, v5
; GFX9-NEXT:    v_rcp_f32_e32 v8, v7
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
; GFX9-NEXT:    v_fma_f32 v8, v9, v8, v8
; GFX9-NEXT:    v_mul_f32_e32 v9, v3, v8
; GFX9-NEXT:    v_fma_f32 v10, -v7, v9, v3
; GFX9-NEXT:    v_fma_f32 v9, v10, v8, v9
; GFX9-NEXT:    v_fma_f32 v3, -v7, v9, v3
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX9-NEXT:    v_div_fmas_f32 v3, v3, v8, v9
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v2
; GFX9-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX9-NEXT:    s_cbranch_vccnz .LBB29_5
; GFX9-NEXT:  ; %bb.2: ; %frem.loop_body85.preheader
; GFX9-NEXT:    v_sub_u32_e32 v2, v5, v6
; GFX9-NEXT:    v_add_u32_e32 v2, 12, v2
; GFX9-NEXT:  .LBB29_3: ; %frem.loop_body85
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v5, v4
; GFX9-NEXT:    v_mul_f32_e32 v4, v5, v3
; GFX9-NEXT:    v_rndne_f32_e32 v4, v4
; GFX9-NEXT:    v_fma_f32 v4, -v4, v1, v5
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; GFX9-NEXT:    v_add_f32_e32 v6, v4, v1
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX9-NEXT:    v_add_u32_e32 v2, -12, v2
; GFX9-NEXT:    v_ldexp_f32 v4, v4, 12
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v2
; GFX9-NEXT:    s_cbranch_vccnz .LBB29_3
; GFX9-NEXT:    s_branch .LBB29_6
; GFX9-NEXT:  .LBB29_4: ; %frem.else78
; GFX9-NEXT:    s_and_b32 s4, 0x80000000, s16
; GFX9-NEXT:    v_mov_b32_e32 v0, s20
; GFX9-NEXT:    v_cmp_eq_f32_e64 vcc, |s16|, |v0|
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s4
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX9-NEXT:    s_branch .LBB29_7
; GFX9-NEXT:  .LBB29_5:
; GFX9-NEXT:    v_mov_b32_e32 v5, v4
; GFX9-NEXT:  .LBB29_6: ; %frem.loop_exit86
; GFX9-NEXT:    v_add_u32_e32 v2, -11, v2
; GFX9-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX9-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX9-NEXT:    v_rndne_f32_e32 v3, v3
; GFX9-NEXT:    v_fma_f32 v2, -v3, v1, v2
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v2
; GFX9-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX9-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX9-NEXT:    s_brev_b32 s4, -2
; GFX9-NEXT:    v_mov_b32_e32 v1, s16
; GFX9-NEXT:    v_bfi_b32 v0, s4, v0, v1
; GFX9-NEXT:  .LBB29_7:
; GFX9-NEXT:    v_mov_b32_e32 v1, s21
; GFX9-NEXT:    v_cmp_gt_f32_e64 vcc, |s17|, |v1|
; GFX9-NEXT:    s_cbranch_vccz .LBB29_11
; GFX9-NEXT:  ; %bb.8: ; %frem.compute46
; GFX9-NEXT:    v_frexp_mant_f32_e64 v2, |s21|
; GFX9-NEXT:    v_ldexp_f32 v2, v2, 1
; GFX9-NEXT:    v_div_scale_f32 v8, s[4:5], v2, v2, 1.0
; GFX9-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v2, 1.0
; GFX9-NEXT:    v_frexp_mant_f32_e64 v1, |s17|
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v6, s17
; GFX9-NEXT:    v_ldexp_f32 v5, v1, 12
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v7, s21
; GFX9-NEXT:    v_add_u32_e32 v1, -1, v7
; GFX9-NEXT:    v_not_b32_e32 v3, v1
; GFX9-NEXT:    v_add_u32_e32 v3, v3, v6
; GFX9-NEXT:    v_rcp_f32_e32 v9, v8
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
; GFX9-NEXT:    v_fma_f32 v9, v10, v9, v9
; GFX9-NEXT:    v_mul_f32_e32 v10, v4, v9
; GFX9-NEXT:    v_fma_f32 v11, -v8, v10, v4
; GFX9-NEXT:    v_fma_f32 v10, v11, v9, v10
; GFX9-NEXT:    v_fma_f32 v4, -v8, v10, v4
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX9-NEXT:    v_div_fmas_f32 v4, v4, v9, v10
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v3
; GFX9-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; GFX9-NEXT:    s_cbranch_vccnz .LBB29_12
; GFX9-NEXT:  ; %bb.9: ; %frem.loop_body54.preheader
; GFX9-NEXT:    v_sub_u32_e32 v3, v6, v7
; GFX9-NEXT:    v_add_u32_e32 v3, 12, v3
; GFX9-NEXT:  .LBB29_10: ; %frem.loop_body54
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v6, v5
; GFX9-NEXT:    v_mul_f32_e32 v5, v6, v4
; GFX9-NEXT:    v_rndne_f32_e32 v5, v5
; GFX9-NEXT:    v_fma_f32 v5, -v5, v2, v6
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
; GFX9-NEXT:    v_add_f32_e32 v7, v5, v2
; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
; GFX9-NEXT:    v_add_u32_e32 v3, -12, v3
; GFX9-NEXT:    v_ldexp_f32 v5, v5, 12
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v3
; GFX9-NEXT:    s_cbranch_vccnz .LBB29_10
; GFX9-NEXT:    s_branch .LBB29_13
; GFX9-NEXT:  .LBB29_11: ; %frem.else47
; GFX9-NEXT:    s_and_b32 s4, 0x80000000, s17
; GFX9-NEXT:    v_mov_b32_e32 v1, s21
; GFX9-NEXT:    v_cmp_eq_f32_e64 vcc, |s17|, |v1|
; GFX9-NEXT:    v_mov_b32_e32 v1, s17
; GFX9-NEXT:    v_mov_b32_e32 v2, s4
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX9-NEXT:    s_branch .LBB29_14
; GFX9-NEXT:  .LBB29_12:
; GFX9-NEXT:    v_mov_b32_e32 v6, v5
; GFX9-NEXT:  .LBB29_13: ; %frem.loop_exit55
; GFX9-NEXT:    v_add_u32_e32 v3, -11, v3
; GFX9-NEXT:    v_ldexp_f32 v3, v6, v3
; GFX9-NEXT:    v_mul_f32_e32 v4, v3, v4
; GFX9-NEXT:    v_rndne_f32_e32 v4, v4
; GFX9-NEXT:    v_fma_f32 v3, -v4, v2, v3
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v3
; GFX9-NEXT:    v_add_f32_e32 v2, v3, v2
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX9-NEXT:    v_ldexp_f32 v1, v2, v1
; GFX9-NEXT:    s_brev_b32 s4, -2
; GFX9-NEXT:    v_mov_b32_e32 v2, s17
; GFX9-NEXT:    v_bfi_b32 v1, s4, v1, v2
; GFX9-NEXT:  .LBB29_14:
; GFX9-NEXT:    v_mov_b32_e32 v2, s22
; GFX9-NEXT:    v_cmp_gt_f32_e64 vcc, |s18|, |v2|
; GFX9-NEXT:    s_cbranch_vccz .LBB29_18
; GFX9-NEXT:  ; %bb.15: ; %frem.compute15
; GFX9-NEXT:    v_frexp_mant_f32_e64 v3, |s22|
; GFX9-NEXT:    v_ldexp_f32 v3, v3, 1
; GFX9-NEXT:    v_div_scale_f32 v9, s[4:5], v3, v3, 1.0
; GFX9-NEXT:    v_div_scale_f32 v5, vcc, 1.0, v3, 1.0
; GFX9-NEXT:    v_frexp_mant_f32_e64 v2, |s18|
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v7, s18
; GFX9-NEXT:    v_ldexp_f32 v6, v2, 12
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v8, s22
; GFX9-NEXT:    v_add_u32_e32 v2, -1, v8
; GFX9-NEXT:    v_not_b32_e32 v4, v2
; GFX9-NEXT:    v_add_u32_e32 v4, v4, v7
; GFX9-NEXT:    v_rcp_f32_e32 v10, v9
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
; GFX9-NEXT:    v_fma_f32 v10, v11, v10, v10
; GFX9-NEXT:    v_mul_f32_e32 v11, v5, v10
; GFX9-NEXT:    v_fma_f32 v12, -v9, v11, v5
; GFX9-NEXT:    v_fma_f32 v11, v12, v10, v11
; GFX9-NEXT:    v_fma_f32 v5, -v9, v11, v5
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX9-NEXT:    v_div_fmas_f32 v5, v5, v10, v11
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v4
; GFX9-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
; GFX9-NEXT:    s_cbranch_vccnz .LBB29_19
; GFX9-NEXT:  ; %bb.16: ; %frem.loop_body23.preheader
; GFX9-NEXT:    v_sub_u32_e32 v4, v7, v8
; GFX9-NEXT:    v_add_u32_e32 v4, 12, v4
; GFX9-NEXT:  .LBB29_17: ; %frem.loop_body23
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v7, v6
; GFX9-NEXT:    v_mul_f32_e32 v6, v7, v5
; GFX9-NEXT:    v_rndne_f32_e32 v6, v6
; GFX9-NEXT:    v_fma_f32 v6, -v6, v3, v7
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v6
; GFX9-NEXT:    v_add_f32_e32 v8, v6, v3
; GFX9-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc
; GFX9-NEXT:    v_add_u32_e32 v4, -12, v4
; GFX9-NEXT:    v_ldexp_f32 v6, v6, 12
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v4
; GFX9-NEXT:    s_cbranch_vccnz .LBB29_17
; GFX9-NEXT:    s_branch .LBB29_20
; GFX9-NEXT:  .LBB29_18: ; %frem.else16
; GFX9-NEXT:    s_and_b32 s4, 0x80000000, s18
; GFX9-NEXT:    v_mov_b32_e32 v2, s22
; GFX9-NEXT:    v_cmp_eq_f32_e64 vcc, |s18|, |v2|
; GFX9-NEXT:    v_mov_b32_e32 v2, s18
; GFX9-NEXT:    v_mov_b32_e32 v3, s4
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX9-NEXT:    s_branch .LBB29_21
; GFX9-NEXT:  .LBB29_19:
; GFX9-NEXT:    v_mov_b32_e32 v7, v6
; GFX9-NEXT:  .LBB29_20: ; %frem.loop_exit24
; GFX9-NEXT:    v_add_u32_e32 v4, -11, v4
; GFX9-NEXT:    v_ldexp_f32 v4, v7, v4
; GFX9-NEXT:    v_mul_f32_e32 v5, v4, v5
; GFX9-NEXT:    v_rndne_f32_e32 v5, v5
; GFX9-NEXT:    v_fma_f32 v4, -v5, v3, v4
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
; GFX9-NEXT:    v_add_f32_e32 v3, v4, v3
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX9-NEXT:    v_ldexp_f32 v2, v3, v2
; GFX9-NEXT:    s_brev_b32 s4, -2
; GFX9-NEXT:    v_mov_b32_e32 v3, s18
; GFX9-NEXT:    v_bfi_b32 v2, s4, v2, v3
; GFX9-NEXT:  .LBB29_21:
; GFX9-NEXT:    v_mov_b32_e32 v3, s23
; GFX9-NEXT:    v_cmp_gt_f32_e64 vcc, |s19|, |v3|
; GFX9-NEXT:    s_cbranch_vccz .LBB29_25
; GFX9-NEXT:  ; %bb.22: ; %frem.compute
; GFX9-NEXT:    v_frexp_mant_f32_e64 v4, |s23|
; GFX9-NEXT:    v_ldexp_f32 v4, v4, 1
; GFX9-NEXT:    v_div_scale_f32 v10, s[4:5], v4, v4, 1.0
; GFX9-NEXT:    v_div_scale_f32 v6, vcc, 1.0, v4, 1.0
; GFX9-NEXT:    v_frexp_mant_f32_e64 v3, |s19|
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v8, s19
; GFX9-NEXT:    v_ldexp_f32 v7, v3, 12
; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v9, s23
; GFX9-NEXT:    v_add_u32_e32 v3, -1, v9
; GFX9-NEXT:    v_not_b32_e32 v5, v3
; GFX9-NEXT:    v_add_u32_e32 v5, v5, v8
; GFX9-NEXT:    v_rcp_f32_e32 v11, v10
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT:    v_fma_f32 v12, -v10, v11, 1.0
; GFX9-NEXT:    v_fma_f32 v11, v12, v11, v11
; GFX9-NEXT:    v_mul_f32_e32 v12, v6, v11
; GFX9-NEXT:    v_fma_f32 v13, -v10, v12, v6
; GFX9-NEXT:    v_fma_f32 v12, v13, v11, v12
; GFX9-NEXT:    v_fma_f32 v6, -v10, v12, v6
; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX9-NEXT:    v_div_fmas_f32 v6, v6, v11, v12
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v5
; GFX9-NEXT:    v_div_fixup_f32 v6, v6, v4, 1.0
; GFX9-NEXT:    s_cbranch_vccnz .LBB29_26
; GFX9-NEXT:  ; %bb.23: ; %frem.loop_body.preheader
; GFX9-NEXT:    v_sub_u32_e32 v5, v8, v9
; GFX9-NEXT:    v_add_u32_e32 v5, 12, v5
; GFX9-NEXT:  .LBB29_24: ; %frem.loop_body
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v8, v7
; GFX9-NEXT:    v_mul_f32_e32 v7, v8, v6
; GFX9-NEXT:    v_rndne_f32_e32 v7, v7
; GFX9-NEXT:    v_fma_f32 v7, -v7, v4, v8
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v7
; GFX9-NEXT:    v_add_f32_e32 v9, v7, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc
; GFX9-NEXT:    v_add_u32_e32 v5, -12, v5
; GFX9-NEXT:    v_ldexp_f32 v7, v7, 12
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v5
; GFX9-NEXT:    s_cbranch_vccnz .LBB29_24
; GFX9-NEXT:    s_branch .LBB29_27
; GFX9-NEXT:  .LBB29_25: ; %frem.else
; GFX9-NEXT:    s_and_b32 s4, 0x80000000, s19
; GFX9-NEXT:    v_mov_b32_e32 v3, s23
; GFX9-NEXT:    v_cmp_eq_f32_e64 vcc, |s19|, |v3|
; GFX9-NEXT:    v_mov_b32_e32 v3, s19
; GFX9-NEXT:    v_mov_b32_e32 v4, s4
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX9-NEXT:    s_branch .LBB29_28
; GFX9-NEXT:  .LBB29_26:
; GFX9-NEXT:    v_mov_b32_e32 v8, v7
; GFX9-NEXT:  .LBB29_27: ; %frem.loop_exit
; GFX9-NEXT:    v_add_u32_e32 v5, -11, v5
; GFX9-NEXT:    v_ldexp_f32 v5, v8, v5
; GFX9-NEXT:    v_mul_f32_e32 v6, v5, v6
; GFX9-NEXT:    v_rndne_f32_e32 v6, v6
; GFX9-NEXT:    v_fma_f32 v5, -v6, v4, v5
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
; GFX9-NEXT:    v_add_f32_e32 v4, v5, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc
; GFX9-NEXT:    v_ldexp_f32 v3, v4, v3
; GFX9-NEXT:    s_brev_b32 s4, -2
; GFX9-NEXT:    v_mov_b32_e32 v4, s19
; GFX9-NEXT:    v_bfi_b32 v3, s4, v3, v4
; GFX9-NEXT:  .LBB29_28:
; GFX9-NEXT:    v_mov_b32_e32 v4, 0x7f800000
; GFX9-NEXT:    v_cmp_lg_f32_e64 s[4:5], s20, 0
; GFX9-NEXT:    v_cmp_nge_f32_e64 s[6:7], |s16|, v4
; GFX9-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; GFX9-NEXT:    v_mov_b32_e32 v5, 0x7fc00000
; GFX9-NEXT:    v_cmp_lg_f32_e64 s[4:5], s21, 0
; GFX9-NEXT:    v_cmp_nge_f32_e64 s[6:7], |s17|, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc
; GFX9-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; GFX9-NEXT:    v_cmp_lg_f32_e64 s[4:5], s22, 0
; GFX9-NEXT:    v_cmp_nge_f32_e64 s[6:7], |s18|, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
; GFX9-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; GFX9-NEXT:    v_cmp_lg_f32_e64 s[4:5], s23, 0
; GFX9-NEXT:    v_cmp_nge_f32_e64 s[6:7], |s19|, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
; GFX9-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: frem_v4f32_uniform:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cmp_gt_f32_e64 vcc_lo, |s16|, |s20|
; GFX10-NEXT:    s_cbranch_vccz .LBB29_5
; GFX10-NEXT:  ; %bb.1: ; %frem.compute77
; GFX10-NEXT:    v_frexp_mant_f32_e64 v1, |s20|
; GFX10-NEXT:    v_frexp_mant_f32_e64 v0, |s16|
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v3, s16
; GFX10-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX10-NEXT:    v_ldexp_f32 v2, v0, 12
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v0, s20
; GFX10-NEXT:    v_readfirstlane_b32 s4, v3
; GFX10-NEXT:    v_div_scale_f32 v5, s6, v1, v1, 1.0
; GFX10-NEXT:    v_readfirstlane_b32 s5, v0
; GFX10-NEXT:    v_add_nc_u32_e32 v0, -1, v0
; GFX10-NEXT:    v_rcp_f32_e32 v6, v5
; GFX10-NEXT:    v_not_b32_e32 v4, v0
; GFX10-NEXT:    v_add_nc_u32_e32 v4, v4, v3
; GFX10-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX10-NEXT:    s_denorm_mode 15
; GFX10-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
; GFX10-NEXT:    v_fmac_f32_e32 v6, v7, v6
; GFX10-NEXT:    v_mul_f32_e32 v7, v3, v6
; GFX10-NEXT:    v_fma_f32 v8, -v5, v7, v3
; GFX10-NEXT:    v_fmac_f32_e32 v7, v8, v6
; GFX10-NEXT:    v_fma_f32 v3, -v5, v7, v3
; GFX10-NEXT:    s_denorm_mode 12
; GFX10-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v4
; GFX10-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX10-NEXT:    s_cbranch_vccnz .LBB29_9
; GFX10-NEXT:  ; %bb.2: ; %frem.loop_body85.preheader
; GFX10-NEXT:    s_sub_i32 s4, s4, s5
; GFX10-NEXT:    s_add_i32 s4, s4, 12
; GFX10-NEXT:  .LBB29_3: ; %frem.loop_body85
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v5, v2
; GFX10-NEXT:    s_add_i32 s4, s4, -12
; GFX10-NEXT:    s_cmp_gt_i32 s4, 12
; GFX10-NEXT:    v_mul_f32_e32 v2, v5, v3
; GFX10-NEXT:    v_rndne_f32_e32 v2, v2
; GFX10-NEXT:    v_fma_f32 v2, -v2, v1, v5
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX10-NEXT:    v_add_f32_e32 v4, v2, v1
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v2, v2, 12
; GFX10-NEXT:    s_cbranch_scc1 .LBB29_3
; GFX10-NEXT:  ; %bb.4:
; GFX10-NEXT:    v_mov_b32_e32 v4, s4
; GFX10-NEXT:    s_branch .LBB29_10
; GFX10-NEXT:  .LBB29_5: ; %frem.else78
; GFX10-NEXT:    s_and_b32 s4, 0x80000000, s16
; GFX10-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |s16|, |s20|
; GFX10-NEXT:    v_mov_b32_e32 v0, s4
; GFX10-NEXT:    v_cndmask_b32_e32 v0, s16, v0, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e64 vcc_lo, |s17|, |s21|
; GFX10-NEXT:    s_cbranch_vccnz .LBB29_11
; GFX10-NEXT:  .LBB29_6: ; %frem.else47
; GFX10-NEXT:    s_and_b32 s4, 0x80000000, s17
; GFX10-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |s17|, |s21|
; GFX10-NEXT:    v_mov_b32_e32 v1, s4
; GFX10-NEXT:    v_cndmask_b32_e32 v1, s17, v1, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e64 vcc_lo, |s18|, |s22|
; GFX10-NEXT:    s_cbranch_vccnz .LBB29_17
; GFX10-NEXT:  .LBB29_7: ; %frem.else16
; GFX10-NEXT:    s_and_b32 s4, 0x80000000, s18
; GFX10-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |s18|, |s22|
; GFX10-NEXT:    v_mov_b32_e32 v2, s4
; GFX10-NEXT:    v_cndmask_b32_e32 v2, s18, v2, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e64 vcc_lo, |s19|, |s23|
; GFX10-NEXT:    s_cbranch_vccnz .LBB29_23
; GFX10-NEXT:  .LBB29_8: ; %frem.else
; GFX10-NEXT:    s_and_b32 s4, 0x80000000, s19
; GFX10-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |s19|, |s23|
; GFX10-NEXT:    v_mov_b32_e32 v3, s4
; GFX10-NEXT:    v_cndmask_b32_e32 v3, s19, v3, vcc_lo
; GFX10-NEXT:    s_branch .LBB29_29
; GFX10-NEXT:  .LBB29_9:
; GFX10-NEXT:    v_mov_b32_e32 v5, v2
; GFX10-NEXT:  .LBB29_10: ; %frem.loop_exit86
; GFX10-NEXT:    v_add_nc_u32_e32 v2, -11, v4
; GFX10-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX10-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX10-NEXT:    v_rndne_f32_e32 v3, v3
; GFX10-NEXT:    v_fma_f32 v2, -v3, v1, v2
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX10-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX10-NEXT:    v_bfi_b32 v0, 0x7fffffff, v0, s16
; GFX10-NEXT:    v_cmp_gt_f32_e64 vcc_lo, |s17|, |s21|
; GFX10-NEXT:    s_cbranch_vccz .LBB29_6
; GFX10-NEXT:  .LBB29_11: ; %frem.compute46
; GFX10-NEXT:    v_frexp_mant_f32_e64 v2, |s21|
; GFX10-NEXT:    v_frexp_mant_f32_e64 v1, |s17|
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v4, s17
; GFX10-NEXT:    v_ldexp_f32 v2, v2, 1
; GFX10-NEXT:    v_ldexp_f32 v3, v1, 12
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v1, s21
; GFX10-NEXT:    v_readfirstlane_b32 s4, v4
; GFX10-NEXT:    v_div_scale_f32 v6, s6, v2, v2, 1.0
; GFX10-NEXT:    v_readfirstlane_b32 s5, v1
; GFX10-NEXT:    v_add_nc_u32_e32 v1, -1, v1
; GFX10-NEXT:    v_rcp_f32_e32 v7, v6
; GFX10-NEXT:    v_not_b32_e32 v5, v1
; GFX10-NEXT:    v_add_nc_u32_e32 v5, v5, v4
; GFX10-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
; GFX10-NEXT:    s_denorm_mode 15
; GFX10-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
; GFX10-NEXT:    v_fmac_f32_e32 v7, v8, v7
; GFX10-NEXT:    v_mul_f32_e32 v8, v4, v7
; GFX10-NEXT:    v_fma_f32 v9, -v6, v8, v4
; GFX10-NEXT:    v_fmac_f32_e32 v8, v9, v7
; GFX10-NEXT:    v_fma_f32 v4, -v6, v8, v4
; GFX10-NEXT:    s_denorm_mode 12
; GFX10-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v5
; GFX10-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; GFX10-NEXT:    s_cbranch_vccnz .LBB29_15
; GFX10-NEXT:  ; %bb.12: ; %frem.loop_body54.preheader
; GFX10-NEXT:    s_sub_i32 s4, s4, s5
; GFX10-NEXT:    s_add_i32 s4, s4, 12
; GFX10-NEXT:  .LBB29_13: ; %frem.loop_body54
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v6, v3
; GFX10-NEXT:    s_add_i32 s4, s4, -12
; GFX10-NEXT:    s_cmp_gt_i32 s4, 12
; GFX10-NEXT:    v_mul_f32_e32 v3, v6, v4
; GFX10-NEXT:    v_rndne_f32_e32 v3, v3
; GFX10-NEXT:    v_fma_f32 v3, -v3, v2, v6
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX10-NEXT:    v_add_f32_e32 v5, v3, v2
; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v3, v3, 12
; GFX10-NEXT:    s_cbranch_scc1 .LBB29_13
; GFX10-NEXT:  ; %bb.14:
; GFX10-NEXT:    v_mov_b32_e32 v5, s4
; GFX10-NEXT:    s_branch .LBB29_16
; GFX10-NEXT:  .LBB29_15:
; GFX10-NEXT:    v_mov_b32_e32 v6, v3
; GFX10-NEXT:  .LBB29_16: ; %frem.loop_exit55
; GFX10-NEXT:    v_add_nc_u32_e32 v3, -11, v5
; GFX10-NEXT:    v_ldexp_f32 v3, v6, v3
; GFX10-NEXT:    v_mul_f32_e32 v4, v3, v4
; GFX10-NEXT:    v_rndne_f32_e32 v4, v4
; GFX10-NEXT:    v_fma_f32 v3, -v4, v2, v3
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX10-NEXT:    v_add_f32_e32 v2, v3, v2
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v1, v2, v1
; GFX10-NEXT:    v_bfi_b32 v1, 0x7fffffff, v1, s17
; GFX10-NEXT:    v_cmp_gt_f32_e64 vcc_lo, |s18|, |s22|
; GFX10-NEXT:    s_cbranch_vccz .LBB29_7
; GFX10-NEXT:  .LBB29_17: ; %frem.compute15
; GFX10-NEXT:    v_frexp_mant_f32_e64 v3, |s22|
; GFX10-NEXT:    v_frexp_mant_f32_e64 v2, |s18|
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v5, s18
; GFX10-NEXT:    v_ldexp_f32 v3, v3, 1
; GFX10-NEXT:    v_ldexp_f32 v4, v2, 12
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v2, s22
; GFX10-NEXT:    v_readfirstlane_b32 s4, v5
; GFX10-NEXT:    v_div_scale_f32 v7, s6, v3, v3, 1.0
; GFX10-NEXT:    v_readfirstlane_b32 s5, v2
; GFX10-NEXT:    v_add_nc_u32_e32 v2, -1, v2
; GFX10-NEXT:    v_rcp_f32_e32 v8, v7
; GFX10-NEXT:    v_not_b32_e32 v6, v2
; GFX10-NEXT:    v_add_nc_u32_e32 v6, v6, v5
; GFX10-NEXT:    v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX10-NEXT:    s_denorm_mode 15
; GFX10-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
; GFX10-NEXT:    v_fmac_f32_e32 v8, v9, v8
; GFX10-NEXT:    v_mul_f32_e32 v9, v5, v8
; GFX10-NEXT:    v_fma_f32 v10, -v7, v9, v5
; GFX10-NEXT:    v_fmac_f32_e32 v9, v10, v8
; GFX10-NEXT:    v_fma_f32 v5, -v7, v9, v5
; GFX10-NEXT:    s_denorm_mode 12
; GFX10-NEXT:    v_div_fmas_f32 v5, v5, v8, v9
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v6
; GFX10-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
; GFX10-NEXT:    s_cbranch_vccnz .LBB29_21
; GFX10-NEXT:  ; %bb.18: ; %frem.loop_body23.preheader
; GFX10-NEXT:    s_sub_i32 s4, s4, s5
; GFX10-NEXT:    s_add_i32 s4, s4, 12
; GFX10-NEXT:  .LBB29_19: ; %frem.loop_body23
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v7, v4
; GFX10-NEXT:    s_add_i32 s4, s4, -12
; GFX10-NEXT:    s_cmp_gt_i32 s4, 12
; GFX10-NEXT:    v_mul_f32_e32 v4, v7, v5
; GFX10-NEXT:    v_rndne_f32_e32 v4, v4
; GFX10-NEXT:    v_fma_f32 v4, -v4, v3, v7
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX10-NEXT:    v_add_f32_e32 v6, v4, v3
; GFX10-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v4, v4, 12
; GFX10-NEXT:    s_cbranch_scc1 .LBB29_19
; GFX10-NEXT:  ; %bb.20:
; GFX10-NEXT:    v_mov_b32_e32 v6, s4
; GFX10-NEXT:    s_branch .LBB29_22
; GFX10-NEXT:  .LBB29_21:
; GFX10-NEXT:    v_mov_b32_e32 v7, v4
; GFX10-NEXT:  .LBB29_22: ; %frem.loop_exit24
; GFX10-NEXT:    v_add_nc_u32_e32 v4, -11, v6
; GFX10-NEXT:    v_ldexp_f32 v4, v7, v4
; GFX10-NEXT:    v_mul_f32_e32 v5, v4, v5
; GFX10-NEXT:    v_rndne_f32_e32 v5, v5
; GFX10-NEXT:    v_fma_f32 v4, -v5, v3, v4
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX10-NEXT:    v_add_f32_e32 v3, v4, v3
; GFX10-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v2, v3, v2
; GFX10-NEXT:    v_bfi_b32 v2, 0x7fffffff, v2, s18
; GFX10-NEXT:    v_cmp_gt_f32_e64 vcc_lo, |s19|, |s23|
; GFX10-NEXT:    s_cbranch_vccz .LBB29_8
; GFX10-NEXT:  .LBB29_23: ; %frem.compute
; GFX10-NEXT:    v_frexp_mant_f32_e64 v4, |s23|
; GFX10-NEXT:    v_frexp_mant_f32_e64 v3, |s19|
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v6, s19
; GFX10-NEXT:    v_ldexp_f32 v4, v4, 1
; GFX10-NEXT:    v_ldexp_f32 v5, v3, 12
; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v3, s23
; GFX10-NEXT:    v_readfirstlane_b32 s4, v6
; GFX10-NEXT:    v_div_scale_f32 v8, s6, v4, v4, 1.0
; GFX10-NEXT:    v_readfirstlane_b32 s5, v3
; GFX10-NEXT:    v_add_nc_u32_e32 v3, -1, v3
; GFX10-NEXT:    v_rcp_f32_e32 v9, v8
; GFX10-NEXT:    v_not_b32_e32 v7, v3
; GFX10-NEXT:    v_add_nc_u32_e32 v7, v7, v6
; GFX10-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v4, 1.0
; GFX10-NEXT:    s_denorm_mode 15
; GFX10-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
; GFX10-NEXT:    v_fmac_f32_e32 v9, v10, v9
; GFX10-NEXT:    v_mul_f32_e32 v10, v6, v9
; GFX10-NEXT:    v_fma_f32 v11, -v8, v10, v6
; GFX10-NEXT:    v_fmac_f32_e32 v10, v11, v9
; GFX10-NEXT:    v_fma_f32 v6, -v8, v10, v6
; GFX10-NEXT:    s_denorm_mode 12
; GFX10-NEXT:    v_div_fmas_f32 v6, v6, v9, v10
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v7
; GFX10-NEXT:    v_div_fixup_f32 v6, v6, v4, 1.0
; GFX10-NEXT:    s_cbranch_vccnz .LBB29_27
; GFX10-NEXT:  ; %bb.24: ; %frem.loop_body.preheader
; GFX10-NEXT:    s_sub_i32 s4, s4, s5
; GFX10-NEXT:    s_add_i32 s4, s4, 12
; GFX10-NEXT:  .LBB29_25: ; %frem.loop_body
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v8, v5
; GFX10-NEXT:    s_add_i32 s4, s4, -12
; GFX10-NEXT:    s_cmp_gt_i32 s4, 12
; GFX10-NEXT:    v_mul_f32_e32 v5, v8, v6
; GFX10-NEXT:    v_rndne_f32_e32 v5, v5
; GFX10-NEXT:    v_fma_f32 v5, -v5, v4, v8
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX10-NEXT:    v_add_f32_e32 v7, v5, v4
; GFX10-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v5, v5, 12
; GFX10-NEXT:    s_cbranch_scc1 .LBB29_25
; GFX10-NEXT:  ; %bb.26:
; GFX10-NEXT:    v_mov_b32_e32 v7, s4
; GFX10-NEXT:    s_branch .LBB29_28
; GFX10-NEXT:  .LBB29_27:
; GFX10-NEXT:    v_mov_b32_e32 v8, v5
; GFX10-NEXT:  .LBB29_28: ; %frem.loop_exit
; GFX10-NEXT:    v_add_nc_u32_e32 v5, -11, v7
; GFX10-NEXT:    v_ldexp_f32 v5, v8, v5
; GFX10-NEXT:    v_mul_f32_e32 v6, v5, v6
; GFX10-NEXT:    v_rndne_f32_e32 v6, v6
; GFX10-NEXT:    v_fma_f32 v5, -v6, v4, v5
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX10-NEXT:    v_add_f32_e32 v4, v5, v4
; GFX10-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc_lo
; GFX10-NEXT:    v_ldexp_f32 v3, v4, v3
; GFX10-NEXT:    v_bfi_b32 v3, 0x7fffffff, v3, s19
; GFX10-NEXT:  .LBB29_29:
; GFX10-NEXT:    v_cmp_lg_f32_e64 s4, s20, 0
; GFX10-NEXT:    v_cmp_nge_f32_e64 s5, |s16|, 0x7f800000
; GFX10-NEXT:    s_and_b32 vcc_lo, s5, s4
; GFX10-NEXT:    v_cmp_lg_f32_e64 s4, s21, 0
; GFX10-NEXT:    v_cmp_nge_f32_e64 s5, |s17|, 0x7f800000
; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
; GFX10-NEXT:    s_and_b32 vcc_lo, s5, s4
; GFX10-NEXT:    v_cmp_lg_f32_e64 s4, s22, 0
; GFX10-NEXT:    v_cmp_nge_f32_e64 s5, |s18|, 0x7f800000
; GFX10-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v1, vcc_lo
; GFX10-NEXT:    s_and_b32 vcc_lo, s5, s4
; GFX10-NEXT:    v_cmp_lg_f32_e64 s4, s23, 0
; GFX10-NEXT:    v_cmp_nge_f32_e64 s5, |s19|, 0x7f800000
; GFX10-NEXT:    v_cndmask_b32_e32 v2, 0x7fc00000, v2, vcc_lo
; GFX10-NEXT:    s_and_b32 vcc_lo, s5, s4
; GFX10-NEXT:    v_cndmask_b32_e32 v3, 0x7fc00000, v3, vcc_lo
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: frem_v4f32_uniform:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cmp_gt_f32_e64 vcc_lo, |s0|, |s16|
; GFX11-NEXT:    s_cbranch_vccz .LBB29_5
; GFX11-NEXT:  ; %bb.1: ; %frem.compute77
; GFX11-NEXT:    v_frexp_mant_f32_e64 v1, |s16|
; GFX11-NEXT:    v_frexp_mant_f32_e64 v0, |s0|
; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v3, s0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX11-NEXT:    v_ldexp_f32 v2, v0, 12
; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v0, s16
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_readfirstlane_b32 s4, v3
; GFX11-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_readfirstlane_b32 s5, v0
; GFX11-NEXT:    v_add_nc_u32_e32 v0, -1, v0
; GFX11-NEXT:    v_rcp_f32_e32 v6, v5
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_not_b32_e32 v4, v0
; GFX11-NEXT:    v_add_nc_u32_e32 v4, v4, v3
; GFX11-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX11-NEXT:    s_denorm_mode 15
; GFX11-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fmac_f32_e32 v6, v7, v6
; GFX11-NEXT:    v_mul_f32_e32 v7, v3, v6
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v8, -v5, v7, v3
; GFX11-NEXT:    v_fmac_f32_e32 v7, v8, v6
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v3, -v5, v7, v3
; GFX11-NEXT:    s_denorm_mode 12
; GFX11-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v4
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX11-NEXT:    s_cbranch_vccnz .LBB29_9
; GFX11-NEXT:  ; %bb.2: ; %frem.loop_body85.preheader
; GFX11-NEXT:    s_sub_i32 s4, s4, s5
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_add_i32 s4, s4, 12
; GFX11-NEXT:  .LBB29_3: ; %frem.loop_body85
; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT:    v_mov_b32_e32 v5, v2
; GFX11-NEXT:    s_add_i32 s4, s4, -12
; GFX11-NEXT:    s_cmp_gt_i32 s4, 12
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_mul_f32_e32 v2, v5, v3
; GFX11-NEXT:    v_rndne_f32_e32 v2, v2
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v2, -v2, v1, v5
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX11-NEXT:    v_add_f32_e32 v4, v2, v1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX11-NEXT:    v_ldexp_f32 v2, v2, 12
; GFX11-NEXT:    s_cbranch_scc1 .LBB29_3
; GFX11-NEXT:  ; %bb.4:
; GFX11-NEXT:    v_mov_b32_e32 v4, s4
; GFX11-NEXT:    s_branch .LBB29_10
; GFX11-NEXT:  .LBB29_5: ; %frem.else78
; GFX11-NEXT:    s_and_b32 s4, 0x80000000, s0
; GFX11-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |s0|, |s16|
; GFX11-NEXT:    v_mov_b32_e32 v0, s4
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_cndmask_b32_e32 v0, s0, v0, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e64 vcc_lo, |s1|, |s17|
; GFX11-NEXT:    s_cbranch_vccnz .LBB29_11
; GFX11-NEXT:  .LBB29_6: ; %frem.else47
; GFX11-NEXT:    s_and_b32 s4, 0x80000000, s1
; GFX11-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |s1|, |s17|
; GFX11-NEXT:    v_mov_b32_e32 v1, s4
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_cndmask_b32_e32 v1, s1, v1, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e64 vcc_lo, |s2|, |s18|
; GFX11-NEXT:    s_cbranch_vccnz .LBB29_17
; GFX11-NEXT:  .LBB29_7: ; %frem.else16
; GFX11-NEXT:    s_and_b32 s4, 0x80000000, s2
; GFX11-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |s2|, |s18|
; GFX11-NEXT:    v_mov_b32_e32 v2, s4
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_cndmask_b32_e32 v2, s2, v2, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e64 vcc_lo, |s3|, |s19|
; GFX11-NEXT:    s_cbranch_vccnz .LBB29_23
; GFX11-NEXT:  .LBB29_8: ; %frem.else
; GFX11-NEXT:    s_and_b32 s4, 0x80000000, s3
; GFX11-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |s3|, |s19|
; GFX11-NEXT:    v_mov_b32_e32 v3, s4
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_cndmask_b32_e32 v3, s3, v3, vcc_lo
; GFX11-NEXT:    s_branch .LBB29_29
; GFX11-NEXT:  .LBB29_9:
; GFX11-NEXT:    v_mov_b32_e32 v5, v2
; GFX11-NEXT:  .LBB29_10: ; %frem.loop_exit86
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_add_nc_u32_e32 v2, -11, v4
; GFX11-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX11-NEXT:    v_rndne_f32_e32 v3, v3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v2, -v3, v1, v2
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX11-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX11-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_bfi_b32 v0, 0x7fffffff, v0, s0
; GFX11-NEXT:    v_cmp_gt_f32_e64 vcc_lo, |s1|, |s17|
; GFX11-NEXT:    s_cbranch_vccz .LBB29_6
; GFX11-NEXT:  .LBB29_11: ; %frem.compute46
; GFX11-NEXT:    v_frexp_mant_f32_e64 v2, |s17|
; GFX11-NEXT:    v_frexp_mant_f32_e64 v1, |s1|
; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v4, s1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_ldexp_f32 v2, v2, 1
; GFX11-NEXT:    v_ldexp_f32 v3, v1, 12
; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v1, s17
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_readfirstlane_b32 s4, v4
; GFX11-NEXT:    v_div_scale_f32 v6, null, v2, v2, 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_readfirstlane_b32 s5, v1
; GFX11-NEXT:    v_add_nc_u32_e32 v1, -1, v1
; GFX11-NEXT:    v_rcp_f32_e32 v7, v6
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_not_b32_e32 v5, v1
; GFX11-NEXT:    v_add_nc_u32_e32 v5, v5, v4
; GFX11-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
; GFX11-NEXT:    s_denorm_mode 15
; GFX11-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fmac_f32_e32 v7, v8, v7
; GFX11-NEXT:    v_mul_f32_e32 v8, v4, v7
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v9, -v6, v8, v4
; GFX11-NEXT:    v_fmac_f32_e32 v8, v9, v7
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v4, -v6, v8, v4
; GFX11-NEXT:    s_denorm_mode 12
; GFX11-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v5
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; GFX11-NEXT:    s_cbranch_vccnz .LBB29_15
; GFX11-NEXT:  ; %bb.12: ; %frem.loop_body54.preheader
; GFX11-NEXT:    s_sub_i32 s4, s4, s5
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_add_i32 s4, s4, 12
; GFX11-NEXT:  .LBB29_13: ; %frem.loop_body54
; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT:    v_mov_b32_e32 v6, v3
; GFX11-NEXT:    s_add_i32 s4, s4, -12
; GFX11-NEXT:    s_cmp_gt_i32 s4, 12
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_mul_f32_e32 v3, v6, v4
; GFX11-NEXT:    v_rndne_f32_e32 v3, v3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v3, -v3, v2, v6
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX11-NEXT:    v_add_f32_e32 v5, v3, v2
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX11-NEXT:    v_ldexp_f32 v3, v3, 12
; GFX11-NEXT:    s_cbranch_scc1 .LBB29_13
; GFX11-NEXT:  ; %bb.14:
; GFX11-NEXT:    v_mov_b32_e32 v5, s4
; GFX11-NEXT:    s_branch .LBB29_16
; GFX11-NEXT:  .LBB29_15:
; GFX11-NEXT:    v_mov_b32_e32 v6, v3
; GFX11-NEXT:  .LBB29_16: ; %frem.loop_exit55
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_add_nc_u32_e32 v3, -11, v5
; GFX11-NEXT:    v_ldexp_f32 v3, v6, v3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_mul_f32_e32 v4, v3, v4
; GFX11-NEXT:    v_rndne_f32_e32 v4, v4
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v3, -v4, v2, v3
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX11-NEXT:    v_add_f32_e32 v2, v3, v2
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX11-NEXT:    v_ldexp_f32 v1, v2, v1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_bfi_b32 v1, 0x7fffffff, v1, s1
; GFX11-NEXT:    v_cmp_gt_f32_e64 vcc_lo, |s2|, |s18|
; GFX11-NEXT:    s_cbranch_vccz .LBB29_7
; GFX11-NEXT:  .LBB29_17: ; %frem.compute15
; GFX11-NEXT:    v_frexp_mant_f32_e64 v3, |s18|
; GFX11-NEXT:    v_frexp_mant_f32_e64 v2, |s2|
; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v5, s2
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_ldexp_f32 v3, v3, 1
; GFX11-NEXT:    v_ldexp_f32 v4, v2, 12
; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v2, s18
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_readfirstlane_b32 s4, v5
; GFX11-NEXT:    v_div_scale_f32 v7, null, v3, v3, 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_readfirstlane_b32 s5, v2
; GFX11-NEXT:    v_add_nc_u32_e32 v2, -1, v2
; GFX11-NEXT:    v_rcp_f32_e32 v8, v7
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_not_b32_e32 v6, v2
; GFX11-NEXT:    v_add_nc_u32_e32 v6, v6, v5
; GFX11-NEXT:    v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX11-NEXT:    s_denorm_mode 15
; GFX11-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fmac_f32_e32 v8, v9, v8
; GFX11-NEXT:    v_mul_f32_e32 v9, v5, v8
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v10, -v7, v9, v5
; GFX11-NEXT:    v_fmac_f32_e32 v9, v10, v8
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v5, -v7, v9, v5
; GFX11-NEXT:    s_denorm_mode 12
; GFX11-NEXT:    v_div_fmas_f32 v5, v5, v8, v9
; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v6
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
; GFX11-NEXT:    s_cbranch_vccnz .LBB29_21
; GFX11-NEXT:  ; %bb.18: ; %frem.loop_body23.preheader
; GFX11-NEXT:    s_sub_i32 s4, s4, s5
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_add_i32 s4, s4, 12
; GFX11-NEXT:  .LBB29_19: ; %frem.loop_body23
; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT:    v_mov_b32_e32 v7, v4
; GFX11-NEXT:    s_add_i32 s4, s4, -12
; GFX11-NEXT:    s_cmp_gt_i32 s4, 12
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_mul_f32_e32 v4, v7, v5
; GFX11-NEXT:    v_rndne_f32_e32 v4, v4
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v4, -v4, v3, v7
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX11-NEXT:    v_add_f32_e32 v6, v4, v3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX11-NEXT:    v_ldexp_f32 v4, v4, 12
; GFX11-NEXT:    s_cbranch_scc1 .LBB29_19
; GFX11-NEXT:  ; %bb.20:
; GFX11-NEXT:    v_mov_b32_e32 v6, s4
; GFX11-NEXT:    s_branch .LBB29_22
; GFX11-NEXT:  .LBB29_21:
; GFX11-NEXT:    v_mov_b32_e32 v7, v4
; GFX11-NEXT:  .LBB29_22: ; %frem.loop_exit24
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_add_nc_u32_e32 v4, -11, v6
; GFX11-NEXT:    v_ldexp_f32 v4, v7, v4
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_mul_f32_e32 v5, v4, v5
; GFX11-NEXT:    v_rndne_f32_e32 v5, v5
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v4, -v5, v3, v4
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX11-NEXT:    v_add_f32_e32 v3, v4, v3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX11-NEXT:    v_ldexp_f32 v2, v3, v2
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_bfi_b32 v2, 0x7fffffff, v2, s2
; GFX11-NEXT:    v_cmp_gt_f32_e64 vcc_lo, |s3|, |s19|
; GFX11-NEXT:    s_cbranch_vccz .LBB29_8
; GFX11-NEXT:  .LBB29_23: ; %frem.compute
; GFX11-NEXT:    v_frexp_mant_f32_e64 v4, |s19|
; GFX11-NEXT:    v_frexp_mant_f32_e64 v3, |s3|
; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v6, s3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_ldexp_f32 v4, v4, 1
; GFX11-NEXT:    v_ldexp_f32 v5, v3, 12
; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v3, s19
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_readfirstlane_b32 s4, v6
; GFX11-NEXT:    v_div_scale_f32 v8, null, v4, v4, 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_readfirstlane_b32 s5, v3
; GFX11-NEXT:    v_add_nc_u32_e32 v3, -1, v3
; GFX11-NEXT:    v_rcp_f32_e32 v9, v8
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_not_b32_e32 v7, v3
; GFX11-NEXT:    v_add_nc_u32_e32 v7, v7, v6
; GFX11-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v4, 1.0
; GFX11-NEXT:    s_denorm_mode 15
; GFX11-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fmac_f32_e32 v9, v10, v9
; GFX11-NEXT:    v_mul_f32_e32 v10, v6, v9
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v11, -v8, v10, v6
; GFX11-NEXT:    v_fmac_f32_e32 v10, v11, v9
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v6, -v8, v10, v6
; GFX11-NEXT:    s_denorm_mode 12
; GFX11-NEXT:    v_div_fmas_f32 v6, v6, v9, v10
; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v7
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT:    v_div_fixup_f32 v6, v6, v4, 1.0
; GFX11-NEXT:    s_cbranch_vccnz .LBB29_27
; GFX11-NEXT:  ; %bb.24: ; %frem.loop_body.preheader
; GFX11-NEXT:    s_sub_i32 s4, s4, s5
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_add_i32 s4, s4, 12
; GFX11-NEXT:  .LBB29_25: ; %frem.loop_body
; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT:    v_mov_b32_e32 v8, v5
; GFX11-NEXT:    s_add_i32 s4, s4, -12
; GFX11-NEXT:    s_cmp_gt_i32 s4, 12
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_mul_f32_e32 v5, v8, v6
; GFX11-NEXT:    v_rndne_f32_e32 v5, v5
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v5, -v5, v4, v8
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX11-NEXT:    v_add_f32_e32 v7, v5, v4
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX11-NEXT:    v_ldexp_f32 v5, v5, 12
; GFX11-NEXT:    s_cbranch_scc1 .LBB29_25
; GFX11-NEXT:  ; %bb.26:
; GFX11-NEXT:    v_mov_b32_e32 v7, s4
; GFX11-NEXT:    s_branch .LBB29_28
; GFX11-NEXT:  .LBB29_27:
; GFX11-NEXT:    v_mov_b32_e32 v8, v5
; GFX11-NEXT:  .LBB29_28: ; %frem.loop_exit
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_add_nc_u32_e32 v5, -11, v7
; GFX11-NEXT:    v_ldexp_f32 v5, v8, v5
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_mul_f32_e32 v6, v5, v6
; GFX11-NEXT:    v_rndne_f32_e32 v6, v6
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f32 v5, -v6, v4, v5
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX11-NEXT:    v_add_f32_e32 v4, v5, v4
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc_lo
; GFX11-NEXT:    v_ldexp_f32 v3, v4, v3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_bfi_b32 v3, 0x7fffffff, v3, s3
; GFX11-NEXT:  .LBB29_29:
; GFX11-NEXT:    v_cmp_lg_f32_e64 s4, s16, 0
; GFX11-NEXT:    v_cmp_nge_f32_e64 s0, |s0|, 0x7f800000
; GFX11-NEXT:    v_cmp_nge_f32_e64 s1, |s1|, 0x7f800000
; GFX11-NEXT:    s_and_b32 vcc_lo, s0, s4
; GFX11-NEXT:    v_cmp_lg_f32_e64 s0, s17, 0
; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
; GFX11-NEXT:    s_and_b32 vcc_lo, s1, s0
; GFX11-NEXT:    v_cmp_lg_f32_e64 s0, s18, 0
; GFX11-NEXT:    v_cmp_nge_f32_e64 s1, |s2|, 0x7f800000
; GFX11-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v1, vcc_lo
; GFX11-NEXT:    s_and_b32 vcc_lo, s1, s0
; GFX11-NEXT:    v_cmp_lg_f32_e64 s0, s19, 0
; GFX11-NEXT:    v_cmp_nge_f32_e64 s1, |s3|, 0x7f800000
; GFX11-NEXT:    v_cndmask_b32_e32 v2, 0x7fc00000, v2, vcc_lo
; GFX11-NEXT:    s_and_b32 vcc_lo, s1, s0
; GFX11-NEXT:    v_cndmask_b32_e32 v3, 0x7fc00000, v3, vcc_lo
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-LABEL: frem_v4f32_uniform:
; GFX1150:       ; %bb.0:
; GFX1150-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-NEXT:    s_and_b32 s4, s0, 0x7fffffff
; GFX1150-NEXT:    s_and_b32 s5, s16, 0x7fffffff
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_cmp_gt_f32 s4, s5
; GFX1150-NEXT:    s_cbranch_scc0 .LBB29_5
; GFX1150-NEXT:  ; %bb.1: ; %frem.compute77
; GFX1150-NEXT:    v_frexp_mant_f32_e64 v1, |s16|
; GFX1150-NEXT:    v_frexp_mant_f32_e64 v0, |s0|
; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v3, s0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX1150-NEXT:    v_ldexp_f32 v2, v0, 12
; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v0, s16
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1150-NEXT:    v_readfirstlane_b32 s5, v3
; GFX1150-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_readfirstlane_b32 s6, v0
; GFX1150-NEXT:    v_add_nc_u32_e32 v0, -1, v0
; GFX1150-NEXT:    v_rcp_f32_e32 v6, v5
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_not_b32_e32 v4, v0
; GFX1150-NEXT:    v_add_nc_u32_e32 v4, v4, v3
; GFX1150-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX1150-NEXT:    s_denorm_mode 15
; GFX1150-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
; GFX1150-NEXT:    v_fmac_f32_e32 v6, v7, v6
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f32_e32 v7, v3, v6
; GFX1150-NEXT:    v_fma_f32 v8, -v5, v7, v3
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fmac_f32_e32 v7, v8, v6
; GFX1150-NEXT:    v_fma_f32 v3, -v5, v7, v3
; GFX1150-NEXT:    s_denorm_mode 12
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
; GFX1150-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v4
; GFX1150-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX1150-NEXT:    s_cbranch_vccnz .LBB29_6
; GFX1150-NEXT:  ; %bb.2: ; %frem.loop_body85.preheader
; GFX1150-NEXT:    s_sub_i32 s5, s5, s6
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_add_i32 s5, s5, 12
; GFX1150-NEXT:  .LBB29_3: ; %frem.loop_body85
; GFX1150-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT:    v_mov_b32_e32 v5, v2
; GFX1150-NEXT:    s_add_i32 s5, s5, -12
; GFX1150-NEXT:    s_cmp_gt_i32 s5, 12
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f32_e32 v2, v5, v3
; GFX1150-NEXT:    v_rndne_f32_e32 v2, v2
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_xor_b32_e32 v2, 0x80000000, v2
; GFX1150-NEXT:    v_fma_f32 v2, v2, v1, v5
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1150-NEXT:    v_add_f32_e32 v4, v2, v1
; GFX1150-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f32 v2, v2, 12
; GFX1150-NEXT:    s_cbranch_scc1 .LBB29_3
; GFX1150-NEXT:  ; %bb.4:
; GFX1150-NEXT:    v_mov_b32_e32 v4, s5
; GFX1150-NEXT:    s_branch .LBB29_7
; GFX1150-NEXT:  .LBB29_5: ; %frem.else78
; GFX1150-NEXT:    s_and_b32 s6, 0x80000000, s0
; GFX1150-NEXT:    s_cmp_eq_f32 s4, s5
; GFX1150-NEXT:    v_mov_b32_e32 v0, s6
; GFX1150-NEXT:    s_cselect_b32 vcc_lo, -1, 0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_cndmask_b32_e32 v0, s0, v0, vcc_lo
; GFX1150-NEXT:    s_branch .LBB29_8
; GFX1150-NEXT:  .LBB29_6:
; GFX1150-NEXT:    v_mov_b32_e32 v5, v2
; GFX1150-NEXT:  .LBB29_7: ; %frem.loop_exit86
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_add_nc_u32_e32 v2, -11, v4
; GFX1150-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX1150-NEXT:    v_rndne_f32_e32 v3, v3
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
; GFX1150-NEXT:    v_fmac_f32_e32 v2, v3, v1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1150-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX1150-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX1150-NEXT:    v_bfi_b32 v0, 0x7fffffff, v0, s0
; GFX1150-NEXT:  .LBB29_8:
; GFX1150-NEXT:    s_and_b32 s0, s1, 0x7fffffff
; GFX1150-NEXT:    s_and_b32 s5, s17, 0x7fffffff
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_cmp_gt_f32 s0, s5
; GFX1150-NEXT:    s_cbranch_scc0 .LBB29_13
; GFX1150-NEXT:  ; %bb.9: ; %frem.compute46
; GFX1150-NEXT:    v_frexp_mant_f32_e64 v2, |s17|
; GFX1150-NEXT:    v_frexp_mant_f32_e64 v1, |s1|
; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v4, s1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_ldexp_f32 v2, v2, 1
; GFX1150-NEXT:    v_ldexp_f32 v3, v1, 12
; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v1, s17
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1150-NEXT:    v_readfirstlane_b32 s5, v4
; GFX1150-NEXT:    v_div_scale_f32 v6, null, v2, v2, 1.0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_readfirstlane_b32 s6, v1
; GFX1150-NEXT:    v_add_nc_u32_e32 v1, -1, v1
; GFX1150-NEXT:    v_rcp_f32_e32 v7, v6
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_not_b32_e32 v5, v1
; GFX1150-NEXT:    v_add_nc_u32_e32 v5, v5, v4
; GFX1150-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
; GFX1150-NEXT:    s_denorm_mode 15
; GFX1150-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
; GFX1150-NEXT:    v_fmac_f32_e32 v7, v8, v7
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f32_e32 v8, v4, v7
; GFX1150-NEXT:    v_fma_f32 v9, -v6, v8, v4
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fmac_f32_e32 v8, v9, v7
; GFX1150-NEXT:    v_fma_f32 v4, -v6, v8, v4
; GFX1150-NEXT:    s_denorm_mode 12
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
; GFX1150-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v5
; GFX1150-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; GFX1150-NEXT:    s_cbranch_vccnz .LBB29_14
; GFX1150-NEXT:  ; %bb.10: ; %frem.loop_body54.preheader
; GFX1150-NEXT:    s_sub_i32 s5, s5, s6
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_add_i32 s5, s5, 12
; GFX1150-NEXT:  .LBB29_11: ; %frem.loop_body54
; GFX1150-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT:    v_mov_b32_e32 v6, v3
; GFX1150-NEXT:    s_add_i32 s5, s5, -12
; GFX1150-NEXT:    s_cmp_gt_i32 s5, 12
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f32_e32 v3, v6, v4
; GFX1150-NEXT:    v_rndne_f32_e32 v3, v3
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
; GFX1150-NEXT:    v_fma_f32 v3, v3, v2, v6
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1150-NEXT:    v_add_f32_e32 v5, v3, v2
; GFX1150-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f32 v3, v3, 12
; GFX1150-NEXT:    s_cbranch_scc1 .LBB29_11
; GFX1150-NEXT:  ; %bb.12:
; GFX1150-NEXT:    v_mov_b32_e32 v5, s5
; GFX1150-NEXT:    s_branch .LBB29_15
; GFX1150-NEXT:  .LBB29_13: ; %frem.else47
; GFX1150-NEXT:    s_and_b32 s6, 0x80000000, s1
; GFX1150-NEXT:    s_cmp_eq_f32 s0, s5
; GFX1150-NEXT:    v_mov_b32_e32 v1, s6
; GFX1150-NEXT:    s_cselect_b32 vcc_lo, -1, 0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_cndmask_b32_e32 v1, s1, v1, vcc_lo
; GFX1150-NEXT:    s_branch .LBB29_16
; GFX1150-NEXT:  .LBB29_14:
; GFX1150-NEXT:    v_mov_b32_e32 v6, v3
; GFX1150-NEXT:  .LBB29_15: ; %frem.loop_exit55
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_add_nc_u32_e32 v3, -11, v5
; GFX1150-NEXT:    v_ldexp_f32 v3, v6, v3
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f32_e32 v4, v3, v4
; GFX1150-NEXT:    v_rndne_f32_e32 v4, v4
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
; GFX1150-NEXT:    v_fmac_f32_e32 v3, v4, v2
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1150-NEXT:    v_add_f32_e32 v2, v3, v2
; GFX1150-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f32 v1, v2, v1
; GFX1150-NEXT:    v_bfi_b32 v1, 0x7fffffff, v1, s1
; GFX1150-NEXT:  .LBB29_16:
; GFX1150-NEXT:    s_and_b32 s1, s2, 0x7fffffff
; GFX1150-NEXT:    s_and_b32 s5, s18, 0x7fffffff
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_cmp_gt_f32 s1, s5
; GFX1150-NEXT:    s_cbranch_scc0 .LBB29_21
; GFX1150-NEXT:  ; %bb.17: ; %frem.compute15
; GFX1150-NEXT:    v_frexp_mant_f32_e64 v3, |s18|
; GFX1150-NEXT:    v_frexp_mant_f32_e64 v2, |s2|
; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v5, s2
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_ldexp_f32 v3, v3, 1
; GFX1150-NEXT:    v_ldexp_f32 v4, v2, 12
; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v2, s18
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1150-NEXT:    v_readfirstlane_b32 s5, v5
; GFX1150-NEXT:    v_div_scale_f32 v7, null, v3, v3, 1.0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_readfirstlane_b32 s6, v2
; GFX1150-NEXT:    v_add_nc_u32_e32 v2, -1, v2
; GFX1150-NEXT:    v_rcp_f32_e32 v8, v7
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_not_b32_e32 v6, v2
; GFX1150-NEXT:    v_add_nc_u32_e32 v6, v6, v5
; GFX1150-NEXT:    v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX1150-NEXT:    s_denorm_mode 15
; GFX1150-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
; GFX1150-NEXT:    v_fmac_f32_e32 v8, v9, v8
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f32_e32 v9, v5, v8
; GFX1150-NEXT:    v_fma_f32 v10, -v7, v9, v5
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fmac_f32_e32 v9, v10, v8
; GFX1150-NEXT:    v_fma_f32 v5, -v7, v9, v5
; GFX1150-NEXT:    s_denorm_mode 12
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-NEXT:    v_div_fmas_f32 v5, v5, v8, v9
; GFX1150-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v6
; GFX1150-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
; GFX1150-NEXT:    s_cbranch_vccnz .LBB29_22
; GFX1150-NEXT:  ; %bb.18: ; %frem.loop_body23.preheader
; GFX1150-NEXT:    s_sub_i32 s5, s5, s6
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_add_i32 s5, s5, 12
; GFX1150-NEXT:  .LBB29_19: ; %frem.loop_body23
; GFX1150-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT:    v_mov_b32_e32 v7, v4
; GFX1150-NEXT:    s_add_i32 s5, s5, -12
; GFX1150-NEXT:    s_cmp_gt_i32 s5, 12
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f32_e32 v4, v7, v5
; GFX1150-NEXT:    v_rndne_f32_e32 v4, v4
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
; GFX1150-NEXT:    v_fma_f32 v4, v4, v3, v7
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX1150-NEXT:    v_add_f32_e32 v6, v4, v3
; GFX1150-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f32 v4, v4, 12
; GFX1150-NEXT:    s_cbranch_scc1 .LBB29_19
; GFX1150-NEXT:  ; %bb.20:
; GFX1150-NEXT:    v_mov_b32_e32 v6, s5
; GFX1150-NEXT:    s_branch .LBB29_23
; GFX1150-NEXT:  .LBB29_21: ; %frem.else16
; GFX1150-NEXT:    s_and_b32 s6, 0x80000000, s2
; GFX1150-NEXT:    s_cmp_eq_f32 s1, s5
; GFX1150-NEXT:    v_mov_b32_e32 v2, s6
; GFX1150-NEXT:    s_cselect_b32 vcc_lo, -1, 0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_cndmask_b32_e32 v2, s2, v2, vcc_lo
; GFX1150-NEXT:    s_branch .LBB29_24
; GFX1150-NEXT:  .LBB29_22:
; GFX1150-NEXT:    v_mov_b32_e32 v7, v4
; GFX1150-NEXT:  .LBB29_23: ; %frem.loop_exit24
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_add_nc_u32_e32 v4, -11, v6
; GFX1150-NEXT:    v_ldexp_f32 v4, v7, v4
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f32_e32 v5, v4, v5
; GFX1150-NEXT:    v_rndne_f32_e32 v5, v5
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_xor_b32_e32 v5, 0x80000000, v5
; GFX1150-NEXT:    v_fmac_f32_e32 v4, v5, v3
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX1150-NEXT:    v_add_f32_e32 v3, v4, v3
; GFX1150-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f32 v2, v3, v2
; GFX1150-NEXT:    v_bfi_b32 v2, 0x7fffffff, v2, s2
; GFX1150-NEXT:  .LBB29_24:
; GFX1150-NEXT:    s_and_b32 s2, s3, 0x7fffffff
; GFX1150-NEXT:    s_and_b32 s5, s19, 0x7fffffff
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_cmp_gt_f32 s2, s5
; GFX1150-NEXT:    s_cbranch_scc0 .LBB29_29
; GFX1150-NEXT:  ; %bb.25: ; %frem.compute
; GFX1150-NEXT:    v_frexp_mant_f32_e64 v4, |s19|
; GFX1150-NEXT:    v_frexp_mant_f32_e64 v3, |s3|
; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v6, s3
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_ldexp_f32 v4, v4, 1
; GFX1150-NEXT:    v_ldexp_f32 v5, v3, 12
; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v3, s19
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1150-NEXT:    v_readfirstlane_b32 s5, v6
; GFX1150-NEXT:    v_div_scale_f32 v8, null, v4, v4, 1.0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1150-NEXT:    v_readfirstlane_b32 s6, v3
; GFX1150-NEXT:    v_add_nc_u32_e32 v3, -1, v3
; GFX1150-NEXT:    v_rcp_f32_e32 v9, v8
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_not_b32_e32 v7, v3
; GFX1150-NEXT:    v_add_nc_u32_e32 v7, v7, v6
; GFX1150-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v4, 1.0
; GFX1150-NEXT:    s_denorm_mode 15
; GFX1150-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
; GFX1150-NEXT:    v_fmac_f32_e32 v9, v10, v9
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f32_e32 v10, v6, v9
; GFX1150-NEXT:    v_fma_f32 v11, -v8, v10, v6
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fmac_f32_e32 v10, v11, v9
; GFX1150-NEXT:    v_fma_f32 v6, -v8, v10, v6
; GFX1150-NEXT:    s_denorm_mode 12
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-NEXT:    v_div_fmas_f32 v6, v6, v9, v10
; GFX1150-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v7
; GFX1150-NEXT:    v_div_fixup_f32 v6, v6, v4, 1.0
; GFX1150-NEXT:    s_cbranch_vccnz .LBB29_30
; GFX1150-NEXT:  ; %bb.26: ; %frem.loop_body.preheader
; GFX1150-NEXT:    s_sub_i32 s5, s5, s6
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_add_i32 s5, s5, 12
; GFX1150-NEXT:  .LBB29_27: ; %frem.loop_body
; GFX1150-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT:    v_mov_b32_e32 v8, v5
; GFX1150-NEXT:    s_add_i32 s5, s5, -12
; GFX1150-NEXT:    s_cmp_gt_i32 s5, 12
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f32_e32 v5, v8, v6
; GFX1150-NEXT:    v_rndne_f32_e32 v5, v5
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_xor_b32_e32 v5, 0x80000000, v5
; GFX1150-NEXT:    v_fma_f32 v5, v5, v4, v8
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX1150-NEXT:    v_add_f32_e32 v7, v5, v4
; GFX1150-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f32 v5, v5, 12
; GFX1150-NEXT:    s_cbranch_scc1 .LBB29_27
; GFX1150-NEXT:  ; %bb.28:
; GFX1150-NEXT:    v_mov_b32_e32 v7, s5
; GFX1150-NEXT:    s_branch .LBB29_31
; GFX1150-NEXT:  .LBB29_29: ; %frem.else
; GFX1150-NEXT:    s_and_b32 s6, 0x80000000, s3
; GFX1150-NEXT:    s_cmp_eq_f32 s2, s5
; GFX1150-NEXT:    v_mov_b32_e32 v3, s6
; GFX1150-NEXT:    s_cselect_b32 vcc_lo, -1, 0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_cndmask_b32_e32 v3, s3, v3, vcc_lo
; GFX1150-NEXT:    s_branch .LBB29_32
; GFX1150-NEXT:  .LBB29_30:
; GFX1150-NEXT:    v_mov_b32_e32 v8, v5
; GFX1150-NEXT:  .LBB29_31: ; %frem.loop_exit
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_add_nc_u32_e32 v5, -11, v7
; GFX1150-NEXT:    v_ldexp_f32 v5, v8, v5
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f32_e32 v6, v5, v6
; GFX1150-NEXT:    v_rndne_f32_e32 v6, v6
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_xor_b32_e32 v6, 0x80000000, v6
; GFX1150-NEXT:    v_fmac_f32_e32 v5, v6, v4
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX1150-NEXT:    v_add_f32_e32 v4, v5, v4
; GFX1150-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc_lo
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f32 v3, v4, v3
; GFX1150-NEXT:    v_bfi_b32 v3, 0x7fffffff, v3, s3
; GFX1150-NEXT:  .LBB29_32:
; GFX1150-NEXT:    s_cmp_lg_f32 s16, 0
; GFX1150-NEXT:    s_cselect_b32 s3, -1, 0
; GFX1150-NEXT:    s_cmp_nge_f32 s4, 0x7f800000
; GFX1150-NEXT:    s_cselect_b32 s4, -1, 0
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_and_b32 vcc_lo, s4, s3
; GFX1150-NEXT:    s_cmp_lg_f32 s17, 0
; GFX1150-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
; GFX1150-NEXT:    s_cselect_b32 s3, -1, 0
; GFX1150-NEXT:    s_cmp_nge_f32 s0, 0x7f800000
; GFX1150-NEXT:    s_cselect_b32 s0, -1, 0
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_and_b32 vcc_lo, s0, s3
; GFX1150-NEXT:    s_cmp_lg_f32 s18, 0
; GFX1150-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v1, vcc_lo
; GFX1150-NEXT:    s_cselect_b32 s0, -1, 0
; GFX1150-NEXT:    s_cmp_nge_f32 s1, 0x7f800000
; GFX1150-NEXT:    s_cselect_b32 s1, -1, 0
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_and_b32 vcc_lo, s1, s0
; GFX1150-NEXT:    s_cmp_lg_f32 s19, 0
; GFX1150-NEXT:    v_cndmask_b32_e32 v2, 0x7fc00000, v2, vcc_lo
; GFX1150-NEXT:    s_cselect_b32 s0, -1, 0
; GFX1150-NEXT:    s_cmp_nge_f32 s2, 0x7f800000
; GFX1150-NEXT:    s_cselect_b32 s1, -1, 0
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_and_b32 vcc_lo, s1, s0
; GFX1150-NEXT:    v_cndmask_b32_e32 v3, 0x7fc00000, v3, vcc_lo
; GFX1150-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: frem_v4f32_uniform:
; GFX1200:       ; %bb.0:
; GFX1200-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT:    s_wait_expcnt 0x0
; GFX1200-NEXT:    s_wait_samplecnt 0x0
; GFX1200-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-NEXT:    s_wait_kmcnt 0x0
; GFX1200-NEXT:    s_and_b32 s4, s0, 0x7fffffff
; GFX1200-NEXT:    s_and_b32 s5, s16, 0x7fffffff
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_cmp_gt_f32 s4, s5
; GFX1200-NEXT:    s_cbranch_scc0 .LBB29_5
; GFX1200-NEXT:  ; %bb.1: ; %frem.compute77
; GFX1200-NEXT:    v_frexp_mant_f32_e64 v1, |s16|
; GFX1200-NEXT:    v_frexp_mant_f32_e64 v0, |s0|
; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v3, s0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT:    v_ldexp_f32 v1, v1, 1
; GFX1200-NEXT:    v_ldexp_f32 v2, v0, 12
; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v0, s16
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-NEXT:    v_readfirstlane_b32 s5, v3
; GFX1200-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1200-NEXT:    v_readfirstlane_b32 s6, v0
; GFX1200-NEXT:    v_add_nc_u32_e32 v0, -1, v0
; GFX1200-NEXT:    v_rcp_f32_e32 v6, v5
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_not_b32_e32 v4, v0
; GFX1200-NEXT:    v_add_nc_u32_e32 v4, v4, v3
; GFX1200-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX1200-NEXT:    s_denorm_mode 15
; GFX1200-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
; GFX1200-NEXT:    v_fmac_f32_e32 v6, v7, v6
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_mul_f32_e32 v7, v3, v6
; GFX1200-NEXT:    v_fma_f32 v8, -v5, v7, v3
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fmac_f32_e32 v7, v8, v6
; GFX1200-NEXT:    v_fma_f32 v3, -v5, v7, v3
; GFX1200-NEXT:    s_denorm_mode 12
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
; GFX1200-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v4
; GFX1200-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
; GFX1200-NEXT:    s_cbranch_vccnz .LBB29_6
; GFX1200-NEXT:  ; %bb.2: ; %frem.loop_body85.preheader
; GFX1200-NEXT:    s_sub_co_i32 s5, s5, s6
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_add_co_i32 s5, s5, 12
; GFX1200-NEXT:  .LBB29_3: ; %frem.loop_body85
; GFX1200-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_mov_b32_e32 v5, v2
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_add_co_i32 s5, s5, -12
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_cmp_gt_i32 s5, 12
; GFX1200-NEXT:    v_mul_f32_e32 v2, v5, v3
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_rndne_f32_e32 v2, v2
; GFX1200-NEXT:    v_xor_b32_e32 v2, 0x80000000, v2
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v2, v2, v1, v5
; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1200-NEXT:    v_add_f32_e32 v4, v2, v1
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1200-NEXT:    v_ldexp_f32 v2, v2, 12
; GFX1200-NEXT:    s_cbranch_scc1 .LBB29_3
; GFX1200-NEXT:  ; %bb.4:
; GFX1200-NEXT:    v_mov_b32_e32 v4, s5
; GFX1200-NEXT:    s_branch .LBB29_7
; GFX1200-NEXT:  .LBB29_5: ; %frem.else78
; GFX1200-NEXT:    s_and_b32 s6, 0x80000000, s0
; GFX1200-NEXT:    s_cmp_eq_f32 s4, s5
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_cselect_b32 s0, s6, s0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    v_mov_b32_e32 v0, s0
; GFX1200-NEXT:    s_branch .LBB29_8
; GFX1200-NEXT:  .LBB29_6:
; GFX1200-NEXT:    v_mov_b32_e32 v5, v2
; GFX1200-NEXT:  .LBB29_7: ; %frem.loop_exit86
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_add_nc_u32_e32 v2, -11, v4
; GFX1200-NEXT:    v_ldexp_f32 v2, v5, v2
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_mul_f32_e32 v3, v2, v3
; GFX1200-NEXT:    v_rndne_f32_e32 v3, v3
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
; GFX1200-NEXT:    v_fmac_f32_e32 v2, v3, v1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1200-NEXT:    v_add_f32_e32 v1, v2, v1
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_ldexp_f32 v0, v1, v0
; GFX1200-NEXT:    v_bfi_b32 v0, 0x7fffffff, v0, s0
; GFX1200-NEXT:  .LBB29_8:
; GFX1200-NEXT:    s_and_b32 s0, s1, 0x7fffffff
; GFX1200-NEXT:    s_and_b32 s5, s17, 0x7fffffff
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_cmp_gt_f32 s0, s5
; GFX1200-NEXT:    s_cbranch_scc0 .LBB29_13
; GFX1200-NEXT:  ; %bb.9: ; %frem.compute46
; GFX1200-NEXT:    v_frexp_mant_f32_e64 v2, |s17|
; GFX1200-NEXT:    v_frexp_mant_f32_e64 v1, |s1|
; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v4, s1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT:    v_ldexp_f32 v2, v2, 1
; GFX1200-NEXT:    v_ldexp_f32 v3, v1, 12
; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v1, s17
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-NEXT:    v_readfirstlane_b32 s5, v4
; GFX1200-NEXT:    v_div_scale_f32 v6, null, v2, v2, 1.0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1200-NEXT:    v_readfirstlane_b32 s6, v1
; GFX1200-NEXT:    v_add_nc_u32_e32 v1, -1, v1
; GFX1200-NEXT:    v_rcp_f32_e32 v7, v6
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_not_b32_e32 v5, v1
; GFX1200-NEXT:    v_add_nc_u32_e32 v5, v5, v4
; GFX1200-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
; GFX1200-NEXT:    s_denorm_mode 15
; GFX1200-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
; GFX1200-NEXT:    v_fmac_f32_e32 v7, v8, v7
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_mul_f32_e32 v8, v4, v7
; GFX1200-NEXT:    v_fma_f32 v9, -v6, v8, v4
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fmac_f32_e32 v8, v9, v7
; GFX1200-NEXT:    v_fma_f32 v4, -v6, v8, v4
; GFX1200-NEXT:    s_denorm_mode 12
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
; GFX1200-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v5
; GFX1200-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
; GFX1200-NEXT:    s_cbranch_vccnz .LBB29_14
; GFX1200-NEXT:  ; %bb.10: ; %frem.loop_body54.preheader
; GFX1200-NEXT:    s_sub_co_i32 s5, s5, s6
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_add_co_i32 s5, s5, 12
; GFX1200-NEXT:  .LBB29_11: ; %frem.loop_body54
; GFX1200-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_mov_b32_e32 v6, v3
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_add_co_i32 s5, s5, -12
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_cmp_gt_i32 s5, 12
; GFX1200-NEXT:    v_mul_f32_e32 v3, v6, v4
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_rndne_f32_e32 v3, v3
; GFX1200-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v3, v3, v2, v6
; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1200-NEXT:    v_add_f32_e32 v5, v3, v2
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1200-NEXT:    v_ldexp_f32 v3, v3, 12
; GFX1200-NEXT:    s_cbranch_scc1 .LBB29_11
; GFX1200-NEXT:  ; %bb.12:
; GFX1200-NEXT:    v_mov_b32_e32 v5, s5
; GFX1200-NEXT:    s_branch .LBB29_15
; GFX1200-NEXT:  .LBB29_13: ; %frem.else47
; GFX1200-NEXT:    s_and_b32 s6, 0x80000000, s1
; GFX1200-NEXT:    s_cmp_eq_f32 s0, s5
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_cselect_b32 s1, s6, s1
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    v_mov_b32_e32 v1, s1
; GFX1200-NEXT:    s_branch .LBB29_16
; GFX1200-NEXT:  .LBB29_14:
; GFX1200-NEXT:    v_mov_b32_e32 v6, v3
; GFX1200-NEXT:  .LBB29_15: ; %frem.loop_exit55
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_add_nc_u32_e32 v3, -11, v5
; GFX1200-NEXT:    v_ldexp_f32 v3, v6, v3
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_mul_f32_e32 v4, v3, v4
; GFX1200-NEXT:    v_rndne_f32_e32 v4, v4
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
; GFX1200-NEXT:    v_fmac_f32_e32 v3, v4, v2
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1200-NEXT:    v_add_f32_e32 v2, v3, v2
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_ldexp_f32 v1, v2, v1
; GFX1200-NEXT:    v_bfi_b32 v1, 0x7fffffff, v1, s1
; GFX1200-NEXT:  .LBB29_16:
; GFX1200-NEXT:    s_and_b32 s1, s2, 0x7fffffff
; GFX1200-NEXT:    s_and_b32 s5, s18, 0x7fffffff
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_cmp_gt_f32 s1, s5
; GFX1200-NEXT:    s_cbranch_scc0 .LBB29_21
; GFX1200-NEXT:  ; %bb.17: ; %frem.compute15
; GFX1200-NEXT:    v_frexp_mant_f32_e64 v3, |s18|
; GFX1200-NEXT:    v_frexp_mant_f32_e64 v2, |s2|
; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v5, s2
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT:    v_ldexp_f32 v3, v3, 1
; GFX1200-NEXT:    v_ldexp_f32 v4, v2, 12
; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v2, s18
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-NEXT:    v_readfirstlane_b32 s5, v5
; GFX1200-NEXT:    v_div_scale_f32 v7, null, v3, v3, 1.0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1200-NEXT:    v_readfirstlane_b32 s6, v2
; GFX1200-NEXT:    v_add_nc_u32_e32 v2, -1, v2
; GFX1200-NEXT:    v_rcp_f32_e32 v8, v7
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_not_b32_e32 v6, v2
; GFX1200-NEXT:    v_add_nc_u32_e32 v6, v6, v5
; GFX1200-NEXT:    v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX1200-NEXT:    s_denorm_mode 15
; GFX1200-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
; GFX1200-NEXT:    v_fmac_f32_e32 v8, v9, v8
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_mul_f32_e32 v9, v5, v8
; GFX1200-NEXT:    v_fma_f32 v10, -v7, v9, v5
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fmac_f32_e32 v9, v10, v8
; GFX1200-NEXT:    v_fma_f32 v5, -v7, v9, v5
; GFX1200-NEXT:    s_denorm_mode 12
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT:    v_div_fmas_f32 v5, v5, v8, v9
; GFX1200-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v6
; GFX1200-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
; GFX1200-NEXT:    s_cbranch_vccnz .LBB29_22
; GFX1200-NEXT:  ; %bb.18: ; %frem.loop_body23.preheader
; GFX1200-NEXT:    s_sub_co_i32 s5, s5, s6
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_add_co_i32 s5, s5, 12
; GFX1200-NEXT:  .LBB29_19: ; %frem.loop_body23
; GFX1200-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_mov_b32_e32 v7, v4
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_add_co_i32 s5, s5, -12
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_cmp_gt_i32 s5, 12
; GFX1200-NEXT:    v_mul_f32_e32 v4, v7, v5
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_rndne_f32_e32 v4, v4
; GFX1200-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v4, v4, v3, v7
; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX1200-NEXT:    v_add_f32_e32 v6, v4, v3
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX1200-NEXT:    v_ldexp_f32 v4, v4, 12
; GFX1200-NEXT:    s_cbranch_scc1 .LBB29_19
; GFX1200-NEXT:  ; %bb.20:
; GFX1200-NEXT:    v_mov_b32_e32 v6, s5
; GFX1200-NEXT:    s_branch .LBB29_23
; GFX1200-NEXT:  .LBB29_21: ; %frem.else16
; GFX1200-NEXT:    s_and_b32 s6, 0x80000000, s2
; GFX1200-NEXT:    s_cmp_eq_f32 s1, s5
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_cselect_b32 s2, s6, s2
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    v_mov_b32_e32 v2, s2
; GFX1200-NEXT:    s_branch .LBB29_24
; GFX1200-NEXT:  .LBB29_22:
; GFX1200-NEXT:    v_mov_b32_e32 v7, v4
; GFX1200-NEXT:  .LBB29_23: ; %frem.loop_exit24
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_add_nc_u32_e32 v4, -11, v6
; GFX1200-NEXT:    v_ldexp_f32 v4, v7, v4
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_mul_f32_e32 v5, v4, v5
; GFX1200-NEXT:    v_rndne_f32_e32 v5, v5
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_xor_b32_e32 v5, 0x80000000, v5
; GFX1200-NEXT:    v_fmac_f32_e32 v4, v5, v3
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX1200-NEXT:    v_add_f32_e32 v3, v4, v3
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_ldexp_f32 v2, v3, v2
; GFX1200-NEXT:    v_bfi_b32 v2, 0x7fffffff, v2, s2
; GFX1200-NEXT:  .LBB29_24:
; GFX1200-NEXT:    s_and_b32 s2, s3, 0x7fffffff
; GFX1200-NEXT:    s_and_b32 s5, s19, 0x7fffffff
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_cmp_gt_f32 s2, s5
; GFX1200-NEXT:    s_cbranch_scc0 .LBB29_29
; GFX1200-NEXT:  ; %bb.25: ; %frem.compute
; GFX1200-NEXT:    v_frexp_mant_f32_e64 v4, |s19|
; GFX1200-NEXT:    v_frexp_mant_f32_e64 v3, |s3|
; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v6, s3
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT:    v_ldexp_f32 v4, v4, 1
; GFX1200-NEXT:    v_ldexp_f32 v5, v3, 12
; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v3, s19
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-NEXT:    v_readfirstlane_b32 s5, v6
; GFX1200-NEXT:    v_div_scale_f32 v8, null, v4, v4, 1.0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1200-NEXT:    v_readfirstlane_b32 s6, v3
; GFX1200-NEXT:    v_add_nc_u32_e32 v3, -1, v3
; GFX1200-NEXT:    v_rcp_f32_e32 v9, v8
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_not_b32_e32 v7, v3
; GFX1200-NEXT:    v_add_nc_u32_e32 v7, v7, v6
; GFX1200-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v4, 1.0
; GFX1200-NEXT:    s_denorm_mode 15
; GFX1200-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
; GFX1200-NEXT:    v_fmac_f32_e32 v9, v10, v9
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_mul_f32_e32 v10, v6, v9
; GFX1200-NEXT:    v_fma_f32 v11, -v8, v10, v6
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fmac_f32_e32 v10, v11, v9
; GFX1200-NEXT:    v_fma_f32 v6, -v8, v10, v6
; GFX1200-NEXT:    s_denorm_mode 12
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT:    v_div_fmas_f32 v6, v6, v9, v10
; GFX1200-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v7
; GFX1200-NEXT:    v_div_fixup_f32 v6, v6, v4, 1.0
; GFX1200-NEXT:    s_cbranch_vccnz .LBB29_30
; GFX1200-NEXT:  ; %bb.26: ; %frem.loop_body.preheader
; GFX1200-NEXT:    s_sub_co_i32 s5, s5, s6
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_add_co_i32 s5, s5, 12
; GFX1200-NEXT:  .LBB29_27: ; %frem.loop_body
; GFX1200-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_mov_b32_e32 v8, v5
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_add_co_i32 s5, s5, -12
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_cmp_gt_i32 s5, 12
; GFX1200-NEXT:    v_mul_f32_e32 v5, v8, v6
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_rndne_f32_e32 v5, v5
; GFX1200-NEXT:    v_xor_b32_e32 v5, 0x80000000, v5
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f32 v5, v5, v4, v8
; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX1200-NEXT:    v_add_f32_e32 v7, v5, v4
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX1200-NEXT:    v_ldexp_f32 v5, v5, 12
; GFX1200-NEXT:    s_cbranch_scc1 .LBB29_27
; GFX1200-NEXT:  ; %bb.28:
; GFX1200-NEXT:    v_mov_b32_e32 v7, s5
; GFX1200-NEXT:    s_branch .LBB29_31
; GFX1200-NEXT:  .LBB29_29: ; %frem.else
; GFX1200-NEXT:    s_and_b32 s6, 0x80000000, s3
; GFX1200-NEXT:    s_cmp_eq_f32 s2, s5
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_cselect_b32 s3, s6, s3
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    v_mov_b32_e32 v3, s3
; GFX1200-NEXT:    s_branch .LBB29_32
; GFX1200-NEXT:  .LBB29_30:
; GFX1200-NEXT:    v_mov_b32_e32 v8, v5
; GFX1200-NEXT:  .LBB29_31: ; %frem.loop_exit
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_add_nc_u32_e32 v5, -11, v7
; GFX1200-NEXT:    v_ldexp_f32 v5, v8, v5
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_mul_f32_e32 v6, v5, v6
; GFX1200-NEXT:    v_rndne_f32_e32 v6, v6
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_xor_b32_e32 v6, 0x80000000, v6
; GFX1200-NEXT:    v_fmac_f32_e32 v5, v6, v4
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX1200-NEXT:    v_add_f32_e32 v4, v5, v4
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc_lo
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_ldexp_f32 v3, v4, v3
; GFX1200-NEXT:    v_bfi_b32 v3, 0x7fffffff, v3, s3
; GFX1200-NEXT:  .LBB29_32:
; GFX1200-NEXT:    s_cmp_lg_f32 s16, 0
; GFX1200-NEXT:    s_cselect_b32 s3, -1, 0
; GFX1200-NEXT:    s_cmp_nge_f32 s4, 0x7f800000
; GFX1200-NEXT:    s_cselect_b32 s4, -1, 0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_and_b32 vcc_lo, s4, s3
; GFX1200-NEXT:    s_cmp_lg_f32 s17, 0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
; GFX1200-NEXT:    s_cselect_b32 s3, -1, 0
; GFX1200-NEXT:    s_cmp_nge_f32 s0, 0x7f800000
; GFX1200-NEXT:    s_cselect_b32 s0, -1, 0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_and_b32 vcc_lo, s0, s3
; GFX1200-NEXT:    s_cmp_lg_f32 s18, 0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v1, vcc_lo
; GFX1200-NEXT:    s_cselect_b32 s0, -1, 0
; GFX1200-NEXT:    s_cmp_nge_f32 s1, 0x7f800000
; GFX1200-NEXT:    s_cselect_b32 s1, -1, 0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_and_b32 vcc_lo, s1, s0
; GFX1200-NEXT:    s_cmp_lg_f32 s19, 0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    v_cndmask_b32_e32 v2, 0x7fc00000, v2, vcc_lo
; GFX1200-NEXT:    s_cselect_b32 s0, -1, 0
; GFX1200-NEXT:    s_cmp_nge_f32 s2, 0x7f800000
; GFX1200-NEXT:    s_cselect_b32 s1, -1, 0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_and_b32 vcc_lo, s1, s0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    v_cndmask_b32_e32 v3, 0x7fc00000, v3, vcc_lo
; GFX1200-NEXT:    s_setpc_b64 s[30:31]
   %r2 = frem <4 x float> %in1, %in2
  ret <4 x float> %r2
}

define <2 x double> @frem_v2f64_uniform(<2 x double> inreg %in1, <2 x double> inreg %in2) #0 {
; SI-LABEL: frem_v2f64_uniform:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_mov_b32_e32 v0, s20
; SI-NEXT:    v_mov_b32_e32 v1, s21
; SI-NEXT:    v_cmp_gt_f64_e64 vcc, |s[16:17]|, |v[0:1]|
; SI-NEXT:    s_cbranch_vccz .LBB30_4
; SI-NEXT:  ; %bb.1: ; %frem.compute15
; SI-NEXT:    s_and_b32 s4, s17, 0x7fffffff
; SI-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[16:17]|
; SI-NEXT:    s_cmp_lt_i32 s4, 0x7ff00000
; SI-NEXT:    s_cselect_b64 vcc, -1, 0
; SI-NEXT:    v_mov_b32_e32 v2, s4
; SI-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; SI-NEXT:    v_mov_b32_e32 v2, s16
; SI-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
; SI-NEXT:    v_frexp_exp_i32_f64_e32 v2, s[16:17]
; SI-NEXT:    v_ldexp_f64 v[4:5], v[0:1], 26
; SI-NEXT:    v_readfirstlane_b32 s4, v2
; SI-NEXT:    s_cselect_b32 s7, s4, 0
; SI-NEXT:    s_and_b32 s4, s21, 0x7fffffff
; SI-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[20:21]|
; SI-NEXT:    s_cmp_lt_i32 s4, 0x7ff00000
; SI-NEXT:    s_cselect_b64 vcc, -1, 0
; SI-NEXT:    v_mov_b32_e32 v2, s4
; SI-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; SI-NEXT:    v_mov_b32_e32 v2, s20
; SI-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
; SI-NEXT:    v_frexp_exp_i32_f64_e32 v2, s[20:21]
; SI-NEXT:    v_ldexp_f64 v[0:1], v[0:1], 1
; SI-NEXT:    v_readfirstlane_b32 s4, v2
; SI-NEXT:    s_cselect_b32 s11, s4, 0
; SI-NEXT:    s_add_i32 s9, s11, -1
; SI-NEXT:    s_not_b32 s4, s9
; SI-NEXT:    s_add_i32 s10, s4, s7
; SI-NEXT:    v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], 1.0
; SI-NEXT:    s_brev_b32 s8, -2
; SI-NEXT:    s_mov_b32 s6, -1
; SI-NEXT:    v_rcp_f64_e32 v[6:7], v[2:3]
; SI-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
; SI-NEXT:    v_fma_f64 v[8:9], -v[2:3], v[6:7], 1.0
; SI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; SI-NEXT:    v_fma_f64 v[8:9], -v[2:3], v[6:7], 1.0
; SI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; SI-NEXT:    v_div_scale_f64 v[8:9], s[4:5], 1.0, v[0:1], 1.0
; SI-NEXT:    s_mov_b32 s4, 0x3ff00000
; SI-NEXT:    v_mul_f64 v[10:11], v[8:9], v[6:7]
; SI-NEXT:    v_cmp_eq_u32_e64 s[4:5], s4, v9
; SI-NEXT:    v_fma_f64 v[12:13], -v[2:3], v[10:11], v[8:9]
; SI-NEXT:    s_xor_b64 vcc, s[4:5], vcc
; SI-NEXT:    v_div_fmas_f64 v[2:3], v[12:13], v[6:7], v[10:11]
; SI-NEXT:    s_cmp_lt_i32 s10, 27
; SI-NEXT:    v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0
; SI-NEXT:    s_cbranch_scc1 .LBB30_5
; SI-NEXT:  ; %bb.2: ; %frem.loop_body23.preheader
; SI-NEXT:    s_sub_i32 s4, s7, s11
; SI-NEXT:    s_add_i32 s10, s4, 26
; SI-NEXT:    s_mov_b32 s7, 0x432fffff
; SI-NEXT:    v_mov_b32_e32 v10, 0x43300000
; SI-NEXT:    v_mov_b32_e32 v8, 0
; SI-NEXT:  .LBB30_3: ; %frem.loop_body23
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v7, v5
; SI-NEXT:    v_mov_b32_e32 v6, v4
; SI-NEXT:    v_mul_f64 v[4:5], v[6:7], v[2:3]
; SI-NEXT:    s_sub_i32 s10, s10, 26
; SI-NEXT:    v_bfi_b32 v9, s8, v10, v5
; SI-NEXT:    v_add_f64 v[11:12], v[4:5], v[8:9]
; SI-NEXT:    v_cmp_gt_f64_e64 vcc, |v[4:5]|, s[6:7]
; SI-NEXT:    v_add_f64 v[11:12], v[11:12], -v[8:9]
; SI-NEXT:    s_cmp_gt_i32 s10, 26
; SI-NEXT:    v_cndmask_b32_e32 v5, v12, v5, vcc
; SI-NEXT:    v_cndmask_b32_e32 v4, v11, v4, vcc
; SI-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[0:1], v[6:7]
; SI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[4:5]
; SI-NEXT:    v_add_f64 v[11:12], v[4:5], v[0:1]
; SI-NEXT:    v_cndmask_b32_e32 v5, v5, v12, vcc
; SI-NEXT:    v_cndmask_b32_e32 v4, v4, v11, vcc
; SI-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; SI-NEXT:    s_cbranch_scc1 .LBB30_3
; SI-NEXT:    s_branch .LBB30_6
; SI-NEXT:  .LBB30_4: ; %frem.else16
; SI-NEXT:    v_mov_b32_e32 v0, s20
; SI-NEXT:    v_mov_b32_e32 v1, s21
; SI-NEXT:    v_cmp_eq_f64_e64 s[4:5], |s[16:17]|, |v[0:1]|
; SI-NEXT:    s_and_b32 s6, s17, 0x80000000
; SI-NEXT:    s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT:    s_cselect_b32 s5, s6, s17
; SI-NEXT:    s_cselect_b32 s4, 0, s16
; SI-NEXT:    v_mov_b32_e32 v0, s4
; SI-NEXT:    v_mov_b32_e32 v1, s5
; SI-NEXT:    s_branch .LBB30_7
; SI-NEXT:  .LBB30_5:
; SI-NEXT:    v_mov_b32_e32 v7, v5
; SI-NEXT:    v_mov_b32_e32 v6, v4
; SI-NEXT:  .LBB30_6: ; %frem.loop_exit24
; SI-NEXT:    s_sub_i32 s4, s10, 25
; SI-NEXT:    v_ldexp_f64 v[4:5], v[6:7], s4
; SI-NEXT:    v_mov_b32_e32 v6, 0x43300000
; SI-NEXT:    v_mul_f64 v[2:3], v[4:5], v[2:3]
; SI-NEXT:    s_mov_b32 s7, 0x432fffff
; SI-NEXT:    v_bfi_b32 v7, s8, v6, v3
; SI-NEXT:    v_mov_b32_e32 v6, 0
; SI-NEXT:    v_add_f64 v[8:9], v[2:3], v[6:7]
; SI-NEXT:    v_cmp_gt_f64_e64 vcc, |v[2:3]|, s[6:7]
; SI-NEXT:    v_add_f64 v[6:7], v[8:9], -v[6:7]
; SI-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
; SI-NEXT:    v_cndmask_b32_e32 v2, v6, v2, vcc
; SI-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[0:1], v[4:5]
; SI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[2:3]
; SI-NEXT:    v_add_f64 v[0:1], v[2:3], v[0:1]
; SI-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
; SI-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
; SI-NEXT:    v_ldexp_f64 v[0:1], v[0:1], s9
; SI-NEXT:    v_mov_b32_e32 v2, s17
; SI-NEXT:    v_bfi_b32 v1, s8, v1, v2
; SI-NEXT:  .LBB30_7:
; SI-NEXT:    v_mov_b32_e32 v2, s22
; SI-NEXT:    v_mov_b32_e32 v3, s23
; SI-NEXT:    v_cmp_gt_f64_e64 vcc, |s[18:19]|, |v[2:3]|
; SI-NEXT:    s_cbranch_vccz .LBB30_11
; SI-NEXT:  ; %bb.8: ; %frem.compute
; SI-NEXT:    s_and_b32 s4, s19, 0x7fffffff
; SI-NEXT:    v_frexp_mant_f64_e64 v[2:3], |s[18:19]|
; SI-NEXT:    s_cmp_lt_i32 s4, 0x7ff00000
; SI-NEXT:    s_cselect_b64 vcc, -1, 0
; SI-NEXT:    v_mov_b32_e32 v4, s4
; SI-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; SI-NEXT:    v_mov_b32_e32 v4, s18
; SI-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; SI-NEXT:    v_frexp_exp_i32_f64_e32 v4, s[18:19]
; SI-NEXT:    v_ldexp_f64 v[6:7], v[2:3], 26
; SI-NEXT:    v_readfirstlane_b32 s4, v4
; SI-NEXT:    s_cselect_b32 s7, s4, 0
; SI-NEXT:    s_and_b32 s4, s23, 0x7fffffff
; SI-NEXT:    v_frexp_mant_f64_e64 v[2:3], |s[22:23]|
; SI-NEXT:    s_cmp_lt_i32 s4, 0x7ff00000
; SI-NEXT:    s_cselect_b64 vcc, -1, 0
; SI-NEXT:    v_mov_b32_e32 v4, s4
; SI-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; SI-NEXT:    v_mov_b32_e32 v4, s22
; SI-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; SI-NEXT:    v_frexp_exp_i32_f64_e32 v4, s[22:23]
; SI-NEXT:    v_ldexp_f64 v[2:3], v[2:3], 1
; SI-NEXT:    v_readfirstlane_b32 s4, v4
; SI-NEXT:    s_cselect_b32 s11, s4, 0
; SI-NEXT:    s_add_i32 s9, s11, -1
; SI-NEXT:    s_not_b32 s4, s9
; SI-NEXT:    s_add_i32 s10, s4, s7
; SI-NEXT:    v_div_scale_f64 v[4:5], s[4:5], v[2:3], v[2:3], 1.0
; SI-NEXT:    s_brev_b32 s8, -2
; SI-NEXT:    s_mov_b32 s6, -1
; SI-NEXT:    v_rcp_f64_e32 v[8:9], v[4:5]
; SI-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v5
; SI-NEXT:    v_fma_f64 v[10:11], -v[4:5], v[8:9], 1.0
; SI-NEXT:    v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
; SI-NEXT:    v_fma_f64 v[10:11], -v[4:5], v[8:9], 1.0
; SI-NEXT:    v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
; SI-NEXT:    v_div_scale_f64 v[10:11], s[4:5], 1.0, v[2:3], 1.0
; SI-NEXT:    s_mov_b32 s4, 0x3ff00000
; SI-NEXT:    v_mul_f64 v[12:13], v[10:11], v[8:9]
; SI-NEXT:    v_cmp_eq_u32_e64 s[4:5], s4, v11
; SI-NEXT:    v_fma_f64 v[14:15], -v[4:5], v[12:13], v[10:11]
; SI-NEXT:    s_xor_b64 vcc, s[4:5], vcc
; SI-NEXT:    v_div_fmas_f64 v[4:5], v[14:15], v[8:9], v[12:13]
; SI-NEXT:    s_cmp_lt_i32 s10, 27
; SI-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], 1.0
; SI-NEXT:    s_cbranch_scc1 .LBB30_12
; SI-NEXT:  ; %bb.9: ; %frem.loop_body.preheader
; SI-NEXT:    s_sub_i32 s4, s7, s11
; SI-NEXT:    s_add_i32 s10, s4, 26
; SI-NEXT:    s_mov_b32 s7, 0x432fffff
; SI-NEXT:    v_mov_b32_e32 v12, 0x43300000
; SI-NEXT:    v_mov_b32_e32 v10, 0
; SI-NEXT:  .LBB30_10: ; %frem.loop_body
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v9, v7
; SI-NEXT:    v_mov_b32_e32 v8, v6
; SI-NEXT:    v_mul_f64 v[6:7], v[8:9], v[4:5]
; SI-NEXT:    s_sub_i32 s10, s10, 26
; SI-NEXT:    v_bfi_b32 v11, s8, v12, v7
; SI-NEXT:    v_add_f64 v[13:14], v[6:7], v[10:11]
; SI-NEXT:    v_cmp_gt_f64_e64 vcc, |v[6:7]|, s[6:7]
; SI-NEXT:    v_add_f64 v[13:14], v[13:14], -v[10:11]
; SI-NEXT:    s_cmp_gt_i32 s10, 26
; SI-NEXT:    v_cndmask_b32_e32 v7, v14, v7, vcc
; SI-NEXT:    v_cndmask_b32_e32 v6, v13, v6, vcc
; SI-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[2:3], v[8:9]
; SI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[6:7]
; SI-NEXT:    v_add_f64 v[13:14], v[6:7], v[2:3]
; SI-NEXT:    v_cndmask_b32_e32 v7, v7, v14, vcc
; SI-NEXT:    v_cndmask_b32_e32 v6, v6, v13, vcc
; SI-NEXT:    v_ldexp_f64 v[6:7], v[6:7], 26
; SI-NEXT:    s_cbranch_scc1 .LBB30_10
; SI-NEXT:    s_branch .LBB30_13
; SI-NEXT:  .LBB30_11: ; %frem.else
; SI-NEXT:    v_mov_b32_e32 v2, s22
; SI-NEXT:    v_mov_b32_e32 v3, s23
; SI-NEXT:    v_cmp_eq_f64_e64 s[4:5], |s[18:19]|, |v[2:3]|
; SI-NEXT:    s_and_b32 s6, s19, 0x80000000
; SI-NEXT:    s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT:    s_cselect_b32 s5, s6, s19
; SI-NEXT:    s_cselect_b32 s4, 0, s18
; SI-NEXT:    v_mov_b32_e32 v2, s4
; SI-NEXT:    v_mov_b32_e32 v3, s5
; SI-NEXT:    s_branch .LBB30_14
; SI-NEXT:  .LBB30_12:
; SI-NEXT:    v_mov_b32_e32 v9, v7
; SI-NEXT:    v_mov_b32_e32 v8, v6
; SI-NEXT:  .LBB30_13: ; %frem.loop_exit
; SI-NEXT:    s_sub_i32 s4, s10, 25
; SI-NEXT:    v_ldexp_f64 v[6:7], v[8:9], s4
; SI-NEXT:    v_mov_b32_e32 v8, 0x43300000
; SI-NEXT:    v_mul_f64 v[4:5], v[6:7], v[4:5]
; SI-NEXT:    s_mov_b32 s7, 0x432fffff
; SI-NEXT:    v_bfi_b32 v9, s8, v8, v5
; SI-NEXT:    v_mov_b32_e32 v8, 0
; SI-NEXT:    v_add_f64 v[10:11], v[4:5], v[8:9]
; SI-NEXT:    v_cmp_gt_f64_e64 vcc, |v[4:5]|, s[6:7]
; SI-NEXT:    v_add_f64 v[8:9], v[10:11], -v[8:9]
; SI-NEXT:    v_cndmask_b32_e32 v5, v9, v5, vcc
; SI-NEXT:    v_cndmask_b32_e32 v4, v8, v4, vcc
; SI-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[2:3], v[6:7]
; SI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[4:5]
; SI-NEXT:    v_add_f64 v[2:3], v[4:5], v[2:3]
; SI-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
; SI-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; SI-NEXT:    v_ldexp_f64 v[2:3], v[2:3], s9
; SI-NEXT:    v_mov_b32_e32 v4, s19
; SI-NEXT:    v_bfi_b32 v3, s8, v3, v4
; SI-NEXT:  .LBB30_14:
; SI-NEXT:    v_mov_b32_e32 v4, 0
; SI-NEXT:    v_mov_b32_e32 v5, 0x7ff00000
; SI-NEXT:    v_cmp_lg_f64_e64 s[4:5], s[20:21], 0
; SI-NEXT:    v_cmp_nge_f64_e64 s[6:7], |s[16:17]|, v[4:5]
; SI-NEXT:    v_mov_b32_e32 v6, 0x7ff80000
; SI-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; SI-NEXT:    v_cmp_lg_f64_e64 s[4:5], s[22:23], 0
; SI-NEXT:    v_cmp_nge_f64_e64 s[6:7], |s[18:19]|, v[4:5]
; SI-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
; SI-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc
; SI-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; SI-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
; SI-NEXT:    v_cndmask_b32_e32 v3, v6, v3, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; CI-LABEL: frem_v2f64_uniform:
; CI:       ; %bb.0:
; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-NEXT:    v_mov_b32_e32 v0, s20
; CI-NEXT:    v_mov_b32_e32 v1, s21
; CI-NEXT:    v_cmp_gt_f64_e64 vcc, |s[16:17]|, |v[0:1]|
; CI-NEXT:    s_cbranch_vccz .LBB30_4
; CI-NEXT:  ; %bb.1: ; %frem.compute15
; CI-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[16:17]|
; CI-NEXT:    v_frexp_exp_i32_f64_e32 v7, s[20:21]
; CI-NEXT:    v_frexp_exp_i32_f64_e32 v6, s[16:17]
; CI-NEXT:    v_ldexp_f64 v[4:5], v[0:1], 26
; CI-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[20:21]|
; CI-NEXT:    v_add_i32_e32 v8, vcc, -1, v7
; CI-NEXT:    v_not_b32_e32 v2, v8
; CI-NEXT:    v_add_i32_e32 v9, vcc, v2, v6
; CI-NEXT:    v_ldexp_f64 v[0:1], v[0:1], 1
; CI-NEXT:    v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], 1.0
; CI-NEXT:    v_rcp_f64_e32 v[10:11], v[2:3]
; CI-NEXT:    v_fma_f64 v[12:13], -v[2:3], v[10:11], 1.0
; CI-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
; CI-NEXT:    v_fma_f64 v[12:13], -v[2:3], v[10:11], 1.0
; CI-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
; CI-NEXT:    v_div_scale_f64 v[12:13], vcc, 1.0, v[0:1], 1.0
; CI-NEXT:    v_mul_f64 v[14:15], v[12:13], v[10:11]
; CI-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[14:15], v[12:13]
; CI-NEXT:    s_nop 1
; CI-NEXT:    v_div_fmas_f64 v[2:3], v[2:3], v[10:11], v[14:15]
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v9
; CI-NEXT:    v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0
; CI-NEXT:    s_cbranch_vccnz .LBB30_5
; CI-NEXT:  ; %bb.2: ; %frem.loop_body23.preheader
; CI-NEXT:    v_sub_i32_e32 v6, vcc, v6, v7
; CI-NEXT:    v_add_i32_e32 v9, vcc, 26, v6
; CI-NEXT:  .LBB30_3: ; %frem.loop_body23
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v7, v5
; CI-NEXT:    v_mov_b32_e32 v6, v4
; CI-NEXT:    v_mul_f64 v[4:5], v[6:7], v[2:3]
; CI-NEXT:    v_rndne_f64_e32 v[4:5], v[4:5]
; CI-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[0:1], v[6:7]
; CI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[4:5]
; CI-NEXT:    v_add_f64 v[10:11], v[4:5], v[0:1]
; CI-NEXT:    v_cndmask_b32_e32 v5, v5, v11, vcc
; CI-NEXT:    v_cndmask_b32_e32 v4, v4, v10, vcc
; CI-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; CI-NEXT:    v_subrev_i32_e32 v9, vcc, 26, v9
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v9
; CI-NEXT:    s_cbranch_vccnz .LBB30_3
; CI-NEXT:    s_branch .LBB30_6
; CI-NEXT:  .LBB30_4: ; %frem.else16
; CI-NEXT:    v_mov_b32_e32 v0, s20
; CI-NEXT:    v_mov_b32_e32 v1, s21
; CI-NEXT:    v_cmp_eq_f64_e64 s[4:5], |s[16:17]|, |v[0:1]|
; CI-NEXT:    s_and_b32 s6, s17, 0x80000000
; CI-NEXT:    s_and_b64 s[4:5], s[4:5], exec
; CI-NEXT:    s_cselect_b32 s5, s6, s17
; CI-NEXT:    s_cselect_b32 s4, 0, s16
; CI-NEXT:    v_mov_b32_e32 v0, s4
; CI-NEXT:    v_mov_b32_e32 v1, s5
; CI-NEXT:    s_branch .LBB30_7
; CI-NEXT:  .LBB30_5:
; CI-NEXT:    v_mov_b32_e32 v7, v5
; CI-NEXT:    v_mov_b32_e32 v6, v4
; CI-NEXT:  .LBB30_6: ; %frem.loop_exit24
; CI-NEXT:    v_subrev_i32_e32 v4, vcc, 25, v9
; CI-NEXT:    v_ldexp_f64 v[4:5], v[6:7], v4
; CI-NEXT:    s_brev_b32 s4, -2
; CI-NEXT:    v_mul_f64 v[2:3], v[4:5], v[2:3]
; CI-NEXT:    v_rndne_f64_e32 v[2:3], v[2:3]
; CI-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[0:1], v[4:5]
; CI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[2:3]
; CI-NEXT:    v_add_f64 v[0:1], v[2:3], v[0:1]
; CI-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
; CI-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
; CI-NEXT:    v_ldexp_f64 v[0:1], v[0:1], v8
; CI-NEXT:    v_mov_b32_e32 v2, s17
; CI-NEXT:    v_bfi_b32 v1, s4, v1, v2
; CI-NEXT:  .LBB30_7:
; CI-NEXT:    v_mov_b32_e32 v2, s22
; CI-NEXT:    v_mov_b32_e32 v3, s23
; CI-NEXT:    v_cmp_gt_f64_e64 vcc, |s[18:19]|, |v[2:3]|
; CI-NEXT:    s_cbranch_vccz .LBB30_11
; CI-NEXT:  ; %bb.8: ; %frem.compute
; CI-NEXT:    v_frexp_mant_f64_e64 v[2:3], |s[18:19]|
; CI-NEXT:    v_frexp_exp_i32_f64_e32 v9, s[22:23]
; CI-NEXT:    v_frexp_exp_i32_f64_e32 v8, s[18:19]
; CI-NEXT:    v_ldexp_f64 v[6:7], v[2:3], 26
; CI-NEXT:    v_frexp_mant_f64_e64 v[2:3], |s[22:23]|
; CI-NEXT:    v_add_i32_e32 v10, vcc, -1, v9
; CI-NEXT:    v_not_b32_e32 v4, v10
; CI-NEXT:    v_add_i32_e32 v11, vcc, v4, v8
; CI-NEXT:    v_ldexp_f64 v[2:3], v[2:3], 1
; CI-NEXT:    v_div_scale_f64 v[4:5], s[4:5], v[2:3], v[2:3], 1.0
; CI-NEXT:    v_rcp_f64_e32 v[12:13], v[4:5]
; CI-NEXT:    v_fma_f64 v[14:15], -v[4:5], v[12:13], 1.0
; CI-NEXT:    v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
; CI-NEXT:    v_fma_f64 v[14:15], -v[4:5], v[12:13], 1.0
; CI-NEXT:    v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
; CI-NEXT:    v_div_scale_f64 v[14:15], vcc, 1.0, v[2:3], 1.0
; CI-NEXT:    v_mul_f64 v[16:17], v[14:15], v[12:13]
; CI-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[16:17], v[14:15]
; CI-NEXT:    s_nop 1
; CI-NEXT:    v_div_fmas_f64 v[4:5], v[4:5], v[12:13], v[16:17]
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v11
; CI-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], 1.0
; CI-NEXT:    s_cbranch_vccnz .LBB30_12
; CI-NEXT:  ; %bb.9: ; %frem.loop_body.preheader
; CI-NEXT:    v_sub_i32_e32 v8, vcc, v8, v9
; CI-NEXT:    v_add_i32_e32 v11, vcc, 26, v8
; CI-NEXT:  .LBB30_10: ; %frem.loop_body
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v9, v7
; CI-NEXT:    v_mov_b32_e32 v8, v6
; CI-NEXT:    v_mul_f64 v[6:7], v[8:9], v[4:5]
; CI-NEXT:    v_rndne_f64_e32 v[6:7], v[6:7]
; CI-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[2:3], v[8:9]
; CI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[6:7]
; CI-NEXT:    v_add_f64 v[12:13], v[6:7], v[2:3]
; CI-NEXT:    v_cndmask_b32_e32 v7, v7, v13, vcc
; CI-NEXT:    v_cndmask_b32_e32 v6, v6, v12, vcc
; CI-NEXT:    v_ldexp_f64 v[6:7], v[6:7], 26
; CI-NEXT:    v_subrev_i32_e32 v11, vcc, 26, v11
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v11
; CI-NEXT:    s_cbranch_vccnz .LBB30_10
; CI-NEXT:    s_branch .LBB30_13
; CI-NEXT:  .LBB30_11: ; %frem.else
; CI-NEXT:    v_mov_b32_e32 v2, s22
; CI-NEXT:    v_mov_b32_e32 v3, s23
; CI-NEXT:    v_cmp_eq_f64_e64 s[4:5], |s[18:19]|, |v[2:3]|
; CI-NEXT:    s_and_b32 s6, s19, 0x80000000
; CI-NEXT:    s_and_b64 s[4:5], s[4:5], exec
; CI-NEXT:    s_cselect_b32 s5, s6, s19
; CI-NEXT:    s_cselect_b32 s4, 0, s18
; CI-NEXT:    v_mov_b32_e32 v2, s4
; CI-NEXT:    v_mov_b32_e32 v3, s5
; CI-NEXT:    s_branch .LBB30_14
; CI-NEXT:  .LBB30_12:
; CI-NEXT:    v_mov_b32_e32 v9, v7
; CI-NEXT:    v_mov_b32_e32 v8, v6
; CI-NEXT:  .LBB30_13: ; %frem.loop_exit
; CI-NEXT:    v_subrev_i32_e32 v6, vcc, 25, v11
; CI-NEXT:    v_ldexp_f64 v[6:7], v[8:9], v6
; CI-NEXT:    s_brev_b32 s4, -2
; CI-NEXT:    v_mul_f64 v[4:5], v[6:7], v[4:5]
; CI-NEXT:    v_rndne_f64_e32 v[4:5], v[4:5]
; CI-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[2:3], v[6:7]
; CI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[4:5]
; CI-NEXT:    v_add_f64 v[2:3], v[4:5], v[2:3]
; CI-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
; CI-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; CI-NEXT:    v_ldexp_f64 v[2:3], v[2:3], v10
; CI-NEXT:    v_mov_b32_e32 v4, s19
; CI-NEXT:    v_bfi_b32 v3, s4, v3, v4
; CI-NEXT:  .LBB30_14:
; CI-NEXT:    v_mov_b32_e32 v4, 0
; CI-NEXT:    v_mov_b32_e32 v5, 0x7ff00000
; CI-NEXT:    v_cmp_lg_f64_e64 s[4:5], s[20:21], 0
; CI-NEXT:    v_cmp_nge_f64_e64 s[6:7], |s[16:17]|, v[4:5]
; CI-NEXT:    v_mov_b32_e32 v6, 0x7ff80000
; CI-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; CI-NEXT:    v_cmp_lg_f64_e64 s[4:5], s[22:23], 0
; CI-NEXT:    v_cmp_nge_f64_e64 s[6:7], |s[18:19]|, v[4:5]
; CI-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
; CI-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc
; CI-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; CI-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
; CI-NEXT:    v_cndmask_b32_e32 v3, v6, v3, vcc
; CI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: frem_v2f64_uniform:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_mov_b32_e32 v0, s20
; VI-NEXT:    v_mov_b32_e32 v1, s21
; VI-NEXT:    v_cmp_gt_f64_e64 vcc, |s[16:17]|, |v[0:1]|
; VI-NEXT:    s_cbranch_vccz .LBB30_4
; VI-NEXT:  ; %bb.1: ; %frem.compute15
; VI-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[16:17]|
; VI-NEXT:    v_frexp_exp_i32_f64_e32 v7, s[20:21]
; VI-NEXT:    v_frexp_exp_i32_f64_e32 v6, s[16:17]
; VI-NEXT:    v_ldexp_f64 v[4:5], v[0:1], 26
; VI-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[20:21]|
; VI-NEXT:    v_add_u32_e32 v8, vcc, -1, v7
; VI-NEXT:    v_not_b32_e32 v2, v8
; VI-NEXT:    v_add_u32_e32 v9, vcc, v2, v6
; VI-NEXT:    v_ldexp_f64 v[0:1], v[0:1], 1
; VI-NEXT:    v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], 1.0
; VI-NEXT:    v_rcp_f64_e32 v[10:11], v[2:3]
; VI-NEXT:    v_fma_f64 v[12:13], -v[2:3], v[10:11], 1.0
; VI-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
; VI-NEXT:    v_fma_f64 v[12:13], -v[2:3], v[10:11], 1.0
; VI-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
; VI-NEXT:    v_div_scale_f64 v[12:13], vcc, 1.0, v[0:1], 1.0
; VI-NEXT:    v_mul_f64 v[14:15], v[12:13], v[10:11]
; VI-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[14:15], v[12:13]
; VI-NEXT:    s_nop 1
; VI-NEXT:    v_div_fmas_f64 v[2:3], v[2:3], v[10:11], v[14:15]
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v9
; VI-NEXT:    v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0
; VI-NEXT:    s_cbranch_vccnz .LBB30_5
; VI-NEXT:  ; %bb.2: ; %frem.loop_body23.preheader
; VI-NEXT:    v_sub_u32_e32 v6, vcc, v6, v7
; VI-NEXT:    v_add_u32_e32 v9, vcc, 26, v6
; VI-NEXT:  .LBB30_3: ; %frem.loop_body23
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v7, v5
; VI-NEXT:    v_mov_b32_e32 v6, v4
; VI-NEXT:    v_mul_f64 v[4:5], v[6:7], v[2:3]
; VI-NEXT:    v_rndne_f64_e32 v[4:5], v[4:5]
; VI-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[0:1], v[6:7]
; VI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[4:5]
; VI-NEXT:    v_add_f64 v[10:11], v[4:5], v[0:1]
; VI-NEXT:    v_cndmask_b32_e32 v5, v5, v11, vcc
; VI-NEXT:    v_cndmask_b32_e32 v4, v4, v10, vcc
; VI-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; VI-NEXT:    v_subrev_u32_e32 v9, vcc, 26, v9
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v9
; VI-NEXT:    s_cbranch_vccnz .LBB30_3
; VI-NEXT:    s_branch .LBB30_6
; VI-NEXT:  .LBB30_4: ; %frem.else16
; VI-NEXT:    v_mov_b32_e32 v0, s20
; VI-NEXT:    v_mov_b32_e32 v1, s21
; VI-NEXT:    v_cmp_eq_f64_e64 s[4:5], |s[16:17]|, |v[0:1]|
; VI-NEXT:    s_and_b32 s6, s17, 0x80000000
; VI-NEXT:    s_cmp_lg_u64 s[4:5], 0
; VI-NEXT:    s_cselect_b32 s5, s6, s17
; VI-NEXT:    s_cselect_b32 s4, 0, s16
; VI-NEXT:    v_mov_b32_e32 v0, s4
; VI-NEXT:    v_mov_b32_e32 v1, s5
; VI-NEXT:    s_branch .LBB30_7
; VI-NEXT:  .LBB30_5:
; VI-NEXT:    v_mov_b32_e32 v7, v5
; VI-NEXT:    v_mov_b32_e32 v6, v4
; VI-NEXT:  .LBB30_6: ; %frem.loop_exit24
; VI-NEXT:    v_subrev_u32_e32 v4, vcc, 25, v9
; VI-NEXT:    v_ldexp_f64 v[4:5], v[6:7], v4
; VI-NEXT:    s_brev_b32 s4, -2
; VI-NEXT:    v_mul_f64 v[2:3], v[4:5], v[2:3]
; VI-NEXT:    v_rndne_f64_e32 v[2:3], v[2:3]
; VI-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[0:1], v[4:5]
; VI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[2:3]
; VI-NEXT:    v_add_f64 v[0:1], v[2:3], v[0:1]
; VI-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-NEXT:    v_ldexp_f64 v[0:1], v[0:1], v8
; VI-NEXT:    v_mov_b32_e32 v2, s17
; VI-NEXT:    v_bfi_b32 v1, s4, v1, v2
; VI-NEXT:  .LBB30_7:
; VI-NEXT:    v_mov_b32_e32 v2, s22
; VI-NEXT:    v_mov_b32_e32 v3, s23
; VI-NEXT:    v_cmp_gt_f64_e64 vcc, |s[18:19]|, |v[2:3]|
; VI-NEXT:    s_cbranch_vccz .LBB30_11
; VI-NEXT:  ; %bb.8: ; %frem.compute
; VI-NEXT:    v_frexp_mant_f64_e64 v[2:3], |s[18:19]|
; VI-NEXT:    v_frexp_exp_i32_f64_e32 v9, s[22:23]
; VI-NEXT:    v_frexp_exp_i32_f64_e32 v8, s[18:19]
; VI-NEXT:    v_ldexp_f64 v[6:7], v[2:3], 26
; VI-NEXT:    v_frexp_mant_f64_e64 v[2:3], |s[22:23]|
; VI-NEXT:    v_add_u32_e32 v10, vcc, -1, v9
; VI-NEXT:    v_not_b32_e32 v4, v10
; VI-NEXT:    v_add_u32_e32 v11, vcc, v4, v8
; VI-NEXT:    v_ldexp_f64 v[2:3], v[2:3], 1
; VI-NEXT:    v_div_scale_f64 v[4:5], s[4:5], v[2:3], v[2:3], 1.0
; VI-NEXT:    v_rcp_f64_e32 v[12:13], v[4:5]
; VI-NEXT:    v_fma_f64 v[14:15], -v[4:5], v[12:13], 1.0
; VI-NEXT:    v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
; VI-NEXT:    v_fma_f64 v[14:15], -v[4:5], v[12:13], 1.0
; VI-NEXT:    v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
; VI-NEXT:    v_div_scale_f64 v[14:15], vcc, 1.0, v[2:3], 1.0
; VI-NEXT:    v_mul_f64 v[16:17], v[14:15], v[12:13]
; VI-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[16:17], v[14:15]
; VI-NEXT:    s_nop 1
; VI-NEXT:    v_div_fmas_f64 v[4:5], v[4:5], v[12:13], v[16:17]
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v11
; VI-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], 1.0
; VI-NEXT:    s_cbranch_vccnz .LBB30_12
; VI-NEXT:  ; %bb.9: ; %frem.loop_body.preheader
; VI-NEXT:    v_sub_u32_e32 v8, vcc, v8, v9
; VI-NEXT:    v_add_u32_e32 v11, vcc, 26, v8
; VI-NEXT:  .LBB30_10: ; %frem.loop_body
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v9, v7
; VI-NEXT:    v_mov_b32_e32 v8, v6
; VI-NEXT:    v_mul_f64 v[6:7], v[8:9], v[4:5]
; VI-NEXT:    v_rndne_f64_e32 v[6:7], v[6:7]
; VI-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[2:3], v[8:9]
; VI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[6:7]
; VI-NEXT:    v_add_f64 v[12:13], v[6:7], v[2:3]
; VI-NEXT:    v_cndmask_b32_e32 v7, v7, v13, vcc
; VI-NEXT:    v_cndmask_b32_e32 v6, v6, v12, vcc
; VI-NEXT:    v_ldexp_f64 v[6:7], v[6:7], 26
; VI-NEXT:    v_subrev_u32_e32 v11, vcc, 26, v11
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v11
; VI-NEXT:    s_cbranch_vccnz .LBB30_10
; VI-NEXT:    s_branch .LBB30_13
; VI-NEXT:  .LBB30_11: ; %frem.else
; VI-NEXT:    v_mov_b32_e32 v2, s22
; VI-NEXT:    v_mov_b32_e32 v3, s23
; VI-NEXT:    v_cmp_eq_f64_e64 s[4:5], |s[18:19]|, |v[2:3]|
; VI-NEXT:    s_and_b32 s6, s19, 0x80000000
; VI-NEXT:    s_cmp_lg_u64 s[4:5], 0
; VI-NEXT:    s_cselect_b32 s5, s6, s19
; VI-NEXT:    s_cselect_b32 s4, 0, s18
; VI-NEXT:    v_mov_b32_e32 v2, s4
; VI-NEXT:    v_mov_b32_e32 v3, s5
; VI-NEXT:    s_branch .LBB30_14
; VI-NEXT:  .LBB30_12:
; VI-NEXT:    v_mov_b32_e32 v9, v7
; VI-NEXT:    v_mov_b32_e32 v8, v6
; VI-NEXT:  .LBB30_13: ; %frem.loop_exit
; VI-NEXT:    v_subrev_u32_e32 v6, vcc, 25, v11
; VI-NEXT:    v_ldexp_f64 v[6:7], v[8:9], v6
; VI-NEXT:    s_brev_b32 s4, -2
; VI-NEXT:    v_mul_f64 v[4:5], v[6:7], v[4:5]
; VI-NEXT:    v_rndne_f64_e32 v[4:5], v[4:5]
; VI-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[2:3], v[6:7]
; VI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[4:5]
; VI-NEXT:    v_add_f64 v[2:3], v[4:5], v[2:3]
; VI-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
; VI-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; VI-NEXT:    v_ldexp_f64 v[2:3], v[2:3], v10
; VI-NEXT:    v_mov_b32_e32 v4, s19
; VI-NEXT:    v_bfi_b32 v3, s4, v3, v4
; VI-NEXT:  .LBB30_14:
; VI-NEXT:    v_mov_b32_e32 v4, 0
; VI-NEXT:    v_mov_b32_e32 v5, 0x7ff00000
; VI-NEXT:    v_cmp_lg_f64_e64 s[4:5], s[20:21], 0
; VI-NEXT:    v_cmp_nge_f64_e64 s[6:7], |s[16:17]|, v[4:5]
; VI-NEXT:    v_mov_b32_e32 v6, 0x7ff80000
; VI-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; VI-NEXT:    v_cmp_lg_f64_e64 s[4:5], s[22:23], 0
; VI-NEXT:    v_cmp_nge_f64_e64 s[6:7], |s[18:19]|, v[4:5]
; VI-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
; VI-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc
; VI-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; VI-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
; VI-NEXT:    v_cndmask_b32_e32 v3, v6, v3, vcc
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: frem_v2f64_uniform:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v0, s20
; GFX9-NEXT:    v_mov_b32_e32 v1, s21
; GFX9-NEXT:    v_cmp_gt_f64_e64 vcc, |s[16:17]|, |v[0:1]|
; GFX9-NEXT:    s_cbranch_vccz .LBB30_4
; GFX9-NEXT:  ; %bb.1: ; %frem.compute15
; GFX9-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[16:17]|
; GFX9-NEXT:    v_frexp_exp_i32_f64_e32 v7, s[20:21]
; GFX9-NEXT:    v_frexp_exp_i32_f64_e32 v6, s[16:17]
; GFX9-NEXT:    v_ldexp_f64 v[4:5], v[0:1], 26
; GFX9-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[20:21]|
; GFX9-NEXT:    v_add_u32_e32 v8, -1, v7
; GFX9-NEXT:    v_not_b32_e32 v2, v8
; GFX9-NEXT:    v_add_u32_e32 v9, v2, v6
; GFX9-NEXT:    v_ldexp_f64 v[0:1], v[0:1], 1
; GFX9-NEXT:    v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], 1.0
; GFX9-NEXT:    v_rcp_f64_e32 v[10:11], v[2:3]
; GFX9-NEXT:    v_fma_f64 v[12:13], -v[2:3], v[10:11], 1.0
; GFX9-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
; GFX9-NEXT:    v_fma_f64 v[12:13], -v[2:3], v[10:11], 1.0
; GFX9-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
; GFX9-NEXT:    v_div_scale_f64 v[12:13], vcc, 1.0, v[0:1], 1.0
; GFX9-NEXT:    v_mul_f64 v[14:15], v[12:13], v[10:11]
; GFX9-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[14:15], v[12:13]
; GFX9-NEXT:    s_nop 1
; GFX9-NEXT:    v_div_fmas_f64 v[2:3], v[2:3], v[10:11], v[14:15]
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v9
; GFX9-NEXT:    v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0
; GFX9-NEXT:    s_cbranch_vccnz .LBB30_5
; GFX9-NEXT:  ; %bb.2: ; %frem.loop_body23.preheader
; GFX9-NEXT:    v_sub_u32_e32 v6, v6, v7
; GFX9-NEXT:    v_add_u32_e32 v9, 26, v6
; GFX9-NEXT:  .LBB30_3: ; %frem.loop_body23
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v7, v5
; GFX9-NEXT:    v_mov_b32_e32 v6, v4
; GFX9-NEXT:    v_mul_f64 v[4:5], v[6:7], v[2:3]
; GFX9-NEXT:    v_subrev_u32_e32 v9, 26, v9
; GFX9-NEXT:    v_rndne_f64_e32 v[4:5], v[4:5]
; GFX9-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[0:1], v[6:7]
; GFX9-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[4:5]
; GFX9-NEXT:    v_add_f64 v[10:11], v[4:5], v[0:1]
; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v11, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v10, vcc
; GFX9-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v9
; GFX9-NEXT:    s_cbranch_vccnz .LBB30_3
; GFX9-NEXT:    s_branch .LBB30_6
; GFX9-NEXT:  .LBB30_4: ; %frem.else16
; GFX9-NEXT:    v_mov_b32_e32 v0, s20
; GFX9-NEXT:    v_mov_b32_e32 v1, s21
; GFX9-NEXT:    v_cmp_eq_f64_e64 s[4:5], |s[16:17]|, |v[0:1]|
; GFX9-NEXT:    s_and_b32 s6, s17, 0x80000000
; GFX9-NEXT:    s_cmp_lg_u64 s[4:5], 0
; GFX9-NEXT:    s_cselect_b32 s5, s6, s17
; GFX9-NEXT:    s_cselect_b32 s4, 0, s16
; GFX9-NEXT:    v_mov_b32_e32 v0, s4
; GFX9-NEXT:    v_mov_b32_e32 v1, s5
; GFX9-NEXT:    s_branch .LBB30_7
; GFX9-NEXT:  .LBB30_5:
; GFX9-NEXT:    v_mov_b32_e32 v7, v5
; GFX9-NEXT:    v_mov_b32_e32 v6, v4
; GFX9-NEXT:  .LBB30_6: ; %frem.loop_exit24
; GFX9-NEXT:    v_subrev_u32_e32 v4, 25, v9
; GFX9-NEXT:    v_ldexp_f64 v[4:5], v[6:7], v4
; GFX9-NEXT:    s_brev_b32 s4, -2
; GFX9-NEXT:    v_mul_f64 v[2:3], v[4:5], v[2:3]
; GFX9-NEXT:    v_rndne_f64_e32 v[2:3], v[2:3]
; GFX9-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[0:1], v[4:5]
; GFX9-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[2:3]
; GFX9-NEXT:    v_add_f64 v[0:1], v[2:3], v[0:1]
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX9-NEXT:    v_ldexp_f64 v[0:1], v[0:1], v8
; GFX9-NEXT:    v_mov_b32_e32 v2, s17
; GFX9-NEXT:    v_bfi_b32 v1, s4, v1, v2
; GFX9-NEXT:  .LBB30_7:
; GFX9-NEXT:    v_mov_b32_e32 v2, s22
; GFX9-NEXT:    v_mov_b32_e32 v3, s23
; GFX9-NEXT:    v_cmp_gt_f64_e64 vcc, |s[18:19]|, |v[2:3]|
; GFX9-NEXT:    s_cbranch_vccz .LBB30_11
; GFX9-NEXT:  ; %bb.8: ; %frem.compute
; GFX9-NEXT:    v_frexp_mant_f64_e64 v[2:3], |s[18:19]|
; GFX9-NEXT:    v_frexp_exp_i32_f64_e32 v9, s[22:23]
; GFX9-NEXT:    v_frexp_exp_i32_f64_e32 v8, s[18:19]
; GFX9-NEXT:    v_ldexp_f64 v[6:7], v[2:3], 26
; GFX9-NEXT:    v_frexp_mant_f64_e64 v[2:3], |s[22:23]|
; GFX9-NEXT:    v_add_u32_e32 v10, -1, v9
; GFX9-NEXT:    v_not_b32_e32 v4, v10
; GFX9-NEXT:    v_add_u32_e32 v11, v4, v8
; GFX9-NEXT:    v_ldexp_f64 v[2:3], v[2:3], 1
; GFX9-NEXT:    v_div_scale_f64 v[4:5], s[4:5], v[2:3], v[2:3], 1.0
; GFX9-NEXT:    v_rcp_f64_e32 v[12:13], v[4:5]
; GFX9-NEXT:    v_fma_f64 v[14:15], -v[4:5], v[12:13], 1.0
; GFX9-NEXT:    v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
; GFX9-NEXT:    v_fma_f64 v[14:15], -v[4:5], v[12:13], 1.0
; GFX9-NEXT:    v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
; GFX9-NEXT:    v_div_scale_f64 v[14:15], vcc, 1.0, v[2:3], 1.0
; GFX9-NEXT:    v_mul_f64 v[16:17], v[14:15], v[12:13]
; GFX9-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[16:17], v[14:15]
; GFX9-NEXT:    s_nop 1
; GFX9-NEXT:    v_div_fmas_f64 v[4:5], v[4:5], v[12:13], v[16:17]
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v11
; GFX9-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], 1.0
; GFX9-NEXT:    s_cbranch_vccnz .LBB30_12
; GFX9-NEXT:  ; %bb.9: ; %frem.loop_body.preheader
; GFX9-NEXT:    v_sub_u32_e32 v8, v8, v9
; GFX9-NEXT:    v_add_u32_e32 v11, 26, v8
; GFX9-NEXT:  .LBB30_10: ; %frem.loop_body
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v9, v7
; GFX9-NEXT:    v_mov_b32_e32 v8, v6
; GFX9-NEXT:    v_mul_f64 v[6:7], v[8:9], v[4:5]
; GFX9-NEXT:    v_subrev_u32_e32 v11, 26, v11
; GFX9-NEXT:    v_rndne_f64_e32 v[6:7], v[6:7]
; GFX9-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[2:3], v[8:9]
; GFX9-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[6:7]
; GFX9-NEXT:    v_add_f64 v[12:13], v[6:7], v[2:3]
; GFX9-NEXT:    v_cndmask_b32_e32 v7, v7, v13, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v6, v6, v12, vcc
; GFX9-NEXT:    v_ldexp_f64 v[6:7], v[6:7], 26
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v11
; GFX9-NEXT:    s_cbranch_vccnz .LBB30_10
; GFX9-NEXT:    s_branch .LBB30_13
; GFX9-NEXT:  .LBB30_11: ; %frem.else
; GFX9-NEXT:    v_mov_b32_e32 v2, s22
; GFX9-NEXT:    v_mov_b32_e32 v3, s23
; GFX9-NEXT:    v_cmp_eq_f64_e64 s[4:5], |s[18:19]|, |v[2:3]|
; GFX9-NEXT:    s_and_b32 s6, s19, 0x80000000
; GFX9-NEXT:    s_cmp_lg_u64 s[4:5], 0
; GFX9-NEXT:    s_cselect_b32 s5, s6, s19
; GFX9-NEXT:    s_cselect_b32 s4, 0, s18
; GFX9-NEXT:    v_mov_b32_e32 v2, s4
; GFX9-NEXT:    v_mov_b32_e32 v3, s5
; GFX9-NEXT:    s_branch .LBB30_14
; GFX9-NEXT:  .LBB30_12:
; GFX9-NEXT:    v_mov_b32_e32 v9, v7
; GFX9-NEXT:    v_mov_b32_e32 v8, v6
; GFX9-NEXT:  .LBB30_13: ; %frem.loop_exit
; GFX9-NEXT:    v_subrev_u32_e32 v6, 25, v11
; GFX9-NEXT:    v_ldexp_f64 v[6:7], v[8:9], v6
; GFX9-NEXT:    s_brev_b32 s4, -2
; GFX9-NEXT:    v_mul_f64 v[4:5], v[6:7], v[4:5]
; GFX9-NEXT:    v_rndne_f64_e32 v[4:5], v[4:5]
; GFX9-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[2:3], v[6:7]
; GFX9-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[4:5]
; GFX9-NEXT:    v_add_f64 v[2:3], v[4:5], v[2:3]
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX9-NEXT:    v_ldexp_f64 v[2:3], v[2:3], v10
; GFX9-NEXT:    v_mov_b32_e32 v4, s19
; GFX9-NEXT:    v_bfi_b32 v3, s4, v3, v4
; GFX9-NEXT:  .LBB30_14:
; GFX9-NEXT:    v_mov_b32_e32 v4, 0
; GFX9-NEXT:    v_mov_b32_e32 v5, 0x7ff00000
; GFX9-NEXT:    v_cmp_lg_f64_e64 s[4:5], s[20:21], 0
; GFX9-NEXT:    v_cmp_nge_f64_e64 s[6:7], |s[16:17]|, v[4:5]
; GFX9-NEXT:    v_mov_b32_e32 v6, 0x7ff80000
; GFX9-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; GFX9-NEXT:    v_cmp_lg_f64_e64 s[4:5], s[22:23], 0
; GFX9-NEXT:    v_cmp_nge_f64_e64 s[6:7], |s[18:19]|, v[4:5]
; GFX9-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc
; GFX9-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
; GFX9-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v6, v3, vcc
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: frem_v2f64_uniform:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cmp_gt_f64_e64 vcc_lo, |s[16:17]|, |s[20:21]|
; GFX10-NEXT:    s_cbranch_vccz .LBB30_5
; GFX10-NEXT:  ; %bb.1: ; %frem.compute15
; GFX10-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[16:17]|
; GFX10-NEXT:    v_frexp_exp_i32_f64_e32 v3, s[20:21]
; GFX10-NEXT:    v_frexp_exp_i32_f64_e32 v2, s[16:17]
; GFX10-NEXT:    v_ldexp_f64 v[4:5], v[0:1], 26
; GFX10-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[20:21]|
; GFX10-NEXT:    v_add_nc_u32_e32 v8, -1, v3
; GFX10-NEXT:    v_readfirstlane_b32 s5, v3
; GFX10-NEXT:    v_readfirstlane_b32 s4, v2
; GFX10-NEXT:    v_not_b32_e32 v3, v8
; GFX10-NEXT:    v_add_nc_u32_e32 v9, v3, v2
; GFX10-NEXT:    v_ldexp_f64 v[0:1], v[0:1], 1
; GFX10-NEXT:    v_div_scale_f64 v[2:3], s6, v[0:1], v[0:1], 1.0
; GFX10-NEXT:    v_rcp_f64_e32 v[6:7], v[2:3]
; GFX10-NEXT:    v_fma_f64 v[10:11], -v[2:3], v[6:7], 1.0
; GFX10-NEXT:    v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
; GFX10-NEXT:    v_fma_f64 v[10:11], -v[2:3], v[6:7], 1.0
; GFX10-NEXT:    v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
; GFX10-NEXT:    v_div_scale_f64 v[10:11], vcc_lo, 1.0, v[0:1], 1.0
; GFX10-NEXT:    v_mul_f64 v[12:13], v[10:11], v[6:7]
; GFX10-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[12:13], v[10:11]
; GFX10-NEXT:    v_div_fmas_f64 v[2:3], v[2:3], v[6:7], v[12:13]
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v9
; GFX10-NEXT:    v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0
; GFX10-NEXT:    s_cbranch_vccnz .LBB30_7
; GFX10-NEXT:  ; %bb.2: ; %frem.loop_body23.preheader
; GFX10-NEXT:    s_sub_i32 s4, s4, s5
; GFX10-NEXT:    s_add_i32 s4, s4, 26
; GFX10-NEXT:  .LBB30_3: ; %frem.loop_body23
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v7, v5
; GFX10-NEXT:    v_mov_b32_e32 v6, v4
; GFX10-NEXT:    s_sub_i32 s4, s4, 26
; GFX10-NEXT:    s_cmp_gt_i32 s4, 26
; GFX10-NEXT:    v_mul_f64 v[4:5], v[6:7], v[2:3]
; GFX10-NEXT:    v_rndne_f64_e32 v[4:5], v[4:5]
; GFX10-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[0:1], v[6:7]
; GFX10-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
; GFX10-NEXT:    v_add_f64 v[9:10], v[4:5], v[0:1]
; GFX10-NEXT:    v_cndmask_b32_e32 v5, v5, v10, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v4, v4, v9, vcc_lo
; GFX10-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; GFX10-NEXT:    s_cbranch_scc1 .LBB30_3
; GFX10-NEXT:  ; %bb.4:
; GFX10-NEXT:    v_mov_b32_e32 v9, s4
; GFX10-NEXT:    s_branch .LBB30_8
; GFX10-NEXT:  .LBB30_5: ; %frem.else16
; GFX10-NEXT:    v_cmp_eq_f64_e64 s5, |s[16:17]|, |s[20:21]|
; GFX10-NEXT:    s_and_b32 s4, s17, 0x80000000
; GFX10-NEXT:    s_cmp_lg_u32 s5, 0
; GFX10-NEXT:    s_cselect_b32 s5, s4, s17
; GFX10-NEXT:    s_cselect_b32 s4, 0, s16
; GFX10-NEXT:    v_mov_b32_e32 v1, s5
; GFX10-NEXT:    v_mov_b32_e32 v0, s4
; GFX10-NEXT:    v_cmp_gt_f64_e64 vcc_lo, |s[18:19]|, |s[22:23]|
; GFX10-NEXT:    s_cbranch_vccnz .LBB30_9
; GFX10-NEXT:  .LBB30_6: ; %frem.else
; GFX10-NEXT:    v_cmp_eq_f64_e64 s5, |s[18:19]|, |s[22:23]|
; GFX10-NEXT:    s_and_b32 s4, s19, 0x80000000
; GFX10-NEXT:    s_cmp_lg_u32 s5, 0
; GFX10-NEXT:    s_cselect_b32 s5, s4, s19
; GFX10-NEXT:    s_cselect_b32 s4, 0, s18
; GFX10-NEXT:    v_mov_b32_e32 v3, s5
; GFX10-NEXT:    v_mov_b32_e32 v2, s4
; GFX10-NEXT:    s_branch .LBB30_15
; GFX10-NEXT:  .LBB30_7:
; GFX10-NEXT:    v_mov_b32_e32 v7, v5
; GFX10-NEXT:    v_mov_b32_e32 v6, v4
; GFX10-NEXT:  .LBB30_8: ; %frem.loop_exit24
; GFX10-NEXT:    v_subrev_nc_u32_e32 v4, 25, v9
; GFX10-NEXT:    v_ldexp_f64 v[4:5], v[6:7], v4
; GFX10-NEXT:    v_mul_f64 v[2:3], v[4:5], v[2:3]
; GFX10-NEXT:    v_rndne_f64_e32 v[2:3], v[2:3]
; GFX10-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[0:1], v[4:5]
; GFX10-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[2:3]
; GFX10-NEXT:    v_add_f64 v[0:1], v[2:3], v[0:1]
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-NEXT:    v_ldexp_f64 v[0:1], v[0:1], v8
; GFX10-NEXT:    v_bfi_b32 v1, 0x7fffffff, v1, s17
; GFX10-NEXT:    v_cmp_gt_f64_e64 vcc_lo, |s[18:19]|, |s[22:23]|
; GFX10-NEXT:    s_cbranch_vccz .LBB30_6
; GFX10-NEXT:  .LBB30_9: ; %frem.compute
; GFX10-NEXT:    v_frexp_mant_f64_e64 v[2:3], |s[18:19]|
; GFX10-NEXT:    v_frexp_exp_i32_f64_e32 v5, s[22:23]
; GFX10-NEXT:    v_frexp_exp_i32_f64_e32 v4, s[18:19]
; GFX10-NEXT:    v_ldexp_f64 v[6:7], v[2:3], 26
; GFX10-NEXT:    v_frexp_mant_f64_e64 v[2:3], |s[22:23]|
; GFX10-NEXT:    v_add_nc_u32_e32 v10, -1, v5
; GFX10-NEXT:    v_readfirstlane_b32 s5, v5
; GFX10-NEXT:    v_readfirstlane_b32 s4, v4
; GFX10-NEXT:    v_not_b32_e32 v5, v10
; GFX10-NEXT:    v_add_nc_u32_e32 v11, v5, v4
; GFX10-NEXT:    v_ldexp_f64 v[2:3], v[2:3], 1
; GFX10-NEXT:    v_div_scale_f64 v[4:5], s6, v[2:3], v[2:3], 1.0
; GFX10-NEXT:    v_rcp_f64_e32 v[8:9], v[4:5]
; GFX10-NEXT:    v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0
; GFX10-NEXT:    v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
; GFX10-NEXT:    v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0
; GFX10-NEXT:    v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
; GFX10-NEXT:    v_div_scale_f64 v[12:13], vcc_lo, 1.0, v[2:3], 1.0
; GFX10-NEXT:    v_mul_f64 v[14:15], v[12:13], v[8:9]
; GFX10-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[14:15], v[12:13]
; GFX10-NEXT:    v_div_fmas_f64 v[4:5], v[4:5], v[8:9], v[14:15]
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v11
; GFX10-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], 1.0
; GFX10-NEXT:    s_cbranch_vccnz .LBB30_13
; GFX10-NEXT:  ; %bb.10: ; %frem.loop_body.preheader
; GFX10-NEXT:    s_sub_i32 s4, s4, s5
; GFX10-NEXT:    s_add_i32 s4, s4, 26
; GFX10-NEXT:  .LBB30_11: ; %frem.loop_body
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v9, v7
; GFX10-NEXT:    v_mov_b32_e32 v8, v6
; GFX10-NEXT:    s_sub_i32 s4, s4, 26
; GFX10-NEXT:    s_cmp_gt_i32 s4, 26
; GFX10-NEXT:    v_mul_f64 v[6:7], v[8:9], v[4:5]
; GFX10-NEXT:    v_rndne_f64_e32 v[6:7], v[6:7]
; GFX10-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[2:3], v[8:9]
; GFX10-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX10-NEXT:    v_add_f64 v[11:12], v[6:7], v[2:3]
; GFX10-NEXT:    v_cndmask_b32_e32 v7, v7, v12, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v6, v6, v11, vcc_lo
; GFX10-NEXT:    v_ldexp_f64 v[6:7], v[6:7], 26
; GFX10-NEXT:    s_cbranch_scc1 .LBB30_11
; GFX10-NEXT:  ; %bb.12:
; GFX10-NEXT:    v_mov_b32_e32 v11, s4
; GFX10-NEXT:    s_branch .LBB30_14
; GFX10-NEXT:  .LBB30_13:
; GFX10-NEXT:    v_mov_b32_e32 v9, v7
; GFX10-NEXT:    v_mov_b32_e32 v8, v6
; GFX10-NEXT:  .LBB30_14: ; %frem.loop_exit
; GFX10-NEXT:    v_subrev_nc_u32_e32 v6, 25, v11
; GFX10-NEXT:    v_ldexp_f64 v[6:7], v[8:9], v6
; GFX10-NEXT:    v_mul_f64 v[4:5], v[6:7], v[4:5]
; GFX10-NEXT:    v_rndne_f64_e32 v[4:5], v[4:5]
; GFX10-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[2:3], v[6:7]
; GFX10-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
; GFX10-NEXT:    v_add_f64 v[2:3], v[4:5], v[2:3]
; GFX10-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc_lo
; GFX10-NEXT:    v_ldexp_f64 v[2:3], v[2:3], v10
; GFX10-NEXT:    v_bfi_b32 v3, 0x7fffffff, v3, s19
; GFX10-NEXT:  .LBB30_15:
; GFX10-NEXT:    v_cmp_lg_f64_e64 s4, s[20:21], 0
; GFX10-NEXT:    v_cmp_nge_f64_e64 s5, |s[16:17]|, 0x7ff00000
; GFX10-NEXT:    s_and_b32 vcc_lo, s5, s4
; GFX10-NEXT:    v_cmp_lg_f64_e64 s4, s[22:23], 0
; GFX10-NEXT:    v_cmp_nge_f64_e64 s5, |s[18:19]|, 0x7ff00000
; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v1, 0x7ff80000, v1, vcc_lo
; GFX10-NEXT:    s_and_b32 vcc_lo, s5, s4
; GFX10-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v3, 0x7ff80000, v3, vcc_lo
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: frem_v2f64_uniform:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cmp_gt_f64_e64 vcc_lo, |s[0:1]|, |s[16:17]|
; GFX11-NEXT:    s_cbranch_vccz .LBB30_5
; GFX11-NEXT:  ; %bb.1: ; %frem.compute15
; GFX11-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[0:1]|
; GFX11-NEXT:    v_frexp_exp_i32_f64_e32 v3, s[16:17]
; GFX11-NEXT:    v_frexp_exp_i32_f64_e32 v2, s[0:1]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_ldexp_f64 v[4:5], v[0:1], 26
; GFX11-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[16:17]|
; GFX11-NEXT:    v_add_nc_u32_e32 v8, -1, v3
; GFX11-NEXT:    v_readfirstlane_b32 s5, v3
; GFX11-NEXT:    v_readfirstlane_b32 s4, v2
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_not_b32_e32 v3, v8
; GFX11-NEXT:    v_add_nc_u32_e32 v9, v3, v2
; GFX11-NEXT:    v_ldexp_f64 v[0:1], v[0:1], 1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_div_scale_f64 v[2:3], null, v[0:1], v[0:1], 1.0
; GFX11-NEXT:    v_rcp_f64_e32 v[6:7], v[2:3]
; GFX11-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT:    v_fma_f64 v[10:11], -v[2:3], v[6:7], 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
; GFX11-NEXT:    v_fma_f64 v[10:11], -v[2:3], v[6:7], 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
; GFX11-NEXT:    v_div_scale_f64 v[10:11], vcc_lo, 1.0, v[0:1], 1.0
; GFX11-NEXT:    v_mul_f64 v[12:13], v[10:11], v[6:7]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[12:13], v[10:11]
; GFX11-NEXT:    v_div_fmas_f64 v[2:3], v[2:3], v[6:7], v[12:13]
; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v9
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT:    v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0
; GFX11-NEXT:    s_cbranch_vccnz .LBB30_7
; GFX11-NEXT:  ; %bb.2: ; %frem.loop_body23.preheader
; GFX11-NEXT:    s_sub_i32 s4, s4, s5
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_add_i32 s4, s4, 26
; GFX11-NEXT:    .p2align 6
; GFX11-NEXT:  .LBB30_3: ; %frem.loop_body23
; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT:    v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX11-NEXT:    s_sub_i32 s4, s4, 26
; GFX11-NEXT:    s_cmp_gt_i32 s4, 26
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_mul_f64 v[4:5], v[6:7], v[2:3]
; GFX11-NEXT:    v_rndne_f64_e32 v[4:5], v[4:5]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[0:1], v[6:7]
; GFX11-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
; GFX11-NEXT:    v_add_f64 v[9:10], v[4:5], v[0:1]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_dual_cndmask_b32 v5, v5, v10 :: v_dual_cndmask_b32 v4, v4, v9
; GFX11-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; GFX11-NEXT:    s_cbranch_scc1 .LBB30_3
; GFX11-NEXT:  ; %bb.4:
; GFX11-NEXT:    v_mov_b32_e32 v9, s4
; GFX11-NEXT:    s_branch .LBB30_8
; GFX11-NEXT:  .LBB30_5: ; %frem.else16
; GFX11-NEXT:    v_cmp_eq_f64_e64 s5, |s[0:1]|, |s[16:17]|
; GFX11-NEXT:    s_and_b32 s4, s1, 0x80000000
; GFX11-NEXT:    s_cmp_lg_u32 s5, 0
; GFX11-NEXT:    s_cselect_b32 s5, s4, s1
; GFX11-NEXT:    s_cselect_b32 s4, 0, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v0, s4
; GFX11-NEXT:    v_cmp_gt_f64_e64 vcc_lo, |s[2:3]|, |s[18:19]|
; GFX11-NEXT:    s_cbranch_vccnz .LBB30_9
; GFX11-NEXT:  .LBB30_6: ; %frem.else
; GFX11-NEXT:    v_cmp_eq_f64_e64 s5, |s[2:3]|, |s[18:19]|
; GFX11-NEXT:    s_and_b32 s4, s3, 0x80000000
; GFX11-NEXT:    s_cmp_lg_u32 s5, 0
; GFX11-NEXT:    s_cselect_b32 s5, s4, s3
; GFX11-NEXT:    s_cselect_b32 s4, 0, s2
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    v_dual_mov_b32 v3, s5 :: v_dual_mov_b32 v2, s4
; GFX11-NEXT:    s_branch .LBB30_15
; GFX11-NEXT:  .LBB30_7:
; GFX11-NEXT:    v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX11-NEXT:  .LBB30_8: ; %frem.loop_exit24
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_subrev_nc_u32_e32 v4, 25, v9
; GFX11-NEXT:    v_ldexp_f64 v[4:5], v[6:7], v4
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_mul_f64 v[2:3], v[4:5], v[2:3]
; GFX11-NEXT:    v_rndne_f64_e32 v[2:3], v[2:3]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[0:1], v[4:5]
; GFX11-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[2:3]
; GFX11-NEXT:    v_add_f64 v[0:1], v[2:3], v[0:1]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_dual_cndmask_b32 v1, v3, v1 :: v_dual_cndmask_b32 v0, v2, v0
; GFX11-NEXT:    v_ldexp_f64 v[0:1], v[0:1], v8
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_bfi_b32 v1, 0x7fffffff, v1, s1
; GFX11-NEXT:    v_cmp_gt_f64_e64 vcc_lo, |s[2:3]|, |s[18:19]|
; GFX11-NEXT:    s_cbranch_vccz .LBB30_6
; GFX11-NEXT:  .LBB30_9: ; %frem.compute
; GFX11-NEXT:    v_frexp_mant_f64_e64 v[2:3], |s[2:3]|
; GFX11-NEXT:    v_frexp_exp_i32_f64_e32 v5, s[18:19]
; GFX11-NEXT:    v_frexp_exp_i32_f64_e32 v4, s[2:3]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_ldexp_f64 v[6:7], v[2:3], 26
; GFX11-NEXT:    v_frexp_mant_f64_e64 v[2:3], |s[18:19]|
; GFX11-NEXT:    v_add_nc_u32_e32 v10, -1, v5
; GFX11-NEXT:    v_readfirstlane_b32 s5, v5
; GFX11-NEXT:    v_readfirstlane_b32 s4, v4
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_not_b32_e32 v5, v10
; GFX11-NEXT:    v_add_nc_u32_e32 v11, v5, v4
; GFX11-NEXT:    v_ldexp_f64 v[2:3], v[2:3], 1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], 1.0
; GFX11-NEXT:    v_rcp_f64_e32 v[8:9], v[4:5]
; GFX11-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT:    v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
; GFX11-NEXT:    v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
; GFX11-NEXT:    v_div_scale_f64 v[12:13], vcc_lo, 1.0, v[2:3], 1.0
; GFX11-NEXT:    v_mul_f64 v[14:15], v[12:13], v[8:9]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[14:15], v[12:13]
; GFX11-NEXT:    v_div_fmas_f64 v[4:5], v[4:5], v[8:9], v[14:15]
; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v11
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], 1.0
; GFX11-NEXT:    s_cbranch_vccnz .LBB30_13
; GFX11-NEXT:  ; %bb.10: ; %frem.loop_body.preheader
; GFX11-NEXT:    s_sub_i32 s4, s4, s5
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_add_i32 s4, s4, 26
; GFX11-NEXT:    .p2align 6
; GFX11-NEXT:  .LBB30_11: ; %frem.loop_body
; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT:    v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
; GFX11-NEXT:    s_sub_i32 s4, s4, 26
; GFX11-NEXT:    s_cmp_gt_i32 s4, 26
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_mul_f64 v[6:7], v[8:9], v[4:5]
; GFX11-NEXT:    v_rndne_f64_e32 v[6:7], v[6:7]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[2:3], v[8:9]
; GFX11-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX11-NEXT:    v_add_f64 v[11:12], v[6:7], v[2:3]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_dual_cndmask_b32 v7, v7, v12 :: v_dual_cndmask_b32 v6, v6, v11
; GFX11-NEXT:    v_ldexp_f64 v[6:7], v[6:7], 26
; GFX11-NEXT:    s_cbranch_scc1 .LBB30_11
; GFX11-NEXT:  ; %bb.12:
; GFX11-NEXT:    v_mov_b32_e32 v11, s4
; GFX11-NEXT:    s_branch .LBB30_14
; GFX11-NEXT:  .LBB30_13:
; GFX11-NEXT:    v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
; GFX11-NEXT:  .LBB30_14: ; %frem.loop_exit
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_subrev_nc_u32_e32 v6, 25, v11
; GFX11-NEXT:    v_ldexp_f64 v[6:7], v[8:9], v6
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_mul_f64 v[4:5], v[6:7], v[4:5]
; GFX11-NEXT:    v_rndne_f64_e32 v[4:5], v[4:5]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[2:3], v[6:7]
; GFX11-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
; GFX11-NEXT:    v_add_f64 v[2:3], v[4:5], v[2:3]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_dual_cndmask_b32 v3, v5, v3 :: v_dual_cndmask_b32 v2, v4, v2
; GFX11-NEXT:    v_ldexp_f64 v[2:3], v[2:3], v10
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_bfi_b32 v3, 0x7fffffff, v3, s3
; GFX11-NEXT:  .LBB30_15:
; GFX11-NEXT:    v_cmp_lg_f64_e64 s4, s[16:17], 0
; GFX11-NEXT:    v_cmp_nge_f64_e64 s0, |s[0:1]|, 0x7ff00000
; GFX11-NEXT:    v_cmp_nge_f64_e64 s1, |s[2:3]|, 0x7ff00000
; GFX11-NEXT:    s_and_b32 vcc_lo, s0, s4
; GFX11-NEXT:    v_cmp_lg_f64_e64 s0, s[18:19], 0
; GFX11-NEXT:    v_dual_cndmask_b32 v0, 0, v0 :: v_dual_cndmask_b32 v1, 0x7ff80000, v1
; GFX11-NEXT:    s_and_b32 vcc_lo, s1, s0
; GFX11-NEXT:    v_dual_cndmask_b32 v2, 0, v2 :: v_dual_cndmask_b32 v3, 0x7ff80000, v3
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-LABEL: frem_v2f64_uniform:
; GFX1150:       ; %bb.0:
; GFX1150-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-NEXT:    v_cmp_gt_f64_e64 vcc_lo, |s[0:1]|, |s[16:17]|
; GFX1150-NEXT:    s_cbranch_vccz .LBB30_5
; GFX1150-NEXT:  ; %bb.1: ; %frem.compute15
; GFX1150-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[0:1]|
; GFX1150-NEXT:    v_frexp_exp_i32_f64_e32 v3, s[16:17]
; GFX1150-NEXT:    v_frexp_exp_i32_f64_e32 v2, s[0:1]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1150-NEXT:    v_ldexp_f64 v[4:5], v[0:1], 26
; GFX1150-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[16:17]|
; GFX1150-NEXT:    v_add_nc_u32_e32 v8, -1, v3
; GFX1150-NEXT:    v_readfirstlane_b32 s5, v3
; GFX1150-NEXT:    v_readfirstlane_b32 s4, v2
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_not_b32_e32 v3, v8
; GFX1150-NEXT:    v_add_nc_u32_e32 v9, v3, v2
; GFX1150-NEXT:    v_ldexp_f64 v[0:1], v[0:1], 1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_div_scale_f64 v[2:3], null, v[0:1], v[0:1], 1.0
; GFX1150-NEXT:    v_rcp_f64_e32 v[6:7], v[2:3]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[10:11], -v[2:3], v[6:7], 1.0
; GFX1150-NEXT:    v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[10:11], -v[2:3], v[6:7], 1.0
; GFX1150-NEXT:    v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
; GFX1150-NEXT:    v_div_scale_f64 v[10:11], vcc_lo, 1.0, v[0:1], 1.0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f64 v[12:13], v[10:11], v[6:7]
; GFX1150-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[12:13], v[10:11]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-NEXT:    v_div_fmas_f64 v[2:3], v[2:3], v[6:7], v[12:13]
; GFX1150-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v9
; GFX1150-NEXT:    v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0
; GFX1150-NEXT:    s_cbranch_vccnz .LBB30_7
; GFX1150-NEXT:  ; %bb.2: ; %frem.loop_body23.preheader
; GFX1150-NEXT:    s_sub_i32 s4, s4, s5
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_add_i32 s4, s4, 26
; GFX1150-NEXT:    .p2align 6
; GFX1150-NEXT:  .LBB30_3: ; %frem.loop_body23
; GFX1150-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT:    v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX1150-NEXT:    s_sub_i32 s4, s4, 26
; GFX1150-NEXT:    s_cmp_gt_i32 s4, 26
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f64 v[4:5], v[6:7], v[2:3]
; GFX1150-NEXT:    v_rndne_f64_e32 v[4:5], v[4:5]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[0:1], v[6:7]
; GFX1150-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
; GFX1150-NEXT:    v_add_f64 v[9:10], v[4:5], v[0:1]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_dual_cndmask_b32 v5, v5, v10 :: v_dual_cndmask_b32 v4, v4, v9
; GFX1150-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; GFX1150-NEXT:    s_cbranch_scc1 .LBB30_3
; GFX1150-NEXT:  ; %bb.4:
; GFX1150-NEXT:    v_mov_b32_e32 v9, s4
; GFX1150-NEXT:    s_branch .LBB30_8
; GFX1150-NEXT:  .LBB30_5: ; %frem.else16
; GFX1150-NEXT:    v_cmp_eq_f64_e64 s5, |s[0:1]|, |s[16:17]|
; GFX1150-NEXT:    s_and_b32 s4, s1, 0x80000000
; GFX1150-NEXT:    s_cmp_lg_u32 s5, 0
; GFX1150-NEXT:    s_cselect_b32 s5, s4, s1
; GFX1150-NEXT:    s_cselect_b32 s4, 0, s0
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v0, s4
; GFX1150-NEXT:    v_cmp_gt_f64_e64 vcc_lo, |s[2:3]|, |s[18:19]|
; GFX1150-NEXT:    s_cbranch_vccnz .LBB30_9
; GFX1150-NEXT:  .LBB30_6: ; %frem.else
; GFX1150-NEXT:    v_cmp_eq_f64_e64 s5, |s[2:3]|, |s[18:19]|
; GFX1150-NEXT:    s_and_b32 s4, s3, 0x80000000
; GFX1150-NEXT:    s_cmp_lg_u32 s5, 0
; GFX1150-NEXT:    s_cselect_b32 s5, s4, s3
; GFX1150-NEXT:    s_cselect_b32 s4, 0, s2
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    v_dual_mov_b32 v3, s5 :: v_dual_mov_b32 v2, s4
; GFX1150-NEXT:    s_branch .LBB30_15
; GFX1150-NEXT:  .LBB30_7:
; GFX1150-NEXT:    v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX1150-NEXT:  .LBB30_8: ; %frem.loop_exit24
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_subrev_nc_u32_e32 v4, 25, v9
; GFX1150-NEXT:    v_ldexp_f64 v[4:5], v[6:7], v4
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f64 v[2:3], v[4:5], v[2:3]
; GFX1150-NEXT:    v_rndne_f64_e32 v[2:3], v[2:3]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[0:1], v[4:5]
; GFX1150-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[2:3]
; GFX1150-NEXT:    v_add_f64 v[0:1], v[2:3], v[0:1]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_dual_cndmask_b32 v1, v3, v1 :: v_dual_cndmask_b32 v0, v2, v0
; GFX1150-NEXT:    v_ldexp_f64 v[0:1], v[0:1], v8
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_bfi_b32 v1, 0x7fffffff, v1, s1
; GFX1150-NEXT:    v_cmp_gt_f64_e64 vcc_lo, |s[2:3]|, |s[18:19]|
; GFX1150-NEXT:    s_cbranch_vccz .LBB30_6
; GFX1150-NEXT:  .LBB30_9: ; %frem.compute
; GFX1150-NEXT:    v_frexp_mant_f64_e64 v[2:3], |s[2:3]|
; GFX1150-NEXT:    v_frexp_exp_i32_f64_e32 v5, s[18:19]
; GFX1150-NEXT:    v_frexp_exp_i32_f64_e32 v4, s[2:3]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1150-NEXT:    v_ldexp_f64 v[6:7], v[2:3], 26
; GFX1150-NEXT:    v_frexp_mant_f64_e64 v[2:3], |s[18:19]|
; GFX1150-NEXT:    v_add_nc_u32_e32 v10, -1, v5
; GFX1150-NEXT:    v_readfirstlane_b32 s5, v5
; GFX1150-NEXT:    v_readfirstlane_b32 s4, v4
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_not_b32_e32 v5, v10
; GFX1150-NEXT:    v_add_nc_u32_e32 v11, v5, v4
; GFX1150-NEXT:    v_ldexp_f64 v[2:3], v[2:3], 1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], 1.0
; GFX1150-NEXT:    v_rcp_f64_e32 v[8:9], v[4:5]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0
; GFX1150-NEXT:    v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0
; GFX1150-NEXT:    v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
; GFX1150-NEXT:    v_div_scale_f64 v[12:13], vcc_lo, 1.0, v[2:3], 1.0
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f64 v[14:15], v[12:13], v[8:9]
; GFX1150-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[14:15], v[12:13]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-NEXT:    v_div_fmas_f64 v[4:5], v[4:5], v[8:9], v[14:15]
; GFX1150-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v11
; GFX1150-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], 1.0
; GFX1150-NEXT:    s_cbranch_vccnz .LBB30_13
; GFX1150-NEXT:  ; %bb.10: ; %frem.loop_body.preheader
; GFX1150-NEXT:    s_sub_i32 s4, s4, s5
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    s_add_i32 s4, s4, 26
; GFX1150-NEXT:    .p2align 6
; GFX1150-NEXT:  .LBB30_11: ; %frem.loop_body
; GFX1150-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT:    v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
; GFX1150-NEXT:    s_sub_i32 s4, s4, 26
; GFX1150-NEXT:    s_cmp_gt_i32 s4, 26
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f64 v[6:7], v[8:9], v[4:5]
; GFX1150-NEXT:    v_rndne_f64_e32 v[6:7], v[6:7]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[2:3], v[8:9]
; GFX1150-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX1150-NEXT:    v_add_f64 v[11:12], v[6:7], v[2:3]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_dual_cndmask_b32 v7, v7, v12 :: v_dual_cndmask_b32 v6, v6, v11
; GFX1150-NEXT:    v_ldexp_f64 v[6:7], v[6:7], 26
; GFX1150-NEXT:    s_cbranch_scc1 .LBB30_11
; GFX1150-NEXT:  ; %bb.12:
; GFX1150-NEXT:    v_mov_b32_e32 v11, s4
; GFX1150-NEXT:    s_branch .LBB30_14
; GFX1150-NEXT:  .LBB30_13:
; GFX1150-NEXT:    v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
; GFX1150-NEXT:  .LBB30_14: ; %frem.loop_exit
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_subrev_nc_u32_e32 v6, 25, v11
; GFX1150-NEXT:    v_ldexp_f64 v[6:7], v[8:9], v6
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_mul_f64 v[4:5], v[6:7], v[4:5]
; GFX1150-NEXT:    v_rndne_f64_e32 v[4:5], v[4:5]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[2:3], v[6:7]
; GFX1150-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
; GFX1150-NEXT:    v_add_f64 v[2:3], v[4:5], v[2:3]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_dual_cndmask_b32 v3, v5, v3 :: v_dual_cndmask_b32 v2, v4, v2
; GFX1150-NEXT:    v_ldexp_f64 v[2:3], v[2:3], v10
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_bfi_b32 v3, 0x7fffffff, v3, s3
; GFX1150-NEXT:  .LBB30_15:
; GFX1150-NEXT:    v_cmp_lg_f64_e64 s4, s[16:17], 0
; GFX1150-NEXT:    v_cmp_nge_f64_e64 s0, |s[0:1]|, 0x7ff00000
; GFX1150-NEXT:    v_cmp_nge_f64_e64 s1, |s[2:3]|, 0x7ff00000
; GFX1150-NEXT:    s_and_b32 vcc_lo, s0, s4
; GFX1150-NEXT:    v_cmp_lg_f64_e64 s0, s[18:19], 0
; GFX1150-NEXT:    v_dual_cndmask_b32 v0, 0, v0 :: v_dual_cndmask_b32 v1, 0x7ff80000, v1
; GFX1150-NEXT:    s_and_b32 vcc_lo, s1, s0
; GFX1150-NEXT:    v_dual_cndmask_b32 v2, 0, v2 :: v_dual_cndmask_b32 v3, 0x7ff80000, v3
; GFX1150-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: frem_v2f64_uniform:
; GFX1200:       ; %bb.0:
; GFX1200-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT:    s_wait_expcnt 0x0
; GFX1200-NEXT:    s_wait_samplecnt 0x0
; GFX1200-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-NEXT:    s_wait_kmcnt 0x0
; GFX1200-NEXT:    v_cmp_gt_f64_e64 vcc_lo, |s[0:1]|, |s[16:17]|
; GFX1200-NEXT:    s_cbranch_vccz .LBB30_5
; GFX1200-NEXT:  ; %bb.1: ; %frem.compute15
; GFX1200-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[0:1]|
; GFX1200-NEXT:    v_frexp_exp_i32_f64_e32 v3, s[16:17]
; GFX1200-NEXT:    v_frexp_exp_i32_f64_e32 v2, s[0:1]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1200-NEXT:    v_ldexp_f64 v[4:5], v[0:1], 26
; GFX1200-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[16:17]|
; GFX1200-NEXT:    v_add_nc_u32_e32 v8, -1, v3
; GFX1200-NEXT:    v_readfirstlane_b32 s5, v3
; GFX1200-NEXT:    v_readfirstlane_b32 s4, v2
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_not_b32_e32 v3, v8
; GFX1200-NEXT:    v_add_nc_u32_e32 v9, v3, v2
; GFX1200-NEXT:    v_ldexp_f64 v[0:1], v[0:1], 1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_div_scale_f64 v[2:3], null, v[0:1], v[0:1], 1.0
; GFX1200-NEXT:    v_rcp_f64_e32 v[6:7], v[2:3]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f64 v[10:11], -v[2:3], v[6:7], 1.0
; GFX1200-NEXT:    v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f64 v[10:11], -v[2:3], v[6:7], 1.0
; GFX1200-NEXT:    v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
; GFX1200-NEXT:    v_div_scale_f64 v[10:11], vcc_lo, 1.0, v[0:1], 1.0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_mul_f64_e32 v[12:13], v[10:11], v[6:7]
; GFX1200-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[12:13], v[10:11]
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT:    v_div_fmas_f64 v[2:3], v[2:3], v[6:7], v[12:13]
; GFX1200-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v9
; GFX1200-NEXT:    v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0
; GFX1200-NEXT:    s_cbranch_vccnz .LBB30_7
; GFX1200-NEXT:  ; %bb.2: ; %frem.loop_body23.preheader
; GFX1200-NEXT:    s_sub_co_i32 s4, s4, s5
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_add_co_i32 s4, s4, 26
; GFX1200-NEXT:  .LBB30_3: ; %frem.loop_body23
; GFX1200-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX1200-NEXT:    v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_sub_co_i32 s4, s4, 26
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_cmp_gt_i32 s4, 26
; GFX1200-NEXT:    v_mul_f64_e32 v[4:5], v[6:7], v[2:3]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_rndne_f64_e32 v[4:5], v[4:5]
; GFX1200-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[0:1], v[6:7]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
; GFX1200-NEXT:    v_add_f64_e32 v[9:10], v[4:5], v[0:1]
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_dual_cndmask_b32 v5, v5, v10 :: v_dual_cndmask_b32 v4, v4, v9
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; GFX1200-NEXT:    s_cbranch_scc1 .LBB30_3
; GFX1200-NEXT:  ; %bb.4:
; GFX1200-NEXT:    v_mov_b32_e32 v9, s4
; GFX1200-NEXT:    s_branch .LBB30_8
; GFX1200-NEXT:  .LBB30_5: ; %frem.else16
; GFX1200-NEXT:    v_cmp_eq_f64_e64 s5, |s[0:1]|, |s[16:17]|
; GFX1200-NEXT:    s_and_b32 s4, s1, 0x80000000
; GFX1200-NEXT:    s_cmp_lg_u32 s5, 0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_cselect_b32 s5, s4, s1
; GFX1200-NEXT:    s_cselect_b32 s4, 0, s0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v0, s4
; GFX1200-NEXT:    v_cmp_gt_f64_e64 vcc_lo, |s[2:3]|, |s[18:19]|
; GFX1200-NEXT:    s_cbranch_vccnz .LBB30_9
; GFX1200-NEXT:  .LBB30_6: ; %frem.else
; GFX1200-NEXT:    v_cmp_eq_f64_e64 s5, |s[2:3]|, |s[18:19]|
; GFX1200-NEXT:    s_and_b32 s4, s3, 0x80000000
; GFX1200-NEXT:    s_cmp_lg_u32 s5, 0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_cselect_b32 s5, s4, s3
; GFX1200-NEXT:    s_cselect_b32 s4, 0, s2
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    v_dual_mov_b32 v3, s5 :: v_dual_mov_b32 v2, s4
; GFX1200-NEXT:    s_branch .LBB30_15
; GFX1200-NEXT:  .LBB30_7:
; GFX1200-NEXT:    v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX1200-NEXT:  .LBB30_8: ; %frem.loop_exit24
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_subrev_nc_u32_e32 v4, 25, v9
; GFX1200-NEXT:    v_ldexp_f64 v[4:5], v[6:7], v4
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_mul_f64_e32 v[2:3], v[4:5], v[2:3]
; GFX1200-NEXT:    v_rndne_f64_e32 v[2:3], v[2:3]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[0:1], v[4:5]
; GFX1200-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[2:3]
; GFX1200-NEXT:    v_add_f64_e32 v[0:1], v[2:3], v[0:1]
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_dual_cndmask_b32 v1, v3, v1 :: v_dual_cndmask_b32 v0, v2, v0
; GFX1200-NEXT:    v_ldexp_f64 v[0:1], v[0:1], v8
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_bfi_b32 v1, 0x7fffffff, v1, s1
; GFX1200-NEXT:    v_cmp_gt_f64_e64 vcc_lo, |s[2:3]|, |s[18:19]|
; GFX1200-NEXT:    s_cbranch_vccz .LBB30_6
; GFX1200-NEXT:  .LBB30_9: ; %frem.compute
; GFX1200-NEXT:    v_frexp_mant_f64_e64 v[2:3], |s[2:3]|
; GFX1200-NEXT:    v_frexp_exp_i32_f64_e32 v5, s[18:19]
; GFX1200-NEXT:    v_frexp_exp_i32_f64_e32 v4, s[2:3]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1200-NEXT:    v_ldexp_f64 v[6:7], v[2:3], 26
; GFX1200-NEXT:    v_frexp_mant_f64_e64 v[2:3], |s[18:19]|
; GFX1200-NEXT:    v_add_nc_u32_e32 v10, -1, v5
; GFX1200-NEXT:    v_readfirstlane_b32 s5, v5
; GFX1200-NEXT:    v_readfirstlane_b32 s4, v4
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_not_b32_e32 v5, v10
; GFX1200-NEXT:    v_add_nc_u32_e32 v11, v5, v4
; GFX1200-NEXT:    v_ldexp_f64 v[2:3], v[2:3], 1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], 1.0
; GFX1200-NEXT:    v_rcp_f64_e32 v[8:9], v[4:5]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0
; GFX1200-NEXT:    v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0
; GFX1200-NEXT:    v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
; GFX1200-NEXT:    v_div_scale_f64 v[12:13], vcc_lo, 1.0, v[2:3], 1.0
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_mul_f64_e32 v[14:15], v[12:13], v[8:9]
; GFX1200-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[14:15], v[12:13]
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT:    v_div_fmas_f64 v[4:5], v[4:5], v[8:9], v[14:15]
; GFX1200-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v11
; GFX1200-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], 1.0
; GFX1200-NEXT:    s_cbranch_vccnz .LBB30_13
; GFX1200-NEXT:  ; %bb.10: ; %frem.loop_body.preheader
; GFX1200-NEXT:    s_sub_co_i32 s4, s4, s5
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_add_co_i32 s4, s4, 26
; GFX1200-NEXT:  .LBB30_11: ; %frem.loop_body
; GFX1200-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX1200-NEXT:    v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_sub_co_i32 s4, s4, 26
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_cmp_gt_i32 s4, 26
; GFX1200-NEXT:    v_mul_f64_e32 v[6:7], v[8:9], v[4:5]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_rndne_f64_e32 v[6:7], v[6:7]
; GFX1200-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[2:3], v[8:9]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX1200-NEXT:    v_add_f64_e32 v[11:12], v[6:7], v[2:3]
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_dual_cndmask_b32 v7, v7, v12 :: v_dual_cndmask_b32 v6, v6, v11
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_ldexp_f64 v[6:7], v[6:7], 26
; GFX1200-NEXT:    s_cbranch_scc1 .LBB30_11
; GFX1200-NEXT:  ; %bb.12:
; GFX1200-NEXT:    v_mov_b32_e32 v11, s4
; GFX1200-NEXT:    s_branch .LBB30_14
; GFX1200-NEXT:  .LBB30_13:
; GFX1200-NEXT:    v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
; GFX1200-NEXT:  .LBB30_14: ; %frem.loop_exit
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_subrev_nc_u32_e32 v6, 25, v11
; GFX1200-NEXT:    v_ldexp_f64 v[6:7], v[8:9], v6
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_mul_f64_e32 v[4:5], v[6:7], v[4:5]
; GFX1200-NEXT:    v_rndne_f64_e32 v[4:5], v[4:5]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[2:3], v[6:7]
; GFX1200-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
; GFX1200-NEXT:    v_add_f64_e32 v[2:3], v[4:5], v[2:3]
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_dual_cndmask_b32 v3, v5, v3 :: v_dual_cndmask_b32 v2, v4, v2
; GFX1200-NEXT:    v_ldexp_f64 v[2:3], v[2:3], v10
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_bfi_b32 v3, 0x7fffffff, v3, s3
; GFX1200-NEXT:  .LBB30_15:
; GFX1200-NEXT:    v_cmp_lg_f64_e64 s4, s[16:17], 0
; GFX1200-NEXT:    v_cmp_nge_f64_e64 s0, |s[0:1]|, 0x7ff00000
; GFX1200-NEXT:    v_cmp_nge_f64_e64 s1, |s[2:3]|, 0x7ff00000
; GFX1200-NEXT:    s_and_b32 vcc_lo, s0, s4
; GFX1200-NEXT:    v_cmp_lg_f64_e64 s0, s[18:19], 0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    v_dual_cndmask_b32 v0, 0, v0 :: v_dual_cndmask_b32 v1, 0x7ff80000, v1
; GFX1200-NEXT:    s_and_b32 vcc_lo, s1, s0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    v_dual_cndmask_b32 v2, 0, v2 :: v_dual_cndmask_b32 v3, 0x7ff80000, v3
; GFX1200-NEXT:    s_setpc_b64 s[30:31]
   %r2 = frem <2 x double> %in1, %in2
  ret <2 x double> %r2
}

define <2 x double> @frem_v2f64_const_one_denum_uniform(<2 x double> inreg %in) #0 {
; SI-LABEL: frem_v2f64_const_one_denum_uniform:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cmp_gt_f64_e64 vcc, |s[16:17]|, 1.0
; SI-NEXT:    s_cbranch_vccz .LBB31_4
; SI-NEXT:  ; %bb.1: ; %frem.compute15
; SI-NEXT:    s_and_b32 s4, s17, 0x7fffffff
; SI-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[16:17]|
; SI-NEXT:    s_cmp_lt_i32 s4, 0x7ff00000
; SI-NEXT:    s_cselect_b64 vcc, -1, 0
; SI-NEXT:    v_mov_b32_e32 v2, s4
; SI-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; SI-NEXT:    v_mov_b32_e32 v2, s16
; SI-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
; SI-NEXT:    v_frexp_exp_i32_f64_e32 v2, s[16:17]
; SI-NEXT:    v_ldexp_f64 v[4:5], v[0:1], 26
; SI-NEXT:    v_readfirstlane_b32 s4, v2
; SI-NEXT:    s_cselect_b32 s5, s4, 0
; SI-NEXT:    s_add_i32 s7, s5, -1
; SI-NEXT:    s_brev_b32 s6, -2
; SI-NEXT:    s_mov_b32 s4, -1
; SI-NEXT:    s_cmp_lt_i32 s7, 27
; SI-NEXT:    s_cbranch_scc1 .LBB31_6
; SI-NEXT:  ; %bb.2: ; %frem.loop_body23.preheader
; SI-NEXT:    s_add_i32 s7, s5, 25
; SI-NEXT:    v_mov_b32_e32 v6, 0x43300000
; SI-NEXT:    v_mov_b32_e32 v0, 0
; SI-NEXT:    s_mov_b32 s5, 0x432fffff
; SI-NEXT:  .LBB31_3: ; %frem.loop_body23
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v3, v5
; SI-NEXT:    v_mov_b32_e32 v2, v4
; SI-NEXT:    v_bfi_b32 v1, s6, v6, v3
; SI-NEXT:    v_add_f64 v[4:5], v[2:3], v[0:1]
; SI-NEXT:    v_cmp_gt_f64_e64 vcc, |v[2:3]|, s[4:5]
; SI-NEXT:    v_add_f64 v[4:5], v[4:5], -v[0:1]
; SI-NEXT:    s_sub_i32 s7, s7, 26
; SI-NEXT:    v_cndmask_b32_e32 v5, v5, v3, vcc
; SI-NEXT:    v_cndmask_b32_e32 v4, v4, v2, vcc
; SI-NEXT:    v_add_f64 v[4:5], v[2:3], -v[4:5]
; SI-NEXT:    s_cmp_gt_i32 s7, 26
; SI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[4:5]
; SI-NEXT:    v_add_f64 v[7:8], v[4:5], 1.0
; SI-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc
; SI-NEXT:    v_cndmask_b32_e32 v4, v4, v7, vcc
; SI-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; SI-NEXT:    s_cbranch_scc1 .LBB31_3
; SI-NEXT:    s_branch .LBB31_7
; SI-NEXT:  .LBB31_4: ; %frem.else16
; SI-NEXT:    v_cmp_eq_f64_e64 s[4:5], |s[16:17]|, 1.0
; SI-NEXT:    s_and_b32 s6, s17, 0x80000000
; SI-NEXT:    s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT:    s_cselect_b32 s5, s6, s17
; SI-NEXT:    s_cselect_b32 s4, 0, s16
; SI-NEXT:    v_mov_b32_e32 v0, s4
; SI-NEXT:    v_mov_b32_e32 v1, s5
; SI-NEXT:    v_cmp_gt_f64_e64 vcc, |s[18:19]|, 1.0
; SI-NEXT:    s_cbranch_vccnz .LBB31_8
; SI-NEXT:  .LBB31_5: ; %frem.else
; SI-NEXT:    v_cmp_eq_f64_e64 s[4:5], |s[18:19]|, 1.0
; SI-NEXT:    s_and_b32 s6, s19, 0x80000000
; SI-NEXT:    s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT:    s_cselect_b32 s5, s6, s19
; SI-NEXT:    s_cselect_b32 s4, 0, s18
; SI-NEXT:    v_mov_b32_e32 v2, s4
; SI-NEXT:    v_mov_b32_e32 v3, s5
; SI-NEXT:    s_branch .LBB31_13
; SI-NEXT:  .LBB31_6:
; SI-NEXT:    v_mov_b32_e32 v2, v4
; SI-NEXT:    v_mov_b32_e32 v3, v5
; SI-NEXT:  .LBB31_7: ; %frem.loop_exit24
; SI-NEXT:    s_sub_i32 s5, s7, 25
; SI-NEXT:    v_ldexp_f64 v[0:1], v[2:3], s5
; SI-NEXT:    v_mov_b32_e32 v2, 0x43300000
; SI-NEXT:    v_bfi_b32 v3, s6, v2, v1
; SI-NEXT:    v_mov_b32_e32 v2, 0
; SI-NEXT:    v_add_f64 v[4:5], v[0:1], v[2:3]
; SI-NEXT:    s_mov_b32 s5, 0x432fffff
; SI-NEXT:    v_cmp_gt_f64_e64 vcc, |v[0:1]|, s[4:5]
; SI-NEXT:    v_add_f64 v[2:3], v[4:5], -v[2:3]
; SI-NEXT:    v_cndmask_b32_e32 v3, v3, v1, vcc
; SI-NEXT:    v_cndmask_b32_e32 v2, v2, v0, vcc
; SI-NEXT:    v_add_f64 v[0:1], v[0:1], -v[2:3]
; SI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[0:1]
; SI-NEXT:    v_add_f64 v[2:3], v[0:1], 1.0
; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
; SI-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
; SI-NEXT:    v_mov_b32_e32 v2, s17
; SI-NEXT:    v_bfi_b32 v1, s6, v1, v2
; SI-NEXT:    v_cmp_gt_f64_e64 vcc, |s[18:19]|, 1.0
; SI-NEXT:    s_cbranch_vccz .LBB31_5
; SI-NEXT:  .LBB31_8: ; %frem.compute
; SI-NEXT:    s_and_b32 s4, s19, 0x7fffffff
; SI-NEXT:    v_frexp_mant_f64_e64 v[2:3], |s[18:19]|
; SI-NEXT:    s_cmp_lt_i32 s4, 0x7ff00000
; SI-NEXT:    s_cselect_b64 vcc, -1, 0
; SI-NEXT:    v_mov_b32_e32 v4, s4
; SI-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; SI-NEXT:    v_mov_b32_e32 v4, s18
; SI-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; SI-NEXT:    v_frexp_exp_i32_f64_e32 v4, s[18:19]
; SI-NEXT:    v_ldexp_f64 v[6:7], v[2:3], 26
; SI-NEXT:    v_readfirstlane_b32 s4, v4
; SI-NEXT:    s_cselect_b32 s5, s4, 0
; SI-NEXT:    s_add_i32 s7, s5, -1
; SI-NEXT:    s_brev_b32 s6, -2
; SI-NEXT:    s_mov_b32 s4, -1
; SI-NEXT:    s_cmp_lt_i32 s7, 27
; SI-NEXT:    s_cbranch_scc1 .LBB31_11
; SI-NEXT:  ; %bb.9: ; %frem.loop_body.preheader
; SI-NEXT:    s_add_i32 s7, s5, 25
; SI-NEXT:    v_mov_b32_e32 v8, 0x43300000
; SI-NEXT:    v_mov_b32_e32 v2, 0
; SI-NEXT:    s_mov_b32 s5, 0x432fffff
; SI-NEXT:  .LBB31_10: ; %frem.loop_body
; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
; SI-NEXT:    v_mov_b32_e32 v5, v7
; SI-NEXT:    v_mov_b32_e32 v4, v6
; SI-NEXT:    v_bfi_b32 v3, s6, v8, v5
; SI-NEXT:    v_add_f64 v[6:7], v[4:5], v[2:3]
; SI-NEXT:    v_cmp_gt_f64_e64 vcc, |v[4:5]|, s[4:5]
; SI-NEXT:    v_add_f64 v[6:7], v[6:7], -v[2:3]
; SI-NEXT:    s_sub_i32 s7, s7, 26
; SI-NEXT:    v_cndmask_b32_e32 v7, v7, v5, vcc
; SI-NEXT:    v_cndmask_b32_e32 v6, v6, v4, vcc
; SI-NEXT:    v_add_f64 v[6:7], v[4:5], -v[6:7]
; SI-NEXT:    s_cmp_gt_i32 s7, 26
; SI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[6:7]
; SI-NEXT:    v_add_f64 v[9:10], v[6:7], 1.0
; SI-NEXT:    v_cndmask_b32_e32 v7, v7, v10, vcc
; SI-NEXT:    v_cndmask_b32_e32 v6, v6, v9, vcc
; SI-NEXT:    v_ldexp_f64 v[6:7], v[6:7], 26
; SI-NEXT:    s_cbranch_scc1 .LBB31_10
; SI-NEXT:    s_branch .LBB31_12
; SI-NEXT:  .LBB31_11:
; SI-NEXT:    v_mov_b32_e32 v4, v6
; SI-NEXT:    v_mov_b32_e32 v5, v7
; SI-NEXT:  .LBB31_12: ; %frem.loop_exit
; SI-NEXT:    s_sub_i32 s5, s7, 25
; SI-NEXT:    v_ldexp_f64 v[2:3], v[4:5], s5
; SI-NEXT:    v_mov_b32_e32 v4, 0x43300000
; SI-NEXT:    v_bfi_b32 v5, s6, v4, v3
; SI-NEXT:    v_mov_b32_e32 v4, 0
; SI-NEXT:    v_add_f64 v[6:7], v[2:3], v[4:5]
; SI-NEXT:    s_mov_b32 s5, 0x432fffff
; SI-NEXT:    v_cmp_gt_f64_e64 vcc, |v[2:3]|, s[4:5]
; SI-NEXT:    v_add_f64 v[4:5], v[6:7], -v[4:5]
; SI-NEXT:    v_cndmask_b32_e32 v5, v5, v3, vcc
; SI-NEXT:    v_cndmask_b32_e32 v4, v4, v2, vcc
; SI-NEXT:    v_add_f64 v[2:3], v[2:3], -v[4:5]
; SI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[2:3]
; SI-NEXT:    v_add_f64 v[4:5], v[2:3], 1.0
; SI-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
; SI-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
; SI-NEXT:    v_mov_b32_e32 v4, s19
; SI-NEXT:    v_bfi_b32 v3, s6, v3, v4
; SI-NEXT:  .LBB31_13:
; SI-NEXT:    v_mov_b32_e32 v4, 0
; SI-NEXT:    v_mov_b32_e32 v5, 0x7ff00000
; SI-NEXT:    v_cmp_nge_f64_e64 vcc, |s[16:17]|, v[4:5]
; SI-NEXT:    v_mov_b32_e32 v6, 0x7ff80000
; SI-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
; SI-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc
; SI-NEXT:    v_cmp_nge_f64_e64 vcc, |s[18:19]|, v[4:5]
; SI-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
; SI-NEXT:    v_cndmask_b32_e32 v3, v6, v3, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; CI-LABEL: frem_v2f64_const_one_denum_uniform:
; CI:       ; %bb.0:
; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-NEXT:    v_cmp_gt_f64_e64 vcc, |s[16:17]|, 1.0
; CI-NEXT:    s_cbranch_vccz .LBB31_4
; CI-NEXT:  ; %bb.1: ; %frem.compute15
; CI-NEXT:    v_frexp_mant_f64_e64 v[1:2], |s[16:17]|
; CI-NEXT:    v_frexp_exp_i32_f64_e32 v0, s[16:17]
; CI-NEXT:    v_ldexp_f64 v[2:3], v[1:2], 26
; CI-NEXT:    v_add_i32_e32 v4, vcc, -1, v0
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v4
; CI-NEXT:    s_cbranch_vccnz .LBB31_6
; CI-NEXT:  ; %bb.2: ; %frem.loop_body23.preheader
; CI-NEXT:    v_add_i32_e32 v4, vcc, 25, v0
; CI-NEXT:  .LBB31_3: ; %frem.loop_body23
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v0, v2
; CI-NEXT:    v_mov_b32_e32 v1, v3
; CI-NEXT:    v_rndne_f64_e32 v[2:3], v[0:1]
; CI-NEXT:    v_add_f64 v[2:3], v[0:1], -v[2:3]
; CI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[2:3]
; CI-NEXT:    v_add_f64 v[5:6], v[2:3], 1.0
; CI-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc
; CI-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
; CI-NEXT:    v_ldexp_f64 v[2:3], v[2:3], 26
; CI-NEXT:    v_subrev_i32_e32 v4, vcc, 26, v4
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v4
; CI-NEXT:    s_cbranch_vccnz .LBB31_3
; CI-NEXT:    s_branch .LBB31_7
; CI-NEXT:  .LBB31_4: ; %frem.else16
; CI-NEXT:    v_cmp_eq_f64_e64 s[4:5], |s[16:17]|, 1.0
; CI-NEXT:    s_and_b32 s6, s17, 0x80000000
; CI-NEXT:    s_and_b64 s[4:5], s[4:5], exec
; CI-NEXT:    s_cselect_b32 s5, s6, s17
; CI-NEXT:    s_cselect_b32 s4, 0, s16
; CI-NEXT:    v_mov_b32_e32 v0, s4
; CI-NEXT:    v_mov_b32_e32 v1, s5
; CI-NEXT:    v_cmp_gt_f64_e64 vcc, |s[18:19]|, 1.0
; CI-NEXT:    s_cbranch_vccnz .LBB31_8
; CI-NEXT:  .LBB31_5: ; %frem.else
; CI-NEXT:    v_cmp_eq_f64_e64 s[4:5], |s[18:19]|, 1.0
; CI-NEXT:    s_and_b32 s6, s19, 0x80000000
; CI-NEXT:    s_and_b64 s[4:5], s[4:5], exec
; CI-NEXT:    s_cselect_b32 s5, s6, s19
; CI-NEXT:    s_cselect_b32 s4, 0, s18
; CI-NEXT:    v_mov_b32_e32 v2, s4
; CI-NEXT:    v_mov_b32_e32 v3, s5
; CI-NEXT:    s_branch .LBB31_13
; CI-NEXT:  .LBB31_6:
; CI-NEXT:    v_mov_b32_e32 v0, v2
; CI-NEXT:    v_mov_b32_e32 v1, v3
; CI-NEXT:  .LBB31_7: ; %frem.loop_exit24
; CI-NEXT:    v_subrev_i32_e32 v2, vcc, 25, v4
; CI-NEXT:    v_ldexp_f64 v[0:1], v[0:1], v2
; CI-NEXT:    s_brev_b32 s4, -2
; CI-NEXT:    v_rndne_f64_e32 v[2:3], v[0:1]
; CI-NEXT:    v_add_f64 v[0:1], v[0:1], -v[2:3]
; CI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[0:1]
; CI-NEXT:    v_add_f64 v[2:3], v[0:1], 1.0
; CI-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
; CI-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
; CI-NEXT:    v_mov_b32_e32 v2, s17
; CI-NEXT:    v_bfi_b32 v1, s4, v1, v2
; CI-NEXT:    v_cmp_gt_f64_e64 vcc, |s[18:19]|, 1.0
; CI-NEXT:    s_cbranch_vccz .LBB31_5
; CI-NEXT:  .LBB31_8: ; %frem.compute
; CI-NEXT:    v_frexp_mant_f64_e64 v[3:4], |s[18:19]|
; CI-NEXT:    v_frexp_exp_i32_f64_e32 v2, s[18:19]
; CI-NEXT:    v_ldexp_f64 v[4:5], v[3:4], 26
; CI-NEXT:    v_add_i32_e32 v6, vcc, -1, v2
; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v6
; CI-NEXT:    s_cbranch_vccnz .LBB31_11
; CI-NEXT:  ; %bb.9: ; %frem.loop_body.preheader
; CI-NEXT:    v_add_i32_e32 v6, vcc, 25, v2
; CI-NEXT:  .LBB31_10: ; %frem.loop_body
; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
; CI-NEXT:    v_mov_b32_e32 v2, v4
; CI-NEXT:    v_mov_b32_e32 v3, v5
; CI-NEXT:    v_rndne_f64_e32 v[4:5], v[2:3]
; CI-NEXT:    v_add_f64 v[4:5], v[2:3], -v[4:5]
; CI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[4:5]
; CI-NEXT:    v_add_f64 v[7:8], v[4:5], 1.0
; CI-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc
; CI-NEXT:    v_cndmask_b32_e32 v4, v4, v7, vcc
; CI-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; CI-NEXT:    v_subrev_i32_e32 v6, vcc, 26, v6
; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v6
; CI-NEXT:    s_cbranch_vccnz .LBB31_10
; CI-NEXT:    s_branch .LBB31_12
; CI-NEXT:  .LBB31_11:
; CI-NEXT:    v_mov_b32_e32 v2, v4
; CI-NEXT:    v_mov_b32_e32 v3, v5
; CI-NEXT:  .LBB31_12: ; %frem.loop_exit
; CI-NEXT:    v_subrev_i32_e32 v4, vcc, 25, v6
; CI-NEXT:    v_ldexp_f64 v[2:3], v[2:3], v4
; CI-NEXT:    s_brev_b32 s4, -2
; CI-NEXT:    v_rndne_f64_e32 v[4:5], v[2:3]
; CI-NEXT:    v_add_f64 v[2:3], v[2:3], -v[4:5]
; CI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[2:3]
; CI-NEXT:    v_add_f64 v[4:5], v[2:3], 1.0
; CI-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
; CI-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
; CI-NEXT:    v_mov_b32_e32 v4, s19
; CI-NEXT:    v_bfi_b32 v3, s4, v3, v4
; CI-NEXT:  .LBB31_13:
; CI-NEXT:    v_mov_b32_e32 v4, 0
; CI-NEXT:    v_mov_b32_e32 v5, 0x7ff00000
; CI-NEXT:    v_cmp_nge_f64_e64 vcc, |s[16:17]|, v[4:5]
; CI-NEXT:    v_mov_b32_e32 v6, 0x7ff80000
; CI-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
; CI-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc
; CI-NEXT:    v_cmp_nge_f64_e64 vcc, |s[18:19]|, v[4:5]
; CI-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
; CI-NEXT:    v_cndmask_b32_e32 v3, v6, v3, vcc
; CI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: frem_v2f64_const_one_denum_uniform:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_gt_f64_e64 vcc, |s[16:17]|, 1.0
; VI-NEXT:    s_cbranch_vccz .LBB31_4
; VI-NEXT:  ; %bb.1: ; %frem.compute15
; VI-NEXT:    v_frexp_mant_f64_e64 v[1:2], |s[16:17]|
; VI-NEXT:    v_frexp_exp_i32_f64_e32 v0, s[16:17]
; VI-NEXT:    v_ldexp_f64 v[2:3], v[1:2], 26
; VI-NEXT:    v_add_u32_e32 v4, vcc, -1, v0
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v4
; VI-NEXT:    s_cbranch_vccnz .LBB31_6
; VI-NEXT:  ; %bb.2: ; %frem.loop_body23.preheader
; VI-NEXT:    v_add_u32_e32 v4, vcc, 25, v0
; VI-NEXT:  .LBB31_3: ; %frem.loop_body23
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v0, v2
; VI-NEXT:    v_mov_b32_e32 v1, v3
; VI-NEXT:    v_rndne_f64_e32 v[2:3], v[0:1]
; VI-NEXT:    v_add_f64 v[2:3], v[0:1], -v[2:3]
; VI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[2:3]
; VI-NEXT:    v_add_f64 v[5:6], v[2:3], 1.0
; VI-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc
; VI-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
; VI-NEXT:    v_ldexp_f64 v[2:3], v[2:3], 26
; VI-NEXT:    v_subrev_u32_e32 v4, vcc, 26, v4
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v4
; VI-NEXT:    s_cbranch_vccnz .LBB31_3
; VI-NEXT:    s_branch .LBB31_7
; VI-NEXT:  .LBB31_4: ; %frem.else16
; VI-NEXT:    v_cmp_eq_f64_e64 s[4:5], |s[16:17]|, 1.0
; VI-NEXT:    s_and_b32 s6, s17, 0x80000000
; VI-NEXT:    s_cmp_lg_u64 s[4:5], 0
; VI-NEXT:    s_cselect_b32 s5, s6, s17
; VI-NEXT:    s_cselect_b32 s4, 0, s16
; VI-NEXT:    v_mov_b32_e32 v0, s4
; VI-NEXT:    v_mov_b32_e32 v1, s5
; VI-NEXT:    v_cmp_gt_f64_e64 vcc, |s[18:19]|, 1.0
; VI-NEXT:    s_cbranch_vccnz .LBB31_8
; VI-NEXT:  .LBB31_5: ; %frem.else
; VI-NEXT:    v_cmp_eq_f64_e64 s[4:5], |s[18:19]|, 1.0
; VI-NEXT:    s_and_b32 s6, s19, 0x80000000
; VI-NEXT:    s_cmp_lg_u64 s[4:5], 0
; VI-NEXT:    s_cselect_b32 s5, s6, s19
; VI-NEXT:    s_cselect_b32 s4, 0, s18
; VI-NEXT:    v_mov_b32_e32 v2, s4
; VI-NEXT:    v_mov_b32_e32 v3, s5
; VI-NEXT:    s_branch .LBB31_13
; VI-NEXT:  .LBB31_6:
; VI-NEXT:    v_mov_b32_e32 v0, v2
; VI-NEXT:    v_mov_b32_e32 v1, v3
; VI-NEXT:  .LBB31_7: ; %frem.loop_exit24
; VI-NEXT:    v_subrev_u32_e32 v2, vcc, 25, v4
; VI-NEXT:    v_ldexp_f64 v[0:1], v[0:1], v2
; VI-NEXT:    s_brev_b32 s4, -2
; VI-NEXT:    v_rndne_f64_e32 v[2:3], v[0:1]
; VI-NEXT:    v_add_f64 v[0:1], v[0:1], -v[2:3]
; VI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[0:1]
; VI-NEXT:    v_add_f64 v[2:3], v[0:1], 1.0
; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
; VI-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
; VI-NEXT:    v_mov_b32_e32 v2, s17
; VI-NEXT:    v_bfi_b32 v1, s4, v1, v2
; VI-NEXT:    v_cmp_gt_f64_e64 vcc, |s[18:19]|, 1.0
; VI-NEXT:    s_cbranch_vccz .LBB31_5
; VI-NEXT:  .LBB31_8: ; %frem.compute
; VI-NEXT:    v_frexp_mant_f64_e64 v[3:4], |s[18:19]|
; VI-NEXT:    v_frexp_exp_i32_f64_e32 v2, s[18:19]
; VI-NEXT:    v_ldexp_f64 v[4:5], v[3:4], 26
; VI-NEXT:    v_add_u32_e32 v6, vcc, -1, v2
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v6
; VI-NEXT:    s_cbranch_vccnz .LBB31_11
; VI-NEXT:  ; %bb.9: ; %frem.loop_body.preheader
; VI-NEXT:    v_add_u32_e32 v6, vcc, 25, v2
; VI-NEXT:  .LBB31_10: ; %frem.loop_body
; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
; VI-NEXT:    v_mov_b32_e32 v2, v4
; VI-NEXT:    v_mov_b32_e32 v3, v5
; VI-NEXT:    v_rndne_f64_e32 v[4:5], v[2:3]
; VI-NEXT:    v_add_f64 v[4:5], v[2:3], -v[4:5]
; VI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[4:5]
; VI-NEXT:    v_add_f64 v[7:8], v[4:5], 1.0
; VI-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc
; VI-NEXT:    v_cndmask_b32_e32 v4, v4, v7, vcc
; VI-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; VI-NEXT:    v_subrev_u32_e32 v6, vcc, 26, v6
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v6
; VI-NEXT:    s_cbranch_vccnz .LBB31_10
; VI-NEXT:    s_branch .LBB31_12
; VI-NEXT:  .LBB31_11:
; VI-NEXT:    v_mov_b32_e32 v2, v4
; VI-NEXT:    v_mov_b32_e32 v3, v5
; VI-NEXT:  .LBB31_12: ; %frem.loop_exit
; VI-NEXT:    v_subrev_u32_e32 v4, vcc, 25, v6
; VI-NEXT:    v_ldexp_f64 v[2:3], v[2:3], v4
; VI-NEXT:    s_brev_b32 s4, -2
; VI-NEXT:    v_rndne_f64_e32 v[4:5], v[2:3]
; VI-NEXT:    v_add_f64 v[2:3], v[2:3], -v[4:5]
; VI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[2:3]
; VI-NEXT:    v_add_f64 v[4:5], v[2:3], 1.0
; VI-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
; VI-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
; VI-NEXT:    v_mov_b32_e32 v4, s19
; VI-NEXT:    v_bfi_b32 v3, s4, v3, v4
; VI-NEXT:  .LBB31_13:
; VI-NEXT:    v_mov_b32_e32 v4, 0
; VI-NEXT:    v_mov_b32_e32 v5, 0x7ff00000
; VI-NEXT:    v_cmp_nge_f64_e64 vcc, |s[16:17]|, v[4:5]
; VI-NEXT:    v_mov_b32_e32 v6, 0x7ff80000
; VI-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
; VI-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc
; VI-NEXT:    v_cmp_nge_f64_e64 vcc, |s[18:19]|, v[4:5]
; VI-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
; VI-NEXT:    v_cndmask_b32_e32 v3, v6, v3, vcc
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: frem_v2f64_const_one_denum_uniform:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_gt_f64_e64 vcc, |s[16:17]|, 1.0
; GFX9-NEXT:    s_cbranch_vccz .LBB31_4
; GFX9-NEXT:  ; %bb.1: ; %frem.compute15
; GFX9-NEXT:    v_frexp_mant_f64_e64 v[1:2], |s[16:17]|
; GFX9-NEXT:    v_frexp_exp_i32_f64_e32 v0, s[16:17]
; GFX9-NEXT:    v_ldexp_f64 v[2:3], v[1:2], 26
; GFX9-NEXT:    v_add_u32_e32 v4, -1, v0
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v4
; GFX9-NEXT:    s_cbranch_vccnz .LBB31_6
; GFX9-NEXT:  ; %bb.2: ; %frem.loop_body23.preheader
; GFX9-NEXT:    v_add_u32_e32 v4, 25, v0
; GFX9-NEXT:  .LBB31_3: ; %frem.loop_body23
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v0, v2
; GFX9-NEXT:    v_mov_b32_e32 v1, v3
; GFX9-NEXT:    v_rndne_f64_e32 v[2:3], v[0:1]
; GFX9-NEXT:    v_subrev_u32_e32 v4, 26, v4
; GFX9-NEXT:    v_add_f64 v[2:3], v[0:1], -v[2:3]
; GFX9-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[2:3]
; GFX9-NEXT:    v_add_f64 v[5:6], v[2:3], 1.0
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
; GFX9-NEXT:    v_ldexp_f64 v[2:3], v[2:3], 26
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v4
; GFX9-NEXT:    s_cbranch_vccnz .LBB31_3
; GFX9-NEXT:    s_branch .LBB31_7
; GFX9-NEXT:  .LBB31_4: ; %frem.else16
; GFX9-NEXT:    v_cmp_eq_f64_e64 s[4:5], |s[16:17]|, 1.0
; GFX9-NEXT:    s_and_b32 s6, s17, 0x80000000
; GFX9-NEXT:    s_cmp_lg_u64 s[4:5], 0
; GFX9-NEXT:    s_cselect_b32 s5, s6, s17
; GFX9-NEXT:    s_cselect_b32 s4, 0, s16
; GFX9-NEXT:    v_mov_b32_e32 v0, s4
; GFX9-NEXT:    v_mov_b32_e32 v1, s5
; GFX9-NEXT:    v_cmp_gt_f64_e64 vcc, |s[18:19]|, 1.0
; GFX9-NEXT:    s_cbranch_vccnz .LBB31_8
; GFX9-NEXT:  .LBB31_5: ; %frem.else
; GFX9-NEXT:    v_cmp_eq_f64_e64 s[4:5], |s[18:19]|, 1.0
; GFX9-NEXT:    s_and_b32 s6, s19, 0x80000000
; GFX9-NEXT:    s_cmp_lg_u64 s[4:5], 0
; GFX9-NEXT:    s_cselect_b32 s5, s6, s19
; GFX9-NEXT:    s_cselect_b32 s4, 0, s18
; GFX9-NEXT:    v_mov_b32_e32 v2, s4
; GFX9-NEXT:    v_mov_b32_e32 v3, s5
; GFX9-NEXT:    s_branch .LBB31_13
; GFX9-NEXT:  .LBB31_6:
; GFX9-NEXT:    v_mov_b32_e32 v0, v2
; GFX9-NEXT:    v_mov_b32_e32 v1, v3
; GFX9-NEXT:  .LBB31_7: ; %frem.loop_exit24
; GFX9-NEXT:    v_subrev_u32_e32 v2, 25, v4
; GFX9-NEXT:    v_ldexp_f64 v[0:1], v[0:1], v2
; GFX9-NEXT:    s_brev_b32 s4, -2
; GFX9-NEXT:    v_rndne_f64_e32 v[2:3], v[0:1]
; GFX9-NEXT:    v_add_f64 v[0:1], v[0:1], -v[2:3]
; GFX9-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[0:1]
; GFX9-NEXT:    v_add_f64 v[2:3], v[0:1], 1.0
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX9-NEXT:    v_mov_b32_e32 v2, s17
; GFX9-NEXT:    v_bfi_b32 v1, s4, v1, v2
; GFX9-NEXT:    v_cmp_gt_f64_e64 vcc, |s[18:19]|, 1.0
; GFX9-NEXT:    s_cbranch_vccz .LBB31_5
; GFX9-NEXT:  .LBB31_8: ; %frem.compute
; GFX9-NEXT:    v_frexp_mant_f64_e64 v[3:4], |s[18:19]|
; GFX9-NEXT:    v_frexp_exp_i32_f64_e32 v2, s[18:19]
; GFX9-NEXT:    v_ldexp_f64 v[4:5], v[3:4], 26
; GFX9-NEXT:    v_add_u32_e32 v6, -1, v2
; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v6
; GFX9-NEXT:    s_cbranch_vccnz .LBB31_11
; GFX9-NEXT:  ; %bb.9: ; %frem.loop_body.preheader
; GFX9-NEXT:    v_add_u32_e32 v6, 25, v2
; GFX9-NEXT:  .LBB31_10: ; %frem.loop_body
; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT:    v_mov_b32_e32 v2, v4
; GFX9-NEXT:    v_mov_b32_e32 v3, v5
; GFX9-NEXT:    v_rndne_f64_e32 v[4:5], v[2:3]
; GFX9-NEXT:    v_subrev_u32_e32 v6, 26, v6
; GFX9-NEXT:    v_add_f64 v[4:5], v[2:3], -v[4:5]
; GFX9-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[4:5]
; GFX9-NEXT:    v_add_f64 v[7:8], v[4:5], 1.0
; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v7, vcc
; GFX9-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v6
; GFX9-NEXT:    s_cbranch_vccnz .LBB31_10
; GFX9-NEXT:    s_branch .LBB31_12
; GFX9-NEXT:  .LBB31_11:
; GFX9-NEXT:    v_mov_b32_e32 v2, v4
; GFX9-NEXT:    v_mov_b32_e32 v3, v5
; GFX9-NEXT:  .LBB31_12: ; %frem.loop_exit
; GFX9-NEXT:    v_subrev_u32_e32 v4, 25, v6
; GFX9-NEXT:    v_ldexp_f64 v[2:3], v[2:3], v4
; GFX9-NEXT:    s_brev_b32 s4, -2
; GFX9-NEXT:    v_rndne_f64_e32 v[4:5], v[2:3]
; GFX9-NEXT:    v_add_f64 v[2:3], v[2:3], -v[4:5]
; GFX9-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[2:3]
; GFX9-NEXT:    v_add_f64 v[4:5], v[2:3], 1.0
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX9-NEXT:    v_mov_b32_e32 v4, s19
; GFX9-NEXT:    v_bfi_b32 v3, s4, v3, v4
; GFX9-NEXT:  .LBB31_13:
; GFX9-NEXT:    v_mov_b32_e32 v4, 0
; GFX9-NEXT:    v_mov_b32_e32 v5, 0x7ff00000
; GFX9-NEXT:    v_cmp_nge_f64_e64 vcc, |s[16:17]|, v[4:5]
; GFX9-NEXT:    v_mov_b32_e32 v6, 0x7ff80000
; GFX9-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc
; GFX9-NEXT:    v_cmp_nge_f64_e64 vcc, |s[18:19]|, v[4:5]
; GFX9-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v6, v3, vcc
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: frem_v2f64_const_one_denum_uniform:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cmp_gt_f64_e64 vcc_lo, |s[16:17]|, 1.0
; GFX10-NEXT:    s_cbranch_vccz .LBB31_5
; GFX10-NEXT:  ; %bb.1: ; %frem.compute15
; GFX10-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[16:17]|
; GFX10-NEXT:    v_frexp_exp_i32_f64_e32 v2, s[16:17]
; GFX10-NEXT:    v_readfirstlane_b32 s4, v2
; GFX10-NEXT:    v_add_nc_u32_e32 v4, -1, v2
; GFX10-NEXT:    v_ldexp_f64 v[2:3], v[0:1], 26
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v4
; GFX10-NEXT:    s_cbranch_vccnz .LBB31_7
; GFX10-NEXT:  ; %bb.2: ; %frem.loop_body23.preheader
; GFX10-NEXT:    s_add_i32 s4, s4, 25
; GFX10-NEXT:  .LBB31_3: ; %frem.loop_body23
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v0, v2
; GFX10-NEXT:    v_mov_b32_e32 v1, v3
; GFX10-NEXT:    s_sub_i32 s4, s4, 26
; GFX10-NEXT:    s_cmp_gt_i32 s4, 26
; GFX10-NEXT:    v_rndne_f64_e32 v[2:3], v[0:1]
; GFX10-NEXT:    v_add_f64 v[2:3], v[0:1], -v[2:3]
; GFX10-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[2:3]
; GFX10-NEXT:    v_add_f64 v[4:5], v[2:3], 1.0
; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX10-NEXT:    v_ldexp_f64 v[2:3], v[2:3], 26
; GFX10-NEXT:    s_cbranch_scc1 .LBB31_3
; GFX10-NEXT:  ; %bb.4:
; GFX10-NEXT:    v_mov_b32_e32 v4, s4
; GFX10-NEXT:    s_branch .LBB31_8
; GFX10-NEXT:  .LBB31_5: ; %frem.else16
; GFX10-NEXT:    v_cmp_eq_f64_e64 s5, |s[16:17]|, 1.0
; GFX10-NEXT:    s_and_b32 s4, s17, 0x80000000
; GFX10-NEXT:    s_cmp_lg_u32 s5, 0
; GFX10-NEXT:    s_cselect_b32 s5, s4, s17
; GFX10-NEXT:    s_cselect_b32 s4, 0, s16
; GFX10-NEXT:    v_mov_b32_e32 v1, s5
; GFX10-NEXT:    v_mov_b32_e32 v0, s4
; GFX10-NEXT:    v_cmp_gt_f64_e64 vcc_lo, |s[18:19]|, 1.0
; GFX10-NEXT:    s_cbranch_vccnz .LBB31_9
; GFX10-NEXT:  .LBB31_6: ; %frem.else
; GFX10-NEXT:    v_cmp_eq_f64_e64 s5, |s[18:19]|, 1.0
; GFX10-NEXT:    s_and_b32 s4, s19, 0x80000000
; GFX10-NEXT:    s_cmp_lg_u32 s5, 0
; GFX10-NEXT:    s_cselect_b32 s5, s4, s19
; GFX10-NEXT:    s_cselect_b32 s4, 0, s18
; GFX10-NEXT:    v_mov_b32_e32 v3, s5
; GFX10-NEXT:    v_mov_b32_e32 v2, s4
; GFX10-NEXT:    s_branch .LBB31_15
; GFX10-NEXT:  .LBB31_7:
; GFX10-NEXT:    v_mov_b32_e32 v0, v2
; GFX10-NEXT:    v_mov_b32_e32 v1, v3
; GFX10-NEXT:  .LBB31_8: ; %frem.loop_exit24
; GFX10-NEXT:    v_subrev_nc_u32_e32 v2, 25, v4
; GFX10-NEXT:    v_ldexp_f64 v[0:1], v[0:1], v2
; GFX10-NEXT:    v_rndne_f64_e32 v[2:3], v[0:1]
; GFX10-NEXT:    v_add_f64 v[0:1], v[0:1], -v[2:3]
; GFX10-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[0:1]
; GFX10-NEXT:    v_add_f64 v[2:3], v[0:1], 1.0
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX10-NEXT:    v_bfi_b32 v1, 0x7fffffff, v1, s17
; GFX10-NEXT:    v_cmp_gt_f64_e64 vcc_lo, |s[18:19]|, 1.0
; GFX10-NEXT:    s_cbranch_vccz .LBB31_6
; GFX10-NEXT:  .LBB31_9: ; %frem.compute
; GFX10-NEXT:    v_frexp_mant_f64_e64 v[2:3], |s[18:19]|
; GFX10-NEXT:    v_frexp_exp_i32_f64_e32 v4, s[18:19]
; GFX10-NEXT:    v_readfirstlane_b32 s4, v4
; GFX10-NEXT:    v_add_nc_u32_e32 v6, -1, v4
; GFX10-NEXT:    v_ldexp_f64 v[4:5], v[2:3], 26
; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v6
; GFX10-NEXT:    s_cbranch_vccnz .LBB31_13
; GFX10-NEXT:  ; %bb.10: ; %frem.loop_body.preheader
; GFX10-NEXT:    s_add_i32 s4, s4, 25
; GFX10-NEXT:  .LBB31_11: ; %frem.loop_body
; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT:    v_mov_b32_e32 v2, v4
; GFX10-NEXT:    v_mov_b32_e32 v3, v5
; GFX10-NEXT:    s_sub_i32 s4, s4, 26
; GFX10-NEXT:    s_cmp_gt_i32 s4, 26
; GFX10-NEXT:    v_rndne_f64_e32 v[4:5], v[2:3]
; GFX10-NEXT:    v_add_f64 v[4:5], v[2:3], -v[4:5]
; GFX10-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
; GFX10-NEXT:    v_add_f64 v[6:7], v[4:5], 1.0
; GFX10-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX10-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; GFX10-NEXT:    s_cbranch_scc1 .LBB31_11
; GFX10-NEXT:  ; %bb.12:
; GFX10-NEXT:    v_mov_b32_e32 v6, s4
; GFX10-NEXT:    s_branch .LBB31_14
; GFX10-NEXT:  .LBB31_13:
; GFX10-NEXT:    v_mov_b32_e32 v2, v4
; GFX10-NEXT:    v_mov_b32_e32 v3, v5
; GFX10-NEXT:  .LBB31_14: ; %frem.loop_exit
; GFX10-NEXT:    v_subrev_nc_u32_e32 v4, 25, v6
; GFX10-NEXT:    v_ldexp_f64 v[2:3], v[2:3], v4
; GFX10-NEXT:    v_rndne_f64_e32 v[4:5], v[2:3]
; GFX10-NEXT:    v_add_f64 v[2:3], v[2:3], -v[4:5]
; GFX10-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[2:3]
; GFX10-NEXT:    v_add_f64 v[4:5], v[2:3], 1.0
; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX10-NEXT:    v_bfi_b32 v3, 0x7fffffff, v3, s19
; GFX10-NEXT:  .LBB31_15:
; GFX10-NEXT:    v_cmp_nge_f64_e64 vcc_lo, |s[16:17]|, 0x7ff00000
; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v1, 0x7ff80000, v1, vcc_lo
; GFX10-NEXT:    v_cmp_nge_f64_e64 vcc_lo, |s[18:19]|, 0x7ff00000
; GFX10-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e32 v3, 0x7ff80000, v3, vcc_lo
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: frem_v2f64_const_one_denum_uniform:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cmp_gt_f64_e64 vcc_lo, |s[0:1]|, 1.0
; GFX11-NEXT:    s_cbranch_vccz .LBB31_5
; GFX11-NEXT:  ; %bb.1: ; %frem.compute15
; GFX11-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[0:1]|
; GFX11-NEXT:    v_frexp_exp_i32_f64_e32 v2, s[0:1]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_readfirstlane_b32 s4, v2
; GFX11-NEXT:    v_add_nc_u32_e32 v4, -1, v2
; GFX11-NEXT:    v_ldexp_f64 v[2:3], v[0:1], 26
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v4
; GFX11-NEXT:    s_cbranch_vccnz .LBB31_7
; GFX11-NEXT:  ; %bb.2: ; %frem.loop_body23.preheader
; GFX11-NEXT:    s_add_i32 s4, s4, 25
; GFX11-NEXT:  .LBB31_3: ; %frem.loop_body23
; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT:    v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
; GFX11-NEXT:    s_sub_i32 s4, s4, 26
; GFX11-NEXT:    s_cmp_gt_i32 s4, 26
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_rndne_f64_e32 v[2:3], v[0:1]
; GFX11-NEXT:    v_add_f64 v[2:3], v[0:1], -v[2:3]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[2:3]
; GFX11-NEXT:    v_add_f64 v[4:5], v[2:3], 1.0
; GFX11-NEXT:    v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v2, v2, v4
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_ldexp_f64 v[2:3], v[2:3], 26
; GFX11-NEXT:    s_cbranch_scc1 .LBB31_3
; GFX11-NEXT:  ; %bb.4:
; GFX11-NEXT:    v_mov_b32_e32 v4, s4
; GFX11-NEXT:    s_branch .LBB31_8
; GFX11-NEXT:  .LBB31_5: ; %frem.else16
; GFX11-NEXT:    v_cmp_eq_f64_e64 s5, |s[0:1]|, 1.0
; GFX11-NEXT:    s_and_b32 s4, s1, 0x80000000
; GFX11-NEXT:    s_cmp_lg_u32 s5, 0
; GFX11-NEXT:    s_cselect_b32 s5, s4, s1
; GFX11-NEXT:    s_cselect_b32 s4, 0, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v0, s4
; GFX11-NEXT:    v_cmp_gt_f64_e64 vcc_lo, |s[2:3]|, 1.0
; GFX11-NEXT:    s_cbranch_vccnz .LBB31_9
; GFX11-NEXT:  .LBB31_6: ; %frem.else
; GFX11-NEXT:    v_cmp_eq_f64_e64 s5, |s[2:3]|, 1.0
; GFX11-NEXT:    s_and_b32 s4, s3, 0x80000000
; GFX11-NEXT:    s_cmp_lg_u32 s5, 0
; GFX11-NEXT:    s_cselect_b32 s5, s4, s3
; GFX11-NEXT:    s_cselect_b32 s4, 0, s2
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    v_dual_mov_b32 v3, s5 :: v_dual_mov_b32 v2, s4
; GFX11-NEXT:    s_branch .LBB31_15
; GFX11-NEXT:  .LBB31_7:
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT:    v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
; GFX11-NEXT:  .LBB31_8: ; %frem.loop_exit24
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_subrev_nc_u32_e32 v2, 25, v4
; GFX11-NEXT:    v_ldexp_f64 v[0:1], v[0:1], v2
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_rndne_f64_e32 v[2:3], v[0:1]
; GFX11-NEXT:    v_add_f64 v[0:1], v[0:1], -v[2:3]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[0:1]
; GFX11-NEXT:    v_add_f64 v[2:3], v[0:1], 1.0
; GFX11-NEXT:    v_dual_cndmask_b32 v0, v0, v2 :: v_dual_cndmask_b32 v1, v1, v3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_bfi_b32 v1, 0x7fffffff, v1, s1
; GFX11-NEXT:    v_cmp_gt_f64_e64 vcc_lo, |s[2:3]|, 1.0
; GFX11-NEXT:    s_cbranch_vccz .LBB31_6
; GFX11-NEXT:  .LBB31_9: ; %frem.compute
; GFX11-NEXT:    v_frexp_mant_f64_e64 v[2:3], |s[2:3]|
; GFX11-NEXT:    v_frexp_exp_i32_f64_e32 v4, s[2:3]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_readfirstlane_b32 s4, v4
; GFX11-NEXT:    v_add_nc_u32_e32 v6, -1, v4
; GFX11-NEXT:    v_ldexp_f64 v[4:5], v[2:3], 26
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v6
; GFX11-NEXT:    s_cbranch_vccnz .LBB31_13
; GFX11-NEXT:  ; %bb.10: ; %frem.loop_body.preheader
; GFX11-NEXT:    s_add_i32 s4, s4, 25
; GFX11-NEXT:  .LBB31_11: ; %frem.loop_body
; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT:    v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
; GFX11-NEXT:    s_sub_i32 s4, s4, 26
; GFX11-NEXT:    s_cmp_gt_i32 s4, 26
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_rndne_f64_e32 v[4:5], v[2:3]
; GFX11-NEXT:    v_add_f64 v[4:5], v[2:3], -v[4:5]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
; GFX11-NEXT:    v_add_f64 v[6:7], v[4:5], 1.0
; GFX11-NEXT:    v_dual_cndmask_b32 v5, v5, v7 :: v_dual_cndmask_b32 v4, v4, v6
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; GFX11-NEXT:    s_cbranch_scc1 .LBB31_11
; GFX11-NEXT:  ; %bb.12:
; GFX11-NEXT:    v_mov_b32_e32 v6, s4
; GFX11-NEXT:    s_branch .LBB31_14
; GFX11-NEXT:  .LBB31_13:
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT:    v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
; GFX11-NEXT:  .LBB31_14: ; %frem.loop_exit
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_subrev_nc_u32_e32 v4, 25, v6
; GFX11-NEXT:    v_ldexp_f64 v[2:3], v[2:3], v4
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_rndne_f64_e32 v[4:5], v[2:3]
; GFX11-NEXT:    v_add_f64 v[2:3], v[2:3], -v[4:5]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[2:3]
; GFX11-NEXT:    v_add_f64 v[4:5], v[2:3], 1.0
; GFX11-NEXT:    v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v3, v3, v5
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_bfi_b32 v3, 0x7fffffff, v3, s3
; GFX11-NEXT:  .LBB31_15:
; GFX11-NEXT:    v_cmp_nge_f64_e64 vcc_lo, |s[0:1]|, 0x7ff00000
; GFX11-NEXT:    v_dual_cndmask_b32 v0, 0, v0 :: v_dual_cndmask_b32 v1, 0x7ff80000, v1
; GFX11-NEXT:    v_cmp_nge_f64_e64 vcc_lo, |s[2:3]|, 0x7ff00000
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT:    v_dual_cndmask_b32 v2, 0, v2 :: v_dual_cndmask_b32 v3, 0x7ff80000, v3
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1150-LABEL: frem_v2f64_const_one_denum_uniform:
; GFX1150:       ; %bb.0:
; GFX1150-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1150-NEXT:    v_cmp_gt_f64_e64 vcc_lo, |s[0:1]|, 1.0
; GFX1150-NEXT:    s_cbranch_vccz .LBB31_5
; GFX1150-NEXT:  ; %bb.1: ; %frem.compute15
; GFX1150-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[0:1]|
; GFX1150-NEXT:    v_frexp_exp_i32_f64_e32 v2, s[0:1]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1150-NEXT:    v_readfirstlane_b32 s4, v2
; GFX1150-NEXT:    v_add_nc_u32_e32 v4, -1, v2
; GFX1150-NEXT:    v_ldexp_f64 v[2:3], v[0:1], 26
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1150-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v4
; GFX1150-NEXT:    s_cbranch_vccnz .LBB31_7
; GFX1150-NEXT:  ; %bb.2: ; %frem.loop_body23.preheader
; GFX1150-NEXT:    s_add_i32 s4, s4, 25
; GFX1150-NEXT:  .LBB31_3: ; %frem.loop_body23
; GFX1150-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT:    v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
; GFX1150-NEXT:    s_sub_i32 s4, s4, 26
; GFX1150-NEXT:    s_cmp_gt_i32 s4, 26
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_rndne_f64_e32 v[2:3], v[0:1]
; GFX1150-NEXT:    v_add_f64 v[2:3], v[0:1], -v[2:3]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[2:3]
; GFX1150-NEXT:    v_add_f64 v[4:5], v[2:3], 1.0
; GFX1150-NEXT:    v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v2, v2, v4
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f64 v[2:3], v[2:3], 26
; GFX1150-NEXT:    s_cbranch_scc1 .LBB31_3
; GFX1150-NEXT:  ; %bb.4:
; GFX1150-NEXT:    v_mov_b32_e32 v4, s4
; GFX1150-NEXT:    s_branch .LBB31_8
; GFX1150-NEXT:  .LBB31_5: ; %frem.else16
; GFX1150-NEXT:    v_cmp_eq_f64_e64 s5, |s[0:1]|, 1.0
; GFX1150-NEXT:    s_and_b32 s4, s1, 0x80000000
; GFX1150-NEXT:    s_cmp_lg_u32 s5, 0
; GFX1150-NEXT:    s_cselect_b32 s5, s4, s1
; GFX1150-NEXT:    s_cselect_b32 s4, 0, s0
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v0, s4
; GFX1150-NEXT:    v_cmp_gt_f64_e64 vcc_lo, |s[2:3]|, 1.0
; GFX1150-NEXT:    s_cbranch_vccnz .LBB31_9
; GFX1150-NEXT:  .LBB31_6: ; %frem.else
; GFX1150-NEXT:    v_cmp_eq_f64_e64 s5, |s[2:3]|, 1.0
; GFX1150-NEXT:    s_and_b32 s4, s3, 0x80000000
; GFX1150-NEXT:    s_cmp_lg_u32 s5, 0
; GFX1150-NEXT:    s_cselect_b32 s5, s4, s3
; GFX1150-NEXT:    s_cselect_b32 s4, 0, s2
; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT:    v_dual_mov_b32 v3, s5 :: v_dual_mov_b32 v2, s4
; GFX1150-NEXT:    s_branch .LBB31_15
; GFX1150-NEXT:  .LBB31_7:
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1150-NEXT:    v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
; GFX1150-NEXT:  .LBB31_8: ; %frem.loop_exit24
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_subrev_nc_u32_e32 v2, 25, v4
; GFX1150-NEXT:    v_ldexp_f64 v[0:1], v[0:1], v2
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_rndne_f64_e32 v[2:3], v[0:1]
; GFX1150-NEXT:    v_add_f64 v[0:1], v[0:1], -v[2:3]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[0:1]
; GFX1150-NEXT:    v_add_f64 v[2:3], v[0:1], 1.0
; GFX1150-NEXT:    v_dual_cndmask_b32 v0, v0, v2 :: v_dual_cndmask_b32 v1, v1, v3
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_bfi_b32 v1, 0x7fffffff, v1, s1
; GFX1150-NEXT:    v_cmp_gt_f64_e64 vcc_lo, |s[2:3]|, 1.0
; GFX1150-NEXT:    s_cbranch_vccz .LBB31_6
; GFX1150-NEXT:  .LBB31_9: ; %frem.compute
; GFX1150-NEXT:    v_frexp_mant_f64_e64 v[2:3], |s[2:3]|
; GFX1150-NEXT:    v_frexp_exp_i32_f64_e32 v4, s[2:3]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1150-NEXT:    v_readfirstlane_b32 s4, v4
; GFX1150-NEXT:    v_add_nc_u32_e32 v6, -1, v4
; GFX1150-NEXT:    v_ldexp_f64 v[4:5], v[2:3], 26
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1150-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v6
; GFX1150-NEXT:    s_cbranch_vccnz .LBB31_13
; GFX1150-NEXT:  ; %bb.10: ; %frem.loop_body.preheader
; GFX1150-NEXT:    s_add_i32 s4, s4, 25
; GFX1150-NEXT:  .LBB31_11: ; %frem.loop_body
; GFX1150-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT:    v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
; GFX1150-NEXT:    s_sub_i32 s4, s4, 26
; GFX1150-NEXT:    s_cmp_gt_i32 s4, 26
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_rndne_f64_e32 v[4:5], v[2:3]
; GFX1150-NEXT:    v_add_f64 v[4:5], v[2:3], -v[4:5]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
; GFX1150-NEXT:    v_add_f64 v[6:7], v[4:5], 1.0
; GFX1150-NEXT:    v_dual_cndmask_b32 v5, v5, v7 :: v_dual_cndmask_b32 v4, v4, v6
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; GFX1150-NEXT:    s_cbranch_scc1 .LBB31_11
; GFX1150-NEXT:  ; %bb.12:
; GFX1150-NEXT:    v_mov_b32_e32 v6, s4
; GFX1150-NEXT:    s_branch .LBB31_14
; GFX1150-NEXT:  .LBB31_13:
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1150-NEXT:    v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
; GFX1150-NEXT:  .LBB31_14: ; %frem.loop_exit
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_subrev_nc_u32_e32 v4, 25, v6
; GFX1150-NEXT:    v_ldexp_f64 v[2:3], v[2:3], v4
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_rndne_f64_e32 v[4:5], v[2:3]
; GFX1150-NEXT:    v_add_f64 v[2:3], v[2:3], -v[4:5]
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[2:3]
; GFX1150-NEXT:    v_add_f64 v[4:5], v[2:3], 1.0
; GFX1150-NEXT:    v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v3, v3, v5
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT:    v_bfi_b32 v3, 0x7fffffff, v3, s3
; GFX1150-NEXT:  .LBB31_15:
; GFX1150-NEXT:    v_cmp_nge_f64_e64 vcc_lo, |s[0:1]|, 0x7ff00000
; GFX1150-NEXT:    v_dual_cndmask_b32 v0, 0, v0 :: v_dual_cndmask_b32 v1, 0x7ff80000, v1
; GFX1150-NEXT:    v_cmp_nge_f64_e64 vcc_lo, |s[2:3]|, 0x7ff00000
; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_4)
; GFX1150-NEXT:    v_dual_cndmask_b32 v2, 0, v2 :: v_dual_cndmask_b32 v3, 0x7ff80000, v3
; GFX1150-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: frem_v2f64_const_one_denum_uniform:
; GFX1200:       ; %bb.0:
; GFX1200-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT:    s_wait_expcnt 0x0
; GFX1200-NEXT:    s_wait_samplecnt 0x0
; GFX1200-NEXT:    s_wait_bvhcnt 0x0
; GFX1200-NEXT:    s_wait_kmcnt 0x0
; GFX1200-NEXT:    v_cmp_gt_f64_e64 vcc_lo, |s[0:1]|, 1.0
; GFX1200-NEXT:    s_cbranch_vccz .LBB31_5
; GFX1200-NEXT:  ; %bb.1: ; %frem.compute15
; GFX1200-NEXT:    v_frexp_mant_f64_e64 v[0:1], |s[0:1]|
; GFX1200-NEXT:    v_frexp_exp_i32_f64_e32 v2, s[0:1]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1200-NEXT:    v_readfirstlane_b32 s4, v2
; GFX1200-NEXT:    v_add_nc_u32_e32 v4, -1, v2
; GFX1200-NEXT:    v_ldexp_f64 v[2:3], v[0:1], 26
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v4
; GFX1200-NEXT:    s_cbranch_vccnz .LBB31_7
; GFX1200-NEXT:  ; %bb.2: ; %frem.loop_body23.preheader
; GFX1200-NEXT:    s_add_co_i32 s4, s4, 25
; GFX1200-NEXT:  .LBB31_3: ; %frem.loop_body23
; GFX1200-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_sub_co_i32 s4, s4, 26
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_cmp_gt_i32 s4, 26
; GFX1200-NEXT:    v_rndne_f64_e32 v[2:3], v[0:1]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_add_f64_e64 v[2:3], v[0:1], -v[2:3]
; GFX1200-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[2:3]
; GFX1200-NEXT:    v_add_f64_e32 v[4:5], 1.0, v[2:3]
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v2, v2, v4
; GFX1200-NEXT:    v_ldexp_f64 v[2:3], v[2:3], 26
; GFX1200-NEXT:    s_cbranch_scc1 .LBB31_3
; GFX1200-NEXT:  ; %bb.4:
; GFX1200-NEXT:    v_mov_b32_e32 v4, s4
; GFX1200-NEXT:    s_branch .LBB31_8
; GFX1200-NEXT:  .LBB31_5: ; %frem.else16
; GFX1200-NEXT:    v_cmp_eq_f64_e64 s5, |s[0:1]|, 1.0
; GFX1200-NEXT:    s_and_b32 s4, s1, 0x80000000
; GFX1200-NEXT:    s_cmp_lg_u32 s5, 0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_cselect_b32 s5, s4, s1
; GFX1200-NEXT:    s_cselect_b32 s4, 0, s0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v0, s4
; GFX1200-NEXT:    v_cmp_gt_f64_e64 vcc_lo, |s[2:3]|, 1.0
; GFX1200-NEXT:    s_cbranch_vccnz .LBB31_9
; GFX1200-NEXT:  .LBB31_6: ; %frem.else
; GFX1200-NEXT:    v_cmp_eq_f64_e64 s5, |s[2:3]|, 1.0
; GFX1200-NEXT:    s_and_b32 s4, s3, 0x80000000
; GFX1200-NEXT:    s_cmp_lg_u32 s5, 0
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_cselect_b32 s5, s4, s3
; GFX1200-NEXT:    s_cselect_b32 s4, 0, s2
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    v_dual_mov_b32 v3, s5 :: v_dual_mov_b32 v2, s4
; GFX1200-NEXT:    s_branch .LBB31_15
; GFX1200-NEXT:  .LBB31_7:
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-NEXT:    v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
; GFX1200-NEXT:  .LBB31_8: ; %frem.loop_exit24
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_subrev_nc_u32_e32 v2, 25, v4
; GFX1200-NEXT:    v_ldexp_f64 v[0:1], v[0:1], v2
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_rndne_f64_e32 v[2:3], v[0:1]
; GFX1200-NEXT:    v_add_f64_e64 v[0:1], v[0:1], -v[2:3]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[0:1]
; GFX1200-NEXT:    v_add_f64_e32 v[2:3], 1.0, v[0:1]
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_dual_cndmask_b32 v0, v0, v2 :: v_dual_cndmask_b32 v1, v1, v3
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_bfi_b32 v1, 0x7fffffff, v1, s1
; GFX1200-NEXT:    v_cmp_gt_f64_e64 vcc_lo, |s[2:3]|, 1.0
; GFX1200-NEXT:    s_cbranch_vccz .LBB31_6
; GFX1200-NEXT:  .LBB31_9: ; %frem.compute
; GFX1200-NEXT:    v_frexp_mant_f64_e64 v[2:3], |s[2:3]|
; GFX1200-NEXT:    v_frexp_exp_i32_f64_e32 v4, s[2:3]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1200-NEXT:    v_readfirstlane_b32 s4, v4
; GFX1200-NEXT:    v_add_nc_u32_e32 v6, -1, v4
; GFX1200-NEXT:    v_ldexp_f64 v[4:5], v[2:3], 26
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v6
; GFX1200-NEXT:    s_cbranch_vccnz .LBB31_13
; GFX1200-NEXT:  ; %bb.10: ; %frem.loop_body.preheader
; GFX1200-NEXT:    s_add_co_i32 s4, s4, 25
; GFX1200-NEXT:  .LBB31_11: ; %frem.loop_body
; GFX1200-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_sub_co_i32 s4, s4, 26
; GFX1200-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT:    s_cmp_gt_i32 s4, 26
; GFX1200-NEXT:    v_rndne_f64_e32 v[4:5], v[2:3]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_add_f64_e64 v[4:5], v[2:3], -v[4:5]
; GFX1200-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
; GFX1200-NEXT:    v_add_f64_e32 v[6:7], 1.0, v[4:5]
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_dual_cndmask_b32 v5, v5, v7 :: v_dual_cndmask_b32 v4, v4, v6
; GFX1200-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 26
; GFX1200-NEXT:    s_cbranch_scc1 .LBB31_11
; GFX1200-NEXT:  ; %bb.12:
; GFX1200-NEXT:    v_mov_b32_e32 v6, s4
; GFX1200-NEXT:    s_branch .LBB31_14
; GFX1200-NEXT:  .LBB31_13:
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1200-NEXT:    v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
; GFX1200-NEXT:  .LBB31_14: ; %frem.loop_exit
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_subrev_nc_u32_e32 v4, 25, v6
; GFX1200-NEXT:    v_ldexp_f64 v[2:3], v[2:3], v4
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_rndne_f64_e32 v[4:5], v[2:3]
; GFX1200-NEXT:    v_add_f64_e64 v[2:3], v[2:3], -v[4:5]
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[2:3]
; GFX1200-NEXT:    v_add_f64_e32 v[4:5], 1.0, v[2:3]
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v3, v3, v5
; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT:    v_bfi_b32 v3, 0x7fffffff, v3, s3
; GFX1200-NEXT:  .LBB31_15:
; GFX1200-NEXT:    v_cmp_nge_f64_e64 vcc_lo, |s[0:1]|, 0x7ff00000
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_dual_cndmask_b32 v0, 0, v0 :: v_dual_cndmask_b32 v1, 0x7ff80000, v1
; GFX1200-NEXT:    v_cmp_nge_f64_e64 vcc_lo, |s[2:3]|, 0x7ff00000
; GFX1200-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT:    v_dual_cndmask_b32 v2, 0, v2 :: v_dual_cndmask_b32 v3, 0x7ff80000, v3
; GFX1200-NEXT:    s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT:    s_setpc_b64 s[30:31]
   %r1 = frem  <2 x double> %in, <double 1.0, double 1.0>
  ret <2 x double> %r1
}



attributes #0 = { nounwind denormal_fpenv(float: preservesign) }