llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=amdgpu6.00 -global-isel=0 < %s | FileCheck -enable-var-scope -check-prefixes=SI-SDAG %s
; RUN: llc -mtriple=amdgpu6.00 -global-isel=1 < %s | FileCheck -check-prefixes=SI-GISEL %s
; RUN: llc -mtriple=amdgpu8.03 -global-isel=0 < %s | FileCheck -enable-var-scope -check-prefixes=VI-SDAG %s
; RUN: llc -mtriple=amdgpu8.03 -global-isel=1 < %s | FileCheck -enable-var-scope -check-prefixes=VI-GISEL %s
; RUN: llc -mtriple=amdgpu9.00 -global-isel=0 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX9-SDAG %s
; RUN: llc -mtriple=amdgpu9.00 -global-isel=1 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX9-GISEL %s
; RUN: llc -mtriple=amdgpu9.50 -global-isel=0 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX950-SDAG %s
; RUN: llc -mtriple=amdgpu9.50 -global-isel=1 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX950-GISEL %s
; RUN: llc -mtriple=amdgpu11.00 -global-isel=0 -mattr=+real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX11-SDAG-TRUE16 %s
; RUN: llc -mtriple=amdgpu11.00 -global-isel=0 -mattr=-real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX11-SDAG-FAKE16 %s
; RUN: llc -mtriple=amdgpu11.00 -global-isel=1 -mattr=+real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX11-GISEL-TRUE16 %s
; RUN: llc -mtriple=amdgpu11.00 -global-isel=1 -mattr=-real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX11-GISEL-FAKE16 %s
; RUN: llc -mtriple=amdgpu12.50 -global-isel=0 -mattr=+real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250-SDAG-TRUE16 %s
; RUN: llc -mtriple=amdgpu12.50 -global-isel=0 -mattr=-real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250-SDAG-FAKE16 %s
; RUN: llc -mtriple=amdgpu12.50 -global-isel=1 -mattr=+real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250-GISEL-TRUE16 %s
; RUN: llc -mtriple=amdgpu12.50 -global-isel=1 -mattr=-real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250-GISEL-FAKE16 %s

define half @fptrunc_f32_to_f16(float %a) {
; SI-SDAG-LABEL: fptrunc_f32_to_f16:
; SI-SDAG:       ; %bb.0:
; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; SI-GISEL-LABEL: fptrunc_f32_to_f16:
; SI-GISEL:       ; %bb.0:
; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: fptrunc_f32_to_f16:
; VI-SDAG:       ; %bb.0:
; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: fptrunc_f32_to_f16:
; VI-GISEL:       ; %bb.0:
; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: fptrunc_f32_to_f16:
; GFX9-SDAG:       ; %bb.0:
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: fptrunc_f32_to_f16:
; GFX9-GISEL:       ; %bb.0:
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX950-SDAG-LABEL: fptrunc_f32_to_f16:
; GFX950-SDAG:       ; %bb.0:
; GFX950-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX950-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX950-GISEL-LABEL: fptrunc_f32_to_f16:
; GFX950-GISEL:       ; %bb.0:
; GFX950-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX950-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: fptrunc_f32_to_f16:
; GFX11-SDAG-TRUE16:       ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: fptrunc_f32_to_f16:
; GFX11-SDAG-FAKE16:       ; %bb.0:
; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-GISEL-TRUE16-LABEL: fptrunc_f32_to_f16:
; GFX11-GISEL-TRUE16:       ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: fptrunc_f32_to_f16:
; GFX11-GISEL-FAKE16:       ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1250-SDAG-TRUE16-LABEL: fptrunc_f32_to_f16:
; GFX1250-SDAG-TRUE16:       ; %bb.0:
; GFX1250-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
; GFX1250-SDAG-TRUE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-SDAG-FAKE16-LABEL: fptrunc_f32_to_f16:
; GFX1250-SDAG-FAKE16:       ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX1250-SDAG-FAKE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-GISEL-TRUE16-LABEL: fptrunc_f32_to_f16:
; GFX1250-GISEL-TRUE16:       ; %bb.0:
; GFX1250-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
; GFX1250-GISEL-TRUE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-GISEL-FAKE16-LABEL: fptrunc_f32_to_f16:
; GFX1250-GISEL-FAKE16:       ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX1250-GISEL-FAKE16-NEXT:    s_set_pc_i64 s[30:31]
  %r.val = fptrunc float %a to half
  ret half %r.val
}

define half @fptrunc_f32_to_f16_afn(float %a) {
; SI-SDAG-LABEL: fptrunc_f32_to_f16_afn:
; SI-SDAG:       ; %bb.0:
; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; SI-GISEL-LABEL: fptrunc_f32_to_f16_afn:
; SI-GISEL:       ; %bb.0:
; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: fptrunc_f32_to_f16_afn:
; VI-SDAG:       ; %bb.0:
; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: fptrunc_f32_to_f16_afn:
; VI-GISEL:       ; %bb.0:
; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: fptrunc_f32_to_f16_afn:
; GFX9-SDAG:       ; %bb.0:
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: fptrunc_f32_to_f16_afn:
; GFX9-GISEL:       ; %bb.0:
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX950-SDAG-LABEL: fptrunc_f32_to_f16_afn:
; GFX950-SDAG:       ; %bb.0:
; GFX950-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX950-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX950-GISEL-LABEL: fptrunc_f32_to_f16_afn:
; GFX950-GISEL:       ; %bb.0:
; GFX950-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX950-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: fptrunc_f32_to_f16_afn:
; GFX11-SDAG-TRUE16:       ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: fptrunc_f32_to_f16_afn:
; GFX11-SDAG-FAKE16:       ; %bb.0:
; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-GISEL-TRUE16-LABEL: fptrunc_f32_to_f16_afn:
; GFX11-GISEL-TRUE16:       ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: fptrunc_f32_to_f16_afn:
; GFX11-GISEL-FAKE16:       ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1250-SDAG-TRUE16-LABEL: fptrunc_f32_to_f16_afn:
; GFX1250-SDAG-TRUE16:       ; %bb.0:
; GFX1250-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
; GFX1250-SDAG-TRUE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-SDAG-FAKE16-LABEL: fptrunc_f32_to_f16_afn:
; GFX1250-SDAG-FAKE16:       ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX1250-SDAG-FAKE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-GISEL-TRUE16-LABEL: fptrunc_f32_to_f16_afn:
; GFX1250-GISEL-TRUE16:       ; %bb.0:
; GFX1250-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
; GFX1250-GISEL-TRUE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-GISEL-FAKE16-LABEL: fptrunc_f32_to_f16_afn:
; GFX1250-GISEL-FAKE16:       ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX1250-GISEL-FAKE16-NEXT:    s_set_pc_i64 s[30:31]
  %r.val = fptrunc afn float %a to half
  ret half %r.val
}

define half @fptrunc_f64_to_f16(double %a) {
; SI-SDAG-LABEL: fptrunc_f64_to_f16:
; SI-SDAG:       ; %bb.0:
; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-SDAG-NEXT:    v_and_b32_e32 v2, 0x1ff, v1
; SI-SDAG-NEXT:    v_or_b32_e32 v0, v2, v0
; SI-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; SI-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 8, v1
; SI-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-SDAG-NEXT:    v_and_b32_e32 v2, 0xffe, v2
; SI-SDAG-NEXT:    v_bfe_u32 v3, v1, 20, 11
; SI-SDAG-NEXT:    v_or_b32_e32 v0, v2, v0
; SI-SDAG-NEXT:    v_sub_i32_e32 v4, vcc, 0x3f1, v3
; SI-SDAG-NEXT:    v_or_b32_e32 v2, 0x1000, v0
; SI-SDAG-NEXT:    v_med3_i32 v4, v4, 0, 13
; SI-SDAG-NEXT:    v_lshrrev_b32_e32 v5, v4, v2
; SI-SDAG-NEXT:    v_lshlrev_b32_e32 v4, v4, v5
; SI-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, v4, v2
; SI-SDAG-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
; SI-SDAG-NEXT:    v_add_i32_e32 v3, vcc, 0xfffffc10, v3
; SI-SDAG-NEXT:    v_lshlrev_b32_e32 v4, 12, v3
; SI-SDAG-NEXT:    v_or_b32_e32 v2, v5, v2
; SI-SDAG-NEXT:    v_or_b32_e32 v4, v0, v4
; SI-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v3
; SI-SDAG-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; SI-SDAG-NEXT:    v_and_b32_e32 v4, 7, v2
; SI-SDAG-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v4
; SI-SDAG-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
; SI-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v4
; SI-SDAG-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
; SI-SDAG-NEXT:    v_or_b32_e32 v4, v4, v5
; SI-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
; SI-SDAG-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
; SI-SDAG-NEXT:    v_mov_b32_e32 v4, 0x7c00
; SI-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v3
; SI-SDAG-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; SI-SDAG-NEXT:    v_mov_b32_e32 v5, 0x7e00
; SI-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; SI-SDAG-NEXT:    s_movk_i32 s4, 0x40f
; SI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v4, v5, vcc
; SI-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, s4, v3
; SI-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
; SI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
; SI-SDAG-NEXT:    v_and_b32_e32 v1, 0x8000, v1
; SI-SDAG-NEXT:    v_or_b32_e32 v0, v1, v0
; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; SI-GISEL-LABEL: fptrunc_f64_to_f16:
; SI-GISEL:       ; %bb.0:
; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-GISEL-NEXT:    v_bfe_u32 v2, v1, 20, 11
; SI-GISEL-NEXT:    v_and_b32_e32 v4, 0x1ff, v1
; SI-GISEL-NEXT:    v_add_i32_e32 v2, vcc, 0xfffffc10, v2
; SI-GISEL-NEXT:    v_or_b32_e32 v0, v4, v0
; SI-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 8, v1
; SI-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; SI-GISEL-NEXT:    v_and_b32_e32 v3, 0xffe, v3
; SI-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-GISEL-NEXT:    v_or_b32_e32 v0, v3, v0
; SI-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; SI-GISEL-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
; SI-GISEL-NEXT:    v_lshlrev_b32_e32 v5, 12, v2
; SI-GISEL-NEXT:    v_sub_i32_e32 v6, vcc, 1, v2
; SI-GISEL-NEXT:    v_or_b32_e32 v5, v0, v5
; SI-GISEL-NEXT:    v_med3_i32 v6, v6, 0, 13
; SI-GISEL-NEXT:    v_or_b32_e32 v0, 0x1000, v0
; SI-GISEL-NEXT:    v_lshrrev_b32_e32 v7, v6, v0
; SI-GISEL-NEXT:    v_lshlrev_b32_e32 v6, v6, v7
; SI-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, v6, v0
; SI-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-GISEL-NEXT:    v_or_b32_e32 v0, v7, v0
; SI-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v2
; SI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc
; SI-GISEL-NEXT:    v_and_b32_e32 v5, 7, v0
; SI-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v5
; SI-GISEL-NEXT:    v_cmp_lt_i32_e64 s[4:5], 5, v5
; SI-GISEL-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
; SI-GISEL-NEXT:    v_lshrrev_b32_e32 v0, 2, v0
; SI-GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s[4:5]
; SI-GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v5
; SI-GISEL-NEXT:    v_mov_b32_e32 v4, 0x7c00
; SI-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, 30, v2
; SI-GISEL-NEXT:    v_lshlrev_b32_e32 v3, 9, v3
; SI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
; SI-GISEL-NEXT:    v_mov_b32_e32 v4, 0x40f
; SI-GISEL-NEXT:    v_or_b32_e32 v3, 0x7c00, v3
; SI-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v4
; SI-GISEL-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
; SI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
; SI-GISEL-NEXT:    v_and_b32_e32 v1, 0x8000, v1
; SI-GISEL-NEXT:    v_or_b32_e32 v0, v1, v0
; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: fptrunc_f64_to_f16:
; VI-SDAG:       ; %bb.0:
; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-NEXT:    v_and_b32_e32 v2, 0x1ff, v1
; VI-SDAG-NEXT:    v_or_b32_e32 v0, v2, v0
; VI-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; VI-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 8, v1
; VI-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; VI-SDAG-NEXT:    v_and_b32_e32 v2, 0xffe, v2
; VI-SDAG-NEXT:    v_bfe_u32 v3, v1, 20, 11
; VI-SDAG-NEXT:    v_or_b32_e32 v0, v2, v0
; VI-SDAG-NEXT:    v_sub_u32_e32 v4, vcc, 0x3f1, v3
; VI-SDAG-NEXT:    v_or_b32_e32 v2, 0x1000, v0
; VI-SDAG-NEXT:    v_med3_i32 v4, v4, 0, 13
; VI-SDAG-NEXT:    v_lshrrev_b32_e32 v5, v4, v2
; VI-SDAG-NEXT:    v_lshlrev_b32_e32 v4, v4, v5
; VI-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, v4, v2
; VI-SDAG-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
; VI-SDAG-NEXT:    v_add_u32_e32 v3, vcc, 0xfffffc10, v3
; VI-SDAG-NEXT:    v_lshlrev_b32_e32 v4, 12, v3
; VI-SDAG-NEXT:    v_or_b32_e32 v2, v5, v2
; VI-SDAG-NEXT:    v_or_b32_e32 v4, v0, v4
; VI-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v3
; VI-SDAG-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; VI-SDAG-NEXT:    v_and_b32_e32 v4, 7, v2
; VI-SDAG-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v4
; VI-SDAG-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
; VI-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v4
; VI-SDAG-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
; VI-SDAG-NEXT:    v_or_b32_e32 v4, v4, v5
; VI-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
; VI-SDAG-NEXT:    v_add_u32_e32 v2, vcc, v2, v4
; VI-SDAG-NEXT:    v_mov_b32_e32 v4, 0x7c00
; VI-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v3
; VI-SDAG-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; VI-SDAG-NEXT:    v_mov_b32_e32 v5, 0x7e00
; VI-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; VI-SDAG-NEXT:    s_movk_i32 s4, 0x40f
; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v4, v5, vcc
; VI-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, s4, v3
; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-SDAG-NEXT:    v_mov_b32_e32 v2, 0x8000
; VI-SDAG-NEXT:    v_and_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-SDAG-NEXT:    v_or_b32_e32 v0, v1, v0
; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: fptrunc_f64_to_f16:
; VI-GISEL:       ; %bb.0:
; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT:    v_bfe_u32 v2, v1, 20, 11
; VI-GISEL-NEXT:    v_and_b32_e32 v4, 0x1ff, v1
; VI-GISEL-NEXT:    v_add_u32_e32 v2, vcc, 0xfffffc10, v2
; VI-GISEL-NEXT:    v_or_b32_e32 v0, v4, v0
; VI-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 8, v1
; VI-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; VI-GISEL-NEXT:    v_and_b32_e32 v3, 0xffe, v3
; VI-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; VI-GISEL-NEXT:    v_or_b32_e32 v0, v3, v0
; VI-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; VI-GISEL-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
; VI-GISEL-NEXT:    v_lshlrev_b32_e32 v5, 12, v2
; VI-GISEL-NEXT:    v_sub_u32_e32 v6, vcc, 1, v2
; VI-GISEL-NEXT:    v_or_b32_e32 v5, v0, v5
; VI-GISEL-NEXT:    v_med3_i32 v6, v6, 0, 13
; VI-GISEL-NEXT:    v_or_b32_e32 v0, 0x1000, v0
; VI-GISEL-NEXT:    v_lshrrev_b32_e32 v7, v6, v0
; VI-GISEL-NEXT:    v_lshlrev_b32_e32 v6, v6, v7
; VI-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, v6, v0
; VI-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; VI-GISEL-NEXT:    v_or_b32_e32 v0, v7, v0
; VI-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v2
; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc
; VI-GISEL-NEXT:    v_and_b32_e32 v5, 7, v0
; VI-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v5
; VI-GISEL-NEXT:    v_cmp_lt_i32_e64 s[4:5], 5, v5
; VI-GISEL-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
; VI-GISEL-NEXT:    v_lshrrev_b32_e32 v0, 2, v0
; VI-GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s[4:5]
; VI-GISEL-NEXT:    v_add_u32_e32 v0, vcc, v0, v5
; VI-GISEL-NEXT:    v_mov_b32_e32 v4, 0x7c00
; VI-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, 30, v2
; VI-GISEL-NEXT:    v_lshlrev_b32_e32 v3, 9, v3
; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
; VI-GISEL-NEXT:    v_mov_b32_e32 v4, 0x40f
; VI-GISEL-NEXT:    v_or_b32_e32 v3, 0x7c00, v3
; VI-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v4
; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x8000
; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
; VI-GISEL-NEXT:    v_and_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-GISEL-NEXT:    v_or_b32_e32 v0, v1, v0
; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: fptrunc_f64_to_f16:
; GFX9-SDAG:       ; %bb.0:
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT:    s_movk_i32 s4, 0x1ff
; GFX9-SDAG-NEXT:    v_and_or_b32 v0, v1, s4, v0
; GFX9-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 8, v1
; GFX9-SDAG-NEXT:    s_movk_i32 s4, 0xffe
; GFX9-SDAG-NEXT:    v_bfe_u32 v3, v1, 20, 11
; GFX9-SDAG-NEXT:    v_and_or_b32 v0, v2, s4, v0
; GFX9-SDAG-NEXT:    v_sub_u32_e32 v4, 0x3f1, v3
; GFX9-SDAG-NEXT:    v_or_b32_e32 v2, 0x1000, v0
; GFX9-SDAG-NEXT:    v_med3_i32 v4, v4, 0, 13
; GFX9-SDAG-NEXT:    v_lshrrev_b32_e32 v5, v4, v2
; GFX9-SDAG-NEXT:    v_lshlrev_b32_e32 v4, v4, v5
; GFX9-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, v4, v2
; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-SDAG-NEXT:    v_add_u32_e32 v3, 0xfffffc10, v3
; GFX9-SDAG-NEXT:    v_or_b32_e32 v2, v5, v2
; GFX9-SDAG-NEXT:    v_lshl_or_b32 v4, v3, 12, v0
; GFX9-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v3
; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX9-SDAG-NEXT:    v_and_b32_e32 v4, 7, v2
; GFX9-SDAG-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v4
; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX9-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v4
; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX9-SDAG-NEXT:    v_or_b32_e32 v4, v4, v5
; GFX9-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
; GFX9-SDAG-NEXT:    v_add_u32_e32 v2, v2, v4
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v4, 0x7c00
; GFX9-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v3
; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v5, 0x7e00
; GFX9-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-SDAG-NEXT:    s_movk_i32 s4, 0x40f
; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v0, v4, v5, vcc
; GFX9-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, s4, v3
; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX9-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
; GFX9-SDAG-NEXT:    s_mov_b32 s4, 0x8000
; GFX9-SDAG-NEXT:    v_and_or_b32 v0, v1, s4, v0
; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: fptrunc_f64_to_f16:
; GFX9-GISEL:       ; %bb.0:
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v5, 0x1ff
; GFX9-GISEL-NEXT:    v_and_or_b32 v0, v1, v5, v0
; GFX9-GISEL-NEXT:    v_bfe_u32 v2, v1, 20, 11
; GFX9-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-GISEL-NEXT:    v_add_u32_e32 v2, 0xfffffc10, v2
; GFX9-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 8, v1
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v4, 0xffe
; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9-GISEL-NEXT:    v_and_or_b32 v0, v3, v4, v0
; GFX9-GISEL-NEXT:    v_sub_u32_e32 v6, 1, v2
; GFX9-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-GISEL-NEXT:    v_lshl_or_b32 v5, v2, 12, v0
; GFX9-GISEL-NEXT:    v_med3_i32 v6, v6, 0, 13
; GFX9-GISEL-NEXT:    v_or_b32_e32 v0, 0x1000, v0
; GFX9-GISEL-NEXT:    v_lshrrev_b32_e32 v7, v6, v0
; GFX9-GISEL-NEXT:    v_lshlrev_b32_e32 v6, v6, v7
; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX9-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, v6, v0
; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9-GISEL-NEXT:    v_or_b32_e32 v0, v7, v0
; GFX9-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v2
; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc
; GFX9-GISEL-NEXT:    v_and_b32_e32 v5, 7, v0
; GFX9-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v5
; GFX9-GISEL-NEXT:    v_cmp_lt_i32_e64 s[4:5], 5, v5
; GFX9-GISEL-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
; GFX9-GISEL-NEXT:    v_lshrrev_b32_e32 v0, 2, v0
; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s[4:5]
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v4, 0x7c00
; GFX9-GISEL-NEXT:    v_add_u32_e32 v0, v0, v5
; GFX9-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, 30, v2
; GFX9-GISEL-NEXT:    v_lshl_or_b32 v3, v3, 9, v4
; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v4, 0x40f
; GFX9-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v4
; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-GISEL-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v2, 0x8000
; GFX9-GISEL-NEXT:    v_and_or_b32 v0, v1, v2, v0
; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX950-SDAG-LABEL: fptrunc_f64_to_f16:
; GFX950-SDAG:       ; %bb.0:
; GFX950-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-SDAG-NEXT:    s_movk_i32 s0, 0x1ff
; GFX950-SDAG-NEXT:    v_and_or_b32 v0, v1, s0, v0
; GFX950-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; GFX950-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 8, v1
; GFX950-SDAG-NEXT:    s_movk_i32 s0, 0xffe
; GFX950-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX950-SDAG-NEXT:    v_bfe_u32 v3, v1, 20, 11
; GFX950-SDAG-NEXT:    v_and_or_b32 v0, v2, s0, v0
; GFX950-SDAG-NEXT:    v_sub_u32_e32 v4, 0x3f1, v3
; GFX950-SDAG-NEXT:    v_or_b32_e32 v2, 0x1000, v0
; GFX950-SDAG-NEXT:    v_med3_i32 v4, v4, 0, 13
; GFX950-SDAG-NEXT:    v_lshrrev_b32_e32 v5, v4, v2
; GFX950-SDAG-NEXT:    v_lshlrev_b32_e32 v4, v4, v5
; GFX950-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, v4, v2
; GFX950-SDAG-NEXT:    v_add_u32_e32 v3, 0xfffffc10, v3
; GFX950-SDAG-NEXT:    v_lshl_or_b32 v4, v3, 12, v0
; GFX950-SDAG-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX950-SDAG-NEXT:    v_or_b32_e32 v2, v5, v2
; GFX950-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v3
; GFX950-SDAG-NEXT:    s_movk_i32 s0, 0x40f
; GFX950-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
; GFX950-SDAG-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX950-SDAG-NEXT:    v_and_b32_e32 v4, 7, v2
; GFX950-SDAG-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v4
; GFX950-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
; GFX950-SDAG-NEXT:    s_nop 0
; GFX950-SDAG-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX950-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v4
; GFX950-SDAG-NEXT:    s_nop 1
; GFX950-SDAG-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX950-SDAG-NEXT:    v_or_b32_e32 v4, v4, v5
; GFX950-SDAG-NEXT:    v_add_u32_e32 v2, v2, v4
; GFX950-SDAG-NEXT:    v_mov_b32_e32 v4, 0x7c00
; GFX950-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v3
; GFX950-SDAG-NEXT:    v_mov_b32_e32 v5, 0x7e00
; GFX950-SDAG-NEXT:    s_nop 0
; GFX950-SDAG-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX950-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; GFX950-SDAG-NEXT:    s_nop 1
; GFX950-SDAG-NEXT:    v_cndmask_b32_e32 v0, v4, v5, vcc
; GFX950-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, s0, v3
; GFX950-SDAG-NEXT:    s_mov_b32 s0, 0x8000
; GFX950-SDAG-NEXT:    s_nop 0
; GFX950-SDAG-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX950-SDAG-NEXT:    v_and_or_b32 v0, v1, s0, v0
; GFX950-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX950-GISEL-LABEL: fptrunc_f64_to_f16:
; GFX950-GISEL:       ; %bb.0:
; GFX950-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-GISEL-NEXT:    v_mov_b32_e32 v5, 0x1ff
; GFX950-GISEL-NEXT:    v_and_or_b32 v0, v1, v5, v0
; GFX950-GISEL-NEXT:    v_bfe_u32 v2, v1, 20, 11
; GFX950-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; GFX950-GISEL-NEXT:    v_add_u32_e32 v2, 0xfffffc10, v2
; GFX950-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 8, v1
; GFX950-GISEL-NEXT:    v_mov_b32_e32 v4, 0xffe
; GFX950-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX950-GISEL-NEXT:    v_and_or_b32 v0, v3, v4, v0
; GFX950-GISEL-NEXT:    v_sub_u32_e32 v6, 1, v2
; GFX950-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; GFX950-GISEL-NEXT:    v_lshl_or_b32 v5, v2, 12, v0
; GFX950-GISEL-NEXT:    v_med3_i32 v6, v6, 0, 13
; GFX950-GISEL-NEXT:    v_or_b32_e32 v0, 0x1000, v0
; GFX950-GISEL-NEXT:    v_lshrrev_b32_e32 v7, v6, v0
; GFX950-GISEL-NEXT:    v_lshlrev_b32_e32 v6, v6, v7
; GFX950-GISEL-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX950-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, v6, v0
; GFX950-GISEL-NEXT:    v_mov_b32_e32 v4, 0x7c00
; GFX950-GISEL-NEXT:    v_lshl_or_b32 v3, v3, 9, v4
; GFX950-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX950-GISEL-NEXT:    v_or_b32_e32 v0, v7, v0
; GFX950-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v2
; GFX950-GISEL-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
; GFX950-GISEL-NEXT:    s_nop 0
; GFX950-GISEL-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc
; GFX950-GISEL-NEXT:    v_and_b32_e32 v5, 7, v0
; GFX950-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v5
; GFX950-GISEL-NEXT:    v_cmp_lt_i32_e64 s[0:1], 5, v5
; GFX950-GISEL-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]
; GFX950-GISEL-NEXT:    v_lshrrev_b32_e32 v0, 2, v0
; GFX950-GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s[0:1]
; GFX950-GISEL-NEXT:    v_add_u32_e32 v0, v0, v5
; GFX950-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, 30, v2
; GFX950-GISEL-NEXT:    s_nop 1
; GFX950-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX950-GISEL-NEXT:    v_mov_b32_e32 v4, 0x40f
; GFX950-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v4
; GFX950-GISEL-NEXT:    v_mov_b32_e32 v2, 0x8000
; GFX950-GISEL-NEXT:    s_nop 0
; GFX950-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX950-GISEL-NEXT:    v_and_or_b32 v0, v1, v2, v0
; GFX950-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: fptrunc_f64_to_f16:
; GFX11-SDAG-TRUE16:       ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT:    v_and_or_b32 v0, v1, 0x1ff, v0
; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 8, v1
; GFX11-SDAG-TRUE16-NEXT:    v_bfe_u32 v3, v1, 20, 11
; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-SDAG-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-SDAG-TRUE16-NEXT:    v_sub_nc_u32_e32 v4, 0x3f1, v3
; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-SDAG-TRUE16-NEXT:    v_and_or_b32 v0, v2, 0xffe, v0
; GFX11-SDAG-TRUE16-NEXT:    v_med3_i32 v2, v4, 0, 13
; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT:    v_or_b32_e32 v4, 0x1000, v0
; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, v2, v4
; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, v2, v5
; GFX11-SDAG-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v2, v4
; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT:    v_or_b32_e32 v2, v5, v2
; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u32_e32 v3, 0xfffffc10, v3
; GFX11-SDAG-TRUE16-NEXT:    v_lshl_or_b32 v4, v3, 12, v0
; GFX11-SDAG-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v3
; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc_lo
; GFX11-SDAG-TRUE16-NEXT:    v_and_b32_e32 v4, 7, v2
; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 5, v4
; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v4
; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
; GFX11-SDAG-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-SDAG-TRUE16-NEXT:    v_or_b32_e32 v4, v4, v5
; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT:    v_dual_mov_b32 v5, 0x7e00 :: v_dual_add_nc_u32 v2, v2, v4
; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v0, 0x7c00, v5, vcc_lo
; GFX11-SDAG-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 31, v3
; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v2, 0x7c00, v2, vcc_lo
; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v3
; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT:    v_and_or_b32 v0, v1, 0x8000, v0
; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: fptrunc_f64_to_f16:
; GFX11-SDAG-FAKE16:       ; %bb.0:
; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT:    v_and_or_b32 v0, v1, 0x1ff, v0
; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 8, v1
; GFX11-SDAG-FAKE16-NEXT:    v_bfe_u32 v3, v1, 20, 11
; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-SDAG-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-SDAG-FAKE16-NEXT:    v_sub_nc_u32_e32 v4, 0x3f1, v3
; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-SDAG-FAKE16-NEXT:    v_and_or_b32 v0, v2, 0xffe, v0
; GFX11-SDAG-FAKE16-NEXT:    v_med3_i32 v2, v4, 0, 13
; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v4, 0x1000, v0
; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, v2, v4
; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, v2, v5
; GFX11-SDAG-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v2, v4
; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v2, v5, v2
; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u32_e32 v3, 0xfffffc10, v3
; GFX11-SDAG-FAKE16-NEXT:    v_lshl_or_b32 v4, v3, 12, v0
; GFX11-SDAG-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v3
; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc_lo
; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v4, 7, v2
; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 5, v4
; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v4
; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
; GFX11-SDAG-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v5
; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v5, 0x7e00 :: v_dual_add_nc_u32 v2, v2, v4
; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7c00, v5, vcc_lo
; GFX11-SDAG-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 31, v3
; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v2, 0x7c00, v2, vcc_lo
; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v3
; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT:    v_and_or_b32 v0, v1, 0x8000, v0
; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-GISEL-TRUE16-LABEL: fptrunc_f64_to_f16:
; GFX11-GISEL-TRUE16:       ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT:    v_and_or_b32 v0, v1, 0x1ff, v0
; GFX11-GISEL-TRUE16-NEXT:    v_bfe_u32 v2, v1, 20, 11
; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 8, v1
; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-GISEL-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-GISEL-TRUE16-NEXT:    v_add_nc_u32_e32 v2, 0xfffffc10, v2
; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-TRUE16-NEXT:    v_sub_nc_u32_e32 v4, 1, v2
; GFX11-GISEL-TRUE16-NEXT:    v_and_or_b32 v0, v3, 0xffe, v0
; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-TRUE16-NEXT:    v_med3_i32 v3, v4, 0, 13
; GFX11-GISEL-TRUE16-NEXT:    v_or_b32_e32 v4, 0x1000, v0
; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, v3, v4
; GFX11-GISEL-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, v3, v5
; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-GISEL-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v3, v4
; GFX11-GISEL-TRUE16-NEXT:    v_lshl_or_b32 v4, v2, 12, v0
; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc_lo
; GFX11-GISEL-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v2
; GFX11-GISEL-TRUE16-NEXT:    v_or_b32_e32 v3, v5, v3
; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX11-GISEL-TRUE16-NEXT:    v_and_b32_e32 v4, 7, v3
; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 2, v3
; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v4
; GFX11-GISEL-TRUE16-NEXT:    v_cmp_lt_i32_e64 s0, 5, v4
; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s0, vcc_lo, s0
; GFX11-GISEL-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s0
; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-GISEL-TRUE16-NEXT:    v_add_nc_u32_e32 v3, v3, v4
; GFX11-GISEL-TRUE16-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 30, v2
; GFX11-GISEL-TRUE16-NEXT:    v_lshl_or_b32 v0, v0, 9, 0x7c00
; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v3, v3, 0x7c00, vcc_lo
; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v2
; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc_lo
; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT:    v_and_or_b32 v0, v1, 0x8000, v0
; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: fptrunc_f64_to_f16:
; GFX11-GISEL-FAKE16:       ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT:    v_and_or_b32 v0, v1, 0x1ff, v0
; GFX11-GISEL-FAKE16-NEXT:    v_bfe_u32 v2, v1, 20, 11
; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 8, v1
; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-GISEL-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-GISEL-FAKE16-NEXT:    v_add_nc_u32_e32 v2, 0xfffffc10, v2
; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-FAKE16-NEXT:    v_sub_nc_u32_e32 v4, 1, v2
; GFX11-GISEL-FAKE16-NEXT:    v_and_or_b32 v0, v3, 0xffe, v0
; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-FAKE16-NEXT:    v_med3_i32 v3, v4, 0, 13
; GFX11-GISEL-FAKE16-NEXT:    v_or_b32_e32 v4, 0x1000, v0
; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, v3, v4
; GFX11-GISEL-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, v3, v5
; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-GISEL-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v3, v4
; GFX11-GISEL-FAKE16-NEXT:    v_lshl_or_b32 v4, v2, 12, v0
; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc_lo
; GFX11-GISEL-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v2
; GFX11-GISEL-FAKE16-NEXT:    v_or_b32_e32 v3, v5, v3
; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX11-GISEL-FAKE16-NEXT:    v_and_b32_e32 v4, 7, v3
; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 2, v3
; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v4
; GFX11-GISEL-FAKE16-NEXT:    v_cmp_lt_i32_e64 s0, 5, v4
; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s0, vcc_lo, s0
; GFX11-GISEL-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s0
; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-GISEL-FAKE16-NEXT:    v_add_nc_u32_e32 v3, v3, v4
; GFX11-GISEL-FAKE16-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 30, v2
; GFX11-GISEL-FAKE16-NEXT:    v_lshl_or_b32 v0, v0, 9, 0x7c00
; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v3, v3, 0x7c00, vcc_lo
; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v2
; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc_lo
; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-FAKE16-NEXT:    v_and_or_b32 v0, v1, 0x8000, v0
; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1250-SDAG-TRUE16-LABEL: fptrunc_f64_to_f16:
; GFX1250-SDAG-TRUE16:       ; %bb.0:
; GFX1250-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-TRUE16-NEXT:    v_and_or_b32 v0, v1, 0x1ff, v0
; GFX1250-SDAG-TRUE16-NEXT:    v_bfe_u32 v3, v1, 20, 11
; GFX1250-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 8, v1
; GFX1250-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
; GFX1250-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1250-SDAG-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX1250-SDAG-TRUE16-NEXT:    v_sub_nc_u32_e32 v4, 0x3f1, v3
; GFX1250-SDAG-TRUE16-NEXT:    v_add_nc_u32_e32 v3, 0xfffffc10, v3
; GFX1250-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX1250-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1250-SDAG-TRUE16-NEXT:    v_and_or_b32 v0, v2, 0xffe, v0
; GFX1250-SDAG-TRUE16-NEXT:    v_med3_i32 v2, v4, 0, 13
; GFX1250-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-TRUE16-NEXT:    v_or_b32_e32 v4, 0x1000, v0
; GFX1250-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, v2, v4
; GFX1250-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, v2, v5
; GFX1250-SDAG-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v2, v4
; GFX1250-SDAG-TRUE16-NEXT:    v_lshl_or_b32 v4, v3, 12, v0
; GFX1250-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX1250-SDAG-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v3
; GFX1250-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-TRUE16-NEXT:    v_or_b32_e32 v2, v5, v2
; GFX1250-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc_lo
; GFX1250-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-TRUE16-NEXT:    v_and_b32_e32 v4, 7, v2
; GFX1250-SDAG-TRUE16-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 5, v4
; GFX1250-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX1250-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v4
; GFX1250-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
; GFX1250-SDAG-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX1250-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-TRUE16-NEXT:    v_dual_lshrrev_b32 v2, 2, v2 :: v_dual_bitop2_b32 v4, v4, v5 bitop3:0x54
; GFX1250-SDAG-TRUE16-NEXT:    v_dual_mov_b32 v5, 0x7e00 :: v_dual_add_nc_u32 v2, v2, v4
; GFX1250-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1250-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v0, 0x7c00, v5, vcc_lo
; GFX1250-SDAG-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 31, v3
; GFX1250-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v2, 0x7c00, v2, vcc_lo
; GFX1250-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v3
; GFX1250-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX1250-SDAG-TRUE16-NEXT:    v_and_or_b32 v0, v1, 0x8000, v0
; GFX1250-SDAG-TRUE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-SDAG-FAKE16-LABEL: fptrunc_f64_to_f16:
; GFX1250-SDAG-FAKE16:       ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-FAKE16-NEXT:    v_and_or_b32 v0, v1, 0x1ff, v0
; GFX1250-SDAG-FAKE16-NEXT:    v_bfe_u32 v3, v1, 20, 11
; GFX1250-SDAG-FAKE16-NEXT:    v_dual_lshrrev_b32 v2, 8, v1 :: v_dual_lshrrev_b32 v1, 16, v1
; GFX1250-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-SDAG-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX1250-SDAG-FAKE16-NEXT:    v_sub_nc_u32_e32 v4, 0x3f1, v3
; GFX1250-SDAG-FAKE16-NEXT:    v_add_nc_u32_e32 v3, 0xfffffc10, v3
; GFX1250-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX1250-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1250-SDAG-FAKE16-NEXT:    v_and_or_b32 v0, v2, 0xffe, v0
; GFX1250-SDAG-FAKE16-NEXT:    v_med3_i32 v2, v4, 0, 13
; GFX1250-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-FAKE16-NEXT:    v_or_b32_e32 v4, 0x1000, v0
; GFX1250-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, v2, v4
; GFX1250-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, v2, v5
; GFX1250-SDAG-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v2, v4
; GFX1250-SDAG-FAKE16-NEXT:    v_lshl_or_b32 v4, v3, 12, v0
; GFX1250-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX1250-SDAG-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v3
; GFX1250-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-FAKE16-NEXT:    v_or_b32_e32 v2, v5, v2
; GFX1250-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc_lo
; GFX1250-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-FAKE16-NEXT:    v_and_b32_e32 v4, 7, v2
; GFX1250-SDAG-FAKE16-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 5, v4
; GFX1250-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX1250-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v4
; GFX1250-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
; GFX1250-SDAG-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX1250-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-FAKE16-NEXT:    v_dual_lshrrev_b32 v2, 2, v2 :: v_dual_bitop2_b32 v4, v4, v5 bitop3:0x54
; GFX1250-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v5, 0x7e00 :: v_dual_add_nc_u32 v2, v2, v4
; GFX1250-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1250-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7c00, v5, vcc_lo
; GFX1250-SDAG-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 31, v3
; GFX1250-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v2, 0x7c00, v2, vcc_lo
; GFX1250-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v3
; GFX1250-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX1250-SDAG-FAKE16-NEXT:    v_and_or_b32 v0, v1, 0x8000, v0
; GFX1250-SDAG-FAKE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-GISEL-TRUE16-LABEL: fptrunc_f64_to_f16:
; GFX1250-GISEL-TRUE16:       ; %bb.0:
; GFX1250-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT:    v_and_or_b32 v0, v1, 0x1ff, v0
; GFX1250-GISEL-TRUE16-NEXT:    v_bfe_u32 v2, v1, 20, 11
; GFX1250-GISEL-TRUE16-NEXT:    v_dual_lshrrev_b32 v3, 8, v1 :: v_dual_lshrrev_b32 v1, 16, v1
; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-GISEL-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX1250-GISEL-TRUE16-NEXT:    v_add_nc_u32_e32 v2, 0xfffffc10, v2
; GFX1250-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-GISEL-TRUE16-NEXT:    v_sub_nc_u32_e32 v4, 1, v2
; GFX1250-GISEL-TRUE16-NEXT:    v_and_or_b32 v0, v3, 0xffe, v0
; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-GISEL-TRUE16-NEXT:    v_med3_i32 v3, v4, 0, 13
; GFX1250-GISEL-TRUE16-NEXT:    v_or_b32_e32 v4, 0x1000, v0
; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, v3, v4
; GFX1250-GISEL-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, v3, v5
; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1250-GISEL-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v3, v4
; GFX1250-GISEL-TRUE16-NEXT:    v_lshl_or_b32 v4, v2, 12, v0
; GFX1250-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc_lo
; GFX1250-GISEL-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v2
; GFX1250-GISEL-TRUE16-NEXT:    v_or_b32_e32 v3, v5, v3
; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-GISEL-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX1250-GISEL-TRUE16-NEXT:    v_and_b32_e32 v4, 7, v3
; GFX1250-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 2, v3
; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1250-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v4
; GFX1250-GISEL-TRUE16-NEXT:    v_cmp_lt_i32_e64 s0, 5, v4
; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s0, vcc_lo, s0
; GFX1250-GISEL-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX1250-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s0
; GFX1250-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1250-GISEL-TRUE16-NEXT:    v_add_nc_u32_e32 v3, v3, v4
; GFX1250-GISEL-TRUE16-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 30, v2
; GFX1250-GISEL-TRUE16-NEXT:    v_lshl_or_b32 v0, v0, 9, 0x7c00
; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v3, v3, 0x7c00, vcc_lo
; GFX1250-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v2
; GFX1250-GISEL-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc_lo
; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-TRUE16-NEXT:    v_and_or_b32 v0, v1, 0x8000, v0
; GFX1250-GISEL-TRUE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-GISEL-FAKE16-LABEL: fptrunc_f64_to_f16:
; GFX1250-GISEL-FAKE16:       ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT:    v_and_or_b32 v0, v1, 0x1ff, v0
; GFX1250-GISEL-FAKE16-NEXT:    v_bfe_u32 v2, v1, 20, 11
; GFX1250-GISEL-FAKE16-NEXT:    v_dual_lshrrev_b32 v3, 8, v1 :: v_dual_lshrrev_b32 v1, 16, v1
; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-GISEL-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX1250-GISEL-FAKE16-NEXT:    v_add_nc_u32_e32 v2, 0xfffffc10, v2
; GFX1250-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-GISEL-FAKE16-NEXT:    v_sub_nc_u32_e32 v4, 1, v2
; GFX1250-GISEL-FAKE16-NEXT:    v_and_or_b32 v0, v3, 0xffe, v0
; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-GISEL-FAKE16-NEXT:    v_med3_i32 v3, v4, 0, 13
; GFX1250-GISEL-FAKE16-NEXT:    v_or_b32_e32 v4, 0x1000, v0
; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, v3, v4
; GFX1250-GISEL-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, v3, v5
; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1250-GISEL-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v3, v4
; GFX1250-GISEL-FAKE16-NEXT:    v_lshl_or_b32 v4, v2, 12, v0
; GFX1250-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc_lo
; GFX1250-GISEL-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v2
; GFX1250-GISEL-FAKE16-NEXT:    v_or_b32_e32 v3, v5, v3
; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX1250-GISEL-FAKE16-NEXT:    v_and_b32_e32 v4, 7, v3
; GFX1250-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 2, v3
; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1250-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v4
; GFX1250-GISEL-FAKE16-NEXT:    v_cmp_lt_i32_e64 s0, 5, v4
; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s0, vcc_lo, s0
; GFX1250-GISEL-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX1250-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s0
; GFX1250-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1250-GISEL-FAKE16-NEXT:    v_add_nc_u32_e32 v3, v3, v4
; GFX1250-GISEL-FAKE16-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 30, v2
; GFX1250-GISEL-FAKE16-NEXT:    v_lshl_or_b32 v0, v0, 9, 0x7c00
; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v3, v3, 0x7c00, vcc_lo
; GFX1250-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v2
; GFX1250-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc_lo
; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-FAKE16-NEXT:    v_and_or_b32 v0, v1, 0x8000, v0
; GFX1250-GISEL-FAKE16-NEXT:    s_set_pc_i64 s[30:31]
  %r.val = fptrunc double %a to half
  ret half %r.val
}

define half @fptrunc_f64_to_f16_afn(double %a) {
; SI-SDAG-LABEL: fptrunc_f64_to_f16_afn:
; SI-SDAG:       ; %bb.0:
; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-SDAG-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; SI-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; SI-GISEL-LABEL: fptrunc_f64_to_f16_afn:
; SI-GISEL:       ; %bb.0:
; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-GISEL-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; SI-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: fptrunc_f64_to_f16_afn:
; VI-SDAG:       ; %bb.0:
; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; VI-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: fptrunc_f64_to_f16_afn:
; VI-GISEL:       ; %bb.0:
; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; VI-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: fptrunc_f64_to_f16_afn:
; GFX9-SDAG:       ; %bb.0:
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; GFX9-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: fptrunc_f64_to_f16_afn:
; GFX9-GISEL:       ; %bb.0:
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; GFX9-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX950-SDAG-LABEL: fptrunc_f64_to_f16_afn:
; GFX950-SDAG:       ; %bb.0:
; GFX950-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-SDAG-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; GFX950-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX950-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX950-GISEL-LABEL: fptrunc_f64_to_f16_afn:
; GFX950-GISEL:       ; %bb.0:
; GFX950-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-GISEL-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; GFX950-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX950-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: fptrunc_f64_to_f16_afn:
; GFX11-SDAG-TRUE16:       ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: fptrunc_f64_to_f16_afn:
; GFX11-SDAG-FAKE16:       ; %bb.0:
; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-GISEL-TRUE16-LABEL: fptrunc_f64_to_f16_afn:
; GFX11-GISEL-TRUE16:       ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: fptrunc_f64_to_f16_afn:
; GFX11-GISEL-FAKE16:       ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1250-SDAG-TRUE16-LABEL: fptrunc_f64_to_f16_afn:
; GFX1250-SDAG-TRUE16:       ; %bb.0:
; GFX1250-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-TRUE16-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; GFX1250-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
; GFX1250-SDAG-TRUE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-SDAG-FAKE16-LABEL: fptrunc_f64_to_f16_afn:
; GFX1250-SDAG-FAKE16:       ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-FAKE16-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; GFX1250-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX1250-SDAG-FAKE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-GISEL-TRUE16-LABEL: fptrunc_f64_to_f16_afn:
; GFX1250-GISEL-TRUE16:       ; %bb.0:
; GFX1250-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
; GFX1250-GISEL-TRUE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-GISEL-FAKE16-LABEL: fptrunc_f64_to_f16_afn:
; GFX1250-GISEL-FAKE16:       ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX1250-GISEL-FAKE16-NEXT:    s_set_pc_i64 s[30:31]
  %r.val = fptrunc afn double %a to half
  ret half %r.val
}

define <2 x half> @fptrunc_v2f32_to_v2f16(<2 x float> %a) {
; SI-SDAG-LABEL: fptrunc_v2f32_to_v2f16:
; SI-SDAG:       ; %bb.0:
; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-SDAG-NEXT:    v_cvt_f16_f32_e32 v1, v1
; SI-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-SDAG-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; SI-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; SI-GISEL-LABEL: fptrunc_v2f32_to_v2f16:
; SI-GISEL:       ; %bb.0:
; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-GISEL-NEXT:    v_cvt_f16_f32_e32 v1, v1
; SI-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-GISEL-NEXT:    v_bfe_u32 v1, v1, 0, 16
; SI-GISEL-NEXT:    v_bfe_u32 v0, v0, 0, 16
; SI-GISEL-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; SI-GISEL-NEXT:    v_or_b32_e32 v0, v0, v1
; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: fptrunc_v2f32_to_v2f16:
; VI-SDAG:       ; %bb.0:
; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-NEXT:    v_cvt_f16_f32_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
; VI-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
; VI-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: fptrunc_v2f32_to_v2f16:
; VI-GISEL:       ; %bb.0:
; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT:    v_cvt_f16_f32_e32 v1, v1
; VI-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 16
; VI-GISEL-NEXT:    v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-GISEL-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: fptrunc_v2f32_to_v2f16:
; GFX9-SDAG:       ; %bb.0:
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX9-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX9-SDAG-NEXT:    v_pack_b32_f16 v0, v0, v1
; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: fptrunc_v2f32_to_v2f16:
; GFX9-GISEL:       ; %bb.0:
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX9-GISEL-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX9-GISEL-NEXT:    v_pack_b32_f16 v0, v0, v1
; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX950-SDAG-LABEL: fptrunc_v2f32_to_v2f16:
; GFX950-SDAG:       ; %bb.0:
; GFX950-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-SDAG-NEXT:    v_cvt_pk_f16_f32 v0, v0, v1
; GFX950-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX950-GISEL-LABEL: fptrunc_v2f32_to_v2f16:
; GFX950-GISEL:       ; %bb.0:
; GFX950-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-GISEL-NEXT:    v_cvt_pk_f16_f32 v0, v0, v1
; GFX950-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: fptrunc_v2f32_to_v2f16:
; GFX11-SDAG-TRUE16:       ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT:    v_cvt_f16_f32_e32 v1.h, v1
; GFX11-SDAG-TRUE16-NEXT:    v_cvt_f16_f32_e32 v1.l, v0
; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, v1
; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: fptrunc_v2f32_to_v2f16:
; GFX11-SDAG-FAKE16:       ; %bb.0:
; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX11-SDAG-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-GISEL-TRUE16-LABEL: fptrunc_v2f32_to_v2f16:
; GFX11-GISEL-TRUE16:       ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
; GFX11-GISEL-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.h, v1
; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: fptrunc_v2f32_to_v2f16:
; GFX11-GISEL-FAKE16:       ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX11-GISEL-FAKE16-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1250-SDAG-TRUE16-LABEL: fptrunc_v2f32_to_v2f16:
; GFX1250-SDAG-TRUE16:       ; %bb.0:
; GFX1250-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-TRUE16-NEXT:    v_cvt_pk_f16_f32 v0, v0, v1
; GFX1250-SDAG-TRUE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-SDAG-FAKE16-LABEL: fptrunc_v2f32_to_v2f16:
; GFX1250-SDAG-FAKE16:       ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-FAKE16-NEXT:    v_cvt_pk_f16_f32 v0, v0, v1
; GFX1250-SDAG-FAKE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-GISEL-TRUE16-LABEL: fptrunc_v2f32_to_v2f16:
; GFX1250-GISEL-TRUE16:       ; %bb.0:
; GFX1250-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT:    v_cvt_pk_f16_f32 v0, v0, v1
; GFX1250-GISEL-TRUE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-GISEL-FAKE16-LABEL: fptrunc_v2f32_to_v2f16:
; GFX1250-GISEL-FAKE16:       ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_pk_f16_f32 v0, v0, v1
; GFX1250-GISEL-FAKE16-NEXT:    s_set_pc_i64 s[30:31]
  %r.val = fptrunc <2 x float> %a to <2 x half>
  ret <2 x half> %r.val
}

define <2 x half> @fptrunc_v2f64_to_v2f16(<2 x double> %a) {
; SI-SDAG-LABEL: fptrunc_v2f64_to_v2f16:
; SI-SDAG:       ; %bb.0:
; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-SDAG-NEXT:    v_and_b32_e32 v5, 0x1ff, v3
; SI-SDAG-NEXT:    v_or_b32_e32 v2, v5, v2
; SI-SDAG-NEXT:    v_lshrrev_b32_e32 v4, 8, v3
; SI-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
; SI-SDAG-NEXT:    v_and_b32_e32 v4, 0xffe, v4
; SI-SDAG-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
; SI-SDAG-NEXT:    v_bfe_u32 v5, v3, 20, 11
; SI-SDAG-NEXT:    s_movk_i32 s4, 0x3f1
; SI-SDAG-NEXT:    v_or_b32_e32 v2, v4, v2
; SI-SDAG-NEXT:    v_sub_i32_e32 v6, vcc, s4, v5
; SI-SDAG-NEXT:    v_or_b32_e32 v4, 0x1000, v2
; SI-SDAG-NEXT:    v_med3_i32 v6, v6, 0, 13
; SI-SDAG-NEXT:    v_lshrrev_b32_e32 v7, v6, v4
; SI-SDAG-NEXT:    v_lshlrev_b32_e32 v6, v6, v7
; SI-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, v6, v4
; SI-SDAG-NEXT:    s_movk_i32 s5, 0xfc10
; SI-SDAG-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
; SI-SDAG-NEXT:    v_add_i32_e32 v5, vcc, s5, v5
; SI-SDAG-NEXT:    v_lshlrev_b32_e32 v6, 12, v5
; SI-SDAG-NEXT:    v_or_b32_e32 v4, v7, v4
; SI-SDAG-NEXT:    v_or_b32_e32 v6, v2, v6
; SI-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v5
; SI-SDAG-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc
; SI-SDAG-NEXT:    v_and_b32_e32 v6, 7, v4
; SI-SDAG-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v6
; SI-SDAG-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
; SI-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v6
; SI-SDAG-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
; SI-SDAG-NEXT:    v_or_b32_e32 v6, v6, v7
; SI-SDAG-NEXT:    v_lshrrev_b32_e32 v4, 2, v4
; SI-SDAG-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
; SI-SDAG-NEXT:    v_mov_b32_e32 v6, 0x7c00
; SI-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v5
; SI-SDAG-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc
; SI-SDAG-NEXT:    v_mov_b32_e32 v7, 0x7e00
; SI-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
; SI-SDAG-NEXT:    s_movk_i32 s6, 0x40f
; SI-SDAG-NEXT:    v_cndmask_b32_e32 v2, v6, v7, vcc
; SI-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, s6, v5
; SI-SDAG-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; SI-SDAG-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
; SI-SDAG-NEXT:    v_and_b32_e32 v4, 0x1ff, v1
; SI-SDAG-NEXT:    v_and_b32_e32 v3, 0x8000, v3
; SI-SDAG-NEXT:    v_or_b32_e32 v0, v4, v0
; SI-SDAG-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-SDAG-NEXT:    v_lshrrev_b32_e32 v3, 8, v1
; SI-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; SI-SDAG-NEXT:    v_and_b32_e32 v3, 0xffe, v3
; SI-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-SDAG-NEXT:    v_bfe_u32 v4, v1, 20, 11
; SI-SDAG-NEXT:    v_or_b32_e32 v0, v3, v0
; SI-SDAG-NEXT:    v_sub_i32_e32 v5, vcc, s4, v4
; SI-SDAG-NEXT:    v_or_b32_e32 v3, 0x1000, v0
; SI-SDAG-NEXT:    v_med3_i32 v5, v5, 0, 13
; SI-SDAG-NEXT:    v_lshrrev_b32_e32 v8, v5, v3
; SI-SDAG-NEXT:    v_lshlrev_b32_e32 v5, v5, v8
; SI-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, v5, v3
; SI-SDAG-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
; SI-SDAG-NEXT:    v_add_i32_e32 v4, vcc, s5, v4
; SI-SDAG-NEXT:    v_lshlrev_b32_e32 v5, 12, v4
; SI-SDAG-NEXT:    v_or_b32_e32 v3, v8, v3
; SI-SDAG-NEXT:    v_or_b32_e32 v5, v0, v5
; SI-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v4
; SI-SDAG-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
; SI-SDAG-NEXT:    v_and_b32_e32 v5, 7, v3
; SI-SDAG-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v5
; SI-SDAG-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
; SI-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v5
; SI-SDAG-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
; SI-SDAG-NEXT:    v_or_b32_e32 v5, v5, v8
; SI-SDAG-NEXT:    v_lshrrev_b32_e32 v3, 2, v3
; SI-SDAG-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
; SI-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v4
; SI-SDAG-NEXT:    v_cndmask_b32_e32 v3, v6, v3, vcc
; SI-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; SI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v6, v7, vcc
; SI-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, s6, v4
; SI-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
; SI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc
; SI-SDAG-NEXT:    v_and_b32_e32 v1, 0x8000, v1
; SI-SDAG-NEXT:    v_or_b32_e32 v0, v1, v0
; SI-SDAG-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-SDAG-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-SDAG-NEXT:    v_or_b32_e32 v0, v0, v2
; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; SI-GISEL-LABEL: fptrunc_v2f64_to_v2f16:
; SI-GISEL:       ; %bb.0:
; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-GISEL-NEXT:    v_bfe_u32 v4, v1, 20, 11
; SI-GISEL-NEXT:    v_and_b32_e32 v7, 0x1ff, v1
; SI-GISEL-NEXT:    v_add_i32_e32 v4, vcc, 0xfffffc10, v4
; SI-GISEL-NEXT:    v_or_b32_e32 v0, v7, v0
; SI-GISEL-NEXT:    v_lshrrev_b32_e32 v6, 8, v1
; SI-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; SI-GISEL-NEXT:    v_and_b32_e32 v6, 0xffe, v6
; SI-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-GISEL-NEXT:    v_or_b32_e32 v0, v6, v0
; SI-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; SI-GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
; SI-GISEL-NEXT:    v_lshlrev_b32_e32 v8, 12, v4
; SI-GISEL-NEXT:    v_sub_i32_e32 v9, vcc, 1, v4
; SI-GISEL-NEXT:    v_or_b32_e32 v8, v0, v8
; SI-GISEL-NEXT:    v_med3_i32 v9, v9, 0, 13
; SI-GISEL-NEXT:    v_or_b32_e32 v0, 0x1000, v0
; SI-GISEL-NEXT:    v_lshrrev_b32_e32 v10, v9, v0
; SI-GISEL-NEXT:    v_lshlrev_b32_e32 v9, v9, v10
; SI-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, v9, v0
; SI-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-GISEL-NEXT:    v_or_b32_e32 v0, v10, v0
; SI-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v4
; SI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
; SI-GISEL-NEXT:    v_and_b32_e32 v8, 7, v0
; SI-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v8
; SI-GISEL-NEXT:    v_cmp_lt_i32_e64 s[4:5], 5, v8
; SI-GISEL-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
; SI-GISEL-NEXT:    v_lshrrev_b32_e32 v0, 2, v0
; SI-GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
; SI-GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v8
; SI-GISEL-NEXT:    v_lshlrev_b32_e32 v6, 9, v6
; SI-GISEL-NEXT:    v_mov_b32_e32 v7, 0x7c00
; SI-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, 30, v4
; SI-GISEL-NEXT:    v_mov_b32_e32 v8, 0x40f
; SI-GISEL-NEXT:    v_or_b32_e32 v6, 0x7c00, v6
; SI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v7, vcc
; SI-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v4, v8
; SI-GISEL-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
; SI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
; SI-GISEL-NEXT:    v_and_b32_e32 v1, 0x8000, v1
; SI-GISEL-NEXT:    v_mov_b32_e32 v5, 0xfffffc10
; SI-GISEL-NEXT:    v_or_b32_e32 v0, v1, v0
; SI-GISEL-NEXT:    v_bfe_u32 v1, v3, 20, 11
; SI-GISEL-NEXT:    v_add_i32_e32 v1, vcc, v1, v5
; SI-GISEL-NEXT:    v_and_b32_e32 v5, 0x1ff, v3
; SI-GISEL-NEXT:    v_or_b32_e32 v2, v5, v2
; SI-GISEL-NEXT:    v_lshrrev_b32_e32 v4, 8, v3
; SI-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
; SI-GISEL-NEXT:    v_and_b32_e32 v4, 0xffe, v4
; SI-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
; SI-GISEL-NEXT:    v_or_b32_e32 v2, v4, v2
; SI-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
; SI-GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
; SI-GISEL-NEXT:    v_lshlrev_b32_e32 v5, 12, v1
; SI-GISEL-NEXT:    v_sub_i32_e32 v6, vcc, 1, v1
; SI-GISEL-NEXT:    v_or_b32_e32 v5, v2, v5
; SI-GISEL-NEXT:    v_med3_i32 v6, v6, 0, 13
; SI-GISEL-NEXT:    v_or_b32_e32 v2, 0x1000, v2
; SI-GISEL-NEXT:    v_lshrrev_b32_e32 v9, v6, v2
; SI-GISEL-NEXT:    v_lshlrev_b32_e32 v6, v6, v9
; SI-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, v6, v2
; SI-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
; SI-GISEL-NEXT:    v_or_b32_e32 v2, v9, v2
; SI-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v1
; SI-GISEL-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
; SI-GISEL-NEXT:    v_and_b32_e32 v5, 7, v2
; SI-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v5
; SI-GISEL-NEXT:    v_cmp_lt_i32_e64 s[4:5], 5, v5
; SI-GISEL-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
; SI-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
; SI-GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s[4:5]
; SI-GISEL-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
; SI-GISEL-NEXT:    v_lshlrev_b32_e32 v4, 9, v4
; SI-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, 30, v1
; SI-GISEL-NEXT:    v_or_b32_e32 v4, 0x7c00, v4
; SI-GISEL-NEXT:    v_cndmask_b32_e32 v2, v2, v7, vcc
; SI-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v8
; SI-GISEL-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc
; SI-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
; SI-GISEL-NEXT:    v_and_b32_e32 v2, 0x8000, v2
; SI-GISEL-NEXT:    v_or_b32_e32 v1, v2, v1
; SI-GISEL-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-GISEL-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-GISEL-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; SI-GISEL-NEXT:    v_or_b32_e32 v0, v0, v1
; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: fptrunc_v2f64_to_v2f16:
; VI-SDAG:       ; %bb.0:
; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-NEXT:    v_and_b32_e32 v5, 0x1ff, v3
; VI-SDAG-NEXT:    v_or_b32_e32 v2, v5, v2
; VI-SDAG-NEXT:    v_lshrrev_b32_e32 v4, 8, v3
; VI-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
; VI-SDAG-NEXT:    v_and_b32_e32 v4, 0xffe, v4
; VI-SDAG-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
; VI-SDAG-NEXT:    v_bfe_u32 v5, v3, 20, 11
; VI-SDAG-NEXT:    s_movk_i32 s4, 0x3f1
; VI-SDAG-NEXT:    v_or_b32_e32 v2, v4, v2
; VI-SDAG-NEXT:    v_sub_u32_e32 v6, vcc, s4, v5
; VI-SDAG-NEXT:    v_or_b32_e32 v4, 0x1000, v2
; VI-SDAG-NEXT:    v_med3_i32 v6, v6, 0, 13
; VI-SDAG-NEXT:    v_lshrrev_b32_e32 v7, v6, v4
; VI-SDAG-NEXT:    v_lshlrev_b32_e32 v6, v6, v7
; VI-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, v6, v4
; VI-SDAG-NEXT:    s_movk_i32 s5, 0xfc10
; VI-SDAG-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
; VI-SDAG-NEXT:    v_add_u32_e32 v5, vcc, s5, v5
; VI-SDAG-NEXT:    v_lshlrev_b32_e32 v6, 12, v5
; VI-SDAG-NEXT:    v_or_b32_e32 v4, v7, v4
; VI-SDAG-NEXT:    v_or_b32_e32 v6, v2, v6
; VI-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v5
; VI-SDAG-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc
; VI-SDAG-NEXT:    v_and_b32_e32 v6, 7, v4
; VI-SDAG-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v6
; VI-SDAG-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
; VI-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v6
; VI-SDAG-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
; VI-SDAG-NEXT:    v_or_b32_e32 v6, v6, v7
; VI-SDAG-NEXT:    v_lshrrev_b32_e32 v4, 2, v4
; VI-SDAG-NEXT:    v_add_u32_e32 v4, vcc, v4, v6
; VI-SDAG-NEXT:    v_mov_b32_e32 v6, 0x7c00
; VI-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v5
; VI-SDAG-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc
; VI-SDAG-NEXT:    v_mov_b32_e32 v7, 0x7e00
; VI-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
; VI-SDAG-NEXT:    s_movk_i32 s6, 0x40f
; VI-SDAG-NEXT:    v_cndmask_b32_e32 v2, v6, v7, vcc
; VI-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, s6, v5
; VI-SDAG-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; VI-SDAG-NEXT:    v_mov_b32_e32 v4, 0x8000
; VI-SDAG-NEXT:    v_and_b32_e32 v5, 0x1ff, v1
; VI-SDAG-NEXT:    v_and_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-SDAG-NEXT:    v_or_b32_e32 v0, v5, v0
; VI-SDAG-NEXT:    v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-SDAG-NEXT:    v_lshrrev_b32_e32 v3, 8, v1
; VI-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; VI-SDAG-NEXT:    v_and_b32_e32 v3, 0xffe, v3
; VI-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; VI-SDAG-NEXT:    v_bfe_u32 v5, v1, 20, 11
; VI-SDAG-NEXT:    v_or_b32_e32 v0, v3, v0
; VI-SDAG-NEXT:    v_sub_u32_e32 v8, vcc, s4, v5
; VI-SDAG-NEXT:    v_or_b32_e32 v3, 0x1000, v0
; VI-SDAG-NEXT:    v_med3_i32 v8, v8, 0, 13
; VI-SDAG-NEXT:    v_lshrrev_b32_e32 v9, v8, v3
; VI-SDAG-NEXT:    v_lshlrev_b32_e32 v8, v8, v9
; VI-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, v8, v3
; VI-SDAG-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
; VI-SDAG-NEXT:    v_add_u32_e32 v5, vcc, s5, v5
; VI-SDAG-NEXT:    v_lshlrev_b32_e32 v8, 12, v5
; VI-SDAG-NEXT:    v_or_b32_e32 v3, v9, v3
; VI-SDAG-NEXT:    v_or_b32_e32 v8, v0, v8
; VI-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v5
; VI-SDAG-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc
; VI-SDAG-NEXT:    v_and_b32_e32 v8, 7, v3
; VI-SDAG-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v8
; VI-SDAG-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
; VI-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v8
; VI-SDAG-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
; VI-SDAG-NEXT:    v_or_b32_e32 v8, v8, v9
; VI-SDAG-NEXT:    v_lshrrev_b32_e32 v3, 2, v3
; VI-SDAG-NEXT:    v_add_u32_e32 v3, vcc, v3, v8
; VI-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v5
; VI-SDAG-NEXT:    v_cndmask_b32_e32 v3, v6, v3, vcc
; VI-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v6, v7, vcc
; VI-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, s6, v5
; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc
; VI-SDAG-NEXT:    v_and_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-SDAG-NEXT:    v_or_b32_e32 v0, v1, v0
; VI-SDAG-NEXT:    v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: fptrunc_v2f64_to_v2f16:
; VI-GISEL:       ; %bb.0:
; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT:    v_bfe_u32 v4, v1, 20, 11
; VI-GISEL-NEXT:    v_and_b32_e32 v7, 0x1ff, v1
; VI-GISEL-NEXT:    v_add_u32_e32 v4, vcc, 0xfffffc10, v4
; VI-GISEL-NEXT:    v_or_b32_e32 v0, v7, v0
; VI-GISEL-NEXT:    v_lshrrev_b32_e32 v6, 8, v1
; VI-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; VI-GISEL-NEXT:    v_and_b32_e32 v6, 0xffe, v6
; VI-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; VI-GISEL-NEXT:    v_or_b32_e32 v0, v6, v0
; VI-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; VI-GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
; VI-GISEL-NEXT:    v_lshlrev_b32_e32 v8, 12, v4
; VI-GISEL-NEXT:    v_sub_u32_e32 v9, vcc, 1, v4
; VI-GISEL-NEXT:    v_or_b32_e32 v8, v0, v8
; VI-GISEL-NEXT:    v_med3_i32 v9, v9, 0, 13
; VI-GISEL-NEXT:    v_or_b32_e32 v0, 0x1000, v0
; VI-GISEL-NEXT:    v_lshrrev_b32_e32 v10, v9, v0
; VI-GISEL-NEXT:    v_lshlrev_b32_e32 v9, v9, v10
; VI-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, v9, v0
; VI-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; VI-GISEL-NEXT:    v_or_b32_e32 v0, v10, v0
; VI-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v4
; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
; VI-GISEL-NEXT:    v_and_b32_e32 v8, 7, v0
; VI-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v8
; VI-GISEL-NEXT:    v_cmp_lt_i32_e64 s[4:5], 5, v8
; VI-GISEL-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
; VI-GISEL-NEXT:    v_lshrrev_b32_e32 v0, 2, v0
; VI-GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
; VI-GISEL-NEXT:    v_add_u32_e32 v0, vcc, v0, v8
; VI-GISEL-NEXT:    v_lshlrev_b32_e32 v6, 9, v6
; VI-GISEL-NEXT:    v_mov_b32_e32 v7, 0x7c00
; VI-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, 30, v4
; VI-GISEL-NEXT:    v_mov_b32_e32 v8, 0x40f
; VI-GISEL-NEXT:    v_or_b32_e32 v6, 0x7c00, v6
; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v7, vcc
; VI-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v4, v8
; VI-GISEL-NEXT:    v_mov_b32_e32 v4, 0x8000
; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
; VI-GISEL-NEXT:    v_and_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-GISEL-NEXT:    v_mov_b32_e32 v5, 0xfffffc10
; VI-GISEL-NEXT:    v_or_b32_e32 v0, v1, v0
; VI-GISEL-NEXT:    v_bfe_u32 v1, v3, 20, 11
; VI-GISEL-NEXT:    v_and_b32_e32 v6, 0x1ff, v3
; VI-GISEL-NEXT:    v_add_u32_e32 v1, vcc, v1, v5
; VI-GISEL-NEXT:    v_or_b32_e32 v2, v6, v2
; VI-GISEL-NEXT:    v_lshrrev_b32_e32 v5, 8, v3
; VI-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
; VI-GISEL-NEXT:    v_and_b32_e32 v5, 0xffe, v5
; VI-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
; VI-GISEL-NEXT:    v_or_b32_e32 v2, v5, v2
; VI-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
; VI-GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
; VI-GISEL-NEXT:    v_lshlrev_b32_e32 v6, 12, v1
; VI-GISEL-NEXT:    v_sub_u32_e32 v9, vcc, 1, v1
; VI-GISEL-NEXT:    v_or_b32_e32 v6, v2, v6
; VI-GISEL-NEXT:    v_med3_i32 v9, v9, 0, 13
; VI-GISEL-NEXT:    v_or_b32_e32 v2, 0x1000, v2
; VI-GISEL-NEXT:    v_lshrrev_b32_e32 v10, v9, v2
; VI-GISEL-NEXT:    v_lshlrev_b32_e32 v9, v9, v10
; VI-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, v9, v2
; VI-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
; VI-GISEL-NEXT:    v_or_b32_e32 v2, v10, v2
; VI-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v1
; VI-GISEL-NEXT:    v_cndmask_b32_e32 v2, v6, v2, vcc
; VI-GISEL-NEXT:    v_and_b32_e32 v6, 7, v2
; VI-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v6
; VI-GISEL-NEXT:    v_cmp_lt_i32_e64 s[4:5], 5, v6
; VI-GISEL-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
; VI-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
; VI-GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[4:5]
; VI-GISEL-NEXT:    v_add_u32_e32 v2, vcc, v2, v6
; VI-GISEL-NEXT:    v_lshlrev_b32_e32 v5, 9, v5
; VI-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, 30, v1
; VI-GISEL-NEXT:    v_or_b32_e32 v5, 0x7c00, v5
; VI-GISEL-NEXT:    v_cndmask_b32_e32 v2, v2, v7, vcc
; VI-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v8
; VI-GISEL-NEXT:    v_cndmask_b32_e32 v1, v2, v5, vcc
; VI-GISEL-NEXT:    v_and_b32_sdwa v2, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-GISEL-NEXT:    v_or_b32_e32 v1, v2, v1
; VI-GISEL-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; VI-GISEL-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; VI-GISEL-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: fptrunc_v2f64_to_v2f16:
; GFX9-SDAG:       ; %bb.0:
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT:    s_movk_i32 s4, 0x1ff
; GFX9-SDAG-NEXT:    v_and_or_b32 v0, v1, s4, v0
; GFX9-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9-SDAG-NEXT:    v_lshrrev_b32_e32 v4, 8, v1
; GFX9-SDAG-NEXT:    s_movk_i32 s5, 0xffe
; GFX9-SDAG-NEXT:    v_bfe_u32 v5, v1, 20, 11
; GFX9-SDAG-NEXT:    v_and_or_b32 v0, v4, s5, v0
; GFX9-SDAG-NEXT:    v_sub_u32_e32 v6, 0x3f1, v5
; GFX9-SDAG-NEXT:    v_or_b32_e32 v4, 0x1000, v0
; GFX9-SDAG-NEXT:    v_med3_i32 v6, v6, 0, 13
; GFX9-SDAG-NEXT:    v_lshrrev_b32_e32 v7, v6, v4
; GFX9-SDAG-NEXT:    v_lshlrev_b32_e32 v6, v6, v7
; GFX9-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, v6, v4
; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX9-SDAG-NEXT:    v_add_u32_e32 v5, 0xfffffc10, v5
; GFX9-SDAG-NEXT:    v_or_b32_e32 v4, v7, v4
; GFX9-SDAG-NEXT:    v_lshl_or_b32 v6, v5, 12, v0
; GFX9-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v5
; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc
; GFX9-SDAG-NEXT:    v_and_b32_e32 v6, 7, v4
; GFX9-SDAG-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v6
; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX9-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v6
; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX9-SDAG-NEXT:    v_or_b32_e32 v6, v6, v7
; GFX9-SDAG-NEXT:    v_lshrrev_b32_e32 v4, 2, v4
; GFX9-SDAG-NEXT:    v_add_u32_e32 v4, v4, v6
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v6, 0x7c00
; GFX9-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v5
; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v7, 0x7e00
; GFX9-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-SDAG-NEXT:    s_movk_i32 s6, 0x40f
; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v0, v6, v7, vcc
; GFX9-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, s6, v5
; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX9-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
; GFX9-SDAG-NEXT:    s_mov_b32 s7, 0x8000
; GFX9-SDAG-NEXT:    v_and_or_b32 v0, v1, s7, v0
; GFX9-SDAG-NEXT:    v_and_or_b32 v1, v3, s4, v2
; GFX9-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 8, v3
; GFX9-SDAG-NEXT:    v_bfe_u32 v4, v3, 20, 11
; GFX9-SDAG-NEXT:    v_and_or_b32 v1, v2, s5, v1
; GFX9-SDAG-NEXT:    v_sub_u32_e32 v5, 0x3f1, v4
; GFX9-SDAG-NEXT:    v_or_b32_e32 v2, 0x1000, v1
; GFX9-SDAG-NEXT:    v_med3_i32 v5, v5, 0, 13
; GFX9-SDAG-NEXT:    v_lshrrev_b32_e32 v8, v5, v2
; GFX9-SDAG-NEXT:    v_lshlrev_b32_e32 v5, v5, v8
; GFX9-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, v5, v2
; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-SDAG-NEXT:    v_add_u32_e32 v4, 0xfffffc10, v4
; GFX9-SDAG-NEXT:    v_or_b32_e32 v2, v8, v2
; GFX9-SDAG-NEXT:    v_lshl_or_b32 v5, v4, 12, v1
; GFX9-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v4
; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
; GFX9-SDAG-NEXT:    v_and_b32_e32 v5, 7, v2
; GFX9-SDAG-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v5
; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX9-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v5
; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX9-SDAG-NEXT:    v_or_b32_e32 v5, v5, v8
; GFX9-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
; GFX9-SDAG-NEXT:    v_add_u32_e32 v2, v2, v5
; GFX9-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v4
; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v2, v6, v2, vcc
; GFX9-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v1, v6, v7, vcc
; GFX9-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, s6, v4
; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX9-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
; GFX9-SDAG-NEXT:    v_and_or_b32 v1, v2, s7, v1
; GFX9-SDAG-NEXT:    s_mov_b32 s4, 0x5040100
; GFX9-SDAG-NEXT:    v_perm_b32 v0, v1, v0, s4
; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: fptrunc_v2f64_to_v2f16:
; GFX9-GISEL:       ; %bb.0:
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v7, 0x1ff
; GFX9-GISEL-NEXT:    v_and_or_b32 v0, v1, v7, v0
; GFX9-GISEL-NEXT:    v_bfe_u32 v4, v1, 20, 11
; GFX9-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-GISEL-NEXT:    v_add_u32_e32 v4, 0xfffffc10, v4
; GFX9-GISEL-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v6, 0xffe
; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9-GISEL-NEXT:    v_and_or_b32 v0, v5, v6, v0
; GFX9-GISEL-NEXT:    v_sub_u32_e32 v10, 1, v4
; GFX9-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-GISEL-NEXT:    v_lshl_or_b32 v9, v4, 12, v0
; GFX9-GISEL-NEXT:    v_med3_i32 v10, v10, 0, 13
; GFX9-GISEL-NEXT:    v_or_b32_e32 v0, 0x1000, v0
; GFX9-GISEL-NEXT:    v_lshrrev_b32_e32 v11, v10, v0
; GFX9-GISEL-NEXT:    v_lshlrev_b32_e32 v10, v10, v11
; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX9-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, v10, v0
; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9-GISEL-NEXT:    v_or_b32_e32 v0, v11, v0
; GFX9-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v4
; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v0, v9, v0, vcc
; GFX9-GISEL-NEXT:    v_and_b32_e32 v9, 7, v0
; GFX9-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v9
; GFX9-GISEL-NEXT:    v_cmp_lt_i32_e64 s[4:5], 5, v9
; GFX9-GISEL-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
; GFX9-GISEL-NEXT:    v_lshrrev_b32_e32 v0, 2, v0
; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v8, 0x7c00
; GFX9-GISEL-NEXT:    v_add_u32_e32 v0, v0, v9
; GFX9-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, 30, v4
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v9, 0x40f
; GFX9-GISEL-NEXT:    v_lshl_or_b32 v5, v5, 9, v8
; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc
; GFX9-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v4, v9
; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
; GFX9-GISEL-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v4, 0x8000
; GFX9-GISEL-NEXT:    v_and_or_b32 v2, v3, v7, v2
; GFX9-GISEL-NEXT:    v_and_or_b32 v0, v1, v4, v0
; GFX9-GISEL-NEXT:    v_bfe_u32 v1, v3, 20, 11
; GFX9-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
; GFX9-GISEL-NEXT:    v_add_u32_e32 v1, 0xfffffc10, v1
; GFX9-GISEL-NEXT:    v_lshrrev_b32_e32 v5, 8, v3
; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-GISEL-NEXT:    v_and_or_b32 v2, v5, v6, v2
; GFX9-GISEL-NEXT:    v_sub_u32_e32 v7, 1, v1
; GFX9-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
; GFX9-GISEL-NEXT:    v_lshl_or_b32 v6, v1, 12, v2
; GFX9-GISEL-NEXT:    v_med3_i32 v7, v7, 0, 13
; GFX9-GISEL-NEXT:    v_or_b32_e32 v2, 0x1000, v2
; GFX9-GISEL-NEXT:    v_lshrrev_b32_e32 v10, v7, v2
; GFX9-GISEL-NEXT:    v_lshlrev_b32_e32 v7, v7, v10
; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX9-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, v7, v2
; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-GISEL-NEXT:    v_or_b32_e32 v2, v10, v2
; GFX9-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v1
; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v2, v6, v2, vcc
; GFX9-GISEL-NEXT:    v_and_b32_e32 v6, 7, v2
; GFX9-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v6
; GFX9-GISEL-NEXT:    v_cmp_lt_i32_e64 s[4:5], 5, v6
; GFX9-GISEL-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
; GFX9-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[4:5]
; GFX9-GISEL-NEXT:    v_add_u32_e32 v2, v2, v6
; GFX9-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, 30, v1
; GFX9-GISEL-NEXT:    v_lshl_or_b32 v5, v5, 9, v8
; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v2, v2, v8, vcc
; GFX9-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v9
; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v1, v2, v5, vcc
; GFX9-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
; GFX9-GISEL-NEXT:    v_and_or_b32 v1, v2, v4, v1
; GFX9-GISEL-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX9-GISEL-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX950-SDAG-LABEL: fptrunc_v2f64_to_v2f16:
; GFX950-SDAG:       ; %bb.0:
; GFX950-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-SDAG-NEXT:    s_movk_i32 s0, 0x1ff
; GFX950-SDAG-NEXT:    v_and_or_b32 v0, v1, s0, v0
; GFX950-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; GFX950-SDAG-NEXT:    v_lshrrev_b32_e32 v4, 8, v1
; GFX950-SDAG-NEXT:    s_movk_i32 s1, 0xffe
; GFX950-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX950-SDAG-NEXT:    v_bfe_u32 v5, v1, 20, 11
; GFX950-SDAG-NEXT:    v_and_or_b32 v0, v4, s1, v0
; GFX950-SDAG-NEXT:    v_sub_u32_e32 v6, 0x3f1, v5
; GFX950-SDAG-NEXT:    v_or_b32_e32 v4, 0x1000, v0
; GFX950-SDAG-NEXT:    v_med3_i32 v6, v6, 0, 13
; GFX950-SDAG-NEXT:    v_lshrrev_b32_e32 v7, v6, v4
; GFX950-SDAG-NEXT:    v_lshlrev_b32_e32 v6, v6, v7
; GFX950-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, v6, v4
; GFX950-SDAG-NEXT:    v_add_u32_e32 v5, 0xfffffc10, v5
; GFX950-SDAG-NEXT:    v_lshl_or_b32 v6, v5, 12, v0
; GFX950-SDAG-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX950-SDAG-NEXT:    v_or_b32_e32 v4, v7, v4
; GFX950-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v5
; GFX950-SDAG-NEXT:    s_movk_i32 s2, 0x40f
; GFX950-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
; GFX950-SDAG-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc
; GFX950-SDAG-NEXT:    v_and_b32_e32 v6, 7, v4
; GFX950-SDAG-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v6
; GFX950-SDAG-NEXT:    v_lshrrev_b32_e32 v4, 2, v4
; GFX950-SDAG-NEXT:    s_mov_b32 s3, 0x8000
; GFX950-SDAG-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX950-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v6
; GFX950-SDAG-NEXT:    s_nop 1
; GFX950-SDAG-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX950-SDAG-NEXT:    v_or_b32_e32 v6, v6, v7
; GFX950-SDAG-NEXT:    v_add_u32_e32 v4, v4, v6
; GFX950-SDAG-NEXT:    v_mov_b32_e32 v6, 0x7c00
; GFX950-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v5
; GFX950-SDAG-NEXT:    v_mov_b32_e32 v7, 0x7e00
; GFX950-SDAG-NEXT:    s_nop 0
; GFX950-SDAG-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc
; GFX950-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; GFX950-SDAG-NEXT:    s_nop 1
; GFX950-SDAG-NEXT:    v_cndmask_b32_e32 v0, v6, v7, vcc
; GFX950-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, s2, v5
; GFX950-SDAG-NEXT:    s_nop 1
; GFX950-SDAG-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX950-SDAG-NEXT:    v_and_or_b32 v0, v1, s3, v0
; GFX950-SDAG-NEXT:    v_and_or_b32 v1, v3, s0, v2
; GFX950-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
; GFX950-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 8, v3
; GFX950-SDAG-NEXT:    v_bfe_u32 v4, v3, 20, 11
; GFX950-SDAG-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX950-SDAG-NEXT:    v_and_or_b32 v1, v2, s1, v1
; GFX950-SDAG-NEXT:    v_sub_u32_e32 v5, 0x3f1, v4
; GFX950-SDAG-NEXT:    v_or_b32_e32 v2, 0x1000, v1
; GFX950-SDAG-NEXT:    v_med3_i32 v5, v5, 0, 13
; GFX950-SDAG-NEXT:    v_lshrrev_b32_e32 v8, v5, v2
; GFX950-SDAG-NEXT:    v_lshlrev_b32_e32 v5, v5, v8
; GFX950-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, v5, v2
; GFX950-SDAG-NEXT:    v_add_u32_e32 v4, 0xfffffc10, v4
; GFX950-SDAG-NEXT:    v_lshl_or_b32 v5, v4, 12, v1
; GFX950-SDAG-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX950-SDAG-NEXT:    v_or_b32_e32 v2, v8, v2
; GFX950-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v4
; GFX950-SDAG-NEXT:    s_mov_b32 s0, 0x5040100
; GFX950-SDAG-NEXT:    s_nop 0
; GFX950-SDAG-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
; GFX950-SDAG-NEXT:    v_and_b32_e32 v5, 7, v2
; GFX950-SDAG-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v5
; GFX950-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
; GFX950-SDAG-NEXT:    s_nop 0
; GFX950-SDAG-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX950-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v5
; GFX950-SDAG-NEXT:    s_nop 1
; GFX950-SDAG-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX950-SDAG-NEXT:    v_or_b32_e32 v5, v5, v8
; GFX950-SDAG-NEXT:    v_add_u32_e32 v2, v2, v5
; GFX950-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v4
; GFX950-SDAG-NEXT:    s_nop 1
; GFX950-SDAG-NEXT:    v_cndmask_b32_e32 v2, v6, v2, vcc
; GFX950-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
; GFX950-SDAG-NEXT:    s_nop 1
; GFX950-SDAG-NEXT:    v_cndmask_b32_e32 v1, v6, v7, vcc
; GFX950-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, s2, v4
; GFX950-SDAG-NEXT:    s_nop 1
; GFX950-SDAG-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX950-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
; GFX950-SDAG-NEXT:    v_and_or_b32 v1, v2, s3, v1
; GFX950-SDAG-NEXT:    v_perm_b32 v0, v1, v0, s0
; GFX950-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX950-GISEL-LABEL: fptrunc_v2f64_to_v2f16:
; GFX950-GISEL:       ; %bb.0:
; GFX950-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-GISEL-NEXT:    v_mov_b32_e32 v7, 0x1ff
; GFX950-GISEL-NEXT:    v_and_or_b32 v0, v1, v7, v0
; GFX950-GISEL-NEXT:    v_bfe_u32 v4, v1, 20, 11
; GFX950-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; GFX950-GISEL-NEXT:    v_add_u32_e32 v4, 0xfffffc10, v4
; GFX950-GISEL-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
; GFX950-GISEL-NEXT:    v_mov_b32_e32 v6, 0xffe
; GFX950-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX950-GISEL-NEXT:    v_and_or_b32 v0, v5, v6, v0
; GFX950-GISEL-NEXT:    v_sub_u32_e32 v10, 1, v4
; GFX950-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; GFX950-GISEL-NEXT:    v_lshl_or_b32 v9, v4, 12, v0
; GFX950-GISEL-NEXT:    v_med3_i32 v10, v10, 0, 13
; GFX950-GISEL-NEXT:    v_or_b32_e32 v0, 0x1000, v0
; GFX950-GISEL-NEXT:    v_lshrrev_b32_e32 v11, v10, v0
; GFX950-GISEL-NEXT:    v_lshlrev_b32_e32 v10, v10, v11
; GFX950-GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX950-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, v10, v0
; GFX950-GISEL-NEXT:    v_mov_b32_e32 v8, 0x7c00
; GFX950-GISEL-NEXT:    v_lshl_or_b32 v5, v5, 9, v8
; GFX950-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX950-GISEL-NEXT:    v_or_b32_e32 v0, v11, v0
; GFX950-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v4
; GFX950-GISEL-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
; GFX950-GISEL-NEXT:    v_and_or_b32 v2, v3, v7, v2
; GFX950-GISEL-NEXT:    v_cndmask_b32_e32 v0, v9, v0, vcc
; GFX950-GISEL-NEXT:    v_and_b32_e32 v9, 7, v0
; GFX950-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v9
; GFX950-GISEL-NEXT:    v_cmp_lt_i32_e64 s[0:1], 5, v9
; GFX950-GISEL-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]
; GFX950-GISEL-NEXT:    v_lshrrev_b32_e32 v0, 2, v0
; GFX950-GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[0:1]
; GFX950-GISEL-NEXT:    v_add_u32_e32 v0, v0, v9
; GFX950-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, 30, v4
; GFX950-GISEL-NEXT:    v_mov_b32_e32 v9, 0x40f
; GFX950-GISEL-NEXT:    s_nop 0
; GFX950-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc
; GFX950-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v4, v9
; GFX950-GISEL-NEXT:    v_mov_b32_e32 v4, 0x8000
; GFX950-GISEL-NEXT:    s_nop 0
; GFX950-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
; GFX950-GISEL-NEXT:    v_and_or_b32 v0, v1, v4, v0
; GFX950-GISEL-NEXT:    v_bfe_u32 v1, v3, 20, 11
; GFX950-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
; GFX950-GISEL-NEXT:    v_add_u32_e32 v1, 0xfffffc10, v1
; GFX950-GISEL-NEXT:    v_lshrrev_b32_e32 v5, 8, v3
; GFX950-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX950-GISEL-NEXT:    v_and_or_b32 v2, v5, v6, v2
; GFX950-GISEL-NEXT:    v_sub_u32_e32 v7, 1, v1
; GFX950-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
; GFX950-GISEL-NEXT:    v_lshl_or_b32 v6, v1, 12, v2
; GFX950-GISEL-NEXT:    v_med3_i32 v7, v7, 0, 13
; GFX950-GISEL-NEXT:    v_or_b32_e32 v2, 0x1000, v2
; GFX950-GISEL-NEXT:    v_lshrrev_b32_e32 v10, v7, v2
; GFX950-GISEL-NEXT:    v_lshlrev_b32_e32 v7, v7, v10
; GFX950-GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX950-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, v7, v2
; GFX950-GISEL-NEXT:    v_lshl_or_b32 v5, v5, 9, v8
; GFX950-GISEL-NEXT:    s_nop 0
; GFX950-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX950-GISEL-NEXT:    v_or_b32_e32 v2, v10, v2
; GFX950-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v1
; GFX950-GISEL-NEXT:    s_nop 1
; GFX950-GISEL-NEXT:    v_cndmask_b32_e32 v2, v6, v2, vcc
; GFX950-GISEL-NEXT:    v_and_b32_e32 v6, 7, v2
; GFX950-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v6
; GFX950-GISEL-NEXT:    v_cmp_lt_i32_e64 s[0:1], 5, v6
; GFX950-GISEL-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]
; GFX950-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
; GFX950-GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[0:1]
; GFX950-GISEL-NEXT:    v_add_u32_e32 v2, v2, v6
; GFX950-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, 30, v1
; GFX950-GISEL-NEXT:    s_nop 1
; GFX950-GISEL-NEXT:    v_cndmask_b32_e32 v2, v2, v8, vcc
; GFX950-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v9
; GFX950-GISEL-NEXT:    s_nop 1
; GFX950-GISEL-NEXT:    v_cndmask_b32_e32 v1, v2, v5, vcc
; GFX950-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
; GFX950-GISEL-NEXT:    v_and_or_b32 v1, v2, v4, v1
; GFX950-GISEL-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX950-GISEL-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX950-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: fptrunc_v2f64_to_v2f16:
; GFX11-SDAG-TRUE16:       ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT:    v_and_or_b32 v2, v3, 0x1ff, v2
; GFX11-SDAG-TRUE16-NEXT:    v_and_or_b32 v0, v1, 0x1ff, v0
; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v4, 8, v3
; GFX11-SDAG-TRUE16-NEXT:    v_bfe_u32 v5, v3, 20, 11
; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v6, 8, v1
; GFX11-SDAG-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX11-SDAG-TRUE16-NEXT:    v_bfe_u32 v7, v1, 20, 11
; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
; GFX11-SDAG-TRUE16-NEXT:    v_sub_nc_u32_e32 v8, 0x3f1, v5
; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX11-SDAG-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT:    v_and_or_b32 v2, v4, 0xffe, v2
; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-SDAG-TRUE16-NEXT:    v_sub_nc_u32_e32 v4, 0x3f1, v7
; GFX11-SDAG-TRUE16-NEXT:    v_and_or_b32 v0, v6, 0xffe, v0
; GFX11-SDAG-TRUE16-NEXT:    v_med3_i32 v6, v8, 0, 13
; GFX11-SDAG-TRUE16-NEXT:    v_or_b32_e32 v8, 0x1000, v2
; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-SDAG-TRUE16-NEXT:    v_med3_i32 v4, v4, 0, 13
; GFX11-SDAG-TRUE16-NEXT:    v_or_b32_e32 v9, 0x1000, v0
; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v10, v6, v8
; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v11, v4, v9
; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, v6, v10
; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, v4, v11
; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-SDAG-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v6, v8
; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX11-SDAG-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v4, v9
; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT:    v_or_b32_e32 v6, v10, v6
; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u32_e32 v5, 0xfffffc10, v5
; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
; GFX11-SDAG-TRUE16-NEXT:    v_lshl_or_b32 v8, v5, 12, v2
; GFX11-SDAG-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v5
; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-SDAG-TRUE16-NEXT:    v_or_b32_e32 v4, v11, v4
; GFX11-SDAG-TRUE16-NEXT:    v_dual_cndmask_b32 v6, v8, v6 :: v_dual_add_nc_u32 v7, 0xfffffc10, v7
; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-SDAG-TRUE16-NEXT:    v_lshl_or_b32 v9, v7, 12, v0
; GFX11-SDAG-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v7
; GFX11-SDAG-TRUE16-NEXT:    v_and_b32_e32 v8, 7, v6
; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v6, 2, v6
; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v9, v4, vcc_lo
; GFX11-SDAG-TRUE16-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 5, v8
; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT:    v_and_b32_e32 v9, 7, v4
; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v4, 2, v4
; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc_lo
; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v8
; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX11-SDAG-TRUE16-NEXT:    v_or_b32_e32 v8, v8, v10
; GFX11-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v10, 0x7e00
; GFX11-SDAG-TRUE16-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 5, v9
; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u32_e32 v6, v6, v8
; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc_lo
; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v9
; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc_lo
; GFX11-SDAG-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX11-SDAG-TRUE16-NEXT:    v_or_b32_e32 v9, v9, v11
; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v2, 0x7c00, v10, vcc_lo
; GFX11-SDAG-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 31, v5
; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u32_e32 v4, v4, v9
; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v6, 0x7c00, v6, vcc_lo
; GFX11-SDAG-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v0, 0x7c00, v10, vcc_lo
; GFX11-SDAG-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 31, v7
; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v4, 0x7c00, v4, vcc_lo
; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v5
; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v6, v2, vcc_lo
; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v7
; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT:    v_and_or_b32 v2, v3, 0x8000, v2
; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX11-SDAG-TRUE16-NEXT:    v_and_or_b32 v0, v1, 0x8000, v0
; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v2.l
; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: fptrunc_v2f64_to_v2f16:
; GFX11-SDAG-FAKE16:       ; %bb.0:
; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT:    v_and_or_b32 v0, v1, 0x1ff, v0
; GFX11-SDAG-FAKE16-NEXT:    v_and_or_b32 v2, v3, 0x1ff, v2
; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 8, v1
; GFX11-SDAG-FAKE16-NEXT:    v_bfe_u32 v5, v1, 20, 11
; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 8, v3
; GFX11-SDAG-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-SDAG-FAKE16-NEXT:    v_bfe_u32 v7, v3, 20, 11
; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
; GFX11-SDAG-FAKE16-NEXT:    v_sub_nc_u32_e32 v8, 0x3f1, v5
; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-SDAG-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v12, 0x7e00
; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT:    v_and_or_b32 v0, v4, 0xffe, v0
; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX11-SDAG-FAKE16-NEXT:    v_sub_nc_u32_e32 v4, 0x3f1, v7
; GFX11-SDAG-FAKE16-NEXT:    v_and_or_b32 v2, v6, 0xffe, v2
; GFX11-SDAG-FAKE16-NEXT:    v_med3_i32 v6, v8, 0, 13
; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v8, 0x1000, v0
; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-SDAG-FAKE16-NEXT:    v_med3_i32 v4, v4, 0, 13
; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v9, 0x1000, v2
; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, v6, v8
; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v11, v4, v9
; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, v6, v10
; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, v4, v11
; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-SDAG-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v6, v8
; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX11-SDAG-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v4, v9
; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v6, v10, v6
; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u32_e32 v5, 0xfffffc10, v5
; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
; GFX11-SDAG-FAKE16-NEXT:    v_lshl_or_b32 v8, v5, 12, v0
; GFX11-SDAG-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v5
; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v4, v11, v4
; GFX11-SDAG-FAKE16-NEXT:    v_dual_cndmask_b32 v6, v8, v6 :: v_dual_add_nc_u32 v7, 0xfffffc10, v7
; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-SDAG-FAKE16-NEXT:    v_lshl_or_b32 v9, v7, 12, v2
; GFX11-SDAG-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v7
; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v8, 7, v6
; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 2, v6
; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v9, v4, vcc_lo
; GFX11-SDAG-FAKE16-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 5, v8
; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v9, 7, v4
; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 2, v4
; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc_lo
; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v8
; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX11-SDAG-FAKE16-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 5, v9
; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v10
; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc_lo
; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v9
; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u32_e32 v6, v6, v8
; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc_lo
; GFX11-SDAG-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v11
; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7c00, v12, vcc_lo
; GFX11-SDAG-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u32_e32 v4, v4, v9
; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v2, 0x7c00, v12, vcc_lo
; GFX11-SDAG-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 31, v5
; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v6, 0x7c00, v6, vcc_lo
; GFX11-SDAG-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 31, v7
; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v4, 0x7c00, v4, vcc_lo
; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v5
; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc_lo
; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v7
; GFX11-SDAG-FAKE16-NEXT:    v_and_or_b32 v0, v1, 0x8000, v0
; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc_lo
; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT:    v_and_or_b32 v1, v3, 0x8000, v2
; GFX11-SDAG-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-GISEL-TRUE16-LABEL: fptrunc_v2f64_to_v2f16:
; GFX11-GISEL-TRUE16:       ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT:    v_and_or_b32 v2, v3, 0x1ff, v2
; GFX11-GISEL-TRUE16-NEXT:    v_bfe_u32 v5, v3, 20, 11
; GFX11-GISEL-TRUE16-NEXT:    v_and_or_b32 v0, v1, 0x1ff, v0
; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v6, 8, v3
; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 8, v1
; GFX11-GISEL-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX11-GISEL-TRUE16-NEXT:    v_add_nc_u32_e32 v5, 0xfffffc10, v5
; GFX11-GISEL-TRUE16-NEXT:    v_bfe_u32 v4, v1, 20, 11
; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX11-GISEL-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-GISEL-TRUE16-NEXT:    v_sub_nc_u32_e32 v8, 1, v5
; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT:    v_and_or_b32 v2, v6, 0xffe, v2
; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-GISEL-TRUE16-NEXT:    v_and_or_b32 v0, v7, 0xffe, v0
; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-GISEL-TRUE16-NEXT:    v_med3_i32 v7, v8, 0, 13
; GFX11-GISEL-TRUE16-NEXT:    v_or_b32_e32 v8, 0x1000, v2
; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-TRUE16-NEXT:    v_or_b32_e32 v9, 0x1000, v0
; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v10, v7, v8
; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, v7, v10
; GFX11-GISEL-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v7, v8
; GFX11-GISEL-TRUE16-NEXT:    v_lshl_or_b32 v8, v5, 12, v2
; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT:    v_or_b32_e32 v7, v10, v7
; GFX11-GISEL-TRUE16-NEXT:    v_add_nc_u32_e32 v4, 0xfffffc10, v4
; GFX11-GISEL-TRUE16-NEXT:    v_sub_nc_u32_e32 v6, 1, v4
; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT:    v_med3_i32 v6, v6, 0, 13
; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v11, v6, v9
; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, v6, v11
; GFX11-GISEL-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v6, v9
; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX11-GISEL-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v5
; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-GISEL-TRUE16-NEXT:    v_or_b32_e32 v6, v11, v6
; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e32 v7, v8, v7, vcc_lo
; GFX11-GISEL-TRUE16-NEXT:    v_lshl_or_b32 v9, v4, 12, v0
; GFX11-GISEL-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v4
; GFX11-GISEL-TRUE16-NEXT:    v_and_b32_e32 v8, 7, v7
; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 2, v7
; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v9, v6, vcc_lo
; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v8
; GFX11-GISEL-TRUE16-NEXT:    v_cmp_lt_i32_e64 s0, 5, v8
; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-GISEL-TRUE16-NEXT:    v_and_b32_e32 v9, 7, v6
; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v6, 2, v6
; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s0, vcc_lo, s0
; GFX11-GISEL-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e64 s1, 3, v9
; GFX11-GISEL-TRUE16-NEXT:    v_cmp_lt_i32_e64 s2, 5, v9
; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s0
; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX11-GISEL-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s0, s1, s2
; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-GISEL-TRUE16-NEXT:    v_add_nc_u32_e32 v7, v7, v8
; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s0
; GFX11-GISEL-TRUE16-NEXT:    v_lshl_or_b32 v2, v2, 9, 0x7c00
; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-GISEL-TRUE16-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 30, v5
; GFX11-GISEL-TRUE16-NEXT:    v_add_nc_u32_e32 v6, v6, v9
; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-GISEL-TRUE16-NEXT:    v_lshl_or_b32 v0, v0, 9, 0x7c00
; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v7, v7, 0x7c00, vcc_lo
; GFX11-GISEL-TRUE16-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 30, v4
; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v6, v6, 0x7c00, vcc_lo
; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v5
; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v7, v2, vcc_lo
; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v4
; GFX11-GISEL-TRUE16-NEXT:    v_and_or_b32 v2, v3, 0x8000, v2
; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc_lo
; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-GISEL-TRUE16-NEXT:    v_and_or_b32 v0, v1, 0x8000, v0
; GFX11-GISEL-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v2.l
; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: fptrunc_v2f64_to_v2f16:
; GFX11-GISEL-FAKE16:       ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT:    v_and_or_b32 v0, v1, 0x1ff, v0
; GFX11-GISEL-FAKE16-NEXT:    v_bfe_u32 v4, v1, 20, 11
; GFX11-GISEL-FAKE16-NEXT:    v_and_or_b32 v2, v3, 0x1ff, v2
; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
; GFX11-GISEL-FAKE16-NEXT:    v_bfe_u32 v6, v3, 20, 11
; GFX11-GISEL-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-GISEL-FAKE16-NEXT:    v_add_nc_u32_e32 v4, 0xfffffc10, v4
; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 8, v3
; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
; GFX11-GISEL-FAKE16-NEXT:    v_add_nc_u32_e32 v6, 0xfffffc10, v6
; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-GISEL-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX11-GISEL-FAKE16-NEXT:    v_sub_nc_u32_e32 v8, 1, v4
; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-GISEL-FAKE16-NEXT:    v_and_or_b32 v0, v5, 0xffe, v0
; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX11-GISEL-FAKE16-NEXT:    v_sub_nc_u32_e32 v5, 1, v6
; GFX11-GISEL-FAKE16-NEXT:    v_and_or_b32 v2, v7, 0xffe, v2
; GFX11-GISEL-FAKE16-NEXT:    v_med3_i32 v7, v8, 0, 13
; GFX11-GISEL-FAKE16-NEXT:    v_or_b32_e32 v8, 0x1000, v0
; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-GISEL-FAKE16-NEXT:    v_med3_i32 v5, v5, 0, 13
; GFX11-GISEL-FAKE16-NEXT:    v_or_b32_e32 v9, 0x1000, v2
; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, v7, v8
; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v11, v5, v9
; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, v7, v10
; GFX11-GISEL-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, v5, v11
; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-GISEL-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v7, v8
; GFX11-GISEL-FAKE16-NEXT:    v_lshl_or_b32 v8, v4, 12, v0
; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; GFX11-GISEL-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v5, v9
; GFX11-GISEL-FAKE16-NEXT:    v_lshl_or_b32 v9, v6, 12, v2
; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-GISEL-FAKE16-NEXT:    v_or_b32_e32 v7, v10, v7
; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX11-GISEL-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v4
; GFX11-GISEL-FAKE16-NEXT:    v_or_b32_e32 v5, v11, v5
; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v8, v7, vcc_lo
; GFX11-GISEL-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v6
; GFX11-GISEL-FAKE16-NEXT:    v_and_b32_e32 v8, 7, v7
; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v9, v5, vcc_lo
; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 2, v7
; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v8
; GFX11-GISEL-FAKE16-NEXT:    v_cmp_lt_i32_e64 s0, 5, v8
; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s0, vcc_lo, s0
; GFX11-GISEL-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s0
; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-GISEL-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-GISEL-FAKE16-NEXT:    v_add_nc_u32_e32 v7, v7, v8
; GFX11-GISEL-FAKE16-NEXT:    v_lshl_or_b32 v0, v0, 9, 0x7c00
; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX11-GISEL-FAKE16-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 30, v4
; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-GISEL-FAKE16-NEXT:    v_lshl_or_b32 v2, v2, 9, 0x7c00
; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v7, v7, 0x7c00, vcc_lo
; GFX11-GISEL-FAKE16-NEXT:    v_and_b32_e32 v9, 7, v5
; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 2, v5
; GFX11-GISEL-FAKE16-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 30, v6
; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e64 s1, 3, v9
; GFX11-GISEL-FAKE16-NEXT:    v_cmp_lt_i32_e64 s2, 5, v9
; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s0, s1, s2
; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s0
; GFX11-GISEL-FAKE16-NEXT:    v_add_nc_u32_e32 v5, v5, v9
; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v5, v5, 0x7c00, vcc_lo
; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v4
; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc_lo
; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v6
; GFX11-GISEL-FAKE16-NEXT:    v_and_or_b32 v0, v1, 0x8000, v0
; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc_lo
; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; GFX11-GISEL-FAKE16-NEXT:    v_and_or_b32 v1, v3, 0x8000, v2
; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1250-SDAG-TRUE16-LABEL: fptrunc_v2f64_to_v2f16:
; GFX1250-SDAG-TRUE16:       ; %bb.0:
; GFX1250-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-TRUE16-NEXT:    v_and_or_b32 v2, v3, 0x1ff, v2
; GFX1250-SDAG-TRUE16-NEXT:    v_and_or_b32 v0, v1, 0x1ff, v0
; GFX1250-SDAG-TRUE16-NEXT:    v_dual_lshrrev_b32 v4, 8, v3 :: v_dual_lshrrev_b32 v6, 8, v1
; GFX1250-SDAG-TRUE16-NEXT:    v_bfe_u32 v5, v3, 20, 11
; GFX1250-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX1250-SDAG-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX1250-SDAG-TRUE16-NEXT:    v_bfe_u32 v7, v1, 20, 11
; GFX1250-SDAG-TRUE16-NEXT:    v_dual_lshrrev_b32 v1, 16, v1 :: v_dual_lshrrev_b32 v3, 16, v3
; GFX1250-SDAG-TRUE16-NEXT:    v_sub_nc_u32_e32 v8, 0x3f1, v5
; GFX1250-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX1250-SDAG-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX1250-SDAG-TRUE16-NEXT:    v_add_nc_u32_e32 v5, 0xfffffc10, v5
; GFX1250-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX1250-SDAG-TRUE16-NEXT:    v_and_or_b32 v2, v4, 0xffe, v2
; GFX1250-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX1250-SDAG-TRUE16-NEXT:    v_sub_nc_u32_e32 v4, 0x3f1, v7
; GFX1250-SDAG-TRUE16-NEXT:    v_add_nc_u32_e32 v7, 0xfffffc10, v7
; GFX1250-SDAG-TRUE16-NEXT:    v_and_or_b32 v0, v6, 0xffe, v0
; GFX1250-SDAG-TRUE16-NEXT:    v_med3_i32 v6, v8, 0, 13
; GFX1250-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-SDAG-TRUE16-NEXT:    v_med3_i32 v4, v4, 0, 13
; GFX1250-SDAG-TRUE16-NEXT:    v_or_b32_e32 v9, 0x1000, v0
; GFX1250-SDAG-TRUE16-NEXT:    v_or_b32_e32 v8, 0x1000, v2
; GFX1250-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-TRUE16-NEXT:    v_dual_lshrrev_b32 v11, v4, v9 :: v_dual_lshrrev_b32 v10, v6, v8
; GFX1250-SDAG-TRUE16-NEXT:    v_dual_lshlrev_b32 v4, v4, v11 :: v_dual_lshlrev_b32 v6, v6, v10
; GFX1250-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX1250-SDAG-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v6, v8
; GFX1250-SDAG-TRUE16-NEXT:    v_lshl_or_b32 v8, v5, 12, v2
; GFX1250-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX1250-SDAG-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v4, v9
; GFX1250-SDAG-TRUE16-NEXT:    v_lshl_or_b32 v9, v7, 12, v0
; GFX1250-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
; GFX1250-SDAG-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v5
; GFX1250-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1250-SDAG-TRUE16-NEXT:    v_or_b32_e32 v4, v11, v4
; GFX1250-SDAG-TRUE16-NEXT:    v_or_b32_e32 v6, v10, v6
; GFX1250-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v8, v6, vcc_lo
; GFX1250-SDAG-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v7
; GFX1250-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-SDAG-TRUE16-NEXT:    v_dual_cndmask_b32 v4, v9, v4, vcc_lo :: v_dual_bitop2_b32 v8, 7, v6 bitop3:0x40
; GFX1250-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v6, 2, v6
; GFX1250-SDAG-TRUE16-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 5, v8
; GFX1250-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX1250-SDAG-TRUE16-NEXT:    v_and_b32_e32 v9, 7, v4
; GFX1250-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v4, 2, v4
; GFX1250-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc_lo
; GFX1250-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v8
; GFX1250-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX1250-SDAG-TRUE16-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 5, v9
; GFX1250-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1250-SDAG-TRUE16-NEXT:    v_or_b32_e32 v8, v8, v10
; GFX1250-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc_lo
; GFX1250-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v9
; GFX1250-SDAG-TRUE16-NEXT:    s_mov_b32 s0, 0x7e00
; GFX1250-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
; GFX1250-SDAG-TRUE16-NEXT:    v_dual_mov_b32 v10, s0 :: v_dual_add_nc_u32 v6, v6, v8
; GFX1250-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc_lo
; GFX1250-SDAG-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX1250-SDAG-TRUE16-NEXT:    s_mov_b32 s0, 0x7c00
; GFX1250-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
; GFX1250-SDAG-TRUE16-NEXT:    v_dual_cndmask_b32 v2, s0, v10, vcc_lo :: v_dual_bitop2_b32 v9, v9, v11 bitop3:0x54
; GFX1250-SDAG-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 31, v5
; GFX1250-SDAG-TRUE16-NEXT:    s_mov_b32 s0, 0x7c00
; GFX1250-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
; GFX1250-SDAG-TRUE16-NEXT:    v_dual_add_nc_u32 v4, v4, v9 :: v_dual_cndmask_b32 v6, s0, v6, vcc_lo
; GFX1250-SDAG-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX1250-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v0, 0x7c00, v10, vcc_lo
; GFX1250-SDAG-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 31, v7
; GFX1250-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX1250-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v4, 0x7c00, v4, vcc_lo
; GFX1250-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v5
; GFX1250-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v6, v2, vcc_lo
; GFX1250-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v7
; GFX1250-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX1250-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-SDAG-TRUE16-NEXT:    v_and_or_b32 v2, v3, 0x8000, v2
; GFX1250-SDAG-TRUE16-NEXT:    v_and_or_b32 v0, v1, 0x8000, v0
; GFX1250-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1250-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v2.l
; GFX1250-SDAG-TRUE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-SDAG-FAKE16-LABEL: fptrunc_v2f64_to_v2f16:
; GFX1250-SDAG-FAKE16:       ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-FAKE16-NEXT:    v_and_or_b32 v0, v1, 0x1ff, v0
; GFX1250-SDAG-FAKE16-NEXT:    v_and_or_b32 v2, v3, 0x1ff, v2
; GFX1250-SDAG-FAKE16-NEXT:    v_dual_lshrrev_b32 v4, 8, v1 :: v_dual_lshrrev_b32 v6, 8, v3
; GFX1250-SDAG-FAKE16-NEXT:    v_bfe_u32 v5, v1, 20, 11
; GFX1250-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX1250-SDAG-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX1250-SDAG-FAKE16-NEXT:    v_bfe_u32 v7, v3, 20, 11
; GFX1250-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v12, 0x7e00 :: v_dual_lshrrev_b32 v3, 16, v3
; GFX1250-SDAG-FAKE16-NEXT:    v_sub_nc_u32_e32 v8, 0x3f1, v5
; GFX1250-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX1250-SDAG-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX1250-SDAG-FAKE16-NEXT:    v_add_nc_u32_e32 v5, 0xfffffc10, v5
; GFX1250-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
; GFX1250-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX1250-SDAG-FAKE16-NEXT:    v_and_or_b32 v0, v4, 0xffe, v0
; GFX1250-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX1250-SDAG-FAKE16-NEXT:    v_sub_nc_u32_e32 v4, 0x3f1, v7
; GFX1250-SDAG-FAKE16-NEXT:    v_add_nc_u32_e32 v7, 0xfffffc10, v7
; GFX1250-SDAG-FAKE16-NEXT:    v_and_or_b32 v2, v6, 0xffe, v2
; GFX1250-SDAG-FAKE16-NEXT:    v_med3_i32 v6, v8, 0, 13
; GFX1250-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-SDAG-FAKE16-NEXT:    v_med3_i32 v4, v4, 0, 13
; GFX1250-SDAG-FAKE16-NEXT:    v_or_b32_e32 v9, 0x1000, v2
; GFX1250-SDAG-FAKE16-NEXT:    v_or_b32_e32 v8, 0x1000, v0
; GFX1250-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-FAKE16-NEXT:    v_dual_lshrrev_b32 v11, v4, v9 :: v_dual_lshrrev_b32 v10, v6, v8
; GFX1250-SDAG-FAKE16-NEXT:    v_dual_lshlrev_b32 v4, v4, v11 :: v_dual_lshlrev_b32 v6, v6, v10
; GFX1250-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX1250-SDAG-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v6, v8
; GFX1250-SDAG-FAKE16-NEXT:    v_lshl_or_b32 v8, v5, 12, v0
; GFX1250-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX1250-SDAG-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v4, v9
; GFX1250-SDAG-FAKE16-NEXT:    v_lshl_or_b32 v9, v7, 12, v2
; GFX1250-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
; GFX1250-SDAG-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v5
; GFX1250-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1250-SDAG-FAKE16-NEXT:    v_or_b32_e32 v4, v11, v4
; GFX1250-SDAG-FAKE16-NEXT:    v_or_b32_e32 v6, v10, v6
; GFX1250-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v8, v6, vcc_lo
; GFX1250-SDAG-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v7
; GFX1250-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-SDAG-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v9, v4, vcc_lo :: v_dual_bitop2_b32 v8, 7, v6 bitop3:0x40
; GFX1250-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 2, v6
; GFX1250-SDAG-FAKE16-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 5, v8
; GFX1250-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX1250-SDAG-FAKE16-NEXT:    v_and_b32_e32 v9, 7, v4
; GFX1250-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc_lo
; GFX1250-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v8
; GFX1250-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX1250-SDAG-FAKE16-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 5, v9
; GFX1250-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1250-SDAG-FAKE16-NEXT:    v_dual_lshrrev_b32 v4, 2, v4 :: v_dual_bitop2_b32 v8, v8, v10 bitop3:0x54
; GFX1250-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc_lo
; GFX1250-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v9
; GFX1250-SDAG-FAKE16-NEXT:    v_add_nc_u32_e32 v6, v6, v8
; GFX1250-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc_lo
; GFX1250-SDAG-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX1250-SDAG-FAKE16-NEXT:    s_mov_b32 s0, 0x7c00
; GFX1250-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
; GFX1250-SDAG-FAKE16-NEXT:    v_dual_cndmask_b32 v0, s0, v12, vcc_lo :: v_dual_bitop2_b32 v9, v9, v11 bitop3:0x54
; GFX1250-SDAG-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX1250-SDAG-FAKE16-NEXT:    s_mov_b32 s0, 0x7c00
; GFX1250-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
; GFX1250-SDAG-FAKE16-NEXT:    v_dual_add_nc_u32 v4, v4, v9 :: v_dual_cndmask_b32 v2, s0, v12, vcc_lo
; GFX1250-SDAG-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 31, v5
; GFX1250-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v6, 0x7c00, v6, vcc_lo
; GFX1250-SDAG-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 31, v7
; GFX1250-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1250-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v4, 0x7c00, v4, vcc_lo
; GFX1250-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v5
; GFX1250-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc_lo
; GFX1250-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v7
; GFX1250-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc_lo
; GFX1250-SDAG-FAKE16-NEXT:    v_and_or_b32 v0, v1, 0x8000, v0
; GFX1250-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-FAKE16-NEXT:    v_and_or_b32 v1, v3, 0x8000, v2
; GFX1250-SDAG-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
; GFX1250-SDAG-FAKE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-GISEL-TRUE16-LABEL: fptrunc_v2f64_to_v2f16:
; GFX1250-GISEL-TRUE16:       ; %bb.0:
; GFX1250-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT:    v_and_or_b32 v2, v3, 0x1ff, v2
; GFX1250-GISEL-TRUE16-NEXT:    v_and_or_b32 v0, v1, 0x1ff, v0
; GFX1250-GISEL-TRUE16-NEXT:    v_bfe_u32 v4, v1, 20, 11
; GFX1250-GISEL-TRUE16-NEXT:    v_bfe_u32 v5, v3, 20, 11
; GFX1250-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v6, 8, v3
; GFX1250-GISEL-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s0, 0xfffffc10
; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1250-GISEL-TRUE16-NEXT:    v_dual_lshrrev_b32 v3, 16, v3 :: v_dual_add_nc_u32 v4, s0, v4
; GFX1250-GISEL-TRUE16-NEXT:    v_add_nc_u32_e32 v5, 0xfffffc10, v5
; GFX1250-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX1250-GISEL-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX1250-GISEL-TRUE16-NEXT:    v_and_or_b32 v2, v6, 0xffe, v2
; GFX1250-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 8, v1
; GFX1250-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX1250-GISEL-TRUE16-NEXT:    v_dual_sub_nc_u32 v6, 1, v4 :: v_dual_lshrrev_b32 v1, 16, v1
; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1250-GISEL-TRUE16-NEXT:    v_and_or_b32 v0, v7, 0xffe, v0
; GFX1250-GISEL-TRUE16-NEXT:    v_sub_nc_u32_e32 v8, 1, v5
; GFX1250-GISEL-TRUE16-NEXT:    v_med3_i32 v6, v6, 0, 13
; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-GISEL-TRUE16-NEXT:    v_or_b32_e32 v9, 0x1000, v0
; GFX1250-GISEL-TRUE16-NEXT:    v_med3_i32 v7, v8, 0, 13
; GFX1250-GISEL-TRUE16-NEXT:    v_or_b32_e32 v8, 0x1000, v2
; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-GISEL-TRUE16-NEXT:    v_dual_lshrrev_b32 v11, v6, v9 :: v_dual_lshrrev_b32 v10, v7, v8
; GFX1250-GISEL-TRUE16-NEXT:    v_dual_lshlrev_b32 v6, v6, v11 :: v_dual_lshlrev_b32 v7, v7, v10
; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX1250-GISEL-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v7, v8
; GFX1250-GISEL-TRUE16-NEXT:    v_lshl_or_b32 v8, v5, 12, v2
; GFX1250-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; GFX1250-GISEL-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v6, v9
; GFX1250-GISEL-TRUE16-NEXT:    v_lshl_or_b32 v9, v4, 12, v0
; GFX1250-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX1250-GISEL-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v5
; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1250-GISEL-TRUE16-NEXT:    v_or_b32_e32 v6, v11, v6
; GFX1250-GISEL-TRUE16-NEXT:    v_or_b32_e32 v7, v10, v7
; GFX1250-GISEL-TRUE16-NEXT:    v_cndmask_b32_e32 v7, v8, v7, vcc_lo
; GFX1250-GISEL-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v4
; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-GISEL-TRUE16-NEXT:    v_dual_cndmask_b32 v6, v9, v6, vcc_lo :: v_dual_bitop2_b32 v8, 7, v7 bitop3:0x40
; GFX1250-GISEL-TRUE16-NEXT:    v_dual_lshrrev_b32 v7, 2, v7 :: v_dual_bitop2_b32 v9, 7, v6 bitop3:0x40
; GFX1250-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v6, 2, v6
; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1250-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v8
; GFX1250-GISEL-TRUE16-NEXT:    v_cmp_lt_i32_e64 s0, 5, v8
; GFX1250-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e64 s1, 3, v9
; GFX1250-GISEL-TRUE16-NEXT:    v_cmp_lt_i32_e64 s2, 5, v9
; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s0, vcc_lo, s0
; GFX1250-GISEL-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX1250-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s0
; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s0, s1, s2
; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1250-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s0
; GFX1250-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX1250-GISEL-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX1250-GISEL-TRUE16-NEXT:    v_dual_add_nc_u32 v7, v7, v8 :: v_dual_add_nc_u32 v6, v6, v9
; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1250-GISEL-TRUE16-NEXT:    v_lshl_or_b32 v2, v2, 9, 0x7c00
; GFX1250-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX1250-GISEL-TRUE16-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 30, v5
; GFX1250-GISEL-TRUE16-NEXT:    v_lshl_or_b32 v0, v0, 9, 0x7c00
; GFX1250-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v7, v7, 0x7c00, vcc_lo
; GFX1250-GISEL-TRUE16-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 30, v4
; GFX1250-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v6, v6, 0x7c00, vcc_lo
; GFX1250-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v5
; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-GISEL-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v7, v2, vcc_lo
; GFX1250-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v4
; GFX1250-GISEL-TRUE16-NEXT:    v_and_or_b32 v2, v3, 0x8000, v2
; GFX1250-GISEL-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc_lo
; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-GISEL-TRUE16-NEXT:    v_and_or_b32 v0, v1, 0x8000, v0
; GFX1250-GISEL-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v2.l
; GFX1250-GISEL-TRUE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-GISEL-FAKE16-LABEL: fptrunc_v2f64_to_v2f16:
; GFX1250-GISEL-FAKE16:       ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT:    v_and_or_b32 v0, v1, 0x1ff, v0
; GFX1250-GISEL-FAKE16-NEXT:    v_and_or_b32 v2, v3, 0x1ff, v2
; GFX1250-GISEL-FAKE16-NEXT:    v_bfe_u32 v4, v1, 20, 11
; GFX1250-GISEL-FAKE16-NEXT:    v_bfe_u32 v6, v3, 20, 11
; GFX1250-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
; GFX1250-GISEL-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s0, 0xfffffc10
; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1250-GISEL-FAKE16-NEXT:    v_dual_lshrrev_b32 v7, 8, v3 :: v_dual_add_nc_u32 v4, s0, v4
; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s0, 0xfffffc10
; GFX1250-GISEL-FAKE16-NEXT:    v_dual_add_nc_u32 v6, s0, v6 :: v_dual_lshrrev_b32 v1, 16, v1
; GFX1250-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX1250-GISEL-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX1250-GISEL-FAKE16-NEXT:    v_dual_sub_nc_u32 v8, 1, v4 :: v_dual_lshrrev_b32 v3, 16, v3
; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1250-GISEL-FAKE16-NEXT:    v_and_or_b32 v0, v5, 0xffe, v0
; GFX1250-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX1250-GISEL-FAKE16-NEXT:    v_sub_nc_u32_e32 v5, 1, v6
; GFX1250-GISEL-FAKE16-NEXT:    v_and_or_b32 v2, v7, 0xffe, v2
; GFX1250-GISEL-FAKE16-NEXT:    v_med3_i32 v7, v8, 0, 13
; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-GISEL-FAKE16-NEXT:    v_med3_i32 v5, v5, 0, 13
; GFX1250-GISEL-FAKE16-NEXT:    v_or_b32_e32 v9, 0x1000, v2
; GFX1250-GISEL-FAKE16-NEXT:    v_or_b32_e32 v8, 0x1000, v0
; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-GISEL-FAKE16-NEXT:    v_dual_lshrrev_b32 v11, v5, v9 :: v_dual_lshrrev_b32 v10, v7, v8
; GFX1250-GISEL-FAKE16-NEXT:    v_dual_lshlrev_b32 v5, v5, v11 :: v_dual_lshlrev_b32 v7, v7, v10
; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX1250-GISEL-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v7, v8
; GFX1250-GISEL-FAKE16-NEXT:    v_lshl_or_b32 v8, v4, 12, v0
; GFX1250-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; GFX1250-GISEL-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v5, v9
; GFX1250-GISEL-FAKE16-NEXT:    v_lshl_or_b32 v9, v6, 12, v2
; GFX1250-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX1250-GISEL-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v4
; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1250-GISEL-FAKE16-NEXT:    v_or_b32_e32 v5, v11, v5
; GFX1250-GISEL-FAKE16-NEXT:    v_or_b32_e32 v7, v10, v7
; GFX1250-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v8, v7, vcc_lo
; GFX1250-GISEL-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v6
; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-GISEL-FAKE16-NEXT:    v_dual_cndmask_b32 v5, v9, v5, vcc_lo :: v_dual_bitop2_b32 v8, 7, v7 bitop3:0x40
; GFX1250-GISEL-FAKE16-NEXT:    v_dual_lshrrev_b32 v7, 2, v7 :: v_dual_bitop2_b32 v9, 7, v5 bitop3:0x40
; GFX1250-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 2, v5
; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1250-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v8
; GFX1250-GISEL-FAKE16-NEXT:    v_cmp_lt_i32_e64 s0, 5, v8
; GFX1250-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e64 s1, 3, v9
; GFX1250-GISEL-FAKE16-NEXT:    v_cmp_lt_i32_e64 s2, 5, v9
; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s0, vcc_lo, s0
; GFX1250-GISEL-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX1250-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s0
; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s0, s1, s2
; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1250-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s0
; GFX1250-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX1250-GISEL-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX1250-GISEL-FAKE16-NEXT:    v_dual_add_nc_u32 v7, v7, v8 :: v_dual_add_nc_u32 v5, v5, v9
; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1250-GISEL-FAKE16-NEXT:    v_lshl_or_b32 v0, v0, 9, 0x7c00
; GFX1250-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX1250-GISEL-FAKE16-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 30, v4
; GFX1250-GISEL-FAKE16-NEXT:    v_lshl_or_b32 v2, v2, 9, 0x7c00
; GFX1250-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v7, v7, 0x7c00, vcc_lo
; GFX1250-GISEL-FAKE16-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 30, v6
; GFX1250-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v5, v5, 0x7c00, vcc_lo
; GFX1250-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v4
; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc_lo
; GFX1250-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v6
; GFX1250-GISEL-FAKE16-NEXT:    v_and_or_b32 v0, v1, 0x8000, v0
; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s0, 0xffff
; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1250-GISEL-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v5, v2, vcc_lo :: v_dual_bitop2_b32 v0, s0, v0 bitop3:0x40
; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-GISEL-FAKE16-NEXT:    v_and_or_b32 v1, v3, 0x8000, v2
; GFX1250-GISEL-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
; GFX1250-GISEL-FAKE16-NEXT:    s_set_pc_i64 s[30:31]
  %r.val = fptrunc <2 x double> %a to <2 x half>
  ret <2 x half> %r.val
}

define <2 x half> @fptrunc_v2f64_to_v2f16_afn(<2 x double> %a) {
; SI-SDAG-LABEL: fptrunc_v2f64_to_v2f16_afn:
; SI-SDAG:       ; %bb.0:
; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-SDAG-NEXT:    v_cvt_f32_f64_e32 v2, v[2:3]
; SI-SDAG-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; SI-SDAG-NEXT:    v_cvt_f16_f32_e32 v1, v2
; SI-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-SDAG-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; SI-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; SI-GISEL-LABEL: fptrunc_v2f64_to_v2f16_afn:
; SI-GISEL:       ; %bb.0:
; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-GISEL-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; SI-GISEL-NEXT:    v_cvt_f32_f64_e32 v1, v[2:3]
; SI-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-GISEL-NEXT:    v_cvt_f16_f32_e32 v1, v1
; SI-GISEL-NEXT:    v_bfe_u32 v0, v0, 0, 16
; SI-GISEL-NEXT:    v_bfe_u32 v1, v1, 0, 16
; SI-GISEL-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; SI-GISEL-NEXT:    v_or_b32_e32 v0, v0, v1
; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: fptrunc_v2f64_to_v2f16_afn:
; VI-SDAG:       ; %bb.0:
; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-NEXT:    v_cvt_f32_f64_e32 v2, v[2:3]
; VI-SDAG-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; VI-SDAG-NEXT:    v_cvt_f16_f32_sdwa v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
; VI-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
; VI-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: fptrunc_v2f64_to_v2f16_afn:
; VI-GISEL:       ; %bb.0:
; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT:    v_cvt_f32_f64_e32 v2, v[2:3]
; VI-GISEL-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; VI-GISEL-NEXT:    v_cvt_f16_f32_e32 v1, v2
; VI-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 16
; VI-GISEL-NEXT:    v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-GISEL-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: fptrunc_v2f64_to_v2f16_afn:
; GFX9-SDAG:       ; %bb.0:
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT:    v_cvt_f32_f64_e32 v2, v[2:3]
; GFX9-SDAG-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; GFX9-SDAG-NEXT:    v_cvt_f16_f32_e32 v1, v2
; GFX9-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX9-SDAG-NEXT:    v_pack_b32_f16 v0, v0, v1
; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: fptrunc_v2f64_to_v2f16_afn:
; GFX9-GISEL:       ; %bb.0:
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; GFX9-GISEL-NEXT:    v_cvt_f32_f64_e32 v1, v[2:3]
; GFX9-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX9-GISEL-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX9-GISEL-NEXT:    v_pack_b32_f16 v0, v0, v1
; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX950-SDAG-LABEL: fptrunc_v2f64_to_v2f16_afn:
; GFX950-SDAG:       ; %bb.0:
; GFX950-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-SDAG-NEXT:    v_cvt_f32_f64_e32 v2, v[2:3]
; GFX950-SDAG-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; GFX950-SDAG-NEXT:    v_cvt_pk_f16_f32 v0, v0, v2
; GFX950-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX950-GISEL-LABEL: fptrunc_v2f64_to_v2f16_afn:
; GFX950-GISEL:       ; %bb.0:
; GFX950-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-GISEL-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; GFX950-GISEL-NEXT:    v_cvt_f32_f64_e32 v1, v[2:3]
; GFX950-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX950-GISEL-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX950-GISEL-NEXT:    v_pack_b32_f16 v0, v0, v1
; GFX950-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: fptrunc_v2f64_to_v2f16_afn:
; GFX11-SDAG-TRUE16:       ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT:    v_cvt_f32_f64_e32 v2, v[2:3]
; GFX11-SDAG-TRUE16-NEXT:    v_cvt_f32_f64_e32 v1, v[0:1]
; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.h, v2
; GFX11-SDAG-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v1
; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: fptrunc_v2f64_to_v2f16_afn:
; GFX11-SDAG-FAKE16:       ; %bb.0:
; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT:    v_cvt_f32_f64_e32 v2, v[2:3]
; GFX11-SDAG-FAKE16-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT:    v_cvt_f16_f32_e32 v1, v2
; GFX11-SDAG-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-GISEL-TRUE16-LABEL: fptrunc_v2f64_to_v2f16_afn:
; GFX11-GISEL-TRUE16:       ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; GFX11-GISEL-TRUE16-NEXT:    v_cvt_f32_f64_e32 v1, v[2:3]
; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
; GFX11-GISEL-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.h, v1
; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: fptrunc_v2f64_to_v2f16_afn:
; GFX11-GISEL-FAKE16:       ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; GFX11-GISEL-FAKE16-NEXT:    v_cvt_f32_f64_e32 v1, v[2:3]
; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX11-GISEL-FAKE16-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1250-SDAG-TRUE16-LABEL: fptrunc_v2f64_to_v2f16_afn:
; GFX1250-SDAG-TRUE16:       ; %bb.0:
; GFX1250-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-TRUE16-NEXT:    v_cvt_f32_f64_e32 v2, v[2:3]
; GFX1250-SDAG-TRUE16-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; GFX1250-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-TRUE16-NEXT:    v_cvt_pk_f16_f32 v0, v0, v2
; GFX1250-SDAG-TRUE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-SDAG-FAKE16-LABEL: fptrunc_v2f64_to_v2f16_afn:
; GFX1250-SDAG-FAKE16:       ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-FAKE16-NEXT:    v_cvt_f32_f64_e32 v2, v[2:3]
; GFX1250-SDAG-FAKE16-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; GFX1250-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-FAKE16-NEXT:    v_cvt_pk_f16_f32 v0, v0, v2
; GFX1250-SDAG-FAKE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-GISEL-TRUE16-LABEL: fptrunc_v2f64_to_v2f16_afn:
; GFX1250-GISEL-TRUE16:       ; %bb.0:
; GFX1250-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; GFX1250-GISEL-TRUE16-NEXT:    v_cvt_f32_f64_e32 v1, v[2:3]
; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-TRUE16-NEXT:    v_cvt_pk_f16_f32 v0, v0, v1
; GFX1250-GISEL-TRUE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-GISEL-FAKE16-LABEL: fptrunc_v2f64_to_v2f16_afn:
; GFX1250-GISEL-FAKE16:       ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_f32_f64_e32 v1, v[2:3]
; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
; GFX1250-GISEL-FAKE16-NEXT:    s_set_pc_i64 s[30:31]
  %r.val = fptrunc afn <2 x double> %a to <2 x half>
  ret <2 x half> %r.val
}

define half @fneg_fptrunc_f32_to_f16(float %a) {
; SI-SDAG-LABEL: fneg_fptrunc_f32_to_f16:
; SI-SDAG:       ; %bb.0:
; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-SDAG-NEXT:    v_cvt_f16_f32_e64 v0, -v0
; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; SI-GISEL-LABEL: fneg_fptrunc_f32_to_f16:
; SI-GISEL:       ; %bb.0:
; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-GISEL-NEXT:    v_cvt_f16_f32_e64 v0, -v0
; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: fneg_fptrunc_f32_to_f16:
; VI-SDAG:       ; %bb.0:
; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-NEXT:    v_cvt_f16_f32_e64 v0, -v0
; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: fneg_fptrunc_f32_to_f16:
; VI-GISEL:       ; %bb.0:
; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT:    v_cvt_f16_f32_e64 v0, -v0
; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: fneg_fptrunc_f32_to_f16:
; GFX9-SDAG:       ; %bb.0:
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT:    v_cvt_f16_f32_e64 v0, -v0
; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: fneg_fptrunc_f32_to_f16:
; GFX9-GISEL:       ; %bb.0:
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT:    v_cvt_f16_f32_e64 v0, -v0
; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX950-SDAG-LABEL: fneg_fptrunc_f32_to_f16:
; GFX950-SDAG:       ; %bb.0:
; GFX950-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-SDAG-NEXT:    v_cvt_f16_f32_e64 v0, -v0
; GFX950-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX950-GISEL-LABEL: fneg_fptrunc_f32_to_f16:
; GFX950-GISEL:       ; %bb.0:
; GFX950-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-GISEL-NEXT:    v_cvt_f16_f32_e64 v0, -v0
; GFX950-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: fneg_fptrunc_f32_to_f16:
; GFX11-SDAG-TRUE16:       ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT:    v_cvt_f16_f32_e64 v0.l, -v0
; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: fneg_fptrunc_f32_to_f16:
; GFX11-SDAG-FAKE16:       ; %bb.0:
; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT:    v_cvt_f16_f32_e64 v0, -v0
; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-GISEL-TRUE16-LABEL: fneg_fptrunc_f32_to_f16:
; GFX11-GISEL-TRUE16:       ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT:    v_cvt_f16_f32_e64 v0.l, -v0
; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: fneg_fptrunc_f32_to_f16:
; GFX11-GISEL-FAKE16:       ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT:    v_cvt_f16_f32_e64 v0, -v0
; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1250-SDAG-TRUE16-LABEL: fneg_fptrunc_f32_to_f16:
; GFX1250-SDAG-TRUE16:       ; %bb.0:
; GFX1250-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-TRUE16-NEXT:    v_cvt_f16_f32_e64 v0.l, -v0
; GFX1250-SDAG-TRUE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-SDAG-FAKE16-LABEL: fneg_fptrunc_f32_to_f16:
; GFX1250-SDAG-FAKE16:       ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-FAKE16-NEXT:    v_cvt_f16_f32_e64 v0, -v0
; GFX1250-SDAG-FAKE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-GISEL-TRUE16-LABEL: fneg_fptrunc_f32_to_f16:
; GFX1250-GISEL-TRUE16:       ; %bb.0:
; GFX1250-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT:    v_cvt_f16_f32_e64 v0.l, -v0
; GFX1250-GISEL-TRUE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-GISEL-FAKE16-LABEL: fneg_fptrunc_f32_to_f16:
; GFX1250-GISEL-FAKE16:       ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_f16_f32_e64 v0, -v0
; GFX1250-GISEL-FAKE16-NEXT:    s_set_pc_i64 s[30:31]
  %a.fneg = fneg float %a
  %r.val = fptrunc float %a.fneg to half
  ret half %r.val
}

define half @fabs_fptrunc_f32_to_f16(float %a) {
; SI-SDAG-LABEL: fabs_fptrunc_f32_to_f16:
; SI-SDAG:       ; %bb.0:
; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-SDAG-NEXT:    v_cvt_f16_f32_e64 v0, |v0|
; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; SI-GISEL-LABEL: fabs_fptrunc_f32_to_f16:
; SI-GISEL:       ; %bb.0:
; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-GISEL-NEXT:    v_cvt_f16_f32_e64 v0, |v0|
; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: fabs_fptrunc_f32_to_f16:
; VI-SDAG:       ; %bb.0:
; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-NEXT:    v_cvt_f16_f32_e64 v0, |v0|
; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: fabs_fptrunc_f32_to_f16:
; VI-GISEL:       ; %bb.0:
; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT:    v_cvt_f16_f32_e64 v0, |v0|
; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: fabs_fptrunc_f32_to_f16:
; GFX9-SDAG:       ; %bb.0:
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT:    v_cvt_f16_f32_e64 v0, |v0|
; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: fabs_fptrunc_f32_to_f16:
; GFX9-GISEL:       ; %bb.0:
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT:    v_cvt_f16_f32_e64 v0, |v0|
; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX950-SDAG-LABEL: fabs_fptrunc_f32_to_f16:
; GFX950-SDAG:       ; %bb.0:
; GFX950-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-SDAG-NEXT:    v_cvt_f16_f32_e64 v0, |v0|
; GFX950-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX950-GISEL-LABEL: fabs_fptrunc_f32_to_f16:
; GFX950-GISEL:       ; %bb.0:
; GFX950-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-GISEL-NEXT:    v_cvt_f16_f32_e64 v0, |v0|
; GFX950-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: fabs_fptrunc_f32_to_f16:
; GFX11-SDAG-TRUE16:       ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT:    v_cvt_f16_f32_e64 v0.l, |v0|
; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: fabs_fptrunc_f32_to_f16:
; GFX11-SDAG-FAKE16:       ; %bb.0:
; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT:    v_cvt_f16_f32_e64 v0, |v0|
; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-GISEL-TRUE16-LABEL: fabs_fptrunc_f32_to_f16:
; GFX11-GISEL-TRUE16:       ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT:    v_cvt_f16_f32_e64 v0.l, |v0|
; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: fabs_fptrunc_f32_to_f16:
; GFX11-GISEL-FAKE16:       ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT:    v_cvt_f16_f32_e64 v0, |v0|
; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1250-SDAG-TRUE16-LABEL: fabs_fptrunc_f32_to_f16:
; GFX1250-SDAG-TRUE16:       ; %bb.0:
; GFX1250-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-TRUE16-NEXT:    v_cvt_f16_f32_e64 v0.l, |v0|
; GFX1250-SDAG-TRUE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-SDAG-FAKE16-LABEL: fabs_fptrunc_f32_to_f16:
; GFX1250-SDAG-FAKE16:       ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-FAKE16-NEXT:    v_cvt_f16_f32_e64 v0, |v0|
; GFX1250-SDAG-FAKE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-GISEL-TRUE16-LABEL: fabs_fptrunc_f32_to_f16:
; GFX1250-GISEL-TRUE16:       ; %bb.0:
; GFX1250-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT:    v_cvt_f16_f32_e64 v0.l, |v0|
; GFX1250-GISEL-TRUE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-GISEL-FAKE16-LABEL: fabs_fptrunc_f32_to_f16:
; GFX1250-GISEL-FAKE16:       ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_f16_f32_e64 v0, |v0|
; GFX1250-GISEL-FAKE16-NEXT:    s_set_pc_i64 s[30:31]
  %a.fabs = call float @llvm.fabs.f32(float %a)
  %r.val = fptrunc float %a.fabs to half
  ret half %r.val
}

define half @fneg_fabs_fptrunc_f32_to_f16(float %a) #0 {
; SI-SDAG-LABEL: fneg_fabs_fptrunc_f32_to_f16:
; SI-SDAG:       ; %bb.0:
; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-SDAG-NEXT:    v_cvt_f16_f32_e64 v0, -|v0|
; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; SI-GISEL-LABEL: fneg_fabs_fptrunc_f32_to_f16:
; SI-GISEL:       ; %bb.0:
; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-GISEL-NEXT:    v_cvt_f16_f32_e64 v0, -|v0|
; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: fneg_fabs_fptrunc_f32_to_f16:
; VI-SDAG:       ; %bb.0:
; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-NEXT:    v_cvt_f16_f32_e64 v0, -|v0|
; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: fneg_fabs_fptrunc_f32_to_f16:
; VI-GISEL:       ; %bb.0:
; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT:    v_cvt_f16_f32_e64 v0, -|v0|
; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: fneg_fabs_fptrunc_f32_to_f16:
; GFX9-SDAG:       ; %bb.0:
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT:    v_cvt_f16_f32_e64 v0, -|v0|
; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: fneg_fabs_fptrunc_f32_to_f16:
; GFX9-GISEL:       ; %bb.0:
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT:    v_cvt_f16_f32_e64 v0, -|v0|
; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX950-SDAG-LABEL: fneg_fabs_fptrunc_f32_to_f16:
; GFX950-SDAG:       ; %bb.0:
; GFX950-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-SDAG-NEXT:    v_cvt_f16_f32_e64 v0, -|v0|
; GFX950-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX950-GISEL-LABEL: fneg_fabs_fptrunc_f32_to_f16:
; GFX950-GISEL:       ; %bb.0:
; GFX950-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-GISEL-NEXT:    v_cvt_f16_f32_e64 v0, -|v0|
; GFX950-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: fneg_fabs_fptrunc_f32_to_f16:
; GFX11-SDAG-TRUE16:       ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT:    v_cvt_f16_f32_e64 v0.l, -|v0|
; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: fneg_fabs_fptrunc_f32_to_f16:
; GFX11-SDAG-FAKE16:       ; %bb.0:
; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT:    v_cvt_f16_f32_e64 v0, -|v0|
; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-GISEL-TRUE16-LABEL: fneg_fabs_fptrunc_f32_to_f16:
; GFX11-GISEL-TRUE16:       ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT:    v_cvt_f16_f32_e64 v0.l, -|v0|
; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: fneg_fabs_fptrunc_f32_to_f16:
; GFX11-GISEL-FAKE16:       ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT:    v_cvt_f16_f32_e64 v0, -|v0|
; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1250-SDAG-TRUE16-LABEL: fneg_fabs_fptrunc_f32_to_f16:
; GFX1250-SDAG-TRUE16:       ; %bb.0:
; GFX1250-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-TRUE16-NEXT:    v_cvt_f16_f32_e64 v0.l, -|v0|
; GFX1250-SDAG-TRUE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-SDAG-FAKE16-LABEL: fneg_fabs_fptrunc_f32_to_f16:
; GFX1250-SDAG-FAKE16:       ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-FAKE16-NEXT:    v_cvt_f16_f32_e64 v0, -|v0|
; GFX1250-SDAG-FAKE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-GISEL-TRUE16-LABEL: fneg_fabs_fptrunc_f32_to_f16:
; GFX1250-GISEL-TRUE16:       ; %bb.0:
; GFX1250-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT:    v_cvt_f16_f32_e64 v0.l, -|v0|
; GFX1250-GISEL-TRUE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-GISEL-FAKE16-LABEL: fneg_fabs_fptrunc_f32_to_f16:
; GFX1250-GISEL-FAKE16:       ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_f16_f32_e64 v0, -|v0|
; GFX1250-GISEL-FAKE16-NEXT:    s_set_pc_i64 s[30:31]
  %a.fabs = call float @llvm.fabs.f32(float %a)
  %a.fneg.fabs = fneg float %a.fabs
  %r.val = fptrunc float %a.fneg.fabs to half
  ret half %r.val
}

define i32 @fptrunc_f32_to_f16_zext_i32(float %a) #0 {
; SI-SDAG-LABEL: fptrunc_f32_to_f16_zext_i32:
; SI-SDAG:       ; %bb.0:
; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; SI-GISEL-LABEL: fptrunc_f32_to_f16_zext_i32:
; SI-GISEL:       ; %bb.0:
; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: fptrunc_f32_to_f16_zext_i32:
; VI-SDAG:       ; %bb.0:
; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: fptrunc_f32_to_f16_zext_i32:
; VI-GISEL:       ; %bb.0:
; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: fptrunc_f32_to_f16_zext_i32:
; GFX9-SDAG:       ; %bb.0:
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: fptrunc_f32_to_f16_zext_i32:
; GFX9-GISEL:       ; %bb.0:
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX950-SDAG-LABEL: fptrunc_f32_to_f16_zext_i32:
; GFX950-SDAG:       ; %bb.0:
; GFX950-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX950-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX950-GISEL-LABEL: fptrunc_f32_to_f16_zext_i32:
; GFX950-GISEL:       ; %bb.0:
; GFX950-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX950-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: fptrunc_f32_to_f16_zext_i32:
; GFX11-SDAG-TRUE16:       ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT:    v_cvt_u32_u16_e32 v0, v0.l
; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: fptrunc_f32_to_f16_zext_i32:
; GFX11-SDAG-FAKE16:       ; %bb.0:
; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-GISEL-TRUE16-LABEL: fptrunc_f32_to_f16_zext_i32:
; GFX11-GISEL-TRUE16:       ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT:    v_cvt_u32_u16_e32 v0, v0.l
; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: fptrunc_f32_to_f16_zext_i32:
; GFX11-GISEL-FAKE16:       ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1250-SDAG-TRUE16-LABEL: fptrunc_f32_to_f16_zext_i32:
; GFX1250-SDAG-TRUE16:       ; %bb.0:
; GFX1250-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
; GFX1250-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-TRUE16-NEXT:    v_cvt_u32_u16_e32 v0, v0.l
; GFX1250-SDAG-TRUE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-SDAG-FAKE16-LABEL: fptrunc_f32_to_f16_zext_i32:
; GFX1250-SDAG-FAKE16:       ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX1250-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; GFX1250-SDAG-FAKE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-GISEL-TRUE16-LABEL: fptrunc_f32_to_f16_zext_i32:
; GFX1250-GISEL-TRUE16:       ; %bb.0:
; GFX1250-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-TRUE16-NEXT:    v_cvt_u32_u16_e32 v0, v0.l
; GFX1250-GISEL-TRUE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-GISEL-FAKE16-LABEL: fptrunc_f32_to_f16_zext_i32:
; GFX1250-GISEL-FAKE16:       ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; GFX1250-GISEL-FAKE16-NEXT:    s_set_pc_i64 s[30:31]
  %r.val = fptrunc float %a to half
  %r.i16 = bitcast half %r.val to i16
  %zext = zext i16 %r.i16 to i32
  ret i32 %zext
}

define i32 @fptrunc_fabs_f32_to_f16_zext_i32(float %a) #0 {
; SI-SDAG-LABEL: fptrunc_fabs_f32_to_f16_zext_i32:
; SI-SDAG:       ; %bb.0:
; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-SDAG-NEXT:    v_cvt_f16_f32_e64 v0, |v0|
; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; SI-GISEL-LABEL: fptrunc_fabs_f32_to_f16_zext_i32:
; SI-GISEL:       ; %bb.0:
; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-GISEL-NEXT:    v_cvt_f16_f32_e64 v0, |v0|
; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: fptrunc_fabs_f32_to_f16_zext_i32:
; VI-SDAG:       ; %bb.0:
; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-NEXT:    v_cvt_f16_f32_e64 v0, |v0|
; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: fptrunc_fabs_f32_to_f16_zext_i32:
; VI-GISEL:       ; %bb.0:
; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT:    v_cvt_f16_f32_e64 v0, |v0|
; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: fptrunc_fabs_f32_to_f16_zext_i32:
; GFX9-SDAG:       ; %bb.0:
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT:    v_cvt_f16_f32_e64 v0, |v0|
; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: fptrunc_fabs_f32_to_f16_zext_i32:
; GFX9-GISEL:       ; %bb.0:
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT:    v_cvt_f16_f32_e64 v0, |v0|
; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX950-SDAG-LABEL: fptrunc_fabs_f32_to_f16_zext_i32:
; GFX950-SDAG:       ; %bb.0:
; GFX950-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-SDAG-NEXT:    v_cvt_f16_f32_e64 v0, |v0|
; GFX950-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX950-GISEL-LABEL: fptrunc_fabs_f32_to_f16_zext_i32:
; GFX950-GISEL:       ; %bb.0:
; GFX950-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-GISEL-NEXT:    v_cvt_f16_f32_e64 v0, |v0|
; GFX950-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: fptrunc_fabs_f32_to_f16_zext_i32:
; GFX11-SDAG-TRUE16:       ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT:    v_cvt_f16_f32_e64 v0.l, |v0|
; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT:    v_cvt_u32_u16_e32 v0, v0.l
; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: fptrunc_fabs_f32_to_f16_zext_i32:
; GFX11-SDAG-FAKE16:       ; %bb.0:
; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT:    v_cvt_f16_f32_e64 v0, |v0|
; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-GISEL-TRUE16-LABEL: fptrunc_fabs_f32_to_f16_zext_i32:
; GFX11-GISEL-TRUE16:       ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT:    v_cvt_f16_f32_e64 v0.l, |v0|
; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT:    v_cvt_u32_u16_e32 v0, v0.l
; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: fptrunc_fabs_f32_to_f16_zext_i32:
; GFX11-GISEL-FAKE16:       ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT:    v_cvt_f16_f32_e64 v0, |v0|
; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1250-SDAG-TRUE16-LABEL: fptrunc_fabs_f32_to_f16_zext_i32:
; GFX1250-SDAG-TRUE16:       ; %bb.0:
; GFX1250-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-TRUE16-NEXT:    v_cvt_f16_f32_e64 v0.l, |v0|
; GFX1250-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-TRUE16-NEXT:    v_cvt_u32_u16_e32 v0, v0.l
; GFX1250-SDAG-TRUE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-SDAG-FAKE16-LABEL: fptrunc_fabs_f32_to_f16_zext_i32:
; GFX1250-SDAG-FAKE16:       ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-FAKE16-NEXT:    v_cvt_f16_f32_e64 v0, |v0|
; GFX1250-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; GFX1250-SDAG-FAKE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-GISEL-TRUE16-LABEL: fptrunc_fabs_f32_to_f16_zext_i32:
; GFX1250-GISEL-TRUE16:       ; %bb.0:
; GFX1250-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT:    v_cvt_f16_f32_e64 v0.l, |v0|
; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-TRUE16-NEXT:    v_cvt_u32_u16_e32 v0, v0.l
; GFX1250-GISEL-TRUE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-GISEL-FAKE16-LABEL: fptrunc_fabs_f32_to_f16_zext_i32:
; GFX1250-GISEL-FAKE16:       ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_f16_f32_e64 v0, |v0|
; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; GFX1250-GISEL-FAKE16-NEXT:    s_set_pc_i64 s[30:31]
  %a.fabs = call float @llvm.fabs.f32(float %a)
  %r.val = fptrunc float %a.fabs to half
  %r.i16 = bitcast half %r.val to i16
  %zext = zext i16 %r.i16 to i32
  ret i32 %zext
}

define i32 @fptrunc_f32_to_f16_sext_i32(float %a) #0 {
; SI-SDAG-LABEL: fptrunc_f32_to_f16_sext_i32:
; SI-SDAG:       ; %bb.0:
; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-SDAG-NEXT:    v_bfe_i32 v0, v0, 0, 16
; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; SI-GISEL-LABEL: fptrunc_f32_to_f16_sext_i32:
; SI-GISEL:       ; %bb.0:
; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-GISEL-NEXT:    v_bfe_i32 v0, v0, 0, 16
; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: fptrunc_f32_to_f16_sext_i32:
; VI-SDAG:       ; %bb.0:
; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
; VI-SDAG-NEXT:    v_bfe_i32 v0, v0, 0, 16
; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: fptrunc_f32_to_f16_sext_i32:
; VI-GISEL:       ; %bb.0:
; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
; VI-GISEL-NEXT:    v_bfe_i32 v0, v0, 0, 16
; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: fptrunc_f32_to_f16_sext_i32:
; GFX9-SDAG:       ; %bb.0:
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX9-SDAG-NEXT:    v_bfe_i32 v0, v0, 0, 16
; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: fptrunc_f32_to_f16_sext_i32:
; GFX9-GISEL:       ; %bb.0:
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX9-GISEL-NEXT:    v_bfe_i32 v0, v0, 0, 16
; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX950-SDAG-LABEL: fptrunc_f32_to_f16_sext_i32:
; GFX950-SDAG:       ; %bb.0:
; GFX950-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX950-SDAG-NEXT:    v_bfe_i32 v0, v0, 0, 16
; GFX950-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX950-GISEL-LABEL: fptrunc_f32_to_f16_sext_i32:
; GFX950-GISEL:       ; %bb.0:
; GFX950-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX950-GISEL-NEXT:    v_bfe_i32 v0, v0, 0, 16
; GFX950-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: fptrunc_f32_to_f16_sext_i32:
; GFX11-SDAG-TRUE16:       ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: fptrunc_f32_to_f16_sext_i32:
; GFX11-SDAG-FAKE16:       ; %bb.0:
; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-GISEL-TRUE16-LABEL: fptrunc_f32_to_f16_sext_i32:
; GFX11-GISEL-TRUE16:       ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: fptrunc_f32_to_f16_sext_i32:
; GFX11-GISEL-FAKE16:       ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1250-SDAG-TRUE16-LABEL: fptrunc_f32_to_f16_sext_i32:
; GFX1250-SDAG-TRUE16:       ; %bb.0:
; GFX1250-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
; GFX1250-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
; GFX1250-SDAG-TRUE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-SDAG-FAKE16-LABEL: fptrunc_f32_to_f16_sext_i32:
; GFX1250-SDAG-FAKE16:       ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX1250-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
; GFX1250-SDAG-FAKE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-GISEL-TRUE16-LABEL: fptrunc_f32_to_f16_sext_i32:
; GFX1250-GISEL-TRUE16:       ; %bb.0:
; GFX1250-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
; GFX1250-GISEL-TRUE16-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-GISEL-FAKE16-LABEL: fptrunc_f32_to_f16_sext_i32:
; GFX1250-GISEL-FAKE16:       ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
; GFX1250-GISEL-FAKE16-NEXT:    s_set_pc_i64 s[30:31]
  %r.val = fptrunc float %a to half
  %r.i16 = bitcast half %r.val to i16
  %zext = sext i16 %r.i16 to i32
  ret i32 %zext
}

declare float @llvm.fabs.f32(float) #1

attributes #0 = { nounwind }
attributes #1 = { nounwind readnone }