llvm/test/CodeGen/AMDGPU/fold-and-exec-wave32.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=amdgpu11.00 -run-pass=si-fold-operands -o - %s | FileCheck %s

# Wave32 version of fold-and-exec.mir: a V_CMP already writes 0 to the bits of
# inactive lanes, so ANDing its result with EXEC_LO is a no-op.

---
name: vcmp_e64
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; CHECK-LABEL: name: vcmp_e64
    ; CHECK: liveins: $vgpr0, $vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[V_CMP_LT_I32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_LT_I32_e64 $vgpr0, $vgpr1, implicit $exec
    ; CHECK-NEXT: $vcc_lo = COPY [[V_CMP_LT_I32_e64_]]
    ; CHECK-NEXT: S_ENDPGM 0, implicit $vcc_lo
    %0:sreg_32_xm0_xexec = V_CMP_LT_I32_e64 $vgpr0, $vgpr1, implicit $exec
    %1:sreg_32_xm0_xexec = S_AND_B32 $exec_lo, %0, implicit-def dead $scc
    $vcc_lo = COPY %1
    S_ENDPGM 0, implicit $vcc_lo
...

# Negative test: nothing is known about the lane mask.
---
name: unknown_mask
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $sgpr0
    ; CHECK-LABEL: name: unknown_mask
    ; CHECK: liveins: $sgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32_xm0_xexec = COPY $sgpr0
    ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 $exec_lo, [[COPY]], implicit-def dead $scc
    ; CHECK-NEXT: $vcc_lo = COPY [[S_AND_B32_]]
    ; CHECK-NEXT: S_ENDPGM 0, implicit $vcc_lo
    %0:sreg_32_xm0_xexec = COPY $sgpr0
    %1:sreg_32_xm0_xexec = S_AND_B32 $exec_lo, %0, implicit-def dead $scc
    $vcc_lo = COPY %1
    S_ENDPGM 0, implicit $vcc_lo
...