llvm/test/CodeGen/AMDGPU/fcmp.f16.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN:  llc -mtriple=amdgpu6.00 < %s | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=SI %s
; RUN:  llc -mtriple=amdgpu8.03 < %s | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=VI %s
; RUN:  llc -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=GFX11-TRUE16 %s
; RUN:  llc -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=GFX11-FAKE16 %s
; RUN:  llc -mtriple=amdgpu12.00 -mattr=+real-true16 < %s | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=GFX12,GFX12-TRUE16 %s
; RUN:  llc -mtriple=amdgpu12.00 -mattr=-real-true16 < %s | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=GFX12,GFX12-FAKE16 %s

define i32 @fcmp_f16_lt(half %a, half %b) {
; SI-LABEL: fcmp_f16_lt:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
; SI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: fcmp_f16_lt:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_lt_f16_e32 vcc, v0, v1
; VI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: fcmp_f16_lt:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v0.l, v1.l
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fcmp_f16_lt:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v0, v1
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: fcmp_f16_lt:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: fcmp_f16_lt:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v0, v1
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %r.val = fcmp olt half %a, %b
  %r.val.sext = sext i1 %r.val to i32
  ret i32 %r.val.sext
}

define i32 @fcmp_f16_lt_abs(half %a, half %b) {
; SI-LABEL: fcmp_f16_lt_abs:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cvt_f32_f16_e64 v1, |v1|
; SI-NEXT:    v_cvt_f32_f16_e64 v0, |v0|
; SI-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
; SI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: fcmp_f16_lt_abs:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_lt_f16_e64 s[4:5], |v0|, |v1|
; VI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, s[4:5]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: fcmp_f16_lt_abs:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cmp_lt_f16_e64 s0, |v0.l|, |v1.l|
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, s0
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fcmp_f16_lt_abs:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cmp_lt_f16_e64 s0, |v0|, |v1|
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, s0
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: fcmp_f16_lt_abs:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cmp_lt_f16_e64 s0, |v0.l|, |v1.l|
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, s0
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: fcmp_f16_lt_abs:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_cmp_lt_f16_e64 s0, |v0|, |v1|
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, s0
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %a.abs = call half @llvm.fabs.f16(half %a)
  %b.abs = call half @llvm.fabs.f16(half %b)
  %r.val = fcmp olt half %a.abs, %b.abs
  %r.val.sext = sext i1 %r.val to i32
  ret i32 %r.val.sext
}

define i32 @fcmp_f16_eq(half %a, half %b) {
; SI-LABEL: fcmp_f16_eq:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_cmp_eq_f32_e32 vcc, v0, v1
; SI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: fcmp_f16_eq:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_eq_f16_e32 vcc, v0, v1
; VI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: fcmp_f16_eq:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cmp_eq_f16_e32 vcc_lo, v0.l, v1.l
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fcmp_f16_eq:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cmp_eq_f16_e32 vcc_lo, v0, v1
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: fcmp_f16_eq:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cmp_eq_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: fcmp_f16_eq:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_cmp_eq_f16_e32 vcc_lo, v0, v1
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %r.val = fcmp oeq half %a, %b
  %r.val.sext = sext i1 %r.val to i32
  ret i32 %r.val.sext
}

define i32 @fcmp_f16_le(half %a, half %b) {
; SI-LABEL: fcmp_f16_le:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_cmp_le_f32_e32 vcc, v0, v1
; SI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: fcmp_f16_le:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_le_f16_e32 vcc, v0, v1
; VI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: fcmp_f16_le:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cmp_le_f16_e32 vcc_lo, v0.l, v1.l
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fcmp_f16_le:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cmp_le_f16_e32 vcc_lo, v0, v1
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: fcmp_f16_le:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cmp_le_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: fcmp_f16_le:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_cmp_le_f16_e32 vcc_lo, v0, v1
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %r.val = fcmp ole half %a, %b
  %r.val.sext = sext i1 %r.val to i32
  ret i32 %r.val.sext
}

define i32 @fcmp_f16_gt(half %a, half %b) {
; SI-LABEL: fcmp_f16_gt:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v1
; SI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: fcmp_f16_gt:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_gt_f16_e32 vcc, v0, v1
; VI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: fcmp_f16_gt:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v0.l, v1.l
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fcmp_f16_gt:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v0, v1
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: fcmp_f16_gt:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: fcmp_f16_gt:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v0, v1
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %r.val = fcmp ogt half %a, %b
  %r.val.sext = sext i1 %r.val to i32
  ret i32 %r.val.sext
}

define i32 @fcmp_f16_lg(half %a, half %b) {
; SI-LABEL: fcmp_f16_lg:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_cmp_lg_f32_e32 vcc, v0, v1
; SI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: fcmp_f16_lg:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_lg_f16_e32 vcc, v0, v1
; VI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: fcmp_f16_lg:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, v0.l, v1.l
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fcmp_f16_lg:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, v0, v1
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: fcmp_f16_lg:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: fcmp_f16_lg:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, v0, v1
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %r.val = fcmp one half %a, %b
  %r.val.sext = sext i1 %r.val to i32
  ret i32 %r.val.sext
}

define i32 @fcmp_f16_ge(half %a, half %b) {
; SI-LABEL: fcmp_f16_ge:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_cmp_ge_f32_e32 vcc, v0, v1
; SI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: fcmp_f16_ge:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ge_f16_e32 vcc, v0, v1
; VI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: fcmp_f16_ge:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, v0.l, v1.l
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fcmp_f16_ge:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, v0, v1
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: fcmp_f16_ge:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: fcmp_f16_ge:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, v0, v1
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %r.val = fcmp oge half %a, %b
  %r.val.sext = sext i1 %r.val to i32
  ret i32 %r.val.sext
}

define i32 @fcmp_f16_o(half %a, half %b) {
; SI-LABEL: fcmp_f16_o:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_cmp_o_f32_e32 vcc, v0, v1
; SI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: fcmp_f16_o:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_o_f16_e32 vcc, v0, v1
; VI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: fcmp_f16_o:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fcmp_f16_o:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v1
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: fcmp_f16_o:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: fcmp_f16_o:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v1
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %r.val = fcmp ord half %a, %b
  %r.val.sext = sext i1 %r.val to i32
  ret i32 %r.val.sext
}

define i32 @fcmp_f16_u(half %a, half %b) {
; SI-LABEL: fcmp_f16_u:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v1
; SI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: fcmp_f16_u:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_u_f16_e32 vcc, v0, v1
; VI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: fcmp_f16_u:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cmp_u_f16_e32 vcc_lo, v0.l, v1.l
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fcmp_f16_u:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cmp_u_f16_e32 vcc_lo, v0, v1
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: fcmp_f16_u:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cmp_u_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: fcmp_f16_u:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_cmp_u_f16_e32 vcc_lo, v0, v1
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %r.val = fcmp uno half %a, %b
  %r.val.sext = sext i1 %r.val to i32
  ret i32 %r.val.sext
}

define i32 @fcmp_f16_nge(half %a, half %b) {
; SI-LABEL: fcmp_f16_nge:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_cmp_nge_f32_e32 vcc, v0, v1
; SI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: fcmp_f16_nge:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_nge_f16_e32 vcc, v0, v1
; VI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: fcmp_f16_nge:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cmp_nge_f16_e32 vcc_lo, v0.l, v1.l
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fcmp_f16_nge:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cmp_nge_f16_e32 vcc_lo, v0, v1
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: fcmp_f16_nge:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cmp_nge_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: fcmp_f16_nge:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_cmp_nge_f16_e32 vcc_lo, v0, v1
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %r.val = fcmp ult half %a, %b
  %r.val.sext = sext i1 %r.val to i32
  ret i32 %r.val.sext
}

define i32 @fcmp_f16_nlg(half %a, half %b) {
; SI-LABEL: fcmp_f16_nlg:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_cmp_nlg_f32_e32 vcc, v0, v1
; SI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: fcmp_f16_nlg:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_nlg_f16_e32 vcc, v0, v1
; VI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: fcmp_f16_nlg:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cmp_nlg_f16_e32 vcc_lo, v0.l, v1.l
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fcmp_f16_nlg:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cmp_nlg_f16_e32 vcc_lo, v0, v1
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: fcmp_f16_nlg:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cmp_nlg_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: fcmp_f16_nlg:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_cmp_nlg_f16_e32 vcc_lo, v0, v1
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %r.val = fcmp ueq half %a, %b
  %r.val.sext = sext i1 %r.val to i32
  ret i32 %r.val.sext
}

define i32 @fcmp_f16_ngt(half %a, half %b) {
; SI-LABEL: fcmp_f16_ngt:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_cmp_ngt_f32_e32 vcc, v0, v1
; SI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: fcmp_f16_ngt:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ngt_f16_e32 vcc, v0, v1
; VI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: fcmp_f16_ngt:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0.l, v1.l
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fcmp_f16_ngt:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v1
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: fcmp_f16_ngt:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: fcmp_f16_ngt:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v1
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %r.val = fcmp ule half %a, %b
  %r.val.sext = sext i1 %r.val to i32
  ret i32 %r.val.sext
}

define i32 @fcmp_f16_nle(half %a, half %b) {
; SI-LABEL: fcmp_f16_nle:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_cmp_nle_f32_e32 vcc, v0, v1
; SI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: fcmp_f16_nle:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_nle_f16_e32 vcc, v0, v1
; VI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: fcmp_f16_nle:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v0.l, v1.l
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fcmp_f16_nle:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v0, v1
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: fcmp_f16_nle:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: fcmp_f16_nle:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v0, v1
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %r.val = fcmp ugt half %a, %b
  %r.val.sext = sext i1 %r.val to i32
  ret i32 %r.val.sext
}

define i32 @fcmp_f16_neq(half %a, half %b) {
; SI-LABEL: fcmp_f16_neq:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_cmp_neq_f32_e32 vcc, v0, v1
; SI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: fcmp_f16_neq:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_neq_f16_e32 vcc, v0, v1
; VI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: fcmp_f16_neq:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cmp_neq_f16_e32 vcc_lo, v0.l, v1.l
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fcmp_f16_neq:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cmp_neq_f16_e32 vcc_lo, v0, v1
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: fcmp_f16_neq:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cmp_neq_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: fcmp_f16_neq:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_cmp_neq_f16_e32 vcc_lo, v0, v1
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %r.val = fcmp une half %a, %b
  %r.val.sext = sext i1 %r.val to i32
  ret i32 %r.val.sext
}

define i32 @fcmp_f16_nlt(half %a, half %b) {
; SI-LABEL: fcmp_f16_nlt:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_cmp_nlt_f32_e32 vcc, v0, v1
; SI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: fcmp_f16_nlt:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_nlt_f16_e32 vcc, v0, v1
; VI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: fcmp_f16_nlt:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0.l, v1.l
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fcmp_f16_nlt:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v1
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: fcmp_f16_nlt:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: fcmp_f16_nlt:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v1
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %r.val = fcmp uge half %a, %b
  %r.val.sext = sext i1 %r.val to i32
  ret i32 %r.val.sext
}

define <2 x i32> @fcmp_v2f16_lt(<2 x half> %a, <2 x half> %b) {
; SI-LABEL: fcmp_v2f16_lt:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v3, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v2, v2
; SI-NEXT:    v_cvt_f32_f16_e32 v4, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_cmp_lt_f32_e32 vcc, v2, v3
; SI-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc
; SI-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v4
; SI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: fcmp_v2f16_lt:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; VI-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; VI-NEXT:    v_cmp_lt_f16_e32 vcc, v3, v2
; VI-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
; VI-NEXT:    v_cmp_lt_f16_e32 vcc, v0, v1
; VI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; VI-NEXT:    v_mov_b32_e32 v1, v2
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: fcmp_v2f16_lt:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v0.l, v1.l
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v0.h, v1.h
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, v2
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fcmp_v2f16_lt:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX11-FAKE16-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v0, v1
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v3, v2
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: fcmp_v2f16_lt:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v0.h, v1.h
; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v0, v2
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: fcmp_v2f16_lt:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX12-FAKE16-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v0, v1
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v3, v2
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %r.val = fcmp olt <2 x half> %a, %b
  %r.val.sext = sext <2 x i1> %r.val to <2 x i32>
  ret <2 x i32> %r.val.sext
}


define <2 x i32> @fcmp_v2f16_eq(<2 x half> %a, <2 x half> %b) {
; SI-LABEL: fcmp_v2f16_eq:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v3, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v2, v2
; SI-NEXT:    v_cvt_f32_f16_e32 v4, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_cmp_eq_f32_e32 vcc, v2, v3
; SI-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc
; SI-NEXT:    v_cmp_eq_f32_e32 vcc, v0, v4
; SI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: fcmp_v2f16_eq:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; VI-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; VI-NEXT:    v_cmp_eq_f16_e32 vcc, v3, v2
; VI-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
; VI-NEXT:    v_cmp_eq_f16_e32 vcc, v0, v1
; VI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; VI-NEXT:    v_mov_b32_e32 v1, v2
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: fcmp_v2f16_eq:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cmp_eq_f16_e32 vcc_lo, v0.l, v1.l
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    v_cmp_eq_f16_e32 vcc_lo, v0.h, v1.h
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, v2
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fcmp_v2f16_eq:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX11-FAKE16-NEXT:    v_cmp_eq_f16_e32 vcc_lo, v0, v1
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT:    v_cmp_eq_f16_e32 vcc_lo, v3, v2
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: fcmp_v2f16_eq:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cmp_eq_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    v_cmp_eq_f16_e32 vcc_lo, v0.h, v1.h
; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v0, v2
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: fcmp_v2f16_eq:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX12-FAKE16-NEXT:    v_cmp_eq_f16_e32 vcc_lo, v0, v1
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT:    v_cmp_eq_f16_e32 vcc_lo, v3, v2
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %r.val = fcmp oeq <2 x half> %a, %b
  %r.val.sext = sext <2 x i1> %r.val to <2 x i32>
  ret <2 x i32> %r.val.sext
}

define <2 x i32> @fcmp_v2f16_le(<2 x half> %a, <2 x half> %b) {
; SI-LABEL: fcmp_v2f16_le:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v3, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v2, v2
; SI-NEXT:    v_cvt_f32_f16_e32 v4, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_cmp_le_f32_e32 vcc, v2, v3
; SI-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc
; SI-NEXT:    v_cmp_le_f32_e32 vcc, v0, v4
; SI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: fcmp_v2f16_le:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; VI-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; VI-NEXT:    v_cmp_le_f16_e32 vcc, v3, v2
; VI-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
; VI-NEXT:    v_cmp_le_f16_e32 vcc, v0, v1
; VI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; VI-NEXT:    v_mov_b32_e32 v1, v2
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: fcmp_v2f16_le:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cmp_le_f16_e32 vcc_lo, v0.l, v1.l
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    v_cmp_le_f16_e32 vcc_lo, v0.h, v1.h
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, v2
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fcmp_v2f16_le:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX11-FAKE16-NEXT:    v_cmp_le_f16_e32 vcc_lo, v0, v1
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT:    v_cmp_le_f16_e32 vcc_lo, v3, v2
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: fcmp_v2f16_le:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cmp_le_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    v_cmp_le_f16_e32 vcc_lo, v0.h, v1.h
; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v0, v2
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: fcmp_v2f16_le:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX12-FAKE16-NEXT:    v_cmp_le_f16_e32 vcc_lo, v0, v1
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT:    v_cmp_le_f16_e32 vcc_lo, v3, v2
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %r.val = fcmp ole <2 x half> %a, %b
  %r.val.sext = sext <2 x i1> %r.val to <2 x i32>
  ret <2 x i32> %r.val.sext
}

define <2 x i32> @fcmp_v2f16_gt(<2 x half> %a, <2 x half> %b) {
; SI-LABEL: fcmp_v2f16_gt:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v3, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v2, v2
; SI-NEXT:    v_cvt_f32_f16_e32 v4, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v3
; SI-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc
; SI-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v4
; SI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: fcmp_v2f16_gt:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; VI-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; VI-NEXT:    v_cmp_gt_f16_e32 vcc, v3, v2
; VI-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
; VI-NEXT:    v_cmp_gt_f16_e32 vcc, v0, v1
; VI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; VI-NEXT:    v_mov_b32_e32 v1, v2
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: fcmp_v2f16_gt:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v0.l, v1.l
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v0.h, v1.h
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, v2
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fcmp_v2f16_gt:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX11-FAKE16-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v0, v1
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v3, v2
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: fcmp_v2f16_gt:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v0.h, v1.h
; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v0, v2
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: fcmp_v2f16_gt:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX12-FAKE16-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v0, v1
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v3, v2
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %r.val = fcmp ogt <2 x half> %a, %b
  %r.val.sext = sext <2 x i1> %r.val to <2 x i32>
  ret <2 x i32> %r.val.sext
}


define <2 x i32> @fcmp_v2f16_lg(<2 x half> %a, <2 x half> %b) {
; SI-LABEL: fcmp_v2f16_lg:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v3, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v2, v2
; SI-NEXT:    v_cvt_f32_f16_e32 v4, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_cmp_lg_f32_e32 vcc, v2, v3
; SI-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc
; SI-NEXT:    v_cmp_lg_f32_e32 vcc, v0, v4
; SI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: fcmp_v2f16_lg:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; VI-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; VI-NEXT:    v_cmp_lg_f16_e32 vcc, v3, v2
; VI-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
; VI-NEXT:    v_cmp_lg_f16_e32 vcc, v0, v1
; VI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; VI-NEXT:    v_mov_b32_e32 v1, v2
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: fcmp_v2f16_lg:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, v0.l, v1.l
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, v0.h, v1.h
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, v2
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fcmp_v2f16_lg:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX11-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, v0, v1
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, v3, v2
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: fcmp_v2f16_lg:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, v0.h, v1.h
; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v0, v2
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: fcmp_v2f16_lg:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX12-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, v0, v1
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, v3, v2
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %r.val = fcmp one <2 x half> %a, %b
  %r.val.sext = sext <2 x i1> %r.val to <2 x i32>
  ret <2 x i32> %r.val.sext
}


define <2 x i32> @fcmp_v2f16_ge(<2 x half> %a, <2 x half> %b) {
; SI-LABEL: fcmp_v2f16_ge:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v3, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v2, v2
; SI-NEXT:    v_cvt_f32_f16_e32 v4, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_cmp_ge_f32_e32 vcc, v2, v3
; SI-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc
; SI-NEXT:    v_cmp_ge_f32_e32 vcc, v0, v4
; SI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: fcmp_v2f16_ge:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; VI-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; VI-NEXT:    v_cmp_ge_f16_e32 vcc, v3, v2
; VI-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
; VI-NEXT:    v_cmp_ge_f16_e32 vcc, v0, v1
; VI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; VI-NEXT:    v_mov_b32_e32 v1, v2
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: fcmp_v2f16_ge:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, v0.l, v1.l
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, v0.h, v1.h
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, v2
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fcmp_v2f16_ge:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX11-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, v0, v1
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, v3, v2
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: fcmp_v2f16_ge:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, v0.h, v1.h
; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v0, v2
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: fcmp_v2f16_ge:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX12-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, v0, v1
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, v3, v2
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %r.val = fcmp oge <2 x half> %a, %b
  %r.val.sext = sext <2 x i1> %r.val to <2 x i32>
  ret <2 x i32> %r.val.sext
}


define <2 x i32> @fcmp_v2f16_o(<2 x half> %a, <2 x half> %b) {
; SI-LABEL: fcmp_v2f16_o:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v3, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v2, v2
; SI-NEXT:    v_cvt_f32_f16_e32 v4, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_cmp_o_f32_e32 vcc, v2, v3
; SI-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc
; SI-NEXT:    v_cmp_o_f32_e32 vcc, v0, v4
; SI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: fcmp_v2f16_o:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; VI-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; VI-NEXT:    v_cmp_o_f16_e32 vcc, v3, v2
; VI-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
; VI-NEXT:    v_cmp_o_f16_e32 vcc, v0, v1
; VI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; VI-NEXT:    v_mov_b32_e32 v1, v2
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: fcmp_v2f16_o:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.h, v1.h
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, v2
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fcmp_v2f16_o:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX11-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v1
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v3, v2
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: fcmp_v2f16_o:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.h, v1.h
; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v0, v2
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: fcmp_v2f16_o:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX12-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v1
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v3, v2
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %r.val = fcmp ord <2 x half> %a, %b
  %r.val.sext = sext <2 x i1> %r.val to <2 x i32>
  ret <2 x i32> %r.val.sext
}


define <2 x i32> @fcmp_v2f16_u(<2 x half> %a, <2 x half> %b) {
; SI-LABEL: fcmp_v2f16_u:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v3, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v2, v2
; SI-NEXT:    v_cvt_f32_f16_e32 v4, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_cmp_u_f32_e32 vcc, v2, v3
; SI-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc
; SI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v4
; SI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: fcmp_v2f16_u:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; VI-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; VI-NEXT:    v_cmp_u_f16_e32 vcc, v3, v2
; VI-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
; VI-NEXT:    v_cmp_u_f16_e32 vcc, v0, v1
; VI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; VI-NEXT:    v_mov_b32_e32 v1, v2
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: fcmp_v2f16_u:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cmp_u_f16_e32 vcc_lo, v0.l, v1.l
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    v_cmp_u_f16_e32 vcc_lo, v0.h, v1.h
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, v2
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fcmp_v2f16_u:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX11-FAKE16-NEXT:    v_cmp_u_f16_e32 vcc_lo, v0, v1
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT:    v_cmp_u_f16_e32 vcc_lo, v3, v2
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: fcmp_v2f16_u:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cmp_u_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    v_cmp_u_f16_e32 vcc_lo, v0.h, v1.h
; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v0, v2
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: fcmp_v2f16_u:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX12-FAKE16-NEXT:    v_cmp_u_f16_e32 vcc_lo, v0, v1
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT:    v_cmp_u_f16_e32 vcc_lo, v3, v2
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %r.val = fcmp uno <2 x half> %a, %b
  %r.val.sext = sext <2 x i1> %r.val to <2 x i32>
  ret <2 x i32> %r.val.sext
}

define <2 x i32> @fcmp_v2f16_nge(<2 x half> %a, <2 x half> %b) {
; SI-LABEL: fcmp_v2f16_nge:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v3, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v2, v2
; SI-NEXT:    v_cvt_f32_f16_e32 v4, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_cmp_nge_f32_e32 vcc, v2, v3
; SI-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc
; SI-NEXT:    v_cmp_nge_f32_e32 vcc, v0, v4
; SI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: fcmp_v2f16_nge:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; VI-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; VI-NEXT:    v_cmp_nge_f16_e32 vcc, v3, v2
; VI-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
; VI-NEXT:    v_cmp_nge_f16_e32 vcc, v0, v1
; VI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; VI-NEXT:    v_mov_b32_e32 v1, v2
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: fcmp_v2f16_nge:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cmp_nge_f16_e32 vcc_lo, v0.l, v1.l
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    v_cmp_nge_f16_e32 vcc_lo, v0.h, v1.h
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, v2
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fcmp_v2f16_nge:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX11-FAKE16-NEXT:    v_cmp_nge_f16_e32 vcc_lo, v0, v1
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT:    v_cmp_nge_f16_e32 vcc_lo, v3, v2
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: fcmp_v2f16_nge:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cmp_nge_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    v_cmp_nge_f16_e32 vcc_lo, v0.h, v1.h
; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v0, v2
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: fcmp_v2f16_nge:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX12-FAKE16-NEXT:    v_cmp_nge_f16_e32 vcc_lo, v0, v1
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT:    v_cmp_nge_f16_e32 vcc_lo, v3, v2
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %r.val = fcmp ult <2 x half> %a, %b
  %r.val.sext = sext <2 x i1> %r.val to <2 x i32>
  ret <2 x i32> %r.val.sext
}

define <2 x i32> @fcmp_v2f16_nlg(<2 x half> %a, <2 x half> %b) {
; SI-LABEL: fcmp_v2f16_nlg:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v3, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v2, v2
; SI-NEXT:    v_cvt_f32_f16_e32 v4, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_cmp_nlg_f32_e32 vcc, v2, v3
; SI-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc
; SI-NEXT:    v_cmp_nlg_f32_e32 vcc, v0, v4
; SI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: fcmp_v2f16_nlg:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; VI-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; VI-NEXT:    v_cmp_nlg_f16_e32 vcc, v3, v2
; VI-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
; VI-NEXT:    v_cmp_nlg_f16_e32 vcc, v0, v1
; VI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; VI-NEXT:    v_mov_b32_e32 v1, v2
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: fcmp_v2f16_nlg:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cmp_nlg_f16_e32 vcc_lo, v0.l, v1.l
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    v_cmp_nlg_f16_e32 vcc_lo, v0.h, v1.h
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, v2
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fcmp_v2f16_nlg:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX11-FAKE16-NEXT:    v_cmp_nlg_f16_e32 vcc_lo, v0, v1
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT:    v_cmp_nlg_f16_e32 vcc_lo, v3, v2
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: fcmp_v2f16_nlg:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cmp_nlg_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    v_cmp_nlg_f16_e32 vcc_lo, v0.h, v1.h
; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v0, v2
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: fcmp_v2f16_nlg:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX12-FAKE16-NEXT:    v_cmp_nlg_f16_e32 vcc_lo, v0, v1
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT:    v_cmp_nlg_f16_e32 vcc_lo, v3, v2
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %r.val = fcmp ueq <2 x half> %a, %b
  %r.val.sext = sext <2 x i1> %r.val to <2 x i32>
  ret <2 x i32> %r.val.sext
}


define <2 x i32> @fcmp_v2f16_ngt(<2 x half> %a, <2 x half> %b) {
; SI-LABEL: fcmp_v2f16_ngt:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v3, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v2, v2
; SI-NEXT:    v_cvt_f32_f16_e32 v4, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_cmp_ngt_f32_e32 vcc, v2, v3
; SI-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc
; SI-NEXT:    v_cmp_ngt_f32_e32 vcc, v0, v4
; SI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: fcmp_v2f16_ngt:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; VI-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; VI-NEXT:    v_cmp_ngt_f16_e32 vcc, v3, v2
; VI-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
; VI-NEXT:    v_cmp_ngt_f16_e32 vcc, v0, v1
; VI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; VI-NEXT:    v_mov_b32_e32 v1, v2
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: fcmp_v2f16_ngt:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0.l, v1.l
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0.h, v1.h
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, v2
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fcmp_v2f16_ngt:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX11-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v1
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v3, v2
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: fcmp_v2f16_ngt:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0.h, v1.h
; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v0, v2
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: fcmp_v2f16_ngt:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v1
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v3, v2
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %r.val = fcmp ule <2 x half> %a, %b
  %r.val.sext = sext <2 x i1> %r.val to <2 x i32>
  ret <2 x i32> %r.val.sext
}

define <2 x i32> @fcmp_v2f16_nle(<2 x half> %a, <2 x half> %b) {
; SI-LABEL: fcmp_v2f16_nle:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v3, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v2, v2
; SI-NEXT:    v_cvt_f32_f16_e32 v4, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_cmp_nle_f32_e32 vcc, v2, v3
; SI-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc
; SI-NEXT:    v_cmp_nle_f32_e32 vcc, v0, v4
; SI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: fcmp_v2f16_nle:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; VI-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; VI-NEXT:    v_cmp_nle_f16_e32 vcc, v3, v2
; VI-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
; VI-NEXT:    v_cmp_nle_f16_e32 vcc, v0, v1
; VI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; VI-NEXT:    v_mov_b32_e32 v1, v2
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: fcmp_v2f16_nle:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v0.l, v1.l
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v0.h, v1.h
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, v2
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fcmp_v2f16_nle:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX11-FAKE16-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v0, v1
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v3, v2
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: fcmp_v2f16_nle:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v0.h, v1.h
; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v0, v2
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: fcmp_v2f16_nle:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX12-FAKE16-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v0, v1
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v3, v2
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %r.val = fcmp ugt <2 x half> %a, %b
  %r.val.sext = sext <2 x i1> %r.val to <2 x i32>
  ret <2 x i32> %r.val.sext
}

define <2 x i32> @fcmp_v2f16_neq(<2 x half> %a, <2 x half> %b) {
; SI-LABEL: fcmp_v2f16_neq:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v3, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v2, v2
; SI-NEXT:    v_cvt_f32_f16_e32 v4, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_cmp_neq_f32_e32 vcc, v2, v3
; SI-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc
; SI-NEXT:    v_cmp_neq_f32_e32 vcc, v0, v4
; SI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: fcmp_v2f16_neq:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; VI-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; VI-NEXT:    v_cmp_neq_f16_e32 vcc, v3, v2
; VI-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
; VI-NEXT:    v_cmp_neq_f16_e32 vcc, v0, v1
; VI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; VI-NEXT:    v_mov_b32_e32 v1, v2
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: fcmp_v2f16_neq:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cmp_neq_f16_e32 vcc_lo, v0.l, v1.l
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    v_cmp_neq_f16_e32 vcc_lo, v0.h, v1.h
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, v2
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fcmp_v2f16_neq:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX11-FAKE16-NEXT:    v_cmp_neq_f16_e32 vcc_lo, v0, v1
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT:    v_cmp_neq_f16_e32 vcc_lo, v3, v2
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: fcmp_v2f16_neq:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cmp_neq_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    v_cmp_neq_f16_e32 vcc_lo, v0.h, v1.h
; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v0, v2
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: fcmp_v2f16_neq:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX12-FAKE16-NEXT:    v_cmp_neq_f16_e32 vcc_lo, v0, v1
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT:    v_cmp_neq_f16_e32 vcc_lo, v3, v2
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %r.val = fcmp une <2 x half> %a, %b
  %r.val.sext = sext <2 x i1> %r.val to <2 x i32>
  ret <2 x i32> %r.val.sext
}

define <2 x i32> @fcmp_v2f16_nlt(<2 x half> %a, <2 x half> %b) {
; SI-LABEL: fcmp_v2f16_nlt:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v3, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v2, v2
; SI-NEXT:    v_cvt_f32_f16_e32 v4, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_cmp_nlt_f32_e32 vcc, v2, v3
; SI-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc
; SI-NEXT:    v_cmp_nlt_f32_e32 vcc, v0, v4
; SI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: fcmp_v2f16_nlt:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; VI-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; VI-NEXT:    v_cmp_nlt_f16_e32 vcc, v3, v2
; VI-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
; VI-NEXT:    v_cmp_nlt_f16_e32 vcc, v0, v1
; VI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; VI-NEXT:    v_mov_b32_e32 v1, v2
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: fcmp_v2f16_nlt:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0.l, v1.l
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0.h, v1.h
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, v2
; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fcmp_v2f16_nlt:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX11-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v1
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v3, v2
; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: fcmp_v2f16_nlt:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0.h, v1.h
; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v0, v2
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: fcmp_v2f16_nlt:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v1
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v3, v2
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %r.val = fcmp uge <2 x half> %a, %b
  %r.val.sext = sext <2 x i1> %r.val to <2 x i32>
  ret <2 x i32> %r.val.sext
}

declare half @llvm.fabs.f16(half) #1

attributes #0 = { nounwind }
attributes #1 = { nounwind readnone }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX12: {{.*}}