llvm/test/CodeGen/AMDGPU/clmul.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN:  llc  -mtriple=amdgpu6.01 < %s | FileCheck -check-prefixes=SI %s
; RUN:  llc  -mtriple=amdgpu8.02 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=VI %s
; RUN:  llc  -mtriple=amdgpu9.00 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX9 %s
; RUN:  llc  -mtriple=amdgpu10.10 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX10 %s
; RUN:  llc  -mtriple=amdgpu11.00 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX11 %s
; RUN:  llc  -mtriple=amdgpu12.00 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX12 %s
; RUN:  llc  -mtriple=amdgpu12.50 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX1250 %s
; RUN:  llc  -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefixes=EG %s

define amdgpu_kernel void @test_clmul_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {
; SI-LABEL: test_clmul_i32:
; SI:       ; %bb.0:
; SI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x9
; SI-NEXT:    s_mov_b32 s3, 0xf000
; SI-NEXT:    s_mov_b32 s10, 0
; SI-NEXT:    s_mov_b32 s11, s3
; SI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    s_mov_b64 s[8:9], s[6:7]
; SI-NEXT:    v_mov_b32_e32 v1, 0
; SI-NEXT:    buffer_load_dwordx2 v[0:1], v[0:1], s[8:11], 0 addr64
; SI-NEXT:    s_mov_b32 s2, -1
; SI-NEXT:    s_mov_b32 s0, s4
; SI-NEXT:    s_mov_b32 s1, s5
; SI-NEXT:    s_waitcnt vmcnt(0)
; SI-NEXT:    v_and_b32_e32 v2, 0x11111111, v1
; SI-NEXT:    v_and_b32_e32 v3, 0x22222222, v0
; SI-NEXT:    v_and_b32_e32 v4, 0x22222222, v1
; SI-NEXT:    v_and_b32_e32 v5, 0x11111111, v0
; SI-NEXT:    v_and_b32_e32 v6, 0x88888888, v1
; SI-NEXT:    v_and_b32_e32 v7, 0x44444444, v0
; SI-NEXT:    v_and_b32_e32 v1, 0x44444444, v1
; SI-NEXT:    v_and_b32_e32 v0, 0x88888888, v0
; SI-NEXT:    v_mul_lo_u32 v8, v3, v2
; SI-NEXT:    v_mul_lo_u32 v9, v5, v4
; SI-NEXT:    v_mul_lo_u32 v12, v3, v6
; SI-NEXT:    v_mul_lo_u32 v13, v5, v2
; SI-NEXT:    v_mul_lo_u32 v10, v7, v6
; SI-NEXT:    v_mul_lo_u32 v11, v0, v1
; SI-NEXT:    v_mul_lo_u32 v14, v7, v1
; SI-NEXT:    v_mul_lo_u32 v16, v3, v4
; SI-NEXT:    v_mul_lo_u32 v17, v5, v1
; SI-NEXT:    v_mul_lo_u32 v1, v3, v1
; SI-NEXT:    v_mul_lo_u32 v3, v5, v6
; SI-NEXT:    v_mul_lo_u32 v15, v0, v4
; SI-NEXT:    v_mul_lo_u32 v18, v7, v2
; SI-NEXT:    v_mul_lo_u32 v4, v7, v4
; SI-NEXT:    v_mul_lo_u32 v19, v0, v6
; SI-NEXT:    v_mul_lo_u32 v0, v0, v2
; SI-NEXT:    v_xor_b32_e32 v2, v9, v8
; SI-NEXT:    v_xor_b32_e32 v5, v13, v12
; SI-NEXT:    v_xor_b32_e32 v6, v17, v16
; SI-NEXT:    v_xor_b32_e32 v1, v3, v1
; SI-NEXT:    v_xor_b32_e32 v2, v2, v10
; SI-NEXT:    v_xor_b32_e32 v3, v5, v14
; SI-NEXT:    v_xor_b32_e32 v5, v6, v18
; SI-NEXT:    v_xor_b32_e32 v1, v1, v4
; SI-NEXT:    v_xor_b32_e32 v2, v2, v11
; SI-NEXT:    v_xor_b32_e32 v3, v3, v15
; SI-NEXT:    v_xor_b32_e32 v4, v5, v19
; SI-NEXT:    v_xor_b32_e32 v0, v1, v0
; SI-NEXT:    v_and_b32_e32 v1, 0x22222222, v2
; SI-NEXT:    v_and_b32_e32 v2, 0x11111111, v3
; SI-NEXT:    v_and_b32_e32 v3, 0x44444444, v4
; SI-NEXT:    v_or_b32_e32 v1, v2, v1
; SI-NEXT:    v_or_b32_e32 v1, v1, v3
; SI-NEXT:    v_and_b32_e32 v0, 0x88888888, v0
; SI-NEXT:    v_or_b32_e32 v0, v1, v0
; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT:    s_endpgm
;
; VI-LABEL: test_clmul_i32:
; VI:       ; %bb.0:
; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; VI-NEXT:    s_waitcnt lgkmcnt(0)
; VI-NEXT:    v_mov_b32_e32 v1, s3
; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v0
; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT:    flat_load_dwordx2 v[0:1], v[0:1]
; VI-NEXT:    s_mov_b32 s3, 0xf000
; VI-NEXT:    s_mov_b32 s2, -1
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    v_and_b32_e32 v2, 0x11111111, v1
; VI-NEXT:    v_and_b32_e32 v3, 0x22222222, v0
; VI-NEXT:    v_and_b32_e32 v4, 0x22222222, v1
; VI-NEXT:    v_and_b32_e32 v5, 0x11111111, v0
; VI-NEXT:    v_and_b32_e32 v6, 0x88888888, v1
; VI-NEXT:    v_and_b32_e32 v7, 0x44444444, v0
; VI-NEXT:    v_and_b32_e32 v1, 0x44444444, v1
; VI-NEXT:    v_and_b32_e32 v0, 0x88888888, v0
; VI-NEXT:    v_mul_lo_u32 v8, v3, v2
; VI-NEXT:    v_mul_lo_u32 v9, v5, v4
; VI-NEXT:    v_mul_lo_u32 v12, v3, v6
; VI-NEXT:    v_mul_lo_u32 v13, v5, v2
; VI-NEXT:    v_mul_lo_u32 v10, v7, v6
; VI-NEXT:    v_mul_lo_u32 v11, v0, v1
; VI-NEXT:    v_mul_lo_u32 v14, v7, v1
; VI-NEXT:    v_mul_lo_u32 v16, v3, v4
; VI-NEXT:    v_mul_lo_u32 v17, v5, v1
; VI-NEXT:    v_mul_lo_u32 v1, v3, v1
; VI-NEXT:    v_mul_lo_u32 v3, v5, v6
; VI-NEXT:    v_mul_lo_u32 v15, v0, v4
; VI-NEXT:    v_mul_lo_u32 v18, v7, v2
; VI-NEXT:    v_mul_lo_u32 v4, v7, v4
; VI-NEXT:    v_mul_lo_u32 v19, v0, v6
; VI-NEXT:    v_mul_lo_u32 v0, v0, v2
; VI-NEXT:    v_xor_b32_e32 v2, v9, v8
; VI-NEXT:    v_xor_b32_e32 v5, v13, v12
; VI-NEXT:    v_xor_b32_e32 v6, v17, v16
; VI-NEXT:    v_xor_b32_e32 v1, v3, v1
; VI-NEXT:    v_xor_b32_e32 v2, v2, v10
; VI-NEXT:    v_xor_b32_e32 v3, v5, v14
; VI-NEXT:    v_xor_b32_e32 v5, v6, v18
; VI-NEXT:    v_xor_b32_e32 v1, v1, v4
; VI-NEXT:    v_xor_b32_e32 v2, v2, v11
; VI-NEXT:    v_xor_b32_e32 v3, v3, v15
; VI-NEXT:    v_xor_b32_e32 v4, v5, v19
; VI-NEXT:    v_xor_b32_e32 v0, v1, v0
; VI-NEXT:    v_and_b32_e32 v1, 0x22222222, v2
; VI-NEXT:    v_and_b32_e32 v2, 0x11111111, v3
; VI-NEXT:    v_and_b32_e32 v3, 0x44444444, v4
; VI-NEXT:    v_or_b32_e32 v1, v2, v1
; VI-NEXT:    v_or_b32_e32 v1, v1, v3
; VI-NEXT:    v_and_b32_e32 v0, 0x88888888, v0
; VI-NEXT:    v_or_b32_e32 v0, v1, v0
; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT:    s_endpgm
;
; GFX9-LABEL: test_clmul_i32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT:    s_mov_b32 s4, 0x11111111
; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-NEXT:    global_load_dwordx2 v[0:1], v0, s[2:3]
; GFX9-NEXT:    s_mov_b32 s3, 0xf000
; GFX9-NEXT:    s_mov_b32 s2, -1
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    v_and_b32_e32 v2, 0x88888888, v1
; GFX9-NEXT:    v_and_b32_e32 v3, 0x22222222, v0
; GFX9-NEXT:    v_and_b32_e32 v4, 0x11111111, v1
; GFX9-NEXT:    v_and_b32_e32 v5, 0x11111111, v0
; GFX9-NEXT:    v_and_b32_e32 v6, 0x44444444, v1
; GFX9-NEXT:    v_and_b32_e32 v1, 0x22222222, v1
; GFX9-NEXT:    v_and_b32_e32 v7, 0x44444444, v0
; GFX9-NEXT:    v_and_b32_e32 v0, 0x88888888, v0
; GFX9-NEXT:    v_mul_lo_u32 v12, v3, v4
; GFX9-NEXT:    v_mul_lo_u32 v13, v5, v1
; GFX9-NEXT:    v_mul_lo_u32 v8, v3, v2
; GFX9-NEXT:    v_mul_lo_u32 v9, v5, v4
; GFX9-NEXT:    v_mul_lo_u32 v11, v0, v1
; GFX9-NEXT:    v_mul_lo_u32 v14, v7, v2
; GFX9-NEXT:    v_mul_lo_u32 v16, v3, v6
; GFX9-NEXT:    v_mul_lo_u32 v17, v5, v2
; GFX9-NEXT:    v_mul_lo_u32 v18, v7, v1
; GFX9-NEXT:    v_mul_lo_u32 v1, v3, v1
; GFX9-NEXT:    v_mul_lo_u32 v3, v5, v6
; GFX9-NEXT:    v_mul_lo_u32 v10, v7, v6
; GFX9-NEXT:    v_mul_lo_u32 v15, v0, v6
; GFX9-NEXT:    v_mul_lo_u32 v19, v0, v4
; GFX9-NEXT:    v_mul_lo_u32 v4, v7, v4
; GFX9-NEXT:    v_mul_lo_u32 v0, v0, v2
; GFX9-NEXT:    v_xor_b32_e32 v5, v13, v12
; GFX9-NEXT:    v_xor_b32_e32 v2, v9, v8
; GFX9-NEXT:    v_xor_b32_e32 v6, v17, v16
; GFX9-NEXT:    v_xor_b32_e32 v1, v3, v1
; GFX9-NEXT:    v_xor_b32_e32 v3, v5, v14
; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v10
; GFX9-NEXT:    v_xor_b32_e32 v5, v6, v18
; GFX9-NEXT:    v_xor_b32_e32 v1, v1, v4
; GFX9-NEXT:    v_xor_b32_e32 v3, v3, v15
; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v11
; GFX9-NEXT:    v_xor_b32_e32 v4, v5, v19
; GFX9-NEXT:    v_xor_b32_e32 v0, v1, v0
; GFX9-NEXT:    v_and_b32_e32 v1, 0x22222222, v3
; GFX9-NEXT:    v_and_b32_e32 v3, 0x88888888, v4
; GFX9-NEXT:    v_and_or_b32 v1, v2, s4, v1
; GFX9-NEXT:    v_and_b32_e32 v0, 0x44444444, v0
; GFX9-NEXT:    v_or3_b32 v0, v1, v0, v3
; GFX9-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; GFX9-NEXT:    s_endpgm
;
; GFX10-LABEL: test_clmul_i32:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
; GFX10-NEXT:    global_load_dwordx2 v[0:1], v0, s[2:3]
; GFX10-NEXT:    s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT:    s_mov_b32 s3, 0x31016000
; GFX10-NEXT:    s_mov_b32 s2, -1
; GFX10-NEXT:    s_waitcnt vmcnt(0)
; GFX10-NEXT:    v_and_b32_e32 v3, 0x22222222, v0
; GFX10-NEXT:    v_and_b32_e32 v4, 0x11111111, v1
; GFX10-NEXT:    v_and_b32_e32 v5, 0x11111111, v0
; GFX10-NEXT:    v_and_b32_e32 v6, 0x22222222, v1
; GFX10-NEXT:    v_and_b32_e32 v2, 0x88888888, v1
; GFX10-NEXT:    v_and_b32_e32 v7, 0x88888888, v0
; GFX10-NEXT:    v_and_b32_e32 v1, 0x44444444, v1
; GFX10-NEXT:    v_and_b32_e32 v0, 0x44444444, v0
; GFX10-NEXT:    v_mul_lo_u32 v12, v3, v4
; GFX10-NEXT:    v_mul_lo_u32 v13, v5, v6
; GFX10-NEXT:    v_mul_lo_u32 v8, v3, v2
; GFX10-NEXT:    v_mul_lo_u32 v9, v5, v4
; GFX10-NEXT:    v_mul_lo_u32 v11, v0, v1
; GFX10-NEXT:    v_mul_lo_u32 v14, v7, v1
; GFX10-NEXT:    v_mul_lo_u32 v15, v0, v2
; GFX10-NEXT:    v_mul_lo_u32 v16, v3, v1
; GFX10-NEXT:    v_mul_lo_u32 v17, v5, v2
; GFX10-NEXT:    v_mul_lo_u32 v3, v3, v6
; GFX10-NEXT:    v_mul_lo_u32 v1, v5, v1
; GFX10-NEXT:    v_mul_lo_u32 v10, v7, v6
; GFX10-NEXT:    v_mul_lo_u32 v5, v0, v6
; GFX10-NEXT:    v_xor_b32_e32 v6, v13, v12
; GFX10-NEXT:    v_mul_lo_u32 v18, v7, v4
; GFX10-NEXT:    v_mul_lo_u32 v2, v7, v2
; GFX10-NEXT:    v_mul_lo_u32 v0, v0, v4
; GFX10-NEXT:    v_xor_b32_e32 v4, v9, v8
; GFX10-NEXT:    v_xor_b32_e32 v7, v17, v16
; GFX10-NEXT:    v_xor3_b32 v6, v6, v15, v14
; GFX10-NEXT:    v_xor_b32_e32 v1, v1, v3
; GFX10-NEXT:    v_xor3_b32 v3, v4, v11, v10
; GFX10-NEXT:    v_xor3_b32 v4, v7, v5, v18
; GFX10-NEXT:    v_and_b32_e32 v5, 0x22222222, v6
; GFX10-NEXT:    v_xor3_b32 v0, v1, v0, v2
; GFX10-NEXT:    v_and_b32_e32 v1, 0x88888888, v4
; GFX10-NEXT:    v_and_or_b32 v2, v3, 0x11111111, v5
; GFX10-NEXT:    v_and_b32_e32 v0, 0x44444444, v0
; GFX10-NEXT:    v_or3_b32 v0, v2, v0, v1
; GFX10-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; GFX10-NEXT:    s_endpgm
;
; GFX11-LABEL: test_clmul_i32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-NEXT:    global_load_b64 v[0:1], v0, s[2:3]
; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
; GFX11-NEXT:    s_mov_b32 s2, -1
; GFX11-NEXT:    s_waitcnt vmcnt(0)
; GFX11-NEXT:    v_and_b32_e32 v3, 0x22222222, v0
; GFX11-NEXT:    v_and_b32_e32 v4, 0x11111111, v1
; GFX11-NEXT:    v_and_b32_e32 v5, 0x11111111, v0
; GFX11-NEXT:    v_and_b32_e32 v6, 0x22222222, v1
; GFX11-NEXT:    v_and_b32_e32 v2, 0x88888888, v1
; GFX11-NEXT:    v_and_b32_e32 v7, 0x88888888, v0
; GFX11-NEXT:    v_and_b32_e32 v1, 0x44444444, v1
; GFX11-NEXT:    v_and_b32_e32 v0, 0x44444444, v0
; GFX11-NEXT:    v_mul_lo_u32 v12, v3, v4
; GFX11-NEXT:    v_mul_lo_u32 v13, v5, v6
; GFX11-NEXT:    v_mul_lo_u32 v8, v3, v2
; GFX11-NEXT:    v_mul_lo_u32 v9, v5, v4
; GFX11-NEXT:    v_mul_lo_u32 v11, v0, v1
; GFX11-NEXT:    v_mul_lo_u32 v14, v7, v1
; GFX11-NEXT:    v_mul_lo_u32 v15, v0, v2
; GFX11-NEXT:    v_mul_lo_u32 v16, v3, v1
; GFX11-NEXT:    v_mul_lo_u32 v17, v5, v2
; GFX11-NEXT:    v_mul_lo_u32 v3, v3, v6
; GFX11-NEXT:    v_mul_lo_u32 v1, v5, v1
; GFX11-NEXT:    v_mul_lo_u32 v10, v7, v6
; GFX11-NEXT:    v_mul_lo_u32 v5, v0, v6
; GFX11-NEXT:    v_xor_b32_e32 v6, v13, v12
; GFX11-NEXT:    v_mul_lo_u32 v18, v7, v4
; GFX11-NEXT:    v_mul_lo_u32 v2, v7, v2
; GFX11-NEXT:    v_mul_lo_u32 v0, v0, v4
; GFX11-NEXT:    v_xor_b32_e32 v4, v9, v8
; GFX11-NEXT:    v_xor_b32_e32 v7, v17, v16
; GFX11-NEXT:    v_xor3_b32 v6, v6, v15, v14
; GFX11-NEXT:    v_xor_b32_e32 v1, v1, v3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_xor3_b32 v3, v4, v11, v10
; GFX11-NEXT:    v_xor3_b32 v4, v7, v5, v18
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_and_b32_e32 v5, 0x22222222, v6
; GFX11-NEXT:    v_xor3_b32 v0, v1, v0, v2
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_and_b32_e32 v1, 0x88888888, v4
; GFX11-NEXT:    v_and_or_b32 v2, v3, 0x11111111, v5
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_and_b32_e32 v0, 0x44444444, v0
; GFX11-NEXT:    v_or3_b32 v0, v2, v0, v1
; GFX11-NEXT:    buffer_store_b32 v0, off, s[0:3], 0
; GFX11-NEXT:    s_endpgm
;
; GFX12-LABEL: test_clmul_i32:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    global_load_b64 v[0:1], v0, s[2:3]
; GFX12-NEXT:    s_mov_b32 s3, 0x31016000
; GFX12-NEXT:    s_mov_b32 s2, -1
; GFX12-NEXT:    s_wait_loadcnt 0x0
; GFX12-NEXT:    v_and_b32_e32 v3, 0x22222222, v0
; GFX12-NEXT:    v_and_b32_e32 v4, 0x11111111, v1
; GFX12-NEXT:    v_and_b32_e32 v5, 0x11111111, v0
; GFX12-NEXT:    v_and_b32_e32 v6, 0x22222222, v1
; GFX12-NEXT:    v_and_b32_e32 v2, 0x88888888, v1
; GFX12-NEXT:    v_and_b32_e32 v7, 0x88888888, v0
; GFX12-NEXT:    v_and_b32_e32 v1, 0x44444444, v1
; GFX12-NEXT:    v_and_b32_e32 v0, 0x44444444, v0
; GFX12-NEXT:    v_mul_lo_u32 v12, v3, v4
; GFX12-NEXT:    v_mul_lo_u32 v13, v5, v6
; GFX12-NEXT:    v_mul_lo_u32 v8, v3, v2
; GFX12-NEXT:    v_mul_lo_u32 v9, v5, v4
; GFX12-NEXT:    v_mul_lo_u32 v11, v0, v1
; GFX12-NEXT:    v_mul_lo_u32 v14, v7, v1
; GFX12-NEXT:    v_mul_lo_u32 v15, v0, v2
; GFX12-NEXT:    v_mul_lo_u32 v16, v3, v1
; GFX12-NEXT:    v_mul_lo_u32 v17, v5, v2
; GFX12-NEXT:    v_mul_lo_u32 v3, v3, v6
; GFX12-NEXT:    v_mul_lo_u32 v1, v5, v1
; GFX12-NEXT:    v_mul_lo_u32 v10, v7, v6
; GFX12-NEXT:    v_mul_lo_u32 v5, v0, v6
; GFX12-NEXT:    v_xor_b32_e32 v6, v13, v12
; GFX12-NEXT:    v_mul_lo_u32 v18, v7, v4
; GFX12-NEXT:    v_mul_lo_u32 v2, v7, v2
; GFX12-NEXT:    v_mul_lo_u32 v0, v0, v4
; GFX12-NEXT:    v_xor_b32_e32 v4, v9, v8
; GFX12-NEXT:    v_xor_b32_e32 v7, v17, v16
; GFX12-NEXT:    v_xor3_b32 v6, v6, v15, v14
; GFX12-NEXT:    v_xor_b32_e32 v1, v1, v3
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-NEXT:    v_xor3_b32 v3, v4, v11, v10
; GFX12-NEXT:    v_xor3_b32 v4, v7, v5, v18
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-NEXT:    v_and_b32_e32 v5, 0x22222222, v6
; GFX12-NEXT:    v_xor3_b32 v0, v1, v0, v2
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-NEXT:    v_and_b32_e32 v1, 0x88888888, v4
; GFX12-NEXT:    v_and_or_b32 v2, v3, 0x11111111, v5
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT:    v_and_b32_e32 v0, 0x44444444, v0
; GFX12-NEXT:    v_or3_b32 v0, v2, v0, v1
; GFX12-NEXT:    buffer_store_b32 v0, off, s[0:3], null
; GFX12-NEXT:    s_endpgm
;
; GFX1250-LABEL: test_clmul_i32:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-NEXT:    v_nop
; GFX1250-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
; GFX1250-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    global_load_b64 v[0:1], v0, s[2:3]
; GFX1250-NEXT:    s_wait_xcnt 0x0
; GFX1250-NEXT:    s_mov_b32 s3, 0x31016000
; GFX1250-NEXT:    s_mov_b32 s2, -1
; GFX1250-NEXT:    s_wait_loadcnt 0x0
; GFX1250-NEXT:    v_and_b32_e32 v2, 0x22222222, v1
; GFX1250-NEXT:    v_and_b32_e32 v3, 0x44444444, v0
; GFX1250-NEXT:    v_and_b32_e32 v4, 0x44444444, v1
; GFX1250-NEXT:    v_and_b32_e32 v5, 0x22222222, v0
; GFX1250-NEXT:    v_and_b32_e32 v6, 0x88888888, v1
; GFX1250-NEXT:    v_and_b32_e32 v7, 0x11111111, v0
; GFX1250-NEXT:    v_and_b32_e32 v1, 0x11111111, v1
; GFX1250-NEXT:    v_and_b32_e32 v8, 0x88888888, v0
; GFX1250-NEXT:    v_mul_lo_u32 v9, v3, v2
; GFX1250-NEXT:    v_mul_lo_u32 v13, v3, v6
; GFX1250-NEXT:    v_mul_lo_u32 v15, v7, v2
; GFX1250-NEXT:    v_mul_lo_u32 v14, v5, v1
; GFX1250-NEXT:    v_mul_lo_u32 v16, v5, v6
; GFX1250-NEXT:    v_mul_lo_u32 v17, v7, v1
; GFX1250-NEXT:    v_mul_lo_u32 v10, v5, v4
; GFX1250-NEXT:    v_mul_lo_u32 v11, v7, v6
; GFX1250-NEXT:    v_mul_lo_u32 v12, v3, v1
; GFX1250-NEXT:    v_mul_lo_u32 v5, v5, v2
; GFX1250-NEXT:    v_mul_lo_u32 v7, v7, v4
; GFX1250-NEXT:    v_mul_lo_u32 v18, v8, v4
; GFX1250-NEXT:    v_mul_lo_u32 v2, v8, v2
; GFX1250-NEXT:    v_mul_lo_u32 v3, v3, v4
; GFX1250-NEXT:    v_xor3_b32 v4, v15, v14, v13
; GFX1250-NEXT:    v_xor_b32_e32 v13, v17, v16
; GFX1250-NEXT:    v_mul_lo_u32 v1, v8, v1
; GFX1250-NEXT:    v_mul_lo_u32 v6, v8, v6
; GFX1250-NEXT:    v_xor3_b32 v8, v11, v10, v9
; GFX1250-NEXT:    v_xor3_b32 v5, v7, v5, v12
; GFX1250-NEXT:    v_bitop3_b32 v4, v4, 0x22222222, v18 bitop3:0x48
; GFX1250-NEXT:    v_xor3_b32 v2, v13, v3, v2
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1250-NEXT:    v_bitop3_b32 v1, v8, 0x88888888, v1 bitop3:0x48
; GFX1250-NEXT:    v_bitop3_b32 v3, v5, 0x44444444, v6 bitop3:0x48
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-NEXT:    v_and_or_b32 v2, v2, 0x11111111, v4
; GFX1250-NEXT:    v_or3_b32 v1, v2, v3, v1
; GFX1250-NEXT:    buffer_store_b32 v1, off, s[0:3], null
; GFX1250-NEXT:    s_endpgm
;
; EG-LABEL: test_clmul_i32:
; EG:       ; %bb.0:
; EG-NEXT:    ALU 2, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT:    TEX 0 @6
; EG-NEXT:    ALU 53, @11, KC0[CB0:0-32], KC1[]
; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
; EG-NEXT:    CF_END
; EG-NEXT:    PAD
; EG-NEXT:    Fetch clause starting at 6:
; EG-NEXT:     VTX_READ_64 T0.XY, T0.X, 0, #1
; EG-NEXT:    ALU clause starting at 8:
; EG-NEXT:     LSHL * T0.W, T0.X, literal.x,
; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
; EG-NEXT:     ADD_INT * T0.X, KC0[2].Z, PV.W,
; EG-NEXT:    ALU clause starting at 11:
; EG-NEXT:     AND_INT T0.W, T0.X, literal.x,
; EG-NEXT:     AND_INT * T1.W, T0.Y, literal.y,
; EG-NEXT:    1145324612(7.850667e+02), 572662306(2.197316e-18)
; EG-NEXT:     AND_INT T2.W, T0.Y, literal.x,
; EG-NEXT:     MULLO_INT * T0.Z, PV.W, PS,
; EG-NEXT:    286331153(1.144374e-28), 0(0.000000e+00)
; EG-NEXT:     AND_INT T3.W, T0.X, literal.x,
; EG-NEXT:     MULLO_INT * T1.X, T0.W, PV.W,
; EG-NEXT:    -2004318072(-8.217301e-34), 0(0.000000e+00)
; EG-NEXT:     AND_INT T4.W, T0.Y, literal.x,
; EG-NEXT:     MULLO_INT * T1.Y, PV.W, T1.W,
; EG-NEXT:    1145324612(7.850667e+02), 0(0.000000e+00)
; EG-NEXT:     AND_INT T1.Z, T0.Y, literal.x,
; EG-NEXT:     AND_INT T5.W, T0.X, literal.y,
; EG-NEXT:     MULLO_INT * T0.Y, T3.W, PV.W,
; EG-NEXT:    -2004318072(-8.217301e-34), 286331153(1.144374e-28)
; EG-NEXT:     MULLO_INT * T2.X, PV.W, PV.Z,
; EG-NEXT:     MULLO_INT * T2.Y, T0.W, T1.Z,
; EG-NEXT:     MULLO_INT * T0.W, T0.W, T4.W,
; EG-NEXT:     MULLO_INT * T2.Z, T5.W, T4.W,
; EG-NEXT:     AND_INT T6.W, T0.X, literal.x,
; EG-NEXT:     MULLO_INT * T0.X, T5.W, T2.W,
; EG-NEXT:    572662306(2.197316e-18), 0(0.000000e+00)
; EG-NEXT:     MULLO_INT * T3.X, PV.W, T1.Z,
; EG-NEXT:     MULLO_INT * T3.Y, T5.W, T1.W,
; EG-NEXT:     MULLO_INT * T3.Z, T6.W, T2.W,
; EG-NEXT:     XOR_INT T3.Z, T3.Y, PS,
; EG-NEXT:     XOR_INT T5.W, T0.X, T3.X,
; EG-NEXT:     MULLO_INT * T0.X, T6.W, T1.W,
; EG-NEXT:     XOR_INT T3.Y, T2.Z, PS,
; EG-NEXT:     XOR_INT T2.Z, PV.W, T0.W, BS:VEC_102/SCL_221
; EG-NEXT:     XOR_INT T0.W, PV.Z, T2.Y,
; EG-NEXT:     MULLO_INT * T0.X, T6.W, T4.W,
; EG-NEXT:     XOR_INT T0.X, T2.X, PS,
; EG-NEXT:     XOR_INT T0.Y, PV.W, T0.Y,
; EG-NEXT:     XOR_INT T2.Z, PV.Z, T1.Y, BS:VEC_021/SCL_122
; EG-NEXT:     XOR_INT T0.W, PV.Y, T1.X,
; EG-NEXT:     MULLO_INT * T1.X, T3.W, T1.Z,
; EG-NEXT:     XOR_INT T1.X, PV.W, PS,
; EG-NEXT:     AND_INT T1.Y, PV.Z, literal.x,
; EG-NEXT:     AND_INT T1.Z, PV.Y, literal.y,
; EG-NEXT:     XOR_INT T0.W, PV.X, T0.Z,
; EG-NEXT:     MULLO_INT * T0.X, T3.W, T2.W,
; EG-NEXT:    286331153(1.144374e-28), 572662306(2.197316e-18)
; EG-NEXT:     XOR_INT T0.Z, PV.W, PS,
; EG-NEXT:     OR_INT T0.W, PV.Y, PV.Z,
; EG-NEXT:     AND_INT * T1.W, PV.X, literal.x,
; EG-NEXT:    1145324612(7.850667e+02), 0(0.000000e+00)
; EG-NEXT:     OR_INT T0.W, PV.W, PS,
; EG-NEXT:     AND_INT * T1.W, PV.Z, literal.x,
; EG-NEXT:    -2004318072(-8.217301e-34), 0(0.000000e+00)
; EG-NEXT:     OR_INT T0.X, PV.W, PS,
; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
  %tid = call i32 @llvm.amdgcn.workitem.id.x()
  %in.tid = getelementptr inbounds i32, ptr addrspace(1) %in, i32 %tid
  %b_ptr = getelementptr i32, ptr addrspace(1) %in.tid, i32 1
  %a = load i32, ptr addrspace(1) %in.tid
  %b = load i32, ptr addrspace(1) %b_ptr
  %res = call i32 @llvm.clmul.i32(i32 %a, i32 %b)
  store i32 %res, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @test_clmulr_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {
; SI-LABEL: test_clmulr_i32:
; SI:       ; %bb.0:
; SI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x9
; SI-NEXT:    s_mov_b32 s3, 0xf000
; SI-NEXT:    s_mov_b32 s10, 0
; SI-NEXT:    s_mov_b32 s11, s3
; SI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    s_mov_b64 s[8:9], s[6:7]
; SI-NEXT:    v_mov_b32_e32 v1, 0
; SI-NEXT:    buffer_load_dwordx2 v[2:3], v[0:1], s[8:11], 0 addr64
; SI-NEXT:    s_mov_b32 s2, -1
; SI-NEXT:    s_mov_b32 s0, s4
; SI-NEXT:    s_mov_b32 s1, s5
; SI-NEXT:    s_waitcnt vmcnt(0)
; SI-NEXT:    v_bfe_i32 v4, v3, 0, 1
; SI-NEXT:    v_mov_b32_e32 v0, v2
; SI-NEXT:    v_and_b32_e32 v2, v4, v2
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 1
; SI-NEXT:    v_bfe_i32 v6, v3, 1, 1
; SI-NEXT:    v_and_b32_e32 v4, v6, v4
; SI-NEXT:    v_and_b32_e32 v7, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 2
; SI-NEXT:    v_bfe_i32 v6, v3, 2, 1
; SI-NEXT:    v_and_b32_e32 v5, v6, v5
; SI-NEXT:    v_and_b32_e32 v4, v6, v4
; SI-NEXT:    v_xor_b32_e32 v6, v7, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 3
; SI-NEXT:    v_bfe_i32 v7, v3, 3, 1
; SI-NEXT:    v_and_b32_e32 v5, v7, v5
; SI-NEXT:    v_and_b32_e32 v4, v7, v4
; SI-NEXT:    v_xor_b32_e32 v6, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 4
; SI-NEXT:    v_bfe_i32 v7, v3, 4, 1
; SI-NEXT:    v_and_b32_e32 v5, v7, v5
; SI-NEXT:    v_and_b32_e32 v4, v7, v4
; SI-NEXT:    v_xor_b32_e32 v6, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 5
; SI-NEXT:    v_bfe_i32 v7, v3, 5, 1
; SI-NEXT:    v_and_b32_e32 v5, v7, v5
; SI-NEXT:    v_and_b32_e32 v4, v7, v4
; SI-NEXT:    v_xor_b32_e32 v6, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 6
; SI-NEXT:    v_bfe_i32 v7, v3, 6, 1
; SI-NEXT:    v_and_b32_e32 v5, v7, v5
; SI-NEXT:    v_and_b32_e32 v4, v7, v4
; SI-NEXT:    v_xor_b32_e32 v6, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 7
; SI-NEXT:    v_bfe_i32 v7, v3, 7, 1
; SI-NEXT:    v_and_b32_e32 v5, v7, v5
; SI-NEXT:    v_and_b32_e32 v4, v7, v4
; SI-NEXT:    v_xor_b32_e32 v6, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 8
; SI-NEXT:    v_bfe_i32 v7, v3, 8, 1
; SI-NEXT:    v_and_b32_e32 v5, v7, v5
; SI-NEXT:    v_and_b32_e32 v4, v7, v4
; SI-NEXT:    v_xor_b32_e32 v6, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 9
; SI-NEXT:    v_bfe_i32 v7, v3, 9, 1
; SI-NEXT:    v_and_b32_e32 v5, v7, v5
; SI-NEXT:    v_and_b32_e32 v4, v7, v4
; SI-NEXT:    v_xor_b32_e32 v6, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 10
; SI-NEXT:    v_bfe_i32 v7, v3, 10, 1
; SI-NEXT:    v_and_b32_e32 v5, v7, v5
; SI-NEXT:    v_and_b32_e32 v4, v7, v4
; SI-NEXT:    v_xor_b32_e32 v6, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 11
; SI-NEXT:    v_bfe_i32 v7, v3, 11, 1
; SI-NEXT:    v_and_b32_e32 v5, v7, v5
; SI-NEXT:    v_and_b32_e32 v4, v7, v4
; SI-NEXT:    v_xor_b32_e32 v6, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 12
; SI-NEXT:    v_bfe_i32 v7, v3, 12, 1
; SI-NEXT:    v_and_b32_e32 v5, v7, v5
; SI-NEXT:    v_and_b32_e32 v4, v7, v4
; SI-NEXT:    v_xor_b32_e32 v6, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 13
; SI-NEXT:    v_bfe_i32 v7, v3, 13, 1
; SI-NEXT:    v_and_b32_e32 v5, v7, v5
; SI-NEXT:    v_and_b32_e32 v4, v7, v4
; SI-NEXT:    v_xor_b32_e32 v6, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 14
; SI-NEXT:    v_bfe_i32 v7, v3, 14, 1
; SI-NEXT:    v_and_b32_e32 v5, v7, v5
; SI-NEXT:    v_and_b32_e32 v4, v7, v4
; SI-NEXT:    v_xor_b32_e32 v6, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 15
; SI-NEXT:    v_bfe_i32 v7, v3, 15, 1
; SI-NEXT:    v_and_b32_e32 v5, v7, v5
; SI-NEXT:    v_and_b32_e32 v4, v7, v4
; SI-NEXT:    v_xor_b32_e32 v6, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 16
; SI-NEXT:    v_bfe_i32 v7, v3, 16, 1
; SI-NEXT:    v_and_b32_e32 v5, v7, v5
; SI-NEXT:    v_and_b32_e32 v4, v7, v4
; SI-NEXT:    v_xor_b32_e32 v6, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 17
; SI-NEXT:    v_bfe_i32 v7, v3, 17, 1
; SI-NEXT:    v_and_b32_e32 v5, v7, v5
; SI-NEXT:    v_and_b32_e32 v4, v7, v4
; SI-NEXT:    v_xor_b32_e32 v6, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 18
; SI-NEXT:    v_bfe_i32 v7, v3, 18, 1
; SI-NEXT:    v_and_b32_e32 v5, v7, v5
; SI-NEXT:    v_and_b32_e32 v4, v7, v4
; SI-NEXT:    v_xor_b32_e32 v6, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 19
; SI-NEXT:    v_bfe_i32 v7, v3, 19, 1
; SI-NEXT:    v_and_b32_e32 v5, v7, v5
; SI-NEXT:    v_and_b32_e32 v4, v7, v4
; SI-NEXT:    v_xor_b32_e32 v6, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 20
; SI-NEXT:    v_bfe_i32 v7, v3, 20, 1
; SI-NEXT:    v_and_b32_e32 v5, v7, v5
; SI-NEXT:    v_and_b32_e32 v4, v7, v4
; SI-NEXT:    v_xor_b32_e32 v6, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 21
; SI-NEXT:    v_bfe_i32 v7, v3, 21, 1
; SI-NEXT:    v_and_b32_e32 v5, v7, v5
; SI-NEXT:    v_and_b32_e32 v4, v7, v4
; SI-NEXT:    v_xor_b32_e32 v6, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 22
; SI-NEXT:    v_bfe_i32 v7, v3, 22, 1
; SI-NEXT:    v_and_b32_e32 v5, v7, v5
; SI-NEXT:    v_and_b32_e32 v4, v7, v4
; SI-NEXT:    v_xor_b32_e32 v6, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 23
; SI-NEXT:    v_bfe_i32 v7, v3, 23, 1
; SI-NEXT:    v_and_b32_e32 v5, v7, v5
; SI-NEXT:    v_and_b32_e32 v4, v7, v4
; SI-NEXT:    v_xor_b32_e32 v6, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 24
; SI-NEXT:    v_bfe_i32 v7, v3, 24, 1
; SI-NEXT:    v_and_b32_e32 v5, v7, v5
; SI-NEXT:    v_and_b32_e32 v4, v7, v4
; SI-NEXT:    v_xor_b32_e32 v6, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 25
; SI-NEXT:    v_bfe_i32 v7, v3, 25, 1
; SI-NEXT:    v_and_b32_e32 v5, v7, v5
; SI-NEXT:    v_and_b32_e32 v4, v7, v4
; SI-NEXT:    v_xor_b32_e32 v6, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 26
; SI-NEXT:    v_bfe_i32 v7, v3, 26, 1
; SI-NEXT:    v_and_b32_e32 v5, v7, v5
; SI-NEXT:    v_and_b32_e32 v4, v7, v4
; SI-NEXT:    v_xor_b32_e32 v6, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 27
; SI-NEXT:    v_bfe_i32 v7, v3, 27, 1
; SI-NEXT:    v_and_b32_e32 v5, v7, v5
; SI-NEXT:    v_and_b32_e32 v4, v7, v4
; SI-NEXT:    v_xor_b32_e32 v6, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 28
; SI-NEXT:    v_bfe_i32 v7, v3, 28, 1
; SI-NEXT:    v_and_b32_e32 v5, v7, v5
; SI-NEXT:    v_and_b32_e32 v4, v7, v4
; SI-NEXT:    v_xor_b32_e32 v6, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 29
; SI-NEXT:    v_bfe_i32 v7, v3, 29, 1
; SI-NEXT:    v_and_b32_e32 v5, v7, v5
; SI-NEXT:    v_and_b32_e32 v4, v7, v4
; SI-NEXT:    v_xor_b32_e32 v6, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 30
; SI-NEXT:    v_bfe_i32 v7, v3, 30, 1
; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], 31
; SI-NEXT:    v_and_b32_e32 v5, v7, v5
; SI-NEXT:    v_and_b32_e32 v4, v7, v4
; SI-NEXT:    v_ashrrev_i32_e32 v3, 31, v3
; SI-NEXT:    v_xor_b32_e32 v5, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_and_b32_e32 v1, v3, v1
; SI-NEXT:    v_and_b32_e32 v0, v3, v0
; SI-NEXT:    v_xor_b32_e32 v1, v5, v1
; SI-NEXT:    v_xor_b32_e32 v0, v2, v0
; SI-NEXT:    v_alignbit_b32 v0, v1, v0, 31
; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT:    s_endpgm
;
; VI-LABEL: test_clmulr_i32:
; VI:       ; %bb.0:
; VI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x24
; VI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; VI-NEXT:    v_mov_b32_e32 v1, 0
; VI-NEXT:    s_mov_b32 s3, 0xf000
; VI-NEXT:    s_mov_b32 s2, -1
; VI-NEXT:    s_waitcnt lgkmcnt(0)
; VI-NEXT:    v_add_u32_e32 v2, vcc, s6, v0
; VI-NEXT:    v_mov_b32_e32 v0, s7
; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v0, vcc
; VI-NEXT:    flat_load_dwordx2 v[2:3], v[2:3]
; VI-NEXT:    s_mov_b32 s0, s4
; VI-NEXT:    s_mov_b32 s1, s5
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    v_bfe_i32 v4, v3, 0, 1
; VI-NEXT:    v_mov_b32_e32 v0, v2
; VI-NEXT:    v_and_b32_e32 v2, v4, v2
; VI-NEXT:    v_lshlrev_b64 v[4:5], 1, v[0:1]
; VI-NEXT:    v_bfe_i32 v6, v3, 1, 1
; VI-NEXT:    v_and_b32_e32 v4, v6, v4
; VI-NEXT:    v_and_b32_e32 v7, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 2, v[0:1]
; VI-NEXT:    v_bfe_i32 v6, v3, 2, 1
; VI-NEXT:    v_and_b32_e32 v5, v6, v5
; VI-NEXT:    v_and_b32_e32 v4, v6, v4
; VI-NEXT:    v_xor_b32_e32 v6, v7, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 3, v[0:1]
; VI-NEXT:    v_bfe_i32 v7, v3, 3, 1
; VI-NEXT:    v_and_b32_e32 v5, v7, v5
; VI-NEXT:    v_and_b32_e32 v4, v7, v4
; VI-NEXT:    v_xor_b32_e32 v6, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 4, v[0:1]
; VI-NEXT:    v_bfe_i32 v7, v3, 4, 1
; VI-NEXT:    v_and_b32_e32 v5, v7, v5
; VI-NEXT:    v_and_b32_e32 v4, v7, v4
; VI-NEXT:    v_xor_b32_e32 v6, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 5, v[0:1]
; VI-NEXT:    v_bfe_i32 v7, v3, 5, 1
; VI-NEXT:    v_and_b32_e32 v5, v7, v5
; VI-NEXT:    v_and_b32_e32 v4, v7, v4
; VI-NEXT:    v_xor_b32_e32 v6, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 6, v[0:1]
; VI-NEXT:    v_bfe_i32 v7, v3, 6, 1
; VI-NEXT:    v_and_b32_e32 v5, v7, v5
; VI-NEXT:    v_and_b32_e32 v4, v7, v4
; VI-NEXT:    v_xor_b32_e32 v6, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 7, v[0:1]
; VI-NEXT:    v_bfe_i32 v7, v3, 7, 1
; VI-NEXT:    v_and_b32_e32 v5, v7, v5
; VI-NEXT:    v_and_b32_e32 v4, v7, v4
; VI-NEXT:    v_xor_b32_e32 v6, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 8, v[0:1]
; VI-NEXT:    v_bfe_i32 v7, v3, 8, 1
; VI-NEXT:    v_and_b32_e32 v5, v7, v5
; VI-NEXT:    v_and_b32_e32 v4, v7, v4
; VI-NEXT:    v_xor_b32_e32 v6, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 9, v[0:1]
; VI-NEXT:    v_bfe_i32 v7, v3, 9, 1
; VI-NEXT:    v_and_b32_e32 v5, v7, v5
; VI-NEXT:    v_and_b32_e32 v4, v7, v4
; VI-NEXT:    v_xor_b32_e32 v6, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 10, v[0:1]
; VI-NEXT:    v_bfe_i32 v7, v3, 10, 1
; VI-NEXT:    v_and_b32_e32 v5, v7, v5
; VI-NEXT:    v_and_b32_e32 v4, v7, v4
; VI-NEXT:    v_xor_b32_e32 v6, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 11, v[0:1]
; VI-NEXT:    v_bfe_i32 v7, v3, 11, 1
; VI-NEXT:    v_and_b32_e32 v5, v7, v5
; VI-NEXT:    v_and_b32_e32 v4, v7, v4
; VI-NEXT:    v_xor_b32_e32 v6, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 12, v[0:1]
; VI-NEXT:    v_bfe_i32 v7, v3, 12, 1
; VI-NEXT:    v_and_b32_e32 v5, v7, v5
; VI-NEXT:    v_and_b32_e32 v4, v7, v4
; VI-NEXT:    v_xor_b32_e32 v6, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 13, v[0:1]
; VI-NEXT:    v_bfe_i32 v7, v3, 13, 1
; VI-NEXT:    v_and_b32_e32 v5, v7, v5
; VI-NEXT:    v_and_b32_e32 v4, v7, v4
; VI-NEXT:    v_xor_b32_e32 v6, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 14, v[0:1]
; VI-NEXT:    v_bfe_i32 v7, v3, 14, 1
; VI-NEXT:    v_and_b32_e32 v5, v7, v5
; VI-NEXT:    v_and_b32_e32 v4, v7, v4
; VI-NEXT:    v_xor_b32_e32 v6, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 15, v[0:1]
; VI-NEXT:    v_bfe_i32 v7, v3, 15, 1
; VI-NEXT:    v_and_b32_e32 v5, v7, v5
; VI-NEXT:    v_and_b32_e32 v4, v7, v4
; VI-NEXT:    v_xor_b32_e32 v6, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 16, v[0:1]
; VI-NEXT:    v_bfe_i32 v7, v3, 16, 1
; VI-NEXT:    v_and_b32_e32 v5, v7, v5
; VI-NEXT:    v_and_b32_e32 v4, v7, v4
; VI-NEXT:    v_xor_b32_e32 v6, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 17, v[0:1]
; VI-NEXT:    v_bfe_i32 v7, v3, 17, 1
; VI-NEXT:    v_and_b32_e32 v5, v7, v5
; VI-NEXT:    v_and_b32_e32 v4, v7, v4
; VI-NEXT:    v_xor_b32_e32 v6, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 18, v[0:1]
; VI-NEXT:    v_bfe_i32 v7, v3, 18, 1
; VI-NEXT:    v_and_b32_e32 v5, v7, v5
; VI-NEXT:    v_and_b32_e32 v4, v7, v4
; VI-NEXT:    v_xor_b32_e32 v6, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 19, v[0:1]
; VI-NEXT:    v_bfe_i32 v7, v3, 19, 1
; VI-NEXT:    v_and_b32_e32 v5, v7, v5
; VI-NEXT:    v_and_b32_e32 v4, v7, v4
; VI-NEXT:    v_xor_b32_e32 v6, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 20, v[0:1]
; VI-NEXT:    v_bfe_i32 v7, v3, 20, 1
; VI-NEXT:    v_and_b32_e32 v5, v7, v5
; VI-NEXT:    v_and_b32_e32 v4, v7, v4
; VI-NEXT:    v_xor_b32_e32 v6, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 21, v[0:1]
; VI-NEXT:    v_bfe_i32 v7, v3, 21, 1
; VI-NEXT:    v_and_b32_e32 v5, v7, v5
; VI-NEXT:    v_and_b32_e32 v4, v7, v4
; VI-NEXT:    v_xor_b32_e32 v6, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 22, v[0:1]
; VI-NEXT:    v_bfe_i32 v7, v3, 22, 1
; VI-NEXT:    v_and_b32_e32 v5, v7, v5
; VI-NEXT:    v_and_b32_e32 v4, v7, v4
; VI-NEXT:    v_xor_b32_e32 v6, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 23, v[0:1]
; VI-NEXT:    v_bfe_i32 v7, v3, 23, 1
; VI-NEXT:    v_and_b32_e32 v5, v7, v5
; VI-NEXT:    v_and_b32_e32 v4, v7, v4
; VI-NEXT:    v_xor_b32_e32 v6, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 24, v[0:1]
; VI-NEXT:    v_bfe_i32 v7, v3, 24, 1
; VI-NEXT:    v_and_b32_e32 v5, v7, v5
; VI-NEXT:    v_and_b32_e32 v4, v7, v4
; VI-NEXT:    v_xor_b32_e32 v6, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 25, v[0:1]
; VI-NEXT:    v_bfe_i32 v7, v3, 25, 1
; VI-NEXT:    v_and_b32_e32 v5, v7, v5
; VI-NEXT:    v_and_b32_e32 v4, v7, v4
; VI-NEXT:    v_xor_b32_e32 v6, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 26, v[0:1]
; VI-NEXT:    v_bfe_i32 v7, v3, 26, 1
; VI-NEXT:    v_and_b32_e32 v5, v7, v5
; VI-NEXT:    v_and_b32_e32 v4, v7, v4
; VI-NEXT:    v_xor_b32_e32 v6, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 27, v[0:1]
; VI-NEXT:    v_bfe_i32 v7, v3, 27, 1
; VI-NEXT:    v_and_b32_e32 v5, v7, v5
; VI-NEXT:    v_and_b32_e32 v4, v7, v4
; VI-NEXT:    v_xor_b32_e32 v6, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 28, v[0:1]
; VI-NEXT:    v_bfe_i32 v7, v3, 28, 1
; VI-NEXT:    v_and_b32_e32 v5, v7, v5
; VI-NEXT:    v_and_b32_e32 v4, v7, v4
; VI-NEXT:    v_xor_b32_e32 v6, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 29, v[0:1]
; VI-NEXT:    v_bfe_i32 v7, v3, 29, 1
; VI-NEXT:    v_and_b32_e32 v5, v7, v5
; VI-NEXT:    v_and_b32_e32 v4, v7, v4
; VI-NEXT:    v_xor_b32_e32 v6, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 30, v[0:1]
; VI-NEXT:    v_bfe_i32 v7, v3, 30, 1
; VI-NEXT:    v_lshlrev_b64 v[0:1], 31, v[0:1]
; VI-NEXT:    v_and_b32_e32 v5, v7, v5
; VI-NEXT:    v_and_b32_e32 v4, v7, v4
; VI-NEXT:    v_ashrrev_i32_e32 v3, 31, v3
; VI-NEXT:    v_xor_b32_e32 v5, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_and_b32_e32 v1, v3, v1
; VI-NEXT:    v_and_b32_e32 v0, v3, v0
; VI-NEXT:    v_xor_b32_e32 v1, v5, v1
; VI-NEXT:    v_xor_b32_e32 v0, v2, v0
; VI-NEXT:    v_alignbit_b32 v0, v1, v0, 31
; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT:    s_endpgm
;
; GFX9-LABEL: test_clmulr_i32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x24
; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT:    v_mov_b32_e32 v3, 0
; GFX9-NEXT:    s_mov_b32 s3, 0xf000
; GFX9-NEXT:    s_mov_b32 s2, -1
; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-NEXT:    global_load_dwordx2 v[0:1], v0, s[10:11]
; GFX9-NEXT:    s_mov_b32 s0, s8
; GFX9-NEXT:    s_mov_b32 s1, s9
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    v_bfe_i32 v4, v1, 0, 1
; GFX9-NEXT:    v_mov_b32_e32 v2, v0
; GFX9-NEXT:    v_and_b32_e32 v0, v4, v0
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 1, v[2:3]
; GFX9-NEXT:    v_bfe_i32 v6, v1, 1, 1
; GFX9-NEXT:    v_and_b32_e32 v4, v6, v4
; GFX9-NEXT:    v_and_b32_e32 v7, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 2, v[2:3]
; GFX9-NEXT:    v_bfe_i32 v6, v1, 2, 1
; GFX9-NEXT:    v_and_b32_e32 v5, v6, v5
; GFX9-NEXT:    v_and_b32_e32 v4, v6, v4
; GFX9-NEXT:    v_xor_b32_e32 v6, v7, v5
; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 3, v[2:3]
; GFX9-NEXT:    v_bfe_i32 v7, v1, 3, 1
; GFX9-NEXT:    v_and_b32_e32 v5, v7, v5
; GFX9-NEXT:    v_and_b32_e32 v4, v7, v4
; GFX9-NEXT:    v_xor_b32_e32 v6, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 4, v[2:3]
; GFX9-NEXT:    v_bfe_i32 v7, v1, 4, 1
; GFX9-NEXT:    v_and_b32_e32 v5, v7, v5
; GFX9-NEXT:    v_and_b32_e32 v4, v7, v4
; GFX9-NEXT:    v_xor_b32_e32 v6, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 5, v[2:3]
; GFX9-NEXT:    v_bfe_i32 v7, v1, 5, 1
; GFX9-NEXT:    v_and_b32_e32 v5, v7, v5
; GFX9-NEXT:    v_and_b32_e32 v4, v7, v4
; GFX9-NEXT:    v_xor_b32_e32 v6, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 6, v[2:3]
; GFX9-NEXT:    v_bfe_i32 v7, v1, 6, 1
; GFX9-NEXT:    v_and_b32_e32 v5, v7, v5
; GFX9-NEXT:    v_and_b32_e32 v4, v7, v4
; GFX9-NEXT:    v_xor_b32_e32 v6, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 7, v[2:3]
; GFX9-NEXT:    v_bfe_i32 v7, v1, 7, 1
; GFX9-NEXT:    v_and_b32_e32 v5, v7, v5
; GFX9-NEXT:    v_and_b32_e32 v4, v7, v4
; GFX9-NEXT:    v_xor_b32_e32 v6, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 8, v[2:3]
; GFX9-NEXT:    v_bfe_i32 v7, v1, 8, 1
; GFX9-NEXT:    v_and_b32_e32 v5, v7, v5
; GFX9-NEXT:    v_and_b32_e32 v4, v7, v4
; GFX9-NEXT:    v_xor_b32_e32 v6, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 9, v[2:3]
; GFX9-NEXT:    v_bfe_i32 v7, v1, 9, 1
; GFX9-NEXT:    v_and_b32_e32 v5, v7, v5
; GFX9-NEXT:    v_and_b32_e32 v4, v7, v4
; GFX9-NEXT:    v_xor_b32_e32 v6, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 10, v[2:3]
; GFX9-NEXT:    v_bfe_i32 v7, v1, 10, 1
; GFX9-NEXT:    v_and_b32_e32 v5, v7, v5
; GFX9-NEXT:    v_and_b32_e32 v4, v7, v4
; GFX9-NEXT:    v_xor_b32_e32 v6, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 11, v[2:3]
; GFX9-NEXT:    v_bfe_i32 v7, v1, 11, 1
; GFX9-NEXT:    v_and_b32_e32 v5, v7, v5
; GFX9-NEXT:    v_and_b32_e32 v4, v7, v4
; GFX9-NEXT:    v_xor_b32_e32 v6, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 12, v[2:3]
; GFX9-NEXT:    v_bfe_i32 v7, v1, 12, 1
; GFX9-NEXT:    v_and_b32_e32 v5, v7, v5
; GFX9-NEXT:    v_and_b32_e32 v4, v7, v4
; GFX9-NEXT:    v_xor_b32_e32 v6, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 13, v[2:3]
; GFX9-NEXT:    v_bfe_i32 v7, v1, 13, 1
; GFX9-NEXT:    v_and_b32_e32 v5, v7, v5
; GFX9-NEXT:    v_and_b32_e32 v4, v7, v4
; GFX9-NEXT:    v_xor_b32_e32 v6, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 14, v[2:3]
; GFX9-NEXT:    v_bfe_i32 v7, v1, 14, 1
; GFX9-NEXT:    v_and_b32_e32 v5, v7, v5
; GFX9-NEXT:    v_and_b32_e32 v4, v7, v4
; GFX9-NEXT:    v_xor_b32_e32 v6, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 15, v[2:3]
; GFX9-NEXT:    v_bfe_i32 v7, v1, 15, 1
; GFX9-NEXT:    v_and_b32_e32 v5, v7, v5
; GFX9-NEXT:    v_and_b32_e32 v4, v7, v4
; GFX9-NEXT:    v_xor_b32_e32 v6, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 16, v[2:3]
; GFX9-NEXT:    v_bfe_i32 v7, v1, 16, 1
; GFX9-NEXT:    v_and_b32_e32 v5, v7, v5
; GFX9-NEXT:    v_and_b32_e32 v4, v7, v4
; GFX9-NEXT:    v_xor_b32_e32 v6, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 17, v[2:3]
; GFX9-NEXT:    v_bfe_i32 v7, v1, 17, 1
; GFX9-NEXT:    v_and_b32_e32 v5, v7, v5
; GFX9-NEXT:    v_and_b32_e32 v4, v7, v4
; GFX9-NEXT:    v_xor_b32_e32 v6, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 18, v[2:3]
; GFX9-NEXT:    v_bfe_i32 v7, v1, 18, 1
; GFX9-NEXT:    v_and_b32_e32 v5, v7, v5
; GFX9-NEXT:    v_and_b32_e32 v4, v7, v4
; GFX9-NEXT:    v_xor_b32_e32 v6, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 19, v[2:3]
; GFX9-NEXT:    v_bfe_i32 v7, v1, 19, 1
; GFX9-NEXT:    v_and_b32_e32 v5, v7, v5
; GFX9-NEXT:    v_and_b32_e32 v4, v7, v4
; GFX9-NEXT:    v_xor_b32_e32 v6, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 20, v[2:3]
; GFX9-NEXT:    v_bfe_i32 v7, v1, 20, 1
; GFX9-NEXT:    v_and_b32_e32 v5, v7, v5
; GFX9-NEXT:    v_and_b32_e32 v4, v7, v4
; GFX9-NEXT:    v_xor_b32_e32 v6, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 21, v[2:3]
; GFX9-NEXT:    v_bfe_i32 v7, v1, 21, 1
; GFX9-NEXT:    v_and_b32_e32 v5, v7, v5
; GFX9-NEXT:    v_and_b32_e32 v4, v7, v4
; GFX9-NEXT:    v_xor_b32_e32 v6, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 22, v[2:3]
; GFX9-NEXT:    v_bfe_i32 v7, v1, 22, 1
; GFX9-NEXT:    v_and_b32_e32 v5, v7, v5
; GFX9-NEXT:    v_and_b32_e32 v4, v7, v4
; GFX9-NEXT:    v_xor_b32_e32 v6, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 23, v[2:3]
; GFX9-NEXT:    v_bfe_i32 v7, v1, 23, 1
; GFX9-NEXT:    v_and_b32_e32 v5, v7, v5
; GFX9-NEXT:    v_and_b32_e32 v4, v7, v4
; GFX9-NEXT:    v_xor_b32_e32 v6, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 24, v[2:3]
; GFX9-NEXT:    v_bfe_i32 v7, v1, 24, 1
; GFX9-NEXT:    v_and_b32_e32 v5, v7, v5
; GFX9-NEXT:    v_and_b32_e32 v4, v7, v4
; GFX9-NEXT:    v_xor_b32_e32 v6, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 25, v[2:3]
; GFX9-NEXT:    v_bfe_i32 v7, v1, 25, 1
; GFX9-NEXT:    v_and_b32_e32 v5, v7, v5
; GFX9-NEXT:    v_and_b32_e32 v4, v7, v4
; GFX9-NEXT:    v_xor_b32_e32 v6, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 26, v[2:3]
; GFX9-NEXT:    v_bfe_i32 v7, v1, 26, 1
; GFX9-NEXT:    v_and_b32_e32 v5, v7, v5
; GFX9-NEXT:    v_and_b32_e32 v4, v7, v4
; GFX9-NEXT:    v_xor_b32_e32 v6, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 27, v[2:3]
; GFX9-NEXT:    v_bfe_i32 v7, v1, 27, 1
; GFX9-NEXT:    v_and_b32_e32 v5, v7, v5
; GFX9-NEXT:    v_and_b32_e32 v4, v7, v4
; GFX9-NEXT:    v_xor_b32_e32 v6, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 28, v[2:3]
; GFX9-NEXT:    v_bfe_i32 v7, v1, 28, 1
; GFX9-NEXT:    v_and_b32_e32 v5, v7, v5
; GFX9-NEXT:    v_and_b32_e32 v4, v7, v4
; GFX9-NEXT:    v_xor_b32_e32 v6, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 29, v[2:3]
; GFX9-NEXT:    v_bfe_i32 v7, v1, 29, 1
; GFX9-NEXT:    v_and_b32_e32 v5, v7, v5
; GFX9-NEXT:    v_and_b32_e32 v4, v7, v4
; GFX9-NEXT:    v_xor_b32_e32 v6, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 30, v[2:3]
; GFX9-NEXT:    v_bfe_i32 v7, v1, 30, 1
; GFX9-NEXT:    v_and_b32_e32 v5, v7, v5
; GFX9-NEXT:    v_and_b32_e32 v4, v7, v4
; GFX9-NEXT:    v_xor_b32_e32 v5, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v4, v0, v4
; GFX9-NEXT:    v_ashrrev_i32_e32 v6, 31, v1
; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 31, v[2:3]
; GFX9-NEXT:    v_and_b32_e32 v1, v6, v1
; GFX9-NEXT:    v_and_b32_e32 v0, v6, v0
; GFX9-NEXT:    v_xor_b32_e32 v1, v5, v1
; GFX9-NEXT:    v_xor_b32_e32 v0, v4, v0
; GFX9-NEXT:    v_alignbit_b32 v0, v1, v0, 31
; GFX9-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; GFX9-NEXT:    s_endpgm
;
; GFX10-LABEL: test_clmulr_i32:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT:    v_mov_b32_e32 v1, 0
; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
; GFX10-NEXT:    global_load_dwordx2 v[2:3], v0, s[2:3]
; GFX10-NEXT:    s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT:    s_mov_b32 s3, 0x31016000
; GFX10-NEXT:    s_mov_b32 s2, -1
; GFX10-NEXT:    s_waitcnt vmcnt(0)
; GFX10-NEXT:    v_mov_b32_e32 v0, v2
; GFX10-NEXT:    v_bfe_i32 v8, v3, 0, 1
; GFX10-NEXT:    v_bfe_i32 v9, v3, 1, 1
; GFX10-NEXT:    v_bfe_i32 v10, v3, 2, 1
; GFX10-NEXT:    v_bfe_i32 v11, v3, 3, 1
; GFX10-NEXT:    v_lshlrev_b64 v[4:5], 1, v[0:1]
; GFX10-NEXT:    v_lshlrev_b64 v[6:7], 2, v[0:1]
; GFX10-NEXT:    v_and_b32_e32 v8, v8, v2
; GFX10-NEXT:    v_bfe_i32 v12, v3, 4, 1
; GFX10-NEXT:    v_bfe_i32 v13, v3, 5, 1
; GFX10-NEXT:    v_bfe_i32 v14, v3, 6, 1
; GFX10-NEXT:    v_and_b32_e32 v4, v9, v4
; GFX10-NEXT:    v_bfe_i32 v15, v3, 7, 1
; GFX10-NEXT:    v_bfe_i32 v16, v3, 8, 1
; GFX10-NEXT:    v_bfe_i32 v17, v3, 9, 1
; GFX10-NEXT:    v_bfe_i32 v18, v3, 10, 1
; GFX10-NEXT:    v_bfe_i32 v19, v3, 11, 1
; GFX10-NEXT:    v_bfe_i32 v20, v3, 12, 1
; GFX10-NEXT:    v_bfe_i32 v21, v3, 13, 1
; GFX10-NEXT:    v_bfe_i32 v22, v3, 14, 1
; GFX10-NEXT:    v_bfe_i32 v23, v3, 15, 1
; GFX10-NEXT:    v_bfe_i32 v24, v3, 16, 1
; GFX10-NEXT:    v_bfe_i32 v25, v3, 17, 1
; GFX10-NEXT:    v_bfe_i32 v26, v3, 18, 1
; GFX10-NEXT:    v_bfe_i32 v27, v3, 19, 1
; GFX10-NEXT:    v_bfe_i32 v28, v3, 20, 1
; GFX10-NEXT:    v_bfe_i32 v29, v3, 21, 1
; GFX10-NEXT:    v_bfe_i32 v30, v3, 22, 1
; GFX10-NEXT:    v_bfe_i32 v31, v3, 23, 1
; GFX10-NEXT:    v_bfe_i32 v32, v3, 24, 1
; GFX10-NEXT:    v_bfe_i32 v33, v3, 25, 1
; GFX10-NEXT:    v_bfe_i32 v34, v3, 26, 1
; GFX10-NEXT:    v_bfe_i32 v35, v3, 27, 1
; GFX10-NEXT:    v_bfe_i32 v36, v3, 28, 1
; GFX10-NEXT:    v_bfe_i32 v37, v3, 29, 1
; GFX10-NEXT:    v_bfe_i32 v38, v3, 30, 1
; GFX10-NEXT:    v_ashrrev_i32_e32 v39, 31, v3
; GFX10-NEXT:    v_lshlrev_b64 v[2:3], 3, v[0:1]
; GFX10-NEXT:    v_and_b32_e32 v9, v9, v5
; GFX10-NEXT:    v_and_b32_e32 v7, v10, v7
; GFX10-NEXT:    v_and_b32_e32 v6, v10, v6
; GFX10-NEXT:    v_xor_b32_e32 v8, v8, v4
; GFX10-NEXT:    v_lshlrev_b64 v[4:5], 4, v[0:1]
; GFX10-NEXT:    v_and_b32_e32 v10, v11, v3
; GFX10-NEXT:    v_and_b32_e32 v11, v11, v2
; GFX10-NEXT:    v_xor_b32_e32 v7, v9, v7
; GFX10-NEXT:    v_xor_b32_e32 v6, v8, v6
; GFX10-NEXT:    v_lshlrev_b64 v[2:3], 5, v[0:1]
; GFX10-NEXT:    v_and_b32_e32 v8, v12, v5
; GFX10-NEXT:    v_and_b32_e32 v9, v12, v4
; GFX10-NEXT:    v_xor_b32_e32 v7, v7, v10
; GFX10-NEXT:    v_xor_b32_e32 v6, v6, v11
; GFX10-NEXT:    v_lshlrev_b64 v[4:5], 6, v[0:1]
; GFX10-NEXT:    v_and_b32_e32 v10, v13, v3
; GFX10-NEXT:    v_and_b32_e32 v11, v13, v2
; GFX10-NEXT:    v_xor_b32_e32 v7, v7, v8
; GFX10-NEXT:    v_xor_b32_e32 v6, v6, v9
; GFX10-NEXT:    v_lshlrev_b64 v[2:3], 7, v[0:1]
; GFX10-NEXT:    v_and_b32_e32 v8, v14, v5
; GFX10-NEXT:    v_and_b32_e32 v9, v14, v4
; GFX10-NEXT:    v_xor_b32_e32 v7, v7, v10
; GFX10-NEXT:    v_xor_b32_e32 v6, v6, v11
; GFX10-NEXT:    v_lshlrev_b64 v[4:5], 8, v[0:1]
; GFX10-NEXT:    v_and_b32_e32 v10, v15, v3
; GFX10-NEXT:    v_and_b32_e32 v11, v15, v2
; GFX10-NEXT:    v_xor_b32_e32 v7, v7, v8
; GFX10-NEXT:    v_xor_b32_e32 v6, v6, v9
; GFX10-NEXT:    v_lshlrev_b64 v[2:3], 9, v[0:1]
; GFX10-NEXT:    v_and_b32_e32 v8, v16, v5
; GFX10-NEXT:    v_and_b32_e32 v9, v16, v4
; GFX10-NEXT:    v_xor_b32_e32 v7, v7, v10
; GFX10-NEXT:    v_xor_b32_e32 v6, v6, v11
; GFX10-NEXT:    v_lshlrev_b64 v[4:5], 10, v[0:1]
; GFX10-NEXT:    v_and_b32_e32 v10, v17, v3
; GFX10-NEXT:    v_and_b32_e32 v11, v17, v2
; GFX10-NEXT:    v_xor_b32_e32 v7, v7, v8
; GFX10-NEXT:    v_xor_b32_e32 v6, v6, v9
; GFX10-NEXT:    v_lshlrev_b64 v[2:3], 11, v[0:1]
; GFX10-NEXT:    v_and_b32_e32 v8, v18, v5
; GFX10-NEXT:    v_and_b32_e32 v9, v18, v4
; GFX10-NEXT:    v_xor_b32_e32 v7, v7, v10
; GFX10-NEXT:    v_xor_b32_e32 v6, v6, v11
; GFX10-NEXT:    v_lshlrev_b64 v[4:5], 12, v[0:1]
; GFX10-NEXT:    v_and_b32_e32 v10, v19, v3
; GFX10-NEXT:    v_and_b32_e32 v11, v19, v2
; GFX10-NEXT:    v_xor_b32_e32 v7, v7, v8
; GFX10-NEXT:    v_xor_b32_e32 v6, v6, v9
; GFX10-NEXT:    v_lshlrev_b64 v[2:3], 13, v[0:1]
; GFX10-NEXT:    v_and_b32_e32 v8, v20, v5
; GFX10-NEXT:    v_and_b32_e32 v9, v20, v4
; GFX10-NEXT:    v_xor_b32_e32 v7, v7, v10
; GFX10-NEXT:    v_xor_b32_e32 v6, v6, v11
; GFX10-NEXT:    v_lshlrev_b64 v[4:5], 14, v[0:1]
; GFX10-NEXT:    v_and_b32_e32 v10, v21, v3
; GFX10-NEXT:    v_and_b32_e32 v11, v21, v2
; GFX10-NEXT:    v_xor_b32_e32 v7, v7, v8
; GFX10-NEXT:    v_xor_b32_e32 v6, v6, v9
; GFX10-NEXT:    v_lshlrev_b64 v[2:3], 15, v[0:1]
; GFX10-NEXT:    v_and_b32_e32 v8, v22, v5
; GFX10-NEXT:    v_and_b32_e32 v9, v22, v4
; GFX10-NEXT:    v_xor_b32_e32 v7, v7, v10
; GFX10-NEXT:    v_xor_b32_e32 v6, v6, v11
; GFX10-NEXT:    v_lshlrev_b64 v[4:5], 16, v[0:1]
; GFX10-NEXT:    v_and_b32_e32 v10, v23, v3
; GFX10-NEXT:    v_and_b32_e32 v11, v23, v2
; GFX10-NEXT:    v_xor_b32_e32 v7, v7, v8
; GFX10-NEXT:    v_xor_b32_e32 v6, v6, v9
; GFX10-NEXT:    v_lshlrev_b64 v[2:3], 17, v[0:1]
; GFX10-NEXT:    v_and_b32_e32 v8, v24, v5
; GFX10-NEXT:    v_and_b32_e32 v9, v24, v4
; GFX10-NEXT:    v_xor_b32_e32 v7, v7, v10
; GFX10-NEXT:    v_xor_b32_e32 v6, v6, v11
; GFX10-NEXT:    v_lshlrev_b64 v[4:5], 18, v[0:1]
; GFX10-NEXT:    v_and_b32_e32 v10, v25, v3
; GFX10-NEXT:    v_and_b32_e32 v11, v25, v2
; GFX10-NEXT:    v_xor_b32_e32 v7, v7, v8
; GFX10-NEXT:    v_xor_b32_e32 v6, v6, v9
; GFX10-NEXT:    v_lshlrev_b64 v[2:3], 19, v[0:1]
; GFX10-NEXT:    v_and_b32_e32 v8, v26, v5
; GFX10-NEXT:    v_and_b32_e32 v9, v26, v4
; GFX10-NEXT:    v_xor_b32_e32 v7, v7, v10
; GFX10-NEXT:    v_xor_b32_e32 v6, v6, v11
; GFX10-NEXT:    v_lshlrev_b64 v[4:5], 20, v[0:1]
; GFX10-NEXT:    v_and_b32_e32 v10, v27, v3
; GFX10-NEXT:    v_and_b32_e32 v11, v27, v2
; GFX10-NEXT:    v_xor_b32_e32 v7, v7, v8
; GFX10-NEXT:    v_xor_b32_e32 v6, v6, v9
; GFX10-NEXT:    v_lshlrev_b64 v[2:3], 21, v[0:1]
; GFX10-NEXT:    v_and_b32_e32 v8, v28, v5
; GFX10-NEXT:    v_and_b32_e32 v9, v28, v4
; GFX10-NEXT:    v_xor_b32_e32 v7, v7, v10
; GFX10-NEXT:    v_xor_b32_e32 v6, v6, v11
; GFX10-NEXT:    v_lshlrev_b64 v[4:5], 22, v[0:1]
; GFX10-NEXT:    v_and_b32_e32 v10, v29, v3
; GFX10-NEXT:    v_and_b32_e32 v11, v29, v2
; GFX10-NEXT:    v_xor_b32_e32 v7, v7, v8
; GFX10-NEXT:    v_xor_b32_e32 v6, v6, v9
; GFX10-NEXT:    v_lshlrev_b64 v[2:3], 23, v[0:1]
; GFX10-NEXT:    v_and_b32_e32 v8, v30, v5
; GFX10-NEXT:    v_and_b32_e32 v9, v30, v4
; GFX10-NEXT:    v_xor_b32_e32 v7, v7, v10
; GFX10-NEXT:    v_xor_b32_e32 v6, v6, v11
; GFX10-NEXT:    v_lshlrev_b64 v[4:5], 24, v[0:1]
; GFX10-NEXT:    v_and_b32_e32 v10, v31, v3
; GFX10-NEXT:    v_and_b32_e32 v11, v31, v2
; GFX10-NEXT:    v_xor_b32_e32 v7, v7, v8
; GFX10-NEXT:    v_xor_b32_e32 v6, v6, v9
; GFX10-NEXT:    v_lshlrev_b64 v[2:3], 25, v[0:1]
; GFX10-NEXT:    v_and_b32_e32 v8, v32, v5
; GFX10-NEXT:    v_and_b32_e32 v9, v32, v4
; GFX10-NEXT:    v_xor_b32_e32 v7, v7, v10
; GFX10-NEXT:    v_xor_b32_e32 v6, v6, v11
; GFX10-NEXT:    v_lshlrev_b64 v[4:5], 26, v[0:1]
; GFX10-NEXT:    v_and_b32_e32 v10, v33, v3
; GFX10-NEXT:    v_and_b32_e32 v11, v33, v2
; GFX10-NEXT:    v_xor_b32_e32 v7, v7, v8
; GFX10-NEXT:    v_xor_b32_e32 v6, v6, v9
; GFX10-NEXT:    v_lshlrev_b64 v[2:3], 27, v[0:1]
; GFX10-NEXT:    v_and_b32_e32 v8, v34, v5
; GFX10-NEXT:    v_and_b32_e32 v9, v34, v4
; GFX10-NEXT:    v_xor_b32_e32 v7, v7, v10
; GFX10-NEXT:    v_xor_b32_e32 v6, v6, v11
; GFX10-NEXT:    v_lshlrev_b64 v[4:5], 28, v[0:1]
; GFX10-NEXT:    v_and_b32_e32 v10, v35, v3
; GFX10-NEXT:    v_and_b32_e32 v11, v35, v2
; GFX10-NEXT:    v_xor_b32_e32 v7, v7, v8
; GFX10-NEXT:    v_xor_b32_e32 v6, v6, v9
; GFX10-NEXT:    v_lshlrev_b64 v[2:3], 29, v[0:1]
; GFX10-NEXT:    v_and_b32_e32 v8, v36, v5
; GFX10-NEXT:    v_and_b32_e32 v9, v36, v4
; GFX10-NEXT:    v_xor_b32_e32 v7, v7, v10
; GFX10-NEXT:    v_xor_b32_e32 v6, v6, v11
; GFX10-NEXT:    v_lshlrev_b64 v[4:5], 30, v[0:1]
; GFX10-NEXT:    v_and_b32_e32 v3, v37, v3
; GFX10-NEXT:    v_and_b32_e32 v2, v37, v2
; GFX10-NEXT:    v_xor_b32_e32 v7, v7, v8
; GFX10-NEXT:    v_xor_b32_e32 v6, v6, v9
; GFX10-NEXT:    v_lshlrev_b64 v[0:1], 31, v[0:1]
; GFX10-NEXT:    v_and_b32_e32 v5, v38, v5
; GFX10-NEXT:    v_and_b32_e32 v4, v38, v4
; GFX10-NEXT:    v_xor_b32_e32 v3, v7, v3
; GFX10-NEXT:    v_xor_b32_e32 v2, v6, v2
; GFX10-NEXT:    v_and_b32_e32 v1, v39, v1
; GFX10-NEXT:    v_and_b32_e32 v0, v39, v0
; GFX10-NEXT:    v_xor_b32_e32 v3, v3, v5
; GFX10-NEXT:    v_xor_b32_e32 v2, v2, v4
; GFX10-NEXT:    v_xor_b32_e32 v1, v3, v1
; GFX10-NEXT:    v_xor_b32_e32 v0, v2, v0
; GFX10-NEXT:    v_alignbit_b32 v0, v1, v0, 31
; GFX10-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; GFX10-NEXT:    s_endpgm
;
; GFX11-LABEL: test_clmulr_i32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-NEXT:    v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x3ff, v0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-NEXT:    global_load_b64 v[0:1], v0, s[2:3]
; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
; GFX11-NEXT:    s_mov_b32 s2, -1
; GFX11-NEXT:    s_waitcnt vmcnt(0)
; GFX11-NEXT:    v_bfe_i32 v9, v1, 1, 1
; GFX11-NEXT:    v_mov_b32_e32 v2, v0
; GFX11-NEXT:    v_bfe_i32 v8, v1, 0, 1
; GFX11-NEXT:    v_bfe_i32 v10, v1, 2, 1
; GFX11-NEXT:    v_bfe_i32 v11, v1, 3, 1
; GFX11-NEXT:    v_bfe_i32 v12, v1, 4, 1
; GFX11-NEXT:    v_lshlrev_b64 v[4:5], 1, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v8, v8, v0
; GFX11-NEXT:    v_bfe_i32 v13, v1, 5, 1
; GFX11-NEXT:    v_bfe_i32 v14, v1, 6, 1
; GFX11-NEXT:    v_bfe_i32 v15, v1, 7, 1
; GFX11-NEXT:    v_bfe_i32 v16, v1, 8, 1
; GFX11-NEXT:    v_and_b32_e32 v4, v9, v4
; GFX11-NEXT:    v_and_b32_e32 v9, v9, v5
; GFX11-NEXT:    v_lshlrev_b64 v[6:7], 2, v[2:3]
; GFX11-NEXT:    v_bfe_i32 v17, v1, 9, 1
; GFX11-NEXT:    v_bfe_i32 v18, v1, 10, 1
; GFX11-NEXT:    v_bfe_i32 v19, v1, 11, 1
; GFX11-NEXT:    v_bfe_i32 v20, v1, 12, 1
; GFX11-NEXT:    v_bfe_i32 v21, v1, 13, 1
; GFX11-NEXT:    v_bfe_i32 v22, v1, 14, 1
; GFX11-NEXT:    v_bfe_i32 v23, v1, 15, 1
; GFX11-NEXT:    v_bfe_i32 v24, v1, 16, 1
; GFX11-NEXT:    v_bfe_i32 v25, v1, 17, 1
; GFX11-NEXT:    v_bfe_i32 v26, v1, 18, 1
; GFX11-NEXT:    v_bfe_i32 v27, v1, 19, 1
; GFX11-NEXT:    v_bfe_i32 v28, v1, 20, 1
; GFX11-NEXT:    v_bfe_i32 v29, v1, 21, 1
; GFX11-NEXT:    v_bfe_i32 v30, v1, 22, 1
; GFX11-NEXT:    v_bfe_i32 v31, v1, 23, 1
; GFX11-NEXT:    v_bfe_i32 v32, v1, 24, 1
; GFX11-NEXT:    v_bfe_i32 v33, v1, 25, 1
; GFX11-NEXT:    v_bfe_i32 v34, v1, 26, 1
; GFX11-NEXT:    v_bfe_i32 v35, v1, 27, 1
; GFX11-NEXT:    v_bfe_i32 v36, v1, 28, 1
; GFX11-NEXT:    v_bfe_i32 v37, v1, 29, 1
; GFX11-NEXT:    v_bfe_i32 v38, v1, 30, 1
; GFX11-NEXT:    v_ashrrev_i32_e32 v39, 31, v1
; GFX11-NEXT:    v_lshlrev_b64 v[0:1], 3, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v7, v10, v7
; GFX11-NEXT:    v_and_b32_e32 v6, v10, v6
; GFX11-NEXT:    v_xor_b32_e32 v8, v8, v4
; GFX11-NEXT:    v_lshlrev_b64 v[4:5], 4, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v10, v11, v1
; GFX11-NEXT:    v_and_b32_e32 v11, v11, v0
; GFX11-NEXT:    v_xor_b32_e32 v7, v9, v7
; GFX11-NEXT:    v_xor_b32_e32 v6, v8, v6
; GFX11-NEXT:    v_lshlrev_b64 v[0:1], 5, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v8, v12, v5
; GFX11-NEXT:    v_and_b32_e32 v9, v12, v4
; GFX11-NEXT:    v_xor_b32_e32 v7, v7, v10
; GFX11-NEXT:    v_xor_b32_e32 v6, v6, v11
; GFX11-NEXT:    v_lshlrev_b64 v[4:5], 6, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v10, v13, v1
; GFX11-NEXT:    v_and_b32_e32 v11, v13, v0
; GFX11-NEXT:    v_xor_b32_e32 v7, v7, v8
; GFX11-NEXT:    v_xor_b32_e32 v6, v6, v9
; GFX11-NEXT:    v_lshlrev_b64 v[0:1], 7, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v8, v14, v5
; GFX11-NEXT:    v_and_b32_e32 v9, v14, v4
; GFX11-NEXT:    v_xor_b32_e32 v7, v7, v10
; GFX11-NEXT:    v_xor_b32_e32 v6, v6, v11
; GFX11-NEXT:    v_lshlrev_b64 v[4:5], 8, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v10, v15, v1
; GFX11-NEXT:    v_and_b32_e32 v11, v15, v0
; GFX11-NEXT:    v_xor_b32_e32 v7, v7, v8
; GFX11-NEXT:    v_xor_b32_e32 v6, v6, v9
; GFX11-NEXT:    v_lshlrev_b64 v[0:1], 9, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v8, v16, v5
; GFX11-NEXT:    v_and_b32_e32 v9, v16, v4
; GFX11-NEXT:    v_xor_b32_e32 v7, v7, v10
; GFX11-NEXT:    v_xor_b32_e32 v6, v6, v11
; GFX11-NEXT:    v_lshlrev_b64 v[4:5], 10, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v10, v17, v1
; GFX11-NEXT:    v_and_b32_e32 v11, v17, v0
; GFX11-NEXT:    v_xor_b32_e32 v7, v7, v8
; GFX11-NEXT:    v_xor_b32_e32 v6, v6, v9
; GFX11-NEXT:    v_lshlrev_b64 v[0:1], 11, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v8, v18, v5
; GFX11-NEXT:    v_and_b32_e32 v9, v18, v4
; GFX11-NEXT:    v_xor_b32_e32 v7, v7, v10
; GFX11-NEXT:    v_xor_b32_e32 v6, v6, v11
; GFX11-NEXT:    v_lshlrev_b64 v[4:5], 12, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v10, v19, v1
; GFX11-NEXT:    v_and_b32_e32 v11, v19, v0
; GFX11-NEXT:    v_xor_b32_e32 v7, v7, v8
; GFX11-NEXT:    v_xor_b32_e32 v6, v6, v9
; GFX11-NEXT:    v_lshlrev_b64 v[0:1], 13, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v8, v20, v5
; GFX11-NEXT:    v_and_b32_e32 v9, v20, v4
; GFX11-NEXT:    v_xor_b32_e32 v7, v7, v10
; GFX11-NEXT:    v_xor_b32_e32 v6, v6, v11
; GFX11-NEXT:    v_lshlrev_b64 v[4:5], 14, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v10, v21, v1
; GFX11-NEXT:    v_and_b32_e32 v11, v21, v0
; GFX11-NEXT:    v_xor_b32_e32 v7, v7, v8
; GFX11-NEXT:    v_xor_b32_e32 v6, v6, v9
; GFX11-NEXT:    v_lshlrev_b64 v[0:1], 15, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v8, v22, v5
; GFX11-NEXT:    v_and_b32_e32 v9, v22, v4
; GFX11-NEXT:    v_xor_b32_e32 v7, v7, v10
; GFX11-NEXT:    v_xor_b32_e32 v6, v6, v11
; GFX11-NEXT:    v_lshlrev_b64 v[4:5], 16, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v10, v23, v1
; GFX11-NEXT:    v_and_b32_e32 v11, v23, v0
; GFX11-NEXT:    v_xor_b32_e32 v7, v7, v8
; GFX11-NEXT:    v_xor_b32_e32 v6, v6, v9
; GFX11-NEXT:    v_lshlrev_b64 v[0:1], 17, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v8, v24, v5
; GFX11-NEXT:    v_and_b32_e32 v9, v24, v4
; GFX11-NEXT:    v_xor_b32_e32 v7, v7, v10
; GFX11-NEXT:    v_xor_b32_e32 v6, v6, v11
; GFX11-NEXT:    v_lshlrev_b64 v[4:5], 18, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v10, v25, v1
; GFX11-NEXT:    v_and_b32_e32 v11, v25, v0
; GFX11-NEXT:    v_xor_b32_e32 v7, v7, v8
; GFX11-NEXT:    v_xor_b32_e32 v6, v6, v9
; GFX11-NEXT:    v_lshlrev_b64 v[0:1], 19, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v8, v26, v5
; GFX11-NEXT:    v_and_b32_e32 v9, v26, v4
; GFX11-NEXT:    v_xor_b32_e32 v7, v7, v10
; GFX11-NEXT:    v_xor_b32_e32 v6, v6, v11
; GFX11-NEXT:    v_lshlrev_b64 v[4:5], 20, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v10, v27, v1
; GFX11-NEXT:    v_and_b32_e32 v11, v27, v0
; GFX11-NEXT:    v_xor_b32_e32 v7, v7, v8
; GFX11-NEXT:    v_xor_b32_e32 v6, v6, v9
; GFX11-NEXT:    v_lshlrev_b64 v[0:1], 21, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v8, v28, v5
; GFX11-NEXT:    v_and_b32_e32 v9, v28, v4
; GFX11-NEXT:    v_xor_b32_e32 v7, v7, v10
; GFX11-NEXT:    v_xor_b32_e32 v6, v6, v11
; GFX11-NEXT:    v_lshlrev_b64 v[4:5], 22, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v10, v29, v1
; GFX11-NEXT:    v_and_b32_e32 v11, v29, v0
; GFX11-NEXT:    v_xor_b32_e32 v7, v7, v8
; GFX11-NEXT:    v_xor_b32_e32 v6, v6, v9
; GFX11-NEXT:    v_lshlrev_b64 v[0:1], 23, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v8, v30, v5
; GFX11-NEXT:    v_and_b32_e32 v9, v30, v4
; GFX11-NEXT:    v_xor_b32_e32 v7, v7, v10
; GFX11-NEXT:    v_xor_b32_e32 v6, v6, v11
; GFX11-NEXT:    v_lshlrev_b64 v[4:5], 24, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v10, v31, v1
; GFX11-NEXT:    v_and_b32_e32 v11, v31, v0
; GFX11-NEXT:    v_xor_b32_e32 v7, v7, v8
; GFX11-NEXT:    v_xor_b32_e32 v6, v6, v9
; GFX11-NEXT:    v_lshlrev_b64 v[0:1], 25, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v8, v32, v5
; GFX11-NEXT:    v_and_b32_e32 v9, v32, v4
; GFX11-NEXT:    v_xor_b32_e32 v7, v7, v10
; GFX11-NEXT:    v_xor_b32_e32 v6, v6, v11
; GFX11-NEXT:    v_lshlrev_b64 v[4:5], 26, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v10, v33, v1
; GFX11-NEXT:    v_and_b32_e32 v11, v33, v0
; GFX11-NEXT:    v_xor_b32_e32 v7, v7, v8
; GFX11-NEXT:    v_xor_b32_e32 v6, v6, v9
; GFX11-NEXT:    v_lshlrev_b64 v[0:1], 27, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v8, v34, v5
; GFX11-NEXT:    v_and_b32_e32 v9, v34, v4
; GFX11-NEXT:    v_xor_b32_e32 v7, v7, v10
; GFX11-NEXT:    v_xor_b32_e32 v6, v6, v11
; GFX11-NEXT:    v_lshlrev_b64 v[4:5], 28, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v10, v35, v1
; GFX11-NEXT:    v_and_b32_e32 v11, v35, v0
; GFX11-NEXT:    v_xor_b32_e32 v7, v7, v8
; GFX11-NEXT:    v_xor_b32_e32 v6, v6, v9
; GFX11-NEXT:    v_lshlrev_b64 v[0:1], 29, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v8, v36, v5
; GFX11-NEXT:    v_and_b32_e32 v9, v36, v4
; GFX11-NEXT:    v_xor_b32_e32 v7, v7, v10
; GFX11-NEXT:    v_xor_b32_e32 v6, v6, v11
; GFX11-NEXT:    v_lshlrev_b64 v[4:5], 30, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v10, v37, v1
; GFX11-NEXT:    v_and_b32_e32 v11, v37, v0
; GFX11-NEXT:    v_xor_b32_e32 v7, v7, v8
; GFX11-NEXT:    v_xor_b32_e32 v6, v6, v9
; GFX11-NEXT:    v_lshlrev_b64 v[0:1], 31, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v2, v38, v5
; GFX11-NEXT:    v_and_b32_e32 v3, v38, v4
; GFX11-NEXT:    v_xor_b32_e32 v4, v7, v10
; GFX11-NEXT:    v_xor_b32_e32 v5, v6, v11
; GFX11-NEXT:    v_and_b32_e32 v1, v39, v1
; GFX11-NEXT:    v_and_b32_e32 v0, v39, v0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_xor_b32_e32 v2, v4, v2
; GFX11-NEXT:    v_xor_b32_e32 v3, v5, v3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT:    v_xor_b32_e32 v1, v2, v1
; GFX11-NEXT:    v_xor_b32_e32 v0, v3, v0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_alignbit_b32 v0, v1, v0, 31
; GFX11-NEXT:    buffer_store_b32 v0, off, s[0:3], 0
; GFX11-NEXT:    s_endpgm
;
; GFX12-LABEL: test_clmulr_i32:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    global_load_b64 v[0:1], v0, s[2:3]
; GFX12-NEXT:    s_mov_b32 s3, 0x31016000
; GFX12-NEXT:    s_mov_b32 s2, -1
; GFX12-NEXT:    s_wait_loadcnt 0x0
; GFX12-NEXT:    v_and_b32_e32 v28, 0x11111111, v1
; GFX12-NEXT:    v_and_b32_e32 v24, 0x22222222, v0
; GFX12-NEXT:    v_and_b32_e32 v25, 0x22222222, v1
; GFX12-NEXT:    v_and_b32_e32 v26, 0x11111111, v0
; GFX12-NEXT:    v_and_b32_e32 v30, 0x88888888, v1
; GFX12-NEXT:    v_and_b32_e32 v29, 0x44444444, v0
; GFX12-NEXT:    v_and_b32_e32 v27, 0x44444444, v1
; GFX12-NEXT:    v_and_b32_e32 v31, 0x88888888, v0
; GFX12-NEXT:    v_mad_co_u64_u32 v[0:1], null, v24, v28, 0
; GFX12-NEXT:    v_mad_co_u64_u32 v[2:3], null, v26, v25, 0
; GFX12-NEXT:    v_mad_co_u64_u32 v[8:9], null, v24, v30, 0
; GFX12-NEXT:    v_mad_co_u64_u32 v[10:11], null, v26, v28, 0
; GFX12-NEXT:    v_mad_co_u64_u32 v[4:5], null, v29, v30, 0
; GFX12-NEXT:    v_mad_co_u64_u32 v[6:7], null, v31, v27, 0
; GFX12-NEXT:    v_mad_co_u64_u32 v[12:13], null, v29, v27, 0
; GFX12-NEXT:    v_mad_co_u64_u32 v[14:15], null, v31, v25, 0
; GFX12-NEXT:    v_mad_co_u64_u32 v[16:17], null, v24, v27, 0
; GFX12-NEXT:    v_mad_co_u64_u32 v[18:19], null, v26, v30, 0
; GFX12-NEXT:    v_mad_co_u64_u32 v[20:21], null, v29, v25, 0
; GFX12-NEXT:    v_mad_co_u64_u32 v[24:25], null, v24, v25, 0
; GFX12-NEXT:    v_mad_co_u64_u32 v[26:27], null, v26, v27, 0
; GFX12-NEXT:    v_xor_b32_e32 v1, v3, v1
; GFX12-NEXT:    v_xor_b32_e32 v0, v2, v0
; GFX12-NEXT:    v_xor_b32_e32 v2, v11, v9
; GFX12-NEXT:    v_xor_b32_e32 v3, v10, v8
; GFX12-NEXT:    v_mad_co_u64_u32 v[22:23], null, v31, v28, 0
; GFX12-NEXT:    v_mad_co_u64_u32 v[28:29], null, v29, v28, 0
; GFX12-NEXT:    v_xor_b32_e32 v8, v19, v17
; GFX12-NEXT:    v_xor_b32_e32 v9, v18, v16
; GFX12-NEXT:    v_xor_b32_e32 v10, v27, v25
; GFX12-NEXT:    v_xor_b32_e32 v11, v26, v24
; GFX12-NEXT:    v_xor_b32_e32 v1, v1, v5
; GFX12-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX12-NEXT:    v_xor_b32_e32 v2, v2, v13
; GFX12-NEXT:    v_xor_b32_e32 v3, v3, v12
; GFX12-NEXT:    v_mad_co_u64_u32 v[30:31], null, v31, v30, 0
; GFX12-NEXT:    v_xor_b32_e32 v4, v8, v21
; GFX12-NEXT:    v_xor_b32_e32 v5, v9, v20
; GFX12-NEXT:    v_xor_b32_e32 v8, v10, v29
; GFX12-NEXT:    v_xor_b32_e32 v9, v11, v28
; GFX12-NEXT:    v_xor_b32_e32 v1, v1, v7
; GFX12-NEXT:    v_xor_b32_e32 v0, v0, v6
; GFX12-NEXT:    v_xor_b32_e32 v2, v2, v15
; GFX12-NEXT:    v_xor_b32_e32 v3, v3, v14
; GFX12-NEXT:    v_xor_b32_e32 v4, v4, v23
; GFX12-NEXT:    v_xor_b32_e32 v5, v5, v22
; GFX12-NEXT:    v_xor_b32_e32 v6, v8, v31
; GFX12-NEXT:    v_xor_b32_e32 v7, v9, v30
; GFX12-NEXT:    v_and_b32_e32 v1, 0x22222222, v1
; GFX12-NEXT:    v_and_b32_e32 v0, 0x22222222, v0
; GFX12-NEXT:    v_and_b32_e32 v2, 0x11111111, v2
; GFX12-NEXT:    v_and_b32_e32 v3, 0x11111111, v3
; GFX12-NEXT:    v_and_b32_e32 v4, 0x88888888, v4
; GFX12-NEXT:    v_and_b32_e32 v5, 0x88888888, v5
; GFX12-NEXT:    v_and_b32_e32 v6, 0x44444444, v6
; GFX12-NEXT:    v_and_b32_e32 v7, 0x44444444, v7
; GFX12-NEXT:    v_or_b32_e32 v1, v2, v1
; GFX12-NEXT:    v_or_b32_e32 v0, v3, v0
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT:    v_or3_b32 v1, v1, v6, v4
; GFX12-NEXT:    v_or3_b32 v0, v0, v7, v5
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT:    v_alignbit_b32 v0, v1, v0, 31
; GFX12-NEXT:    buffer_store_b32 v0, off, s[0:3], null
; GFX12-NEXT:    s_endpgm
;
; GFX1250-LABEL: test_clmulr_i32:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-NEXT:    v_nop
; GFX1250-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
; GFX1250-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT:    v_lshlrev_b32_e32 v32, 2, v0
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    global_load_b64 v[0:1], v32, s[2:3]
; GFX1250-NEXT:    s_wait_xcnt 0x0
; GFX1250-NEXT:    s_mov_b32 s3, 0x31016000
; GFX1250-NEXT:    s_mov_b32 s2, -1
; GFX1250-NEXT:    s_wait_loadcnt 0x0
; GFX1250-NEXT:    v_and_b32_e32 v28, 0x11111111, v1
; GFX1250-NEXT:    v_and_b32_e32 v24, 0x22222222, v0
; GFX1250-NEXT:    v_and_b32_e32 v25, 0x22222222, v1
; GFX1250-NEXT:    v_and_b32_e32 v26, 0x11111111, v0
; GFX1250-NEXT:    v_and_b32_e32 v30, 0x88888888, v1
; GFX1250-NEXT:    v_and_b32_e32 v29, 0x44444444, v0
; GFX1250-NEXT:    v_and_b32_e32 v27, 0x44444444, v1
; GFX1250-NEXT:    v_and_b32_e32 v31, 0x88888888, v0
; GFX1250-NEXT:    v_mad_nc_u64_u32 v[0:1], v24, v28, 0
; GFX1250-NEXT:    v_mad_nc_u64_u32 v[2:3], v26, v25, 0
; GFX1250-NEXT:    v_mad_nc_u64_u32 v[8:9], v24, v30, 0
; GFX1250-NEXT:    v_mad_nc_u64_u32 v[10:11], v26, v28, 0
; GFX1250-NEXT:    v_mad_nc_u64_u32 v[4:5], v29, v30, 0
; GFX1250-NEXT:    v_mad_nc_u64_u32 v[6:7], v31, v27, 0
; GFX1250-NEXT:    v_mad_nc_u64_u32 v[12:13], v29, v27, 0
; GFX1250-NEXT:    v_mad_nc_u64_u32 v[14:15], v31, v25, 0
; GFX1250-NEXT:    v_mad_nc_u64_u32 v[16:17], v24, v27, 0
; GFX1250-NEXT:    v_mad_nc_u64_u32 v[18:19], v26, v30, 0
; GFX1250-NEXT:    v_mad_nc_u64_u32 v[20:21], v29, v25, 0
; GFX1250-NEXT:    v_mad_nc_u64_u32 v[24:25], v24, v25, 0
; GFX1250-NEXT:    v_mad_nc_u64_u32 v[26:27], v26, v27, 0
; GFX1250-NEXT:    v_xor_b32_e32 v1, v3, v1
; GFX1250-NEXT:    v_xor_b32_e32 v0, v2, v0
; GFX1250-NEXT:    v_xor_b32_e32 v2, v11, v9
; GFX1250-NEXT:    v_xor_b32_e32 v3, v10, v8
; GFX1250-NEXT:    v_mad_nc_u64_u32 v[22:23], v31, v28, 0
; GFX1250-NEXT:    v_mad_nc_u64_u32 v[28:29], v29, v28, 0
; GFX1250-NEXT:    v_xor_b32_e32 v8, v19, v17
; GFX1250-NEXT:    v_xor_b32_e32 v9, v18, v16
; GFX1250-NEXT:    v_xor_b32_e32 v10, v27, v25
; GFX1250-NEXT:    v_xor_b32_e32 v11, v26, v24
; GFX1250-NEXT:    v_xor_b32_e32 v1, v1, v5
; GFX1250-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX1250-NEXT:    v_xor_b32_e32 v2, v2, v13
; GFX1250-NEXT:    v_xor_b32_e32 v3, v3, v12
; GFX1250-NEXT:    v_mad_nc_u64_u32 v[30:31], v31, v30, 0
; GFX1250-NEXT:    v_xor_b32_e32 v4, v8, v21
; GFX1250-NEXT:    v_xor_b32_e32 v5, v9, v20
; GFX1250-NEXT:    v_xor_b32_e32 v8, v10, v29
; GFX1250-NEXT:    v_xor_b32_e32 v9, v11, v28
; GFX1250-NEXT:    v_xor_b32_e32 v1, v1, v7
; GFX1250-NEXT:    v_xor_b32_e32 v0, v0, v6
; GFX1250-NEXT:    v_xor_b32_e32 v2, v2, v15
; GFX1250-NEXT:    v_xor_b32_e32 v3, v3, v14
; GFX1250-NEXT:    v_xor_b32_e32 v4, v4, v23
; GFX1250-NEXT:    v_xor_b32_e32 v5, v5, v22
; GFX1250-NEXT:    v_xor_b32_e32 v6, v8, v31
; GFX1250-NEXT:    v_xor_b32_e32 v7, v9, v30
; GFX1250-NEXT:    v_and_b32_e32 v1, 0x22222222, v1
; GFX1250-NEXT:    v_and_b32_e32 v0, 0x22222222, v0
; GFX1250-NEXT:    v_and_b32_e32 v2, 0x11111111, v2
; GFX1250-NEXT:    v_and_b32_e32 v3, 0x11111111, v3
; GFX1250-NEXT:    v_and_b32_e32 v4, 0x88888888, v4
; GFX1250-NEXT:    v_and_b32_e32 v5, 0x88888888, v5
; GFX1250-NEXT:    v_and_b32_e32 v6, 0x44444444, v6
; GFX1250-NEXT:    v_and_b32_e32 v7, 0x44444444, v7
; GFX1250-NEXT:    v_or_b32_e32 v1, v2, v1
; GFX1250-NEXT:    v_or_b32_e32 v0, v3, v0
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-NEXT:    v_or3_b32 v1, v1, v6, v4
; GFX1250-NEXT:    v_or3_b32 v0, v0, v7, v5
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT:    v_alignbit_b32 v0, v1, v0, 31
; GFX1250-NEXT:    buffer_store_b32 v0, off, s[0:3], null
; GFX1250-NEXT:    s_endpgm
;
; EG-LABEL: test_clmulr_i32:
; EG:       ; %bb.0:
; EG-NEXT:    ALU 2, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT:    TEX 0 @6
; EG-NEXT:    ALU 92, @11, KC0[], KC1[]
; EG-NEXT:    ALU 52, @104, KC0[CB0:0-32], KC1[]
; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
; EG-NEXT:    CF_END
; EG-NEXT:    Fetch clause starting at 6:
; EG-NEXT:     VTX_READ_64 T0.XY, T0.X, 0, #1
; EG-NEXT:    ALU clause starting at 8:
; EG-NEXT:     LSHL * T0.W, T0.X, literal.x,
; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
; EG-NEXT:     ADD_INT * T0.X, KC0[2].Z, PV.W,
; EG-NEXT:    ALU clause starting at 11:
; EG-NEXT:     AND_INT T0.W, T0.X, literal.x,
; EG-NEXT:     LSHR * T1.W, T0.X, literal.y,
; EG-NEXT:    65280(9.147676e-41), 8(1.121039e-44)
; EG-NEXT:     AND_INT T1.X, PS, literal.x,
; EG-NEXT:     LSHR T1.Y, T0.X, literal.y,
; EG-NEXT:     LSHL T0.Z, PV.W, literal.z,
; EG-NEXT:     AND_INT T0.W, T0.Y, literal.x,
; EG-NEXT:     LSHR * T1.W, T0.Y, literal.z,
; EG-NEXT:    65280(9.147676e-41), 24(3.363116e-44)
; EG-NEXT:    8(1.121039e-44), 0(0.000000e+00)
; EG-NEXT:     LSHL T0.X, T0.X, literal.x,
; EG-NEXT:     AND_INT T2.Y, PS, literal.y,
; EG-NEXT:     LSHR T1.Z, T0.Y, literal.x,
; EG-NEXT:     LSHL T0.W, PV.W, literal.z,
; EG-NEXT:     LSHL * T1.W, T0.Y, literal.x,
; EG-NEXT:    24(3.363116e-44), 65280(9.147676e-41)
; EG-NEXT:    8(1.121039e-44), 0(0.000000e+00)
; EG-NEXT:     OR_INT T0.Y, PS, PV.W,
; EG-NEXT:     OR_INT T1.Z, PV.Y, PV.Z,
; EG-NEXT:     OR_INT T0.W, PV.X, T0.Z,
; EG-NEXT:     OR_INT * T1.W, T1.X, T1.Y,
; EG-NEXT:     OR_INT T0.W, PV.W, PS,
; EG-NEXT:     OR_INT * T1.W, PV.Y, PV.Z,
; EG-NEXT:     AND_INT T0.Y, PS, literal.x,
; EG-NEXT:     LSHR T0.Z, PS, literal.y,
; EG-NEXT:     AND_INT T1.W, PV.W, literal.x,
; EG-NEXT:     LSHR * T0.W, PV.W, literal.y,
; EG-NEXT:    252645135(7.053345e-30), 4(5.605194e-45)
; EG-NEXT:     AND_INT T1.Y, PS, literal.x,
; EG-NEXT:     LSHL T1.Z, PV.W, literal.y,
; EG-NEXT:     AND_INT T0.W, PV.Z, literal.x,
; EG-NEXT:     LSHL * T1.W, PV.Y, literal.y,
; EG-NEXT:    252645135(7.053345e-30), 4(5.605194e-45)
; EG-NEXT:     OR_INT T0.W, PV.W, PS,
; EG-NEXT:     OR_INT * T1.W, PV.Y, PV.Z,
; EG-NEXT:     AND_INT T0.Y, PS, literal.x,
; EG-NEXT:     LSHR T0.Z, PS, literal.y,
; EG-NEXT:     AND_INT T1.W, PV.W, literal.x,
; EG-NEXT:     LSHR * T0.W, PV.W, literal.y,
; EG-NEXT:    858993459(4.172325e-08), 2(2.802597e-45)
; EG-NEXT:     AND_INT T1.Y, PS, literal.x,
; EG-NEXT:     LSHL T1.Z, PV.W, literal.y,
; EG-NEXT:     AND_INT T0.W, PV.Z, literal.x,
; EG-NEXT:     LSHL * T1.W, PV.Y, literal.y,
; EG-NEXT:    858993459(4.172325e-08), 2(2.802597e-45)
; EG-NEXT:     OR_INT T0.W, PV.W, PS,
; EG-NEXT:     OR_INT * T1.W, PV.Y, PV.Z,
; EG-NEXT:     AND_INT T0.Y, PS, literal.x,
; EG-NEXT:     LSHR T0.Z, PS, 1,
; EG-NEXT:     AND_INT T1.W, PV.W, literal.x,
; EG-NEXT:     LSHR * T0.W, PV.W, 1,
; EG-NEXT:    1431655765(1.466015e+13), 0(0.000000e+00)
; EG-NEXT:     AND_INT T1.Y, PS, literal.x,
; EG-NEXT:     LSHL T1.Z, PV.W, 1,
; EG-NEXT:     AND_INT T0.W, PV.Z, literal.x,
; EG-NEXT:     LSHL * T1.W, PV.Y, 1,
; EG-NEXT:    1431655765(1.466015e+13), 0(0.000000e+00)
; EG-NEXT:     OR_INT T0.W, PV.W, PS,
; EG-NEXT:     OR_INT * T1.W, PV.Y, PV.Z,
; EG-NEXT:     AND_INT T2.W, PS, literal.x,
; EG-NEXT:     AND_INT * T3.W, PV.W, literal.y,
; EG-NEXT:    1145324612(7.850667e+02), 572662306(2.197316e-18)
; EG-NEXT:     AND_INT T4.W, T0.W, literal.x,
; EG-NEXT:     MULLO_INT * T0.X, PV.W, PS,
; EG-NEXT:    286331153(1.144374e-28), 0(0.000000e+00)
; EG-NEXT:     AND_INT T5.W, T1.W, literal.x,
; EG-NEXT:     MULLO_INT * T0.Y, T2.W, PV.W,
; EG-NEXT:    -2004318072(-8.217301e-34), 0(0.000000e+00)
; EG-NEXT:     AND_INT T6.W, T0.W, literal.x,
; EG-NEXT:     MULLO_INT * T0.Z, PV.W, T3.W,
; EG-NEXT:    1145324612(7.850667e+02), 0(0.000000e+00)
; EG-NEXT:     AND_INT T1.Z, T0.W, literal.x,
; EG-NEXT:     AND_INT T0.W, T1.W, literal.y, BS:VEC_120/SCL_212
; EG-NEXT:     MULLO_INT * T1.X, T5.W, PV.W,
; EG-NEXT:    -2004318072(-8.217301e-34), 286331153(1.144374e-28)
; EG-NEXT:     MULLO_INT * T1.Y, PV.W, PV.Z,
; EG-NEXT:     MULLO_INT * T2.X, T2.W, T1.Z,
; EG-NEXT:     MULLO_INT * T2.Y, T2.W, T6.W,
; EG-NEXT:     MULLO_INT * T2.Z, T0.W, T6.W,
; EG-NEXT:     AND_INT T1.W, T1.W, literal.x,
; EG-NEXT:     MULLO_INT * T2.W, T0.W, T4.W,
; EG-NEXT:    572662306(2.197316e-18), 0(0.000000e+00)
; EG-NEXT:     MULLO_INT * T3.X, PV.W, T1.Z,
; EG-NEXT:     MULLO_INT * T0.W, T0.W, T3.W,
; EG-NEXT:     MULLO_INT * T3.Y, T1.W, T4.W,
; EG-NEXT:     XOR_INT T3.Z, T0.W, PS,
; EG-NEXT:     XOR_INT * T0.W, T2.W, T3.X, BS:VEC_120/SCL_212
; EG-NEXT:     MULLO_INT * T2.W, T1.W, T3.W,
; EG-NEXT:     XOR_INT T3.Y, T2.Z, PS,
; EG-NEXT:     XOR_INT T2.Z, T0.W, T2.Y,
; EG-NEXT:     XOR_INT T0.W, T3.Z, T2.X, BS:VEC_120/SCL_212
; EG-NEXT:     MULLO_INT * T1.W, T1.W, T6.W,
; EG-NEXT:     XOR_INT * T2.X, T1.Y, PS,
; EG-NEXT:    ALU clause starting at 104:
; EG-NEXT:     XOR_INT T1.Y, T0.W, T1.X,
; EG-NEXT:     XOR_INT T0.Z, T2.Z, T0.Z, BS:VEC_021/SCL_122
; EG-NEXT:     XOR_INT T0.W, T3.Y, T0.Y,
; EG-NEXT:     MULLO_INT * T0.Y, T5.W, T1.Z,
; EG-NEXT:     XOR_INT T1.X, PV.W, PS,
; EG-NEXT:     AND_INT T0.Y, PV.Z, literal.x,
; EG-NEXT:     AND_INT T0.Z, PV.Y, literal.y,
; EG-NEXT:     XOR_INT T0.W, T2.X, T0.X,
; EG-NEXT:     MULLO_INT * T0.X, T5.W, T4.W,
; EG-NEXT:    286331153(1.144374e-28), 572662306(2.197316e-18)
; EG-NEXT:     XOR_INT T1.Z, PV.W, PS,
; EG-NEXT:     OR_INT T0.W, PV.Y, PV.Z,
; EG-NEXT:     AND_INT * T1.W, PV.X, literal.x,
; EG-NEXT:    1145324612(7.850667e+02), 0(0.000000e+00)
; EG-NEXT:     OR_INT T0.W, PV.W, PS,
; EG-NEXT:     AND_INT * T1.W, PV.Z, literal.x,
; EG-NEXT:    -2004318072(-8.217301e-34), 0(0.000000e+00)
; EG-NEXT:     OR_INT * T0.W, PV.W, PS,
; EG-NEXT:     AND_INT T1.W, PV.W, literal.x,
; EG-NEXT:     LSHR * T2.W, PV.W, literal.y,
; EG-NEXT:    65280(9.147676e-41), 8(1.121039e-44)
; EG-NEXT:     AND_INT T0.Y, PS, literal.x,
; EG-NEXT:     LSHR T0.Z, T0.W, literal.y,
; EG-NEXT:     LSHL T1.W, PV.W, literal.z,
; EG-NEXT:     LSHL * T0.W, T0.W, literal.y,
; EG-NEXT:    65280(9.147676e-41), 24(3.363116e-44)
; EG-NEXT:    8(1.121039e-44), 0(0.000000e+00)
; EG-NEXT:     OR_INT T0.W, PS, PV.W,
; EG-NEXT:     OR_INT * T1.W, PV.Y, PV.Z,
; EG-NEXT:     OR_INT * T0.W, PV.W, PS,
; EG-NEXT:     AND_INT T1.W, PV.W, literal.x,
; EG-NEXT:     LSHR * T0.W, PV.W, literal.y,
; EG-NEXT:    252645135(7.053345e-30), 4(5.605194e-45)
; EG-NEXT:     AND_INT T0.W, PS, literal.x,
; EG-NEXT:     LSHL * T1.W, PV.W, literal.y,
; EG-NEXT:    252645135(7.053345e-30), 4(5.605194e-45)
; EG-NEXT:     OR_INT * T0.W, PV.W, PS,
; EG-NEXT:     AND_INT T1.W, PV.W, literal.x,
; EG-NEXT:     LSHR * T0.W, PV.W, literal.y,
; EG-NEXT:    858993459(4.172325e-08), 2(2.802597e-45)
; EG-NEXT:     AND_INT T0.W, PS, literal.x,
; EG-NEXT:     LSHL * T1.W, PV.W, literal.y,
; EG-NEXT:    858993459(4.172325e-08), 2(2.802597e-45)
; EG-NEXT:     OR_INT * T0.W, PV.W, PS,
; EG-NEXT:     AND_INT T1.W, PV.W, literal.x,
; EG-NEXT:     LSHR * T0.W, PV.W, 1,
; EG-NEXT:    1431655765(1.466015e+13), 0(0.000000e+00)
; EG-NEXT:     AND_INT T0.W, PS, literal.x,
; EG-NEXT:     LSHL * T1.W, PV.W, 1,
; EG-NEXT:    1431655765(1.466015e+13), 0(0.000000e+00)
; EG-NEXT:     OR_INT T0.X, PV.W, PS,
; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
  %tid = call i32 @llvm.amdgcn.workitem.id.x()
  %in.tid = getelementptr inbounds i32, ptr addrspace(1) %in, i32 %tid
  %b_ptr = getelementptr i32, ptr addrspace(1) %in.tid, i32 1
  %a = load i32, ptr addrspace(1) %in.tid
  %b = load i32, ptr addrspace(1) %b_ptr
  %a.ext = zext i32 %a to i64
  %b.ext = zext i32 %b to i64
  %clmul = call i64 @llvm.clmul.i64(i64 %a.ext, i64 %b.ext)
  %res.ext = lshr i64 %clmul, 31
  %res = trunc i64 %res.ext to i32
  store i32 %res, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @test_clmulh_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {
; SI-LABEL: test_clmulh_i32:
; SI:       ; %bb.0:
; SI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x9
; SI-NEXT:    s_mov_b32 s3, 0xf000
; SI-NEXT:    s_mov_b32 s10, 0
; SI-NEXT:    s_mov_b32 s11, s3
; SI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    s_mov_b64 s[8:9], s[6:7]
; SI-NEXT:    v_mov_b32_e32 v1, 0
; SI-NEXT:    buffer_load_dwordx2 v[2:3], v[0:1], s[8:11], 0 addr64
; SI-NEXT:    s_mov_b32 s2, -1
; SI-NEXT:    s_mov_b32 s0, s4
; SI-NEXT:    s_mov_b32 s1, s5
; SI-NEXT:    s_waitcnt vmcnt(0)
; SI-NEXT:    v_mov_b32_e32 v0, v2
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 1
; SI-NEXT:    v_bfe_i32 v2, v3, 1, 1
; SI-NEXT:    v_and_b32_e32 v2, v2, v5
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 2
; SI-NEXT:    v_bfe_i32 v6, v3, 2, 1
; SI-NEXT:    v_and_b32_e32 v4, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 3
; SI-NEXT:    v_bfe_i32 v6, v3, 3, 1
; SI-NEXT:    v_and_b32_e32 v4, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 4
; SI-NEXT:    v_bfe_i32 v6, v3, 4, 1
; SI-NEXT:    v_and_b32_e32 v4, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 5
; SI-NEXT:    v_bfe_i32 v6, v3, 5, 1
; SI-NEXT:    v_and_b32_e32 v4, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 6
; SI-NEXT:    v_bfe_i32 v6, v3, 6, 1
; SI-NEXT:    v_and_b32_e32 v4, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 7
; SI-NEXT:    v_bfe_i32 v6, v3, 7, 1
; SI-NEXT:    v_and_b32_e32 v4, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 8
; SI-NEXT:    v_bfe_i32 v6, v3, 8, 1
; SI-NEXT:    v_and_b32_e32 v4, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 9
; SI-NEXT:    v_bfe_i32 v6, v3, 9, 1
; SI-NEXT:    v_and_b32_e32 v4, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 10
; SI-NEXT:    v_bfe_i32 v6, v3, 10, 1
; SI-NEXT:    v_and_b32_e32 v4, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 11
; SI-NEXT:    v_bfe_i32 v6, v3, 11, 1
; SI-NEXT:    v_and_b32_e32 v4, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 12
; SI-NEXT:    v_bfe_i32 v6, v3, 12, 1
; SI-NEXT:    v_and_b32_e32 v4, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 13
; SI-NEXT:    v_bfe_i32 v6, v3, 13, 1
; SI-NEXT:    v_and_b32_e32 v4, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 14
; SI-NEXT:    v_bfe_i32 v6, v3, 14, 1
; SI-NEXT:    v_and_b32_e32 v4, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 15
; SI-NEXT:    v_bfe_i32 v6, v3, 15, 1
; SI-NEXT:    v_and_b32_e32 v4, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 16
; SI-NEXT:    v_bfe_i32 v6, v3, 16, 1
; SI-NEXT:    v_and_b32_e32 v4, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 17
; SI-NEXT:    v_bfe_i32 v6, v3, 17, 1
; SI-NEXT:    v_and_b32_e32 v4, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 18
; SI-NEXT:    v_bfe_i32 v6, v3, 18, 1
; SI-NEXT:    v_and_b32_e32 v4, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 19
; SI-NEXT:    v_bfe_i32 v6, v3, 19, 1
; SI-NEXT:    v_and_b32_e32 v4, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 20
; SI-NEXT:    v_bfe_i32 v6, v3, 20, 1
; SI-NEXT:    v_and_b32_e32 v4, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 21
; SI-NEXT:    v_bfe_i32 v6, v3, 21, 1
; SI-NEXT:    v_and_b32_e32 v4, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 22
; SI-NEXT:    v_bfe_i32 v6, v3, 22, 1
; SI-NEXT:    v_and_b32_e32 v4, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 23
; SI-NEXT:    v_bfe_i32 v6, v3, 23, 1
; SI-NEXT:    v_and_b32_e32 v4, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 24
; SI-NEXT:    v_bfe_i32 v6, v3, 24, 1
; SI-NEXT:    v_and_b32_e32 v4, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 25
; SI-NEXT:    v_bfe_i32 v6, v3, 25, 1
; SI-NEXT:    v_and_b32_e32 v4, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 26
; SI-NEXT:    v_bfe_i32 v6, v3, 26, 1
; SI-NEXT:    v_and_b32_e32 v4, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 27
; SI-NEXT:    v_bfe_i32 v6, v3, 27, 1
; SI-NEXT:    v_and_b32_e32 v4, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 28
; SI-NEXT:    v_bfe_i32 v6, v3, 28, 1
; SI-NEXT:    v_and_b32_e32 v4, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 29
; SI-NEXT:    v_bfe_i32 v6, v3, 29, 1
; SI-NEXT:    v_and_b32_e32 v4, v6, v5
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_lshl_b64 v[4:5], v[0:1], 30
; SI-NEXT:    v_bfe_i32 v6, v3, 30, 1
; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], 31
; SI-NEXT:    v_and_b32_e32 v4, v6, v5
; SI-NEXT:    v_ashrrev_i32_e32 v3, 31, v3
; SI-NEXT:    v_xor_b32_e32 v2, v2, v4
; SI-NEXT:    v_and_b32_e32 v0, v3, v1
; SI-NEXT:    v_xor_b32_e32 v0, v2, v0
; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT:    s_endpgm
;
; VI-LABEL: test_clmulh_i32:
; VI:       ; %bb.0:
; VI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x24
; VI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; VI-NEXT:    v_mov_b32_e32 v1, 0
; VI-NEXT:    s_mov_b32 s3, 0xf000
; VI-NEXT:    s_mov_b32 s2, -1
; VI-NEXT:    s_waitcnt lgkmcnt(0)
; VI-NEXT:    v_add_u32_e32 v2, vcc, s6, v0
; VI-NEXT:    v_mov_b32_e32 v0, s7
; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v0, vcc
; VI-NEXT:    flat_load_dwordx2 v[2:3], v[2:3]
; VI-NEXT:    s_mov_b32 s0, s4
; VI-NEXT:    s_mov_b32 s1, s5
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    v_mov_b32_e32 v0, v2
; VI-NEXT:    v_lshlrev_b64 v[4:5], 1, v[0:1]
; VI-NEXT:    v_bfe_i32 v2, v3, 1, 1
; VI-NEXT:    v_and_b32_e32 v2, v2, v5
; VI-NEXT:    v_lshlrev_b64 v[4:5], 2, v[0:1]
; VI-NEXT:    v_bfe_i32 v6, v3, 2, 1
; VI-NEXT:    v_and_b32_e32 v4, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 3, v[0:1]
; VI-NEXT:    v_bfe_i32 v6, v3, 3, 1
; VI-NEXT:    v_and_b32_e32 v4, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 4, v[0:1]
; VI-NEXT:    v_bfe_i32 v6, v3, 4, 1
; VI-NEXT:    v_and_b32_e32 v4, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 5, v[0:1]
; VI-NEXT:    v_bfe_i32 v6, v3, 5, 1
; VI-NEXT:    v_and_b32_e32 v4, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 6, v[0:1]
; VI-NEXT:    v_bfe_i32 v6, v3, 6, 1
; VI-NEXT:    v_and_b32_e32 v4, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 7, v[0:1]
; VI-NEXT:    v_bfe_i32 v6, v3, 7, 1
; VI-NEXT:    v_and_b32_e32 v4, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 8, v[0:1]
; VI-NEXT:    v_bfe_i32 v6, v3, 8, 1
; VI-NEXT:    v_and_b32_e32 v4, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 9, v[0:1]
; VI-NEXT:    v_bfe_i32 v6, v3, 9, 1
; VI-NEXT:    v_and_b32_e32 v4, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 10, v[0:1]
; VI-NEXT:    v_bfe_i32 v6, v3, 10, 1
; VI-NEXT:    v_and_b32_e32 v4, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 11, v[0:1]
; VI-NEXT:    v_bfe_i32 v6, v3, 11, 1
; VI-NEXT:    v_and_b32_e32 v4, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 12, v[0:1]
; VI-NEXT:    v_bfe_i32 v6, v3, 12, 1
; VI-NEXT:    v_and_b32_e32 v4, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 13, v[0:1]
; VI-NEXT:    v_bfe_i32 v6, v3, 13, 1
; VI-NEXT:    v_and_b32_e32 v4, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 14, v[0:1]
; VI-NEXT:    v_bfe_i32 v6, v3, 14, 1
; VI-NEXT:    v_and_b32_e32 v4, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 15, v[0:1]
; VI-NEXT:    v_bfe_i32 v6, v3, 15, 1
; VI-NEXT:    v_and_b32_e32 v4, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 16, v[0:1]
; VI-NEXT:    v_bfe_i32 v6, v3, 16, 1
; VI-NEXT:    v_and_b32_e32 v4, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 17, v[0:1]
; VI-NEXT:    v_bfe_i32 v6, v3, 17, 1
; VI-NEXT:    v_and_b32_e32 v4, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 18, v[0:1]
; VI-NEXT:    v_bfe_i32 v6, v3, 18, 1
; VI-NEXT:    v_and_b32_e32 v4, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 19, v[0:1]
; VI-NEXT:    v_bfe_i32 v6, v3, 19, 1
; VI-NEXT:    v_and_b32_e32 v4, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 20, v[0:1]
; VI-NEXT:    v_bfe_i32 v6, v3, 20, 1
; VI-NEXT:    v_and_b32_e32 v4, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 21, v[0:1]
; VI-NEXT:    v_bfe_i32 v6, v3, 21, 1
; VI-NEXT:    v_and_b32_e32 v4, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 22, v[0:1]
; VI-NEXT:    v_bfe_i32 v6, v3, 22, 1
; VI-NEXT:    v_and_b32_e32 v4, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 23, v[0:1]
; VI-NEXT:    v_bfe_i32 v6, v3, 23, 1
; VI-NEXT:    v_and_b32_e32 v4, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 24, v[0:1]
; VI-NEXT:    v_bfe_i32 v6, v3, 24, 1
; VI-NEXT:    v_and_b32_e32 v4, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 25, v[0:1]
; VI-NEXT:    v_bfe_i32 v6, v3, 25, 1
; VI-NEXT:    v_and_b32_e32 v4, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 26, v[0:1]
; VI-NEXT:    v_bfe_i32 v6, v3, 26, 1
; VI-NEXT:    v_and_b32_e32 v4, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 27, v[0:1]
; VI-NEXT:    v_bfe_i32 v6, v3, 27, 1
; VI-NEXT:    v_and_b32_e32 v4, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 28, v[0:1]
; VI-NEXT:    v_bfe_i32 v6, v3, 28, 1
; VI-NEXT:    v_and_b32_e32 v4, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 29, v[0:1]
; VI-NEXT:    v_bfe_i32 v6, v3, 29, 1
; VI-NEXT:    v_and_b32_e32 v4, v6, v5
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_lshlrev_b64 v[4:5], 30, v[0:1]
; VI-NEXT:    v_bfe_i32 v6, v3, 30, 1
; VI-NEXT:    v_lshlrev_b64 v[0:1], 31, v[0:1]
; VI-NEXT:    v_and_b32_e32 v4, v6, v5
; VI-NEXT:    v_ashrrev_i32_e32 v3, 31, v3
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    v_and_b32_e32 v0, v3, v1
; VI-NEXT:    v_xor_b32_e32 v0, v2, v0
; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT:    s_endpgm
;
; GFX9-LABEL: test_clmulh_i32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x24
; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT:    v_mov_b32_e32 v1, 0
; GFX9-NEXT:    s_mov_b32 s3, 0xf000
; GFX9-NEXT:    s_mov_b32 s2, -1
; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-NEXT:    global_load_dwordx2 v[2:3], v0, s[10:11]
; GFX9-NEXT:    s_mov_b32 s0, s8
; GFX9-NEXT:    s_mov_b32 s1, s9
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v0, v2
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 1, v[0:1]
; GFX9-NEXT:    v_bfe_i32 v2, v3, 1, 1
; GFX9-NEXT:    v_and_b32_e32 v2, v2, v5
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 2, v[0:1]
; GFX9-NEXT:    v_bfe_i32 v6, v3, 2, 1
; GFX9-NEXT:    v_and_b32_e32 v4, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 3, v[0:1]
; GFX9-NEXT:    v_bfe_i32 v6, v3, 3, 1
; GFX9-NEXT:    v_and_b32_e32 v4, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 4, v[0:1]
; GFX9-NEXT:    v_bfe_i32 v6, v3, 4, 1
; GFX9-NEXT:    v_and_b32_e32 v4, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 5, v[0:1]
; GFX9-NEXT:    v_bfe_i32 v6, v3, 5, 1
; GFX9-NEXT:    v_and_b32_e32 v4, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 6, v[0:1]
; GFX9-NEXT:    v_bfe_i32 v6, v3, 6, 1
; GFX9-NEXT:    v_and_b32_e32 v4, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 7, v[0:1]
; GFX9-NEXT:    v_bfe_i32 v6, v3, 7, 1
; GFX9-NEXT:    v_and_b32_e32 v4, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 8, v[0:1]
; GFX9-NEXT:    v_bfe_i32 v6, v3, 8, 1
; GFX9-NEXT:    v_and_b32_e32 v4, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 9, v[0:1]
; GFX9-NEXT:    v_bfe_i32 v6, v3, 9, 1
; GFX9-NEXT:    v_and_b32_e32 v4, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 10, v[0:1]
; GFX9-NEXT:    v_bfe_i32 v6, v3, 10, 1
; GFX9-NEXT:    v_and_b32_e32 v4, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 11, v[0:1]
; GFX9-NEXT:    v_bfe_i32 v6, v3, 11, 1
; GFX9-NEXT:    v_and_b32_e32 v4, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 12, v[0:1]
; GFX9-NEXT:    v_bfe_i32 v6, v3, 12, 1
; GFX9-NEXT:    v_and_b32_e32 v4, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 13, v[0:1]
; GFX9-NEXT:    v_bfe_i32 v6, v3, 13, 1
; GFX9-NEXT:    v_and_b32_e32 v4, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 14, v[0:1]
; GFX9-NEXT:    v_bfe_i32 v6, v3, 14, 1
; GFX9-NEXT:    v_and_b32_e32 v4, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 15, v[0:1]
; GFX9-NEXT:    v_bfe_i32 v6, v3, 15, 1
; GFX9-NEXT:    v_and_b32_e32 v4, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 16, v[0:1]
; GFX9-NEXT:    v_bfe_i32 v6, v3, 16, 1
; GFX9-NEXT:    v_and_b32_e32 v4, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 17, v[0:1]
; GFX9-NEXT:    v_bfe_i32 v6, v3, 17, 1
; GFX9-NEXT:    v_and_b32_e32 v4, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 18, v[0:1]
; GFX9-NEXT:    v_bfe_i32 v6, v3, 18, 1
; GFX9-NEXT:    v_and_b32_e32 v4, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 19, v[0:1]
; GFX9-NEXT:    v_bfe_i32 v6, v3, 19, 1
; GFX9-NEXT:    v_and_b32_e32 v4, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 20, v[0:1]
; GFX9-NEXT:    v_bfe_i32 v6, v3, 20, 1
; GFX9-NEXT:    v_and_b32_e32 v4, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 21, v[0:1]
; GFX9-NEXT:    v_bfe_i32 v6, v3, 21, 1
; GFX9-NEXT:    v_and_b32_e32 v4, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 22, v[0:1]
; GFX9-NEXT:    v_bfe_i32 v6, v3, 22, 1
; GFX9-NEXT:    v_and_b32_e32 v4, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 23, v[0:1]
; GFX9-NEXT:    v_bfe_i32 v6, v3, 23, 1
; GFX9-NEXT:    v_and_b32_e32 v4, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 24, v[0:1]
; GFX9-NEXT:    v_bfe_i32 v6, v3, 24, 1
; GFX9-NEXT:    v_and_b32_e32 v4, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 25, v[0:1]
; GFX9-NEXT:    v_bfe_i32 v6, v3, 25, 1
; GFX9-NEXT:    v_and_b32_e32 v4, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 26, v[0:1]
; GFX9-NEXT:    v_bfe_i32 v6, v3, 26, 1
; GFX9-NEXT:    v_and_b32_e32 v4, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 27, v[0:1]
; GFX9-NEXT:    v_bfe_i32 v6, v3, 27, 1
; GFX9-NEXT:    v_and_b32_e32 v4, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 28, v[0:1]
; GFX9-NEXT:    v_bfe_i32 v6, v3, 28, 1
; GFX9-NEXT:    v_and_b32_e32 v4, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 29, v[0:1]
; GFX9-NEXT:    v_bfe_i32 v6, v3, 29, 1
; GFX9-NEXT:    v_and_b32_e32 v4, v6, v5
; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v4
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 30, v[0:1]
; GFX9-NEXT:    v_bfe_i32 v6, v3, 30, 1
; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 31, v[0:1]
; GFX9-NEXT:    v_and_b32_e32 v4, v6, v5
; GFX9-NEXT:    v_ashrrev_i32_e32 v3, 31, v3
; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v4
; GFX9-NEXT:    v_and_b32_e32 v0, v3, v1
; GFX9-NEXT:    v_xor_b32_e32 v0, v2, v0
; GFX9-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; GFX9-NEXT:    s_endpgm
;
; GFX10-LABEL: test_clmulh_i32:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT:    v_mov_b32_e32 v3, 0
; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
; GFX10-NEXT:    global_load_dwordx2 v[0:1], v0, s[2:3]
; GFX10-NEXT:    s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT:    s_mov_b32 s3, 0x31016000
; GFX10-NEXT:    s_mov_b32 s2, -1
; GFX10-NEXT:    s_waitcnt vmcnt(0)
; GFX10-NEXT:    v_mov_b32_e32 v2, v0
; GFX10-NEXT:    v_bfe_i32 v0, v1, 1, 1
; GFX10-NEXT:    v_lshlrev_b64 v[4:5], 1, v[2:3]
; GFX10-NEXT:    v_lshlrev_b64 v[6:7], 2, v[2:3]
; GFX10-NEXT:    v_bfe_i32 v4, v1, 2, 1
; GFX10-NEXT:    v_lshlrev_b64 v[8:9], 3, v[2:3]
; GFX10-NEXT:    v_bfe_i32 v6, v1, 3, 1
; GFX10-NEXT:    v_bfe_i32 v8, v1, 4, 1
; GFX10-NEXT:    v_and_b32_e32 v0, v0, v5
; GFX10-NEXT:    v_and_b32_e32 v7, v4, v7
; GFX10-NEXT:    v_lshlrev_b64 v[4:5], 4, v[2:3]
; GFX10-NEXT:    v_and_b32_e32 v4, v6, v9
; GFX10-NEXT:    v_bfe_i32 v9, v1, 5, 1
; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v7
; GFX10-NEXT:    v_lshlrev_b64 v[6:7], 5, v[2:3]
; GFX10-NEXT:    v_and_b32_e32 v6, v8, v5
; GFX10-NEXT:    v_bfe_i32 v8, v1, 6, 1
; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX10-NEXT:    v_lshlrev_b64 v[4:5], 6, v[2:3]
; GFX10-NEXT:    v_and_b32_e32 v4, v9, v7
; GFX10-NEXT:    v_bfe_i32 v9, v1, 7, 1
; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v6
; GFX10-NEXT:    v_lshlrev_b64 v[6:7], 7, v[2:3]
; GFX10-NEXT:    v_and_b32_e32 v6, v8, v5
; GFX10-NEXT:    v_bfe_i32 v8, v1, 8, 1
; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX10-NEXT:    v_lshlrev_b64 v[4:5], 8, v[2:3]
; GFX10-NEXT:    v_and_b32_e32 v4, v9, v7
; GFX10-NEXT:    v_bfe_i32 v9, v1, 9, 1
; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v6
; GFX10-NEXT:    v_lshlrev_b64 v[6:7], 9, v[2:3]
; GFX10-NEXT:    v_and_b32_e32 v6, v8, v5
; GFX10-NEXT:    v_bfe_i32 v8, v1, 10, 1
; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX10-NEXT:    v_lshlrev_b64 v[4:5], 10, v[2:3]
; GFX10-NEXT:    v_and_b32_e32 v4, v9, v7
; GFX10-NEXT:    v_bfe_i32 v9, v1, 11, 1
; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v6
; GFX10-NEXT:    v_lshlrev_b64 v[6:7], 11, v[2:3]
; GFX10-NEXT:    v_and_b32_e32 v6, v8, v5
; GFX10-NEXT:    v_bfe_i32 v8, v1, 12, 1
; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX10-NEXT:    v_lshlrev_b64 v[4:5], 12, v[2:3]
; GFX10-NEXT:    v_and_b32_e32 v4, v9, v7
; GFX10-NEXT:    v_bfe_i32 v9, v1, 13, 1
; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v6
; GFX10-NEXT:    v_lshlrev_b64 v[6:7], 13, v[2:3]
; GFX10-NEXT:    v_and_b32_e32 v6, v8, v5
; GFX10-NEXT:    v_bfe_i32 v8, v1, 14, 1
; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX10-NEXT:    v_lshlrev_b64 v[4:5], 14, v[2:3]
; GFX10-NEXT:    v_and_b32_e32 v4, v9, v7
; GFX10-NEXT:    v_bfe_i32 v9, v1, 15, 1
; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v6
; GFX10-NEXT:    v_lshlrev_b64 v[6:7], 15, v[2:3]
; GFX10-NEXT:    v_and_b32_e32 v6, v8, v5
; GFX10-NEXT:    v_bfe_i32 v8, v1, 16, 1
; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX10-NEXT:    v_lshlrev_b64 v[4:5], 16, v[2:3]
; GFX10-NEXT:    v_and_b32_e32 v4, v9, v7
; GFX10-NEXT:    v_bfe_i32 v9, v1, 17, 1
; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v6
; GFX10-NEXT:    v_lshlrev_b64 v[6:7], 17, v[2:3]
; GFX10-NEXT:    v_and_b32_e32 v6, v8, v5
; GFX10-NEXT:    v_bfe_i32 v8, v1, 18, 1
; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX10-NEXT:    v_lshlrev_b64 v[4:5], 18, v[2:3]
; GFX10-NEXT:    v_and_b32_e32 v4, v9, v7
; GFX10-NEXT:    v_bfe_i32 v9, v1, 19, 1
; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v6
; GFX10-NEXT:    v_lshlrev_b64 v[6:7], 19, v[2:3]
; GFX10-NEXT:    v_and_b32_e32 v6, v8, v5
; GFX10-NEXT:    v_bfe_i32 v8, v1, 20, 1
; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX10-NEXT:    v_lshlrev_b64 v[4:5], 20, v[2:3]
; GFX10-NEXT:    v_and_b32_e32 v4, v9, v7
; GFX10-NEXT:    v_bfe_i32 v9, v1, 21, 1
; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v6
; GFX10-NEXT:    v_lshlrev_b64 v[6:7], 21, v[2:3]
; GFX10-NEXT:    v_and_b32_e32 v6, v8, v5
; GFX10-NEXT:    v_bfe_i32 v8, v1, 22, 1
; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX10-NEXT:    v_lshlrev_b64 v[4:5], 22, v[2:3]
; GFX10-NEXT:    v_and_b32_e32 v4, v9, v7
; GFX10-NEXT:    v_bfe_i32 v9, v1, 23, 1
; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v6
; GFX10-NEXT:    v_lshlrev_b64 v[6:7], 23, v[2:3]
; GFX10-NEXT:    v_and_b32_e32 v6, v8, v5
; GFX10-NEXT:    v_bfe_i32 v8, v1, 24, 1
; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX10-NEXT:    v_lshlrev_b64 v[4:5], 24, v[2:3]
; GFX10-NEXT:    v_and_b32_e32 v4, v9, v7
; GFX10-NEXT:    v_bfe_i32 v9, v1, 25, 1
; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v6
; GFX10-NEXT:    v_lshlrev_b64 v[6:7], 25, v[2:3]
; GFX10-NEXT:    v_and_b32_e32 v6, v8, v5
; GFX10-NEXT:    v_bfe_i32 v8, v1, 26, 1
; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX10-NEXT:    v_lshlrev_b64 v[4:5], 26, v[2:3]
; GFX10-NEXT:    v_and_b32_e32 v4, v9, v7
; GFX10-NEXT:    v_bfe_i32 v9, v1, 27, 1
; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v6
; GFX10-NEXT:    v_lshlrev_b64 v[6:7], 27, v[2:3]
; GFX10-NEXT:    v_and_b32_e32 v6, v8, v5
; GFX10-NEXT:    v_bfe_i32 v8, v1, 28, 1
; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX10-NEXT:    v_lshlrev_b64 v[4:5], 28, v[2:3]
; GFX10-NEXT:    v_and_b32_e32 v4, v9, v7
; GFX10-NEXT:    v_bfe_i32 v9, v1, 29, 1
; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v6
; GFX10-NEXT:    v_lshlrev_b64 v[6:7], 29, v[2:3]
; GFX10-NEXT:    v_and_b32_e32 v6, v8, v5
; GFX10-NEXT:    v_bfe_i32 v8, v1, 30, 1
; GFX10-NEXT:    v_ashrrev_i32_e32 v1, 31, v1
; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX10-NEXT:    v_lshlrev_b64 v[4:5], 30, v[2:3]
; GFX10-NEXT:    v_and_b32_e32 v4, v9, v7
; GFX10-NEXT:    v_lshlrev_b64 v[2:3], 31, v[2:3]
; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v6
; GFX10-NEXT:    v_and_b32_e32 v2, v8, v5
; GFX10-NEXT:    v_and_b32_e32 v1, v1, v3
; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v2
; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v1
; GFX10-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; GFX10-NEXT:    s_endpgm
;
; GFX11-LABEL: test_clmulh_i32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-NEXT:    v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x3ff, v0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-NEXT:    global_load_b64 v[0:1], v0, s[2:3]
; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
; GFX11-NEXT:    s_mov_b32 s2, -1
; GFX11-NEXT:    s_waitcnt vmcnt(0)
; GFX11-NEXT:    v_mov_b32_e32 v2, v0
; GFX11-NEXT:    v_bfe_i32 v0, v1, 1, 1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT:    v_lshlrev_b64 v[4:5], 1, v[2:3]
; GFX11-NEXT:    v_lshlrev_b64 v[6:7], 2, v[2:3]
; GFX11-NEXT:    v_bfe_i32 v4, v1, 2, 1
; GFX11-NEXT:    v_lshlrev_b64 v[8:9], 3, v[2:3]
; GFX11-NEXT:    v_bfe_i32 v6, v1, 3, 1
; GFX11-NEXT:    v_bfe_i32 v8, v1, 4, 1
; GFX11-NEXT:    v_and_b32_e32 v0, v0, v5
; GFX11-NEXT:    v_and_b32_e32 v7, v4, v7
; GFX11-NEXT:    v_lshlrev_b64 v[4:5], 4, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v4, v6, v9
; GFX11-NEXT:    v_bfe_i32 v9, v1, 5, 1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_xor_b32_e32 v0, v0, v7
; GFX11-NEXT:    v_lshlrev_b64 v[6:7], 5, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v6, v8, v5
; GFX11-NEXT:    v_bfe_i32 v8, v1, 6, 1
; GFX11-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX11-NEXT:    v_lshlrev_b64 v[4:5], 6, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v4, v9, v7
; GFX11-NEXT:    v_bfe_i32 v9, v1, 7, 1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_xor_b32_e32 v0, v0, v6
; GFX11-NEXT:    v_lshlrev_b64 v[6:7], 7, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v6, v8, v5
; GFX11-NEXT:    v_bfe_i32 v8, v1, 8, 1
; GFX11-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX11-NEXT:    v_lshlrev_b64 v[4:5], 8, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v4, v9, v7
; GFX11-NEXT:    v_bfe_i32 v9, v1, 9, 1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_xor_b32_e32 v0, v0, v6
; GFX11-NEXT:    v_lshlrev_b64 v[6:7], 9, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v6, v8, v5
; GFX11-NEXT:    v_bfe_i32 v8, v1, 10, 1
; GFX11-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX11-NEXT:    v_lshlrev_b64 v[4:5], 10, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v4, v9, v7
; GFX11-NEXT:    v_bfe_i32 v9, v1, 11, 1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_xor_b32_e32 v0, v0, v6
; GFX11-NEXT:    v_lshlrev_b64 v[6:7], 11, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v6, v8, v5
; GFX11-NEXT:    v_bfe_i32 v8, v1, 12, 1
; GFX11-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX11-NEXT:    v_lshlrev_b64 v[4:5], 12, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v4, v9, v7
; GFX11-NEXT:    v_bfe_i32 v9, v1, 13, 1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_xor_b32_e32 v0, v0, v6
; GFX11-NEXT:    v_lshlrev_b64 v[6:7], 13, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v6, v8, v5
; GFX11-NEXT:    v_bfe_i32 v8, v1, 14, 1
; GFX11-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX11-NEXT:    v_lshlrev_b64 v[4:5], 14, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v4, v9, v7
; GFX11-NEXT:    v_bfe_i32 v9, v1, 15, 1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_xor_b32_e32 v0, v0, v6
; GFX11-NEXT:    v_lshlrev_b64 v[6:7], 15, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v6, v8, v5
; GFX11-NEXT:    v_bfe_i32 v8, v1, 16, 1
; GFX11-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX11-NEXT:    v_lshlrev_b64 v[4:5], 16, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v4, v9, v7
; GFX11-NEXT:    v_bfe_i32 v9, v1, 17, 1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_xor_b32_e32 v0, v0, v6
; GFX11-NEXT:    v_lshlrev_b64 v[6:7], 17, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v6, v8, v5
; GFX11-NEXT:    v_bfe_i32 v8, v1, 18, 1
; GFX11-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX11-NEXT:    v_lshlrev_b64 v[4:5], 18, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v4, v9, v7
; GFX11-NEXT:    v_bfe_i32 v9, v1, 19, 1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_xor_b32_e32 v0, v0, v6
; GFX11-NEXT:    v_lshlrev_b64 v[6:7], 19, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v6, v8, v5
; GFX11-NEXT:    v_bfe_i32 v8, v1, 20, 1
; GFX11-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX11-NEXT:    v_lshlrev_b64 v[4:5], 20, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v4, v9, v7
; GFX11-NEXT:    v_bfe_i32 v9, v1, 21, 1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_xor_b32_e32 v0, v0, v6
; GFX11-NEXT:    v_lshlrev_b64 v[6:7], 21, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v6, v8, v5
; GFX11-NEXT:    v_bfe_i32 v8, v1, 22, 1
; GFX11-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX11-NEXT:    v_lshlrev_b64 v[4:5], 22, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v4, v9, v7
; GFX11-NEXT:    v_bfe_i32 v9, v1, 23, 1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_xor_b32_e32 v0, v0, v6
; GFX11-NEXT:    v_lshlrev_b64 v[6:7], 23, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v6, v8, v5
; GFX11-NEXT:    v_bfe_i32 v8, v1, 24, 1
; GFX11-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX11-NEXT:    v_lshlrev_b64 v[4:5], 24, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v4, v9, v7
; GFX11-NEXT:    v_bfe_i32 v9, v1, 25, 1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_xor_b32_e32 v0, v0, v6
; GFX11-NEXT:    v_lshlrev_b64 v[6:7], 25, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v6, v8, v5
; GFX11-NEXT:    v_bfe_i32 v8, v1, 26, 1
; GFX11-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX11-NEXT:    v_lshlrev_b64 v[4:5], 26, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v4, v9, v7
; GFX11-NEXT:    v_bfe_i32 v9, v1, 27, 1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_xor_b32_e32 v0, v0, v6
; GFX11-NEXT:    v_lshlrev_b64 v[6:7], 27, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v6, v8, v5
; GFX11-NEXT:    v_bfe_i32 v8, v1, 28, 1
; GFX11-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX11-NEXT:    v_lshlrev_b64 v[4:5], 28, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v4, v9, v7
; GFX11-NEXT:    v_bfe_i32 v9, v1, 29, 1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT:    v_xor_b32_e32 v0, v0, v6
; GFX11-NEXT:    v_lshlrev_b64 v[6:7], 29, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v6, v8, v5
; GFX11-NEXT:    v_bfe_i32 v8, v1, 30, 1
; GFX11-NEXT:    v_ashrrev_i32_e32 v1, 31, v1
; GFX11-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX11-NEXT:    v_lshlrev_b64 v[4:5], 30, v[2:3]
; GFX11-NEXT:    v_and_b32_e32 v4, v9, v7
; GFX11-NEXT:    v_lshlrev_b64 v[2:3], 31, v[2:3]
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_xor_b32_e32 v0, v0, v6
; GFX11-NEXT:    v_and_b32_e32 v2, v8, v5
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_and_b32_e32 v1, v1, v3
; GFX11-NEXT:    v_xor_b32_e32 v0, v0, v4
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_xor_b32_e32 v0, v0, v2
; GFX11-NEXT:    v_xor_b32_e32 v0, v0, v1
; GFX11-NEXT:    buffer_store_b32 v0, off, s[0:3], 0
; GFX11-NEXT:    s_endpgm
;
; GFX12-LABEL: test_clmulh_i32:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    global_load_b64 v[0:1], v0, s[2:3]
; GFX12-NEXT:    s_mov_b32 s3, 0x31016000
; GFX12-NEXT:    s_mov_b32 s2, -1
; GFX12-NEXT:    s_wait_loadcnt 0x0
; GFX12-NEXT:    v_and_b32_e32 v26, 0x11111111, v1
; GFX12-NEXT:    v_and_b32_e32 v22, 0x22222222, v0
; GFX12-NEXT:    v_and_b32_e32 v23, 0x22222222, v1
; GFX12-NEXT:    v_and_b32_e32 v24, 0x11111111, v0
; GFX12-NEXT:    v_and_b32_e32 v27, 0x88888888, v1
; GFX12-NEXT:    v_and_b32_e32 v28, 0x44444444, v0
; GFX12-NEXT:    v_and_b32_e32 v25, 0x44444444, v1
; GFX12-NEXT:    v_and_b32_e32 v29, 0x88888888, v0
; GFX12-NEXT:    v_mad_co_u64_u32 v[0:1], null, v22, v26, 0
; GFX12-NEXT:    v_mad_co_u64_u32 v[2:3], null, v24, v23, 0
; GFX12-NEXT:    v_mad_co_u64_u32 v[8:9], null, v22, v27, 0
; GFX12-NEXT:    v_mad_co_u64_u32 v[10:11], null, v24, v26, 0
; GFX12-NEXT:    v_mad_co_u64_u32 v[4:5], null, v28, v27, 0
; GFX12-NEXT:    v_mad_co_u64_u32 v[6:7], null, v29, v25, 0
; GFX12-NEXT:    v_mad_co_u64_u32 v[12:13], null, v28, v25, 0
; GFX12-NEXT:    v_mad_co_u64_u32 v[14:15], null, v29, v23, 0
; GFX12-NEXT:    v_mad_co_u64_u32 v[16:17], null, v22, v25, 0
; GFX12-NEXT:    v_mad_co_u64_u32 v[18:19], null, v24, v27, 0
; GFX12-NEXT:    v_mad_co_u64_u32 v[20:21], null, v28, v23, 0
; GFX12-NEXT:    v_mad_co_u64_u32 v[22:23], null, v22, v23, 0
; GFX12-NEXT:    v_mad_co_u64_u32 v[24:25], null, v24, v25, 0
; GFX12-NEXT:    v_xor_b32_e32 v4, v3, v1
; GFX12-NEXT:    v_xor_b32_e32 v6, v11, v9
; GFX12-NEXT:    v_mad_co_u64_u32 v[2:3], null, v28, v26, 0
; GFX12-NEXT:    v_mad_co_u64_u32 v[0:1], null, v29, v26, 0
; GFX12-NEXT:    v_xor_b32_e32 v0, v19, v17
; GFX12-NEXT:    v_xor_b32_e32 v2, v4, v5
; GFX12-NEXT:    v_xor_b32_e32 v6, v6, v13
; GFX12-NEXT:    v_xor_b32_e32 v8, v25, v23
; GFX12-NEXT:    v_mad_co_u64_u32 v[4:5], null, v29, v27, 0
; GFX12-NEXT:    v_xor_b32_e32 v0, v0, v21
; GFX12-NEXT:    v_xor_b32_e32 v2, v2, v7
; GFX12-NEXT:    v_xor_b32_e32 v4, v6, v15
; GFX12-NEXT:    v_xor_b32_e32 v3, v8, v3
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-NEXT:    v_xor_b32_e32 v0, v0, v1
; GFX12-NEXT:    v_and_b32_e32 v1, 0x22222222, v2
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-NEXT:    v_and_b32_e32 v2, 0x11111111, v4
; GFX12-NEXT:    v_xor_b32_e32 v3, v3, v5
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-NEXT:    v_and_b32_e32 v0, 0x88888888, v0
; GFX12-NEXT:    v_or_b32_e32 v1, v2, v1
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT:    v_and_b32_e32 v2, 0x44444444, v3
; GFX12-NEXT:    v_or3_b32 v0, v1, v2, v0
; GFX12-NEXT:    buffer_store_b32 v0, off, s[0:3], null
; GFX12-NEXT:    s_endpgm
;
; GFX1250-LABEL: test_clmulh_i32:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-NEXT:    v_nop
; GFX1250-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
; GFX1250-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT:    v_lshlrev_b32_e32 v26, 2, v0
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    global_load_b64 v[0:1], v26, s[2:3]
; GFX1250-NEXT:    s_wait_xcnt 0x0
; GFX1250-NEXT:    s_mov_b32 s3, 0x31016000
; GFX1250-NEXT:    s_mov_b32 s2, -1
; GFX1250-NEXT:    s_wait_loadcnt 0x0
; GFX1250-NEXT:    v_and_b32_e32 v27, 0x11111111, v1
; GFX1250-NEXT:    v_and_b32_e32 v22, 0x22222222, v0
; GFX1250-NEXT:    v_and_b32_e32 v23, 0x22222222, v1
; GFX1250-NEXT:    v_and_b32_e32 v24, 0x11111111, v0
; GFX1250-NEXT:    v_and_b32_e32 v28, 0x88888888, v1
; GFX1250-NEXT:    v_and_b32_e32 v29, 0x44444444, v0
; GFX1250-NEXT:    v_and_b32_e32 v25, 0x44444444, v1
; GFX1250-NEXT:    v_and_b32_e32 v30, 0x88888888, v0
; GFX1250-NEXT:    v_mad_nc_u64_u32 v[0:1], v22, v27, 0
; GFX1250-NEXT:    v_mad_nc_u64_u32 v[2:3], v24, v23, 0
; GFX1250-NEXT:    v_mad_nc_u64_u32 v[8:9], v22, v28, 0
; GFX1250-NEXT:    v_mad_nc_u64_u32 v[10:11], v24, v27, 0
; GFX1250-NEXT:    v_mad_nc_u64_u32 v[4:5], v29, v28, 0
; GFX1250-NEXT:    v_mad_nc_u64_u32 v[6:7], v30, v25, 0
; GFX1250-NEXT:    v_mad_nc_u64_u32 v[12:13], v29, v25, 0
; GFX1250-NEXT:    v_mad_nc_u64_u32 v[14:15], v30, v23, 0
; GFX1250-NEXT:    v_mad_nc_u64_u32 v[16:17], v22, v25, 0
; GFX1250-NEXT:    v_mad_nc_u64_u32 v[18:19], v24, v28, 0
; GFX1250-NEXT:    v_mad_nc_u64_u32 v[20:21], v29, v23, 0
; GFX1250-NEXT:    v_mad_nc_u64_u32 v[22:23], v22, v23, 0
; GFX1250-NEXT:    v_mad_nc_u64_u32 v[24:25], v24, v25, 0
; GFX1250-NEXT:    v_xor_b32_e32 v4, v3, v1
; GFX1250-NEXT:    v_xor_b32_e32 v6, v11, v9
; GFX1250-NEXT:    v_mad_nc_u64_u32 v[2:3], v29, v27, 0
; GFX1250-NEXT:    v_mad_nc_u64_u32 v[0:1], v30, v27, 0
; GFX1250-NEXT:    v_xor_b32_e32 v0, v19, v17
; GFX1250-NEXT:    v_xor_b32_e32 v2, v4, v5
; GFX1250-NEXT:    v_xor_b32_e32 v6, v6, v13
; GFX1250-NEXT:    v_xor_b32_e32 v8, v25, v23
; GFX1250-NEXT:    v_mad_nc_u64_u32 v[4:5], v30, v28, 0
; GFX1250-NEXT:    v_xor_b32_e32 v0, v0, v21
; GFX1250-NEXT:    v_xor_b32_e32 v2, v2, v7
; GFX1250-NEXT:    v_xor_b32_e32 v4, v6, v15
; GFX1250-NEXT:    v_xor_b32_e32 v3, v8, v3
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1250-NEXT:    v_xor_b32_e32 v0, v0, v1
; GFX1250-NEXT:    v_and_b32_e32 v1, 0x22222222, v2
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1250-NEXT:    v_and_b32_e32 v2, 0x11111111, v4
; GFX1250-NEXT:    v_xor_b32_e32 v3, v3, v5
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-NEXT:    v_and_b32_e32 v0, 0x88888888, v0
; GFX1250-NEXT:    v_or_b32_e32 v1, v2, v1
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-NEXT:    v_and_b32_e32 v2, 0x44444444, v3
; GFX1250-NEXT:    v_or3_b32 v0, v1, v2, v0
; GFX1250-NEXT:    buffer_store_b32 v0, off, s[0:3], null
; GFX1250-NEXT:    s_endpgm
;
; EG-LABEL: test_clmulh_i32:
; EG:       ; %bb.0:
; EG-NEXT:    ALU 2, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT:    TEX 0 @6
; EG-NEXT:    ALU 92, @11, KC0[], KC1[]
; EG-NEXT:    ALU 53, @104, KC0[CB0:0-32], KC1[]
; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
; EG-NEXT:    CF_END
; EG-NEXT:    Fetch clause starting at 6:
; EG-NEXT:     VTX_READ_64 T0.XY, T0.X, 0, #1
; EG-NEXT:    ALU clause starting at 8:
; EG-NEXT:     LSHL * T0.W, T0.X, literal.x,
; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
; EG-NEXT:     ADD_INT * T0.X, KC0[2].Z, PV.W,
; EG-NEXT:    ALU clause starting at 11:
; EG-NEXT:     AND_INT T0.W, T0.X, literal.x,
; EG-NEXT:     LSHR * T1.W, T0.X, literal.y,
; EG-NEXT:    65280(9.147676e-41), 8(1.121039e-44)
; EG-NEXT:     AND_INT T1.X, PS, literal.x,
; EG-NEXT:     LSHR T1.Y, T0.X, literal.y,
; EG-NEXT:     LSHL T0.Z, PV.W, literal.z,
; EG-NEXT:     AND_INT T0.W, T0.Y, literal.x,
; EG-NEXT:     LSHR * T1.W, T0.Y, literal.z,
; EG-NEXT:    65280(9.147676e-41), 24(3.363116e-44)
; EG-NEXT:    8(1.121039e-44), 0(0.000000e+00)
; EG-NEXT:     LSHL T0.X, T0.X, literal.x,
; EG-NEXT:     AND_INT T2.Y, PS, literal.y,
; EG-NEXT:     LSHR T1.Z, T0.Y, literal.x,
; EG-NEXT:     LSHL T0.W, PV.W, literal.z,
; EG-NEXT:     LSHL * T1.W, T0.Y, literal.x,
; EG-NEXT:    24(3.363116e-44), 65280(9.147676e-41)
; EG-NEXT:    8(1.121039e-44), 0(0.000000e+00)
; EG-NEXT:     OR_INT T0.Y, PS, PV.W,
; EG-NEXT:     OR_INT T1.Z, PV.Y, PV.Z,
; EG-NEXT:     OR_INT T0.W, PV.X, T0.Z,
; EG-NEXT:     OR_INT * T1.W, T1.X, T1.Y,
; EG-NEXT:     OR_INT T0.W, PV.W, PS,
; EG-NEXT:     OR_INT * T1.W, PV.Y, PV.Z,
; EG-NEXT:     AND_INT T0.Y, PS, literal.x,
; EG-NEXT:     LSHR T0.Z, PS, literal.y,
; EG-NEXT:     AND_INT T1.W, PV.W, literal.x,
; EG-NEXT:     LSHR * T0.W, PV.W, literal.y,
; EG-NEXT:    252645135(7.053345e-30), 4(5.605194e-45)
; EG-NEXT:     AND_INT T1.Y, PS, literal.x,
; EG-NEXT:     LSHL T1.Z, PV.W, literal.y,
; EG-NEXT:     AND_INT T0.W, PV.Z, literal.x,
; EG-NEXT:     LSHL * T1.W, PV.Y, literal.y,
; EG-NEXT:    252645135(7.053345e-30), 4(5.605194e-45)
; EG-NEXT:     OR_INT T0.W, PV.W, PS,
; EG-NEXT:     OR_INT * T1.W, PV.Y, PV.Z,
; EG-NEXT:     AND_INT T0.Y, PS, literal.x,
; EG-NEXT:     LSHR T0.Z, PS, literal.y,
; EG-NEXT:     AND_INT T1.W, PV.W, literal.x,
; EG-NEXT:     LSHR * T0.W, PV.W, literal.y,
; EG-NEXT:    858993459(4.172325e-08), 2(2.802597e-45)
; EG-NEXT:     AND_INT T1.Y, PS, literal.x,
; EG-NEXT:     LSHL T1.Z, PV.W, literal.y,
; EG-NEXT:     AND_INT T0.W, PV.Z, literal.x,
; EG-NEXT:     LSHL * T1.W, PV.Y, literal.y,
; EG-NEXT:    858993459(4.172325e-08), 2(2.802597e-45)
; EG-NEXT:     OR_INT T0.W, PV.W, PS,
; EG-NEXT:     OR_INT * T1.W, PV.Y, PV.Z,
; EG-NEXT:     AND_INT T0.Y, PS, literal.x,
; EG-NEXT:     LSHR T0.Z, PS, 1,
; EG-NEXT:     AND_INT T1.W, PV.W, literal.x,
; EG-NEXT:     LSHR * T0.W, PV.W, 1,
; EG-NEXT:    1431655765(1.466015e+13), 0(0.000000e+00)
; EG-NEXT:     AND_INT T1.Y, PS, literal.x,
; EG-NEXT:     LSHL T1.Z, PV.W, 1,
; EG-NEXT:     AND_INT T0.W, PV.Z, literal.x,
; EG-NEXT:     LSHL * T1.W, PV.Y, 1,
; EG-NEXT:    1431655765(1.466015e+13), 0(0.000000e+00)
; EG-NEXT:     OR_INT T0.W, PV.W, PS,
; EG-NEXT:     OR_INT * T1.W, PV.Y, PV.Z,
; EG-NEXT:     AND_INT T2.W, PS, literal.x,
; EG-NEXT:     AND_INT * T3.W, PV.W, literal.y,
; EG-NEXT:    1145324612(7.850667e+02), 572662306(2.197316e-18)
; EG-NEXT:     AND_INT T4.W, T0.W, literal.x,
; EG-NEXT:     MULLO_INT * T0.X, PV.W, PS,
; EG-NEXT:    286331153(1.144374e-28), 0(0.000000e+00)
; EG-NEXT:     AND_INT T5.W, T1.W, literal.x,
; EG-NEXT:     MULLO_INT * T0.Y, T2.W, PV.W,
; EG-NEXT:    -2004318072(-8.217301e-34), 0(0.000000e+00)
; EG-NEXT:     AND_INT T6.W, T0.W, literal.x,
; EG-NEXT:     MULLO_INT * T0.Z, PV.W, T3.W,
; EG-NEXT:    1145324612(7.850667e+02), 0(0.000000e+00)
; EG-NEXT:     AND_INT T1.Z, T0.W, literal.x,
; EG-NEXT:     AND_INT T0.W, T1.W, literal.y, BS:VEC_120/SCL_212
; EG-NEXT:     MULLO_INT * T1.X, T5.W, PV.W,
; EG-NEXT:    -2004318072(-8.217301e-34), 286331153(1.144374e-28)
; EG-NEXT:     MULLO_INT * T1.Y, PV.W, PV.Z,
; EG-NEXT:     MULLO_INT * T2.X, T2.W, T1.Z,
; EG-NEXT:     MULLO_INT * T2.Y, T2.W, T6.W,
; EG-NEXT:     MULLO_INT * T2.Z, T0.W, T6.W,
; EG-NEXT:     AND_INT T1.W, T1.W, literal.x,
; EG-NEXT:     MULLO_INT * T2.W, T0.W, T4.W,
; EG-NEXT:    572662306(2.197316e-18), 0(0.000000e+00)
; EG-NEXT:     MULLO_INT * T3.X, PV.W, T1.Z,
; EG-NEXT:     MULLO_INT * T0.W, T0.W, T3.W,
; EG-NEXT:     MULLO_INT * T3.Y, T1.W, T4.W,
; EG-NEXT:     XOR_INT T3.Z, T0.W, PS,
; EG-NEXT:     XOR_INT * T0.W, T2.W, T3.X, BS:VEC_120/SCL_212
; EG-NEXT:     MULLO_INT * T2.W, T1.W, T3.W,
; EG-NEXT:     XOR_INT T3.Y, T2.Z, PS,
; EG-NEXT:     XOR_INT T2.Z, T0.W, T2.Y,
; EG-NEXT:     XOR_INT T0.W, T3.Z, T2.X, BS:VEC_120/SCL_212
; EG-NEXT:     MULLO_INT * T1.W, T1.W, T6.W,
; EG-NEXT:     XOR_INT * T2.X, T1.Y, PS,
; EG-NEXT:    ALU clause starting at 104:
; EG-NEXT:     XOR_INT T1.Y, T0.W, T1.X,
; EG-NEXT:     XOR_INT T0.Z, T2.Z, T0.Z, BS:VEC_021/SCL_122
; EG-NEXT:     XOR_INT T0.W, T3.Y, T0.Y,
; EG-NEXT:     MULLO_INT * T0.Y, T5.W, T1.Z,
; EG-NEXT:     XOR_INT T1.X, PV.W, PS,
; EG-NEXT:     AND_INT T0.Y, PV.Z, literal.x,
; EG-NEXT:     AND_INT T0.Z, PV.Y, literal.y,
; EG-NEXT:     XOR_INT T0.W, T2.X, T0.X,
; EG-NEXT:     MULLO_INT * T0.X, T5.W, T4.W,
; EG-NEXT:    286331153(1.144374e-28), 572662306(2.197316e-18)
; EG-NEXT:     XOR_INT T1.Z, PV.W, PS,
; EG-NEXT:     OR_INT T0.W, PV.Y, PV.Z,
; EG-NEXT:     AND_INT * T1.W, PV.X, literal.x,
; EG-NEXT:    1145324612(7.850667e+02), 0(0.000000e+00)
; EG-NEXT:     OR_INT T0.W, PV.W, PS,
; EG-NEXT:     AND_INT * T1.W, PV.Z, literal.x,
; EG-NEXT:    -2004318072(-8.217301e-34), 0(0.000000e+00)
; EG-NEXT:     OR_INT * T0.W, PV.W, PS,
; EG-NEXT:     AND_INT T1.W, PV.W, literal.x,
; EG-NEXT:     LSHR * T2.W, PV.W, literal.y,
; EG-NEXT:    65280(9.147676e-41), 8(1.121039e-44)
; EG-NEXT:     AND_INT T0.Y, PS, literal.x,
; EG-NEXT:     LSHR T0.Z, T0.W, literal.y,
; EG-NEXT:     LSHL T1.W, PV.W, literal.z,
; EG-NEXT:     LSHL * T0.W, T0.W, literal.y,
; EG-NEXT:    65280(9.147676e-41), 24(3.363116e-44)
; EG-NEXT:    8(1.121039e-44), 0(0.000000e+00)
; EG-NEXT:     OR_INT T0.W, PS, PV.W,
; EG-NEXT:     OR_INT * T1.W, PV.Y, PV.Z,
; EG-NEXT:     OR_INT * T0.W, PV.W, PS,
; EG-NEXT:     AND_INT T1.W, PV.W, literal.x,
; EG-NEXT:     LSHR * T0.W, PV.W, literal.y,
; EG-NEXT:    252645135(7.053345e-30), 4(5.605194e-45)
; EG-NEXT:     AND_INT T0.W, PS, literal.x,
; EG-NEXT:     LSHL * T1.W, PV.W, literal.y,
; EG-NEXT:    252645135(7.053345e-30), 4(5.605194e-45)
; EG-NEXT:     OR_INT * T0.W, PV.W, PS,
; EG-NEXT:     AND_INT T1.W, PV.W, literal.x,
; EG-NEXT:     LSHR * T0.W, PV.W, literal.y,
; EG-NEXT:    858993459(4.172325e-08), 2(2.802597e-45)
; EG-NEXT:     AND_INT T0.W, PS, literal.x,
; EG-NEXT:     LSHL * T1.W, PV.W, literal.y,
; EG-NEXT:    858993459(4.172325e-08), 2(2.802597e-45)
; EG-NEXT:     OR_INT * T0.W, PV.W, PS,
; EG-NEXT:     AND_INT T1.W, PV.W, literal.x,
; EG-NEXT:     LSHR * T0.W, PV.W, 1,
; EG-NEXT:    1431655765(1.466015e+13), 0(0.000000e+00)
; EG-NEXT:     AND_INT T0.W, PS, literal.x,
; EG-NEXT:     LSHL * T1.W, PV.W, 1,
; EG-NEXT:    1431655764(1.466015e+13), 0(0.000000e+00)
; EG-NEXT:     OR_INT * T0.W, PV.W, PS,
; EG-NEXT:     LSHR T0.X, PV.W, 1,
; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
  %tid = call i32 @llvm.amdgcn.workitem.id.x()
  %in.tid = getelementptr inbounds i32, ptr addrspace(1) %in, i32 %tid
  %b_ptr = getelementptr i32, ptr addrspace(1) %in.tid, i32 1
  %a = load i32, ptr addrspace(1) %in.tid
  %b = load i32, ptr addrspace(1) %b_ptr
  %a.ext = zext i32 %a to i64
  %b.ext = zext i32 %b to i64
  %clmul = call i64 @llvm.clmul.i64(i64 %a.ext, i64 %b.ext)
  %res.ext = lshr i64 %clmul, 32
  %res = trunc i64 %res.ext to i32
  store i32 %res, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @test_clmul_i32_uniform(ptr addrspace(1) %out, i32 %a, i32 %b) {
; SI-LABEL: test_clmul_i32_uniform:
; SI:       ; %bb.0:
; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    s_mov_b64 s[4:5], s[2:3]
; SI-NEXT:    s_and_b32 s6, s5, 0x11111111
; SI-NEXT:    s_and_b32 s7, s4, 0x22222222
; SI-NEXT:    s_and_b32 s8, s5, 0x22222222
; SI-NEXT:    s_and_b32 s10, s4, 0x11111111
; SI-NEXT:    s_mul_i32 s9, s7, s6
; SI-NEXT:    s_mul_i32 s11, s10, s8
; SI-NEXT:    s_xor_b32 s9, s11, s9
; SI-NEXT:    s_and_b32 s11, s5, 0x88888888
; SI-NEXT:    s_and_b32 s12, s4, 0x44444444
; SI-NEXT:    s_mul_i32 s13, s12, s11
; SI-NEXT:    s_and_b32 s5, s5, 0x44444444
; SI-NEXT:    s_and_b32 s4, s4, 0x88888888
; SI-NEXT:    s_xor_b32 s9, s9, s13
; SI-NEXT:    s_mul_i32 s13, s4, s5
; SI-NEXT:    s_xor_b32 s9, s9, s13
; SI-NEXT:    s_mul_i32 s13, s7, s11
; SI-NEXT:    s_mul_i32 s14, s10, s6
; SI-NEXT:    s_xor_b32 s13, s14, s13
; SI-NEXT:    s_mul_i32 s14, s12, s5
; SI-NEXT:    s_xor_b32 s13, s13, s14
; SI-NEXT:    s_mul_i32 s14, s4, s8
; SI-NEXT:    s_xor_b32 s13, s13, s14
; SI-NEXT:    s_and_b32 s9, s9, 0x22222222
; SI-NEXT:    s_and_b32 s13, s13, 0x11111111
; SI-NEXT:    s_or_b32 s9, s13, s9
; SI-NEXT:    s_mul_i32 s13, s7, s8
; SI-NEXT:    s_mul_i32 s14, s10, s5
; SI-NEXT:    s_xor_b32 s13, s14, s13
; SI-NEXT:    s_mul_i32 s14, s12, s6
; SI-NEXT:    s_mul_i32 s7, s7, s5
; SI-NEXT:    s_mul_i32 s10, s10, s11
; SI-NEXT:    s_xor_b32 s13, s13, s14
; SI-NEXT:    s_mul_i32 s14, s4, s11
; SI-NEXT:    s_xor_b32 s5, s10, s7
; SI-NEXT:    s_mul_i32 s12, s12, s8
; SI-NEXT:    s_xor_b32 s13, s13, s14
; SI-NEXT:    s_xor_b32 s5, s5, s12
; SI-NEXT:    s_mul_i32 s4, s4, s6
; SI-NEXT:    s_and_b32 s13, s13, 0x44444444
; SI-NEXT:    s_xor_b32 s4, s5, s4
; SI-NEXT:    s_or_b32 s9, s9, s13
; SI-NEXT:    s_and_b32 s4, s4, 0x88888888
; SI-NEXT:    s_or_b32 s4, s9, s4
; SI-NEXT:    s_mov_b32 s3, 0xf000
; SI-NEXT:    s_mov_b32 s2, -1
; SI-NEXT:    v_mov_b32_e32 v0, s4
; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT:    s_endpgm
;
; VI-LABEL: test_clmul_i32_uniform:
; VI:       ; %bb.0:
; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT:    s_waitcnt lgkmcnt(0)
; VI-NEXT:    s_mov_b64 s[4:5], s[2:3]
; VI-NEXT:    s_and_b32 s6, s5, 0x11111111
; VI-NEXT:    s_and_b32 s7, s4, 0x22222222
; VI-NEXT:    s_and_b32 s8, s5, 0x22222222
; VI-NEXT:    s_and_b32 s10, s4, 0x11111111
; VI-NEXT:    s_mul_i32 s9, s7, s6
; VI-NEXT:    s_mul_i32 s11, s10, s8
; VI-NEXT:    s_xor_b32 s9, s11, s9
; VI-NEXT:    s_and_b32 s11, s5, 0x88888888
; VI-NEXT:    s_and_b32 s12, s4, 0x44444444
; VI-NEXT:    s_mul_i32 s13, s12, s11
; VI-NEXT:    s_and_b32 s5, s5, 0x44444444
; VI-NEXT:    s_and_b32 s4, s4, 0x88888888
; VI-NEXT:    s_xor_b32 s9, s9, s13
; VI-NEXT:    s_mul_i32 s13, s4, s5
; VI-NEXT:    s_xor_b32 s9, s9, s13
; VI-NEXT:    s_mul_i32 s13, s7, s11
; VI-NEXT:    s_mul_i32 s14, s10, s6
; VI-NEXT:    s_xor_b32 s13, s14, s13
; VI-NEXT:    s_mul_i32 s14, s12, s5
; VI-NEXT:    s_xor_b32 s13, s13, s14
; VI-NEXT:    s_mul_i32 s14, s4, s8
; VI-NEXT:    s_xor_b32 s13, s13, s14
; VI-NEXT:    s_and_b32 s9, s9, 0x22222222
; VI-NEXT:    s_and_b32 s13, s13, 0x11111111
; VI-NEXT:    s_or_b32 s9, s13, s9
; VI-NEXT:    s_mul_i32 s13, s7, s8
; VI-NEXT:    s_mul_i32 s14, s10, s5
; VI-NEXT:    s_xor_b32 s13, s14, s13
; VI-NEXT:    s_mul_i32 s14, s12, s6
; VI-NEXT:    s_mul_i32 s7, s7, s5
; VI-NEXT:    s_mul_i32 s10, s10, s11
; VI-NEXT:    s_xor_b32 s13, s13, s14
; VI-NEXT:    s_mul_i32 s14, s4, s11
; VI-NEXT:    s_xor_b32 s5, s10, s7
; VI-NEXT:    s_mul_i32 s12, s12, s8
; VI-NEXT:    s_xor_b32 s13, s13, s14
; VI-NEXT:    s_xor_b32 s5, s5, s12
; VI-NEXT:    s_mul_i32 s4, s4, s6
; VI-NEXT:    s_and_b32 s13, s13, 0x44444444
; VI-NEXT:    s_xor_b32 s4, s5, s4
; VI-NEXT:    s_or_b32 s9, s9, s13
; VI-NEXT:    s_and_b32 s4, s4, 0x88888888
; VI-NEXT:    s_or_b32 s4, s9, s4
; VI-NEXT:    s_mov_b32 s3, 0xf000
; VI-NEXT:    s_mov_b32 s2, -1
; VI-NEXT:    v_mov_b32_e32 v0, s4
; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT:    s_endpgm
;
; GFX9-LABEL: test_clmul_i32_uniform:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-NEXT:    s_mov_b64 s[4:5], s[2:3]
; GFX9-NEXT:    s_and_b32 s6, s5, 0x11111111
; GFX9-NEXT:    s_and_b32 s7, s4, 0x22222222
; GFX9-NEXT:    s_and_b32 s8, s5, 0x22222222
; GFX9-NEXT:    s_and_b32 s10, s4, 0x11111111
; GFX9-NEXT:    s_mul_i32 s9, s7, s6
; GFX9-NEXT:    s_mul_i32 s11, s10, s8
; GFX9-NEXT:    s_xor_b32 s9, s11, s9
; GFX9-NEXT:    s_and_b32 s11, s5, 0x88888888
; GFX9-NEXT:    s_and_b32 s12, s4, 0x44444444
; GFX9-NEXT:    s_mul_i32 s13, s12, s11
; GFX9-NEXT:    s_and_b32 s5, s5, 0x44444444
; GFX9-NEXT:    s_and_b32 s4, s4, 0x88888888
; GFX9-NEXT:    s_xor_b32 s9, s9, s13
; GFX9-NEXT:    s_mul_i32 s13, s4, s5
; GFX9-NEXT:    s_xor_b32 s9, s9, s13
; GFX9-NEXT:    s_mul_i32 s13, s7, s11
; GFX9-NEXT:    s_mul_i32 s14, s10, s6
; GFX9-NEXT:    s_xor_b32 s13, s14, s13
; GFX9-NEXT:    s_mul_i32 s14, s12, s5
; GFX9-NEXT:    s_xor_b32 s13, s13, s14
; GFX9-NEXT:    s_mul_i32 s14, s4, s8
; GFX9-NEXT:    s_xor_b32 s13, s13, s14
; GFX9-NEXT:    s_and_b32 s9, s9, 0x22222222
; GFX9-NEXT:    s_and_b32 s13, s13, 0x11111111
; GFX9-NEXT:    s_or_b32 s9, s13, s9
; GFX9-NEXT:    s_mul_i32 s13, s7, s8
; GFX9-NEXT:    s_mul_i32 s14, s10, s5
; GFX9-NEXT:    s_xor_b32 s13, s14, s13
; GFX9-NEXT:    s_mul_i32 s14, s12, s6
; GFX9-NEXT:    s_mul_i32 s7, s7, s5
; GFX9-NEXT:    s_mul_i32 s10, s10, s11
; GFX9-NEXT:    s_xor_b32 s13, s13, s14
; GFX9-NEXT:    s_mul_i32 s14, s4, s11
; GFX9-NEXT:    s_xor_b32 s5, s10, s7
; GFX9-NEXT:    s_mul_i32 s12, s12, s8
; GFX9-NEXT:    s_xor_b32 s13, s13, s14
; GFX9-NEXT:    s_xor_b32 s5, s5, s12
; GFX9-NEXT:    s_mul_i32 s4, s4, s6
; GFX9-NEXT:    s_and_b32 s13, s13, 0x44444444
; GFX9-NEXT:    s_xor_b32 s4, s5, s4
; GFX9-NEXT:    s_or_b32 s9, s9, s13
; GFX9-NEXT:    s_and_b32 s4, s4, 0x88888888
; GFX9-NEXT:    s_or_b32 s4, s9, s4
; GFX9-NEXT:    s_mov_b32 s3, 0xf000
; GFX9-NEXT:    s_mov_b32 s2, -1
; GFX9-NEXT:    v_mov_b32_e32 v0, s4
; GFX9-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; GFX9-NEXT:    s_endpgm
;
; GFX10-LABEL: test_clmul_i32_uniform:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
; GFX10-NEXT:    s_and_b32 s4, s3, 0x11111111
; GFX10-NEXT:    s_and_b32 s5, s2, 0x22222222
; GFX10-NEXT:    s_and_b32 s6, s3, 0x22222222
; GFX10-NEXT:    s_and_b32 s7, s2, 0x11111111
; GFX10-NEXT:    s_and_b32 s8, s3, 0x88888888
; GFX10-NEXT:    s_and_b32 s9, s2, 0x44444444
; GFX10-NEXT:    s_and_b32 s3, s3, 0x44444444
; GFX10-NEXT:    s_and_b32 s2, s2, 0x88888888
; GFX10-NEXT:    s_mul_i32 s10, s5, s4
; GFX10-NEXT:    s_mul_i32 s11, s7, s6
; GFX10-NEXT:    s_mul_i32 s14, s5, s8
; GFX10-NEXT:    s_mul_i32 s15, s7, s4
; GFX10-NEXT:    s_mul_i32 s12, s9, s8
; GFX10-NEXT:    s_mul_i32 s13, s2, s3
; GFX10-NEXT:    s_mul_i32 s16, s9, s3
; GFX10-NEXT:    s_mul_i32 s18, s5, s6
; GFX10-NEXT:    s_mul_i32 s19, s7, s3
; GFX10-NEXT:    s_mul_i32 s21, s2, s8
; GFX10-NEXT:    s_mul_i32 s5, s5, s3
; GFX10-NEXT:    s_mul_i32 s7, s7, s8
; GFX10-NEXT:    s_xor_b32 s3, s11, s10
; GFX10-NEXT:    s_xor_b32 s8, s15, s14
; GFX10-NEXT:    s_mul_i32 s17, s2, s6
; GFX10-NEXT:    s_mul_i32 s20, s9, s4
; GFX10-NEXT:    s_xor_b32 s10, s19, s18
; GFX10-NEXT:    s_xor_b32 s5, s7, s5
; GFX10-NEXT:    s_xor_b32 s3, s3, s12
; GFX10-NEXT:    s_xor_b32 s7, s8, s16
; GFX10-NEXT:    s_xor_b32 s3, s3, s13
; GFX10-NEXT:    s_xor_b32 s7, s7, s17
; GFX10-NEXT:    s_xor_b32 s8, s10, s20
; GFX10-NEXT:    s_mul_i32 s9, s9, s6
; GFX10-NEXT:    s_and_b32 s3, s3, 0x22222222
; GFX10-NEXT:    s_and_b32 s7, s7, 0x11111111
; GFX10-NEXT:    s_xor_b32 s6, s8, s21
; GFX10-NEXT:    s_xor_b32 s5, s5, s9
; GFX10-NEXT:    s_mul_i32 s2, s2, s4
; GFX10-NEXT:    s_or_b32 s3, s7, s3
; GFX10-NEXT:    s_and_b32 s4, s6, 0x44444444
; GFX10-NEXT:    s_xor_b32 s2, s5, s2
; GFX10-NEXT:    s_or_b32 s3, s3, s4
; GFX10-NEXT:    s_and_b32 s2, s2, 0x88888888
; GFX10-NEXT:    s_or_b32 s2, s3, s2
; GFX10-NEXT:    s_mov_b32 s3, 0x31016000
; GFX10-NEXT:    v_mov_b32_e32 v0, s2
; GFX10-NEXT:    s_mov_b32 s2, -1
; GFX10-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; GFX10-NEXT:    s_endpgm
;
; GFX11-LABEL: test_clmul_i32_uniform:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-NEXT:    s_and_b32 s4, s3, 0x11111111
; GFX11-NEXT:    s_and_b32 s5, s2, 0x22222222
; GFX11-NEXT:    s_and_b32 s6, s3, 0x22222222
; GFX11-NEXT:    s_and_b32 s7, s2, 0x11111111
; GFX11-NEXT:    s_and_b32 s8, s3, 0x88888888
; GFX11-NEXT:    s_and_b32 s9, s2, 0x44444444
; GFX11-NEXT:    s_and_b32 s3, s3, 0x44444444
; GFX11-NEXT:    s_and_b32 s2, s2, 0x88888888
; GFX11-NEXT:    s_mul_i32 s10, s5, s4
; GFX11-NEXT:    s_mul_i32 s11, s7, s6
; GFX11-NEXT:    s_mul_i32 s14, s5, s8
; GFX11-NEXT:    s_mul_i32 s15, s7, s4
; GFX11-NEXT:    s_mul_i32 s12, s9, s8
; GFX11-NEXT:    s_mul_i32 s13, s2, s3
; GFX11-NEXT:    s_mul_i32 s16, s9, s3
; GFX11-NEXT:    s_mul_i32 s18, s5, s6
; GFX11-NEXT:    s_mul_i32 s19, s7, s3
; GFX11-NEXT:    s_mul_i32 s21, s2, s8
; GFX11-NEXT:    s_mul_i32 s5, s5, s3
; GFX11-NEXT:    s_mul_i32 s7, s7, s8
; GFX11-NEXT:    s_xor_b32 s3, s11, s10
; GFX11-NEXT:    s_xor_b32 s8, s15, s14
; GFX11-NEXT:    s_mul_i32 s17, s2, s6
; GFX11-NEXT:    s_mul_i32 s20, s9, s4
; GFX11-NEXT:    s_xor_b32 s10, s19, s18
; GFX11-NEXT:    s_xor_b32 s5, s7, s5
; GFX11-NEXT:    s_xor_b32 s3, s3, s12
; GFX11-NEXT:    s_xor_b32 s7, s8, s16
; GFX11-NEXT:    s_xor_b32 s3, s3, s13
; GFX11-NEXT:    s_xor_b32 s7, s7, s17
; GFX11-NEXT:    s_xor_b32 s8, s10, s20
; GFX11-NEXT:    s_mul_i32 s9, s9, s6
; GFX11-NEXT:    s_and_b32 s3, s3, 0x22222222
; GFX11-NEXT:    s_and_b32 s7, s7, 0x11111111
; GFX11-NEXT:    s_xor_b32 s6, s8, s21
; GFX11-NEXT:    s_xor_b32 s5, s5, s9
; GFX11-NEXT:    s_mul_i32 s2, s2, s4
; GFX11-NEXT:    s_or_b32 s3, s7, s3
; GFX11-NEXT:    s_and_b32 s4, s6, 0x44444444
; GFX11-NEXT:    s_xor_b32 s2, s5, s2
; GFX11-NEXT:    s_or_b32 s3, s3, s4
; GFX11-NEXT:    s_and_b32 s2, s2, 0x88888888
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_or_b32 s2, s3, s2
; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
; GFX11-NEXT:    v_mov_b32_e32 v0, s2
; GFX11-NEXT:    s_mov_b32 s2, -1
; GFX11-NEXT:    buffer_store_b32 v0, off, s[0:3], 0
; GFX11-NEXT:    s_endpgm
;
; GFX12-LABEL: test_clmul_i32_uniform:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    s_and_b32 s4, s3, 0x11111111
; GFX12-NEXT:    s_and_b32 s5, s2, 0x22222222
; GFX12-NEXT:    s_and_b32 s6, s3, 0x22222222
; GFX12-NEXT:    s_and_b32 s7, s2, 0x11111111
; GFX12-NEXT:    s_and_b32 s8, s3, 0x88888888
; GFX12-NEXT:    s_and_b32 s9, s2, 0x44444444
; GFX12-NEXT:    s_and_b32 s3, s3, 0x44444444
; GFX12-NEXT:    s_and_b32 s2, s2, 0x88888888
; GFX12-NEXT:    s_mul_i32 s10, s5, s4
; GFX12-NEXT:    s_mul_i32 s11, s7, s6
; GFX12-NEXT:    s_mul_i32 s14, s5, s8
; GFX12-NEXT:    s_mul_i32 s15, s7, s4
; GFX12-NEXT:    s_mul_i32 s12, s9, s8
; GFX12-NEXT:    s_mul_i32 s13, s2, s3
; GFX12-NEXT:    s_mul_i32 s16, s9, s3
; GFX12-NEXT:    s_mul_i32 s18, s5, s6
; GFX12-NEXT:    s_mul_i32 s19, s7, s3
; GFX12-NEXT:    s_mul_i32 s21, s2, s8
; GFX12-NEXT:    s_mul_i32 s5, s5, s3
; GFX12-NEXT:    s_mul_i32 s7, s7, s8
; GFX12-NEXT:    s_xor_b32 s3, s11, s10
; GFX12-NEXT:    s_xor_b32 s8, s15, s14
; GFX12-NEXT:    s_mul_i32 s17, s2, s6
; GFX12-NEXT:    s_mul_i32 s20, s9, s4
; GFX12-NEXT:    s_xor_b32 s10, s19, s18
; GFX12-NEXT:    s_xor_b32 s5, s7, s5
; GFX12-NEXT:    s_xor_b32 s3, s3, s12
; GFX12-NEXT:    s_xor_b32 s7, s8, s16
; GFX12-NEXT:    s_xor_b32 s3, s3, s13
; GFX12-NEXT:    s_xor_b32 s7, s7, s17
; GFX12-NEXT:    s_xor_b32 s8, s10, s20
; GFX12-NEXT:    s_mul_i32 s9, s9, s6
; GFX12-NEXT:    s_and_b32 s3, s3, 0x22222222
; GFX12-NEXT:    s_and_b32 s7, s7, 0x11111111
; GFX12-NEXT:    s_xor_b32 s6, s8, s21
; GFX12-NEXT:    s_xor_b32 s5, s5, s9
; GFX12-NEXT:    s_mul_i32 s2, s2, s4
; GFX12-NEXT:    s_or_b32 s3, s7, s3
; GFX12-NEXT:    s_and_b32 s4, s6, 0x44444444
; GFX12-NEXT:    s_xor_b32 s2, s5, s2
; GFX12-NEXT:    s_or_b32 s3, s3, s4
; GFX12-NEXT:    s_and_b32 s2, s2, 0x88888888
; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-NEXT:    s_or_b32 s2, s3, s2
; GFX12-NEXT:    s_mov_b32 s3, 0x31016000
; GFX12-NEXT:    v_mov_b32_e32 v0, s2
; GFX12-NEXT:    s_mov_b32 s2, -1
; GFX12-NEXT:    buffer_store_b32 v0, off, s[0:3], null
; GFX12-NEXT:    s_endpgm
;
; GFX1250-LABEL: test_clmul_i32_uniform:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-NEXT:    v_nop
; GFX1250-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    s_and_b32 s4, s3, 0x11111111
; GFX1250-NEXT:    s_and_b32 s5, s2, 0x22222222
; GFX1250-NEXT:    s_and_b32 s6, s3, 0x22222222
; GFX1250-NEXT:    s_and_b32 s7, s2, 0x11111111
; GFX1250-NEXT:    s_and_b32 s8, s3, 0x88888888
; GFX1250-NEXT:    s_and_b32 s9, s2, 0x44444444
; GFX1250-NEXT:    s_and_b32 s3, s3, 0x44444444
; GFX1250-NEXT:    s_and_b32 s2, s2, 0x88888888
; GFX1250-NEXT:    s_mul_i32 s10, s5, s4
; GFX1250-NEXT:    s_mul_i32 s11, s7, s6
; GFX1250-NEXT:    s_mul_i32 s14, s5, s8
; GFX1250-NEXT:    s_mul_i32 s15, s7, s4
; GFX1250-NEXT:    s_mul_i32 s12, s9, s8
; GFX1250-NEXT:    s_mul_i32 s13, s2, s3
; GFX1250-NEXT:    s_mul_i32 s16, s9, s3
; GFX1250-NEXT:    s_mul_i32 s18, s5, s6
; GFX1250-NEXT:    s_mul_i32 s19, s7, s3
; GFX1250-NEXT:    s_mul_i32 s21, s2, s8
; GFX1250-NEXT:    s_mul_i32 s5, s5, s3
; GFX1250-NEXT:    s_mul_i32 s7, s7, s8
; GFX1250-NEXT:    s_xor_b32 s3, s11, s10
; GFX1250-NEXT:    s_xor_b32 s8, s15, s14
; GFX1250-NEXT:    s_mul_i32 s17, s2, s6
; GFX1250-NEXT:    s_mul_i32 s20, s9, s4
; GFX1250-NEXT:    s_xor_b32 s10, s19, s18
; GFX1250-NEXT:    s_xor_b32 s5, s7, s5
; GFX1250-NEXT:    s_xor_b32 s3, s3, s12
; GFX1250-NEXT:    s_xor_b32 s7, s8, s16
; GFX1250-NEXT:    s_xor_b32 s3, s3, s13
; GFX1250-NEXT:    s_xor_b32 s7, s7, s17
; GFX1250-NEXT:    s_xor_b32 s8, s10, s20
; GFX1250-NEXT:    s_mul_i32 s9, s9, s6
; GFX1250-NEXT:    s_and_b32 s3, s3, 0x22222222
; GFX1250-NEXT:    s_and_b32 s7, s7, 0x11111111
; GFX1250-NEXT:    s_xor_b32 s6, s8, s21
; GFX1250-NEXT:    s_xor_b32 s5, s5, s9
; GFX1250-NEXT:    s_mul_i32 s2, s2, s4
; GFX1250-NEXT:    s_or_b32 s3, s7, s3
; GFX1250-NEXT:    s_and_b32 s4, s6, 0x44444444
; GFX1250-NEXT:    s_xor_b32 s2, s5, s2
; GFX1250-NEXT:    s_or_b32 s3, s3, s4
; GFX1250-NEXT:    s_and_b32 s2, s2, 0x88888888
; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT:    s_or_b32 s2, s3, s2
; GFX1250-NEXT:    s_mov_b32 s3, 0x31016000
; GFX1250-NEXT:    v_mov_b32_e32 v0, s2
; GFX1250-NEXT:    s_mov_b32 s2, -1
; GFX1250-NEXT:    buffer_store_b32 v0, off, s[0:3], null
; GFX1250-NEXT:    s_endpgm
;
; EG-LABEL: test_clmul_i32_uniform:
; EG:       ; %bb.0:
; EG-NEXT:    ALU 53, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
; EG-NEXT:    CF_END
; EG-NEXT:    PAD
; EG-NEXT:    ALU clause starting at 4:
; EG-NEXT:     AND_INT T0.W, KC0[2].Z, literal.x,
; EG-NEXT:     AND_INT * T1.W, KC0[2].W, literal.y,
; EG-NEXT:    1145324612(7.850667e+02), 572662306(2.197316e-18)
; EG-NEXT:     AND_INT T2.W, KC0[2].W, literal.x,
; EG-NEXT:     MULLO_INT * T0.X, PV.W, PS,
; EG-NEXT:    286331153(1.144374e-28), 0(0.000000e+00)
; EG-NEXT:     AND_INT T3.W, KC0[2].Z, literal.x,
; EG-NEXT:     MULLO_INT * T0.Y, T0.W, PV.W,
; EG-NEXT:    -2004318072(-8.217301e-34), 0(0.000000e+00)
; EG-NEXT:     AND_INT T4.W, KC0[2].W, literal.x,
; EG-NEXT:     MULLO_INT * T0.Z, PV.W, T1.W,
; EG-NEXT:    1145324612(7.850667e+02), 0(0.000000e+00)
; EG-NEXT:     AND_INT T1.Z, KC0[2].W, literal.x,
; EG-NEXT:     AND_INT T5.W, KC0[2].Z, literal.y,
; EG-NEXT:     MULLO_INT * T1.X, T3.W, PV.W,
; EG-NEXT:    -2004318072(-8.217301e-34), 286331153(1.144374e-28)
; EG-NEXT:     MULLO_INT * T1.Y, PV.W, PV.Z,
; EG-NEXT:     MULLO_INT * T2.X, T0.W, T1.Z,
; EG-NEXT:     MULLO_INT * T0.W, T0.W, T4.W,
; EG-NEXT:     MULLO_INT * T2.Y, T5.W, T4.W,
; EG-NEXT:     AND_INT T6.W, KC0[2].Z, literal.x,
; EG-NEXT:     MULLO_INT * T2.Z, T5.W, T2.W,
; EG-NEXT:    572662306(2.197316e-18), 0(0.000000e+00)
; EG-NEXT:     MULLO_INT * T3.X, PV.W, T1.Z,
; EG-NEXT:     MULLO_INT * T3.Y, T5.W, T1.W,
; EG-NEXT:     MULLO_INT * T3.Z, T6.W, T2.W,
; EG-NEXT:     XOR_INT T3.Z, T3.Y, PS,
; EG-NEXT:     XOR_INT T5.W, T2.Z, T3.X,
; EG-NEXT:     MULLO_INT * T1.W, T6.W, T1.W,
; EG-NEXT:     XOR_INT T2.Y, T2.Y, PS,
; EG-NEXT:     XOR_INT T2.Z, PV.W, T0.W, BS:VEC_102/SCL_221
; EG-NEXT:     XOR_INT T0.W, PV.Z, T2.X,
; EG-NEXT:     MULLO_INT * T1.W, T6.W, T4.W,
; EG-NEXT:     XOR_INT T2.X, T1.Y, PS,
; EG-NEXT:     XOR_INT T1.Y, PV.W, T1.X,
; EG-NEXT:     XOR_INT T0.Z, PV.Z, T0.Z, BS:VEC_021/SCL_122
; EG-NEXT:     XOR_INT T0.W, PV.Y, T0.Y,
; EG-NEXT:     MULLO_INT * T0.Y, T3.W, T1.Z,
; EG-NEXT:     XOR_INT T1.X, PV.W, PS,
; EG-NEXT:     AND_INT T0.Y, PV.Z, literal.x,
; EG-NEXT:     AND_INT T0.Z, PV.Y, literal.y,
; EG-NEXT:     XOR_INT T0.W, PV.X, T0.X,
; EG-NEXT:     MULLO_INT * T0.X, T3.W, T2.W,
; EG-NEXT:    286331153(1.144374e-28), 572662306(2.197316e-18)
; EG-NEXT:     XOR_INT T1.Z, PV.W, PS,
; EG-NEXT:     OR_INT T0.W, PV.Y, PV.Z,
; EG-NEXT:     AND_INT * T1.W, PV.X, literal.x,
; EG-NEXT:    1145324612(7.850667e+02), 0(0.000000e+00)
; EG-NEXT:     OR_INT T0.W, PV.W, PS,
; EG-NEXT:     AND_INT * T1.W, PV.Z, literal.x,
; EG-NEXT:    -2004318072(-8.217301e-34), 0(0.000000e+00)
; EG-NEXT:     OR_INT T0.X, PV.W, PS,
; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
  %res = call i32 @llvm.clmul.i32(i32 %a, i32 %b)
  store i32 %res, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @test_clmulr_i32_uniform(ptr addrspace(1) %out, i32 %a, i32 %b) {
; SI-LABEL: test_clmulr_i32_uniform:
; SI:       ; %bb.0:
; SI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x9
; SI-NEXT:    s_mov_b32 s9, 0
; SI-NEXT:    s_mov_b32 s11, s9
; SI-NEXT:    s_mov_b32 s3, 0xf000
; SI-NEXT:    s_mov_b32 s2, -1
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    s_mov_b32 s8, s6
; SI-NEXT:    s_mov_b32 s0, s4
; SI-NEXT:    s_mov_b32 s1, s5
; SI-NEXT:    s_ashr_i32 s10, s7, 31
; SI-NEXT:    s_lshl_b64 s[4:5], s[8:9], 31
; SI-NEXT:    s_and_b32 s5, s10, s5
; SI-NEXT:    s_and_b32 s4, s10, s4
; SI-NEXT:    s_bfe_i32 s10, s7, 0x10000
; SI-NEXT:    s_and_b32 s10, s10, s6
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 1
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10001
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 2
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10002
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 3
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10003
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 4
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10004
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 5
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10005
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 6
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10006
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 7
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10007
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 8
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10008
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 9
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10009
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 10
; SI-NEXT:    s_bfe_i32 s6, s7, 0x1000a
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 11
; SI-NEXT:    s_bfe_i32 s6, s7, 0x1000b
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 12
; SI-NEXT:    s_bfe_i32 s6, s7, 0x1000c
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 13
; SI-NEXT:    s_bfe_i32 s6, s7, 0x1000d
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 14
; SI-NEXT:    s_bfe_i32 s6, s7, 0x1000e
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 15
; SI-NEXT:    s_bfe_i32 s6, s7, 0x1000f
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 16
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10010
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 17
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10011
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 18
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10012
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 19
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10013
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 20
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10014
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 21
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10015
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 22
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10016
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 23
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10017
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 24
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10018
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 25
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10019
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 26
; SI-NEXT:    s_bfe_i32 s6, s7, 0x1001a
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 27
; SI-NEXT:    s_bfe_i32 s6, s7, 0x1001b
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 28
; SI-NEXT:    s_bfe_i32 s6, s7, 0x1001c
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 29
; SI-NEXT:    s_bfe_i32 s6, s7, 0x1001d
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_lshl_b64 s[8:9], s[8:9], 30
; SI-NEXT:    s_bfe_i32 s6, s7, 0x1001e
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_and_b32 s7, s6, s9
; SI-NEXT:    s_and_b32 s6, s6, s8
; SI-NEXT:    s_xor_b64 s[6:7], s[10:11], s[6:7]
; SI-NEXT:    s_xor_b64 s[4:5], s[6:7], s[4:5]
; SI-NEXT:    s_lshr_b64 s[4:5], s[4:5], 31
; SI-NEXT:    v_mov_b32_e32 v0, s4
; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT:    s_endpgm
;
; VI-LABEL: test_clmulr_i32_uniform:
; VI:       ; %bb.0:
; VI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x24
; VI-NEXT:    s_mov_b32 s9, 0
; VI-NEXT:    s_mov_b32 s11, s9
; VI-NEXT:    s_mov_b32 s3, 0xf000
; VI-NEXT:    s_mov_b32 s2, -1
; VI-NEXT:    s_waitcnt lgkmcnt(0)
; VI-NEXT:    s_mov_b32 s8, s6
; VI-NEXT:    s_mov_b32 s0, s4
; VI-NEXT:    s_mov_b32 s1, s5
; VI-NEXT:    s_ashr_i32 s10, s7, 31
; VI-NEXT:    s_lshl_b64 s[4:5], s[8:9], 31
; VI-NEXT:    s_and_b32 s5, s10, s5
; VI-NEXT:    s_and_b32 s4, s10, s4
; VI-NEXT:    s_bfe_i32 s10, s7, 0x10000
; VI-NEXT:    s_and_b32 s10, s10, s6
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 1
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10001
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 2
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10002
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 3
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10003
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 4
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10004
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 5
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10005
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 6
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10006
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 7
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10007
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 8
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10008
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 9
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10009
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 10
; VI-NEXT:    s_bfe_i32 s6, s7, 0x1000a
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 11
; VI-NEXT:    s_bfe_i32 s6, s7, 0x1000b
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 12
; VI-NEXT:    s_bfe_i32 s6, s7, 0x1000c
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 13
; VI-NEXT:    s_bfe_i32 s6, s7, 0x1000d
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 14
; VI-NEXT:    s_bfe_i32 s6, s7, 0x1000e
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 15
; VI-NEXT:    s_bfe_i32 s6, s7, 0x1000f
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 16
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10010
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 17
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10011
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 18
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10012
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 19
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10013
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 20
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10014
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 21
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10015
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 22
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10016
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 23
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10017
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 24
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10018
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 25
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10019
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 26
; VI-NEXT:    s_bfe_i32 s6, s7, 0x1001a
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 27
; VI-NEXT:    s_bfe_i32 s6, s7, 0x1001b
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 28
; VI-NEXT:    s_bfe_i32 s6, s7, 0x1001c
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 29
; VI-NEXT:    s_bfe_i32 s6, s7, 0x1001d
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_lshl_b64 s[8:9], s[8:9], 30
; VI-NEXT:    s_bfe_i32 s6, s7, 0x1001e
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_and_b32 s7, s6, s9
; VI-NEXT:    s_and_b32 s6, s6, s8
; VI-NEXT:    s_xor_b64 s[6:7], s[10:11], s[6:7]
; VI-NEXT:    s_xor_b64 s[4:5], s[6:7], s[4:5]
; VI-NEXT:    s_lshr_b64 s[4:5], s[4:5], 31
; VI-NEXT:    v_mov_b32_e32 v0, s4
; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT:    s_endpgm
;
; GFX9-LABEL: test_clmulr_i32_uniform:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x24
; GFX9-NEXT:    s_mov_b32 s7, 0
; GFX9-NEXT:    s_mov_b32 s3, 0xf000
; GFX9-NEXT:    s_mov_b32 s2, -1
; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-NEXT:    s_mov_b32 s6, s10
; GFX9-NEXT:    s_mov_b32 s0, s8
; GFX9-NEXT:    s_ashr_i32 s8, s11, 31
; GFX9-NEXT:    s_lshl_b64 s[4:5], s[6:7], 31
; GFX9-NEXT:    s_and_b32 s5, s8, s5
; GFX9-NEXT:    s_and_b32 s4, s8, s4
; GFX9-NEXT:    s_bfe_i32 s8, s11, 0x10000
; GFX9-NEXT:    s_and_b32 s8, s8, s10
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 1
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10001
; GFX9-NEXT:    s_mov_b32 s1, s9
; GFX9-NEXT:    s_mov_b32 s9, s7
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 2
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10002
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 3
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10003
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 4
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10004
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 5
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10005
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 6
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10006
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 7
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10007
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 8
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10008
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 9
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10009
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 10
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x1000a
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 11
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x1000b
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 12
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x1000c
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 13
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x1000d
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 14
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x1000e
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 15
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x1000f
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 16
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10010
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 17
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10011
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 18
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10012
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 19
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10013
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 20
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10014
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 21
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10015
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 22
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10016
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 23
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10017
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 24
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10018
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 25
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10019
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 26
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x1001a
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 27
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x1001b
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 28
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x1001c
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 29
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x1001d
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_lshl_b64 s[6:7], s[6:7], 30
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x1001e
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_and_b32 s7, s10, s7
; GFX9-NEXT:    s_and_b32 s6, s10, s6
; GFX9-NEXT:    s_xor_b64 s[6:7], s[8:9], s[6:7]
; GFX9-NEXT:    s_xor_b64 s[4:5], s[6:7], s[4:5]
; GFX9-NEXT:    s_lshr_b64 s[4:5], s[4:5], 31
; GFX9-NEXT:    v_mov_b32_e32 v0, s4
; GFX9-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; GFX9-NEXT:    s_endpgm
;
; GFX10-LABEL: test_clmulr_i32_uniform:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX10-NEXT:    s_mov_b32 s5, 0
; GFX10-NEXT:    s_mov_b32 s11, s5
; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
; GFX10-NEXT:    s_mov_b32 s4, s2
; GFX10-NEXT:    s_bfe_i32 s9, s3, 0x10000
; GFX10-NEXT:    s_bfe_i32 s24, s3, 0x10001
; GFX10-NEXT:    s_lshl_b64 s[12:13], s[4:5], 1
; GFX10-NEXT:    s_bfe_i32 s25, s3, 0x10002
; GFX10-NEXT:    s_and_b32 s10, s9, s2
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 2
; GFX10-NEXT:    s_and_b32 s13, s24, s13
; GFX10-NEXT:    s_and_b32 s12, s24, s12
; GFX10-NEXT:    s_bfe_i32 s26, s3, 0x10003
; GFX10-NEXT:    s_lshl_b64 s[16:17], s[4:5], 3
; GFX10-NEXT:    s_and_b32 s15, s25, s15
; GFX10-NEXT:    s_and_b32 s14, s25, s14
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_bfe_i32 s27, s3, 0x10004
; GFX10-NEXT:    s_lshl_b64 s[18:19], s[4:5], 4
; GFX10-NEXT:    s_and_b32 s17, s26, s17
; GFX10-NEXT:    s_and_b32 s16, s26, s16
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[14:15]
; GFX10-NEXT:    s_bfe_i32 s28, s3, 0x10005
; GFX10-NEXT:    s_lshl_b64 s[20:21], s[4:5], 5
; GFX10-NEXT:    s_and_b32 s19, s27, s19
; GFX10-NEXT:    s_and_b32 s18, s27, s18
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[16:17]
; GFX10-NEXT:    s_bfe_i32 s29, s3, 0x10006
; GFX10-NEXT:    s_lshl_b64 s[22:23], s[4:5], 6
; GFX10-NEXT:    s_and_b32 s13, s28, s21
; GFX10-NEXT:    s_and_b32 s12, s28, s20
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[18:19]
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 7
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s29, s23
; GFX10-NEXT:    s_and_b32 s12, s29, s22
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x10007
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 8
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x10008
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 9
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x10009
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 10
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x1000a
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 11
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x1000b
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 12
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x1000c
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 13
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x1000d
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 14
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x1000e
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 15
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x1000f
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 16
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x10010
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 17
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x10011
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 18
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x10012
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 19
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x10013
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 20
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x10014
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 21
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x10015
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 22
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x10016
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 23
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x10017
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 24
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x10018
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 25
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x10019
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 26
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x1001a
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 27
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x1001b
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 28
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x1001c
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 29
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x1001d
; GFX10-NEXT:    s_lshl_b64 s[6:7], s[4:5], 31
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[4:5], s[4:5], 30
; GFX10-NEXT:    s_bfe_i32 s9, s3, 0x1001e
; GFX10-NEXT:    s_ashr_i32 s8, s3, 31
; GFX10-NEXT:    s_xor_b64 s[2:3], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s5, s9, s5
; GFX10-NEXT:    s_and_b32 s4, s9, s4
; GFX10-NEXT:    s_and_b32 s7, s8, s7
; GFX10-NEXT:    s_and_b32 s6, s8, s6
; GFX10-NEXT:    s_xor_b64 s[2:3], s[2:3], s[4:5]
; GFX10-NEXT:    s_xor_b64 s[2:3], s[2:3], s[6:7]
; GFX10-NEXT:    s_lshr_b64 s[2:3], s[2:3], 31
; GFX10-NEXT:    s_mov_b32 s3, 0x31016000
; GFX10-NEXT:    v_mov_b32_e32 v0, s2
; GFX10-NEXT:    s_mov_b32 s2, -1
; GFX10-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; GFX10-NEXT:    s_endpgm
;
; GFX11-LABEL: test_clmulr_i32_uniform:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-NEXT:    s_mov_b32 s5, 0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_mov_b32 s11, s5
; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s4, s2
; GFX11-NEXT:    s_bfe_i32 s9, s3, 0x10000
; GFX11-NEXT:    s_bfe_i32 s24, s3, 0x10001
; GFX11-NEXT:    s_lshl_b64 s[12:13], s[4:5], 1
; GFX11-NEXT:    s_bfe_i32 s25, s3, 0x10002
; GFX11-NEXT:    s_and_b32 s10, s9, s2
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 2
; GFX11-NEXT:    s_and_b32 s13, s24, s13
; GFX11-NEXT:    s_and_b32 s12, s24, s12
; GFX11-NEXT:    s_bfe_i32 s26, s3, 0x10003
; GFX11-NEXT:    s_lshl_b64 s[16:17], s[4:5], 3
; GFX11-NEXT:    s_and_b32 s15, s25, s15
; GFX11-NEXT:    s_and_b32 s14, s25, s14
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_bfe_i32 s27, s3, 0x10004
; GFX11-NEXT:    s_lshl_b64 s[18:19], s[4:5], 4
; GFX11-NEXT:    s_and_b32 s17, s26, s17
; GFX11-NEXT:    s_and_b32 s16, s26, s16
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[14:15]
; GFX11-NEXT:    s_bfe_i32 s28, s3, 0x10005
; GFX11-NEXT:    s_lshl_b64 s[20:21], s[4:5], 5
; GFX11-NEXT:    s_and_b32 s19, s27, s19
; GFX11-NEXT:    s_and_b32 s18, s27, s18
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[16:17]
; GFX11-NEXT:    s_bfe_i32 s29, s3, 0x10006
; GFX11-NEXT:    s_lshl_b64 s[22:23], s[4:5], 6
; GFX11-NEXT:    s_and_b32 s13, s28, s21
; GFX11-NEXT:    s_and_b32 s12, s28, s20
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[18:19]
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 7
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s29, s23
; GFX11-NEXT:    s_and_b32 s12, s29, s22
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x10007
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 8
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x10008
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 9
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x10009
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 10
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x1000a
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 11
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x1000b
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 12
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x1000c
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 13
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x1000d
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 14
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x1000e
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 15
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x1000f
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 16
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x10010
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 17
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x10011
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 18
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x10012
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 19
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x10013
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 20
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x10014
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 21
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x10015
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 22
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x10016
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 23
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x10017
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 24
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x10018
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 25
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x10019
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 26
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x1001a
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 27
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x1001b
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 28
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x1001c
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 29
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x1001d
; GFX11-NEXT:    s_lshl_b64 s[6:7], s[4:5], 31
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[4:5], s[4:5], 30
; GFX11-NEXT:    s_bfe_i32 s9, s3, 0x1001e
; GFX11-NEXT:    s_ashr_i32 s8, s3, 31
; GFX11-NEXT:    s_xor_b64 s[2:3], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s5, s9, s5
; GFX11-NEXT:    s_and_b32 s4, s9, s4
; GFX11-NEXT:    s_and_b32 s7, s8, s7
; GFX11-NEXT:    s_and_b32 s6, s8, s6
; GFX11-NEXT:    s_xor_b64 s[2:3], s[2:3], s[4:5]
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT:    s_xor_b64 s[2:3], s[2:3], s[6:7]
; GFX11-NEXT:    s_lshr_b64 s[2:3], s[2:3], 31
; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
; GFX11-NEXT:    v_mov_b32_e32 v0, s2
; GFX11-NEXT:    s_mov_b32 s2, -1
; GFX11-NEXT:    buffer_store_b32 v0, off, s[0:3], 0
; GFX11-NEXT:    s_endpgm
;
; GFX12-LABEL: test_clmulr_i32_uniform:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT:    s_mov_b32 s5, 0
; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-NEXT:    s_mov_b32 s7, s5
; GFX12-NEXT:    s_mov_b32 s9, s5
; GFX12-NEXT:    s_mov_b32 s11, s5
; GFX12-NEXT:    s_mov_b32 s13, s5
; GFX12-NEXT:    s_mov_b32 s17, s5
; GFX12-NEXT:    s_mov_b32 s15, s5
; GFX12-NEXT:    s_mov_b32 s19, s5
; GFX12-NEXT:    s_mov_b32 s20, s5
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    s_and_b32 s4, s3, 0x44444444
; GFX12-NEXT:    s_and_b32 s6, s2, 0x22222222
; GFX12-NEXT:    s_and_b32 s8, s3, 0x88888888
; GFX12-NEXT:    s_and_b32 s10, s2, 0x11111111
; GFX12-NEXT:    s_and_b32 s12, s3, 0x22222222
; GFX12-NEXT:    s_and_b32 s16, s3, 0x11111111
; GFX12-NEXT:    s_and_b32 s14, s2, 0x44444444
; GFX12-NEXT:    s_and_b32 s18, s2, 0x88888888
; GFX12-NEXT:    s_mul_u64 s[2:3], s[6:7], s[4:5]
; GFX12-NEXT:    s_mul_u64 s[22:23], s[10:11], s[8:9]
; GFX12-NEXT:    s_mul_u64 s[28:29], s[6:7], s[16:17]
; GFX12-NEXT:    s_mul_u64 s[30:31], s[10:11], s[12:13]
; GFX12-NEXT:    s_mul_u64 s[34:35], s[14:15], s[8:9]
; GFX12-NEXT:    s_xor_b64 s[2:3], s[22:23], s[2:3]
; GFX12-NEXT:    s_xor_b64 s[22:23], s[30:31], s[28:29]
; GFX12-NEXT:    s_mul_u64 s[36:37], s[18:19], s[4:5]
; GFX12-NEXT:    s_xor_b64 s[22:23], s[22:23], s[34:35]
; GFX12-NEXT:    s_mul_u64 s[24:25], s[14:15], s[12:13]
; GFX12-NEXT:    s_mul_u64 s[38:39], s[6:7], s[8:9]
; GFX12-NEXT:    s_mul_u64 s[40:41], s[10:11], s[16:17]
; GFX12-NEXT:    s_xor_b64 s[22:23], s[22:23], s[36:37]
; GFX12-NEXT:    s_mul_u64 s[26:27], s[18:19], s[16:17]
; GFX12-NEXT:    s_xor_b64 s[2:3], s[2:3], s[24:25]
; GFX12-NEXT:    s_and_b32 s21, s23, 0x22222222
; GFX12-NEXT:    s_mul_u64 s[22:23], s[14:15], s[4:5]
; GFX12-NEXT:    s_xor_b64 s[24:25], s[40:41], s[38:39]
; GFX12-NEXT:    s_mul_u64 s[6:7], s[6:7], s[12:13]
; GFX12-NEXT:    s_mul_u64 s[10:11], s[10:11], s[4:5]
; GFX12-NEXT:    s_xor_b64 s[2:3], s[2:3], s[26:27]
; GFX12-NEXT:    s_mul_u64 s[26:27], s[18:19], s[12:13]
; GFX12-NEXT:    s_xor_b64 s[12:13], s[24:25], s[22:23]
; GFX12-NEXT:    s_mul_u64 s[14:15], s[14:15], s[16:17]
; GFX12-NEXT:    s_xor_b64 s[6:7], s[10:11], s[6:7]
; GFX12-NEXT:    s_xor_b64 s[12:13], s[12:13], s[26:27]
; GFX12-NEXT:    s_mul_u64 s[8:9], s[18:19], s[8:9]
; GFX12-NEXT:    s_xor_b64 s[6:7], s[6:7], s[14:15]
; GFX12-NEXT:    s_and_b32 s11, s13, 0x11111111
; GFX12-NEXT:    s_mov_b32 s10, s5
; GFX12-NEXT:    s_xor_b64 s[6:7], s[6:7], s[8:9]
; GFX12-NEXT:    s_or_b64 s[8:9], s[10:11], s[20:21]
; GFX12-NEXT:    s_and_b32 s7, s7, 0x44444444
; GFX12-NEXT:    s_mov_b32 s6, s5
; GFX12-NEXT:    s_and_b32 s3, s3, 0x8888888
; GFX12-NEXT:    s_and_b32 s2, s2, 0x80000000
; GFX12-NEXT:    s_or_b64 s[4:5], s[8:9], s[6:7]
; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-NEXT:    s_or_b64 s[2:3], s[4:5], s[2:3]
; GFX12-NEXT:    s_lshr_b64 s[2:3], s[2:3], 31
; GFX12-NEXT:    s_mov_b32 s3, 0x31016000
; GFX12-NEXT:    v_mov_b32_e32 v0, s2
; GFX12-NEXT:    s_mov_b32 s2, -1
; GFX12-NEXT:    buffer_store_b32 v0, off, s[0:3], null
; GFX12-NEXT:    s_endpgm
;
; GFX1250-LABEL: test_clmulr_i32_uniform:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-NEXT:    v_nop
; GFX1250-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
; GFX1250-NEXT:    s_wait_xcnt 0x0
; GFX1250-NEXT:    s_mov_b32 s5, 0
; GFX1250-NEXT:    s_mov_b64 s[6:7], 0x88888888
; GFX1250-NEXT:    s_mov_b32 s9, s5
; GFX1250-NEXT:    s_mov_b32 s11, s5
; GFX1250-NEXT:    s_mov_b32 s13, s5
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    s_mov_b32 s4, s3
; GFX1250-NEXT:    s_and_b32 s8, s2, 0x22222222
; GFX1250-NEXT:    s_and_b32 s10, s2, 0x11111111
; GFX1250-NEXT:    s_and_b64 s[14:15], s[4:5], 0x11111111
; GFX1250-NEXT:    s_and_b64 s[16:17], s[4:5], 0x22222222
; GFX1250-NEXT:    s_and_b64 s[6:7], s[4:5], s[6:7]
; GFX1250-NEXT:    s_and_b32 s12, s2, 0x44444444
; GFX1250-NEXT:    s_and_b64 s[18:19], s[4:5], 0x44444444
; GFX1250-NEXT:    s_and_b32 s4, s2, 0x88888888
; GFX1250-NEXT:    s_mul_u64 s[2:3], s[8:9], s[14:15]
; GFX1250-NEXT:    s_mul_u64 s[20:21], s[10:11], s[16:17]
; GFX1250-NEXT:    s_mul_u64 s[26:27], s[8:9], s[6:7]
; GFX1250-NEXT:    s_mul_u64 s[28:29], s[10:11], s[14:15]
; GFX1250-NEXT:    s_mul_u64 s[22:23], s[12:13], s[6:7]
; GFX1250-NEXT:    s_mul_u64 s[24:25], s[4:5], s[18:19]
; GFX1250-NEXT:    s_mul_u64 s[30:31], s[12:13], s[18:19]
; GFX1250-NEXT:    s_mul_u64 s[36:37], s[8:9], s[16:17]
; GFX1250-NEXT:    s_mul_u64 s[38:39], s[10:11], s[18:19]
; GFX1250-NEXT:    s_mul_u64 s[8:9], s[8:9], s[18:19]
; GFX1250-NEXT:    s_xor_b64 s[2:3], s[20:21], s[2:3]
; GFX1250-NEXT:    s_xor_b64 s[18:19], s[28:29], s[26:27]
; GFX1250-NEXT:    s_mul_u64 s[34:35], s[4:5], s[16:17]
; GFX1250-NEXT:    s_mul_u64 s[40:41], s[12:13], s[14:15]
; GFX1250-NEXT:    s_mul_u64 s[10:11], s[10:11], s[6:7]
; GFX1250-NEXT:    s_xor_b64 s[2:3], s[2:3], s[22:23]
; GFX1250-NEXT:    s_xor_b64 s[18:19], s[18:19], s[30:31]
; GFX1250-NEXT:    s_xor_b64 s[20:21], s[38:39], s[36:37]
; GFX1250-NEXT:    s_xor_b64 s[2:3], s[2:3], s[24:25]
; GFX1250-NEXT:    s_xor_b64 s[18:19], s[18:19], s[34:35]
; GFX1250-NEXT:    s_mul_u64 s[6:7], s[4:5], s[6:7]
; GFX1250-NEXT:    s_mul_u64 s[12:13], s[12:13], s[16:17]
; GFX1250-NEXT:    s_xor_b64 s[16:17], s[20:21], s[40:41]
; GFX1250-NEXT:    s_xor_b64 s[8:9], s[10:11], s[8:9]
; GFX1250-NEXT:    s_and_b64 s[2:3], s[2:3], 0x2222222200000000
; GFX1250-NEXT:    s_and_b64 s[18:19], s[18:19], 0x1111111100000000
; GFX1250-NEXT:    s_mul_u64 s[4:5], s[4:5], s[14:15]
; GFX1250-NEXT:    s_xor_b64 s[6:7], s[16:17], s[6:7]
; GFX1250-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX1250-NEXT:    s_or_b64 s[2:3], s[18:19], s[2:3]
; GFX1250-NEXT:    s_and_b64 s[6:7], s[6:7], 0x4444444400000000
; GFX1250-NEXT:    s_xor_b64 s[4:5], s[8:9], s[4:5]
; GFX1250-NEXT:    s_or_b64 s[2:3], s[2:3], s[6:7]
; GFX1250-NEXT:    s_and_b64 s[4:5], s[4:5], 0x888888880000000
; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-NEXT:    s_or_b64 s[2:3], s[2:3], s[4:5]
; GFX1250-NEXT:    s_lshr_b64 s[2:3], s[2:3], 31
; GFX1250-NEXT:    s_mov_b32 s3, 0x31016000
; GFX1250-NEXT:    v_mov_b32_e32 v0, s2
; GFX1250-NEXT:    s_mov_b32 s2, -1
; GFX1250-NEXT:    buffer_store_b32 v0, off, s[0:3], null
; GFX1250-NEXT:    s_endpgm
;
; EG-LABEL: test_clmulr_i32_uniform:
; EG:       ; %bb.0:
; EG-NEXT:    ALU 92, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT:    ALU 52, @97, KC0[CB0:0-32], KC1[]
; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
; EG-NEXT:    CF_END
; EG-NEXT:    ALU clause starting at 4:
; EG-NEXT:     AND_INT T0.W, KC0[2].Z, literal.x,
; EG-NEXT:     LSHR * T1.W, KC0[2].Z, literal.y,
; EG-NEXT:    65280(9.147676e-41), 8(1.121039e-44)
; EG-NEXT:     AND_INT T0.X, PS, literal.x,
; EG-NEXT:     LSHR T0.Y, KC0[2].Z, literal.y,
; EG-NEXT:     LSHL T0.Z, PV.W, literal.z,
; EG-NEXT:     AND_INT T0.W, KC0[2].W, literal.x,
; EG-NEXT:     LSHR * T1.W, KC0[2].W, literal.z,
; EG-NEXT:    65280(9.147676e-41), 24(3.363116e-44)
; EG-NEXT:    8(1.121039e-44), 0(0.000000e+00)
; EG-NEXT:     LSHL T1.X, KC0[2].Z, literal.x,
; EG-NEXT:     AND_INT T1.Y, PS, literal.y,
; EG-NEXT:     LSHR T1.Z, KC0[2].W, literal.x,
; EG-NEXT:     LSHL T0.W, PV.W, literal.z,
; EG-NEXT:     LSHL * T1.W, KC0[2].W, literal.x,
; EG-NEXT:    24(3.363116e-44), 65280(9.147676e-41)
; EG-NEXT:    8(1.121039e-44), 0(0.000000e+00)
; EG-NEXT:     OR_INT T2.Y, PS, PV.W,
; EG-NEXT:     OR_INT T1.Z, PV.Y, PV.Z,
; EG-NEXT:     OR_INT T0.W, PV.X, T0.Z,
; EG-NEXT:     OR_INT * T1.W, T0.X, T0.Y,
; EG-NEXT:     OR_INT T0.W, PV.W, PS,
; EG-NEXT:     OR_INT * T1.W, PV.Y, PV.Z,
; EG-NEXT:     AND_INT T0.Y, PS, literal.x,
; EG-NEXT:     LSHR T0.Z, PS, literal.y,
; EG-NEXT:     AND_INT T1.W, PV.W, literal.x,
; EG-NEXT:     LSHR * T0.W, PV.W, literal.y,
; EG-NEXT:    252645135(7.053345e-30), 4(5.605194e-45)
; EG-NEXT:     AND_INT T1.Y, PS, literal.x,
; EG-NEXT:     LSHL T1.Z, PV.W, literal.y,
; EG-NEXT:     AND_INT T0.W, PV.Z, literal.x,
; EG-NEXT:     LSHL * T1.W, PV.Y, literal.y,
; EG-NEXT:    252645135(7.053345e-30), 4(5.605194e-45)
; EG-NEXT:     OR_INT T0.W, PV.W, PS,
; EG-NEXT:     OR_INT * T1.W, PV.Y, PV.Z,
; EG-NEXT:     AND_INT T0.Y, PS, literal.x,
; EG-NEXT:     LSHR T0.Z, PS, literal.y,
; EG-NEXT:     AND_INT T1.W, PV.W, literal.x,
; EG-NEXT:     LSHR * T0.W, PV.W, literal.y,
; EG-NEXT:    858993459(4.172325e-08), 2(2.802597e-45)
; EG-NEXT:     AND_INT T1.Y, PS, literal.x,
; EG-NEXT:     LSHL T1.Z, PV.W, literal.y,
; EG-NEXT:     AND_INT T0.W, PV.Z, literal.x,
; EG-NEXT:     LSHL * T1.W, PV.Y, literal.y,
; EG-NEXT:    858993459(4.172325e-08), 2(2.802597e-45)
; EG-NEXT:     OR_INT T0.W, PV.W, PS,
; EG-NEXT:     OR_INT * T1.W, PV.Y, PV.Z,
; EG-NEXT:     AND_INT T0.Y, PS, literal.x,
; EG-NEXT:     LSHR T0.Z, PS, 1,
; EG-NEXT:     AND_INT T1.W, PV.W, literal.x,
; EG-NEXT:     LSHR * T0.W, PV.W, 1,
; EG-NEXT:    1431655765(1.466015e+13), 0(0.000000e+00)
; EG-NEXT:     AND_INT T1.Y, PS, literal.x,
; EG-NEXT:     LSHL T1.Z, PV.W, 1,
; EG-NEXT:     AND_INT T0.W, PV.Z, literal.x,
; EG-NEXT:     LSHL * T1.W, PV.Y, 1,
; EG-NEXT:    1431655765(1.466015e+13), 0(0.000000e+00)
; EG-NEXT:     OR_INT T0.W, PV.W, PS,
; EG-NEXT:     OR_INT * T1.W, PV.Y, PV.Z,
; EG-NEXT:     AND_INT T2.W, PS, literal.x,
; EG-NEXT:     AND_INT * T3.W, PV.W, literal.y,
; EG-NEXT:    1145324612(7.850667e+02), 572662306(2.197316e-18)
; EG-NEXT:     AND_INT T4.W, T0.W, literal.x,
; EG-NEXT:     MULLO_INT * T0.X, PV.W, PS,
; EG-NEXT:    286331153(1.144374e-28), 0(0.000000e+00)
; EG-NEXT:     AND_INT T5.W, T1.W, literal.x,
; EG-NEXT:     MULLO_INT * T0.Y, T2.W, PV.W,
; EG-NEXT:    -2004318072(-8.217301e-34), 0(0.000000e+00)
; EG-NEXT:     AND_INT T6.W, T0.W, literal.x,
; EG-NEXT:     MULLO_INT * T0.Z, PV.W, T3.W,
; EG-NEXT:    1145324612(7.850667e+02), 0(0.000000e+00)
; EG-NEXT:     AND_INT T1.Z, T0.W, literal.x,
; EG-NEXT:     AND_INT T0.W, T1.W, literal.y, BS:VEC_120/SCL_212
; EG-NEXT:     MULLO_INT * T1.X, T5.W, PV.W,
; EG-NEXT:    -2004318072(-8.217301e-34), 286331153(1.144374e-28)
; EG-NEXT:     MULLO_INT * T1.Y, PV.W, PV.Z,
; EG-NEXT:     MULLO_INT * T2.X, T2.W, T1.Z,
; EG-NEXT:     MULLO_INT * T2.Y, T2.W, T6.W,
; EG-NEXT:     MULLO_INT * T2.Z, T0.W, T6.W,
; EG-NEXT:     AND_INT T1.W, T1.W, literal.x,
; EG-NEXT:     MULLO_INT * T2.W, T0.W, T4.W,
; EG-NEXT:    572662306(2.197316e-18), 0(0.000000e+00)
; EG-NEXT:     MULLO_INT * T3.X, PV.W, T1.Z,
; EG-NEXT:     MULLO_INT * T0.W, T0.W, T3.W,
; EG-NEXT:     MULLO_INT * T3.Y, T1.W, T4.W,
; EG-NEXT:     XOR_INT T3.Z, T0.W, PS,
; EG-NEXT:     XOR_INT * T0.W, T2.W, T3.X, BS:VEC_120/SCL_212
; EG-NEXT:     MULLO_INT * T2.W, T1.W, T3.W,
; EG-NEXT:     XOR_INT T3.Y, T2.Z, PS,
; EG-NEXT:     XOR_INT T2.Z, T0.W, T2.Y,
; EG-NEXT:     XOR_INT T0.W, T3.Z, T2.X, BS:VEC_120/SCL_212
; EG-NEXT:     MULLO_INT * T1.W, T1.W, T6.W,
; EG-NEXT:     XOR_INT * T2.X, T1.Y, PS,
; EG-NEXT:    ALU clause starting at 97:
; EG-NEXT:     XOR_INT T1.Y, T0.W, T1.X,
; EG-NEXT:     XOR_INT T0.Z, T2.Z, T0.Z, BS:VEC_021/SCL_122
; EG-NEXT:     XOR_INT T0.W, T3.Y, T0.Y,
; EG-NEXT:     MULLO_INT * T0.Y, T5.W, T1.Z,
; EG-NEXT:     XOR_INT T1.X, PV.W, PS,
; EG-NEXT:     AND_INT T0.Y, PV.Z, literal.x,
; EG-NEXT:     AND_INT T0.Z, PV.Y, literal.y,
; EG-NEXT:     XOR_INT T0.W, T2.X, T0.X,
; EG-NEXT:     MULLO_INT * T0.X, T5.W, T4.W,
; EG-NEXT:    286331153(1.144374e-28), 572662306(2.197316e-18)
; EG-NEXT:     XOR_INT T1.Z, PV.W, PS,
; EG-NEXT:     OR_INT T0.W, PV.Y, PV.Z,
; EG-NEXT:     AND_INT * T1.W, PV.X, literal.x,
; EG-NEXT:    1145324612(7.850667e+02), 0(0.000000e+00)
; EG-NEXT:     OR_INT T0.W, PV.W, PS,
; EG-NEXT:     AND_INT * T1.W, PV.Z, literal.x,
; EG-NEXT:    -2004318072(-8.217301e-34), 0(0.000000e+00)
; EG-NEXT:     OR_INT * T0.W, PV.W, PS,
; EG-NEXT:     AND_INT T1.W, PV.W, literal.x,
; EG-NEXT:     LSHR * T2.W, PV.W, literal.y,
; EG-NEXT:    65280(9.147676e-41), 8(1.121039e-44)
; EG-NEXT:     AND_INT T0.Y, PS, literal.x,
; EG-NEXT:     LSHR T0.Z, T0.W, literal.y,
; EG-NEXT:     LSHL T1.W, PV.W, literal.z,
; EG-NEXT:     LSHL * T0.W, T0.W, literal.y,
; EG-NEXT:    65280(9.147676e-41), 24(3.363116e-44)
; EG-NEXT:    8(1.121039e-44), 0(0.000000e+00)
; EG-NEXT:     OR_INT T0.W, PS, PV.W,
; EG-NEXT:     OR_INT * T1.W, PV.Y, PV.Z,
; EG-NEXT:     OR_INT * T0.W, PV.W, PS,
; EG-NEXT:     AND_INT T1.W, PV.W, literal.x,
; EG-NEXT:     LSHR * T0.W, PV.W, literal.y,
; EG-NEXT:    252645135(7.053345e-30), 4(5.605194e-45)
; EG-NEXT:     AND_INT T0.W, PS, literal.x,
; EG-NEXT:     LSHL * T1.W, PV.W, literal.y,
; EG-NEXT:    252645135(7.053345e-30), 4(5.605194e-45)
; EG-NEXT:     OR_INT * T0.W, PV.W, PS,
; EG-NEXT:     AND_INT T1.W, PV.W, literal.x,
; EG-NEXT:     LSHR * T0.W, PV.W, literal.y,
; EG-NEXT:    858993459(4.172325e-08), 2(2.802597e-45)
; EG-NEXT:     AND_INT T0.W, PS, literal.x,
; EG-NEXT:     LSHL * T1.W, PV.W, literal.y,
; EG-NEXT:    858993459(4.172325e-08), 2(2.802597e-45)
; EG-NEXT:     OR_INT * T0.W, PV.W, PS,
; EG-NEXT:     AND_INT T1.W, PV.W, literal.x,
; EG-NEXT:     LSHR * T0.W, PV.W, 1,
; EG-NEXT:    1431655765(1.466015e+13), 0(0.000000e+00)
; EG-NEXT:     AND_INT T0.W, PS, literal.x,
; EG-NEXT:     LSHL * T1.W, PV.W, 1,
; EG-NEXT:    1431655765(1.466015e+13), 0(0.000000e+00)
; EG-NEXT:     OR_INT T0.X, PV.W, PS,
; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
  %a.ext = zext i32 %a to i64
  %b.ext = zext i32 %b to i64
  %clmul = call i64 @llvm.clmul.i64(i64 %a.ext, i64 %b.ext)
  %res.ext = lshr i64 %clmul, 31
  %res = trunc i64 %res.ext to i32
  store i32 %res, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @test_clmulh_i32_uniform(ptr addrspace(1) %out, i32 %a, i32 %b) {
; SI-LABEL: test_clmulh_i32_uniform:
; SI:       ; %bb.0:
; SI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x9
; SI-NEXT:    s_mov_b32 s9, 0
; SI-NEXT:    s_mov_b32 s11, s9
; SI-NEXT:    s_mov_b32 s3, 0xf000
; SI-NEXT:    s_mov_b32 s2, -1
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    s_mov_b32 s8, s6
; SI-NEXT:    s_mov_b32 s0, s4
; SI-NEXT:    s_mov_b32 s1, s5
; SI-NEXT:    s_ashr_i32 s10, s7, 31
; SI-NEXT:    s_lshl_b64 s[4:5], s[8:9], 31
; SI-NEXT:    s_and_b32 s5, s10, s5
; SI-NEXT:    s_and_b32 s4, s10, s4
; SI-NEXT:    s_bfe_i32 s10, s7, 0x10000
; SI-NEXT:    s_and_b32 s10, s10, s6
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 1
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10001
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 2
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10002
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 3
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10003
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 4
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10004
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 5
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10005
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 6
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10006
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 7
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10007
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 8
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10008
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 9
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10009
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 10
; SI-NEXT:    s_bfe_i32 s6, s7, 0x1000a
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 11
; SI-NEXT:    s_bfe_i32 s6, s7, 0x1000b
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 12
; SI-NEXT:    s_bfe_i32 s6, s7, 0x1000c
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 13
; SI-NEXT:    s_bfe_i32 s6, s7, 0x1000d
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 14
; SI-NEXT:    s_bfe_i32 s6, s7, 0x1000e
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 15
; SI-NEXT:    s_bfe_i32 s6, s7, 0x1000f
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 16
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10010
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 17
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10011
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 18
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10012
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 19
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10013
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 20
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10014
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 21
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10015
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 22
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10016
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 23
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10017
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 24
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10018
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 25
; SI-NEXT:    s_bfe_i32 s6, s7, 0x10019
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 26
; SI-NEXT:    s_bfe_i32 s6, s7, 0x1001a
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 27
; SI-NEXT:    s_bfe_i32 s6, s7, 0x1001b
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 28
; SI-NEXT:    s_bfe_i32 s6, s7, 0x1001c
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 29
; SI-NEXT:    s_bfe_i32 s6, s7, 0x1001d
; SI-NEXT:    s_and_b32 s13, s6, s13
; SI-NEXT:    s_and_b32 s12, s6, s12
; SI-NEXT:    s_lshl_b64 s[8:9], s[8:9], 30
; SI-NEXT:    s_bfe_i32 s6, s7, 0x1001e
; SI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; SI-NEXT:    s_and_b32 s7, s6, s9
; SI-NEXT:    s_and_b32 s6, s6, s8
; SI-NEXT:    s_xor_b64 s[6:7], s[10:11], s[6:7]
; SI-NEXT:    s_xor_b64 s[4:5], s[6:7], s[4:5]
; SI-NEXT:    v_mov_b32_e32 v0, s5
; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT:    s_endpgm
;
; VI-LABEL: test_clmulh_i32_uniform:
; VI:       ; %bb.0:
; VI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x24
; VI-NEXT:    s_mov_b32 s9, 0
; VI-NEXT:    s_mov_b32 s11, s9
; VI-NEXT:    s_mov_b32 s3, 0xf000
; VI-NEXT:    s_mov_b32 s2, -1
; VI-NEXT:    s_waitcnt lgkmcnt(0)
; VI-NEXT:    s_mov_b32 s8, s6
; VI-NEXT:    s_mov_b32 s0, s4
; VI-NEXT:    s_mov_b32 s1, s5
; VI-NEXT:    s_ashr_i32 s10, s7, 31
; VI-NEXT:    s_lshl_b64 s[4:5], s[8:9], 31
; VI-NEXT:    s_and_b32 s5, s10, s5
; VI-NEXT:    s_and_b32 s4, s10, s4
; VI-NEXT:    s_bfe_i32 s10, s7, 0x10000
; VI-NEXT:    s_and_b32 s10, s10, s6
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 1
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10001
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 2
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10002
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 3
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10003
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 4
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10004
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 5
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10005
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 6
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10006
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 7
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10007
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 8
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10008
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 9
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10009
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 10
; VI-NEXT:    s_bfe_i32 s6, s7, 0x1000a
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 11
; VI-NEXT:    s_bfe_i32 s6, s7, 0x1000b
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 12
; VI-NEXT:    s_bfe_i32 s6, s7, 0x1000c
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 13
; VI-NEXT:    s_bfe_i32 s6, s7, 0x1000d
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 14
; VI-NEXT:    s_bfe_i32 s6, s7, 0x1000e
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 15
; VI-NEXT:    s_bfe_i32 s6, s7, 0x1000f
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 16
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10010
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 17
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10011
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 18
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10012
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 19
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10013
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 20
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10014
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 21
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10015
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 22
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10016
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 23
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10017
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 24
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10018
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 25
; VI-NEXT:    s_bfe_i32 s6, s7, 0x10019
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 26
; VI-NEXT:    s_bfe_i32 s6, s7, 0x1001a
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 27
; VI-NEXT:    s_bfe_i32 s6, s7, 0x1001b
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 28
; VI-NEXT:    s_bfe_i32 s6, s7, 0x1001c
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_lshl_b64 s[12:13], s[8:9], 29
; VI-NEXT:    s_bfe_i32 s6, s7, 0x1001d
; VI-NEXT:    s_and_b32 s13, s6, s13
; VI-NEXT:    s_and_b32 s12, s6, s12
; VI-NEXT:    s_lshl_b64 s[8:9], s[8:9], 30
; VI-NEXT:    s_bfe_i32 s6, s7, 0x1001e
; VI-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; VI-NEXT:    s_and_b32 s7, s6, s9
; VI-NEXT:    s_and_b32 s6, s6, s8
; VI-NEXT:    s_xor_b64 s[6:7], s[10:11], s[6:7]
; VI-NEXT:    s_xor_b64 s[4:5], s[6:7], s[4:5]
; VI-NEXT:    v_mov_b32_e32 v0, s5
; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT:    s_endpgm
;
; GFX9-LABEL: test_clmulh_i32_uniform:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x24
; GFX9-NEXT:    s_mov_b32 s7, 0
; GFX9-NEXT:    s_mov_b32 s3, 0xf000
; GFX9-NEXT:    s_mov_b32 s2, -1
; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-NEXT:    s_mov_b32 s6, s10
; GFX9-NEXT:    s_mov_b32 s0, s8
; GFX9-NEXT:    s_ashr_i32 s8, s11, 31
; GFX9-NEXT:    s_lshl_b64 s[4:5], s[6:7], 31
; GFX9-NEXT:    s_and_b32 s5, s8, s5
; GFX9-NEXT:    s_and_b32 s4, s8, s4
; GFX9-NEXT:    s_bfe_i32 s8, s11, 0x10000
; GFX9-NEXT:    s_and_b32 s8, s8, s10
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 1
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10001
; GFX9-NEXT:    s_mov_b32 s1, s9
; GFX9-NEXT:    s_mov_b32 s9, s7
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 2
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10002
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 3
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10003
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 4
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10004
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 5
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10005
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 6
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10006
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 7
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10007
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 8
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10008
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 9
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10009
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 10
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x1000a
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 11
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x1000b
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 12
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x1000c
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 13
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x1000d
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 14
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x1000e
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 15
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x1000f
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 16
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10010
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 17
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10011
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 18
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10012
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 19
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10013
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 20
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10014
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 21
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10015
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 22
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10016
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 23
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10017
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 24
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10018
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 25
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x10019
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 26
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x1001a
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 27
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x1001b
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 28
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x1001c
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], 29
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x1001d
; GFX9-NEXT:    s_and_b32 s13, s10, s13
; GFX9-NEXT:    s_and_b32 s12, s10, s12
; GFX9-NEXT:    s_lshl_b64 s[6:7], s[6:7], 30
; GFX9-NEXT:    s_bfe_i32 s10, s11, 0x1001e
; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT:    s_and_b32 s7, s10, s7
; GFX9-NEXT:    s_and_b32 s6, s10, s6
; GFX9-NEXT:    s_xor_b64 s[6:7], s[8:9], s[6:7]
; GFX9-NEXT:    s_xor_b64 s[4:5], s[6:7], s[4:5]
; GFX9-NEXT:    v_mov_b32_e32 v0, s5
; GFX9-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; GFX9-NEXT:    s_endpgm
;
; GFX10-LABEL: test_clmulh_i32_uniform:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX10-NEXT:    s_mov_b32 s5, 0
; GFX10-NEXT:    s_mov_b32 s11, s5
; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
; GFX10-NEXT:    s_mov_b32 s4, s2
; GFX10-NEXT:    s_bfe_i32 s9, s3, 0x10000
; GFX10-NEXT:    s_bfe_i32 s24, s3, 0x10001
; GFX10-NEXT:    s_lshl_b64 s[12:13], s[4:5], 1
; GFX10-NEXT:    s_bfe_i32 s25, s3, 0x10002
; GFX10-NEXT:    s_and_b32 s10, s9, s2
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 2
; GFX10-NEXT:    s_and_b32 s13, s24, s13
; GFX10-NEXT:    s_and_b32 s12, s24, s12
; GFX10-NEXT:    s_bfe_i32 s26, s3, 0x10003
; GFX10-NEXT:    s_lshl_b64 s[16:17], s[4:5], 3
; GFX10-NEXT:    s_and_b32 s15, s25, s15
; GFX10-NEXT:    s_and_b32 s14, s25, s14
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_bfe_i32 s27, s3, 0x10004
; GFX10-NEXT:    s_lshl_b64 s[18:19], s[4:5], 4
; GFX10-NEXT:    s_and_b32 s17, s26, s17
; GFX10-NEXT:    s_and_b32 s16, s26, s16
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[14:15]
; GFX10-NEXT:    s_bfe_i32 s28, s3, 0x10005
; GFX10-NEXT:    s_lshl_b64 s[20:21], s[4:5], 5
; GFX10-NEXT:    s_and_b32 s19, s27, s19
; GFX10-NEXT:    s_and_b32 s18, s27, s18
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[16:17]
; GFX10-NEXT:    s_bfe_i32 s29, s3, 0x10006
; GFX10-NEXT:    s_lshl_b64 s[22:23], s[4:5], 6
; GFX10-NEXT:    s_and_b32 s13, s28, s21
; GFX10-NEXT:    s_and_b32 s12, s28, s20
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[18:19]
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 7
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s29, s23
; GFX10-NEXT:    s_and_b32 s12, s29, s22
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x10007
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 8
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x10008
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 9
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x10009
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 10
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x1000a
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 11
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x1000b
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 12
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x1000c
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 13
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x1000d
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 14
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x1000e
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 15
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x1000f
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 16
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x10010
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 17
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x10011
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 18
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x10012
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 19
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x10013
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 20
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x10014
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 21
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x10015
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 22
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x10016
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 23
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x10017
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 24
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x10018
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 25
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x10019
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 26
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x1001a
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 27
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x1001b
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 28
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x1001c
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[14:15], s[4:5], 29
; GFX10-NEXT:    s_bfe_i32 s2, s3, 0x1001d
; GFX10-NEXT:    s_lshl_b64 s[6:7], s[4:5], 31
; GFX10-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s13, s2, s15
; GFX10-NEXT:    s_and_b32 s12, s2, s14
; GFX10-NEXT:    s_lshl_b64 s[4:5], s[4:5], 30
; GFX10-NEXT:    s_bfe_i32 s9, s3, 0x1001e
; GFX10-NEXT:    s_ashr_i32 s8, s3, 31
; GFX10-NEXT:    s_xor_b64 s[2:3], s[10:11], s[12:13]
; GFX10-NEXT:    s_and_b32 s5, s9, s5
; GFX10-NEXT:    s_and_b32 s4, s9, s4
; GFX10-NEXT:    s_and_b32 s7, s8, s7
; GFX10-NEXT:    s_and_b32 s6, s8, s6
; GFX10-NEXT:    s_xor_b64 s[2:3], s[2:3], s[4:5]
; GFX10-NEXT:    s_xor_b64 s[4:5], s[2:3], s[6:7]
; GFX10-NEXT:    s_mov_b32 s3, 0x31016000
; GFX10-NEXT:    v_mov_b32_e32 v0, s5
; GFX10-NEXT:    s_mov_b32 s2, -1
; GFX10-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; GFX10-NEXT:    s_endpgm
;
; GFX11-LABEL: test_clmulh_i32_uniform:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-NEXT:    s_mov_b32 s5, 0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_mov_b32 s11, s5
; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s4, s2
; GFX11-NEXT:    s_bfe_i32 s9, s3, 0x10000
; GFX11-NEXT:    s_bfe_i32 s24, s3, 0x10001
; GFX11-NEXT:    s_lshl_b64 s[12:13], s[4:5], 1
; GFX11-NEXT:    s_bfe_i32 s25, s3, 0x10002
; GFX11-NEXT:    s_and_b32 s10, s9, s2
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 2
; GFX11-NEXT:    s_and_b32 s13, s24, s13
; GFX11-NEXT:    s_and_b32 s12, s24, s12
; GFX11-NEXT:    s_bfe_i32 s26, s3, 0x10003
; GFX11-NEXT:    s_lshl_b64 s[16:17], s[4:5], 3
; GFX11-NEXT:    s_and_b32 s15, s25, s15
; GFX11-NEXT:    s_and_b32 s14, s25, s14
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_bfe_i32 s27, s3, 0x10004
; GFX11-NEXT:    s_lshl_b64 s[18:19], s[4:5], 4
; GFX11-NEXT:    s_and_b32 s17, s26, s17
; GFX11-NEXT:    s_and_b32 s16, s26, s16
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[14:15]
; GFX11-NEXT:    s_bfe_i32 s28, s3, 0x10005
; GFX11-NEXT:    s_lshl_b64 s[20:21], s[4:5], 5
; GFX11-NEXT:    s_and_b32 s19, s27, s19
; GFX11-NEXT:    s_and_b32 s18, s27, s18
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[16:17]
; GFX11-NEXT:    s_bfe_i32 s29, s3, 0x10006
; GFX11-NEXT:    s_lshl_b64 s[22:23], s[4:5], 6
; GFX11-NEXT:    s_and_b32 s13, s28, s21
; GFX11-NEXT:    s_and_b32 s12, s28, s20
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[18:19]
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 7
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s29, s23
; GFX11-NEXT:    s_and_b32 s12, s29, s22
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x10007
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 8
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x10008
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 9
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x10009
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 10
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x1000a
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 11
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x1000b
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 12
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x1000c
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 13
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x1000d
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 14
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x1000e
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 15
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x1000f
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 16
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x10010
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 17
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x10011
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 18
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x10012
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 19
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x10013
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 20
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x10014
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 21
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x10015
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 22
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x10016
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 23
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x10017
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 24
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x10018
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 25
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x10019
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 26
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x1001a
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 27
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x1001b
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 28
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x1001c
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[14:15], s[4:5], 29
; GFX11-NEXT:    s_bfe_i32 s2, s3, 0x1001d
; GFX11-NEXT:    s_lshl_b64 s[6:7], s[4:5], 31
; GFX11-NEXT:    s_xor_b64 s[10:11], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s13, s2, s15
; GFX11-NEXT:    s_and_b32 s12, s2, s14
; GFX11-NEXT:    s_lshl_b64 s[4:5], s[4:5], 30
; GFX11-NEXT:    s_bfe_i32 s9, s3, 0x1001e
; GFX11-NEXT:    s_ashr_i32 s8, s3, 31
; GFX11-NEXT:    s_xor_b64 s[2:3], s[10:11], s[12:13]
; GFX11-NEXT:    s_and_b32 s5, s9, s5
; GFX11-NEXT:    s_and_b32 s4, s9, s4
; GFX11-NEXT:    s_and_b32 s7, s8, s7
; GFX11-NEXT:    s_and_b32 s6, s8, s6
; GFX11-NEXT:    s_xor_b64 s[2:3], s[2:3], s[4:5]
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_xor_b64 s[4:5], s[2:3], s[6:7]
; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
; GFX11-NEXT:    v_mov_b32_e32 v0, s5
; GFX11-NEXT:    s_mov_b32 s2, -1
; GFX11-NEXT:    buffer_store_b32 v0, off, s[0:3], 0
; GFX11-NEXT:    s_endpgm
;
; GFX12-LABEL: test_clmulh_i32_uniform:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT:    s_mov_b32 s5, 0
; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-NEXT:    s_mov_b32 s7, s5
; GFX12-NEXT:    s_mov_b32 s9, s5
; GFX12-NEXT:    s_mov_b32 s11, s5
; GFX12-NEXT:    s_mov_b32 s13, s5
; GFX12-NEXT:    s_mov_b32 s15, s5
; GFX12-NEXT:    s_mov_b32 s17, s5
; GFX12-NEXT:    s_mov_b32 s19, s5
; GFX12-NEXT:    s_mov_b32 s20, s5
; GFX12-NEXT:    s_mov_b32 s22, s5
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    s_and_b32 s4, s3, 0x11111111
; GFX12-NEXT:    s_and_b32 s6, s2, 0x22222222
; GFX12-NEXT:    s_and_b32 s8, s3, 0x22222222
; GFX12-NEXT:    s_and_b32 s10, s2, 0x11111111
; GFX12-NEXT:    s_and_b32 s12, s3, 0x88888888
; GFX12-NEXT:    s_and_b32 s14, s2, 0x44444444
; GFX12-NEXT:    s_and_b32 s16, s3, 0x44444444
; GFX12-NEXT:    s_and_b32 s18, s2, 0x88888888
; GFX12-NEXT:    s_mul_u64 s[2:3], s[6:7], s[4:5]
; GFX12-NEXT:    s_mul_u64 s[24:25], s[10:11], s[8:9]
; GFX12-NEXT:    s_mul_u64 s[30:31], s[6:7], s[12:13]
; GFX12-NEXT:    s_mul_u64 s[34:35], s[10:11], s[4:5]
; GFX12-NEXT:    s_mul_u64 s[26:27], s[14:15], s[12:13]
; GFX12-NEXT:    s_mul_u64 s[36:37], s[14:15], s[16:17]
; GFX12-NEXT:    s_xor_b64 s[2:3], s[24:25], s[2:3]
; GFX12-NEXT:    s_xor_b64 s[24:25], s[34:35], s[30:31]
; GFX12-NEXT:    s_mul_u64 s[28:29], s[18:19], s[16:17]
; GFX12-NEXT:    s_mul_u64 s[38:39], s[18:19], s[8:9]
; GFX12-NEXT:    s_xor_b64 s[2:3], s[2:3], s[26:27]
; GFX12-NEXT:    s_xor_b64 s[24:25], s[24:25], s[36:37]
; GFX12-NEXT:    s_xor_b64 s[2:3], s[2:3], s[28:29]
; GFX12-NEXT:    s_xor_b64 s[24:25], s[24:25], s[38:39]
; GFX12-NEXT:    s_mul_u64 s[40:41], s[6:7], s[8:9]
; GFX12-NEXT:    s_mul_u64 s[42:43], s[10:11], s[16:17]
; GFX12-NEXT:    s_and_b32 s21, s3, 0x22222222
; GFX12-NEXT:    s_and_b32 s23, s25, 0x11111111
; GFX12-NEXT:    s_mul_u64 s[6:7], s[6:7], s[16:17]
; GFX12-NEXT:    s_or_b64 s[2:3], s[22:23], s[20:21]
; GFX12-NEXT:    s_mul_u64 s[20:21], s[14:15], s[4:5]
; GFX12-NEXT:    s_xor_b64 s[22:23], s[42:43], s[40:41]
; GFX12-NEXT:    s_mul_u64 s[10:11], s[10:11], s[12:13]
; GFX12-NEXT:    s_mul_u64 s[24:25], s[18:19], s[12:13]
; GFX12-NEXT:    s_xor_b64 s[12:13], s[22:23], s[20:21]
; GFX12-NEXT:    s_mul_u64 s[8:9], s[14:15], s[8:9]
; GFX12-NEXT:    s_xor_b64 s[6:7], s[10:11], s[6:7]
; GFX12-NEXT:    s_xor_b64 s[12:13], s[12:13], s[24:25]
; GFX12-NEXT:    s_mul_u64 s[14:15], s[18:19], s[4:5]
; GFX12-NEXT:    s_xor_b64 s[6:7], s[6:7], s[8:9]
; GFX12-NEXT:    s_and_b32 s11, s13, 0x44444444
; GFX12-NEXT:    s_mov_b32 s10, s5
; GFX12-NEXT:    s_xor_b64 s[6:7], s[6:7], s[14:15]
; GFX12-NEXT:    s_or_b64 s[2:3], s[2:3], s[10:11]
; GFX12-NEXT:    s_and_b32 s7, s7, 0x88888888
; GFX12-NEXT:    s_mov_b32 s6, s5
; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-NEXT:    s_or_b64 s[2:3], s[2:3], s[6:7]
; GFX12-NEXT:    s_mov_b32 s2, -1
; GFX12-NEXT:    v_mov_b32_e32 v0, s3
; GFX12-NEXT:    s_mov_b32 s3, 0x31016000
; GFX12-NEXT:    buffer_store_b32 v0, off, s[0:3], null
; GFX12-NEXT:    s_endpgm
;
; GFX1250-LABEL: test_clmulh_i32_uniform:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-NEXT:    v_nop
; GFX1250-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
; GFX1250-NEXT:    s_wait_xcnt 0x0
; GFX1250-NEXT:    s_mov_b32 s5, 0
; GFX1250-NEXT:    s_mov_b64 s[6:7], 0x88888888
; GFX1250-NEXT:    s_mov_b32 s9, s5
; GFX1250-NEXT:    s_mov_b32 s11, s5
; GFX1250-NEXT:    s_mov_b32 s13, s5
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    s_mov_b32 s4, s3
; GFX1250-NEXT:    s_and_b32 s8, s2, 0x22222222
; GFX1250-NEXT:    s_and_b32 s10, s2, 0x11111111
; GFX1250-NEXT:    s_and_b64 s[14:15], s[4:5], 0x11111111
; GFX1250-NEXT:    s_and_b64 s[16:17], s[4:5], 0x22222222
; GFX1250-NEXT:    s_and_b64 s[6:7], s[4:5], s[6:7]
; GFX1250-NEXT:    s_and_b32 s12, s2, 0x44444444
; GFX1250-NEXT:    s_and_b64 s[18:19], s[4:5], 0x44444444
; GFX1250-NEXT:    s_and_b32 s4, s2, 0x88888888
; GFX1250-NEXT:    s_mul_u64 s[2:3], s[8:9], s[14:15]
; GFX1250-NEXT:    s_mul_u64 s[20:21], s[10:11], s[16:17]
; GFX1250-NEXT:    s_mul_u64 s[26:27], s[8:9], s[6:7]
; GFX1250-NEXT:    s_mul_u64 s[28:29], s[10:11], s[14:15]
; GFX1250-NEXT:    s_mul_u64 s[22:23], s[12:13], s[6:7]
; GFX1250-NEXT:    s_mul_u64 s[24:25], s[4:5], s[18:19]
; GFX1250-NEXT:    s_mul_u64 s[30:31], s[12:13], s[18:19]
; GFX1250-NEXT:    s_mul_u64 s[36:37], s[8:9], s[16:17]
; GFX1250-NEXT:    s_mul_u64 s[38:39], s[10:11], s[18:19]
; GFX1250-NEXT:    s_mul_u64 s[8:9], s[8:9], s[18:19]
; GFX1250-NEXT:    s_xor_b64 s[2:3], s[20:21], s[2:3]
; GFX1250-NEXT:    s_xor_b64 s[18:19], s[28:29], s[26:27]
; GFX1250-NEXT:    s_mul_u64 s[34:35], s[4:5], s[16:17]
; GFX1250-NEXT:    s_mul_u64 s[40:41], s[12:13], s[14:15]
; GFX1250-NEXT:    s_mul_u64 s[10:11], s[10:11], s[6:7]
; GFX1250-NEXT:    s_xor_b64 s[2:3], s[2:3], s[22:23]
; GFX1250-NEXT:    s_xor_b64 s[18:19], s[18:19], s[30:31]
; GFX1250-NEXT:    s_xor_b64 s[20:21], s[38:39], s[36:37]
; GFX1250-NEXT:    s_xor_b64 s[2:3], s[2:3], s[24:25]
; GFX1250-NEXT:    s_xor_b64 s[18:19], s[18:19], s[34:35]
; GFX1250-NEXT:    s_mul_u64 s[6:7], s[4:5], s[6:7]
; GFX1250-NEXT:    s_mul_u64 s[12:13], s[12:13], s[16:17]
; GFX1250-NEXT:    s_xor_b64 s[16:17], s[20:21], s[40:41]
; GFX1250-NEXT:    s_xor_b64 s[8:9], s[10:11], s[8:9]
; GFX1250-NEXT:    s_and_b64 s[2:3], s[2:3], 0x2222222200000000
; GFX1250-NEXT:    s_and_b64 s[18:19], s[18:19], 0x1111111100000000
; GFX1250-NEXT:    s_mul_u64 s[4:5], s[4:5], s[14:15]
; GFX1250-NEXT:    s_xor_b64 s[6:7], s[16:17], s[6:7]
; GFX1250-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX1250-NEXT:    s_or_b64 s[2:3], s[18:19], s[2:3]
; GFX1250-NEXT:    s_and_b64 s[6:7], s[6:7], 0x4444444400000000
; GFX1250-NEXT:    s_xor_b64 s[4:5], s[8:9], s[4:5]
; GFX1250-NEXT:    s_or_b64 s[2:3], s[2:3], s[6:7]
; GFX1250-NEXT:    s_and_b64 s[4:5], s[4:5], 0x8888888800000000
; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT:    s_or_b64 s[4:5], s[2:3], s[4:5]
; GFX1250-NEXT:    s_mov_b32 s3, 0x31016000
; GFX1250-NEXT:    v_mov_b32_e32 v0, s5
; GFX1250-NEXT:    s_mov_b32 s2, -1
; GFX1250-NEXT:    buffer_store_b32 v0, off, s[0:3], null
; GFX1250-NEXT:    s_endpgm
;
; EG-LABEL: test_clmulh_i32_uniform:
; EG:       ; %bb.0:
; EG-NEXT:    ALU 92, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT:    ALU 53, @97, KC0[CB0:0-32], KC1[]
; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
; EG-NEXT:    CF_END
; EG-NEXT:    ALU clause starting at 4:
; EG-NEXT:     AND_INT T0.W, KC0[2].Z, literal.x,
; EG-NEXT:     LSHR * T1.W, KC0[2].Z, literal.y,
; EG-NEXT:    65280(9.147676e-41), 8(1.121039e-44)
; EG-NEXT:     AND_INT T0.X, PS, literal.x,
; EG-NEXT:     LSHR T0.Y, KC0[2].Z, literal.y,
; EG-NEXT:     LSHL T0.Z, PV.W, literal.z,
; EG-NEXT:     AND_INT T0.W, KC0[2].W, literal.x,
; EG-NEXT:     LSHR * T1.W, KC0[2].W, literal.z,
; EG-NEXT:    65280(9.147676e-41), 24(3.363116e-44)
; EG-NEXT:    8(1.121039e-44), 0(0.000000e+00)
; EG-NEXT:     LSHL T1.X, KC0[2].Z, literal.x,
; EG-NEXT:     AND_INT T1.Y, PS, literal.y,
; EG-NEXT:     LSHR T1.Z, KC0[2].W, literal.x,
; EG-NEXT:     LSHL T0.W, PV.W, literal.z,
; EG-NEXT:     LSHL * T1.W, KC0[2].W, literal.x,
; EG-NEXT:    24(3.363116e-44), 65280(9.147676e-41)
; EG-NEXT:    8(1.121039e-44), 0(0.000000e+00)
; EG-NEXT:     OR_INT T2.Y, PS, PV.W,
; EG-NEXT:     OR_INT T1.Z, PV.Y, PV.Z,
; EG-NEXT:     OR_INT T0.W, PV.X, T0.Z,
; EG-NEXT:     OR_INT * T1.W, T0.X, T0.Y,
; EG-NEXT:     OR_INT T0.W, PV.W, PS,
; EG-NEXT:     OR_INT * T1.W, PV.Y, PV.Z,
; EG-NEXT:     AND_INT T0.Y, PS, literal.x,
; EG-NEXT:     LSHR T0.Z, PS, literal.y,
; EG-NEXT:     AND_INT T1.W, PV.W, literal.x,
; EG-NEXT:     LSHR * T0.W, PV.W, literal.y,
; EG-NEXT:    252645135(7.053345e-30), 4(5.605194e-45)
; EG-NEXT:     AND_INT T1.Y, PS, literal.x,
; EG-NEXT:     LSHL T1.Z, PV.W, literal.y,
; EG-NEXT:     AND_INT T0.W, PV.Z, literal.x,
; EG-NEXT:     LSHL * T1.W, PV.Y, literal.y,
; EG-NEXT:    252645135(7.053345e-30), 4(5.605194e-45)
; EG-NEXT:     OR_INT T0.W, PV.W, PS,
; EG-NEXT:     OR_INT * T1.W, PV.Y, PV.Z,
; EG-NEXT:     AND_INT T0.Y, PS, literal.x,
; EG-NEXT:     LSHR T0.Z, PS, literal.y,
; EG-NEXT:     AND_INT T1.W, PV.W, literal.x,
; EG-NEXT:     LSHR * T0.W, PV.W, literal.y,
; EG-NEXT:    858993459(4.172325e-08), 2(2.802597e-45)
; EG-NEXT:     AND_INT T1.Y, PS, literal.x,
; EG-NEXT:     LSHL T1.Z, PV.W, literal.y,
; EG-NEXT:     AND_INT T0.W, PV.Z, literal.x,
; EG-NEXT:     LSHL * T1.W, PV.Y, literal.y,
; EG-NEXT:    858993459(4.172325e-08), 2(2.802597e-45)
; EG-NEXT:     OR_INT T0.W, PV.W, PS,
; EG-NEXT:     OR_INT * T1.W, PV.Y, PV.Z,
; EG-NEXT:     AND_INT T0.Y, PS, literal.x,
; EG-NEXT:     LSHR T0.Z, PS, 1,
; EG-NEXT:     AND_INT T1.W, PV.W, literal.x,
; EG-NEXT:     LSHR * T0.W, PV.W, 1,
; EG-NEXT:    1431655765(1.466015e+13), 0(0.000000e+00)
; EG-NEXT:     AND_INT T1.Y, PS, literal.x,
; EG-NEXT:     LSHL T1.Z, PV.W, 1,
; EG-NEXT:     AND_INT T0.W, PV.Z, literal.x,
; EG-NEXT:     LSHL * T1.W, PV.Y, 1,
; EG-NEXT:    1431655765(1.466015e+13), 0(0.000000e+00)
; EG-NEXT:     OR_INT T0.W, PV.W, PS,
; EG-NEXT:     OR_INT * T1.W, PV.Y, PV.Z,
; EG-NEXT:     AND_INT T2.W, PS, literal.x,
; EG-NEXT:     AND_INT * T3.W, PV.W, literal.y,
; EG-NEXT:    1145324612(7.850667e+02), 572662306(2.197316e-18)
; EG-NEXT:     AND_INT T4.W, T0.W, literal.x,
; EG-NEXT:     MULLO_INT * T0.X, PV.W, PS,
; EG-NEXT:    286331153(1.144374e-28), 0(0.000000e+00)
; EG-NEXT:     AND_INT T5.W, T1.W, literal.x,
; EG-NEXT:     MULLO_INT * T0.Y, T2.W, PV.W,
; EG-NEXT:    -2004318072(-8.217301e-34), 0(0.000000e+00)
; EG-NEXT:     AND_INT T6.W, T0.W, literal.x,
; EG-NEXT:     MULLO_INT * T0.Z, PV.W, T3.W,
; EG-NEXT:    1145324612(7.850667e+02), 0(0.000000e+00)
; EG-NEXT:     AND_INT T1.Z, T0.W, literal.x,
; EG-NEXT:     AND_INT T0.W, T1.W, literal.y, BS:VEC_120/SCL_212
; EG-NEXT:     MULLO_INT * T1.X, T5.W, PV.W,
; EG-NEXT:    -2004318072(-8.217301e-34), 286331153(1.144374e-28)
; EG-NEXT:     MULLO_INT * T1.Y, PV.W, PV.Z,
; EG-NEXT:     MULLO_INT * T2.X, T2.W, T1.Z,
; EG-NEXT:     MULLO_INT * T2.Y, T2.W, T6.W,
; EG-NEXT:     MULLO_INT * T2.Z, T0.W, T6.W,
; EG-NEXT:     AND_INT T1.W, T1.W, literal.x,
; EG-NEXT:     MULLO_INT * T2.W, T0.W, T4.W,
; EG-NEXT:    572662306(2.197316e-18), 0(0.000000e+00)
; EG-NEXT:     MULLO_INT * T3.X, PV.W, T1.Z,
; EG-NEXT:     MULLO_INT * T0.W, T0.W, T3.W,
; EG-NEXT:     MULLO_INT * T3.Y, T1.W, T4.W,
; EG-NEXT:     XOR_INT T3.Z, T0.W, PS,
; EG-NEXT:     XOR_INT * T0.W, T2.W, T3.X, BS:VEC_120/SCL_212
; EG-NEXT:     MULLO_INT * T2.W, T1.W, T3.W,
; EG-NEXT:     XOR_INT T3.Y, T2.Z, PS,
; EG-NEXT:     XOR_INT T2.Z, T0.W, T2.Y,
; EG-NEXT:     XOR_INT T0.W, T3.Z, T2.X, BS:VEC_120/SCL_212
; EG-NEXT:     MULLO_INT * T1.W, T1.W, T6.W,
; EG-NEXT:     XOR_INT * T2.X, T1.Y, PS,
; EG-NEXT:    ALU clause starting at 97:
; EG-NEXT:     XOR_INT T1.Y, T0.W, T1.X,
; EG-NEXT:     XOR_INT T0.Z, T2.Z, T0.Z, BS:VEC_021/SCL_122
; EG-NEXT:     XOR_INT T0.W, T3.Y, T0.Y,
; EG-NEXT:     MULLO_INT * T0.Y, T5.W, T1.Z,
; EG-NEXT:     XOR_INT T1.X, PV.W, PS,
; EG-NEXT:     AND_INT T0.Y, PV.Z, literal.x,
; EG-NEXT:     AND_INT T0.Z, PV.Y, literal.y,
; EG-NEXT:     XOR_INT T0.W, T2.X, T0.X,
; EG-NEXT:     MULLO_INT * T0.X, T5.W, T4.W,
; EG-NEXT:    286331153(1.144374e-28), 572662306(2.197316e-18)
; EG-NEXT:     XOR_INT T1.Z, PV.W, PS,
; EG-NEXT:     OR_INT T0.W, PV.Y, PV.Z,
; EG-NEXT:     AND_INT * T1.W, PV.X, literal.x,
; EG-NEXT:    1145324612(7.850667e+02), 0(0.000000e+00)
; EG-NEXT:     OR_INT T0.W, PV.W, PS,
; EG-NEXT:     AND_INT * T1.W, PV.Z, literal.x,
; EG-NEXT:    -2004318072(-8.217301e-34), 0(0.000000e+00)
; EG-NEXT:     OR_INT * T0.W, PV.W, PS,
; EG-NEXT:     AND_INT T1.W, PV.W, literal.x,
; EG-NEXT:     LSHR * T2.W, PV.W, literal.y,
; EG-NEXT:    65280(9.147676e-41), 8(1.121039e-44)
; EG-NEXT:     AND_INT T0.Y, PS, literal.x,
; EG-NEXT:     LSHR T0.Z, T0.W, literal.y,
; EG-NEXT:     LSHL T1.W, PV.W, literal.z,
; EG-NEXT:     LSHL * T0.W, T0.W, literal.y,
; EG-NEXT:    65280(9.147676e-41), 24(3.363116e-44)
; EG-NEXT:    8(1.121039e-44), 0(0.000000e+00)
; EG-NEXT:     OR_INT T0.W, PS, PV.W,
; EG-NEXT:     OR_INT * T1.W, PV.Y, PV.Z,
; EG-NEXT:     OR_INT * T0.W, PV.W, PS,
; EG-NEXT:     AND_INT T1.W, PV.W, literal.x,
; EG-NEXT:     LSHR * T0.W, PV.W, literal.y,
; EG-NEXT:    252645135(7.053345e-30), 4(5.605194e-45)
; EG-NEXT:     AND_INT T0.W, PS, literal.x,
; EG-NEXT:     LSHL * T1.W, PV.W, literal.y,
; EG-NEXT:    252645135(7.053345e-30), 4(5.605194e-45)
; EG-NEXT:     OR_INT * T0.W, PV.W, PS,
; EG-NEXT:     AND_INT T1.W, PV.W, literal.x,
; EG-NEXT:     LSHR * T0.W, PV.W, literal.y,
; EG-NEXT:    858993459(4.172325e-08), 2(2.802597e-45)
; EG-NEXT:     AND_INT T0.W, PS, literal.x,
; EG-NEXT:     LSHL * T1.W, PV.W, literal.y,
; EG-NEXT:    858993459(4.172325e-08), 2(2.802597e-45)
; EG-NEXT:     OR_INT * T0.W, PV.W, PS,
; EG-NEXT:     AND_INT T1.W, PV.W, literal.x,
; EG-NEXT:     LSHR * T0.W, PV.W, 1,
; EG-NEXT:    1431655765(1.466015e+13), 0(0.000000e+00)
; EG-NEXT:     AND_INT T0.W, PS, literal.x,
; EG-NEXT:     LSHL * T1.W, PV.W, 1,
; EG-NEXT:    1431655764(1.466015e+13), 0(0.000000e+00)
; EG-NEXT:     OR_INT * T0.W, PV.W, PS,
; EG-NEXT:     LSHR T0.X, PV.W, 1,
; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
  %a.ext = zext i32 %a to i64
  %b.ext = zext i32 %b to i64
  %clmul = call i64 @llvm.clmul.i64(i64 %a.ext, i64 %b.ext)
  %res.ext = lshr i64 %clmul, 32
  %res = trunc i64 %res.ext to i32
  store i32 %res, ptr addrspace(1) %out
  ret void
}

declare i32 @llvm.amdgcn.workitem.id.x() #1

attributes #0 = { nounwind }
attributes #1 = { nounwind readnone}