llvm/test/CodeGen/AMDGPU/attr-amdgpu-align.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt  -S -mtriple=amdgpu-amd-amdhsa -passes=amdgpu-attributor %s -o - | FileCheck %s

define float @align_back_prop(ptr addrspace(1) align 4 %x) {
; CHECK-LABEL: define float @align_back_prop(
; CHECK-SAME: ptr addrspace(1) align 8 [[X:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT:    [[FAT_PTR:%.*]] = call align 8 ptr addrspace(7) @llvm.amdgcn.make.buffer.rsrc.p7.p1.i64(ptr addrspace(1) [[X]], i16 0, i64 256, i32 0)
; CHECK-NEXT:    [[Y:%.*]] = load float, ptr addrspace(7) [[FAT_PTR]], align 8
; CHECK-NEXT:    ret float [[Y]]
;
  %fat.ptr = call ptr addrspace(7) @llvm.amdgcn.make.buffer.rsrc.p7.p1.i64(ptr addrspace(1) %x, i16 0, i64 256, i32 0)
  %y = load float, ptr addrspace(7) %fat.ptr, align 8
  ret float %y
}

define float @align_foward_prop(ptr addrspace(1) align 8 %x) {
; CHECK-LABEL: define float @align_foward_prop(
; CHECK-SAME: ptr addrspace(1) align 8 [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:    [[FAT_PTR:%.*]] = call align 8 ptr addrspace(7) @llvm.amdgcn.make.buffer.rsrc.p7.p1.i64(ptr addrspace(1) [[X]], i16 0, i64 256, i32 0)
; CHECK-NEXT:    [[Y:%.*]] = load float, ptr addrspace(7) [[FAT_PTR]], align 8
; CHECK-NEXT:    ret float [[Y]]
;
  %fat.ptr = call ptr addrspace(7) @llvm.amdgcn.make.buffer.rsrc.p7.p1.i64(ptr addrspace(1) %x, i16 0, i64 256, i32 0)
  %y = load float, ptr addrspace(7) %fat.ptr, align 4
  ret float %y
}

define float @align_mix_prop(ptr addrspace(1) align 4 %x) {
; CHECK-LABEL: define float @align_mix_prop(
; CHECK-SAME: ptr addrspace(1) align 8 [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:    [[FAT_PTR:%.*]] = call align 8 ptr addrspace(7) @llvm.amdgcn.make.buffer.rsrc.p7.p1.i64(ptr addrspace(1) [[X]], i16 0, i64 256, i32 0)
; CHECK-NEXT:    [[Y:%.*]] = load float, ptr addrspace(7) [[FAT_PTR]], align 8
; CHECK-NEXT:    [[Z:%.*]] = load float, ptr addrspace(1) [[X]], align 8
; CHECK-NEXT:    ret float [[Z]]
;
  %fat.ptr = call ptr addrspace(7) @llvm.amdgcn.make.buffer.rsrc.p7.p1.i64(ptr addrspace(1) %x, i16 0, i64 256, i32 0)
  %y = load float, ptr addrspace(7) %fat.ptr, align 2
  %z = load float, ptr addrspace(1) %x, align 8
  ret float %z
}