| ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals all --version 4 | |
| ; RUN: opt < %s -passes=amdgpu-sw-lower-lds -amdgpu-asan-instrument-lds=false -S -mtriple=amdgpu-amd-amdhsa | FileCheck %s | |
| ; Test to check if static and dynamic LDS accesses are lowered correctly in kernel. | |
| @lds_1 = internal addrspace(3) global [1 x i8] poison, align 4 | |
| @lds_2 = internal addrspace(3) global [1 x i32] poison, align 8 | |
| @lds_3 = external addrspace(3) global [0 x i8], align 4 | |
| @lds_4 = external addrspace(3) global [0 x i8], align 8 | |
| ;. | |
| ; CHECK: @llvm.amdgcn.sw.lds.k0 = internal addrspace(3) global ptr poison, no_sanitize_address, align 8, !absolute_symbol [[META0:![0-9]+]] | |
| ; CHECK: @llvm.amdgcn.k0.dynlds = external addrspace(3) global [0 x i8], no_sanitize_address, align 8, !absolute_symbol [[META1:![0-9]+]] | |
| ; CHECK: @llvm.amdgcn.sw.lds.k0.md = internal addrspace(1) global %llvm.amdgcn.sw.lds.k0.md.type { %llvm.amdgcn.sw.lds.k0.md.item { i32 0, i32 8, i32 32 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 32, i32 1, i32 32 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 64, i32 4, i32 32 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 96, i32 0, i32 32 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 128, i32 0, i32 32 } }, no_sanitize_address | |
| ;. | |
| define amdgpu_kernel void @k0() sanitize_address { | |
| ; CHECK-LABEL: define amdgpu_kernel void @k0( | |
| ; CHECK-SAME: ) #[[ATTR0:[0-9]+]] { | |
| ; CHECK-NEXT: WId: | |
| ; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() | |
| ; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y() | |
| ; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.amdgcn.workitem.id.z() | |
| ; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP0]], [[TMP1]] | |
| ; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP3]], [[TMP2]] | |
| ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0 | |
| ; CHECK-NEXT: br i1 [[TMP5]], label [[MALLOC:%.*]], label [[TMP21:%.*]] | |
| ; CHECK: Malloc: | |
| ; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 24), align 4 | |
| ; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 32), align 4 | |
| ; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP9]], [[TMP7]] | |
| ; CHECK-NEXT: [[TMP6:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() | |
| ; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) [[TMP6]], i64 15 | |
| ; CHECK-NEXT: store i32 [[TMP8]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 36), align 4 | |
| ; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(4) [[TMP10]], align 4 | |
| ; CHECK-NEXT: store i32 [[TMP11]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 40), align 4 | |
| ; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[TMP11]], 7 | |
| ; CHECK-NEXT: [[TMP13:%.*]] = udiv i32 [[TMP12]], 8 | |
| ; CHECK-NEXT: [[TMP14:%.*]] = mul i32 [[TMP13]], 8 | |
| ; CHECK-NEXT: store i32 [[TMP14]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 44), align 4 | |
| ; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[TMP8]], [[TMP14]] | |
| ; CHECK-NEXT: store i32 [[TMP15]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 48), align 4 | |
| ; CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr addrspace(4) [[TMP10]], align 4 | |
| ; CHECK-NEXT: store i32 [[TMP31]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 52), align 4 | |
| ; CHECK-NEXT: [[TMP17:%.*]] = add i32 [[TMP31]], 7 | |
| ; CHECK-NEXT: [[TMP18:%.*]] = udiv i32 [[TMP17]], 8 | |
| ; CHECK-NEXT: [[TMP19:%.*]] = mul i32 [[TMP18]], 8 | |
| ; CHECK-NEXT: store i32 [[TMP19]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 56), align 4 | |
| ; CHECK-NEXT: [[TMP32:%.*]] = add i32 [[TMP15]], [[TMP19]] | |
| ; CHECK-NEXT: [[TMP30:%.*]] = zext i32 [[TMP32]] to i64 | |
| ; CHECK-NEXT: [[TMP22:%.*]] = call ptr @llvm.returnaddress.p0(i32 0) | |
| ; CHECK-NEXT: [[TMP23:%.*]] = ptrtoint ptr [[TMP22]] to i64 | |
| ; CHECK-NEXT: [[TMP39:%.*]] = call i64 @__asan_malloc_impl(i64 [[TMP30]], i64 [[TMP23]]) | |
| ; CHECK-NEXT: [[TMP20:%.*]] = inttoptr i64 [[TMP39]] to ptr addrspace(1) | |
| ; CHECK-NEXT: store ptr addrspace(1) [[TMP20]], ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8 | |
| ; CHECK-NEXT: [[TMP40:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP20]], i64 8 | |
| ; CHECK-NEXT: [[TMP41:%.*]] = ptrtoint ptr addrspace(1) [[TMP40]] to i64 | |
| ; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP41]], i64 24) | |
| ; CHECK-NEXT: [[TMP57:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP20]], i64 33 | |
| ; CHECK-NEXT: [[TMP111:%.*]] = ptrtoint ptr addrspace(1) [[TMP57]] to i64 | |
| ; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP111]], i64 31) | |
| ; CHECK-NEXT: [[TMP112:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP20]], i64 68 | |
| ; CHECK-NEXT: [[TMP113:%.*]] = ptrtoint ptr addrspace(1) [[TMP112]] to i64 | |
| ; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP113]], i64 28) | |
| ; CHECK-NEXT: br label [[TMP21]] | |
| ; CHECK: 32: | |
| ; CHECK-NEXT: [[XYZCOND:%.*]] = phi i1 [ false, [[WID:%.*]] ], [ true, [[MALLOC]] ] | |
| ; CHECK-NEXT: call void @llvm.amdgcn.s.barrier() | |
| ; CHECK-NEXT: [[TMP35:%.*]] = load ptr addrspace(1), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8 | |
| ; CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 12), align 4 | |
| ; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds i8, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 [[TMP24]] | |
| ; CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 24), align 4 | |
| ; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds i8, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 [[TMP26]] | |
| ; CHECK-NEXT: [[TMP28:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 36), align 4 | |
| ; CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds i8, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 [[TMP28]] | |
| ; CHECK-NEXT: [[TMP33:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 48), align 4 | |
| ; CHECK-NEXT: [[TMP34:%.*]] = getelementptr inbounds i8, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 [[TMP33]] | |
| ; CHECK-NEXT: call void @llvm.donothing() [ "ExplicitUse"(ptr addrspace(3) @llvm.amdgcn.k0.dynlds) ] | |
| ; CHECK-NEXT: [[TMP42:%.*]] = ptrtoint ptr addrspace(3) [[TMP25]] to i32 | |
| ; CHECK-NEXT: [[TMP43:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP35]], i32 [[TMP42]] | |
| ; CHECK-NEXT: store i8 7, ptr addrspace(1) [[TMP43]], align 4 | |
| ; CHECK-NEXT: [[TMP59:%.*]] = ptrtoint ptr addrspace(3) [[TMP27]] to i32 | |
| ; CHECK-NEXT: [[TMP60:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP35]], i32 [[TMP59]] | |
| ; CHECK-NEXT: store i32 8, ptr addrspace(1) [[TMP60]], align 8 | |
| ; CHECK-NEXT: [[TMP77:%.*]] = ptrtoint ptr addrspace(3) [[TMP29]] to i32 | |
| ; CHECK-NEXT: [[TMP78:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP35]], i32 [[TMP77]] | |
| ; CHECK-NEXT: store i8 7, ptr addrspace(1) [[TMP78]], align 4 | |
| ; CHECK-NEXT: [[TMP94:%.*]] = ptrtoint ptr addrspace(3) [[TMP34]] to i32 | |
| ; CHECK-NEXT: [[TMP95:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP35]], i32 [[TMP94]] | |
| ; CHECK-NEXT: store i8 8, ptr addrspace(1) [[TMP95]], align 8 | |
| ; CHECK-NEXT: br label [[CONDFREE1:%.*]] | |
| ; CHECK: CondFree: | |
| ; CHECK-NEXT: call void @llvm.amdgcn.s.barrier() | |
| ; CHECK-NEXT: br i1 [[XYZCOND]], label [[FREE:%.*]], label [[END:%.*]] | |
| ; CHECK: Free: | |
| ; CHECK-NEXT: [[TMP36:%.*]] = call ptr @llvm.returnaddress.p0(i32 0) | |
| ; CHECK-NEXT: [[TMP37:%.*]] = ptrtoint ptr [[TMP36]] to i64 | |
| ; CHECK-NEXT: [[TMP38:%.*]] = ptrtoint ptr addrspace(1) [[TMP35]] to i64 | |
| ; CHECK-NEXT: call void @__asan_free_impl(i64 [[TMP38]], i64 [[TMP37]]) | |
| ; CHECK-NEXT: br label [[END]] | |
| ; CHECK: End: | |
| ; CHECK-NEXT: ret void | |
| ; | |
| store i8 7, ptr addrspace(3) @lds_1, align 4 | |
| store i32 8, ptr addrspace(3) @lds_2, align 8 | |
| store i8 7, ptr addrspace(3) @lds_3, align 4 | |
| store i8 8, ptr addrspace(3) @lds_4, align 8 | |
| ret void | |
| } | |
| !llvm.module.flags = !{!0} | |
| !0 = !{i32 4, !"nosanitize_address", i32 1} | |
| ;. | |
| ; CHECK: attributes #[[ATTR0]] = { sanitize_address "amdgpu-lds-size"="8,8" } | |
| ; CHECK: attributes #[[ATTR1:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(none) } | |
| ; CHECK: attributes #[[ATTR2:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } | |
| ; CHECK: attributes #[[ATTR3:[0-9]+]] = { convergent nocallback nofree nounwind willreturn } | |
| ;. | |
| ; CHECK: [[META0]] = !{i32 0, i32 1} | |
| ; CHECK: [[META1]] = !{i32 8, i32 9} | |
| ; CHECK: [[META2:![0-9]+]] = !{i32 4, !"nosanitize_address", i32 1} | |
| ;. |