llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5

; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=SI %s
; RUN: llc -mtriple=amdgpu8.02 < %s | FileCheck -check-prefix=VI %s
; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck -check-prefix=GFX9 %s
; RUN: llc -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
; RUN: llc -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s

define <10 x float> @bitcast_v10i32_to_v10f32(<10 x i32> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v10i32_to_v10f32:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB0_2
; SI-NEXT:  ; %bb.1: ; %cmp.true
; SI-NEXT:    v_add_i32_e32 v9, vcc, 3, v9
; SI-NEXT:    v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT:    v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT:    v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT:    v_add_i32_e32 v5, vcc, 3, v5
; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v3
; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT:  .LBB0_2: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v10i32_to_v10f32:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB0_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    v_add_u32_e32 v9, vcc, 3, v9
; VI-NEXT:    v_add_u32_e32 v8, vcc, 3, v8
; VI-NEXT:    v_add_u32_e32 v7, vcc, 3, v7
; VI-NEXT:    v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT:    v_add_u32_e32 v5, vcc, 3, v5
; VI-NEXT:    v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT:    v_add_u32_e32 v3, vcc, 3, v3
; VI-NEXT:    v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT:    v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT:  .LBB0_2: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v10i32_to_v10f32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB0_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    v_add_u32_e32 v9, 3, v9
; GFX9-NEXT:    v_add_u32_e32 v8, 3, v8
; GFX9-NEXT:    v_add_u32_e32 v7, 3, v7
; GFX9-NEXT:    v_add_u32_e32 v6, 3, v6
; GFX9-NEXT:    v_add_u32_e32 v5, 3, v5
; GFX9-NEXT:    v_add_u32_e32 v4, 3, v4
; GFX9-NEXT:    v_add_u32_e32 v3, 3, v3
; GFX9-NEXT:    v_add_u32_e32 v2, 3, v2
; GFX9-NEXT:    v_add_u32_e32 v1, 3, v1
; GFX9-NEXT:    v_add_u32_e32 v0, 3, v0
; GFX9-NEXT:  .LBB0_2: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v10i32_to_v10f32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB0_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    v_add_nc_u32_e32 v9, 3, v9
; GFX11-NEXT:    v_add_nc_u32_e32 v8, 3, v8
; GFX11-NEXT:    v_add_nc_u32_e32 v7, 3, v7
; GFX11-NEXT:    v_add_nc_u32_e32 v6, 3, v6
; GFX11-NEXT:    v_add_nc_u32_e32 v5, 3, v5
; GFX11-NEXT:    v_add_nc_u32_e32 v4, 3, v4
; GFX11-NEXT:    v_add_nc_u32_e32 v3, 3, v3
; GFX11-NEXT:    v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT:    v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT:    v_add_nc_u32_e32 v0, 3, v0
; GFX11-NEXT:  .LBB0_2: ; %end
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <10 x i32> %a, splat (i32 3)
  %a2 = bitcast <10 x i32> %a1 to <10 x float>
  br label %end

cmp.false:
  %a3 = bitcast <10 x i32> %a to <10 x float>
  br label %end

end:
  %phi = phi <10 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <10 x float> %phi
}

define inreg <10 x float> @bitcast_v10i32_to_v10f32_scalar(<10 x i32> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v10i32_to_v10f32_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc1 .LBB1_2
; SI-NEXT:  ; %bb.1: ; %cmp.true
; SI-NEXT:    s_add_i32 s25, s25, 3
; SI-NEXT:    s_add_i32 s24, s24, 3
; SI-NEXT:    s_add_i32 s23, s23, 3
; SI-NEXT:    s_add_i32 s22, s22, 3
; SI-NEXT:    s_add_i32 s21, s21, 3
; SI-NEXT:    s_add_i32 s20, s20, 3
; SI-NEXT:    s_add_i32 s19, s19, 3
; SI-NEXT:    s_add_i32 s18, s18, 3
; SI-NEXT:    s_add_i32 s17, s17, 3
; SI-NEXT:    s_add_i32 s16, s16, 3
; SI-NEXT:  .LBB1_2: ; %end
; SI-NEXT:    v_mov_b32_e32 v0, s16
; SI-NEXT:    v_mov_b32_e32 v1, s17
; SI-NEXT:    v_mov_b32_e32 v2, s18
; SI-NEXT:    v_mov_b32_e32 v3, s19
; SI-NEXT:    v_mov_b32_e32 v4, s20
; SI-NEXT:    v_mov_b32_e32 v5, s21
; SI-NEXT:    v_mov_b32_e32 v6, s22
; SI-NEXT:    v_mov_b32_e32 v7, s23
; SI-NEXT:    v_mov_b32_e32 v8, s24
; SI-NEXT:    v_mov_b32_e32 v9, s25
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v10i32_to_v10f32_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc1 .LBB1_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    s_add_i32 s25, s25, 3
; VI-NEXT:    s_add_i32 s24, s24, 3
; VI-NEXT:    s_add_i32 s23, s23, 3
; VI-NEXT:    s_add_i32 s22, s22, 3
; VI-NEXT:    s_add_i32 s21, s21, 3
; VI-NEXT:    s_add_i32 s20, s20, 3
; VI-NEXT:    s_add_i32 s19, s19, 3
; VI-NEXT:    s_add_i32 s18, s18, 3
; VI-NEXT:    s_add_i32 s17, s17, 3
; VI-NEXT:    s_add_i32 s16, s16, 3
; VI-NEXT:  .LBB1_2: ; %end
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s17
; VI-NEXT:    v_mov_b32_e32 v2, s18
; VI-NEXT:    v_mov_b32_e32 v3, s19
; VI-NEXT:    v_mov_b32_e32 v4, s20
; VI-NEXT:    v_mov_b32_e32 v5, s21
; VI-NEXT:    v_mov_b32_e32 v6, s22
; VI-NEXT:    v_mov_b32_e32 v7, s23
; VI-NEXT:    v_mov_b32_e32 v8, s24
; VI-NEXT:    v_mov_b32_e32 v9, s25
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v10i32_to_v10f32_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc1 .LBB1_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    s_add_i32 s25, s25, 3
; GFX9-NEXT:    s_add_i32 s24, s24, 3
; GFX9-NEXT:    s_add_i32 s23, s23, 3
; GFX9-NEXT:    s_add_i32 s22, s22, 3
; GFX9-NEXT:    s_add_i32 s21, s21, 3
; GFX9-NEXT:    s_add_i32 s20, s20, 3
; GFX9-NEXT:    s_add_i32 s19, s19, 3
; GFX9-NEXT:    s_add_i32 s18, s18, 3
; GFX9-NEXT:    s_add_i32 s17, s17, 3
; GFX9-NEXT:    s_add_i32 s16, s16, 3
; GFX9-NEXT:  .LBB1_2: ; %end
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s17
; GFX9-NEXT:    v_mov_b32_e32 v2, s18
; GFX9-NEXT:    v_mov_b32_e32 v3, s19
; GFX9-NEXT:    v_mov_b32_e32 v4, s20
; GFX9-NEXT:    v_mov_b32_e32 v5, s21
; GFX9-NEXT:    v_mov_b32_e32 v6, s22
; GFX9-NEXT:    v_mov_b32_e32 v7, s23
; GFX9-NEXT:    v_mov_b32_e32 v8, s24
; GFX9-NEXT:    v_mov_b32_e32 v9, s25
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v10i32_to_v10f32_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc1 .LBB1_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    s_add_i32 s21, s21, 3
; GFX11-NEXT:    s_add_i32 s20, s20, 3
; GFX11-NEXT:    s_add_i32 s19, s19, 3
; GFX11-NEXT:    s_add_i32 s18, s18, 3
; GFX11-NEXT:    s_add_i32 s17, s17, 3
; GFX11-NEXT:    s_add_i32 s16, s16, 3
; GFX11-NEXT:    s_add_i32 s3, s3, 3
; GFX11-NEXT:    s_add_i32 s2, s2, 3
; GFX11-NEXT:    s_add_i32 s1, s1, 3
; GFX11-NEXT:    s_add_i32 s0, s0, 3
; GFX11-NEXT:  .LBB1_2: ; %end
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <10 x i32> %a, splat (i32 3)
  %a2 = bitcast <10 x i32> %a1 to <10 x float>
  br label %end

cmp.false:
  %a3 = bitcast <10 x i32> %a to <10 x float>
  br label %end

end:
  %phi = phi <10 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <10 x float> %phi
}

define <10 x i32> @bitcast_v10f32_to_v10i32(<10 x float> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v10f32_to_v10i32:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB2_2
; SI-NEXT:  ; %bb.1: ; %cmp.true
; SI-NEXT:    v_add_f32_e32 v9, 1.0, v9
; SI-NEXT:    v_add_f32_e32 v8, 1.0, v8
; SI-NEXT:    v_add_f32_e32 v7, 1.0, v7
; SI-NEXT:    v_add_f32_e32 v6, 1.0, v6
; SI-NEXT:    v_add_f32_e32 v5, 1.0, v5
; SI-NEXT:    v_add_f32_e32 v4, 1.0, v4
; SI-NEXT:    v_add_f32_e32 v3, 1.0, v3
; SI-NEXT:    v_add_f32_e32 v2, 1.0, v2
; SI-NEXT:    v_add_f32_e32 v1, 1.0, v1
; SI-NEXT:    v_add_f32_e32 v0, 1.0, v0
; SI-NEXT:  .LBB2_2: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v10f32_to_v10i32:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB2_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    v_add_f32_e32 v9, 1.0, v9
; VI-NEXT:    v_add_f32_e32 v8, 1.0, v8
; VI-NEXT:    v_add_f32_e32 v7, 1.0, v7
; VI-NEXT:    v_add_f32_e32 v6, 1.0, v6
; VI-NEXT:    v_add_f32_e32 v5, 1.0, v5
; VI-NEXT:    v_add_f32_e32 v4, 1.0, v4
; VI-NEXT:    v_add_f32_e32 v3, 1.0, v3
; VI-NEXT:    v_add_f32_e32 v2, 1.0, v2
; VI-NEXT:    v_add_f32_e32 v1, 1.0, v1
; VI-NEXT:    v_add_f32_e32 v0, 1.0, v0
; VI-NEXT:  .LBB2_2: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v10f32_to_v10i32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB2_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    v_add_f32_e32 v9, 1.0, v9
; GFX9-NEXT:    v_add_f32_e32 v8, 1.0, v8
; GFX9-NEXT:    v_add_f32_e32 v7, 1.0, v7
; GFX9-NEXT:    v_add_f32_e32 v6, 1.0, v6
; GFX9-NEXT:    v_add_f32_e32 v5, 1.0, v5
; GFX9-NEXT:    v_add_f32_e32 v4, 1.0, v4
; GFX9-NEXT:    v_add_f32_e32 v3, 1.0, v3
; GFX9-NEXT:    v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT:    v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT:    v_add_f32_e32 v0, 1.0, v0
; GFX9-NEXT:  .LBB2_2: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v10f32_to_v10i32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8
; GFX11-NEXT:    v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
; GFX11-NEXT:    v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT:    v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT:    v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
; GFX11-NEXT:  ; %bb.2: ; %end
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <10 x float> %a, splat (float 1.000000e+00)
  %a2 = bitcast <10 x float> %a1 to <10 x i32>
  br label %end

cmp.false:
  %a3 = bitcast <10 x float> %a to <10 x i32>
  br label %end

end:
  %phi = phi <10 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <10 x i32> %phi
}

define inreg <10 x i32> @bitcast_v10f32_to_v10i32_scalar(<10 x float> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v10f32_to_v10i32_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc0 .LBB3_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    v_mov_b32_e32 v0, s16
; SI-NEXT:    v_mov_b32_e32 v1, s17
; SI-NEXT:    v_mov_b32_e32 v2, s18
; SI-NEXT:    v_mov_b32_e32 v3, s19
; SI-NEXT:    v_mov_b32_e32 v4, s20
; SI-NEXT:    v_mov_b32_e32 v5, s21
; SI-NEXT:    v_mov_b32_e32 v6, s22
; SI-NEXT:    v_mov_b32_e32 v7, s23
; SI-NEXT:    v_mov_b32_e32 v8, s24
; SI-NEXT:    v_mov_b32_e32 v9, s25
; SI-NEXT:    s_setpc_b64 s[30:31]
; SI-NEXT:  .LBB3_2: ; %cmp.true
; SI-NEXT:    v_add_f32_e64 v9, s25, 1.0
; SI-NEXT:    v_add_f32_e64 v8, s24, 1.0
; SI-NEXT:    v_add_f32_e64 v7, s23, 1.0
; SI-NEXT:    v_add_f32_e64 v6, s22, 1.0
; SI-NEXT:    v_add_f32_e64 v5, s21, 1.0
; SI-NEXT:    v_add_f32_e64 v4, s20, 1.0
; SI-NEXT:    v_add_f32_e64 v3, s19, 1.0
; SI-NEXT:    v_add_f32_e64 v2, s18, 1.0
; SI-NEXT:    v_add_f32_e64 v1, s17, 1.0
; SI-NEXT:    v_add_f32_e64 v0, s16, 1.0
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v10f32_to_v10i32_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc0 .LBB3_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s17
; VI-NEXT:    v_mov_b32_e32 v2, s18
; VI-NEXT:    v_mov_b32_e32 v3, s19
; VI-NEXT:    v_mov_b32_e32 v4, s20
; VI-NEXT:    v_mov_b32_e32 v5, s21
; VI-NEXT:    v_mov_b32_e32 v6, s22
; VI-NEXT:    v_mov_b32_e32 v7, s23
; VI-NEXT:    v_mov_b32_e32 v8, s24
; VI-NEXT:    v_mov_b32_e32 v9, s25
; VI-NEXT:    s_setpc_b64 s[30:31]
; VI-NEXT:  .LBB3_2: ; %cmp.true
; VI-NEXT:    v_add_f32_e64 v9, s25, 1.0
; VI-NEXT:    v_add_f32_e64 v8, s24, 1.0
; VI-NEXT:    v_add_f32_e64 v7, s23, 1.0
; VI-NEXT:    v_add_f32_e64 v6, s22, 1.0
; VI-NEXT:    v_add_f32_e64 v5, s21, 1.0
; VI-NEXT:    v_add_f32_e64 v4, s20, 1.0
; VI-NEXT:    v_add_f32_e64 v3, s19, 1.0
; VI-NEXT:    v_add_f32_e64 v2, s18, 1.0
; VI-NEXT:    v_add_f32_e64 v1, s17, 1.0
; VI-NEXT:    v_add_f32_e64 v0, s16, 1.0
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v10f32_to_v10i32_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc0 .LBB3_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s17
; GFX9-NEXT:    v_mov_b32_e32 v2, s18
; GFX9-NEXT:    v_mov_b32_e32 v3, s19
; GFX9-NEXT:    v_mov_b32_e32 v4, s20
; GFX9-NEXT:    v_mov_b32_e32 v5, s21
; GFX9-NEXT:    v_mov_b32_e32 v6, s22
; GFX9-NEXT:    v_mov_b32_e32 v7, s23
; GFX9-NEXT:    v_mov_b32_e32 v8, s24
; GFX9-NEXT:    v_mov_b32_e32 v9, s25
; GFX9-NEXT:    s_setpc_b64 s[30:31]
; GFX9-NEXT:  .LBB3_2: ; %cmp.true
; GFX9-NEXT:    v_add_f32_e64 v9, s25, 1.0
; GFX9-NEXT:    v_add_f32_e64 v8, s24, 1.0
; GFX9-NEXT:    v_add_f32_e64 v7, s23, 1.0
; GFX9-NEXT:    v_add_f32_e64 v6, s22, 1.0
; GFX9-NEXT:    v_add_f32_e64 v5, s21, 1.0
; GFX9-NEXT:    v_add_f32_e64 v4, s20, 1.0
; GFX9-NEXT:    v_add_f32_e64 v3, s19, 1.0
; GFX9-NEXT:    v_add_f32_e64 v2, s18, 1.0
; GFX9-NEXT:    v_add_f32_e64 v1, s17, 1.0
; GFX9-NEXT:    v_add_f32_e64 v0, s16, 1.0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v10f32_to_v10i32_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s15, s3
; GFX11-NEXT:    s_mov_b32 s14, s2
; GFX11-NEXT:    s_mov_b32 s13, s1
; GFX11-NEXT:    s_mov_b32 s12, s0
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc0 .LBB3_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-NEXT:    v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
; GFX11-NEXT:    v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT:    s_setpc_b64 s[30:31]
; GFX11-NEXT:  .LBB3_2: ; %cmp.true
; GFX11-NEXT:    v_add_f32_e64 v9, s21, 1.0
; GFX11-NEXT:    v_add_f32_e64 v8, s20, 1.0
; GFX11-NEXT:    v_add_f32_e64 v7, s19, 1.0
; GFX11-NEXT:    v_add_f32_e64 v6, s18, 1.0
; GFX11-NEXT:    v_add_f32_e64 v5, s17, 1.0
; GFX11-NEXT:    v_add_f32_e64 v4, s16, 1.0
; GFX11-NEXT:    v_add_f32_e64 v3, s15, 1.0
; GFX11-NEXT:    v_add_f32_e64 v2, s14, 1.0
; GFX11-NEXT:    v_add_f32_e64 v1, s13, 1.0
; GFX11-NEXT:    v_add_f32_e64 v0, s12, 1.0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <10 x float> %a, splat (float 1.000000e+00)
  %a2 = bitcast <10 x float> %a1 to <10 x i32>
  br label %end

cmp.false:
  %a3 = bitcast <10 x float> %a to <10 x i32>
  br label %end

end:
  %phi = phi <10 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <10 x i32> %phi
}

define <20 x i16> @bitcast_v10i32_to_v20i16(<10 x i32> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v10i32_to_v20i16:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; SI-NEXT:    ; implicit-def: $vgpr16
; SI-NEXT:    ; implicit-def: $vgpr19
; SI-NEXT:    ; implicit-def: $vgpr14
; SI-NEXT:    ; implicit-def: $vgpr18
; SI-NEXT:    ; implicit-def: $vgpr12
; SI-NEXT:    ; implicit-def: $vgpr17
; SI-NEXT:    ; implicit-def: $vgpr11
; SI-NEXT:    ; implicit-def: $vgpr15
; SI-NEXT:    ; implicit-def: $vgpr10
; SI-NEXT:    ; implicit-def: $vgpr13
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB4_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    v_alignbit_b32 v10, v9, v8, 16
; SI-NEXT:    v_alignbit_b32 v11, v7, v6, 16
; SI-NEXT:    v_alignbit_b32 v12, v5, v4, 16
; SI-NEXT:    v_alignbit_b32 v14, v3, v2, 16
; SI-NEXT:    v_alignbit_b32 v16, v1, v0, 16
; SI-NEXT:    v_lshrrev_b32_e32 v13, 16, v9
; SI-NEXT:    v_lshrrev_b32_e32 v15, 16, v7
; SI-NEXT:    v_lshrrev_b32_e32 v17, 16, v5
; SI-NEXT:    v_lshrrev_b32_e32 v18, 16, v3
; SI-NEXT:    v_lshrrev_b32_e32 v19, 16, v1
; SI-NEXT:  .LBB4_2: ; %Flow
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB4_4
; SI-NEXT:  ; %bb.3: ; %cmp.true
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v3
; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT:    v_add_i32_e32 v5, vcc, 3, v5
; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT:    v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT:    v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT:    v_add_i32_e32 v9, vcc, 3, v9
; SI-NEXT:    v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT:    v_alignbit_b32 v10, v9, v8, 16
; SI-NEXT:    v_alignbit_b32 v11, v7, v6, 16
; SI-NEXT:    v_alignbit_b32 v12, v5, v4, 16
; SI-NEXT:    v_alignbit_b32 v14, v3, v2, 16
; SI-NEXT:    v_alignbit_b32 v16, v1, v0, 16
; SI-NEXT:    v_lshrrev_b32_e32 v13, 16, v9
; SI-NEXT:    v_lshrrev_b32_e32 v15, 16, v7
; SI-NEXT:    v_lshrrev_b32_e32 v17, 16, v5
; SI-NEXT:    v_lshrrev_b32_e32 v18, 16, v3
; SI-NEXT:    v_lshrrev_b32_e32 v19, 16, v1
; SI-NEXT:  .LBB4_4: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT:    v_or_b32_e32 v0, v0, v16
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_lshlrev_b32_e32 v16, 16, v19
; SI-NEXT:    v_or_b32_e32 v2, v2, v14
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT:    v_lshlrev_b32_e32 v14, 16, v18
; SI-NEXT:    v_or_b32_e32 v4, v4, v12
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT:    v_lshlrev_b32_e32 v12, 16, v17
; SI-NEXT:    v_or_b32_e32 v6, v6, v11
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT:    v_lshlrev_b32_e32 v11, 16, v15
; SI-NEXT:    v_or_b32_e32 v8, v8, v10
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v13
; SI-NEXT:    v_or_b32_e32 v1, v1, v16
; SI-NEXT:    v_or_b32_e32 v3, v3, v14
; SI-NEXT:    v_or_b32_e32 v5, v5, v12
; SI-NEXT:    v_or_b32_e32 v7, v7, v11
; SI-NEXT:    v_or_b32_e32 v9, v9, v10
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v10i32_to_v20i16:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB4_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    v_add_u32_e32 v9, vcc, 3, v9
; VI-NEXT:    v_add_u32_e32 v8, vcc, 3, v8
; VI-NEXT:    v_add_u32_e32 v7, vcc, 3, v7
; VI-NEXT:    v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT:    v_add_u32_e32 v5, vcc, 3, v5
; VI-NEXT:    v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT:    v_add_u32_e32 v3, vcc, 3, v3
; VI-NEXT:    v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT:    v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT:  .LBB4_2: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v10i32_to_v20i16:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB4_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    v_add_u32_e32 v9, 3, v9
; GFX9-NEXT:    v_add_u32_e32 v8, 3, v8
; GFX9-NEXT:    v_add_u32_e32 v7, 3, v7
; GFX9-NEXT:    v_add_u32_e32 v6, 3, v6
; GFX9-NEXT:    v_add_u32_e32 v5, 3, v5
; GFX9-NEXT:    v_add_u32_e32 v4, 3, v4
; GFX9-NEXT:    v_add_u32_e32 v3, 3, v3
; GFX9-NEXT:    v_add_u32_e32 v2, 3, v2
; GFX9-NEXT:    v_add_u32_e32 v1, 3, v1
; GFX9-NEXT:    v_add_u32_e32 v0, 3, v0
; GFX9-NEXT:  .LBB4_2: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v10i32_to_v20i16:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB4_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    v_add_nc_u32_e32 v9, 3, v9
; GFX11-NEXT:    v_add_nc_u32_e32 v8, 3, v8
; GFX11-NEXT:    v_add_nc_u32_e32 v7, 3, v7
; GFX11-NEXT:    v_add_nc_u32_e32 v6, 3, v6
; GFX11-NEXT:    v_add_nc_u32_e32 v5, 3, v5
; GFX11-NEXT:    v_add_nc_u32_e32 v4, 3, v4
; GFX11-NEXT:    v_add_nc_u32_e32 v3, 3, v3
; GFX11-NEXT:    v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT:    v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT:    v_add_nc_u32_e32 v0, 3, v0
; GFX11-NEXT:  .LBB4_2: ; %end
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <10 x i32> %a, splat (i32 3)
  %a2 = bitcast <10 x i32> %a1 to <20 x i16>
  br label %end

cmp.false:
  %a3 = bitcast <10 x i32> %a to <20 x i16>
  br label %end

end:
  %phi = phi <20 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <20 x i16> %phi
}

define inreg <20 x i16> @bitcast_v10i32_to_v20i16_scalar(<10 x i32> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v10i32_to_v20i16_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc0 .LBB5_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    s_lshr_b32 s14, s25, 16
; SI-NEXT:    s_lshr_b32 s15, s23, 16
; SI-NEXT:    s_lshr_b32 s26, s21, 16
; SI-NEXT:    s_lshr_b32 s27, s19, 16
; SI-NEXT:    s_lshr_b32 s28, s17, 16
; SI-NEXT:    s_lshr_b64 s[4:5], s[24:25], 16
; SI-NEXT:    s_lshr_b64 s[6:7], s[22:23], 16
; SI-NEXT:    s_lshr_b64 s[8:9], s[20:21], 16
; SI-NEXT:    s_lshr_b64 s[10:11], s[18:19], 16
; SI-NEXT:    s_lshr_b64 s[12:13], s[16:17], 16
; SI-NEXT:    s_branch .LBB5_3
; SI-NEXT:  .LBB5_2: ; %cmp.true
; SI-NEXT:    s_add_i32 s17, s17, 3
; SI-NEXT:    s_add_i32 s16, s16, 3
; SI-NEXT:    s_add_i32 s19, s19, 3
; SI-NEXT:    s_add_i32 s18, s18, 3
; SI-NEXT:    s_add_i32 s21, s21, 3
; SI-NEXT:    s_add_i32 s20, s20, 3
; SI-NEXT:    s_add_i32 s23, s23, 3
; SI-NEXT:    s_add_i32 s22, s22, 3
; SI-NEXT:    s_add_i32 s25, s25, 3
; SI-NEXT:    s_add_i32 s24, s24, 3
; SI-NEXT:    s_lshr_b64 s[4:5], s[24:25], 16
; SI-NEXT:    s_lshr_b64 s[6:7], s[22:23], 16
; SI-NEXT:    s_lshr_b64 s[8:9], s[20:21], 16
; SI-NEXT:    s_lshr_b64 s[10:11], s[18:19], 16
; SI-NEXT:    s_lshr_b64 s[12:13], s[16:17], 16
; SI-NEXT:    s_lshr_b32 s14, s25, 16
; SI-NEXT:    s_lshr_b32 s15, s23, 16
; SI-NEXT:    s_lshr_b32 s26, s21, 16
; SI-NEXT:    s_lshr_b32 s27, s19, 16
; SI-NEXT:    s_lshr_b32 s28, s17, 16
; SI-NEXT:  .LBB5_3: ; %end
; SI-NEXT:    s_and_b32 s5, s16, 0xffff
; SI-NEXT:    s_lshl_b32 s7, s12, 16
; SI-NEXT:    s_or_b32 s5, s5, s7
; SI-NEXT:    s_and_b32 s7, s17, 0xffff
; SI-NEXT:    s_lshl_b32 s9, s28, 16
; SI-NEXT:    s_or_b32 s7, s7, s9
; SI-NEXT:    s_and_b32 s9, s18, 0xffff
; SI-NEXT:    s_lshl_b32 s10, s10, 16
; SI-NEXT:    s_or_b32 s9, s9, s10
; SI-NEXT:    s_and_b32 s10, s19, 0xffff
; SI-NEXT:    s_lshl_b32 s11, s27, 16
; SI-NEXT:    s_or_b32 s10, s10, s11
; SI-NEXT:    s_and_b32 s11, s20, 0xffff
; SI-NEXT:    s_lshl_b32 s8, s8, 16
; SI-NEXT:    s_or_b32 s8, s11, s8
; SI-NEXT:    s_and_b32 s11, s21, 0xffff
; SI-NEXT:    s_lshl_b32 s12, s26, 16
; SI-NEXT:    s_or_b32 s11, s11, s12
; SI-NEXT:    s_and_b32 s12, s22, 0xffff
; SI-NEXT:    s_lshl_b32 s6, s6, 16
; SI-NEXT:    s_or_b32 s6, s12, s6
; SI-NEXT:    s_and_b32 s12, s23, 0xffff
; SI-NEXT:    s_lshl_b32 s13, s15, 16
; SI-NEXT:    s_or_b32 s12, s12, s13
; SI-NEXT:    s_and_b32 s13, s24, 0xffff
; SI-NEXT:    s_lshl_b32 s4, s4, 16
; SI-NEXT:    s_or_b32 s4, s13, s4
; SI-NEXT:    s_and_b32 s13, s25, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s14, 16
; SI-NEXT:    s_or_b32 s13, s13, s14
; SI-NEXT:    v_mov_b32_e32 v0, s5
; SI-NEXT:    v_mov_b32_e32 v1, s7
; SI-NEXT:    v_mov_b32_e32 v2, s9
; SI-NEXT:    v_mov_b32_e32 v3, s10
; SI-NEXT:    v_mov_b32_e32 v4, s8
; SI-NEXT:    v_mov_b32_e32 v5, s11
; SI-NEXT:    v_mov_b32_e32 v6, s6
; SI-NEXT:    v_mov_b32_e32 v7, s12
; SI-NEXT:    v_mov_b32_e32 v8, s4
; SI-NEXT:    v_mov_b32_e32 v9, s13
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v10i32_to_v20i16_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc1 .LBB5_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    s_add_i32 s25, s25, 3
; VI-NEXT:    s_add_i32 s24, s24, 3
; VI-NEXT:    s_add_i32 s23, s23, 3
; VI-NEXT:    s_add_i32 s22, s22, 3
; VI-NEXT:    s_add_i32 s21, s21, 3
; VI-NEXT:    s_add_i32 s20, s20, 3
; VI-NEXT:    s_add_i32 s19, s19, 3
; VI-NEXT:    s_add_i32 s18, s18, 3
; VI-NEXT:    s_add_i32 s17, s17, 3
; VI-NEXT:    s_add_i32 s16, s16, 3
; VI-NEXT:  .LBB5_2: ; %end
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s17
; VI-NEXT:    v_mov_b32_e32 v2, s18
; VI-NEXT:    v_mov_b32_e32 v3, s19
; VI-NEXT:    v_mov_b32_e32 v4, s20
; VI-NEXT:    v_mov_b32_e32 v5, s21
; VI-NEXT:    v_mov_b32_e32 v6, s22
; VI-NEXT:    v_mov_b32_e32 v7, s23
; VI-NEXT:    v_mov_b32_e32 v8, s24
; VI-NEXT:    v_mov_b32_e32 v9, s25
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v10i32_to_v20i16_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc1 .LBB5_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    s_add_i32 s25, s25, 3
; GFX9-NEXT:    s_add_i32 s24, s24, 3
; GFX9-NEXT:    s_add_i32 s23, s23, 3
; GFX9-NEXT:    s_add_i32 s22, s22, 3
; GFX9-NEXT:    s_add_i32 s21, s21, 3
; GFX9-NEXT:    s_add_i32 s20, s20, 3
; GFX9-NEXT:    s_add_i32 s19, s19, 3
; GFX9-NEXT:    s_add_i32 s18, s18, 3
; GFX9-NEXT:    s_add_i32 s17, s17, 3
; GFX9-NEXT:    s_add_i32 s16, s16, 3
; GFX9-NEXT:  .LBB5_2: ; %end
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s17
; GFX9-NEXT:    v_mov_b32_e32 v2, s18
; GFX9-NEXT:    v_mov_b32_e32 v3, s19
; GFX9-NEXT:    v_mov_b32_e32 v4, s20
; GFX9-NEXT:    v_mov_b32_e32 v5, s21
; GFX9-NEXT:    v_mov_b32_e32 v6, s22
; GFX9-NEXT:    v_mov_b32_e32 v7, s23
; GFX9-NEXT:    v_mov_b32_e32 v8, s24
; GFX9-NEXT:    v_mov_b32_e32 v9, s25
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v10i32_to_v20i16_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc1 .LBB5_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    s_add_i32 s21, s21, 3
; GFX11-NEXT:    s_add_i32 s20, s20, 3
; GFX11-NEXT:    s_add_i32 s19, s19, 3
; GFX11-NEXT:    s_add_i32 s18, s18, 3
; GFX11-NEXT:    s_add_i32 s17, s17, 3
; GFX11-NEXT:    s_add_i32 s16, s16, 3
; GFX11-NEXT:    s_add_i32 s3, s3, 3
; GFX11-NEXT:    s_add_i32 s2, s2, 3
; GFX11-NEXT:    s_add_i32 s1, s1, 3
; GFX11-NEXT:    s_add_i32 s0, s0, 3
; GFX11-NEXT:  .LBB5_2: ; %end
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <10 x i32> %a, splat (i32 3)
  %a2 = bitcast <10 x i32> %a1 to <20 x i16>
  br label %end

cmp.false:
  %a3 = bitcast <10 x i32> %a to <20 x i16>
  br label %end

end:
  %phi = phi <20 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <20 x i16> %phi
}

define <10 x i32> @bitcast_v20i16_to_v10i32(<20 x i16> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v20i16_to_v10i32:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_mov_b32_e32 v20, v9
; SI-NEXT:    v_mov_b32_e32 v11, v8
; SI-NEXT:    v_mov_b32_e32 v12, v7
; SI-NEXT:    v_mov_b32_e32 v13, v6
; SI-NEXT:    v_mov_b32_e32 v14, v5
; SI-NEXT:    v_mov_b32_e32 v15, v4
; SI-NEXT:    v_mov_b32_e32 v16, v3
; SI-NEXT:    v_mov_b32_e32 v17, v2
; SI-NEXT:    v_mov_b32_e32 v18, v1
; SI-NEXT:    v_mov_b32_e32 v19, v0
; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v20
; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v11
; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v12
; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v13
; SI-NEXT:    v_lshrrev_b32_e32 v4, 16, v14
; SI-NEXT:    v_lshrrev_b32_e32 v5, 16, v15
; SI-NEXT:    v_lshrrev_b32_e32 v6, 16, v16
; SI-NEXT:    v_lshrrev_b32_e32 v7, 16, v17
; SI-NEXT:    v_lshrrev_b32_e32 v8, 16, v18
; SI-NEXT:    v_lshrrev_b32_e32 v9, 16, v19
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; SI-NEXT:    v_lshlrev_b32_e32 v29, 16, v9
; SI-NEXT:    v_lshlrev_b32_e32 v28, 16, v8
; SI-NEXT:    v_lshlrev_b32_e32 v27, 16, v7
; SI-NEXT:    v_lshlrev_b32_e32 v26, 16, v6
; SI-NEXT:    v_lshlrev_b32_e32 v25, 16, v5
; SI-NEXT:    v_lshlrev_b32_e32 v24, 16, v4
; SI-NEXT:    v_lshlrev_b32_e32 v23, 16, v3
; SI-NEXT:    v_lshlrev_b32_e32 v22, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v21, 16, v1
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v0
; SI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_cbranch_execnz .LBB6_3
; SI-NEXT:  ; %bb.1: ; %Flow
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execnz .LBB6_4
; SI-NEXT:  .LBB6_2: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    s_setpc_b64 s[30:31]
; SI-NEXT:  .LBB6_3: ; %cmp.false
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v19
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v18
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v17
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v16
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v15
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v14
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v13
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v12
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v11
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v20
; SI-NEXT:    v_or_b32_e32 v0, v0, v29
; SI-NEXT:    v_or_b32_e32 v1, v1, v28
; SI-NEXT:    v_or_b32_e32 v2, v2, v27
; SI-NEXT:    v_or_b32_e32 v3, v3, v26
; SI-NEXT:    v_or_b32_e32 v4, v4, v25
; SI-NEXT:    v_or_b32_e32 v5, v5, v24
; SI-NEXT:    v_or_b32_e32 v6, v6, v23
; SI-NEXT:    v_or_b32_e32 v7, v7, v22
; SI-NEXT:    v_or_b32_e32 v8, v8, v21
; SI-NEXT:    v_or_b32_e32 v9, v9, v10
; SI-NEXT:    ; implicit-def: $vgpr19
; SI-NEXT:    ; implicit-def: $vgpr18
; SI-NEXT:    ; implicit-def: $vgpr17
; SI-NEXT:    ; implicit-def: $vgpr16
; SI-NEXT:    ; implicit-def: $vgpr15
; SI-NEXT:    ; implicit-def: $vgpr14
; SI-NEXT:    ; implicit-def: $vgpr13
; SI-NEXT:    ; implicit-def: $vgpr12
; SI-NEXT:    ; implicit-def: $vgpr11
; SI-NEXT:    ; implicit-def: $vgpr20
; SI-NEXT:    ; implicit-def: $vgpr29
; SI-NEXT:    ; implicit-def: $vgpr28
; SI-NEXT:    ; implicit-def: $vgpr27
; SI-NEXT:    ; implicit-def: $vgpr26
; SI-NEXT:    ; implicit-def: $vgpr25
; SI-NEXT:    ; implicit-def: $vgpr24
; SI-NEXT:    ; implicit-def: $vgpr23
; SI-NEXT:    ; implicit-def: $vgpr22
; SI-NEXT:    ; implicit-def: $vgpr21
; SI-NEXT:    ; implicit-def: $vgpr10
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB6_2
; SI-NEXT:  .LBB6_4: ; %cmp.true
; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v19
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v18
; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v17
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v16
; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v15
; SI-NEXT:    v_add_i32_e32 v5, vcc, 3, v14
; SI-NEXT:    v_add_i32_e32 v6, vcc, 3, v13
; SI-NEXT:    v_add_i32_e32 v7, vcc, 3, v12
; SI-NEXT:    v_add_i32_e32 v8, vcc, 3, v11
; SI-NEXT:    v_add_i32_e32 v9, vcc, 3, v20
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT:    v_or_b32_e32 v0, v29, v0
; SI-NEXT:    v_or_b32_e32 v1, v28, v1
; SI-NEXT:    v_or_b32_e32 v2, v27, v2
; SI-NEXT:    v_or_b32_e32 v3, v26, v3
; SI-NEXT:    v_or_b32_e32 v4, v25, v4
; SI-NEXT:    v_or_b32_e32 v5, v24, v5
; SI-NEXT:    v_or_b32_e32 v6, v23, v6
; SI-NEXT:    v_or_b32_e32 v7, v22, v7
; SI-NEXT:    v_or_b32_e32 v8, v21, v8
; SI-NEXT:    v_or_b32_e32 v9, v10, v9
; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT:    v_add_i32_e32 v1, vcc, 0x30000, v1
; SI-NEXT:    v_add_i32_e32 v2, vcc, 0x30000, v2
; SI-NEXT:    v_add_i32_e32 v3, vcc, 0x30000, v3
; SI-NEXT:    v_add_i32_e32 v4, vcc, 0x30000, v4
; SI-NEXT:    v_add_i32_e32 v5, vcc, 0x30000, v5
; SI-NEXT:    v_add_i32_e32 v6, vcc, 0x30000, v6
; SI-NEXT:    v_add_i32_e32 v7, vcc, 0x30000, v7
; SI-NEXT:    v_add_i32_e32 v8, vcc, 0x30000, v8
; SI-NEXT:    v_add_i32_e32 v9, vcc, 0x30000, v9
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v20i16_to_v10i32:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB6_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    v_mov_b32_e32 v11, 3
; VI-NEXT:    v_add_u16_e32 v10, 3, v9
; VI-NEXT:    v_add_u16_sdwa v9, v9, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v9, v10, v9
; VI-NEXT:    v_add_u16_e32 v10, 3, v8
; VI-NEXT:    v_add_u16_sdwa v8, v8, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v8, v10, v8
; VI-NEXT:    v_add_u16_e32 v10, 3, v7
; VI-NEXT:    v_add_u16_sdwa v7, v7, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v7, v10, v7
; VI-NEXT:    v_add_u16_e32 v10, 3, v6
; VI-NEXT:    v_add_u16_sdwa v6, v6, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v6, v10, v6
; VI-NEXT:    v_add_u16_e32 v10, 3, v5
; VI-NEXT:    v_add_u16_sdwa v5, v5, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v5, v10, v5
; VI-NEXT:    v_add_u16_e32 v10, 3, v4
; VI-NEXT:    v_add_u16_sdwa v4, v4, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v4, v10, v4
; VI-NEXT:    v_add_u16_e32 v10, 3, v3
; VI-NEXT:    v_add_u16_sdwa v3, v3, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v3, v10, v3
; VI-NEXT:    v_add_u16_e32 v10, 3, v2
; VI-NEXT:    v_add_u16_sdwa v2, v2, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v2, v10, v2
; VI-NEXT:    v_add_u16_e32 v10, 3, v1
; VI-NEXT:    v_add_u16_sdwa v1, v1, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v1, v10, v1
; VI-NEXT:    v_add_u16_e32 v10, 3, v0
; VI-NEXT:    v_add_u16_sdwa v0, v0, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v0, v10, v0
; VI-NEXT:  .LBB6_2: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v20i16_to_v10i32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB6_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX9-NEXT:  .LBB6_2: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v20i16_to_v10i32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB6_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-NEXT:  .LBB6_2: ; %end
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <20 x i16> %a, splat (i16 3)
  %a2 = bitcast <20 x i16> %a1 to <10 x i32>
  br label %end

cmp.false:
  %a3 = bitcast <20 x i16> %a to <10 x i32>
  br label %end

end:
  %phi = phi <10 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <10 x i32> %phi
}

define inreg <10 x i32> @bitcast_v20i16_to_v10i32_scalar(<20 x i16> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v20i16_to_v10i32_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_lshr_b32 s11, s25, 16
; SI-NEXT:    s_lshr_b32 s13, s24, 16
; SI-NEXT:    s_lshr_b32 s12, s23, 16
; SI-NEXT:    s_lshr_b32 s10, s22, 16
; SI-NEXT:    s_lshr_b32 s9, s21, 16
; SI-NEXT:    s_lshr_b32 s8, s20, 16
; SI-NEXT:    s_lshr_b32 s7, s19, 16
; SI-NEXT:    s_lshr_b32 s6, s18, 16
; SI-NEXT:    s_lshr_b32 s5, s17, 16
; SI-NEXT:    s_lshr_b32 s4, s16, 16
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc0 .LBB7_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    s_and_b32 s14, s16, 0xffff
; SI-NEXT:    s_lshl_b32 s4, s4, 16
; SI-NEXT:    s_or_b32 s4, s14, s4
; SI-NEXT:    s_and_b32 s14, s17, 0xffff
; SI-NEXT:    s_lshl_b32 s5, s5, 16
; SI-NEXT:    s_or_b32 s5, s14, s5
; SI-NEXT:    s_and_b32 s14, s18, 0xffff
; SI-NEXT:    s_lshl_b32 s6, s6, 16
; SI-NEXT:    s_or_b32 s6, s14, s6
; SI-NEXT:    s_and_b32 s14, s19, 0xffff
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_or_b32 s7, s14, s7
; SI-NEXT:    s_and_b32 s14, s20, 0xffff
; SI-NEXT:    s_lshl_b32 s8, s8, 16
; SI-NEXT:    s_or_b32 s8, s14, s8
; SI-NEXT:    s_and_b32 s14, s21, 0xffff
; SI-NEXT:    s_lshl_b32 s9, s9, 16
; SI-NEXT:    s_or_b32 s9, s14, s9
; SI-NEXT:    s_and_b32 s14, s22, 0xffff
; SI-NEXT:    s_lshl_b32 s10, s10, 16
; SI-NEXT:    s_or_b32 s10, s14, s10
; SI-NEXT:    s_and_b32 s14, s23, 0xffff
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_or_b32 s12, s14, s12
; SI-NEXT:    s_and_b32 s14, s24, 0xffff
; SI-NEXT:    s_lshl_b32 s13, s13, 16
; SI-NEXT:    s_or_b32 s13, s14, s13
; SI-NEXT:    s_and_b32 s14, s25, 0xffff
; SI-NEXT:    s_lshl_b32 s11, s11, 16
; SI-NEXT:    s_or_b32 s11, s14, s11
; SI-NEXT:    s_branch .LBB7_3
; SI-NEXT:  .LBB7_2: ; %cmp.true
; SI-NEXT:    s_add_i32 s16, s16, 3
; SI-NEXT:    s_and_b32 s14, s16, 0xffff
; SI-NEXT:    s_lshl_b32 s4, s4, 16
; SI-NEXT:    s_add_i32 s17, s17, 3
; SI-NEXT:    s_or_b32 s4, s4, s14
; SI-NEXT:    s_and_b32 s14, s17, 0xffff
; SI-NEXT:    s_lshl_b32 s5, s5, 16
; SI-NEXT:    s_add_i32 s18, s18, 3
; SI-NEXT:    s_or_b32 s5, s5, s14
; SI-NEXT:    s_and_b32 s14, s18, 0xffff
; SI-NEXT:    s_lshl_b32 s6, s6, 16
; SI-NEXT:    s_add_i32 s19, s19, 3
; SI-NEXT:    s_or_b32 s6, s6, s14
; SI-NEXT:    s_and_b32 s14, s19, 0xffff
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_add_i32 s20, s20, 3
; SI-NEXT:    s_or_b32 s7, s7, s14
; SI-NEXT:    s_and_b32 s14, s20, 0xffff
; SI-NEXT:    s_lshl_b32 s8, s8, 16
; SI-NEXT:    s_add_i32 s21, s21, 3
; SI-NEXT:    s_or_b32 s8, s8, s14
; SI-NEXT:    s_and_b32 s14, s21, 0xffff
; SI-NEXT:    s_lshl_b32 s9, s9, 16
; SI-NEXT:    s_add_i32 s22, s22, 3
; SI-NEXT:    s_or_b32 s9, s9, s14
; SI-NEXT:    s_and_b32 s14, s22, 0xffff
; SI-NEXT:    s_lshl_b32 s10, s10, 16
; SI-NEXT:    s_add_i32 s23, s23, 3
; SI-NEXT:    s_or_b32 s10, s10, s14
; SI-NEXT:    s_and_b32 s14, s23, 0xffff
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_add_i32 s24, s24, 3
; SI-NEXT:    s_or_b32 s12, s12, s14
; SI-NEXT:    s_and_b32 s14, s24, 0xffff
; SI-NEXT:    s_lshl_b32 s13, s13, 16
; SI-NEXT:    s_add_i32 s25, s25, 3
; SI-NEXT:    s_or_b32 s13, s13, s14
; SI-NEXT:    s_and_b32 s14, s25, 0xffff
; SI-NEXT:    s_lshl_b32 s11, s11, 16
; SI-NEXT:    s_or_b32 s11, s11, s14
; SI-NEXT:    s_add_i32 s4, s4, 0x30000
; SI-NEXT:    s_add_i32 s5, s5, 0x30000
; SI-NEXT:    s_add_i32 s6, s6, 0x30000
; SI-NEXT:    s_add_i32 s7, s7, 0x30000
; SI-NEXT:    s_add_i32 s8, s8, 0x30000
; SI-NEXT:    s_add_i32 s9, s9, 0x30000
; SI-NEXT:    s_add_i32 s10, s10, 0x30000
; SI-NEXT:    s_add_i32 s12, s12, 0x30000
; SI-NEXT:    s_add_i32 s13, s13, 0x30000
; SI-NEXT:    s_add_i32 s11, s11, 0x30000
; SI-NEXT:  .LBB7_3: ; %end
; SI-NEXT:    v_mov_b32_e32 v0, s4
; SI-NEXT:    v_mov_b32_e32 v1, s5
; SI-NEXT:    v_mov_b32_e32 v2, s6
; SI-NEXT:    v_mov_b32_e32 v3, s7
; SI-NEXT:    v_mov_b32_e32 v4, s8
; SI-NEXT:    v_mov_b32_e32 v5, s9
; SI-NEXT:    v_mov_b32_e32 v6, s10
; SI-NEXT:    v_mov_b32_e32 v7, s12
; SI-NEXT:    v_mov_b32_e32 v8, s13
; SI-NEXT:    v_mov_b32_e32 v9, s11
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v20i16_to_v10i32_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc1 .LBB7_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    s_add_i32 s5, s25, 3
; VI-NEXT:    s_and_b32 s4, s25, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s24, 3
; VI-NEXT:    s_add_i32 s25, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s24, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s23, 3
; VI-NEXT:    s_add_i32 s24, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s23, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s22, 3
; VI-NEXT:    s_add_i32 s23, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s22, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s21, 3
; VI-NEXT:    s_add_i32 s22, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s21, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s20, 3
; VI-NEXT:    s_add_i32 s21, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s20, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s19, 3
; VI-NEXT:    s_add_i32 s20, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s19, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s18, 3
; VI-NEXT:    s_add_i32 s19, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s18, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s17, 3
; VI-NEXT:    s_add_i32 s18, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s17, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s16, 3
; VI-NEXT:    s_add_i32 s17, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s16, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s16, s4, 0x30000
; VI-NEXT:  .LBB7_2: ; %end
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s17
; VI-NEXT:    v_mov_b32_e32 v2, s18
; VI-NEXT:    v_mov_b32_e32 v3, s19
; VI-NEXT:    v_mov_b32_e32 v4, s20
; VI-NEXT:    v_mov_b32_e32 v5, s21
; VI-NEXT:    v_mov_b32_e32 v6, s22
; VI-NEXT:    v_mov_b32_e32 v7, s23
; VI-NEXT:    v_mov_b32_e32 v8, s24
; VI-NEXT:    v_mov_b32_e32 v9, s25
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v20i16_to_v10i32_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc0 .LBB7_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s17
; GFX9-NEXT:    v_mov_b32_e32 v2, s18
; GFX9-NEXT:    v_mov_b32_e32 v3, s19
; GFX9-NEXT:    v_mov_b32_e32 v4, s20
; GFX9-NEXT:    v_mov_b32_e32 v5, s21
; GFX9-NEXT:    v_mov_b32_e32 v6, s22
; GFX9-NEXT:    v_mov_b32_e32 v7, s23
; GFX9-NEXT:    v_mov_b32_e32 v8, s24
; GFX9-NEXT:    v_mov_b32_e32 v9, s25
; GFX9-NEXT:    s_setpc_b64 s[30:31]
; GFX9-NEXT:  .LBB7_2: ; %cmp.true
; GFX9-NEXT:    v_pk_add_u16 v9, s25, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v8, s24, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v7, s23, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v6, s22, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v5, s21, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v4, s20, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v3, s19, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v20i16_to_v10i32_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s15, s3
; GFX11-NEXT:    s_mov_b32 s14, s2
; GFX11-NEXT:    s_mov_b32 s13, s1
; GFX11-NEXT:    s_mov_b32 s12, s0
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc0 .LBB7_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-NEXT:    v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
; GFX11-NEXT:    v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT:    s_setpc_b64 s[30:31]
; GFX11-NEXT:  .LBB7_2: ; %cmp.true
; GFX11-NEXT:    v_pk_add_u16 v9, s21, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v8, s20, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v7, s19, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v6, s18, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v5, s17, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v4, s16, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v3, s15, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v2, s14, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v1, s13, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v0, s12, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <20 x i16> %a, splat (i16 3)
  %a2 = bitcast <20 x i16> %a1 to <10 x i32>
  br label %end

cmp.false:
  %a3 = bitcast <20 x i16> %a to <10 x i32>
  br label %end

end:
  %phi = phi <10 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <10 x i32> %phi
}

define <20 x half> @bitcast_v10i32_to_v20f16(<10 x i32> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v10i32_to_v20f16:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; SI-NEXT:    ; implicit-def: $vgpr16
; SI-NEXT:    ; implicit-def: $vgpr19
; SI-NEXT:    ; implicit-def: $vgpr14
; SI-NEXT:    ; implicit-def: $vgpr18
; SI-NEXT:    ; implicit-def: $vgpr12
; SI-NEXT:    ; implicit-def: $vgpr17
; SI-NEXT:    ; implicit-def: $vgpr11
; SI-NEXT:    ; implicit-def: $vgpr15
; SI-NEXT:    ; implicit-def: $vgpr10
; SI-NEXT:    ; implicit-def: $vgpr13
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB8_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    v_alignbit_b32 v10, v9, v8, 16
; SI-NEXT:    v_alignbit_b32 v11, v7, v6, 16
; SI-NEXT:    v_alignbit_b32 v12, v5, v4, 16
; SI-NEXT:    v_alignbit_b32 v14, v3, v2, 16
; SI-NEXT:    v_alignbit_b32 v16, v1, v0, 16
; SI-NEXT:    v_lshrrev_b32_e32 v13, 16, v9
; SI-NEXT:    v_lshrrev_b32_e32 v15, 16, v7
; SI-NEXT:    v_lshrrev_b32_e32 v17, 16, v5
; SI-NEXT:    v_lshrrev_b32_e32 v18, 16, v3
; SI-NEXT:    v_lshrrev_b32_e32 v19, 16, v1
; SI-NEXT:  .LBB8_2: ; %Flow
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB8_4
; SI-NEXT:  ; %bb.3: ; %cmp.true
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v3
; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT:    v_add_i32_e32 v5, vcc, 3, v5
; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT:    v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT:    v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT:    v_add_i32_e32 v9, vcc, 3, v9
; SI-NEXT:    v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT:    v_alignbit_b32 v10, v9, v8, 16
; SI-NEXT:    v_alignbit_b32 v11, v7, v6, 16
; SI-NEXT:    v_alignbit_b32 v12, v5, v4, 16
; SI-NEXT:    v_alignbit_b32 v14, v3, v2, 16
; SI-NEXT:    v_alignbit_b32 v16, v1, v0, 16
; SI-NEXT:    v_lshrrev_b32_e32 v13, 16, v9
; SI-NEXT:    v_lshrrev_b32_e32 v15, 16, v7
; SI-NEXT:    v_lshrrev_b32_e32 v17, 16, v5
; SI-NEXT:    v_lshrrev_b32_e32 v18, 16, v3
; SI-NEXT:    v_lshrrev_b32_e32 v19, 16, v1
; SI-NEXT:  .LBB8_4: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT:    v_or_b32_e32 v0, v0, v16
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_lshlrev_b32_e32 v16, 16, v19
; SI-NEXT:    v_or_b32_e32 v2, v2, v14
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT:    v_lshlrev_b32_e32 v14, 16, v18
; SI-NEXT:    v_or_b32_e32 v4, v4, v12
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT:    v_lshlrev_b32_e32 v12, 16, v17
; SI-NEXT:    v_or_b32_e32 v6, v6, v11
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT:    v_lshlrev_b32_e32 v11, 16, v15
; SI-NEXT:    v_or_b32_e32 v8, v8, v10
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v13
; SI-NEXT:    v_or_b32_e32 v1, v1, v16
; SI-NEXT:    v_or_b32_e32 v3, v3, v14
; SI-NEXT:    v_or_b32_e32 v5, v5, v12
; SI-NEXT:    v_or_b32_e32 v7, v7, v11
; SI-NEXT:    v_or_b32_e32 v9, v9, v10
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v10i32_to_v20f16:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB8_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    v_add_u32_e32 v9, vcc, 3, v9
; VI-NEXT:    v_add_u32_e32 v8, vcc, 3, v8
; VI-NEXT:    v_add_u32_e32 v7, vcc, 3, v7
; VI-NEXT:    v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT:    v_add_u32_e32 v5, vcc, 3, v5
; VI-NEXT:    v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT:    v_add_u32_e32 v3, vcc, 3, v3
; VI-NEXT:    v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT:    v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT:  .LBB8_2: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v10i32_to_v20f16:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB8_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    v_add_u32_e32 v9, 3, v9
; GFX9-NEXT:    v_add_u32_e32 v8, 3, v8
; GFX9-NEXT:    v_add_u32_e32 v7, 3, v7
; GFX9-NEXT:    v_add_u32_e32 v6, 3, v6
; GFX9-NEXT:    v_add_u32_e32 v5, 3, v5
; GFX9-NEXT:    v_add_u32_e32 v4, 3, v4
; GFX9-NEXT:    v_add_u32_e32 v3, 3, v3
; GFX9-NEXT:    v_add_u32_e32 v2, 3, v2
; GFX9-NEXT:    v_add_u32_e32 v1, 3, v1
; GFX9-NEXT:    v_add_u32_e32 v0, 3, v0
; GFX9-NEXT:  .LBB8_2: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v10i32_to_v20f16:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB8_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    v_add_nc_u32_e32 v9, 3, v9
; GFX11-NEXT:    v_add_nc_u32_e32 v8, 3, v8
; GFX11-NEXT:    v_add_nc_u32_e32 v7, 3, v7
; GFX11-NEXT:    v_add_nc_u32_e32 v6, 3, v6
; GFX11-NEXT:    v_add_nc_u32_e32 v5, 3, v5
; GFX11-NEXT:    v_add_nc_u32_e32 v4, 3, v4
; GFX11-NEXT:    v_add_nc_u32_e32 v3, 3, v3
; GFX11-NEXT:    v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT:    v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT:    v_add_nc_u32_e32 v0, 3, v0
; GFX11-NEXT:  .LBB8_2: ; %end
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <10 x i32> %a, splat (i32 3)
  %a2 = bitcast <10 x i32> %a1 to <20 x half>
  br label %end

cmp.false:
  %a3 = bitcast <10 x i32> %a to <20 x half>
  br label %end

end:
  %phi = phi <20 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <20 x half> %phi
}

define inreg <20 x half> @bitcast_v10i32_to_v20f16_scalar(<10 x i32> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v10i32_to_v20f16_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc0 .LBB9_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    s_lshr_b32 s14, s25, 16
; SI-NEXT:    s_lshr_b32 s15, s23, 16
; SI-NEXT:    s_lshr_b32 s26, s21, 16
; SI-NEXT:    s_lshr_b32 s27, s19, 16
; SI-NEXT:    s_lshr_b32 s28, s17, 16
; SI-NEXT:    s_lshr_b64 s[4:5], s[24:25], 16
; SI-NEXT:    s_lshr_b64 s[6:7], s[22:23], 16
; SI-NEXT:    s_lshr_b64 s[8:9], s[20:21], 16
; SI-NEXT:    s_lshr_b64 s[10:11], s[18:19], 16
; SI-NEXT:    s_lshr_b64 s[12:13], s[16:17], 16
; SI-NEXT:    s_branch .LBB9_3
; SI-NEXT:  .LBB9_2: ; %cmp.true
; SI-NEXT:    s_add_i32 s17, s17, 3
; SI-NEXT:    s_add_i32 s16, s16, 3
; SI-NEXT:    s_add_i32 s19, s19, 3
; SI-NEXT:    s_add_i32 s18, s18, 3
; SI-NEXT:    s_add_i32 s21, s21, 3
; SI-NEXT:    s_add_i32 s20, s20, 3
; SI-NEXT:    s_add_i32 s23, s23, 3
; SI-NEXT:    s_add_i32 s22, s22, 3
; SI-NEXT:    s_add_i32 s25, s25, 3
; SI-NEXT:    s_add_i32 s24, s24, 3
; SI-NEXT:    s_lshr_b64 s[4:5], s[24:25], 16
; SI-NEXT:    s_lshr_b64 s[6:7], s[22:23], 16
; SI-NEXT:    s_lshr_b64 s[8:9], s[20:21], 16
; SI-NEXT:    s_lshr_b64 s[10:11], s[18:19], 16
; SI-NEXT:    s_lshr_b64 s[12:13], s[16:17], 16
; SI-NEXT:    s_lshr_b32 s14, s25, 16
; SI-NEXT:    s_lshr_b32 s15, s23, 16
; SI-NEXT:    s_lshr_b32 s26, s21, 16
; SI-NEXT:    s_lshr_b32 s27, s19, 16
; SI-NEXT:    s_lshr_b32 s28, s17, 16
; SI-NEXT:  .LBB9_3: ; %end
; SI-NEXT:    s_and_b32 s5, s16, 0xffff
; SI-NEXT:    s_lshl_b32 s7, s12, 16
; SI-NEXT:    s_or_b32 s5, s5, s7
; SI-NEXT:    s_and_b32 s7, s17, 0xffff
; SI-NEXT:    s_lshl_b32 s9, s28, 16
; SI-NEXT:    s_or_b32 s7, s7, s9
; SI-NEXT:    s_and_b32 s9, s18, 0xffff
; SI-NEXT:    s_lshl_b32 s10, s10, 16
; SI-NEXT:    s_or_b32 s9, s9, s10
; SI-NEXT:    s_and_b32 s10, s19, 0xffff
; SI-NEXT:    s_lshl_b32 s11, s27, 16
; SI-NEXT:    s_or_b32 s10, s10, s11
; SI-NEXT:    s_and_b32 s11, s20, 0xffff
; SI-NEXT:    s_lshl_b32 s8, s8, 16
; SI-NEXT:    s_or_b32 s8, s11, s8
; SI-NEXT:    s_and_b32 s11, s21, 0xffff
; SI-NEXT:    s_lshl_b32 s12, s26, 16
; SI-NEXT:    s_or_b32 s11, s11, s12
; SI-NEXT:    s_and_b32 s12, s22, 0xffff
; SI-NEXT:    s_lshl_b32 s6, s6, 16
; SI-NEXT:    s_or_b32 s6, s12, s6
; SI-NEXT:    s_and_b32 s12, s23, 0xffff
; SI-NEXT:    s_lshl_b32 s13, s15, 16
; SI-NEXT:    s_or_b32 s12, s12, s13
; SI-NEXT:    s_and_b32 s13, s24, 0xffff
; SI-NEXT:    s_lshl_b32 s4, s4, 16
; SI-NEXT:    s_or_b32 s4, s13, s4
; SI-NEXT:    s_and_b32 s13, s25, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s14, 16
; SI-NEXT:    s_or_b32 s13, s13, s14
; SI-NEXT:    v_mov_b32_e32 v0, s5
; SI-NEXT:    v_mov_b32_e32 v1, s7
; SI-NEXT:    v_mov_b32_e32 v2, s9
; SI-NEXT:    v_mov_b32_e32 v3, s10
; SI-NEXT:    v_mov_b32_e32 v4, s8
; SI-NEXT:    v_mov_b32_e32 v5, s11
; SI-NEXT:    v_mov_b32_e32 v6, s6
; SI-NEXT:    v_mov_b32_e32 v7, s12
; SI-NEXT:    v_mov_b32_e32 v8, s4
; SI-NEXT:    v_mov_b32_e32 v9, s13
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v10i32_to_v20f16_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc1 .LBB9_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    s_add_i32 s25, s25, 3
; VI-NEXT:    s_add_i32 s24, s24, 3
; VI-NEXT:    s_add_i32 s23, s23, 3
; VI-NEXT:    s_add_i32 s22, s22, 3
; VI-NEXT:    s_add_i32 s21, s21, 3
; VI-NEXT:    s_add_i32 s20, s20, 3
; VI-NEXT:    s_add_i32 s19, s19, 3
; VI-NEXT:    s_add_i32 s18, s18, 3
; VI-NEXT:    s_add_i32 s17, s17, 3
; VI-NEXT:    s_add_i32 s16, s16, 3
; VI-NEXT:  .LBB9_2: ; %end
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s17
; VI-NEXT:    v_mov_b32_e32 v2, s18
; VI-NEXT:    v_mov_b32_e32 v3, s19
; VI-NEXT:    v_mov_b32_e32 v4, s20
; VI-NEXT:    v_mov_b32_e32 v5, s21
; VI-NEXT:    v_mov_b32_e32 v6, s22
; VI-NEXT:    v_mov_b32_e32 v7, s23
; VI-NEXT:    v_mov_b32_e32 v8, s24
; VI-NEXT:    v_mov_b32_e32 v9, s25
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v10i32_to_v20f16_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc1 .LBB9_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    s_add_i32 s25, s25, 3
; GFX9-NEXT:    s_add_i32 s24, s24, 3
; GFX9-NEXT:    s_add_i32 s23, s23, 3
; GFX9-NEXT:    s_add_i32 s22, s22, 3
; GFX9-NEXT:    s_add_i32 s21, s21, 3
; GFX9-NEXT:    s_add_i32 s20, s20, 3
; GFX9-NEXT:    s_add_i32 s19, s19, 3
; GFX9-NEXT:    s_add_i32 s18, s18, 3
; GFX9-NEXT:    s_add_i32 s17, s17, 3
; GFX9-NEXT:    s_add_i32 s16, s16, 3
; GFX9-NEXT:  .LBB9_2: ; %end
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s17
; GFX9-NEXT:    v_mov_b32_e32 v2, s18
; GFX9-NEXT:    v_mov_b32_e32 v3, s19
; GFX9-NEXT:    v_mov_b32_e32 v4, s20
; GFX9-NEXT:    v_mov_b32_e32 v5, s21
; GFX9-NEXT:    v_mov_b32_e32 v6, s22
; GFX9-NEXT:    v_mov_b32_e32 v7, s23
; GFX9-NEXT:    v_mov_b32_e32 v8, s24
; GFX9-NEXT:    v_mov_b32_e32 v9, s25
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v10i32_to_v20f16_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc1 .LBB9_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    s_add_i32 s21, s21, 3
; GFX11-NEXT:    s_add_i32 s20, s20, 3
; GFX11-NEXT:    s_add_i32 s19, s19, 3
; GFX11-NEXT:    s_add_i32 s18, s18, 3
; GFX11-NEXT:    s_add_i32 s17, s17, 3
; GFX11-NEXT:    s_add_i32 s16, s16, 3
; GFX11-NEXT:    s_add_i32 s3, s3, 3
; GFX11-NEXT:    s_add_i32 s2, s2, 3
; GFX11-NEXT:    s_add_i32 s1, s1, 3
; GFX11-NEXT:    s_add_i32 s0, s0, 3
; GFX11-NEXT:  .LBB9_2: ; %end
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <10 x i32> %a, splat (i32 3)
  %a2 = bitcast <10 x i32> %a1 to <20 x half>
  br label %end

cmp.false:
  %a3 = bitcast <10 x i32> %a to <20 x half>
  br label %end

end:
  %phi = phi <20 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <20 x half> %phi
}

define <10 x i32> @bitcast_v20f16_to_v10i32(<20 x half> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v20f16_to_v10i32:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_mov_b32_e32 v20, v9
; SI-NEXT:    v_mov_b32_e32 v11, v8
; SI-NEXT:    v_mov_b32_e32 v12, v7
; SI-NEXT:    v_mov_b32_e32 v13, v6
; SI-NEXT:    v_mov_b32_e32 v14, v5
; SI-NEXT:    v_mov_b32_e32 v15, v4
; SI-NEXT:    v_mov_b32_e32 v16, v3
; SI-NEXT:    v_mov_b32_e32 v17, v2
; SI-NEXT:    v_mov_b32_e32 v18, v1
; SI-NEXT:    v_mov_b32_e32 v19, v0
; SI-NEXT:    v_lshrrev_b32_e32 v21, 16, v20
; SI-NEXT:    v_lshrrev_b32_e32 v22, 16, v11
; SI-NEXT:    v_lshrrev_b32_e32 v23, 16, v12
; SI-NEXT:    v_lshrrev_b32_e32 v24, 16, v13
; SI-NEXT:    v_lshrrev_b32_e32 v25, 16, v14
; SI-NEXT:    v_lshrrev_b32_e32 v26, 16, v15
; SI-NEXT:    v_lshrrev_b32_e32 v27, 16, v16
; SI-NEXT:    v_lshrrev_b32_e32 v28, 16, v17
; SI-NEXT:    v_lshrrev_b32_e32 v29, 16, v18
; SI-NEXT:    v_lshrrev_b32_e32 v30, 16, v19
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; SI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_cbranch_execnz .LBB10_3
; SI-NEXT:  ; %bb.1: ; %Flow
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execnz .LBB10_4
; SI-NEXT:  .LBB10_2: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    s_setpc_b64 s[30:31]
; SI-NEXT:  .LBB10_3: ; %cmp.false
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v19
; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v30
; SI-NEXT:    v_or_b32_e32 v0, v0, v1
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v18
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v29
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v17
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v28
; SI-NEXT:    v_or_b32_e32 v2, v2, v3
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v16
; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v27
; SI-NEXT:    v_or_b32_e32 v3, v3, v4
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v15
; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v26
; SI-NEXT:    v_or_b32_e32 v4, v4, v5
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v14
; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v25
; SI-NEXT:    v_or_b32_e32 v5, v5, v6
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v13
; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v24
; SI-NEXT:    v_or_b32_e32 v6, v6, v7
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v12
; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v23
; SI-NEXT:    v_or_b32_e32 v7, v7, v8
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v11
; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v22
; SI-NEXT:    v_or_b32_e32 v8, v8, v9
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v20
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v21
; SI-NEXT:    v_or_b32_e32 v9, v9, v10
; SI-NEXT:    ; implicit-def: $vgpr19
; SI-NEXT:    ; implicit-def: $vgpr18
; SI-NEXT:    ; implicit-def: $vgpr17
; SI-NEXT:    ; implicit-def: $vgpr16
; SI-NEXT:    ; implicit-def: $vgpr15
; SI-NEXT:    ; implicit-def: $vgpr14
; SI-NEXT:    ; implicit-def: $vgpr13
; SI-NEXT:    ; implicit-def: $vgpr12
; SI-NEXT:    ; implicit-def: $vgpr11
; SI-NEXT:    ; implicit-def: $vgpr20
; SI-NEXT:    ; implicit-def: $vgpr30
; SI-NEXT:    ; implicit-def: $vgpr29
; SI-NEXT:    ; implicit-def: $vgpr28
; SI-NEXT:    ; implicit-def: $vgpr27
; SI-NEXT:    ; implicit-def: $vgpr26
; SI-NEXT:    ; implicit-def: $vgpr25
; SI-NEXT:    ; implicit-def: $vgpr24
; SI-NEXT:    ; implicit-def: $vgpr23
; SI-NEXT:    ; implicit-def: $vgpr22
; SI-NEXT:    ; implicit-def: $vgpr21
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB10_2
; SI-NEXT:  .LBB10_4: ; %cmp.true
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v30
; SI-NEXT:    v_cvt_f32_f16_e32 v1, v19
; SI-NEXT:    v_cvt_f32_f16_e32 v2, v29
; SI-NEXT:    v_cvt_f32_f16_e32 v3, v18
; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1
; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT:    v_cvt_f16_f32_e32 v3, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v4, v28
; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT:    v_or_b32_e32 v0, v1, v0
; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v2
; SI-NEXT:    v_or_b32_e32 v1, v3, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v2, v17
; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v4
; SI-NEXT:    v_cvt_f32_f16_e32 v4, v27
; SI-NEXT:    v_cvt_f16_f32_e32 v3, v3
; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT:    v_cvt_f16_f32_e32 v4, v4
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v5, v16
; SI-NEXT:    v_or_b32_e32 v2, v2, v3
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v4
; SI-NEXT:    v_cvt_f32_f16_e32 v4, v26
; SI-NEXT:    v_cvt_f32_f16_e32 v6, v15
; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT:    v_cvt_f16_f32_e32 v5, v5
; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT:    v_cvt_f16_f32_e32 v4, v4
; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT:    v_cvt_f16_f32_e32 v6, v6
; SI-NEXT:    v_or_b32_e32 v3, v5, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v5, v25
; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT:    v_or_b32_e32 v4, v6, v4
; SI-NEXT:    v_cvt_f32_f16_e32 v6, v14
; SI-NEXT:    v_cvt_f32_f16_e32 v7, v24
; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT:    v_cvt_f16_f32_e32 v5, v5
; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT:    v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT:    v_cvt_f16_f32_e32 v6, v6
; SI-NEXT:    v_cvt_f16_f32_e32 v7, v7
; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT:    v_cvt_f32_f16_e32 v8, v13
; SI-NEXT:    v_or_b32_e32 v5, v6, v5
; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v7
; SI-NEXT:    v_cvt_f32_f16_e32 v7, v23
; SI-NEXT:    v_cvt_f32_f16_e32 v9, v12
; SI-NEXT:    v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT:    v_cvt_f16_f32_e32 v8, v8
; SI-NEXT:    v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT:    v_cvt_f16_f32_e32 v7, v7
; SI-NEXT:    v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT:    v_cvt_f16_f32_e32 v9, v9
; SI-NEXT:    v_or_b32_e32 v6, v8, v6
; SI-NEXT:    v_cvt_f32_f16_e32 v8, v22
; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT:    v_or_b32_e32 v7, v9, v7
; SI-NEXT:    v_cvt_f32_f16_e32 v9, v11
; SI-NEXT:    v_cvt_f32_f16_e32 v10, v21
; SI-NEXT:    v_cvt_f32_f16_e32 v11, v20
; SI-NEXT:    v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT:    v_cvt_f16_f32_e32 v8, v8
; SI-NEXT:    v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT:    v_add_f32_e32 v10, 0x38000000, v10
; SI-NEXT:    v_cvt_f16_f32_e32 v9, v9
; SI-NEXT:    v_cvt_f16_f32_e32 v10, v10
; SI-NEXT:    v_add_f32_e32 v11, 0x38000000, v11
; SI-NEXT:    v_cvt_f16_f32_e32 v11, v11
; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT:    v_or_b32_e32 v8, v9, v8
; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v10
; SI-NEXT:    v_or_b32_e32 v9, v11, v9
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v20f16_to_v10i32:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB10_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    v_mov_b32_e32 v10, 0x200
; VI-NEXT:    v_add_f16_sdwa v11, v9, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v9, 0x200, v9
; VI-NEXT:    v_or_b32_e32 v9, v9, v11
; VI-NEXT:    v_add_f16_sdwa v11, v8, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v8, 0x200, v8
; VI-NEXT:    v_or_b32_e32 v8, v8, v11
; VI-NEXT:    v_add_f16_sdwa v11, v7, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v7, 0x200, v7
; VI-NEXT:    v_or_b32_e32 v7, v7, v11
; VI-NEXT:    v_add_f16_sdwa v11, v6, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v6, 0x200, v6
; VI-NEXT:    v_or_b32_e32 v6, v6, v11
; VI-NEXT:    v_add_f16_sdwa v11, v5, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v5, 0x200, v5
; VI-NEXT:    v_or_b32_e32 v5, v5, v11
; VI-NEXT:    v_add_f16_sdwa v11, v4, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v4, 0x200, v4
; VI-NEXT:    v_or_b32_e32 v4, v4, v11
; VI-NEXT:    v_add_f16_sdwa v11, v3, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v3, 0x200, v3
; VI-NEXT:    v_or_b32_e32 v3, v3, v11
; VI-NEXT:    v_add_f16_sdwa v11, v2, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, 0x200, v2
; VI-NEXT:    v_or_b32_e32 v2, v2, v11
; VI-NEXT:    v_add_f16_sdwa v11, v1, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v1, 0x200, v1
; VI-NEXT:    v_add_f16_sdwa v10, v0, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v0, 0x200, v0
; VI-NEXT:    v_or_b32_e32 v1, v1, v11
; VI-NEXT:    v_or_b32_e32 v0, v0, v10
; VI-NEXT:  .LBB10_2: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v20f16_to_v10i32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB10_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    s_movk_i32 s6, 0x200
; GFX9-NEXT:    v_pk_add_f16 v9, v9, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v8, v8, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
; GFX9-NEXT:  .LBB10_2: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v20f16_to_v10i32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB10_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    v_pk_add_f16 v9, v9, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v8, v8, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v7, v7, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v6, v6, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v5, v5, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v4, v4, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v3, v3, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v2, v2, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v1, v1, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v0, v0, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:  .LBB10_2: ; %end
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <20 x half> %a, splat (half 0xH0200)
  %a2 = bitcast <20 x half> %a1 to <10 x i32>
  br label %end

cmp.false:
  %a3 = bitcast <20 x half> %a to <10 x i32>
  br label %end

end:
  %phi = phi <10 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <10 x i32> %phi
}

define inreg <10 x i32> @bitcast_v20f16_to_v10i32_scalar(<20 x half> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v20f16_to_v10i32_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_lshr_b32 s13, s25, 16
; SI-NEXT:    s_lshr_b32 s12, s24, 16
; SI-NEXT:    s_lshr_b32 s11, s23, 16
; SI-NEXT:    s_lshr_b32 s10, s22, 16
; SI-NEXT:    s_lshr_b32 s9, s21, 16
; SI-NEXT:    s_lshr_b32 s8, s20, 16
; SI-NEXT:    s_lshr_b32 s7, s19, 16
; SI-NEXT:    s_lshr_b32 s6, s18, 16
; SI-NEXT:    s_lshr_b32 s5, s17, 16
; SI-NEXT:    s_lshr_b32 s4, s16, 16
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc0 .LBB11_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    s_and_b32 s14, s16, 0xffff
; SI-NEXT:    s_lshl_b32 s4, s4, 16
; SI-NEXT:    s_or_b32 s4, s14, s4
; SI-NEXT:    s_and_b32 s14, s17, 0xffff
; SI-NEXT:    s_lshl_b32 s5, s5, 16
; SI-NEXT:    s_or_b32 s5, s14, s5
; SI-NEXT:    s_and_b32 s14, s18, 0xffff
; SI-NEXT:    s_lshl_b32 s6, s6, 16
; SI-NEXT:    s_or_b32 s6, s14, s6
; SI-NEXT:    s_and_b32 s14, s19, 0xffff
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_or_b32 s7, s14, s7
; SI-NEXT:    s_and_b32 s14, s20, 0xffff
; SI-NEXT:    s_lshl_b32 s8, s8, 16
; SI-NEXT:    s_or_b32 s8, s14, s8
; SI-NEXT:    s_and_b32 s14, s21, 0xffff
; SI-NEXT:    s_lshl_b32 s9, s9, 16
; SI-NEXT:    s_or_b32 s9, s14, s9
; SI-NEXT:    s_and_b32 s14, s22, 0xffff
; SI-NEXT:    s_lshl_b32 s10, s10, 16
; SI-NEXT:    s_or_b32 s10, s14, s10
; SI-NEXT:    s_and_b32 s14, s23, 0xffff
; SI-NEXT:    s_lshl_b32 s11, s11, 16
; SI-NEXT:    s_or_b32 s11, s14, s11
; SI-NEXT:    s_and_b32 s14, s24, 0xffff
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_or_b32 s12, s14, s12
; SI-NEXT:    s_and_b32 s14, s25, 0xffff
; SI-NEXT:    s_lshl_b32 s13, s13, 16
; SI-NEXT:    s_or_b32 s13, s14, s13
; SI-NEXT:    v_mov_b32_e32 v0, s4
; SI-NEXT:    v_mov_b32_e32 v1, s5
; SI-NEXT:    v_mov_b32_e32 v2, s6
; SI-NEXT:    v_mov_b32_e32 v3, s7
; SI-NEXT:    v_mov_b32_e32 v4, s8
; SI-NEXT:    v_mov_b32_e32 v5, s9
; SI-NEXT:    v_mov_b32_e32 v6, s10
; SI-NEXT:    v_mov_b32_e32 v7, s11
; SI-NEXT:    v_mov_b32_e32 v8, s12
; SI-NEXT:    v_mov_b32_e32 v9, s13
; SI-NEXT:    s_setpc_b64 s[30:31]
; SI-NEXT:  .LBB11_2: ; %cmp.true
; SI-NEXT:    v_cvt_f32_f16_e32 v0, s4
; SI-NEXT:    v_cvt_f32_f16_e32 v1, s16
; SI-NEXT:    v_cvt_f32_f16_e32 v2, s5
; SI-NEXT:    v_cvt_f32_f16_e32 v3, s17
; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1
; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT:    v_cvt_f16_f32_e32 v3, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v4, s6
; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT:    v_or_b32_e32 v0, v1, v0
; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v2
; SI-NEXT:    v_or_b32_e32 v1, v3, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v2, s18
; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v4
; SI-NEXT:    v_cvt_f32_f16_e32 v4, s7
; SI-NEXT:    v_cvt_f16_f32_e32 v3, v3
; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT:    v_cvt_f16_f32_e32 v4, v4
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v5, s19
; SI-NEXT:    v_or_b32_e32 v2, v2, v3
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v4
; SI-NEXT:    v_cvt_f32_f16_e32 v4, s8
; SI-NEXT:    v_cvt_f32_f16_e32 v6, s20
; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT:    v_cvt_f16_f32_e32 v5, v5
; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT:    v_cvt_f16_f32_e32 v4, v4
; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT:    v_cvt_f16_f32_e32 v6, v6
; SI-NEXT:    v_or_b32_e32 v3, v5, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v5, s9
; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT:    v_or_b32_e32 v4, v6, v4
; SI-NEXT:    v_cvt_f32_f16_e32 v6, s21
; SI-NEXT:    v_cvt_f32_f16_e32 v7, s10
; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT:    v_cvt_f16_f32_e32 v5, v5
; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT:    v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT:    v_cvt_f16_f32_e32 v6, v6
; SI-NEXT:    v_cvt_f16_f32_e32 v7, v7
; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT:    v_cvt_f32_f16_e32 v8, s22
; SI-NEXT:    v_or_b32_e32 v5, v6, v5
; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v7
; SI-NEXT:    v_cvt_f32_f16_e32 v7, s11
; SI-NEXT:    v_cvt_f32_f16_e32 v9, s23
; SI-NEXT:    v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT:    v_cvt_f16_f32_e32 v8, v8
; SI-NEXT:    v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT:    v_cvt_f16_f32_e32 v7, v7
; SI-NEXT:    v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT:    v_cvt_f16_f32_e32 v9, v9
; SI-NEXT:    v_or_b32_e32 v6, v8, v6
; SI-NEXT:    v_cvt_f32_f16_e32 v8, s12
; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT:    v_or_b32_e32 v7, v9, v7
; SI-NEXT:    v_cvt_f32_f16_e32 v9, s24
; SI-NEXT:    v_cvt_f32_f16_e32 v10, s13
; SI-NEXT:    v_cvt_f32_f16_e32 v11, s25
; SI-NEXT:    v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT:    v_cvt_f16_f32_e32 v8, v8
; SI-NEXT:    v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT:    v_add_f32_e32 v10, 0x38000000, v10
; SI-NEXT:    v_cvt_f16_f32_e32 v9, v9
; SI-NEXT:    v_cvt_f16_f32_e32 v10, v10
; SI-NEXT:    v_add_f32_e32 v11, 0x38000000, v11
; SI-NEXT:    v_cvt_f16_f32_e32 v11, v11
; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT:    v_or_b32_e32 v8, v9, v8
; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v10
; SI-NEXT:    v_or_b32_e32 v9, v11, v9
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v20f16_to_v10i32_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc0 .LBB11_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s17
; VI-NEXT:    v_mov_b32_e32 v2, s18
; VI-NEXT:    v_mov_b32_e32 v3, s19
; VI-NEXT:    v_mov_b32_e32 v4, s20
; VI-NEXT:    v_mov_b32_e32 v5, s21
; VI-NEXT:    v_mov_b32_e32 v6, s22
; VI-NEXT:    v_mov_b32_e32 v7, s23
; VI-NEXT:    v_mov_b32_e32 v8, s24
; VI-NEXT:    v_mov_b32_e32 v9, s25
; VI-NEXT:    s_setpc_b64 s[30:31]
; VI-NEXT:  .LBB11_2: ; %cmp.true
; VI-NEXT:    s_lshr_b32 s4, s25, 16
; VI-NEXT:    v_mov_b32_e32 v0, 0x200
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, s25, v0
; VI-NEXT:    s_lshr_b32 s4, s24, 16
; VI-NEXT:    v_or_b32_e32 v9, v2, v1
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, s24, v0
; VI-NEXT:    s_lshr_b32 s4, s23, 16
; VI-NEXT:    v_or_b32_e32 v8, v2, v1
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, s23, v0
; VI-NEXT:    s_lshr_b32 s4, s22, 16
; VI-NEXT:    v_or_b32_e32 v7, v2, v1
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, s22, v0
; VI-NEXT:    s_lshr_b32 s4, s21, 16
; VI-NEXT:    v_or_b32_e32 v6, v2, v1
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, s21, v0
; VI-NEXT:    s_lshr_b32 s4, s20, 16
; VI-NEXT:    v_or_b32_e32 v5, v2, v1
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, s20, v0
; VI-NEXT:    s_lshr_b32 s4, s19, 16
; VI-NEXT:    v_or_b32_e32 v4, v2, v1
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, s19, v0
; VI-NEXT:    s_lshr_b32 s4, s18, 16
; VI-NEXT:    v_or_b32_e32 v3, v2, v1
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, s18, v0
; VI-NEXT:    s_lshr_b32 s4, s17, 16
; VI-NEXT:    v_or_b32_e32 v2, v2, v1
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v10, s17, v0
; VI-NEXT:    s_lshr_b32 s4, s16, 16
; VI-NEXT:    v_or_b32_e32 v1, v10, v1
; VI-NEXT:    v_mov_b32_e32 v10, s4
; VI-NEXT:    v_add_f16_sdwa v10, v10, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v0, s16, v0
; VI-NEXT:    v_or_b32_e32 v0, v0, v10
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v20f16_to_v10i32_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc0 .LBB11_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s17
; GFX9-NEXT:    v_mov_b32_e32 v2, s18
; GFX9-NEXT:    v_mov_b32_e32 v3, s19
; GFX9-NEXT:    v_mov_b32_e32 v4, s20
; GFX9-NEXT:    v_mov_b32_e32 v5, s21
; GFX9-NEXT:    v_mov_b32_e32 v6, s22
; GFX9-NEXT:    v_mov_b32_e32 v7, s23
; GFX9-NEXT:    v_mov_b32_e32 v8, s24
; GFX9-NEXT:    v_mov_b32_e32 v9, s25
; GFX9-NEXT:    s_setpc_b64 s[30:31]
; GFX9-NEXT:  .LBB11_2: ; %cmp.true
; GFX9-NEXT:    v_mov_b32_e32 v0, 0x200
; GFX9-NEXT:    v_pk_add_f16 v9, s25, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v8, s24, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v7, s23, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v6, s22, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v5, s21, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v4, s20, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v3, s19, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v20f16_to_v10i32_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s15, s3
; GFX11-NEXT:    s_mov_b32 s14, s2
; GFX11-NEXT:    s_mov_b32 s13, s1
; GFX11-NEXT:    s_mov_b32 s12, s0
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc0 .LBB11_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-NEXT:    v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
; GFX11-NEXT:    v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT:    s_setpc_b64 s[30:31]
; GFX11-NEXT:  .LBB11_2: ; %cmp.true
; GFX11-NEXT:    v_pk_add_f16 v9, s21, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v8, s20, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v7, s19, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v6, s18, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v5, s17, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v4, s16, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v3, s15, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v2, s14, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v1, s13, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v0, s12, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <20 x half> %a, splat (half 0xH0200)
  %a2 = bitcast <20 x half> %a1 to <10 x i32>
  br label %end

cmp.false:
  %a3 = bitcast <20 x half> %a to <10 x i32>
  br label %end

end:
  %phi = phi <10 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <10 x i32> %phi
}

define <40 x i8> @bitcast_v10i32_to_v40i8(<10 x i32> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v10i32_to_v40i8:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
; SI-NEXT:    ; implicit-def: $vgpr35
; SI-NEXT:    ; implicit-def: $vgpr33
; SI-NEXT:    ; implicit-def: $vgpr32
; SI-NEXT:    ; implicit-def: $vgpr48
; SI-NEXT:    ; implicit-def: $vgpr39
; SI-NEXT:    ; implicit-def: $vgpr38
; SI-NEXT:    ; implicit-def: $vgpr28
; SI-NEXT:    ; implicit-def: $vgpr27
; SI-NEXT:    ; implicit-def: $vgpr26
; SI-NEXT:    ; implicit-def: $vgpr37
; SI-NEXT:    ; implicit-def: $vgpr36
; SI-NEXT:    ; implicit-def: $vgpr34
; SI-NEXT:    ; implicit-def: $vgpr22
; SI-NEXT:    ; implicit-def: $vgpr21
; SI-NEXT:    ; implicit-def: $vgpr20
; SI-NEXT:    ; implicit-def: $vgpr31
; SI-NEXT:    ; implicit-def: $vgpr30
; SI-NEXT:    ; implicit-def: $vgpr29
; SI-NEXT:    ; implicit-def: $vgpr16
; SI-NEXT:    ; implicit-def: $vgpr15
; SI-NEXT:    ; implicit-def: $vgpr14
; SI-NEXT:    ; implicit-def: $vgpr25
; SI-NEXT:    ; implicit-def: $vgpr24
; SI-NEXT:    ; implicit-def: $vgpr23
; SI-NEXT:    ; implicit-def: $vgpr13
; SI-NEXT:    ; implicit-def: $vgpr12
; SI-NEXT:    ; implicit-def: $vgpr11
; SI-NEXT:    ; implicit-def: $vgpr19
; SI-NEXT:    ; implicit-def: $vgpr18
; SI-NEXT:    ; implicit-def: $vgpr17
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB12_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    v_alignbit_b32 v11, v10, v9, 24
; SI-NEXT:    v_alignbit_b32 v12, v10, v9, 16
; SI-NEXT:    v_alignbit_b32 v13, v10, v9, 8
; SI-NEXT:    v_alignbit_b32 v14, v8, v7, 24
; SI-NEXT:    v_alignbit_b32 v15, v8, v7, 16
; SI-NEXT:    v_alignbit_b32 v16, v8, v7, 8
; SI-NEXT:    v_alignbit_b32 v20, v6, v5, 24
; SI-NEXT:    v_alignbit_b32 v21, v6, v5, 16
; SI-NEXT:    v_alignbit_b32 v22, v6, v5, 8
; SI-NEXT:    v_alignbit_b32 v26, v4, v3, 24
; SI-NEXT:    v_alignbit_b32 v27, v4, v3, 16
; SI-NEXT:    v_alignbit_b32 v28, v4, v3, 8
; SI-NEXT:    v_alignbit_b32 v32, v2, v1, 24
; SI-NEXT:    v_alignbit_b32 v33, v2, v1, 16
; SI-NEXT:    v_alignbit_b32 v35, v2, v1, 8
; SI-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; SI-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; SI-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; SI-NEXT:    v_lshrrev_b32_e32 v23, 24, v8
; SI-NEXT:    v_lshrrev_b32_e32 v24, 16, v8
; SI-NEXT:    v_lshrrev_b32_e32 v25, 8, v8
; SI-NEXT:    v_lshrrev_b32_e32 v29, 24, v6
; SI-NEXT:    v_lshrrev_b32_e32 v30, 16, v6
; SI-NEXT:    v_lshrrev_b32_e32 v31, 8, v6
; SI-NEXT:    v_lshrrev_b32_e32 v34, 24, v4
; SI-NEXT:    v_lshrrev_b32_e32 v36, 16, v4
; SI-NEXT:    v_lshrrev_b32_e32 v37, 8, v4
; SI-NEXT:    v_lshrrev_b32_e32 v38, 24, v2
; SI-NEXT:    v_lshrrev_b32_e32 v39, 16, v2
; SI-NEXT:    v_lshrrev_b32_e32 v48, 8, v2
; SI-NEXT:  .LBB12_2: ; %Flow
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB12_4
; SI-NEXT:  ; %bb.3: ; %cmp.true
; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v3
; SI-NEXT:    v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT:    v_add_i32_e32 v5, vcc, 3, v5
; SI-NEXT:    v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT:    v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT:    v_add_i32_e32 v10, vcc, 3, v10
; SI-NEXT:    v_add_i32_e32 v9, vcc, 3, v9
; SI-NEXT:    v_alignbit_b32 v11, v10, v9, 24
; SI-NEXT:    v_alignbit_b32 v12, v10, v9, 16
; SI-NEXT:    v_alignbit_b32 v13, v10, v9, 8
; SI-NEXT:    v_alignbit_b32 v14, v8, v7, 24
; SI-NEXT:    v_alignbit_b32 v15, v8, v7, 16
; SI-NEXT:    v_alignbit_b32 v16, v8, v7, 8
; SI-NEXT:    v_alignbit_b32 v20, v6, v5, 24
; SI-NEXT:    v_alignbit_b32 v21, v6, v5, 16
; SI-NEXT:    v_alignbit_b32 v22, v6, v5, 8
; SI-NEXT:    v_alignbit_b32 v26, v4, v3, 24
; SI-NEXT:    v_alignbit_b32 v27, v4, v3, 16
; SI-NEXT:    v_alignbit_b32 v28, v4, v3, 8
; SI-NEXT:    v_alignbit_b32 v32, v2, v1, 24
; SI-NEXT:    v_alignbit_b32 v33, v2, v1, 16
; SI-NEXT:    v_alignbit_b32 v35, v2, v1, 8
; SI-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; SI-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; SI-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; SI-NEXT:    v_lshrrev_b32_e32 v23, 24, v8
; SI-NEXT:    v_lshrrev_b32_e32 v24, 16, v8
; SI-NEXT:    v_lshrrev_b32_e32 v25, 8, v8
; SI-NEXT:    v_lshrrev_b32_e32 v29, 24, v6
; SI-NEXT:    v_lshrrev_b32_e32 v30, 16, v6
; SI-NEXT:    v_lshrrev_b32_e32 v31, 8, v6
; SI-NEXT:    v_lshrrev_b32_e32 v34, 24, v4
; SI-NEXT:    v_lshrrev_b32_e32 v36, 16, v4
; SI-NEXT:    v_lshrrev_b32_e32 v37, 8, v4
; SI-NEXT:    v_lshrrev_b32_e32 v38, 24, v2
; SI-NEXT:    v_lshrrev_b32_e32 v39, 16, v2
; SI-NEXT:    v_lshrrev_b32_e32 v48, 8, v2
; SI-NEXT:  .LBB12_4: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1
; SI-NEXT:    v_lshlrev_b32_e32 v35, 8, v35
; SI-NEXT:    v_and_b32_e32 v33, 0xff, v33
; SI-NEXT:    v_or_b32_e32 v1, v1, v35
; SI-NEXT:    v_lshlrev_b32_e32 v33, 16, v33
; SI-NEXT:    v_lshlrev_b32_e32 v32, 24, v32
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v32, v32, v33
; SI-NEXT:    v_or_b32_e32 v1, v1, v32
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v2
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v48
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v39
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v32, 24, v38
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v32, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v3
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v28
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v27
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v26
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v4
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v37
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v36
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v34
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v5
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v22
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v21
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v20
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v6
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v31
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v30
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v29
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v7
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v16
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v15
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v14
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v8
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v25
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v24
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v23
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v9
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v13
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v12
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v11
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v10
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v19
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v18
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v17
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v10i32_to_v40i8:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
; VI-NEXT:    ; implicit-def: $vgpr16
; VI-NEXT:    ; implicit-def: $vgpr48
; VI-NEXT:    ; implicit-def: $vgpr15
; VI-NEXT:    ; implicit-def: $vgpr39
; VI-NEXT:    ; implicit-def: $vgpr38
; VI-NEXT:    ; implicit-def: $vgpr37
; VI-NEXT:    ; implicit-def: $vgpr36
; VI-NEXT:    ; implicit-def: $vgpr35
; VI-NEXT:    ; implicit-def: $vgpr14
; VI-NEXT:    ; implicit-def: $vgpr34
; VI-NEXT:    ; implicit-def: $vgpr33
; VI-NEXT:    ; implicit-def: $vgpr32
; VI-NEXT:    ; implicit-def: $vgpr31
; VI-NEXT:    ; implicit-def: $vgpr30
; VI-NEXT:    ; implicit-def: $vgpr13
; VI-NEXT:    ; implicit-def: $vgpr29
; VI-NEXT:    ; implicit-def: $vgpr28
; VI-NEXT:    ; implicit-def: $vgpr27
; VI-NEXT:    ; implicit-def: $vgpr26
; VI-NEXT:    ; implicit-def: $vgpr25
; VI-NEXT:    ; implicit-def: $vgpr12
; VI-NEXT:    ; implicit-def: $vgpr24
; VI-NEXT:    ; implicit-def: $vgpr23
; VI-NEXT:    ; implicit-def: $vgpr22
; VI-NEXT:    ; implicit-def: $vgpr21
; VI-NEXT:    ; implicit-def: $vgpr20
; VI-NEXT:    ; implicit-def: $vgpr19
; VI-NEXT:    ; implicit-def: $vgpr18
; VI-NEXT:    ; implicit-def: $vgpr17
; VI-NEXT:    ; implicit-def: $vgpr11
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB12_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; VI-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; VI-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; VI-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; VI-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; VI-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; VI-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; VI-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; VI-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
; VI-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
; VI-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
; VI-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
; VI-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
; VI-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
; VI-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
; VI-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
; VI-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
; VI-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; VI-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; VI-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; VI-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
; VI-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
; VI-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
; VI-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
; VI-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
; VI-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
; VI-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
; VI-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
; VI-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
; VI-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; VI-NEXT:  .LBB12_2: ; %Flow
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB12_4
; VI-NEXT:  ; %bb.3: ; %cmp.true
; VI-NEXT:    v_add_u32_e32 v10, vcc, 3, v10
; VI-NEXT:    v_add_u32_e32 v9, vcc, 3, v9
; VI-NEXT:    v_add_u32_e32 v8, vcc, 3, v8
; VI-NEXT:    v_add_u32_e32 v7, vcc, 3, v7
; VI-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; VI-NEXT:    v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT:    v_add_u32_e32 v5, vcc, 3, v5
; VI-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; VI-NEXT:    v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT:    v_add_u32_e32 v3, vcc, 3, v3
; VI-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; VI-NEXT:    v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT:    v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; VI-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; VI-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; VI-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; VI-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; VI-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
; VI-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
; VI-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
; VI-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
; VI-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
; VI-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
; VI-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
; VI-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
; VI-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
; VI-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; VI-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; VI-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; VI-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
; VI-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
; VI-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
; VI-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
; VI-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
; VI-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
; VI-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
; VI-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
; VI-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
; VI-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; VI-NEXT:  .LBB12_4: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_mov_b32 s4, 0xc0c0004
; VI-NEXT:    v_perm_b32 v15, v48, v15, s4
; VI-NEXT:    v_perm_b32 v1, v1, v16, s4
; VI-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT:    v_or_b32_e32 v1, v1, v15
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT:    v_perm_b32 v1, v2, v39, s4
; VI-NEXT:    v_perm_b32 v2, v38, v37, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v35, v14, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
; VI-NEXT:    v_perm_b32 v1, v3, v36, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v33, v32, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; VI-NEXT:    v_perm_b32 v1, v4, v34, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v30, v13, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; VI-NEXT:    v_perm_b32 v1, v5, v31, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v28, v27, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; VI-NEXT:    v_perm_b32 v1, v6, v29, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v25, v12, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; VI-NEXT:    v_perm_b32 v1, v7, v26, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v23, v22, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; VI-NEXT:    v_perm_b32 v1, v8, v24, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v20, v11, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; VI-NEXT:    v_perm_b32 v1, v9, v21, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v18, v17, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; VI-NEXT:    v_perm_b32 v1, v10, v19, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v10i32_to_v40i8:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
; GFX9-NEXT:    ; implicit-def: $vgpr16
; GFX9-NEXT:    ; implicit-def: $vgpr48
; GFX9-NEXT:    ; implicit-def: $vgpr15
; GFX9-NEXT:    ; implicit-def: $vgpr39
; GFX9-NEXT:    ; implicit-def: $vgpr38
; GFX9-NEXT:    ; implicit-def: $vgpr37
; GFX9-NEXT:    ; implicit-def: $vgpr36
; GFX9-NEXT:    ; implicit-def: $vgpr35
; GFX9-NEXT:    ; implicit-def: $vgpr14
; GFX9-NEXT:    ; implicit-def: $vgpr34
; GFX9-NEXT:    ; implicit-def: $vgpr33
; GFX9-NEXT:    ; implicit-def: $vgpr32
; GFX9-NEXT:    ; implicit-def: $vgpr31
; GFX9-NEXT:    ; implicit-def: $vgpr30
; GFX9-NEXT:    ; implicit-def: $vgpr13
; GFX9-NEXT:    ; implicit-def: $vgpr29
; GFX9-NEXT:    ; implicit-def: $vgpr28
; GFX9-NEXT:    ; implicit-def: $vgpr27
; GFX9-NEXT:    ; implicit-def: $vgpr26
; GFX9-NEXT:    ; implicit-def: $vgpr25
; GFX9-NEXT:    ; implicit-def: $vgpr12
; GFX9-NEXT:    ; implicit-def: $vgpr24
; GFX9-NEXT:    ; implicit-def: $vgpr23
; GFX9-NEXT:    ; implicit-def: $vgpr22
; GFX9-NEXT:    ; implicit-def: $vgpr21
; GFX9-NEXT:    ; implicit-def: $vgpr20
; GFX9-NEXT:    ; implicit-def: $vgpr19
; GFX9-NEXT:    ; implicit-def: $vgpr18
; GFX9-NEXT:    ; implicit-def: $vgpr17
; GFX9-NEXT:    ; implicit-def: $vgpr11
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB12_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX9-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX9-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX9-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX9-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX9-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
; GFX9-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
; GFX9-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
; GFX9-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
; GFX9-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; GFX9-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; GFX9-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
; GFX9-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
; GFX9-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
; GFX9-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX9-NEXT:  .LBB12_2: ; %Flow
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB12_4
; GFX9-NEXT:  ; %bb.3: ; %cmp.true
; GFX9-NEXT:    v_add_u32_e32 v10, 3, v10
; GFX9-NEXT:    v_add_u32_e32 v9, 3, v9
; GFX9-NEXT:    v_add_u32_e32 v8, 3, v8
; GFX9-NEXT:    v_add_u32_e32 v7, 3, v7
; GFX9-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX9-NEXT:    v_add_u32_e32 v6, 3, v6
; GFX9-NEXT:    v_add_u32_e32 v5, 3, v5
; GFX9-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX9-NEXT:    v_add_u32_e32 v4, 3, v4
; GFX9-NEXT:    v_add_u32_e32 v3, 3, v3
; GFX9-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX9-NEXT:    v_add_u32_e32 v2, 3, v2
; GFX9-NEXT:    v_add_u32_e32 v1, 3, v1
; GFX9-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX9-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX9-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
; GFX9-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
; GFX9-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
; GFX9-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
; GFX9-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; GFX9-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; GFX9-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
; GFX9-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
; GFX9-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
; GFX9-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX9-NEXT:  .LBB12_4: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_mov_b32 s4, 0xc0c0004
; GFX9-NEXT:    v_perm_b32 v15, v48, v15, s4
; GFX9-NEXT:    v_perm_b32 v1, v1, v16, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v15, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen
; GFX9-NEXT:    v_perm_b32 v1, v2, v39, s4
; GFX9-NEXT:    v_perm_b32 v2, v38, v37, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT:    v_perm_b32 v1, v3, v36, s4
; GFX9-NEXT:    v_perm_b32 v2, v35, v14, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT:    v_perm_b32 v1, v4, v34, s4
; GFX9-NEXT:    v_perm_b32 v2, v33, v32, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; GFX9-NEXT:    v_perm_b32 v1, v5, v31, s4
; GFX9-NEXT:    v_perm_b32 v2, v30, v13, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT:    v_perm_b32 v1, v6, v29, s4
; GFX9-NEXT:    v_perm_b32 v2, v28, v27, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; GFX9-NEXT:    v_perm_b32 v1, v7, v26, s4
; GFX9-NEXT:    v_perm_b32 v2, v25, v12, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT:    v_perm_b32 v1, v8, v24, s4
; GFX9-NEXT:    v_perm_b32 v2, v23, v22, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; GFX9-NEXT:    v_perm_b32 v1, v9, v21, s4
; GFX9-NEXT:    v_perm_b32 v2, v20, v11, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT:    v_perm_b32 v1, v10, v19, s4
; GFX9-NEXT:    v_perm_b32 v2, v18, v17, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v10i32_to_v40i8:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v11
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr11_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB12_2
; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v18, 8, v10
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v9
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v20, 24, v8
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v8
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v22, 8, v7
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v6
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v6
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v5
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v4
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v4
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v3
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v28, 24, v2
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v2
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX11-TRUE16-NEXT:  .LBB12_2: ; %Flow
; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB12_4
; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v10, 3, v10
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v9, 3, v9
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v8, 3, v8
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v7, 3, v7
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v6, 3, v6
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v5, 3, v5
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v4, 3, v4
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v3, 3, v3
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, 3, v2
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v1, 3, v1
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v18, 8, v10
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v9
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v20, 24, v8
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v8
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v22, 8, v7
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v6
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v6
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v5
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v4
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v4
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v3
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v28, 24, v2
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v2
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX11-TRUE16-NEXT:  .LBB12_4: ; %end
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v31.l, v1.h
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_perm_b32 v1, v1, v16, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v16, v2, v30, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v29, v3, v29, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v3.h
; GFX11-TRUE16-NEXT:    v_perm_b32 v15, v31, v15, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v31.l, v5.h
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v30.l, v4.h
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
; GFX11-TRUE16-NEXT:    v_perm_b32 v5, v5, v25, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v1, v15, 16, v1
; GFX11-TRUE16-NEXT:    v_perm_b32 v13, v31, v13, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v3, v3, v14, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v4, v4, v27, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v14, v30, v26, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v15.l, v6.h
; GFX11-TRUE16-NEXT:    v_perm_b32 v2, v2, v28, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v5, v13, 16, v5
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v7.h
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v4, v14, 16, v4
; GFX11-TRUE16-NEXT:    v_perm_b32 v14, v15, v23, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v15.l, v8.h
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v2, v2, 16, v16
; GFX11-TRUE16-NEXT:    v_perm_b32 v12, v13, v12, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v9.h
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.l, v10.h
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, v6, v24, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, v7, v22, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v8, v8, v21, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v15, v15, v20, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v9, v9, v19, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v11, v13, v11, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v10, v10, v18, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v13, v16, v17, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v3, v3, 16, v29
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v6, v14, 16, v6
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v7, v12, 16, v7
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v8, v15, 16, v8
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v9, v11, 16, v9
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v10, v13, 16, v10
; GFX11-TRUE16-NEXT:    s_clause 0x2
; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[1:4], off
; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
; GFX11-TRUE16-NEXT:    scratch_store_b64 v0, v[9:10], off offset:32
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v10i32_to_v40i8:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v11
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB12_2
; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX11-FAKE16-NEXT:  .LBB12_2: ; %Flow
; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB12_4
; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v10, 3, v10
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v9, 3, v9
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v8, 3, v8
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v7, 3, v7
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v6, 3, v6
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v5, 3, v5
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, 3, v4
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v3, 3, v3
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v2, 3, v2
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v1, 3, v1
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX11-FAKE16-NEXT:  .LBB12_4: ; %end
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v3, v36, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v35, v14, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v5, v31, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v30, v13, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v1, v16, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v48, v15, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v2, v39, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v16, v38, v37, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v4, v34, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v32, v33, v32, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v3, v14, 16, v3
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v5, v13, 16, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v6, v29, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v28, v27, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v7, v26, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v25, v12, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v8, v24, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v23, v22, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v15, 16, v1
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v9, v21, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v20, v11, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v10, v19, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v18, v17, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, v16, 16, v2
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v4, v32, 16, v4
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v6, v13, 16, v6
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v7, v12, 16, v7
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v8, v14, 16, v8
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v9, v11, 16, v9
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v10, v15, 16, v10
; GFX11-FAKE16-NEXT:    s_clause 0x2
; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[1:4], off
; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
; GFX11-FAKE16-NEXT:    scratch_store_b64 v0, v[9:10], off offset:32
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <10 x i32> %a, splat (i32 3)
  %a2 = bitcast <10 x i32> %a1 to <40 x i8>
  br label %end

cmp.false:
  %a3 = bitcast <10 x i32> %a to <40 x i8>
  br label %end

end:
  %phi = phi <40 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <40 x i8> %phi
}

define inreg <40 x i8> @bitcast_v10i32_to_v40i8_scalar(<10 x i32> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v10i32_to_v40i8_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc0 .LBB13_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    s_lshr_b32 s62, s25, 24
; SI-NEXT:    s_lshr_b32 s63, s25, 16
; SI-NEXT:    s_lshr_b32 s72, s25, 8
; SI-NEXT:    s_lshr_b32 s73, s23, 24
; SI-NEXT:    s_lshr_b32 s74, s23, 16
; SI-NEXT:    s_lshr_b32 s75, s23, 8
; SI-NEXT:    s_lshr_b32 s76, s21, 24
; SI-NEXT:    s_lshr_b32 s77, s21, 16
; SI-NEXT:    s_lshr_b32 s78, s21, 8
; SI-NEXT:    s_lshr_b32 s79, s19, 24
; SI-NEXT:    s_lshr_b32 s88, s19, 16
; SI-NEXT:    s_lshr_b32 s89, s19, 8
; SI-NEXT:    s_lshr_b32 s90, s17, 24
; SI-NEXT:    s_lshr_b32 s91, s17, 16
; SI-NEXT:    s_lshr_b32 s92, s17, 8
; SI-NEXT:    s_lshr_b64 s[4:5], s[24:25], 24
; SI-NEXT:    s_lshr_b64 s[6:7], s[24:25], 16
; SI-NEXT:    s_lshr_b64 s[8:9], s[24:25], 8
; SI-NEXT:    s_lshr_b64 s[10:11], s[22:23], 24
; SI-NEXT:    s_lshr_b64 s[12:13], s[22:23], 16
; SI-NEXT:    s_lshr_b64 s[14:15], s[22:23], 8
; SI-NEXT:    s_lshr_b64 s[26:27], s[20:21], 24
; SI-NEXT:    s_lshr_b64 s[28:29], s[20:21], 16
; SI-NEXT:    s_lshr_b64 s[40:41], s[20:21], 8
; SI-NEXT:    s_lshr_b64 s[42:43], s[18:19], 24
; SI-NEXT:    s_branch .LBB13_3
; SI-NEXT:  .LBB13_2: ; %cmp.true
; SI-NEXT:    s_add_i32 s17, s17, 3
; SI-NEXT:    s_add_i32 s19, s19, 3
; SI-NEXT:    s_add_i32 s18, s18, 3
; SI-NEXT:    s_add_i32 s21, s21, 3
; SI-NEXT:    s_add_i32 s20, s20, 3
; SI-NEXT:    s_add_i32 s23, s23, 3
; SI-NEXT:    s_add_i32 s22, s22, 3
; SI-NEXT:    s_add_i32 s25, s25, 3
; SI-NEXT:    s_add_i32 s24, s24, 3
; SI-NEXT:    s_add_i32 s16, s16, 3
; SI-NEXT:    s_lshr_b64 s[4:5], s[24:25], 24
; SI-NEXT:    s_lshr_b64 s[6:7], s[24:25], 16
; SI-NEXT:    s_lshr_b64 s[8:9], s[24:25], 8
; SI-NEXT:    s_lshr_b64 s[10:11], s[22:23], 24
; SI-NEXT:    s_lshr_b64 s[12:13], s[22:23], 16
; SI-NEXT:    s_lshr_b64 s[14:15], s[22:23], 8
; SI-NEXT:    s_lshr_b64 s[26:27], s[20:21], 24
; SI-NEXT:    s_lshr_b64 s[28:29], s[20:21], 16
; SI-NEXT:    s_lshr_b64 s[40:41], s[20:21], 8
; SI-NEXT:    s_lshr_b64 s[42:43], s[18:19], 24
; SI-NEXT:    s_lshr_b32 s62, s25, 24
; SI-NEXT:    s_lshr_b32 s63, s25, 16
; SI-NEXT:    s_lshr_b32 s72, s25, 8
; SI-NEXT:    s_lshr_b32 s73, s23, 24
; SI-NEXT:    s_lshr_b32 s74, s23, 16
; SI-NEXT:    s_lshr_b32 s75, s23, 8
; SI-NEXT:    s_lshr_b32 s76, s21, 24
; SI-NEXT:    s_lshr_b32 s77, s21, 16
; SI-NEXT:    s_lshr_b32 s78, s21, 8
; SI-NEXT:    s_lshr_b32 s79, s19, 24
; SI-NEXT:    s_lshr_b32 s88, s19, 16
; SI-NEXT:    s_lshr_b32 s89, s19, 8
; SI-NEXT:    s_lshr_b32 s90, s17, 24
; SI-NEXT:    s_lshr_b32 s91, s17, 16
; SI-NEXT:    s_lshr_b32 s92, s17, 8
; SI-NEXT:  .LBB13_3: ; %end
; SI-NEXT:    s_lshr_b64 s[60:61], s[16:17], 8
; SI-NEXT:    s_lshr_b64 s[58:59], s[16:17], 16
; SI-NEXT:    s_lshl_b32 s5, s60, 8
; SI-NEXT:    s_and_b32 s7, s16, 0xff
; SI-NEXT:    s_lshr_b64 s[56:57], s[16:17], 24
; SI-NEXT:    s_or_b32 s5, s7, s5
; SI-NEXT:    s_and_b32 s7, s58, 0xff
; SI-NEXT:    s_lshl_b32 s9, s56, 24
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_or_b32 s7, s9, s7
; SI-NEXT:    s_and_b32 s5, s5, 0xffff
; SI-NEXT:    s_or_b32 s5, s5, s7
; SI-NEXT:    v_mov_b32_e32 v1, s5
; SI-NEXT:    s_and_b32 s5, s17, 0xff
; SI-NEXT:    s_lshl_b32 s7, s92, 8
; SI-NEXT:    s_or_b32 s5, s5, s7
; SI-NEXT:    s_and_b32 s7, s91, 0xff
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_lshl_b32 s9, s90, 24
; SI-NEXT:    s_or_b32 s7, s9, s7
; SI-NEXT:    s_and_b32 s5, s5, 0xffff
; SI-NEXT:    s_lshr_b64 s[46:47], s[18:19], 8
; SI-NEXT:    s_or_b32 s5, s5, s7
; SI-NEXT:    s_lshr_b64 s[44:45], s[18:19], 16
; SI-NEXT:    v_mov_b32_e32 v2, s5
; SI-NEXT:    s_lshl_b32 s5, s46, 8
; SI-NEXT:    s_and_b32 s7, s18, 0xff
; SI-NEXT:    s_or_b32 s5, s7, s5
; SI-NEXT:    s_and_b32 s7, s44, 0xff
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_lshl_b32 s9, s42, 24
; SI-NEXT:    s_and_b32 s5, s5, 0xffff
; SI-NEXT:    s_or_b32 s7, s9, s7
; SI-NEXT:    s_or_b32 s5, s5, s7
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen
; SI-NEXT:    buffer_store_dword v2, v0, s[0:3], 0 offen offset:4
; SI-NEXT:    s_waitcnt expcnt(1)
; SI-NEXT:    v_mov_b32_e32 v1, s5
; SI-NEXT:    s_and_b32 s5, s19, 0xff
; SI-NEXT:    s_lshl_b32 s7, s89, 8
; SI-NEXT:    s_or_b32 s5, s5, s7
; SI-NEXT:    s_and_b32 s7, s88, 0xff
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_lshl_b32 s9, s79, 24
; SI-NEXT:    s_and_b32 s5, s5, 0xffff
; SI-NEXT:    s_or_b32 s7, s9, s7
; SI-NEXT:    s_or_b32 s5, s5, s7
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_mov_b32_e32 v1, s5
; SI-NEXT:    s_and_b32 s5, s20, 0xff
; SI-NEXT:    s_lshl_b32 s7, s40, 8
; SI-NEXT:    s_or_b32 s5, s5, s7
; SI-NEXT:    s_and_b32 s7, s28, 0xff
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_lshl_b32 s9, s26, 24
; SI-NEXT:    s_and_b32 s5, s5, 0xffff
; SI-NEXT:    s_or_b32 s7, s9, s7
; SI-NEXT:    s_or_b32 s5, s5, s7
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_mov_b32_e32 v1, s5
; SI-NEXT:    s_and_b32 s5, s21, 0xff
; SI-NEXT:    s_lshl_b32 s7, s78, 8
; SI-NEXT:    s_or_b32 s5, s5, s7
; SI-NEXT:    s_and_b32 s7, s77, 0xff
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_lshl_b32 s9, s76, 24
; SI-NEXT:    s_and_b32 s5, s5, 0xffff
; SI-NEXT:    s_or_b32 s7, s9, s7
; SI-NEXT:    s_or_b32 s5, s5, s7
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_mov_b32_e32 v1, s5
; SI-NEXT:    s_and_b32 s5, s22, 0xff
; SI-NEXT:    s_lshl_b32 s7, s14, 8
; SI-NEXT:    s_or_b32 s5, s5, s7
; SI-NEXT:    s_and_b32 s7, s12, 0xff
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_lshl_b32 s9, s10, 24
; SI-NEXT:    s_and_b32 s5, s5, 0xffff
; SI-NEXT:    s_or_b32 s7, s9, s7
; SI-NEXT:    s_or_b32 s5, s5, s7
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_mov_b32_e32 v1, s5
; SI-NEXT:    s_and_b32 s5, s23, 0xff
; SI-NEXT:    s_lshl_b32 s7, s75, 8
; SI-NEXT:    s_or_b32 s5, s5, s7
; SI-NEXT:    s_and_b32 s7, s74, 0xff
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_lshl_b32 s9, s73, 24
; SI-NEXT:    s_and_b32 s5, s5, 0xffff
; SI-NEXT:    s_or_b32 s7, s9, s7
; SI-NEXT:    s_or_b32 s5, s5, s7
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_mov_b32_e32 v1, s5
; SI-NEXT:    s_and_b32 s5, s24, 0xff
; SI-NEXT:    s_lshl_b32 s7, s8, 8
; SI-NEXT:    s_and_b32 s6, s6, 0xff
; SI-NEXT:    s_or_b32 s5, s5, s7
; SI-NEXT:    s_lshl_b32 s6, s6, 16
; SI-NEXT:    s_lshl_b32 s4, s4, 24
; SI-NEXT:    s_and_b32 s5, s5, 0xffff
; SI-NEXT:    s_or_b32 s4, s4, s6
; SI-NEXT:    s_or_b32 s4, s5, s4
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_mov_b32_e32 v1, s4
; SI-NEXT:    s_and_b32 s4, s25, 0xff
; SI-NEXT:    s_lshl_b32 s5, s72, 8
; SI-NEXT:    s_or_b32 s4, s4, s5
; SI-NEXT:    s_and_b32 s5, s63, 0xff
; SI-NEXT:    s_lshl_b32 s5, s5, 16
; SI-NEXT:    s_lshl_b32 s6, s62, 24
; SI-NEXT:    s_and_b32 s4, s4, 0xffff
; SI-NEXT:    s_or_b32 s5, s6, s5
; SI-NEXT:    s_or_b32 s4, s4, s5
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_mov_b32_e32 v1, s4
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v10i32_to_v40i8_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc0 .LBB13_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    s_lshr_b32 s14, s25, 24
; VI-NEXT:    s_lshr_b32 s15, s25, 16
; VI-NEXT:    s_lshr_b32 s26, s25, 8
; VI-NEXT:    s_lshr_b32 s27, s24, 16
; VI-NEXT:    s_lshr_b32 s28, s24, 8
; VI-NEXT:    s_lshr_b32 s29, s23, 24
; VI-NEXT:    s_lshr_b32 s40, s23, 16
; VI-NEXT:    s_lshr_b32 s41, s23, 8
; VI-NEXT:    s_lshr_b32 s42, s22, 16
; VI-NEXT:    s_lshr_b32 s43, s22, 8
; VI-NEXT:    s_lshr_b32 s44, s21, 24
; VI-NEXT:    s_lshr_b32 s45, s21, 16
; VI-NEXT:    s_lshr_b32 s46, s21, 8
; VI-NEXT:    s_lshr_b32 s47, s20, 16
; VI-NEXT:    s_lshr_b32 s56, s20, 8
; VI-NEXT:    s_lshr_b32 s57, s19, 24
; VI-NEXT:    s_lshr_b32 s58, s19, 16
; VI-NEXT:    s_lshr_b32 s59, s19, 8
; VI-NEXT:    s_lshr_b32 s60, s18, 16
; VI-NEXT:    s_lshr_b32 s61, s18, 8
; VI-NEXT:    s_lshr_b32 s62, s17, 24
; VI-NEXT:    s_lshr_b32 s63, s17, 16
; VI-NEXT:    s_lshr_b32 s72, s17, 8
; VI-NEXT:    s_lshr_b32 s73, s16, 16
; VI-NEXT:    s_lshr_b32 s74, s16, 8
; VI-NEXT:    s_lshr_b64 s[4:5], s[24:25], 24
; VI-NEXT:    s_lshr_b64 s[6:7], s[22:23], 24
; VI-NEXT:    s_lshr_b64 s[8:9], s[20:21], 24
; VI-NEXT:    s_lshr_b64 s[10:11], s[18:19], 24
; VI-NEXT:    s_lshr_b64 s[12:13], s[16:17], 24
; VI-NEXT:    s_branch .LBB13_3
; VI-NEXT:  .LBB13_2: ; %cmp.true
; VI-NEXT:    s_add_i32 s17, s17, 3
; VI-NEXT:    s_add_i32 s16, s16, 3
; VI-NEXT:    s_add_i32 s19, s19, 3
; VI-NEXT:    s_add_i32 s18, s18, 3
; VI-NEXT:    s_add_i32 s21, s21, 3
; VI-NEXT:    s_add_i32 s20, s20, 3
; VI-NEXT:    s_add_i32 s23, s23, 3
; VI-NEXT:    s_add_i32 s22, s22, 3
; VI-NEXT:    s_add_i32 s25, s25, 3
; VI-NEXT:    s_add_i32 s24, s24, 3
; VI-NEXT:    s_lshr_b64 s[4:5], s[24:25], 24
; VI-NEXT:    s_lshr_b64 s[6:7], s[22:23], 24
; VI-NEXT:    s_lshr_b64 s[8:9], s[20:21], 24
; VI-NEXT:    s_lshr_b64 s[10:11], s[18:19], 24
; VI-NEXT:    s_lshr_b64 s[12:13], s[16:17], 24
; VI-NEXT:    s_lshr_b32 s14, s25, 24
; VI-NEXT:    s_lshr_b32 s15, s25, 16
; VI-NEXT:    s_lshr_b32 s26, s25, 8
; VI-NEXT:    s_lshr_b32 s27, s24, 16
; VI-NEXT:    s_lshr_b32 s28, s24, 8
; VI-NEXT:    s_lshr_b32 s29, s23, 24
; VI-NEXT:    s_lshr_b32 s40, s23, 16
; VI-NEXT:    s_lshr_b32 s41, s23, 8
; VI-NEXT:    s_lshr_b32 s42, s22, 16
; VI-NEXT:    s_lshr_b32 s43, s22, 8
; VI-NEXT:    s_lshr_b32 s44, s21, 24
; VI-NEXT:    s_lshr_b32 s45, s21, 16
; VI-NEXT:    s_lshr_b32 s46, s21, 8
; VI-NEXT:    s_lshr_b32 s47, s20, 16
; VI-NEXT:    s_lshr_b32 s56, s20, 8
; VI-NEXT:    s_lshr_b32 s57, s19, 24
; VI-NEXT:    s_lshr_b32 s58, s19, 16
; VI-NEXT:    s_lshr_b32 s59, s19, 8
; VI-NEXT:    s_lshr_b32 s60, s18, 16
; VI-NEXT:    s_lshr_b32 s61, s18, 8
; VI-NEXT:    s_lshr_b32 s62, s17, 24
; VI-NEXT:    s_lshr_b32 s63, s17, 16
; VI-NEXT:    s_lshr_b32 s72, s17, 8
; VI-NEXT:    s_lshr_b32 s73, s16, 16
; VI-NEXT:    s_lshr_b32 s74, s16, 8
; VI-NEXT:  .LBB13_3: ; %end
; VI-NEXT:    v_mov_b32_e32 v2, 0xc0c0004
; VI-NEXT:    v_mov_b32_e32 v3, s12
; VI-NEXT:    v_mov_b32_e32 v1, s74
; VI-NEXT:    v_perm_b32 v3, s73, v3, v2
; VI-NEXT:    v_perm_b32 v1, s16, v1, v2
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_e32 v1, v1, v3
; VI-NEXT:    v_mov_b32_e32 v3, s62
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT:    v_mov_b32_e32 v1, s72
; VI-NEXT:    v_perm_b32 v3, s63, v3, v2
; VI-NEXT:    v_perm_b32 v1, s17, v1, v2
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_e32 v1, v1, v3
; VI-NEXT:    v_mov_b32_e32 v3, s10
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
; VI-NEXT:    v_mov_b32_e32 v1, s61
; VI-NEXT:    v_perm_b32 v3, s60, v3, v2
; VI-NEXT:    v_perm_b32 v1, s18, v1, v2
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_e32 v1, v1, v3
; VI-NEXT:    v_mov_b32_e32 v3, s57
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; VI-NEXT:    v_mov_b32_e32 v1, s59
; VI-NEXT:    v_perm_b32 v3, s58, v3, v2
; VI-NEXT:    v_perm_b32 v1, s19, v1, v2
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_e32 v1, v1, v3
; VI-NEXT:    v_mov_b32_e32 v3, s8
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; VI-NEXT:    v_mov_b32_e32 v1, s56
; VI-NEXT:    v_perm_b32 v3, s47, v3, v2
; VI-NEXT:    v_perm_b32 v1, s20, v1, v2
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_e32 v1, v1, v3
; VI-NEXT:    v_mov_b32_e32 v3, s44
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; VI-NEXT:    v_mov_b32_e32 v1, s46
; VI-NEXT:    v_perm_b32 v3, s45, v3, v2
; VI-NEXT:    v_perm_b32 v1, s21, v1, v2
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_e32 v1, v1, v3
; VI-NEXT:    v_mov_b32_e32 v3, s6
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; VI-NEXT:    v_mov_b32_e32 v1, s43
; VI-NEXT:    v_perm_b32 v3, s42, v3, v2
; VI-NEXT:    v_perm_b32 v1, s22, v1, v2
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_e32 v1, v1, v3
; VI-NEXT:    v_mov_b32_e32 v3, s29
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; VI-NEXT:    v_mov_b32_e32 v1, s41
; VI-NEXT:    v_perm_b32 v3, s40, v3, v2
; VI-NEXT:    v_perm_b32 v1, s23, v1, v2
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_e32 v1, v1, v3
; VI-NEXT:    v_mov_b32_e32 v3, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; VI-NEXT:    v_mov_b32_e32 v1, s28
; VI-NEXT:    v_perm_b32 v3, s27, v3, v2
; VI-NEXT:    v_perm_b32 v1, s24, v1, v2
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_e32 v1, v1, v3
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; VI-NEXT:    v_mov_b32_e32 v1, s26
; VI-NEXT:    v_mov_b32_e32 v3, s14
; VI-NEXT:    v_perm_b32 v1, s25, v1, v2
; VI-NEXT:    v_perm_b32 v2, s15, v3, v2
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v10i32_to_v40i8_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc0 .LBB13_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    s_lshr_b32 s14, s25, 24
; GFX9-NEXT:    s_lshr_b32 s15, s25, 16
; GFX9-NEXT:    s_lshr_b32 s26, s25, 8
; GFX9-NEXT:    s_lshr_b32 s27, s24, 16
; GFX9-NEXT:    s_lshr_b32 s28, s24, 8
; GFX9-NEXT:    s_lshr_b32 s29, s23, 24
; GFX9-NEXT:    s_lshr_b32 s40, s23, 16
; GFX9-NEXT:    s_lshr_b32 s41, s23, 8
; GFX9-NEXT:    s_lshr_b32 s42, s22, 16
; GFX9-NEXT:    s_lshr_b32 s43, s22, 8
; GFX9-NEXT:    s_lshr_b32 s44, s21, 24
; GFX9-NEXT:    s_lshr_b32 s45, s21, 16
; GFX9-NEXT:    s_lshr_b32 s46, s21, 8
; GFX9-NEXT:    s_lshr_b32 s47, s20, 16
; GFX9-NEXT:    s_lshr_b32 s56, s20, 8
; GFX9-NEXT:    s_lshr_b32 s57, s19, 24
; GFX9-NEXT:    s_lshr_b32 s58, s19, 16
; GFX9-NEXT:    s_lshr_b32 s59, s19, 8
; GFX9-NEXT:    s_lshr_b32 s60, s18, 16
; GFX9-NEXT:    s_lshr_b32 s61, s18, 8
; GFX9-NEXT:    s_lshr_b32 s62, s17, 24
; GFX9-NEXT:    s_lshr_b32 s63, s17, 16
; GFX9-NEXT:    s_lshr_b32 s72, s17, 8
; GFX9-NEXT:    s_lshr_b32 s73, s16, 16
; GFX9-NEXT:    s_lshr_b32 s74, s16, 8
; GFX9-NEXT:    s_lshr_b64 s[4:5], s[24:25], 24
; GFX9-NEXT:    s_lshr_b64 s[6:7], s[22:23], 24
; GFX9-NEXT:    s_lshr_b64 s[8:9], s[20:21], 24
; GFX9-NEXT:    s_lshr_b64 s[10:11], s[18:19], 24
; GFX9-NEXT:    s_lshr_b64 s[12:13], s[16:17], 24
; GFX9-NEXT:    s_branch .LBB13_3
; GFX9-NEXT:  .LBB13_2: ; %cmp.true
; GFX9-NEXT:    s_add_i32 s17, s17, 3
; GFX9-NEXT:    s_add_i32 s16, s16, 3
; GFX9-NEXT:    s_add_i32 s19, s19, 3
; GFX9-NEXT:    s_add_i32 s18, s18, 3
; GFX9-NEXT:    s_add_i32 s21, s21, 3
; GFX9-NEXT:    s_add_i32 s20, s20, 3
; GFX9-NEXT:    s_add_i32 s23, s23, 3
; GFX9-NEXT:    s_add_i32 s22, s22, 3
; GFX9-NEXT:    s_add_i32 s25, s25, 3
; GFX9-NEXT:    s_add_i32 s24, s24, 3
; GFX9-NEXT:    s_lshr_b64 s[4:5], s[24:25], 24
; GFX9-NEXT:    s_lshr_b64 s[6:7], s[22:23], 24
; GFX9-NEXT:    s_lshr_b64 s[8:9], s[20:21], 24
; GFX9-NEXT:    s_lshr_b64 s[10:11], s[18:19], 24
; GFX9-NEXT:    s_lshr_b64 s[12:13], s[16:17], 24
; GFX9-NEXT:    s_lshr_b32 s14, s25, 24
; GFX9-NEXT:    s_lshr_b32 s15, s25, 16
; GFX9-NEXT:    s_lshr_b32 s26, s25, 8
; GFX9-NEXT:    s_lshr_b32 s27, s24, 16
; GFX9-NEXT:    s_lshr_b32 s28, s24, 8
; GFX9-NEXT:    s_lshr_b32 s29, s23, 24
; GFX9-NEXT:    s_lshr_b32 s40, s23, 16
; GFX9-NEXT:    s_lshr_b32 s41, s23, 8
; GFX9-NEXT:    s_lshr_b32 s42, s22, 16
; GFX9-NEXT:    s_lshr_b32 s43, s22, 8
; GFX9-NEXT:    s_lshr_b32 s44, s21, 24
; GFX9-NEXT:    s_lshr_b32 s45, s21, 16
; GFX9-NEXT:    s_lshr_b32 s46, s21, 8
; GFX9-NEXT:    s_lshr_b32 s47, s20, 16
; GFX9-NEXT:    s_lshr_b32 s56, s20, 8
; GFX9-NEXT:    s_lshr_b32 s57, s19, 24
; GFX9-NEXT:    s_lshr_b32 s58, s19, 16
; GFX9-NEXT:    s_lshr_b32 s59, s19, 8
; GFX9-NEXT:    s_lshr_b32 s60, s18, 16
; GFX9-NEXT:    s_lshr_b32 s61, s18, 8
; GFX9-NEXT:    s_lshr_b32 s62, s17, 24
; GFX9-NEXT:    s_lshr_b32 s63, s17, 16
; GFX9-NEXT:    s_lshr_b32 s72, s17, 8
; GFX9-NEXT:    s_lshr_b32 s73, s16, 16
; GFX9-NEXT:    s_lshr_b32 s74, s16, 8
; GFX9-NEXT:  .LBB13_3: ; %end
; GFX9-NEXT:    v_mov_b32_e32 v2, 0xc0c0004
; GFX9-NEXT:    v_mov_b32_e32 v3, s12
; GFX9-NEXT:    v_mov_b32_e32 v1, s74
; GFX9-NEXT:    v_perm_b32 v3, s73, v3, v2
; GFX9-NEXT:    v_perm_b32 v1, s16, v1, v2
; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
; GFX9-NEXT:    v_mov_b32_e32 v3, s62
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen
; GFX9-NEXT:    v_mov_b32_e32 v1, s72
; GFX9-NEXT:    v_perm_b32 v3, s63, v3, v2
; GFX9-NEXT:    v_perm_b32 v1, s17, v1, v2
; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
; GFX9-NEXT:    v_mov_b32_e32 v3, s10
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT:    v_mov_b32_e32 v1, s61
; GFX9-NEXT:    v_perm_b32 v3, s60, v3, v2
; GFX9-NEXT:    v_perm_b32 v1, s18, v1, v2
; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
; GFX9-NEXT:    v_mov_b32_e32 v3, s57
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT:    v_mov_b32_e32 v1, s59
; GFX9-NEXT:    v_perm_b32 v3, s58, v3, v2
; GFX9-NEXT:    v_perm_b32 v1, s19, v1, v2
; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
; GFX9-NEXT:    v_mov_b32_e32 v3, s8
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; GFX9-NEXT:    v_mov_b32_e32 v1, s56
; GFX9-NEXT:    v_perm_b32 v3, s47, v3, v2
; GFX9-NEXT:    v_perm_b32 v1, s20, v1, v2
; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
; GFX9-NEXT:    v_mov_b32_e32 v3, s44
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT:    v_mov_b32_e32 v1, s46
; GFX9-NEXT:    v_perm_b32 v3, s45, v3, v2
; GFX9-NEXT:    v_perm_b32 v1, s21, v1, v2
; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
; GFX9-NEXT:    v_mov_b32_e32 v3, s6
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; GFX9-NEXT:    v_mov_b32_e32 v1, s43
; GFX9-NEXT:    v_perm_b32 v3, s42, v3, v2
; GFX9-NEXT:    v_perm_b32 v1, s22, v1, v2
; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
; GFX9-NEXT:    v_mov_b32_e32 v3, s29
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT:    v_mov_b32_e32 v1, s41
; GFX9-NEXT:    v_perm_b32 v3, s40, v3, v2
; GFX9-NEXT:    v_perm_b32 v1, s23, v1, v2
; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
; GFX9-NEXT:    v_mov_b32_e32 v3, s4
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; GFX9-NEXT:    v_mov_b32_e32 v1, s28
; GFX9-NEXT:    v_perm_b32 v3, s27, v3, v2
; GFX9-NEXT:    v_perm_b32 v1, s24, v1, v2
; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT:    v_mov_b32_e32 v1, s26
; GFX9-NEXT:    v_mov_b32_e32 v3, s14
; GFX9-NEXT:    v_perm_b32 v1, s25, v1, v2
; GFX9-NEXT:    v_perm_b32 v2, s15, v3, v2
; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v2
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v10i32_to_v40i8_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc0 .LBB13_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-NEXT:    s_lshr_b32 s14, s21, 24
; GFX11-NEXT:    s_lshr_b32 s22, s21, 16
; GFX11-NEXT:    s_lshr_b32 s15, s21, 8
; GFX11-NEXT:    s_lshr_b32 s24, s20, 16
; GFX11-NEXT:    s_lshr_b32 s23, s20, 8
; GFX11-NEXT:    s_lshr_b32 s26, s19, 24
; GFX11-NEXT:    s_lshr_b32 s27, s19, 16
; GFX11-NEXT:    s_lshr_b32 s25, s19, 8
; GFX11-NEXT:    s_lshr_b32 s28, s18, 16
; GFX11-NEXT:    s_lshr_b32 s29, s18, 8
; GFX11-NEXT:    s_lshr_b32 s40, s17, 24
; GFX11-NEXT:    s_lshr_b32 s42, s17, 16
; GFX11-NEXT:    s_lshr_b32 s41, s17, 8
; GFX11-NEXT:    s_lshr_b32 s43, s16, 16
; GFX11-NEXT:    s_lshr_b32 s44, s16, 8
; GFX11-NEXT:    s_lshr_b32 s45, s3, 24
; GFX11-NEXT:    s_lshr_b32 s46, s3, 16
; GFX11-NEXT:    s_lshr_b32 s47, s3, 8
; GFX11-NEXT:    s_lshr_b32 s56, s2, 16
; GFX11-NEXT:    s_lshr_b32 s57, s2, 8
; GFX11-NEXT:    s_lshr_b32 s58, s1, 24
; GFX11-NEXT:    s_lshr_b32 s59, s1, 16
; GFX11-NEXT:    s_lshr_b32 s60, s1, 8
; GFX11-NEXT:    s_lshr_b32 s61, s0, 16
; GFX11-NEXT:    s_lshr_b32 s62, s0, 8
; GFX11-NEXT:    s_lshr_b64 s[4:5], s[20:21], 24
; GFX11-NEXT:    s_lshr_b64 s[6:7], s[18:19], 24
; GFX11-NEXT:    s_lshr_b64 s[8:9], s[16:17], 24
; GFX11-NEXT:    s_lshr_b64 s[10:11], s[2:3], 24
; GFX11-NEXT:    s_lshr_b64 s[12:13], s[0:1], 24
; GFX11-NEXT:    s_branch .LBB13_3
; GFX11-NEXT:  .LBB13_2: ; %cmp.true
; GFX11-NEXT:    s_add_i32 s1, s1, 3
; GFX11-NEXT:    s_add_i32 s0, s0, 3
; GFX11-NEXT:    s_add_i32 s3, s3, 3
; GFX11-NEXT:    s_add_i32 s2, s2, 3
; GFX11-NEXT:    s_add_i32 s17, s17, 3
; GFX11-NEXT:    s_add_i32 s16, s16, 3
; GFX11-NEXT:    s_add_i32 s19, s19, 3
; GFX11-NEXT:    s_add_i32 s21, s21, 3
; GFX11-NEXT:    s_add_i32 s20, s20, 3
; GFX11-NEXT:    s_add_i32 s18, s18, 3
; GFX11-NEXT:    s_lshr_b64 s[4:5], s[20:21], 24
; GFX11-NEXT:    s_lshr_b64 s[6:7], s[18:19], 24
; GFX11-NEXT:    s_lshr_b64 s[8:9], s[16:17], 24
; GFX11-NEXT:    s_lshr_b64 s[10:11], s[2:3], 24
; GFX11-NEXT:    s_lshr_b64 s[12:13], s[0:1], 24
; GFX11-NEXT:    s_lshr_b32 s14, s21, 24
; GFX11-NEXT:    s_lshr_b32 s22, s21, 16
; GFX11-NEXT:    s_lshr_b32 s15, s21, 8
; GFX11-NEXT:    s_lshr_b32 s24, s20, 16
; GFX11-NEXT:    s_lshr_b32 s23, s20, 8
; GFX11-NEXT:    s_lshr_b32 s26, s19, 24
; GFX11-NEXT:    s_lshr_b32 s27, s19, 16
; GFX11-NEXT:    s_lshr_b32 s25, s19, 8
; GFX11-NEXT:    s_lshr_b32 s28, s18, 16
; GFX11-NEXT:    s_lshr_b32 s29, s18, 8
; GFX11-NEXT:    s_lshr_b32 s40, s17, 24
; GFX11-NEXT:    s_lshr_b32 s42, s17, 16
; GFX11-NEXT:    s_lshr_b32 s41, s17, 8
; GFX11-NEXT:    s_lshr_b32 s43, s16, 16
; GFX11-NEXT:    s_lshr_b32 s44, s16, 8
; GFX11-NEXT:    s_lshr_b32 s45, s3, 24
; GFX11-NEXT:    s_lshr_b32 s46, s3, 16
; GFX11-NEXT:    s_lshr_b32 s47, s3, 8
; GFX11-NEXT:    s_lshr_b32 s56, s2, 16
; GFX11-NEXT:    s_lshr_b32 s57, s2, 8
; GFX11-NEXT:    s_lshr_b32 s58, s1, 24
; GFX11-NEXT:    s_lshr_b32 s59, s1, 16
; GFX11-NEXT:    s_lshr_b32 s60, s1, 8
; GFX11-NEXT:    s_lshr_b32 s61, s0, 16
; GFX11-NEXT:    s_lshr_b32 s62, s0, 8
; GFX11-NEXT:  .LBB13_3: ; %end
; GFX11-NEXT:    v_mov_b32_e32 v6, 0xc0c0004
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_perm_b32 v7, s56, s10, v6
; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; GFX11-NEXT:    v_perm_b32 v2, s61, s12, v6
; GFX11-NEXT:    v_perm_b32 v4, s59, s58, v6
; GFX11-NEXT:    v_perm_b32 v9, s46, s45, v6
; GFX11-NEXT:    v_perm_b32 v11, s43, s8, v6
; GFX11-NEXT:    v_perm_b32 v1, s0, s62, v6
; GFX11-NEXT:    v_perm_b32 v3, s1, s60, v6
; GFX11-NEXT:    v_perm_b32 v5, s2, s57, v6
; GFX11-NEXT:    v_perm_b32 v8, s3, s47, v6
; GFX11-NEXT:    v_perm_b32 v10, s16, s44, v6
; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; GFX11-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; GFX11-NEXT:    v_perm_b32 v12, s24, s4, v6
; GFX11-NEXT:    v_or_b32_e32 v1, v1, v2
; GFX11-NEXT:    v_or_b32_e32 v2, v3, v4
; GFX11-NEXT:    v_or_b32_e32 v3, v5, v7
; GFX11-NEXT:    v_perm_b32 v7, s42, s40, v6
; GFX11-NEXT:    v_or_b32_e32 v4, v8, v9
; GFX11-NEXT:    v_or_b32_e32 v5, v10, v11
; GFX11-NEXT:    v_perm_b32 v8, s28, s6, v6
; GFX11-NEXT:    v_perm_b32 v11, s27, s26, v6
; GFX11-NEXT:    v_perm_b32 v14, s22, s14, v6
; GFX11-NEXT:    v_perm_b32 v9, s17, s41, v6
; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; GFX11-NEXT:    v_perm_b32 v10, s18, s29, v6
; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; GFX11-NEXT:    v_perm_b32 v13, s19, s25, v6
; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; GFX11-NEXT:    v_perm_b32 v15, s20, s23, v6
; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
; GFX11-NEXT:    v_perm_b32 v16, s21, s15, v6
; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
; GFX11-NEXT:    v_or_b32_e32 v6, v9, v7
; GFX11-NEXT:    v_or_b32_e32 v7, v10, v8
; GFX11-NEXT:    v_or_b32_e32 v8, v13, v11
; GFX11-NEXT:    v_or_b32_e32 v9, v15, v12
; GFX11-NEXT:    v_or_b32_e32 v10, v16, v14
; GFX11-NEXT:    s_clause 0x2
; GFX11-NEXT:    scratch_store_b128 v0, v[1:4], off
; GFX11-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
; GFX11-NEXT:    scratch_store_b64 v0, v[9:10], off offset:32
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <10 x i32> %a, splat (i32 3)
  %a2 = bitcast <10 x i32> %a1 to <40 x i8>
  br label %end

cmp.false:
  %a3 = bitcast <10 x i32> %a to <40 x i8>
  br label %end

end:
  %phi = phi <40 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <40 x i8> %phi
}

define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v40i8_to_v10i32:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; SI-NEXT:    v_mov_b32_e32 v35, v8
; SI-NEXT:    v_mov_b32_e32 v34, v6
; SI-NEXT:    v_mov_b32_e32 v33, v4
; SI-NEXT:    v_mov_b32_e32 v32, v2
; SI-NEXT:    v_mov_b32_e32 v31, v0
; SI-NEXT:    buffer_load_dword v0, off, s[0:3], s32
; SI-NEXT:    buffer_load_dword v2, off, s[0:3], s32 offset:36
; SI-NEXT:    buffer_load_dword v4, off, s[0:3], s32 offset:32
; SI-NEXT:    buffer_load_dword v36, off, s[0:3], s32 offset:28
; SI-NEXT:    buffer_load_dword v6, off, s[0:3], s32 offset:24
; SI-NEXT:    buffer_load_dword v8, off, s[0:3], s32 offset:8
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    buffer_load_dword v44, off, s[0:3], s32 offset:16
; SI-NEXT:    buffer_load_dword v37, off, s[0:3], s32 offset:20
; SI-NEXT:    buffer_load_dword v38, off, s[0:3], s32 offset:12
; SI-NEXT:    buffer_load_dword v39, off, s[0:3], s32 offset:4
; SI-NEXT:    v_lshlrev_b32_e32 v43, 8, v1
; SI-NEXT:    v_lshlrev_b32_e32 v42, 24, v3
; SI-NEXT:    v_lshlrev_b32_e32 v41, 8, v5
; SI-NEXT:    v_lshlrev_b32_e32 v40, 24, v7
; SI-NEXT:    v_lshlrev_b32_e32 v55, 8, v9
; SI-NEXT:    v_lshlrev_b32_e32 v54, 24, v11
; SI-NEXT:    v_lshlrev_b32_e32 v53, 8, v13
; SI-NEXT:    v_lshlrev_b32_e32 v52, 24, v15
; SI-NEXT:    v_lshlrev_b32_e32 v51, 8, v17
; SI-NEXT:    v_lshlrev_b32_e32 v50, 24, v19
; SI-NEXT:    v_lshlrev_b32_e32 v49, 8, v21
; SI-NEXT:    v_lshlrev_b32_e32 v48, 24, v23
; SI-NEXT:    v_lshlrev_b32_e32 v25, 8, v25
; SI-NEXT:    v_lshlrev_b32_e32 v23, 24, v27
; SI-NEXT:    v_lshlrev_b32_e32 v21, 8, v29
; SI-NEXT:    s_waitcnt vmcnt(9)
; SI-NEXT:    v_lshlrev_b32_e32 v19, 24, v0
; SI-NEXT:    s_waitcnt vmcnt(8)
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
; SI-NEXT:    s_waitcnt vmcnt(7)
; SI-NEXT:    v_lshlrev_b32_e32 v11, 24, v4
; SI-NEXT:    s_waitcnt vmcnt(5)
; SI-NEXT:    v_lshlrev_b32_e32 v13, 8, v6
; SI-NEXT:    s_waitcnt vmcnt(4)
; SI-NEXT:    v_lshlrev_b32_e32 v17, 8, v8
; SI-NEXT:    s_waitcnt vmcnt(3)
; SI-NEXT:    v_lshlrev_b32_e32 v15, 24, v44
; SI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB14_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    v_and_b32_e32 v0, 0xff, v31
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v32
; SI-NEXT:    v_or_b32_e32 v0, v0, v43
; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_or_b32_e32 v1, v42, v1
; SI-NEXT:    v_or_b32_e32 v0, v0, v1
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v33
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v34
; SI-NEXT:    v_or_b32_e32 v1, v1, v41
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v40, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v35
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v10
; SI-NEXT:    v_or_b32_e32 v2, v2, v55
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    v_or_b32_e32 v3, v54, v3
; SI-NEXT:    v_or_b32_e32 v2, v2, v3
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v12
; SI-NEXT:    v_and_b32_e32 v4, 0xff, v14
; SI-NEXT:    v_or_b32_e32 v3, v3, v53
; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT:    v_or_b32_e32 v4, v52, v4
; SI-NEXT:    v_or_b32_e32 v3, v3, v4
; SI-NEXT:    v_and_b32_e32 v4, 0xff, v16
; SI-NEXT:    v_and_b32_e32 v5, 0xff, v18
; SI-NEXT:    v_or_b32_e32 v4, v4, v51
; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT:    v_or_b32_e32 v5, v50, v5
; SI-NEXT:    v_or_b32_e32 v4, v4, v5
; SI-NEXT:    v_and_b32_e32 v5, 0xff, v20
; SI-NEXT:    v_and_b32_e32 v6, 0xff, v22
; SI-NEXT:    v_or_b32_e32 v5, v5, v49
; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT:    v_or_b32_e32 v6, v48, v6
; SI-NEXT:    v_or_b32_e32 v5, v5, v6
; SI-NEXT:    v_and_b32_e32 v6, 0xff, v24
; SI-NEXT:    v_and_b32_e32 v7, 0xff, v26
; SI-NEXT:    v_or_b32_e32 v6, v6, v25
; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT:    v_or_b32_e32 v7, v23, v7
; SI-NEXT:    v_or_b32_e32 v6, v6, v7
; SI-NEXT:    v_and_b32_e32 v7, 0xff, v28
; SI-NEXT:    v_and_b32_e32 v8, 0xff, v30
; SI-NEXT:    v_or_b32_e32 v7, v7, v21
; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT:    v_or_b32_e32 v8, v19, v8
; SI-NEXT:    v_or_b32_e32 v7, v7, v8
; SI-NEXT:    s_waitcnt vmcnt(0)
; SI-NEXT:    v_and_b32_e32 v8, 0xff, v39
; SI-NEXT:    v_and_b32_e32 v9, 0xff, v38
; SI-NEXT:    v_or_b32_e32 v8, v8, v17
; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT:    v_or_b32_e32 v9, v15, v9
; SI-NEXT:    v_or_b32_e32 v8, v8, v9
; SI-NEXT:    v_and_b32_e32 v9, 0xff, v37
; SI-NEXT:    v_and_b32_e32 v10, 0xff, v36
; SI-NEXT:    v_or_b32_e32 v9, v9, v13
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT:    v_or_b32_e32 v10, v11, v10
; SI-NEXT:    v_or_b32_e32 v9, v9, v10
; SI-NEXT:    ; implicit-def: $vgpr31
; SI-NEXT:    ; implicit-def: $vgpr32
; SI-NEXT:    ; implicit-def: $vgpr33
; SI-NEXT:    ; implicit-def: $vgpr34
; SI-NEXT:    ; implicit-def: $vgpr35
; SI-NEXT:    ; implicit-def: $vgpr10
; SI-NEXT:    ; implicit-def: $vgpr12
; SI-NEXT:    ; implicit-def: $vgpr14
; SI-NEXT:    ; implicit-def: $vgpr16
; SI-NEXT:    ; implicit-def: $vgpr18
; SI-NEXT:    ; implicit-def: $vgpr20
; SI-NEXT:    ; implicit-def: $vgpr22
; SI-NEXT:    ; implicit-def: $vgpr24
; SI-NEXT:    ; implicit-def: $vgpr26
; SI-NEXT:    ; implicit-def: $vgpr28
; SI-NEXT:    ; implicit-def: $vgpr30
; SI-NEXT:    ; implicit-def: $vgpr39
; SI-NEXT:    ; implicit-def: $vgpr38
; SI-NEXT:    ; implicit-def: $vgpr37
; SI-NEXT:    ; implicit-def: $vgpr36
; SI-NEXT:    ; implicit-def: $vgpr43
; SI-NEXT:    ; implicit-def: $vgpr42
; SI-NEXT:    ; implicit-def: $vgpr41
; SI-NEXT:    ; implicit-def: $vgpr40
; SI-NEXT:    ; implicit-def: $vgpr55
; SI-NEXT:    ; implicit-def: $vgpr54
; SI-NEXT:    ; implicit-def: $vgpr53
; SI-NEXT:    ; implicit-def: $vgpr52
; SI-NEXT:    ; implicit-def: $vgpr51
; SI-NEXT:    ; implicit-def: $vgpr50
; SI-NEXT:    ; implicit-def: $vgpr49
; SI-NEXT:    ; implicit-def: $vgpr48
; SI-NEXT:    ; implicit-def: $vgpr25
; SI-NEXT:    ; implicit-def: $vgpr23
; SI-NEXT:    ; implicit-def: $vgpr21
; SI-NEXT:    ; implicit-def: $vgpr19
; SI-NEXT:    ; implicit-def: $vgpr17
; SI-NEXT:    ; implicit-def: $vgpr15
; SI-NEXT:    ; implicit-def: $vgpr13
; SI-NEXT:    ; implicit-def: $vgpr11
; SI-NEXT:  .LBB14_2: ; %Flow
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB14_4
; SI-NEXT:  ; %bb.3: ; %cmp.true
; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v31
; SI-NEXT:    v_and_b32_e32 v0, 0xff, v0
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v32
; SI-NEXT:    v_or_b32_e32 v0, v43, v0
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1
; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x300, v0
; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_or_b32_e32 v1, v42, v1
; SI-NEXT:    v_or_b32_e32 v0, v1, v0
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v33
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1
; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v34
; SI-NEXT:    s_movk_i32 s6, 0x300
; SI-NEXT:    v_or_b32_e32 v1, v41, v1
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v2
; SI-NEXT:    v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v40, v2
; SI-NEXT:    v_or_b32_e32 v1, v2, v1
; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v35
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v2
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v10
; SI-NEXT:    v_or_b32_e32 v2, v55, v2
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v3
; SI-NEXT:    v_add_i32_e32 v2, vcc, s6, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    v_or_b32_e32 v3, v54, v3
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v12
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v3
; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v14
; SI-NEXT:    v_or_b32_e32 v3, v53, v3
; SI-NEXT:    v_and_b32_e32 v4, 0xff, v4
; SI-NEXT:    v_add_i32_e32 v3, vcc, s6, v3
; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT:    v_or_b32_e32 v4, v52, v4
; SI-NEXT:    v_or_b32_e32 v3, v4, v3
; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v16
; SI-NEXT:    v_and_b32_e32 v4, 0xff, v4
; SI-NEXT:    v_add_i32_e32 v5, vcc, 3, v18
; SI-NEXT:    v_or_b32_e32 v4, v51, v4
; SI-NEXT:    v_and_b32_e32 v5, 0xff, v5
; SI-NEXT:    v_add_i32_e32 v4, vcc, s6, v4
; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT:    v_or_b32_e32 v5, v50, v5
; SI-NEXT:    v_or_b32_e32 v4, v5, v4
; SI-NEXT:    v_add_i32_e32 v5, vcc, 3, v20
; SI-NEXT:    v_and_b32_e32 v5, 0xff, v5
; SI-NEXT:    v_add_i32_e32 v6, vcc, 3, v22
; SI-NEXT:    v_or_b32_e32 v5, v49, v5
; SI-NEXT:    v_and_b32_e32 v6, 0xff, v6
; SI-NEXT:    v_add_i32_e32 v5, vcc, s6, v5
; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT:    v_or_b32_e32 v6, v48, v6
; SI-NEXT:    v_or_b32_e32 v5, v6, v5
; SI-NEXT:    v_add_i32_e32 v6, vcc, 3, v24
; SI-NEXT:    v_and_b32_e32 v6, 0xff, v6
; SI-NEXT:    v_add_i32_e32 v7, vcc, 3, v26
; SI-NEXT:    v_or_b32_e32 v6, v25, v6
; SI-NEXT:    v_and_b32_e32 v7, 0xff, v7
; SI-NEXT:    v_add_i32_e32 v6, vcc, s6, v6
; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT:    v_or_b32_e32 v7, v23, v7
; SI-NEXT:    v_or_b32_e32 v6, v7, v6
; SI-NEXT:    v_add_i32_e32 v7, vcc, 3, v28
; SI-NEXT:    v_and_b32_e32 v7, 0xff, v7
; SI-NEXT:    v_add_i32_e32 v8, vcc, 3, v30
; SI-NEXT:    v_or_b32_e32 v7, v21, v7
; SI-NEXT:    v_and_b32_e32 v8, 0xff, v8
; SI-NEXT:    v_add_i32_e32 v7, vcc, s6, v7
; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT:    v_or_b32_e32 v8, v19, v8
; SI-NEXT:    v_or_b32_e32 v7, v8, v7
; SI-NEXT:    s_waitcnt vmcnt(0)
; SI-NEXT:    v_add_i32_e32 v8, vcc, 3, v39
; SI-NEXT:    v_and_b32_e32 v8, 0xff, v8
; SI-NEXT:    v_add_i32_e32 v9, vcc, 3, v38
; SI-NEXT:    v_or_b32_e32 v8, v17, v8
; SI-NEXT:    v_and_b32_e32 v9, 0xff, v9
; SI-NEXT:    v_add_i32_e32 v8, vcc, s6, v8
; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT:    v_or_b32_e32 v9, v15, v9
; SI-NEXT:    v_or_b32_e32 v8, v9, v8
; SI-NEXT:    v_add_i32_e32 v9, vcc, 3, v37
; SI-NEXT:    v_and_b32_e32 v9, 0xff, v9
; SI-NEXT:    v_add_i32_e32 v10, vcc, 3, v36
; SI-NEXT:    v_or_b32_e32 v9, v13, v9
; SI-NEXT:    v_and_b32_e32 v10, 0xff, v10
; SI-NEXT:    v_add_i32_e32 v9, vcc, 0x300, v9
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT:    v_or_b32_e32 v10, v11, v10
; SI-NEXT:    v_or_b32_e32 v9, v10, v9
; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x3000000, v0
; SI-NEXT:    v_add_i32_e32 v1, vcc, 0x3000000, v1
; SI-NEXT:    v_add_i32_e32 v2, vcc, 0x3000000, v2
; SI-NEXT:    v_add_i32_e32 v3, vcc, 0x3000000, v3
; SI-NEXT:    v_add_i32_e32 v4, vcc, 0x3000000, v4
; SI-NEXT:    v_add_i32_e32 v5, vcc, 0x3000000, v5
; SI-NEXT:    v_add_i32_e32 v6, vcc, 0x3000000, v6
; SI-NEXT:    v_add_i32_e32 v7, vcc, 0x3000000, v7
; SI-NEXT:    v_add_i32_e32 v8, vcc, 0x3000000, v8
; SI-NEXT:    v_add_i32_e32 v9, vcc, 0x3000000, v9
; SI-NEXT:  .LBB14_4: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    buffer_load_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; SI-NEXT:    s_waitcnt vmcnt(0)
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v40i8_to_v10i32:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; VI-NEXT:    buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; VI-NEXT:    v_mov_b32_e32 v48, v0
; VI-NEXT:    buffer_load_ushort v55, off, s[0:3], s32
; VI-NEXT:    buffer_load_dword v0, off, s[0:3], s32 offset:36
; VI-NEXT:    buffer_load_ushort v49, off, s[0:3], s32 offset:32
; VI-NEXT:    buffer_load_ushort v50, off, s[0:3], s32 offset:28
; VI-NEXT:    buffer_load_ushort v51, off, s[0:3], s32 offset:24
; VI-NEXT:    buffer_load_ushort v52, off, s[0:3], s32 offset:20
; VI-NEXT:    buffer_load_ushort v53, off, s[0:3], s32 offset:16
; VI-NEXT:    buffer_load_ushort v54, off, s[0:3], s32 offset:12
; VI-NEXT:    buffer_load_ushort v40, off, s[0:3], s32 offset:8
; VI-NEXT:    buffer_load_ushort v41, off, s[0:3], s32 offset:4
; VI-NEXT:    v_mov_b32_e32 v31, v9
; VI-NEXT:    v_mov_b32_e32 v32, v8
; VI-NEXT:    v_mov_b32_e32 v33, v7
; VI-NEXT:    v_mov_b32_e32 v34, v6
; VI-NEXT:    v_mov_b32_e32 v35, v5
; VI-NEXT:    v_mov_b32_e32 v36, v4
; VI-NEXT:    v_mov_b32_e32 v37, v3
; VI-NEXT:    v_mov_b32_e32 v38, v2
; VI-NEXT:    v_mov_b32_e32 v39, v1
; VI-NEXT:    s_waitcnt vmcnt(8)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; VI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB14_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    s_mov_b32 s6, 0xc0c0004
; VI-NEXT:    v_perm_b32 v1, v38, v37, s6
; VI-NEXT:    v_perm_b32 v0, v48, v39, s6
; VI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT:    v_perm_b32 v2, v34, v33, s6
; VI-NEXT:    v_or_b32_e32 v0, v0, v1
; VI-NEXT:    v_perm_b32 v1, v36, v35, s6
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_perm_b32 v3, v10, v11, s6
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v32, v31, s6
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_perm_b32 v4, v14, v15, s6
; VI-NEXT:    v_or_b32_e32 v2, v2, v3
; VI-NEXT:    v_perm_b32 v3, v12, v13, s6
; VI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT:    v_perm_b32 v5, v18, v19, s6
; VI-NEXT:    v_or_b32_e32 v3, v3, v4
; VI-NEXT:    v_perm_b32 v4, v16, v17, s6
; VI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT:    v_perm_b32 v6, v22, v23, s6
; VI-NEXT:    v_or_b32_e32 v4, v4, v5
; VI-NEXT:    v_perm_b32 v5, v20, v21, s6
; VI-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT:    v_perm_b32 v7, v26, v27, s6
; VI-NEXT:    v_or_b32_e32 v5, v5, v6
; VI-NEXT:    v_perm_b32 v6, v24, v25, s6
; VI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT:    v_perm_b32 v8, v30, v55, s6
; VI-NEXT:    v_or_b32_e32 v6, v6, v7
; VI-NEXT:    v_perm_b32 v7, v28, v29, s6
; VI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT:    s_waitcnt vmcnt(2)
; VI-NEXT:    v_perm_b32 v9, v54, v53, s6
; VI-NEXT:    v_or_b32_e32 v7, v7, v8
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    v_perm_b32 v8, v41, v40, s6
; VI-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT:    v_perm_b32 v10, v50, v49, s6
; VI-NEXT:    v_or_b32_e32 v8, v8, v9
; VI-NEXT:    v_perm_b32 v9, v52, v51, s6
; VI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT:    v_or_b32_e32 v9, v9, v10
; VI-NEXT:    ; implicit-def: $vgpr48
; VI-NEXT:    ; implicit-def: $vgpr39
; VI-NEXT:    ; implicit-def: $vgpr38
; VI-NEXT:    ; implicit-def: $vgpr37
; VI-NEXT:    ; implicit-def: $vgpr36
; VI-NEXT:    ; implicit-def: $vgpr35
; VI-NEXT:    ; implicit-def: $vgpr34
; VI-NEXT:    ; implicit-def: $vgpr33
; VI-NEXT:    ; implicit-def: $vgpr32
; VI-NEXT:    ; implicit-def: $vgpr31
; VI-NEXT:    ; implicit-def: $vgpr10
; VI-NEXT:    ; implicit-def: $vgpr11
; VI-NEXT:    ; implicit-def: $vgpr12
; VI-NEXT:    ; implicit-def: $vgpr13
; VI-NEXT:    ; implicit-def: $vgpr14
; VI-NEXT:    ; implicit-def: $vgpr15
; VI-NEXT:    ; implicit-def: $vgpr16
; VI-NEXT:    ; implicit-def: $vgpr17
; VI-NEXT:    ; implicit-def: $vgpr18
; VI-NEXT:    ; implicit-def: $vgpr19
; VI-NEXT:    ; implicit-def: $vgpr20
; VI-NEXT:    ; implicit-def: $vgpr21
; VI-NEXT:    ; implicit-def: $vgpr22
; VI-NEXT:    ; implicit-def: $vgpr23
; VI-NEXT:    ; implicit-def: $vgpr24
; VI-NEXT:    ; implicit-def: $vgpr25
; VI-NEXT:    ; implicit-def: $vgpr26
; VI-NEXT:    ; implicit-def: $vgpr27
; VI-NEXT:    ; implicit-def: $vgpr28
; VI-NEXT:    ; implicit-def: $vgpr29
; VI-NEXT:    ; implicit-def: $vgpr30
; VI-NEXT:    ; implicit-def: $vgpr55
; VI-NEXT:    ; implicit-def: $vgpr41
; VI-NEXT:    ; implicit-def: $vgpr40
; VI-NEXT:    ; implicit-def: $vgpr54
; VI-NEXT:    ; implicit-def: $vgpr53
; VI-NEXT:    ; implicit-def: $vgpr52
; VI-NEXT:    ; implicit-def: $vgpr51
; VI-NEXT:    ; implicit-def: $vgpr50
; VI-NEXT:    ; implicit-def: $vgpr49
; VI-NEXT:  .LBB14_2: ; %Flow
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB14_4
; VI-NEXT:  ; %bb.3: ; %cmp.true
; VI-NEXT:    v_add_u16_e32 v0, 3, v48
; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v39
; VI-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v1, 3, v38
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v37
; VI-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_mov_b32_e32 v9, 0x300
; VI-NEXT:    v_add_u16_e32 v0, 0x300, v0
; VI-NEXT:    v_add_u16_sdwa v1, v1, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v0, v0, v1
; VI-NEXT:    v_add_u16_e32 v1, 3, v36
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v35
; VI-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v2, 3, v34
; VI-NEXT:    v_lshlrev_b16_e32 v3, 8, v33
; VI-NEXT:    v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v1, 0x300, v1
; VI-NEXT:    v_add_u16_sdwa v2, v2, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_add_u16_e32 v2, 3, v32
; VI-NEXT:    v_lshlrev_b16_e32 v3, 8, v31
; VI-NEXT:    v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v3, 3, v10
; VI-NEXT:    v_lshlrev_b16_e32 v4, 8, v11
; VI-NEXT:    v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v2, 0x300, v2
; VI-NEXT:    v_add_u16_sdwa v3, v3, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v2, v2, v3
; VI-NEXT:    v_add_u16_e32 v3, 3, v12
; VI-NEXT:    v_lshlrev_b16_e32 v4, 8, v13
; VI-NEXT:    v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v4, 3, v14
; VI-NEXT:    v_lshlrev_b16_e32 v5, 8, v15
; VI-NEXT:    v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v3, 0x300, v3
; VI-NEXT:    v_add_u16_sdwa v4, v4, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v3, v3, v4
; VI-NEXT:    v_add_u16_e32 v4, 3, v16
; VI-NEXT:    v_lshlrev_b16_e32 v5, 8, v17
; VI-NEXT:    v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v5, 3, v18
; VI-NEXT:    v_lshlrev_b16_e32 v6, 8, v19
; VI-NEXT:    v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v4, 0x300, v4
; VI-NEXT:    v_add_u16_sdwa v5, v5, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v4, v4, v5
; VI-NEXT:    v_add_u16_e32 v5, 3, v20
; VI-NEXT:    v_lshlrev_b16_e32 v6, 8, v21
; VI-NEXT:    v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v6, 3, v22
; VI-NEXT:    v_lshlrev_b16_e32 v7, 8, v23
; VI-NEXT:    v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v5, 0x300, v5
; VI-NEXT:    v_add_u16_sdwa v6, v6, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v5, v5, v6
; VI-NEXT:    v_add_u16_e32 v6, 3, v24
; VI-NEXT:    v_lshlrev_b16_e32 v7, 8, v25
; VI-NEXT:    v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v7, 3, v26
; VI-NEXT:    v_lshlrev_b16_e32 v8, 8, v27
; VI-NEXT:    v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v6, 0x300, v6
; VI-NEXT:    v_add_u16_sdwa v7, v7, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v6, v6, v7
; VI-NEXT:    v_add_u16_e32 v7, 3, v28
; VI-NEXT:    v_lshlrev_b16_e32 v8, 8, v29
; VI-NEXT:    v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v8, 3, v30
; VI-NEXT:    v_lshlrev_b16_e32 v10, 8, v55
; VI-NEXT:    v_or_b32_sdwa v8, v10, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v7, 0x300, v7
; VI-NEXT:    v_add_u16_sdwa v8, v8, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v7, v7, v8
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    v_add_u16_e32 v8, 3, v41
; VI-NEXT:    v_lshlrev_b16_e32 v10, 8, v40
; VI-NEXT:    v_or_b32_sdwa v8, v10, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v10, 3, v54
; VI-NEXT:    v_lshlrev_b16_e32 v11, 8, v53
; VI-NEXT:    v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v8, 0x300, v8
; VI-NEXT:    v_add_u16_sdwa v10, v10, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v8, v8, v10
; VI-NEXT:    v_add_u16_e32 v10, 3, v52
; VI-NEXT:    v_lshlrev_b16_e32 v11, 8, v51
; VI-NEXT:    v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v11, 3, v50
; VI-NEXT:    v_lshlrev_b16_e32 v12, 8, v49
; VI-NEXT:    v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v10, 0x300, v10
; VI-NEXT:    v_add_u16_sdwa v9, v11, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v9, v10, v9
; VI-NEXT:  .LBB14_4: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; VI-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v40i8_to_v10i32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; GFX9-NEXT:    buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; GFX9-NEXT:    v_mov_b32_e32 v48, v0
; GFX9-NEXT:    buffer_load_ushort v55, off, s[0:3], s32
; GFX9-NEXT:    buffer_load_dword v0, off, s[0:3], s32 offset:36
; GFX9-NEXT:    buffer_load_ushort v49, off, s[0:3], s32 offset:32
; GFX9-NEXT:    buffer_load_ushort v50, off, s[0:3], s32 offset:28
; GFX9-NEXT:    buffer_load_ushort v51, off, s[0:3], s32 offset:24
; GFX9-NEXT:    buffer_load_ushort v52, off, s[0:3], s32 offset:20
; GFX9-NEXT:    buffer_load_ushort v53, off, s[0:3], s32 offset:16
; GFX9-NEXT:    buffer_load_ushort v54, off, s[0:3], s32 offset:12
; GFX9-NEXT:    buffer_load_ushort v40, off, s[0:3], s32 offset:8
; GFX9-NEXT:    buffer_load_ushort v41, off, s[0:3], s32 offset:4
; GFX9-NEXT:    v_mov_b32_e32 v31, v9
; GFX9-NEXT:    v_mov_b32_e32 v32, v8
; GFX9-NEXT:    v_mov_b32_e32 v33, v7
; GFX9-NEXT:    v_mov_b32_e32 v34, v6
; GFX9-NEXT:    v_mov_b32_e32 v35, v5
; GFX9-NEXT:    v_mov_b32_e32 v36, v4
; GFX9-NEXT:    v_mov_b32_e32 v37, v3
; GFX9-NEXT:    v_mov_b32_e32 v38, v2
; GFX9-NEXT:    v_mov_b32_e32 v39, v1
; GFX9-NEXT:    s_waitcnt vmcnt(8)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB14_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    s_mov_b32 s6, 0xc0c0004
; GFX9-NEXT:    v_perm_b32 v0, v48, v39, s6
; GFX9-NEXT:    v_perm_b32 v1, v38, v37, s6
; GFX9-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT:    v_perm_b32 v1, v36, v35, s6
; GFX9-NEXT:    v_perm_b32 v2, v34, v33, s6
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    v_perm_b32 v2, v32, v31, s6
; GFX9-NEXT:    v_perm_b32 v3, v10, v11, s6
; GFX9-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT:    v_perm_b32 v3, v12, v13, s6
; GFX9-NEXT:    v_perm_b32 v4, v14, v15, s6
; GFX9-NEXT:    v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT:    v_perm_b32 v4, v16, v17, s6
; GFX9-NEXT:    v_perm_b32 v5, v18, v19, s6
; GFX9-NEXT:    v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT:    v_perm_b32 v5, v20, v21, s6
; GFX9-NEXT:    v_perm_b32 v6, v22, v23, s6
; GFX9-NEXT:    v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT:    v_perm_b32 v6, v24, v25, s6
; GFX9-NEXT:    v_perm_b32 v7, v26, v27, s6
; GFX9-NEXT:    v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT:    v_perm_b32 v7, v28, v29, s6
; GFX9-NEXT:    v_perm_b32 v8, v30, v55, s6
; GFX9-NEXT:    v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    v_perm_b32 v8, v41, v40, s6
; GFX9-NEXT:    v_perm_b32 v9, v54, v53, s6
; GFX9-NEXT:    v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT:    v_perm_b32 v9, v52, v51, s6
; GFX9-NEXT:    v_perm_b32 v10, v50, v49, s6
; GFX9-NEXT:    v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT:    ; implicit-def: $vgpr48
; GFX9-NEXT:    ; implicit-def: $vgpr39
; GFX9-NEXT:    ; implicit-def: $vgpr38
; GFX9-NEXT:    ; implicit-def: $vgpr37
; GFX9-NEXT:    ; implicit-def: $vgpr36
; GFX9-NEXT:    ; implicit-def: $vgpr35
; GFX9-NEXT:    ; implicit-def: $vgpr34
; GFX9-NEXT:    ; implicit-def: $vgpr33
; GFX9-NEXT:    ; implicit-def: $vgpr32
; GFX9-NEXT:    ; implicit-def: $vgpr31
; GFX9-NEXT:    ; implicit-def: $vgpr10
; GFX9-NEXT:    ; implicit-def: $vgpr11
; GFX9-NEXT:    ; implicit-def: $vgpr12
; GFX9-NEXT:    ; implicit-def: $vgpr13
; GFX9-NEXT:    ; implicit-def: $vgpr14
; GFX9-NEXT:    ; implicit-def: $vgpr15
; GFX9-NEXT:    ; implicit-def: $vgpr16
; GFX9-NEXT:    ; implicit-def: $vgpr17
; GFX9-NEXT:    ; implicit-def: $vgpr18
; GFX9-NEXT:    ; implicit-def: $vgpr19
; GFX9-NEXT:    ; implicit-def: $vgpr20
; GFX9-NEXT:    ; implicit-def: $vgpr21
; GFX9-NEXT:    ; implicit-def: $vgpr22
; GFX9-NEXT:    ; implicit-def: $vgpr23
; GFX9-NEXT:    ; implicit-def: $vgpr24
; GFX9-NEXT:    ; implicit-def: $vgpr25
; GFX9-NEXT:    ; implicit-def: $vgpr26
; GFX9-NEXT:    ; implicit-def: $vgpr27
; GFX9-NEXT:    ; implicit-def: $vgpr28
; GFX9-NEXT:    ; implicit-def: $vgpr29
; GFX9-NEXT:    ; implicit-def: $vgpr30
; GFX9-NEXT:    ; implicit-def: $vgpr55
; GFX9-NEXT:    ; implicit-def: $vgpr41
; GFX9-NEXT:    ; implicit-def: $vgpr40
; GFX9-NEXT:    ; implicit-def: $vgpr54
; GFX9-NEXT:    ; implicit-def: $vgpr53
; GFX9-NEXT:    ; implicit-def: $vgpr52
; GFX9-NEXT:    ; implicit-def: $vgpr51
; GFX9-NEXT:    ; implicit-def: $vgpr50
; GFX9-NEXT:    ; implicit-def: $vgpr49
; GFX9-NEXT:  .LBB14_2: ; %Flow
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB14_4
; GFX9-NEXT:  ; %bb.3: ; %cmp.true
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v48
; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v39
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v1, 3, v38
; GFX9-NEXT:    v_lshlrev_b16_e32 v2, 8, v37
; GFX9-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v0, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v1, 0x300, v1
; GFX9-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT:    v_add_u16_e32 v1, 3, v36
; GFX9-NEXT:    v_lshlrev_b16_e32 v2, 8, v35
; GFX9-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v2, 3, v34
; GFX9-NEXT:    v_lshlrev_b16_e32 v3, 8, v33
; GFX9-NEXT:    v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v1, 0x300, v1
; GFX9-NEXT:    v_add_u16_e32 v2, 0x300, v2
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    v_add_u16_e32 v2, 3, v32
; GFX9-NEXT:    v_lshlrev_b16_e32 v3, 8, v31
; GFX9-NEXT:    v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v3, 3, v10
; GFX9-NEXT:    v_lshlrev_b16_e32 v4, 8, v11
; GFX9-NEXT:    v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v2, 0x300, v2
; GFX9-NEXT:    v_add_u16_e32 v3, 0x300, v3
; GFX9-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT:    v_add_u16_e32 v3, 3, v12
; GFX9-NEXT:    v_lshlrev_b16_e32 v4, 8, v13
; GFX9-NEXT:    v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v4, 3, v14
; GFX9-NEXT:    v_lshlrev_b16_e32 v5, 8, v15
; GFX9-NEXT:    v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v3, 0x300, v3
; GFX9-NEXT:    v_add_u16_e32 v4, 0x300, v4
; GFX9-NEXT:    v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT:    v_add_u16_e32 v4, 3, v16
; GFX9-NEXT:    v_lshlrev_b16_e32 v5, 8, v17
; GFX9-NEXT:    v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v5, 3, v18
; GFX9-NEXT:    v_lshlrev_b16_e32 v6, 8, v19
; GFX9-NEXT:    v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v4, 0x300, v4
; GFX9-NEXT:    v_add_u16_e32 v5, 0x300, v5
; GFX9-NEXT:    v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT:    v_add_u16_e32 v5, 3, v20
; GFX9-NEXT:    v_lshlrev_b16_e32 v6, 8, v21
; GFX9-NEXT:    v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v6, 3, v22
; GFX9-NEXT:    v_lshlrev_b16_e32 v7, 8, v23
; GFX9-NEXT:    v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v5, 0x300, v5
; GFX9-NEXT:    v_add_u16_e32 v6, 0x300, v6
; GFX9-NEXT:    v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT:    v_add_u16_e32 v6, 3, v24
; GFX9-NEXT:    v_lshlrev_b16_e32 v7, 8, v25
; GFX9-NEXT:    v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v7, 3, v26
; GFX9-NEXT:    v_lshlrev_b16_e32 v8, 8, v27
; GFX9-NEXT:    v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v6, 0x300, v6
; GFX9-NEXT:    v_add_u16_e32 v7, 0x300, v7
; GFX9-NEXT:    v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT:    v_add_u16_e32 v7, 3, v28
; GFX9-NEXT:    v_lshlrev_b16_e32 v8, 8, v29
; GFX9-NEXT:    v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v8, 3, v30
; GFX9-NEXT:    v_lshlrev_b16_e32 v9, 8, v55
; GFX9-NEXT:    v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v7, 0x300, v7
; GFX9-NEXT:    v_add_u16_e32 v8, 0x300, v8
; GFX9-NEXT:    v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    v_add_u16_e32 v8, 3, v41
; GFX9-NEXT:    v_lshlrev_b16_e32 v9, 8, v40
; GFX9-NEXT:    v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v9, 3, v54
; GFX9-NEXT:    v_lshlrev_b16_e32 v10, 8, v53
; GFX9-NEXT:    v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v8, 0x300, v8
; GFX9-NEXT:    v_add_u16_e32 v9, 0x300, v9
; GFX9-NEXT:    v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT:    v_add_u16_e32 v9, 3, v52
; GFX9-NEXT:    v_lshlrev_b16_e32 v10, 8, v51
; GFX9-NEXT:    v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v10, 3, v50
; GFX9-NEXT:    v_lshlrev_b16_e32 v11, 8, v49
; GFX9-NEXT:    v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v9, 0x300, v9
; GFX9-NEXT:    v_add_u16_e32 v10, 0x300, v10
; GFX9-NEXT:    v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT:  .LBB14_4: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; GFX9-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v40i8_to_v10i32:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    s_clause 0x9
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v31, off, s32 offset:32
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v32, off, s32 offset:28
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v33, off, s32 offset:24
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v34, off, s32 offset:20
; GFX11-TRUE16-NEXT:    scratch_load_b32 v66, off, s32 offset:36
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v35, off, s32 offset:16
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v37, off, s32 offset:12
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v36, off, s32 offset:8
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v38, off, s32 offset:4
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v39, off, s32
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v48.l, v9.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v49.l, v8.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v50.l, v7.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v51.l, v6.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v52.l, v5.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v53.l, v4.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v54.l, v3.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v2.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v64.l, v1.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v65.l, v0.l
; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(5)
; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v66
; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB14_3
; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB14_4
; GFX11-TRUE16-NEXT:  .LBB14_2: ; %end
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT:  .LBB14_3: ; %cmp.false
; GFX11-TRUE16-NEXT:    v_perm_b32 v0, v65, v64, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v1, v55, v54, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v2, v53, v52, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v3, v51, v50, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v4, v49, v48, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v5, v10, v11, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, v12, v13, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, v14, v15, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v8, v16, v17, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v9, v18, v19, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v1, v3, 16, v2
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v2, v5, 16, v4
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v3, v7, 16, v6
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v4, v9, 16, v8
; GFX11-TRUE16-NEXT:    v_perm_b32 v5, v20, v21, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, v22, v23, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, v24, v25, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v8, v26, v27, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v9, v28, v29, 0xc0c0004
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT:    v_perm_b32 v10, v30, v39, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v11, v38, v36, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v12, v37, v35, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v13, v34, v33, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v14, v32, v31, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v5, v6, 16, v5
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v6, v8, 16, v7
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v7, v10, 16, v9
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v8, v12, 16, v11
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v9, v14, 16, v13
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr65_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr11_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_lo16
; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB14_2
; GFX11-TRUE16-NEXT:  .LBB14_4: ; %cmp.true
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v65.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v55.l, 3
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v64.l
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 8, v54.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v53.l, 3
; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, 0xff
; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, v0.h, 0xff
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v51.l, 3
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v52.l
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v50.l
; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v1.h, v0.h
; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, v2.l, 0xff
; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, v3.l, 0xff
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v49.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v10.l, 3
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.l, 8, v13.l
; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v2.h, v1.l
; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v3.h, v1.h
; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, v2.l, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v48.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, v12.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.h, v14.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, v16.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, v18.l, 3
; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.h, v2.l
; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, v3.l, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.l, 8, v11.l
; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, v3.h, 0xff
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, v22.l, 3
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v23.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, v24.l, 3
; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v3.l, v2.h
; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v4.l, v3.h
; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, v4.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.l, 8, v15.l
; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, v5.l, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.l, 8, v17.l
; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, v6.l, 0xff
; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, v7.l, 0xff
; GFX11-TRUE16-NEXT:    v_or_b16 v3.h, v4.l, v3.h
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v25.l
; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v5.l, v4.h
; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, v5.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.l, 8, v19.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, v20.l, 3
; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.h, v6.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, v28.l, 3
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.l, 8, v27.l
; GFX11-TRUE16-NEXT:    v_or_b16 v4.h, v5.l, v4.h
; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, v5.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v21.l
; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, v6.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v29.l
; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.h, v7.l
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(3)
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, v37.l, 3
; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.h, v5.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, v26.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.h, v34.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v10.h, v32.l, 3
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(2)
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.l, 8, v36.l
; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, v9.l, 0xff
; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, v5.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.l, 8, v35.l
; GFX11-TRUE16-NEXT:    v_and_b16 v9.h, v9.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v33.l
; GFX11-TRUE16-NEXT:    v_and_b16 v10.h, v10.h, 0xff
; GFX11-TRUE16-NEXT:    v_or_b16 v7.h, v8.l, v5.h
; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.h, v6.h
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.h, v30.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, v6.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, v7.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, v7.h, 0x300
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, v38.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, v8.l, 0x300
; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, v8.h, 0xff
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v39.l
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.l, 8, v31.l
; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, v7.h, 0xff
; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v11.l, v9.l
; GFX11-TRUE16-NEXT:    v_or_b16 v9.h, v11.h, v9.h
; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.h, v8.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, 0x300
; GFX11-TRUE16-NEXT:    v_or_b16 v8.h, v10.l, v7.h
; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v12.l, v10.h
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v0.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v1.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v1.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v2.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v2.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v3.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, v3.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, v4.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.h, v4.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, v5.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, v8.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, v8.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.h, v9.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, v9.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.h, v10.l, 0x300
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v40i8_to_v10i32:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v39, v1 :: v_dual_mov_b32 v48, v0
; GFX11-FAKE16-NEXT:    s_clause 0x9
; GFX11-FAKE16-NEXT:    scratch_load_u16 v49, off, s32 offset:32
; GFX11-FAKE16-NEXT:    scratch_load_u16 v50, off, s32 offset:28
; GFX11-FAKE16-NEXT:    scratch_load_u16 v51, off, s32 offset:24
; GFX11-FAKE16-NEXT:    scratch_load_u16 v53, off, s32 offset:20
; GFX11-FAKE16-NEXT:    scratch_load_b32 v0, off, s32 offset:36
; GFX11-FAKE16-NEXT:    scratch_load_u16 v52, off, s32 offset:16
; GFX11-FAKE16-NEXT:    scratch_load_u16 v54, off, s32 offset:12
; GFX11-FAKE16-NEXT:    scratch_load_u16 v55, off, s32 offset:8
; GFX11-FAKE16-NEXT:    scratch_load_u16 v65, off, s32 offset:4
; GFX11-FAKE16-NEXT:    scratch_load_u16 v64, off, s32
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v31, v9 :: v_dual_mov_b32 v32, v8
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v34, v6
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v35, v5 :: v_dual_mov_b32 v36, v4
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v37, v3 :: v_dual_mov_b32 v38, v2
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(5)
; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB14_3
; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB14_4
; GFX11-FAKE16-NEXT:  .LBB14_2: ; %end
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT:  .LBB14_3: ; %cmp.false
; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v48, v39, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v38, v37, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v36, v35, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v34, v33, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v32, v31, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v10, v11, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v12, v13, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v14, v15, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v16, v17, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v18, v19, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, v5, 16, v4
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v3, v7, 16, v6
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v4, v9, 16, v8
; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v20, v21, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v22, v23, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v24, v25, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v26, v27, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v28, v29, 0xc0c0004
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v30, v64, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v65, v55, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v54, v52, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v53, v51, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v50, v49, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v5, v6, 16, v5
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v6, v8, 16, v7
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v7, v10, 16, v9
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v8, v12, 16, v11
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v9, v14, 16, v13
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr55
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB14_2
; GFX11-FAKE16-NEXT:  .LBB14_4: ; %cmp.true
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v48, 3
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v39
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v36, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v32, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v38, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v35
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v34, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v10, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v1, v0
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v31
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v37
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v33
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v5, v4
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v8
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v9
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 8, v11
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v0, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v3, v2
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v4, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v7, v6
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v1, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v8, v5
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v2, 0x300
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v4, 0x300
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v1
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v5, 0x300
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v12, 3
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v2, 16, v0
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v4, 16, v3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v16, 3
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, v5, 16, v6
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v7
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v13
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v14, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v17
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v18, 3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v5, v4
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v6
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v6, 8, v15
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v7, v3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v8
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 8, v19
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v4, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v6, v5
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v20, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v3, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v8, v7
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v5, 0x300
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v9
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 8, v21
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v6, 0x300
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v3, v5, 16, v4
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v24, 3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v22, 3
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v4, v6, 16, v9
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v9, 8, v25
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v7, 0x300
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v8
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v28, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v26, 3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v9, v5
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v23
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v12, 8, v29
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v10
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v5, 0x300
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v10, 8, v27
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v11, v7
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v12, v8
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, v53, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v5
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v65, 3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v10, v9
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v30, 3
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v14, 8, v55
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, v54, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v51
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, v50, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v64
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v14, v5
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v15
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v52
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v16, v12
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v17
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v49
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v8, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v13, v10
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v5, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v15, v14
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, v12, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v17, v16
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v7, 0x300
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v9, 0x300
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v10, 0x300
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v5
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, v13, 0x300
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, v14, 0x300
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v5, v7, 16, v6
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v6, v9, 16, v11
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v7, v10, 16, v8
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v8, v13, 16, v15
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v9, v14, 16, v12
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <40 x i8> %a, splat (i8 3)
  %a2 = bitcast <40 x i8> %a1 to <10 x i32>
  br label %end

cmp.false:
  %a3 = bitcast <40 x i8> %a to <10 x i32>
  br label %end

end:
  %phi = phi <10 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <10 x i32> %phi
}

define inreg <10 x i32> @bitcast_v40i8_to_v10i32_scalar(<40 x i8> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v40i8_to_v10i32_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_readfirstlane_b32 s4, v26
; SI-NEXT:    v_readfirstlane_b32 s5, v25
; SI-NEXT:    v_readfirstlane_b32 s6, v24
; SI-NEXT:    v_readfirstlane_b32 s8, v23
; SI-NEXT:    v_readfirstlane_b32 s9, v22
; SI-NEXT:    v_readfirstlane_b32 s10, v21
; SI-NEXT:    v_readfirstlane_b32 s11, v20
; SI-NEXT:    v_readfirstlane_b32 s13, v19
; SI-NEXT:    v_readfirstlane_b32 s14, v18
; SI-NEXT:    v_readfirstlane_b32 s40, v17
; SI-NEXT:    v_readfirstlane_b32 s41, v16
; SI-NEXT:    v_readfirstlane_b32 s42, v15
; SI-NEXT:    v_readfirstlane_b32 s43, v14
; SI-NEXT:    v_readfirstlane_b32 s44, v13
; SI-NEXT:    v_readfirstlane_b32 s45, v12
; SI-NEXT:    v_readfirstlane_b32 s46, v11
; SI-NEXT:    v_readfirstlane_b32 s47, v10
; SI-NEXT:    v_readfirstlane_b32 s56, v9
; SI-NEXT:    v_readfirstlane_b32 s57, v8
; SI-NEXT:    v_readfirstlane_b32 s58, v7
; SI-NEXT:    v_readfirstlane_b32 s59, v6
; SI-NEXT:    v_readfirstlane_b32 s60, v5
; SI-NEXT:    v_readfirstlane_b32 s61, v4
; SI-NEXT:    s_cmp_lg_u32 s4, 0
; SI-NEXT:    v_readfirstlane_b32 s62, v3
; SI-NEXT:    v_readfirstlane_b32 s63, v2
; SI-NEXT:    v_readfirstlane_b32 s15, v1
; SI-NEXT:    v_readfirstlane_b32 s72, v0
; SI-NEXT:    s_cbranch_scc0 .LBB15_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    s_and_b32 s4, s16, 0xff
; SI-NEXT:    s_lshl_b32 s7, s17, 8
; SI-NEXT:    s_or_b32 s4, s4, s7
; SI-NEXT:    s_and_b32 s7, s18, 0xff
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_lshl_b32 s12, s19, 24
; SI-NEXT:    s_and_b32 s4, s4, 0xffff
; SI-NEXT:    s_or_b32 s7, s12, s7
; SI-NEXT:    s_or_b32 s4, s4, s7
; SI-NEXT:    s_and_b32 s7, s20, 0xff
; SI-NEXT:    s_lshl_b32 s12, s21, 8
; SI-NEXT:    s_or_b32 s7, s7, s12
; SI-NEXT:    s_and_b32 s12, s22, 0xff
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_lshl_b32 s16, s23, 24
; SI-NEXT:    s_and_b32 s7, s7, 0xffff
; SI-NEXT:    s_or_b32 s12, s16, s12
; SI-NEXT:    s_or_b32 s7, s7, s12
; SI-NEXT:    s_and_b32 s12, s24, 0xff
; SI-NEXT:    s_lshl_b32 s16, s25, 8
; SI-NEXT:    s_or_b32 s12, s12, s16
; SI-NEXT:    s_and_b32 s16, s26, 0xff
; SI-NEXT:    s_lshl_b32 s16, s16, 16
; SI-NEXT:    s_lshl_b32 s17, s27, 24
; SI-NEXT:    s_and_b32 s12, s12, 0xffff
; SI-NEXT:    s_or_b32 s16, s17, s16
; SI-NEXT:    s_or_b32 s12, s12, s16
; SI-NEXT:    s_and_b32 s16, s28, 0xff
; SI-NEXT:    s_lshl_b32 s17, s29, 8
; SI-NEXT:    s_or_b32 s16, s16, s17
; SI-NEXT:    s_and_b32 s17, s72, 0xff
; SI-NEXT:    s_lshl_b32 s17, s17, 16
; SI-NEXT:    s_lshl_b32 s15, s15, 24
; SI-NEXT:    s_and_b32 s16, s16, 0xffff
; SI-NEXT:    s_or_b32 s15, s15, s17
; SI-NEXT:    s_or_b32 s15, s16, s15
; SI-NEXT:    s_and_b32 s16, s63, 0xff
; SI-NEXT:    s_lshl_b32 s17, s62, 8
; SI-NEXT:    s_or_b32 s16, s16, s17
; SI-NEXT:    s_and_b32 s17, s61, 0xff
; SI-NEXT:    s_lshl_b32 s17, s17, 16
; SI-NEXT:    s_lshl_b32 s18, s60, 24
; SI-NEXT:    s_and_b32 s16, s16, 0xffff
; SI-NEXT:    s_or_b32 s17, s18, s17
; SI-NEXT:    s_or_b32 s16, s16, s17
; SI-NEXT:    s_and_b32 s17, s59, 0xff
; SI-NEXT:    s_lshl_b32 s18, s58, 8
; SI-NEXT:    s_or_b32 s17, s17, s18
; SI-NEXT:    s_and_b32 s18, s57, 0xff
; SI-NEXT:    s_lshl_b32 s18, s18, 16
; SI-NEXT:    s_lshl_b32 s19, s56, 24
; SI-NEXT:    s_and_b32 s17, s17, 0xffff
; SI-NEXT:    s_or_b32 s18, s19, s18
; SI-NEXT:    s_or_b32 s17, s17, s18
; SI-NEXT:    s_and_b32 s18, s47, 0xff
; SI-NEXT:    s_lshl_b32 s19, s46, 8
; SI-NEXT:    s_or_b32 s18, s18, s19
; SI-NEXT:    s_and_b32 s19, s45, 0xff
; SI-NEXT:    s_lshl_b32 s19, s19, 16
; SI-NEXT:    s_lshl_b32 s20, s44, 24
; SI-NEXT:    s_and_b32 s18, s18, 0xffff
; SI-NEXT:    s_or_b32 s19, s20, s19
; SI-NEXT:    s_or_b32 s18, s18, s19
; SI-NEXT:    s_and_b32 s19, s43, 0xff
; SI-NEXT:    s_lshl_b32 s20, s42, 8
; SI-NEXT:    s_or_b32 s19, s19, s20
; SI-NEXT:    s_and_b32 s20, s41, 0xff
; SI-NEXT:    s_and_b32 s14, s14, 0xff
; SI-NEXT:    s_lshl_b32 s13, s13, 8
; SI-NEXT:    s_and_b32 s11, s11, 0xff
; SI-NEXT:    s_and_b32 s9, s9, 0xff
; SI-NEXT:    s_lshl_b32 s8, s8, 8
; SI-NEXT:    s_and_b32 s6, s6, 0xff
; SI-NEXT:    s_lshl_b32 s20, s20, 16
; SI-NEXT:    s_lshl_b32 s21, s40, 24
; SI-NEXT:    s_or_b32 s13, s14, s13
; SI-NEXT:    s_lshl_b32 s11, s11, 16
; SI-NEXT:    s_lshl_b32 s10, s10, 24
; SI-NEXT:    s_or_b32 s8, s9, s8
; SI-NEXT:    s_lshl_b32 s6, s6, 16
; SI-NEXT:    s_lshl_b32 s5, s5, 24
; SI-NEXT:    s_and_b32 s19, s19, 0xffff
; SI-NEXT:    s_or_b32 s20, s21, s20
; SI-NEXT:    s_and_b32 s13, s13, 0xffff
; SI-NEXT:    s_or_b32 s10, s10, s11
; SI-NEXT:    s_and_b32 s8, s8, 0xffff
; SI-NEXT:    s_or_b32 s5, s5, s6
; SI-NEXT:    s_or_b32 s19, s19, s20
; SI-NEXT:    s_or_b32 s10, s13, s10
; SI-NEXT:    s_or_b32 s5, s8, s5
; SI-NEXT:    s_branch .LBB15_3
; SI-NEXT:  .LBB15_2: ; %cmp.true
; SI-NEXT:    s_add_i32 s16, s16, 3
; SI-NEXT:    s_and_b32 s4, s16, 0xff
; SI-NEXT:    s_lshl_b32 s7, s17, 8
; SI-NEXT:    s_add_i32 s18, s18, 3
; SI-NEXT:    s_or_b32 s4, s7, s4
; SI-NEXT:    s_and_b32 s12, s18, 0xff
; SI-NEXT:    s_addk_i32 s4, 0x300
; SI-NEXT:    s_lshl_b32 s7, s19, 24
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_and_b32 s4, s4, 0xffff
; SI-NEXT:    s_or_b32 s7, s7, s12
; SI-NEXT:    s_add_i32 s20, s20, 3
; SI-NEXT:    s_or_b32 s4, s7, s4
; SI-NEXT:    s_and_b32 s7, s20, 0xff
; SI-NEXT:    s_lshl_b32 s12, s21, 8
; SI-NEXT:    s_add_i32 s22, s22, 3
; SI-NEXT:    s_or_b32 s7, s12, s7
; SI-NEXT:    s_and_b32 s16, s22, 0xff
; SI-NEXT:    s_addk_i32 s7, 0x300
; SI-NEXT:    s_lshl_b32 s12, s23, 24
; SI-NEXT:    s_lshl_b32 s16, s16, 16
; SI-NEXT:    s_and_b32 s7, s7, 0xffff
; SI-NEXT:    s_or_b32 s12, s12, s16
; SI-NEXT:    s_add_i32 s24, s24, 3
; SI-NEXT:    s_or_b32 s7, s12, s7
; SI-NEXT:    s_and_b32 s12, s24, 0xff
; SI-NEXT:    s_lshl_b32 s16, s25, 8
; SI-NEXT:    s_add_i32 s26, s26, 3
; SI-NEXT:    s_or_b32 s12, s16, s12
; SI-NEXT:    s_and_b32 s17, s26, 0xff
; SI-NEXT:    s_addk_i32 s12, 0x300
; SI-NEXT:    s_lshl_b32 s16, s27, 24
; SI-NEXT:    s_lshl_b32 s17, s17, 16
; SI-NEXT:    s_and_b32 s12, s12, 0xffff
; SI-NEXT:    s_or_b32 s16, s16, s17
; SI-NEXT:    s_add_i32 s28, s28, 3
; SI-NEXT:    s_or_b32 s12, s16, s12
; SI-NEXT:    s_and_b32 s16, s28, 0xff
; SI-NEXT:    s_lshl_b32 s17, s29, 8
; SI-NEXT:    s_add_i32 s72, s72, 3
; SI-NEXT:    s_or_b32 s16, s17, s16
; SI-NEXT:    s_and_b32 s17, s72, 0xff
; SI-NEXT:    s_addk_i32 s16, 0x300
; SI-NEXT:    s_lshl_b32 s15, s15, 24
; SI-NEXT:    s_lshl_b32 s17, s17, 16
; SI-NEXT:    s_and_b32 s16, s16, 0xffff
; SI-NEXT:    s_or_b32 s15, s15, s17
; SI-NEXT:    s_add_i32 s63, s63, 3
; SI-NEXT:    s_or_b32 s15, s15, s16
; SI-NEXT:    s_and_b32 s16, s63, 0xff
; SI-NEXT:    s_lshl_b32 s17, s62, 8
; SI-NEXT:    s_add_i32 s61, s61, 3
; SI-NEXT:    s_or_b32 s16, s17, s16
; SI-NEXT:    s_and_b32 s18, s61, 0xff
; SI-NEXT:    s_addk_i32 s16, 0x300
; SI-NEXT:    s_lshl_b32 s17, s60, 24
; SI-NEXT:    s_lshl_b32 s18, s18, 16
; SI-NEXT:    s_and_b32 s16, s16, 0xffff
; SI-NEXT:    s_or_b32 s17, s17, s18
; SI-NEXT:    s_add_i32 s59, s59, 3
; SI-NEXT:    s_or_b32 s16, s17, s16
; SI-NEXT:    s_and_b32 s17, s59, 0xff
; SI-NEXT:    s_lshl_b32 s18, s58, 8
; SI-NEXT:    s_add_i32 s57, s57, 3
; SI-NEXT:    s_or_b32 s17, s18, s17
; SI-NEXT:    s_and_b32 s19, s57, 0xff
; SI-NEXT:    s_addk_i32 s17, 0x300
; SI-NEXT:    s_lshl_b32 s18, s56, 24
; SI-NEXT:    s_lshl_b32 s19, s19, 16
; SI-NEXT:    s_and_b32 s17, s17, 0xffff
; SI-NEXT:    s_or_b32 s18, s18, s19
; SI-NEXT:    s_add_i32 s47, s47, 3
; SI-NEXT:    s_or_b32 s17, s18, s17
; SI-NEXT:    s_and_b32 s18, s47, 0xff
; SI-NEXT:    s_lshl_b32 s19, s46, 8
; SI-NEXT:    s_add_i32 s45, s45, 3
; SI-NEXT:    s_or_b32 s18, s19, s18
; SI-NEXT:    s_and_b32 s20, s45, 0xff
; SI-NEXT:    s_addk_i32 s18, 0x300
; SI-NEXT:    s_lshl_b32 s19, s44, 24
; SI-NEXT:    s_lshl_b32 s20, s20, 16
; SI-NEXT:    s_and_b32 s18, s18, 0xffff
; SI-NEXT:    s_or_b32 s19, s19, s20
; SI-NEXT:    s_add_i32 s43, s43, 3
; SI-NEXT:    s_add_i32 s14, s14, 3
; SI-NEXT:    s_add_i32 s9, s9, 3
; SI-NEXT:    s_or_b32 s18, s19, s18
; SI-NEXT:    s_and_b32 s19, s43, 0xff
; SI-NEXT:    s_lshl_b32 s20, s42, 8
; SI-NEXT:    s_add_i32 s41, s41, 3
; SI-NEXT:    s_and_b32 s14, s14, 0xff
; SI-NEXT:    s_lshl_b32 s13, s13, 8
; SI-NEXT:    s_add_i32 s11, s11, 3
; SI-NEXT:    s_and_b32 s9, s9, 0xff
; SI-NEXT:    s_lshl_b32 s8, s8, 8
; SI-NEXT:    s_add_i32 s6, s6, 3
; SI-NEXT:    s_or_b32 s19, s20, s19
; SI-NEXT:    s_and_b32 s21, s41, 0xff
; SI-NEXT:    s_or_b32 s13, s13, s14
; SI-NEXT:    s_and_b32 s11, s11, 0xff
; SI-NEXT:    s_or_b32 s8, s8, s9
; SI-NEXT:    s_and_b32 s6, s6, 0xff
; SI-NEXT:    s_addk_i32 s19, 0x300
; SI-NEXT:    s_lshl_b32 s20, s40, 24
; SI-NEXT:    s_lshl_b32 s21, s21, 16
; SI-NEXT:    s_addk_i32 s13, 0x300
; SI-NEXT:    s_lshl_b32 s10, s10, 24
; SI-NEXT:    s_lshl_b32 s11, s11, 16
; SI-NEXT:    s_addk_i32 s8, 0x300
; SI-NEXT:    s_lshl_b32 s5, s5, 24
; SI-NEXT:    s_lshl_b32 s6, s6, 16
; SI-NEXT:    s_and_b32 s19, s19, 0xffff
; SI-NEXT:    s_or_b32 s20, s20, s21
; SI-NEXT:    s_and_b32 s13, s13, 0xffff
; SI-NEXT:    s_or_b32 s10, s10, s11
; SI-NEXT:    s_and_b32 s8, s8, 0xffff
; SI-NEXT:    s_or_b32 s5, s5, s6
; SI-NEXT:    s_or_b32 s19, s20, s19
; SI-NEXT:    s_or_b32 s10, s10, s13
; SI-NEXT:    s_or_b32 s5, s5, s8
; SI-NEXT:    s_add_i32 s4, s4, 0x3000000
; SI-NEXT:    s_add_i32 s7, s7, 0x3000000
; SI-NEXT:    s_add_i32 s12, s12, 0x3000000
; SI-NEXT:    s_add_i32 s15, s15, 0x3000000
; SI-NEXT:    s_add_i32 s16, s16, 0x3000000
; SI-NEXT:    s_add_i32 s17, s17, 0x3000000
; SI-NEXT:    s_add_i32 s18, s18, 0x3000000
; SI-NEXT:    s_add_i32 s19, s19, 0x3000000
; SI-NEXT:    s_add_i32 s10, s10, 0x3000000
; SI-NEXT:    s_add_i32 s5, s5, 0x3000000
; SI-NEXT:  .LBB15_3: ; %end
; SI-NEXT:    v_mov_b32_e32 v0, s4
; SI-NEXT:    v_mov_b32_e32 v1, s7
; SI-NEXT:    v_mov_b32_e32 v2, s12
; SI-NEXT:    v_mov_b32_e32 v3, s15
; SI-NEXT:    v_mov_b32_e32 v4, s16
; SI-NEXT:    v_mov_b32_e32 v5, s17
; SI-NEXT:    v_mov_b32_e32 v6, s18
; SI-NEXT:    v_mov_b32_e32 v7, s19
; SI-NEXT:    v_mov_b32_e32 v8, s10
; SI-NEXT:    v_mov_b32_e32 v9, s5
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v40i8_to_v10i32_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_readfirstlane_b32 s61, v26
; VI-NEXT:    v_readfirstlane_b32 s4, v25
; VI-NEXT:    v_readfirstlane_b32 s5, v24
; VI-NEXT:    v_readfirstlane_b32 s6, v23
; VI-NEXT:    v_readfirstlane_b32 s7, v22
; VI-NEXT:    v_readfirstlane_b32 s8, v21
; VI-NEXT:    v_readfirstlane_b32 s9, v20
; VI-NEXT:    v_readfirstlane_b32 s10, v19
; VI-NEXT:    v_readfirstlane_b32 s11, v18
; VI-NEXT:    v_readfirstlane_b32 s12, v17
; VI-NEXT:    v_readfirstlane_b32 s13, v16
; VI-NEXT:    v_readfirstlane_b32 s14, v15
; VI-NEXT:    v_readfirstlane_b32 s15, v14
; VI-NEXT:    v_readfirstlane_b32 s40, v13
; VI-NEXT:    v_readfirstlane_b32 s41, v12
; VI-NEXT:    v_readfirstlane_b32 s42, v11
; VI-NEXT:    v_readfirstlane_b32 s43, v10
; VI-NEXT:    v_readfirstlane_b32 s44, v9
; VI-NEXT:    v_readfirstlane_b32 s45, v8
; VI-NEXT:    v_readfirstlane_b32 s46, v7
; VI-NEXT:    v_readfirstlane_b32 s47, v6
; VI-NEXT:    v_readfirstlane_b32 s56, v5
; VI-NEXT:    v_readfirstlane_b32 s57, v4
; VI-NEXT:    v_readfirstlane_b32 s58, v3
; VI-NEXT:    v_readfirstlane_b32 s59, v2
; VI-NEXT:    v_readfirstlane_b32 s60, v1
; VI-NEXT:    s_cmp_lg_u32 s61, 0
; VI-NEXT:    v_readfirstlane_b32 s61, v0
; VI-NEXT:    s_cbranch_scc0 .LBB15_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    v_mov_b32_e32 v9, 0xc0c0004
; VI-NEXT:    v_mov_b32_e32 v1, s19
; VI-NEXT:    v_mov_b32_e32 v0, s17
; VI-NEXT:    v_perm_b32 v1, s18, v1, v9
; VI-NEXT:    v_perm_b32 v0, s16, v0, v9
; VI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT:    v_mov_b32_e32 v2, s23
; VI-NEXT:    v_or_b32_e32 v0, v0, v1
; VI-NEXT:    v_mov_b32_e32 v1, s21
; VI-NEXT:    v_perm_b32 v2, s22, v2, v9
; VI-NEXT:    v_perm_b32 v1, s20, v1, v9
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_mov_b32_e32 v3, s27
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_mov_b32_e32 v2, s25
; VI-NEXT:    v_perm_b32 v3, s26, v3, v9
; VI-NEXT:    v_perm_b32 v2, s24, v2, v9
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_mov_b32_e32 v4, s60
; VI-NEXT:    v_or_b32_e32 v2, v2, v3
; VI-NEXT:    v_mov_b32_e32 v3, s29
; VI-NEXT:    v_perm_b32 v4, s61, v4, v9
; VI-NEXT:    v_perm_b32 v3, s28, v3, v9
; VI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT:    v_mov_b32_e32 v5, s56
; VI-NEXT:    v_or_b32_e32 v3, v3, v4
; VI-NEXT:    v_mov_b32_e32 v4, s58
; VI-NEXT:    v_perm_b32 v5, s57, v5, v9
; VI-NEXT:    v_perm_b32 v4, s59, v4, v9
; VI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT:    v_mov_b32_e32 v6, s44
; VI-NEXT:    v_or_b32_e32 v4, v4, v5
; VI-NEXT:    v_mov_b32_e32 v5, s46
; VI-NEXT:    v_perm_b32 v6, s45, v6, v9
; VI-NEXT:    v_perm_b32 v5, s47, v5, v9
; VI-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT:    v_mov_b32_e32 v7, s40
; VI-NEXT:    v_or_b32_e32 v5, v5, v6
; VI-NEXT:    v_mov_b32_e32 v6, s42
; VI-NEXT:    v_perm_b32 v7, s41, v7, v9
; VI-NEXT:    v_perm_b32 v6, s43, v6, v9
; VI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT:    v_mov_b32_e32 v8, s12
; VI-NEXT:    v_or_b32_e32 v6, v6, v7
; VI-NEXT:    v_mov_b32_e32 v7, s14
; VI-NEXT:    v_perm_b32 v8, s13, v8, v9
; VI-NEXT:    v_perm_b32 v7, s15, v7, v9
; VI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT:    v_mov_b32_e32 v10, s8
; VI-NEXT:    v_or_b32_e32 v7, v7, v8
; VI-NEXT:    v_mov_b32_e32 v8, s10
; VI-NEXT:    v_perm_b32 v10, s9, v10, v9
; VI-NEXT:    v_perm_b32 v8, s11, v8, v9
; VI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT:    v_or_b32_e32 v8, v8, v10
; VI-NEXT:    v_mov_b32_e32 v10, s6
; VI-NEXT:    v_mov_b32_e32 v11, s4
; VI-NEXT:    v_perm_b32 v10, s7, v10, v9
; VI-NEXT:    v_perm_b32 v9, s5, v11, v9
; VI-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT:    v_or_b32_e32 v9, v10, v9
; VI-NEXT:    s_setpc_b64 s[30:31]
; VI-NEXT:  .LBB15_2: ; %cmp.true
; VI-NEXT:    s_add_i32 s16, s16, 3
; VI-NEXT:    v_mov_b32_e32 v0, s17
; VI-NEXT:    v_mov_b32_e32 v9, 0xc0c0004
; VI-NEXT:    s_add_i32 s18, s18, 3
; VI-NEXT:    v_mov_b32_e32 v1, s19
; VI-NEXT:    v_perm_b32 v0, s16, v0, v9
; VI-NEXT:    v_perm_b32 v1, s18, v1, v9
; VI-NEXT:    v_add_u32_e32 v0, vcc, 0x300, v0
; VI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s20, s20, 3
; VI-NEXT:    v_mov_b32_e32 v1, s21
; VI-NEXT:    s_add_i32 s22, s22, 3
; VI-NEXT:    v_mov_b32_e32 v2, s23
; VI-NEXT:    v_perm_b32 v1, s20, v1, v9
; VI-NEXT:    v_perm_b32 v2, s22, v2, v9
; VI-NEXT:    v_add_u32_e32 v1, vcc, 0x300, v1
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s24, s24, 3
; VI-NEXT:    v_mov_b32_e32 v2, s25
; VI-NEXT:    s_add_i32 s26, s26, 3
; VI-NEXT:    v_mov_b32_e32 v3, s27
; VI-NEXT:    v_perm_b32 v2, s24, v2, v9
; VI-NEXT:    v_perm_b32 v3, s26, v3, v9
; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x300, v2
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s28, s28, 3
; VI-NEXT:    v_mov_b32_e32 v3, s29
; VI-NEXT:    s_add_i32 s61, s61, 3
; VI-NEXT:    v_mov_b32_e32 v4, s60
; VI-NEXT:    v_perm_b32 v3, s28, v3, v9
; VI-NEXT:    v_perm_b32 v4, s61, v4, v9
; VI-NEXT:    v_add_u32_e32 v3, vcc, 0x300, v3
; VI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT:    v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s59, s59, 3
; VI-NEXT:    v_mov_b32_e32 v4, s58
; VI-NEXT:    s_add_i32 s57, s57, 3
; VI-NEXT:    v_mov_b32_e32 v5, s56
; VI-NEXT:    v_perm_b32 v4, s59, v4, v9
; VI-NEXT:    v_perm_b32 v5, s57, v5, v9
; VI-NEXT:    v_add_u32_e32 v4, vcc, 0x300, v4
; VI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT:    v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s47, s47, 3
; VI-NEXT:    v_mov_b32_e32 v5, s46
; VI-NEXT:    s_add_i32 s45, s45, 3
; VI-NEXT:    v_mov_b32_e32 v6, s44
; VI-NEXT:    v_perm_b32 v5, s47, v5, v9
; VI-NEXT:    v_perm_b32 v6, s45, v6, v9
; VI-NEXT:    v_add_u32_e32 v5, vcc, 0x300, v5
; VI-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT:    v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s43, s43, 3
; VI-NEXT:    v_mov_b32_e32 v6, s42
; VI-NEXT:    s_add_i32 s41, s41, 3
; VI-NEXT:    v_mov_b32_e32 v7, s40
; VI-NEXT:    v_perm_b32 v6, s43, v6, v9
; VI-NEXT:    v_perm_b32 v7, s41, v7, v9
; VI-NEXT:    v_add_u32_e32 v6, vcc, 0x300, v6
; VI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT:    v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s15, s15, 3
; VI-NEXT:    v_mov_b32_e32 v7, s14
; VI-NEXT:    s_add_i32 s13, s13, 3
; VI-NEXT:    v_mov_b32_e32 v8, s12
; VI-NEXT:    v_perm_b32 v7, s15, v7, v9
; VI-NEXT:    v_perm_b32 v8, s13, v8, v9
; VI-NEXT:    v_add_u32_e32 v7, vcc, 0x300, v7
; VI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT:    v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s11, s11, 3
; VI-NEXT:    v_mov_b32_e32 v8, s10
; VI-NEXT:    s_add_i32 s9, s9, 3
; VI-NEXT:    v_mov_b32_e32 v10, s8
; VI-NEXT:    v_perm_b32 v8, s11, v8, v9
; VI-NEXT:    v_perm_b32 v10, s9, v10, v9
; VI-NEXT:    v_add_u32_e32 v8, vcc, 0x300, v8
; VI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT:    v_or_b32_sdwa v8, v10, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s7, s7, 3
; VI-NEXT:    v_mov_b32_e32 v10, s6
; VI-NEXT:    s_add_i32 s5, s5, 3
; VI-NEXT:    v_mov_b32_e32 v11, s4
; VI-NEXT:    v_perm_b32 v10, s7, v10, v9
; VI-NEXT:    v_perm_b32 v9, s5, v11, v9
; VI-NEXT:    v_add_u32_e32 v10, vcc, 0x300, v10
; VI-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT:    v_or_b32_sdwa v9, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    v_add_u32_e32 v0, vcc, 0x3000000, v0
; VI-NEXT:    v_add_u32_e32 v1, vcc, 0x3000000, v1
; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x3000000, v2
; VI-NEXT:    v_add_u32_e32 v3, vcc, 0x3000000, v3
; VI-NEXT:    v_add_u32_e32 v4, vcc, 0x3000000, v4
; VI-NEXT:    v_add_u32_e32 v5, vcc, 0x3000000, v5
; VI-NEXT:    v_add_u32_e32 v6, vcc, 0x3000000, v6
; VI-NEXT:    v_add_u32_e32 v7, vcc, 0x3000000, v7
; VI-NEXT:    v_add_u32_e32 v8, vcc, 0x3000000, v8
; VI-NEXT:    v_add_u32_e32 v9, vcc, 0x3000000, v9
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v40i8_to_v10i32_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_readfirstlane_b32 s61, v26
; GFX9-NEXT:    v_readfirstlane_b32 s4, v25
; GFX9-NEXT:    v_readfirstlane_b32 s5, v24
; GFX9-NEXT:    v_readfirstlane_b32 s6, v23
; GFX9-NEXT:    v_readfirstlane_b32 s7, v22
; GFX9-NEXT:    v_readfirstlane_b32 s8, v21
; GFX9-NEXT:    v_readfirstlane_b32 s9, v20
; GFX9-NEXT:    v_readfirstlane_b32 s10, v19
; GFX9-NEXT:    v_readfirstlane_b32 s11, v18
; GFX9-NEXT:    v_readfirstlane_b32 s12, v17
; GFX9-NEXT:    v_readfirstlane_b32 s13, v16
; GFX9-NEXT:    v_readfirstlane_b32 s14, v15
; GFX9-NEXT:    v_readfirstlane_b32 s15, v14
; GFX9-NEXT:    v_readfirstlane_b32 s40, v13
; GFX9-NEXT:    v_readfirstlane_b32 s41, v12
; GFX9-NEXT:    v_readfirstlane_b32 s42, v11
; GFX9-NEXT:    v_readfirstlane_b32 s43, v10
; GFX9-NEXT:    v_readfirstlane_b32 s44, v9
; GFX9-NEXT:    v_readfirstlane_b32 s45, v8
; GFX9-NEXT:    v_readfirstlane_b32 s46, v7
; GFX9-NEXT:    v_readfirstlane_b32 s47, v6
; GFX9-NEXT:    v_readfirstlane_b32 s56, v5
; GFX9-NEXT:    v_readfirstlane_b32 s57, v4
; GFX9-NEXT:    v_readfirstlane_b32 s58, v3
; GFX9-NEXT:    v_readfirstlane_b32 s59, v2
; GFX9-NEXT:    v_readfirstlane_b32 s60, v1
; GFX9-NEXT:    s_cmp_lg_u32 s61, 0
; GFX9-NEXT:    v_readfirstlane_b32 s61, v0
; GFX9-NEXT:    s_cbranch_scc0 .LBB15_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    v_mov_b32_e32 v9, 0xc0c0004
; GFX9-NEXT:    v_mov_b32_e32 v1, s19
; GFX9-NEXT:    v_mov_b32_e32 v0, s17
; GFX9-NEXT:    v_perm_b32 v1, s18, v1, v9
; GFX9-NEXT:    v_perm_b32 v0, s16, v0, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT:    v_mov_b32_e32 v2, s23
; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
; GFX9-NEXT:    v_mov_b32_e32 v1, s21
; GFX9-NEXT:    v_perm_b32 v2, s22, v2, v9
; GFX9-NEXT:    v_perm_b32 v1, s20, v1, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT:    v_mov_b32_e32 v3, s27
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v2
; GFX9-NEXT:    v_mov_b32_e32 v2, s25
; GFX9-NEXT:    v_perm_b32 v3, s26, v3, v9
; GFX9-NEXT:    v_perm_b32 v2, s24, v2, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT:    v_mov_b32_e32 v4, s60
; GFX9-NEXT:    v_or_b32_e32 v2, v2, v3
; GFX9-NEXT:    v_mov_b32_e32 v3, s29
; GFX9-NEXT:    v_perm_b32 v4, s61, v4, v9
; GFX9-NEXT:    v_perm_b32 v3, s28, v3, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; GFX9-NEXT:    v_mov_b32_e32 v5, s56
; GFX9-NEXT:    v_or_b32_e32 v3, v3, v4
; GFX9-NEXT:    v_mov_b32_e32 v4, s58
; GFX9-NEXT:    v_perm_b32 v5, s57, v5, v9
; GFX9-NEXT:    v_perm_b32 v4, s59, v4, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; GFX9-NEXT:    v_mov_b32_e32 v6, s44
; GFX9-NEXT:    v_or_b32_e32 v4, v4, v5
; GFX9-NEXT:    v_mov_b32_e32 v5, s46
; GFX9-NEXT:    v_perm_b32 v6, s45, v6, v9
; GFX9-NEXT:    v_perm_b32 v5, s47, v5, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; GFX9-NEXT:    v_mov_b32_e32 v7, s40
; GFX9-NEXT:    v_or_b32_e32 v5, v5, v6
; GFX9-NEXT:    v_mov_b32_e32 v6, s42
; GFX9-NEXT:    v_perm_b32 v7, s41, v7, v9
; GFX9-NEXT:    v_perm_b32 v6, s43, v6, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; GFX9-NEXT:    v_mov_b32_e32 v8, s12
; GFX9-NEXT:    v_or_b32_e32 v6, v6, v7
; GFX9-NEXT:    v_mov_b32_e32 v7, s14
; GFX9-NEXT:    v_perm_b32 v8, s13, v8, v9
; GFX9-NEXT:    v_perm_b32 v7, s15, v7, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; GFX9-NEXT:    v_mov_b32_e32 v10, s8
; GFX9-NEXT:    v_or_b32_e32 v7, v7, v8
; GFX9-NEXT:    v_mov_b32_e32 v8, s10
; GFX9-NEXT:    v_perm_b32 v10, s9, v10, v9
; GFX9-NEXT:    v_perm_b32 v8, s11, v8, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; GFX9-NEXT:    v_or_b32_e32 v8, v8, v10
; GFX9-NEXT:    v_mov_b32_e32 v10, s6
; GFX9-NEXT:    v_mov_b32_e32 v11, s4
; GFX9-NEXT:    v_perm_b32 v10, s7, v10, v9
; GFX9-NEXT:    v_perm_b32 v9, s5, v11, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; GFX9-NEXT:    v_or_b32_e32 v9, v10, v9
; GFX9-NEXT:    s_setpc_b64 s[30:31]
; GFX9-NEXT:  .LBB15_2: ; %cmp.true
; GFX9-NEXT:    s_add_i32 s16, s16, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s17
; GFX9-NEXT:    v_mov_b32_e32 v9, 0xc0c0004
; GFX9-NEXT:    s_add_i32 s18, s18, 3
; GFX9-NEXT:    v_mov_b32_e32 v1, s19
; GFX9-NEXT:    v_perm_b32 v0, s16, v0, v9
; GFX9-NEXT:    s_movk_i32 s16, 0x300
; GFX9-NEXT:    v_perm_b32 v1, s18, v1, v9
; GFX9-NEXT:    v_add_u32_e32 v0, 0x300, v0
; GFX9-NEXT:    v_add_u32_sdwa v1, v1, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s20, s20, 3
; GFX9-NEXT:    v_mov_b32_e32 v1, s21
; GFX9-NEXT:    s_add_i32 s22, s22, 3
; GFX9-NEXT:    v_mov_b32_e32 v2, s23
; GFX9-NEXT:    v_perm_b32 v1, s20, v1, v9
; GFX9-NEXT:    v_perm_b32 v2, s22, v2, v9
; GFX9-NEXT:    v_add_u32_e32 v1, 0x300, v1
; GFX9-NEXT:    v_add_u32_sdwa v2, v2, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s24, s24, 3
; GFX9-NEXT:    v_mov_b32_e32 v2, s25
; GFX9-NEXT:    s_add_i32 s26, s26, 3
; GFX9-NEXT:    v_mov_b32_e32 v3, s27
; GFX9-NEXT:    v_perm_b32 v2, s24, v2, v9
; GFX9-NEXT:    v_perm_b32 v3, s26, v3, v9
; GFX9-NEXT:    v_add_u32_e32 v2, 0x300, v2
; GFX9-NEXT:    v_add_u32_sdwa v3, v3, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s28, s28, 3
; GFX9-NEXT:    v_mov_b32_e32 v3, s29
; GFX9-NEXT:    s_add_i32 s61, s61, 3
; GFX9-NEXT:    v_mov_b32_e32 v4, s60
; GFX9-NEXT:    v_perm_b32 v3, s28, v3, v9
; GFX9-NEXT:    v_perm_b32 v4, s61, v4, v9
; GFX9-NEXT:    v_add_u32_e32 v3, 0x300, v3
; GFX9-NEXT:    v_add_u32_sdwa v4, v4, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s59, s59, 3
; GFX9-NEXT:    v_mov_b32_e32 v4, s58
; GFX9-NEXT:    s_add_i32 s57, s57, 3
; GFX9-NEXT:    v_mov_b32_e32 v5, s56
; GFX9-NEXT:    v_perm_b32 v4, s59, v4, v9
; GFX9-NEXT:    v_perm_b32 v5, s57, v5, v9
; GFX9-NEXT:    v_add_u32_e32 v4, 0x300, v4
; GFX9-NEXT:    v_add_u32_sdwa v5, v5, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s47, s47, 3
; GFX9-NEXT:    v_mov_b32_e32 v5, s46
; GFX9-NEXT:    s_add_i32 s45, s45, 3
; GFX9-NEXT:    v_mov_b32_e32 v6, s44
; GFX9-NEXT:    v_perm_b32 v5, s47, v5, v9
; GFX9-NEXT:    v_perm_b32 v6, s45, v6, v9
; GFX9-NEXT:    v_add_u32_e32 v5, 0x300, v5
; GFX9-NEXT:    v_add_u32_sdwa v6, v6, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v5, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s43, s43, 3
; GFX9-NEXT:    v_mov_b32_e32 v6, s42
; GFX9-NEXT:    s_add_i32 s41, s41, 3
; GFX9-NEXT:    v_mov_b32_e32 v7, s40
; GFX9-NEXT:    v_perm_b32 v6, s43, v6, v9
; GFX9-NEXT:    v_perm_b32 v7, s41, v7, v9
; GFX9-NEXT:    v_add_u32_e32 v6, 0x300, v6
; GFX9-NEXT:    v_add_u32_sdwa v7, v7, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v6, v6, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s15, s15, 3
; GFX9-NEXT:    v_mov_b32_e32 v7, s14
; GFX9-NEXT:    s_add_i32 s13, s13, 3
; GFX9-NEXT:    v_mov_b32_e32 v8, s12
; GFX9-NEXT:    v_perm_b32 v7, s15, v7, v9
; GFX9-NEXT:    v_perm_b32 v8, s13, v8, v9
; GFX9-NEXT:    v_add_u32_e32 v7, 0x300, v7
; GFX9-NEXT:    v_add_u32_sdwa v8, v8, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s11, s11, 3
; GFX9-NEXT:    v_mov_b32_e32 v8, s10
; GFX9-NEXT:    s_add_i32 s9, s9, 3
; GFX9-NEXT:    v_mov_b32_e32 v10, s8
; GFX9-NEXT:    v_perm_b32 v8, s11, v8, v9
; GFX9-NEXT:    v_perm_b32 v10, s9, v10, v9
; GFX9-NEXT:    v_add_u32_e32 v8, 0x300, v8
; GFX9-NEXT:    v_add_u32_sdwa v10, v10, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v8, v8, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s7, s7, 3
; GFX9-NEXT:    v_mov_b32_e32 v10, s6
; GFX9-NEXT:    s_add_i32 s5, s5, 3
; GFX9-NEXT:    v_mov_b32_e32 v11, s4
; GFX9-NEXT:    v_perm_b32 v10, s7, v10, v9
; GFX9-NEXT:    v_perm_b32 v9, s5, v11, v9
; GFX9-NEXT:    v_add_u32_e32 v10, 0x300, v10
; GFX9-NEXT:    v_add_u32_sdwa v9, v9, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v40i8_to_v10i32_scalar:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s58, v22
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s4, v21
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s5, v20
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s6, v19
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s7, v18
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s9, v17
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s10, v16
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s8, v15
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s11, v14
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s12, v13
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s13, v12
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s14, v11
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s15, v10
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s40, v9
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s41, v8
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s42, v7
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s43, v6
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s44, v5
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s45, v4
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s46, v3
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s47, v2
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s56, v1
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s57, v0
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v5, 0xc0c0004
; GFX11-TRUE16-NEXT:    s_cmp_lg_u32 s58, 0
; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB15_2
; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_perm_b32 v1, s2, s3, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v3, s18, s19, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, s22, s23, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v8, s26, s27, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v10, s57, s56, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v0, s0, s1, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v2, s16, s17, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v4, s20, s21, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, s24, s25, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v9, s28, s29, v5
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v1
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v2, v3
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v4, v6
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, s45, s44, v5
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v7, v8
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v9, v10
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, s41, s40, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v10, s13, s12, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v11, s10, s9, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v13, s5, s4, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v8, s47, s46, v5
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; GFX11-TRUE16-NEXT:    v_perm_b32 v9, s43, s42, v5
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; GFX11-TRUE16-NEXT:    v_perm_b32 v12, s15, s14, v5
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT:    v_perm_b32 v14, s11, s8, v5
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; GFX11-TRUE16-NEXT:    v_perm_b32 v15, s7, s6, v5
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v8, v6
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v9, v7
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v12, v10
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v14, v11
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v15, v13
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT:  .LBB15_2: ; %cmp.true
; GFX11-TRUE16-NEXT:    s_add_i32 s0, s0, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s16, s16, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s18, s18, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s20, s20, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s22, s22, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s24, s24, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s26, s26, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s28, s28, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s57, s57, 3
; GFX11-TRUE16-NEXT:    v_perm_b32 v0, s0, s1, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v1, s2, s3, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v2, s16, s17, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v3, s18, s19, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v4, s20, s21, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, s22, s23, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, s24, s25, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v8, s26, s27, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v9, s28, s29, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v10, s57, s56, v5
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v4, 0x300, v4
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v6, 0x300, v6
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v8, 0x300, v8
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v9, 0x300, v9
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v10, 0x300, v10
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT:    s_add_i32 s47, s47, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s45, s45, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s43, s43, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s41, s41, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s15, s15, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s13, s13, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s11, s11, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s10, s10, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s7, s7, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s5, s5, 3
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v1
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v2, v3
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v4, v6
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v7, v8
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v9, v10
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, s47, s46, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, s45, s44, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v8, s43, s42, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v9, s41, s40, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v10, s15, s14, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v11, s13, s12, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v12, s11, s8, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v13, s10, s9, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v14, s7, s6, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v5, s5, s4, v5
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v6, 0x300, v6
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v8, 0x300, v8
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v9, 0x300, v9
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v10, 0x300, v10
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v11, 0x300, v11
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v13, 0x300, v13
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v14, 0x300, v14
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v5
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v6, v7
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v8, v9
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v10, v11
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v12, v13
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v14, v15
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v40i8_to_v10i32_scalar:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s58, v22
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s5, v21
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s6, v20
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s4, v19
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s7, v18
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s9, v17
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s11, v16
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s8, v15
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s10, v14
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s12, v13
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s13, v12
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s14, v11
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s15, v10
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s40, v9
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s42, v8
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s41, v7
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s43, v6
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s45, v5
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s46, v4
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s44, v3
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s47, v2
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s56, v1
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s57, v0
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, 0xc0c0004
; GFX11-FAKE16-NEXT:    s_cmp_lg_u32 s58, 0
; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB15_2
; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_perm_b32 v1, s2, s3, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v3, s18, s19, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, s22, s23, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, s26, s27, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v10, s57, s56, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v0, s0, s1, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v2, s16, s17, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v4, s20, s21, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, s24, s25, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, s28, s29, v5
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v6
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, s46, s45, v5
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v7, v8
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v9, v10
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, s42, s40, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v10, s13, s12, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v11, s11, s9, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v13, s6, s5, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, s47, s44, v5
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, s43, s41, v5
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; GFX11-FAKE16-NEXT:    v_perm_b32 v12, s15, s14, v5
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; GFX11-FAKE16-NEXT:    v_perm_b32 v14, s10, s8, v5
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; GFX11-FAKE16-NEXT:    v_perm_b32 v15, s7, s4, v5
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v8, v6
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v9, v7
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v12, v10
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v14, v11
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v15, v13
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT:  .LBB15_2: ; %cmp.true
; GFX11-FAKE16-NEXT:    s_add_i32 s0, s0, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s2, s2, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s16, s16, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s18, s18, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s20, s20, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s22, s22, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s24, s24, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s26, s26, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s28, s28, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s57, s57, 3
; GFX11-FAKE16-NEXT:    v_perm_b32 v0, s0, s1, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v1, s2, s3, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v2, s16, s17, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v3, s18, s19, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v4, s20, s21, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, s22, s23, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, s24, s25, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, s26, s27, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, s28, s29, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v10, s57, s56, v5
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, 0x300, v4
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v6, 0x300, v6
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v8, 0x300, v8
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v9, 0x300, v9
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v10, 0x300, v10
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; GFX11-FAKE16-NEXT:    s_add_i32 s47, s47, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s46, s46, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s43, s43, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s42, s42, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s15, s15, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s13, s13, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s10, s10, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s11, s11, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s7, s7, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s6, s6, 3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v6
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v7, v8
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v9, v10
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, s47, s44, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, s46, s45, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, s43, s41, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, s42, s40, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v10, s15, s14, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v11, s13, s12, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v12, s10, s8, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v13, s11, s9, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v14, s7, s4, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v5, s6, s5, v5
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v6, 0x300, v6
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v8, 0x300, v8
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v9, 0x300, v9
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v10, 0x300, v10
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v11, 0x300, v11
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v13, 0x300, v13
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v14, 0x300, v14
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v5
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v6, v7
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v8, v9
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v10, v11
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v12, v13
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v14, v15
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <40 x i8> %a, splat (i8 3)
  %a2 = bitcast <40 x i8> %a1 to <10 x i32>
  br label %end

cmp.false:
  %a3 = bitcast <40 x i8> %a to <10 x i32>
  br label %end

end:
  %phi = phi <10 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <10 x i32> %phi
}

define <5 x double> @bitcast_v10i32_to_v5f64(<10 x i32> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v10i32_to_v5f64:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB16_2
; SI-NEXT:  ; %bb.1: ; %cmp.true
; SI-NEXT:    v_add_i32_e32 v9, vcc, 3, v9
; SI-NEXT:    v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT:    v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT:    v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT:    v_add_i32_e32 v5, vcc, 3, v5
; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v3
; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT:  .LBB16_2: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v10i32_to_v5f64:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB16_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    v_add_u32_e32 v9, vcc, 3, v9
; VI-NEXT:    v_add_u32_e32 v8, vcc, 3, v8
; VI-NEXT:    v_add_u32_e32 v7, vcc, 3, v7
; VI-NEXT:    v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT:    v_add_u32_e32 v5, vcc, 3, v5
; VI-NEXT:    v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT:    v_add_u32_e32 v3, vcc, 3, v3
; VI-NEXT:    v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT:    v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT:  .LBB16_2: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v10i32_to_v5f64:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB16_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    v_add_u32_e32 v9, 3, v9
; GFX9-NEXT:    v_add_u32_e32 v8, 3, v8
; GFX9-NEXT:    v_add_u32_e32 v7, 3, v7
; GFX9-NEXT:    v_add_u32_e32 v6, 3, v6
; GFX9-NEXT:    v_add_u32_e32 v5, 3, v5
; GFX9-NEXT:    v_add_u32_e32 v4, 3, v4
; GFX9-NEXT:    v_add_u32_e32 v3, 3, v3
; GFX9-NEXT:    v_add_u32_e32 v2, 3, v2
; GFX9-NEXT:    v_add_u32_e32 v1, 3, v1
; GFX9-NEXT:    v_add_u32_e32 v0, 3, v0
; GFX9-NEXT:  .LBB16_2: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v10i32_to_v5f64:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB16_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    v_add_nc_u32_e32 v9, 3, v9
; GFX11-NEXT:    v_add_nc_u32_e32 v8, 3, v8
; GFX11-NEXT:    v_add_nc_u32_e32 v7, 3, v7
; GFX11-NEXT:    v_add_nc_u32_e32 v6, 3, v6
; GFX11-NEXT:    v_add_nc_u32_e32 v5, 3, v5
; GFX11-NEXT:    v_add_nc_u32_e32 v4, 3, v4
; GFX11-NEXT:    v_add_nc_u32_e32 v3, 3, v3
; GFX11-NEXT:    v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT:    v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT:    v_add_nc_u32_e32 v0, 3, v0
; GFX11-NEXT:  .LBB16_2: ; %end
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <10 x i32> %a, splat (i32 3)
  %a2 = bitcast <10 x i32> %a1 to <5 x double>
  br label %end

cmp.false:
  %a3 = bitcast <10 x i32> %a to <5 x double>
  br label %end

end:
  %phi = phi <5 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <5 x double> %phi
}

define inreg <5 x double> @bitcast_v10i32_to_v5f64_scalar(<10 x i32> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v10i32_to_v5f64_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc1 .LBB17_2
; SI-NEXT:  ; %bb.1: ; %cmp.true
; SI-NEXT:    s_add_i32 s25, s25, 3
; SI-NEXT:    s_add_i32 s24, s24, 3
; SI-NEXT:    s_add_i32 s23, s23, 3
; SI-NEXT:    s_add_i32 s22, s22, 3
; SI-NEXT:    s_add_i32 s21, s21, 3
; SI-NEXT:    s_add_i32 s20, s20, 3
; SI-NEXT:    s_add_i32 s19, s19, 3
; SI-NEXT:    s_add_i32 s18, s18, 3
; SI-NEXT:    s_add_i32 s17, s17, 3
; SI-NEXT:    s_add_i32 s16, s16, 3
; SI-NEXT:  .LBB17_2: ; %end
; SI-NEXT:    v_mov_b32_e32 v0, s16
; SI-NEXT:    v_mov_b32_e32 v1, s17
; SI-NEXT:    v_mov_b32_e32 v2, s18
; SI-NEXT:    v_mov_b32_e32 v3, s19
; SI-NEXT:    v_mov_b32_e32 v4, s20
; SI-NEXT:    v_mov_b32_e32 v5, s21
; SI-NEXT:    v_mov_b32_e32 v6, s22
; SI-NEXT:    v_mov_b32_e32 v7, s23
; SI-NEXT:    v_mov_b32_e32 v8, s24
; SI-NEXT:    v_mov_b32_e32 v9, s25
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v10i32_to_v5f64_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc1 .LBB17_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    s_add_i32 s25, s25, 3
; VI-NEXT:    s_add_i32 s24, s24, 3
; VI-NEXT:    s_add_i32 s23, s23, 3
; VI-NEXT:    s_add_i32 s22, s22, 3
; VI-NEXT:    s_add_i32 s21, s21, 3
; VI-NEXT:    s_add_i32 s20, s20, 3
; VI-NEXT:    s_add_i32 s19, s19, 3
; VI-NEXT:    s_add_i32 s18, s18, 3
; VI-NEXT:    s_add_i32 s17, s17, 3
; VI-NEXT:    s_add_i32 s16, s16, 3
; VI-NEXT:  .LBB17_2: ; %end
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s17
; VI-NEXT:    v_mov_b32_e32 v2, s18
; VI-NEXT:    v_mov_b32_e32 v3, s19
; VI-NEXT:    v_mov_b32_e32 v4, s20
; VI-NEXT:    v_mov_b32_e32 v5, s21
; VI-NEXT:    v_mov_b32_e32 v6, s22
; VI-NEXT:    v_mov_b32_e32 v7, s23
; VI-NEXT:    v_mov_b32_e32 v8, s24
; VI-NEXT:    v_mov_b32_e32 v9, s25
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v10i32_to_v5f64_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc1 .LBB17_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    s_add_i32 s25, s25, 3
; GFX9-NEXT:    s_add_i32 s24, s24, 3
; GFX9-NEXT:    s_add_i32 s23, s23, 3
; GFX9-NEXT:    s_add_i32 s22, s22, 3
; GFX9-NEXT:    s_add_i32 s21, s21, 3
; GFX9-NEXT:    s_add_i32 s20, s20, 3
; GFX9-NEXT:    s_add_i32 s19, s19, 3
; GFX9-NEXT:    s_add_i32 s18, s18, 3
; GFX9-NEXT:    s_add_i32 s17, s17, 3
; GFX9-NEXT:    s_add_i32 s16, s16, 3
; GFX9-NEXT:  .LBB17_2: ; %end
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s17
; GFX9-NEXT:    v_mov_b32_e32 v2, s18
; GFX9-NEXT:    v_mov_b32_e32 v3, s19
; GFX9-NEXT:    v_mov_b32_e32 v4, s20
; GFX9-NEXT:    v_mov_b32_e32 v5, s21
; GFX9-NEXT:    v_mov_b32_e32 v6, s22
; GFX9-NEXT:    v_mov_b32_e32 v7, s23
; GFX9-NEXT:    v_mov_b32_e32 v8, s24
; GFX9-NEXT:    v_mov_b32_e32 v9, s25
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v10i32_to_v5f64_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc1 .LBB17_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    s_add_i32 s21, s21, 3
; GFX11-NEXT:    s_add_i32 s20, s20, 3
; GFX11-NEXT:    s_add_i32 s19, s19, 3
; GFX11-NEXT:    s_add_i32 s18, s18, 3
; GFX11-NEXT:    s_add_i32 s17, s17, 3
; GFX11-NEXT:    s_add_i32 s16, s16, 3
; GFX11-NEXT:    s_add_i32 s3, s3, 3
; GFX11-NEXT:    s_add_i32 s2, s2, 3
; GFX11-NEXT:    s_add_i32 s1, s1, 3
; GFX11-NEXT:    s_add_i32 s0, s0, 3
; GFX11-NEXT:  .LBB17_2: ; %end
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <10 x i32> %a, splat (i32 3)
  %a2 = bitcast <10 x i32> %a1 to <5 x double>
  br label %end

cmp.false:
  %a3 = bitcast <10 x i32> %a to <5 x double>
  br label %end

end:
  %phi = phi <5 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <5 x double> %phi
}

define <10 x i32> @bitcast_v5f64_to_v10i32(<5 x double> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v5f64_to_v10i32:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB18_2
; SI-NEXT:  ; %bb.1: ; %cmp.true
; SI-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
; SI-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
; SI-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
; SI-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
; SI-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
; SI-NEXT:  .LBB18_2: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v5f64_to_v10i32:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB18_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
; VI-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
; VI-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
; VI-NEXT:  .LBB18_2: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v5f64_to_v10i32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB18_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
; GFX9-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
; GFX9-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
; GFX9-NEXT:  .LBB18_2: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v5f64_to_v10i32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB18_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
; GFX11-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
; GFX11-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
; GFX11-NEXT:  .LBB18_2: ; %end
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <5 x double> %a, splat (double 1.000000e+00)
  %a2 = bitcast <5 x double> %a1 to <10 x i32>
  br label %end

cmp.false:
  %a3 = bitcast <5 x double> %a to <10 x i32>
  br label %end

end:
  %phi = phi <10 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <10 x i32> %phi
}

define inreg <10 x i32> @bitcast_v5f64_to_v10i32_scalar(<5 x double> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v5f64_to_v10i32_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc0 .LBB19_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    v_mov_b32_e32 v0, s16
; SI-NEXT:    v_mov_b32_e32 v1, s17
; SI-NEXT:    v_mov_b32_e32 v2, s18
; SI-NEXT:    v_mov_b32_e32 v3, s19
; SI-NEXT:    v_mov_b32_e32 v4, s20
; SI-NEXT:    v_mov_b32_e32 v5, s21
; SI-NEXT:    v_mov_b32_e32 v6, s22
; SI-NEXT:    v_mov_b32_e32 v7, s23
; SI-NEXT:    v_mov_b32_e32 v8, s24
; SI-NEXT:    v_mov_b32_e32 v9, s25
; SI-NEXT:    s_setpc_b64 s[30:31]
; SI-NEXT:  .LBB19_2: ; %cmp.true
; SI-NEXT:    v_add_f64 v[8:9], s[24:25], 1.0
; SI-NEXT:    v_add_f64 v[6:7], s[22:23], 1.0
; SI-NEXT:    v_add_f64 v[4:5], s[20:21], 1.0
; SI-NEXT:    v_add_f64 v[2:3], s[18:19], 1.0
; SI-NEXT:    v_add_f64 v[0:1], s[16:17], 1.0
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v5f64_to_v10i32_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc0 .LBB19_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s17
; VI-NEXT:    v_mov_b32_e32 v2, s18
; VI-NEXT:    v_mov_b32_e32 v3, s19
; VI-NEXT:    v_mov_b32_e32 v4, s20
; VI-NEXT:    v_mov_b32_e32 v5, s21
; VI-NEXT:    v_mov_b32_e32 v6, s22
; VI-NEXT:    v_mov_b32_e32 v7, s23
; VI-NEXT:    v_mov_b32_e32 v8, s24
; VI-NEXT:    v_mov_b32_e32 v9, s25
; VI-NEXT:    s_setpc_b64 s[30:31]
; VI-NEXT:  .LBB19_2: ; %cmp.true
; VI-NEXT:    v_add_f64 v[8:9], s[24:25], 1.0
; VI-NEXT:    v_add_f64 v[6:7], s[22:23], 1.0
; VI-NEXT:    v_add_f64 v[4:5], s[20:21], 1.0
; VI-NEXT:    v_add_f64 v[2:3], s[18:19], 1.0
; VI-NEXT:    v_add_f64 v[0:1], s[16:17], 1.0
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v5f64_to_v10i32_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc0 .LBB19_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s17
; GFX9-NEXT:    v_mov_b32_e32 v2, s18
; GFX9-NEXT:    v_mov_b32_e32 v3, s19
; GFX9-NEXT:    v_mov_b32_e32 v4, s20
; GFX9-NEXT:    v_mov_b32_e32 v5, s21
; GFX9-NEXT:    v_mov_b32_e32 v6, s22
; GFX9-NEXT:    v_mov_b32_e32 v7, s23
; GFX9-NEXT:    v_mov_b32_e32 v8, s24
; GFX9-NEXT:    v_mov_b32_e32 v9, s25
; GFX9-NEXT:    s_setpc_b64 s[30:31]
; GFX9-NEXT:  .LBB19_2: ; %cmp.true
; GFX9-NEXT:    v_add_f64 v[8:9], s[24:25], 1.0
; GFX9-NEXT:    v_add_f64 v[6:7], s[22:23], 1.0
; GFX9-NEXT:    v_add_f64 v[4:5], s[20:21], 1.0
; GFX9-NEXT:    v_add_f64 v[2:3], s[18:19], 1.0
; GFX9-NEXT:    v_add_f64 v[0:1], s[16:17], 1.0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v5f64_to_v10i32_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s15, s3
; GFX11-NEXT:    s_mov_b32 s14, s2
; GFX11-NEXT:    s_mov_b32 s13, s1
; GFX11-NEXT:    s_mov_b32 s12, s0
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc0 .LBB19_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-NEXT:    v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
; GFX11-NEXT:    v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT:    s_setpc_b64 s[30:31]
; GFX11-NEXT:  .LBB19_2: ; %cmp.true
; GFX11-NEXT:    v_add_f64 v[8:9], s[20:21], 1.0
; GFX11-NEXT:    v_add_f64 v[6:7], s[18:19], 1.0
; GFX11-NEXT:    v_add_f64 v[4:5], s[16:17], 1.0
; GFX11-NEXT:    v_add_f64 v[2:3], s[14:15], 1.0
; GFX11-NEXT:    v_add_f64 v[0:1], s[12:13], 1.0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <5 x double> %a, splat (double 1.000000e+00)
  %a2 = bitcast <5 x double> %a1 to <10 x i32>
  br label %end

cmp.false:
  %a3 = bitcast <5 x double> %a to <10 x i32>
  br label %end

end:
  %phi = phi <10 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <10 x i32> %phi
}

define <5 x i64> @bitcast_v10i32_to_v5i64(<10 x i32> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v10i32_to_v5i64:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB20_2
; SI-NEXT:  ; %bb.1: ; %cmp.true
; SI-NEXT:    v_add_i32_e32 v9, vcc, 3, v9
; SI-NEXT:    v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT:    v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT:    v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT:    v_add_i32_e32 v5, vcc, 3, v5
; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v3
; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT:  .LBB20_2: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v10i32_to_v5i64:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB20_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    v_add_u32_e32 v9, vcc, 3, v9
; VI-NEXT:    v_add_u32_e32 v8, vcc, 3, v8
; VI-NEXT:    v_add_u32_e32 v7, vcc, 3, v7
; VI-NEXT:    v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT:    v_add_u32_e32 v5, vcc, 3, v5
; VI-NEXT:    v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT:    v_add_u32_e32 v3, vcc, 3, v3
; VI-NEXT:    v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT:    v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT:  .LBB20_2: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v10i32_to_v5i64:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB20_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    v_add_u32_e32 v9, 3, v9
; GFX9-NEXT:    v_add_u32_e32 v8, 3, v8
; GFX9-NEXT:    v_add_u32_e32 v7, 3, v7
; GFX9-NEXT:    v_add_u32_e32 v6, 3, v6
; GFX9-NEXT:    v_add_u32_e32 v5, 3, v5
; GFX9-NEXT:    v_add_u32_e32 v4, 3, v4
; GFX9-NEXT:    v_add_u32_e32 v3, 3, v3
; GFX9-NEXT:    v_add_u32_e32 v2, 3, v2
; GFX9-NEXT:    v_add_u32_e32 v1, 3, v1
; GFX9-NEXT:    v_add_u32_e32 v0, 3, v0
; GFX9-NEXT:  .LBB20_2: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v10i32_to_v5i64:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB20_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    v_add_nc_u32_e32 v9, 3, v9
; GFX11-NEXT:    v_add_nc_u32_e32 v8, 3, v8
; GFX11-NEXT:    v_add_nc_u32_e32 v7, 3, v7
; GFX11-NEXT:    v_add_nc_u32_e32 v6, 3, v6
; GFX11-NEXT:    v_add_nc_u32_e32 v5, 3, v5
; GFX11-NEXT:    v_add_nc_u32_e32 v4, 3, v4
; GFX11-NEXT:    v_add_nc_u32_e32 v3, 3, v3
; GFX11-NEXT:    v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT:    v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT:    v_add_nc_u32_e32 v0, 3, v0
; GFX11-NEXT:  .LBB20_2: ; %end
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <10 x i32> %a, splat (i32 3)
  %a2 = bitcast <10 x i32> %a1 to <5 x i64>
  br label %end

cmp.false:
  %a3 = bitcast <10 x i32> %a to <5 x i64>
  br label %end

end:
  %phi = phi <5 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <5 x i64> %phi
}

define inreg <5 x i64> @bitcast_v10i32_to_v5i64_scalar(<10 x i32> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v10i32_to_v5i64_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc1 .LBB21_2
; SI-NEXT:  ; %bb.1: ; %cmp.true
; SI-NEXT:    s_add_i32 s25, s25, 3
; SI-NEXT:    s_add_i32 s24, s24, 3
; SI-NEXT:    s_add_i32 s23, s23, 3
; SI-NEXT:    s_add_i32 s22, s22, 3
; SI-NEXT:    s_add_i32 s21, s21, 3
; SI-NEXT:    s_add_i32 s20, s20, 3
; SI-NEXT:    s_add_i32 s19, s19, 3
; SI-NEXT:    s_add_i32 s18, s18, 3
; SI-NEXT:    s_add_i32 s17, s17, 3
; SI-NEXT:    s_add_i32 s16, s16, 3
; SI-NEXT:  .LBB21_2: ; %end
; SI-NEXT:    v_mov_b32_e32 v0, s16
; SI-NEXT:    v_mov_b32_e32 v1, s17
; SI-NEXT:    v_mov_b32_e32 v2, s18
; SI-NEXT:    v_mov_b32_e32 v3, s19
; SI-NEXT:    v_mov_b32_e32 v4, s20
; SI-NEXT:    v_mov_b32_e32 v5, s21
; SI-NEXT:    v_mov_b32_e32 v6, s22
; SI-NEXT:    v_mov_b32_e32 v7, s23
; SI-NEXT:    v_mov_b32_e32 v8, s24
; SI-NEXT:    v_mov_b32_e32 v9, s25
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v10i32_to_v5i64_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc1 .LBB21_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    s_add_i32 s25, s25, 3
; VI-NEXT:    s_add_i32 s24, s24, 3
; VI-NEXT:    s_add_i32 s23, s23, 3
; VI-NEXT:    s_add_i32 s22, s22, 3
; VI-NEXT:    s_add_i32 s21, s21, 3
; VI-NEXT:    s_add_i32 s20, s20, 3
; VI-NEXT:    s_add_i32 s19, s19, 3
; VI-NEXT:    s_add_i32 s18, s18, 3
; VI-NEXT:    s_add_i32 s17, s17, 3
; VI-NEXT:    s_add_i32 s16, s16, 3
; VI-NEXT:  .LBB21_2: ; %end
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s17
; VI-NEXT:    v_mov_b32_e32 v2, s18
; VI-NEXT:    v_mov_b32_e32 v3, s19
; VI-NEXT:    v_mov_b32_e32 v4, s20
; VI-NEXT:    v_mov_b32_e32 v5, s21
; VI-NEXT:    v_mov_b32_e32 v6, s22
; VI-NEXT:    v_mov_b32_e32 v7, s23
; VI-NEXT:    v_mov_b32_e32 v8, s24
; VI-NEXT:    v_mov_b32_e32 v9, s25
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v10i32_to_v5i64_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc1 .LBB21_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    s_add_i32 s25, s25, 3
; GFX9-NEXT:    s_add_i32 s24, s24, 3
; GFX9-NEXT:    s_add_i32 s23, s23, 3
; GFX9-NEXT:    s_add_i32 s22, s22, 3
; GFX9-NEXT:    s_add_i32 s21, s21, 3
; GFX9-NEXT:    s_add_i32 s20, s20, 3
; GFX9-NEXT:    s_add_i32 s19, s19, 3
; GFX9-NEXT:    s_add_i32 s18, s18, 3
; GFX9-NEXT:    s_add_i32 s17, s17, 3
; GFX9-NEXT:    s_add_i32 s16, s16, 3
; GFX9-NEXT:  .LBB21_2: ; %end
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s17
; GFX9-NEXT:    v_mov_b32_e32 v2, s18
; GFX9-NEXT:    v_mov_b32_e32 v3, s19
; GFX9-NEXT:    v_mov_b32_e32 v4, s20
; GFX9-NEXT:    v_mov_b32_e32 v5, s21
; GFX9-NEXT:    v_mov_b32_e32 v6, s22
; GFX9-NEXT:    v_mov_b32_e32 v7, s23
; GFX9-NEXT:    v_mov_b32_e32 v8, s24
; GFX9-NEXT:    v_mov_b32_e32 v9, s25
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v10i32_to_v5i64_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc1 .LBB21_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    s_add_i32 s21, s21, 3
; GFX11-NEXT:    s_add_i32 s20, s20, 3
; GFX11-NEXT:    s_add_i32 s19, s19, 3
; GFX11-NEXT:    s_add_i32 s18, s18, 3
; GFX11-NEXT:    s_add_i32 s17, s17, 3
; GFX11-NEXT:    s_add_i32 s16, s16, 3
; GFX11-NEXT:    s_add_i32 s3, s3, 3
; GFX11-NEXT:    s_add_i32 s2, s2, 3
; GFX11-NEXT:    s_add_i32 s1, s1, 3
; GFX11-NEXT:    s_add_i32 s0, s0, 3
; GFX11-NEXT:  .LBB21_2: ; %end
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <10 x i32> %a, splat (i32 3)
  %a2 = bitcast <10 x i32> %a1 to <5 x i64>
  br label %end

cmp.false:
  %a3 = bitcast <10 x i32> %a to <5 x i64>
  br label %end

end:
  %phi = phi <5 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <5 x i64> %phi
}

define <10 x i32> @bitcast_v5i64_to_v10i32(<5 x i64> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v5i64_to_v10i32:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB22_2
; SI-NEXT:  ; %bb.1: ; %cmp.true
; SI-NEXT:    v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
; SI-NEXT:    v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
; SI-NEXT:  .LBB22_2: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v5i64_to_v10i32:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB22_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    v_add_u32_e32 v8, vcc, 3, v8
; VI-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
; VI-NEXT:    v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
; VI-NEXT:    v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT:    v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT:  .LBB22_2: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v5i64_to_v10i32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB22_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, 3, v8
; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v9, vcc
; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, 3, v6
; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, 3, v4
; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, 3, v2
; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT:  .LBB22_2: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v5i64_to_v10i32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB22_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    v_add_co_u32 v8, vcc_lo, v8, 3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo
; GFX11-NEXT:    v_add_co_u32 v6, vcc_lo, v6, 3
; GFX11-NEXT:    v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo
; GFX11-NEXT:    v_add_co_u32 v4, vcc_lo, v4, 3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
; GFX11-NEXT:    v_add_co_u32 v2, vcc_lo, v2, 3
; GFX11-NEXT:    v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX11-NEXT:  .LBB22_2: ; %end
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <5 x i64> %a, splat (i64 3)
  %a2 = bitcast <5 x i64> %a1 to <10 x i32>
  br label %end

cmp.false:
  %a3 = bitcast <5 x i64> %a to <10 x i32>
  br label %end

end:
  %phi = phi <10 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <10 x i32> %phi
}

define inreg <10 x i32> @bitcast_v5i64_to_v10i32_scalar(<5 x i64> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v5i64_to_v10i32_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc1 .LBB23_2
; SI-NEXT:  ; %bb.1: ; %cmp.true
; SI-NEXT:    s_add_u32 s24, s24, 3
; SI-NEXT:    s_addc_u32 s25, s25, 0
; SI-NEXT:    s_add_u32 s22, s22, 3
; SI-NEXT:    s_addc_u32 s23, s23, 0
; SI-NEXT:    s_add_u32 s20, s20, 3
; SI-NEXT:    s_addc_u32 s21, s21, 0
; SI-NEXT:    s_add_u32 s18, s18, 3
; SI-NEXT:    s_addc_u32 s19, s19, 0
; SI-NEXT:    s_add_u32 s16, s16, 3
; SI-NEXT:    s_addc_u32 s17, s17, 0
; SI-NEXT:  .LBB23_2: ; %end
; SI-NEXT:    v_mov_b32_e32 v0, s16
; SI-NEXT:    v_mov_b32_e32 v1, s17
; SI-NEXT:    v_mov_b32_e32 v2, s18
; SI-NEXT:    v_mov_b32_e32 v3, s19
; SI-NEXT:    v_mov_b32_e32 v4, s20
; SI-NEXT:    v_mov_b32_e32 v5, s21
; SI-NEXT:    v_mov_b32_e32 v6, s22
; SI-NEXT:    v_mov_b32_e32 v7, s23
; SI-NEXT:    v_mov_b32_e32 v8, s24
; SI-NEXT:    v_mov_b32_e32 v9, s25
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v5i64_to_v10i32_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc1 .LBB23_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    s_add_u32 s24, s24, 3
; VI-NEXT:    s_addc_u32 s25, s25, 0
; VI-NEXT:    s_add_u32 s22, s22, 3
; VI-NEXT:    s_addc_u32 s23, s23, 0
; VI-NEXT:    s_add_u32 s20, s20, 3
; VI-NEXT:    s_addc_u32 s21, s21, 0
; VI-NEXT:    s_add_u32 s18, s18, 3
; VI-NEXT:    s_addc_u32 s19, s19, 0
; VI-NEXT:    s_add_u32 s16, s16, 3
; VI-NEXT:    s_addc_u32 s17, s17, 0
; VI-NEXT:  .LBB23_2: ; %end
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s17
; VI-NEXT:    v_mov_b32_e32 v2, s18
; VI-NEXT:    v_mov_b32_e32 v3, s19
; VI-NEXT:    v_mov_b32_e32 v4, s20
; VI-NEXT:    v_mov_b32_e32 v5, s21
; VI-NEXT:    v_mov_b32_e32 v6, s22
; VI-NEXT:    v_mov_b32_e32 v7, s23
; VI-NEXT:    v_mov_b32_e32 v8, s24
; VI-NEXT:    v_mov_b32_e32 v9, s25
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v5i64_to_v10i32_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc1 .LBB23_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    s_add_u32 s24, s24, 3
; GFX9-NEXT:    s_addc_u32 s25, s25, 0
; GFX9-NEXT:    s_add_u32 s22, s22, 3
; GFX9-NEXT:    s_addc_u32 s23, s23, 0
; GFX9-NEXT:    s_add_u32 s20, s20, 3
; GFX9-NEXT:    s_addc_u32 s21, s21, 0
; GFX9-NEXT:    s_add_u32 s18, s18, 3
; GFX9-NEXT:    s_addc_u32 s19, s19, 0
; GFX9-NEXT:    s_add_u32 s16, s16, 3
; GFX9-NEXT:    s_addc_u32 s17, s17, 0
; GFX9-NEXT:  .LBB23_2: ; %end
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s17
; GFX9-NEXT:    v_mov_b32_e32 v2, s18
; GFX9-NEXT:    v_mov_b32_e32 v3, s19
; GFX9-NEXT:    v_mov_b32_e32 v4, s20
; GFX9-NEXT:    v_mov_b32_e32 v5, s21
; GFX9-NEXT:    v_mov_b32_e32 v6, s22
; GFX9-NEXT:    v_mov_b32_e32 v7, s23
; GFX9-NEXT:    v_mov_b32_e32 v8, s24
; GFX9-NEXT:    v_mov_b32_e32 v9, s25
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v5i64_to_v10i32_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc1 .LBB23_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    s_add_u32 s20, s20, 3
; GFX11-NEXT:    s_addc_u32 s21, s21, 0
; GFX11-NEXT:    s_add_u32 s18, s18, 3
; GFX11-NEXT:    s_addc_u32 s19, s19, 0
; GFX11-NEXT:    s_add_u32 s16, s16, 3
; GFX11-NEXT:    s_addc_u32 s17, s17, 0
; GFX11-NEXT:    s_add_u32 s2, s2, 3
; GFX11-NEXT:    s_addc_u32 s3, s3, 0
; GFX11-NEXT:    s_add_u32 s0, s0, 3
; GFX11-NEXT:    s_addc_u32 s1, s1, 0
; GFX11-NEXT:  .LBB23_2: ; %end
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <5 x i64> %a, splat (i64 3)
  %a2 = bitcast <5 x i64> %a1 to <10 x i32>
  br label %end

cmp.false:
  %a3 = bitcast <5 x i64> %a to <10 x i32>
  br label %end

end:
  %phi = phi <10 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <10 x i32> %phi
}

define <20 x i16> @bitcast_v10f32_to_v20i16(<10 x float> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v10f32_to_v20i16:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; SI-NEXT:    ; implicit-def: $vgpr16
; SI-NEXT:    ; implicit-def: $vgpr19
; SI-NEXT:    ; implicit-def: $vgpr14
; SI-NEXT:    ; implicit-def: $vgpr18
; SI-NEXT:    ; implicit-def: $vgpr12
; SI-NEXT:    ; implicit-def: $vgpr17
; SI-NEXT:    ; implicit-def: $vgpr11
; SI-NEXT:    ; implicit-def: $vgpr15
; SI-NEXT:    ; implicit-def: $vgpr10
; SI-NEXT:    ; implicit-def: $vgpr13
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB24_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    v_alignbit_b32 v10, v9, v8, 16
; SI-NEXT:    v_alignbit_b32 v11, v7, v6, 16
; SI-NEXT:    v_alignbit_b32 v12, v5, v4, 16
; SI-NEXT:    v_alignbit_b32 v14, v3, v2, 16
; SI-NEXT:    v_alignbit_b32 v16, v1, v0, 16
; SI-NEXT:    v_lshrrev_b32_e32 v13, 16, v9
; SI-NEXT:    v_lshrrev_b32_e32 v15, 16, v7
; SI-NEXT:    v_lshrrev_b32_e32 v17, 16, v5
; SI-NEXT:    v_lshrrev_b32_e32 v18, 16, v3
; SI-NEXT:    v_lshrrev_b32_e32 v19, 16, v1
; SI-NEXT:  .LBB24_2: ; %Flow
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB24_4
; SI-NEXT:  ; %bb.3: ; %cmp.true
; SI-NEXT:    v_add_f32_e32 v1, 1.0, v1
; SI-NEXT:    v_add_f32_e32 v0, 1.0, v0
; SI-NEXT:    v_add_f32_e32 v3, 1.0, v3
; SI-NEXT:    v_add_f32_e32 v2, 1.0, v2
; SI-NEXT:    v_add_f32_e32 v5, 1.0, v5
; SI-NEXT:    v_add_f32_e32 v4, 1.0, v4
; SI-NEXT:    v_add_f32_e32 v7, 1.0, v7
; SI-NEXT:    v_add_f32_e32 v6, 1.0, v6
; SI-NEXT:    v_add_f32_e32 v9, 1.0, v9
; SI-NEXT:    v_add_f32_e32 v8, 1.0, v8
; SI-NEXT:    v_alignbit_b32 v10, v9, v8, 16
; SI-NEXT:    v_alignbit_b32 v11, v7, v6, 16
; SI-NEXT:    v_alignbit_b32 v12, v5, v4, 16
; SI-NEXT:    v_alignbit_b32 v14, v3, v2, 16
; SI-NEXT:    v_alignbit_b32 v16, v1, v0, 16
; SI-NEXT:    v_lshrrev_b32_e32 v13, 16, v9
; SI-NEXT:    v_lshrrev_b32_e32 v15, 16, v7
; SI-NEXT:    v_lshrrev_b32_e32 v17, 16, v5
; SI-NEXT:    v_lshrrev_b32_e32 v18, 16, v3
; SI-NEXT:    v_lshrrev_b32_e32 v19, 16, v1
; SI-NEXT:  .LBB24_4: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT:    v_or_b32_e32 v0, v0, v16
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_lshlrev_b32_e32 v16, 16, v19
; SI-NEXT:    v_or_b32_e32 v2, v2, v14
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT:    v_lshlrev_b32_e32 v14, 16, v18
; SI-NEXT:    v_or_b32_e32 v4, v4, v12
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT:    v_lshlrev_b32_e32 v12, 16, v17
; SI-NEXT:    v_or_b32_e32 v6, v6, v11
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT:    v_lshlrev_b32_e32 v11, 16, v15
; SI-NEXT:    v_or_b32_e32 v8, v8, v10
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v13
; SI-NEXT:    v_or_b32_e32 v1, v1, v16
; SI-NEXT:    v_or_b32_e32 v3, v3, v14
; SI-NEXT:    v_or_b32_e32 v5, v5, v12
; SI-NEXT:    v_or_b32_e32 v7, v7, v11
; SI-NEXT:    v_or_b32_e32 v9, v9, v10
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v10f32_to_v20i16:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB24_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    v_add_f32_e32 v9, 1.0, v9
; VI-NEXT:    v_add_f32_e32 v8, 1.0, v8
; VI-NEXT:    v_add_f32_e32 v7, 1.0, v7
; VI-NEXT:    v_add_f32_e32 v6, 1.0, v6
; VI-NEXT:    v_add_f32_e32 v5, 1.0, v5
; VI-NEXT:    v_add_f32_e32 v4, 1.0, v4
; VI-NEXT:    v_add_f32_e32 v3, 1.0, v3
; VI-NEXT:    v_add_f32_e32 v2, 1.0, v2
; VI-NEXT:    v_add_f32_e32 v1, 1.0, v1
; VI-NEXT:    v_add_f32_e32 v0, 1.0, v0
; VI-NEXT:  .LBB24_2: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v10f32_to_v20i16:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB24_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    v_add_f32_e32 v9, 1.0, v9
; GFX9-NEXT:    v_add_f32_e32 v8, 1.0, v8
; GFX9-NEXT:    v_add_f32_e32 v7, 1.0, v7
; GFX9-NEXT:    v_add_f32_e32 v6, 1.0, v6
; GFX9-NEXT:    v_add_f32_e32 v5, 1.0, v5
; GFX9-NEXT:    v_add_f32_e32 v4, 1.0, v4
; GFX9-NEXT:    v_add_f32_e32 v3, 1.0, v3
; GFX9-NEXT:    v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT:    v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT:    v_add_f32_e32 v0, 1.0, v0
; GFX9-NEXT:  .LBB24_2: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v10f32_to_v20i16:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8
; GFX11-NEXT:    v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
; GFX11-NEXT:    v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT:    v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT:    v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
; GFX11-NEXT:  ; %bb.2: ; %end
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <10 x float> %a, splat (float 1.000000e+00)
  %a2 = bitcast <10 x float> %a1 to <20 x i16>
  br label %end

cmp.false:
  %a3 = bitcast <10 x float> %a to <20 x i16>
  br label %end

end:
  %phi = phi <20 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <20 x i16> %phi
}

define inreg <20 x i16> @bitcast_v10f32_to_v20i16_scalar(<10 x float> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v10f32_to_v20i16_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc0 .LBB25_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    s_lshr_b32 s14, s25, 16
; SI-NEXT:    s_lshr_b32 s15, s23, 16
; SI-NEXT:    s_lshr_b32 s26, s21, 16
; SI-NEXT:    s_lshr_b32 s27, s19, 16
; SI-NEXT:    s_lshr_b32 s28, s17, 16
; SI-NEXT:    s_lshr_b64 s[4:5], s[24:25], 16
; SI-NEXT:    s_lshr_b64 s[6:7], s[22:23], 16
; SI-NEXT:    s_lshr_b64 s[8:9], s[20:21], 16
; SI-NEXT:    s_lshr_b64 s[10:11], s[18:19], 16
; SI-NEXT:    s_lshr_b64 s[12:13], s[16:17], 16
; SI-NEXT:    v_mov_b32_e32 v0, s16
; SI-NEXT:    v_mov_b32_e32 v1, s17
; SI-NEXT:    v_mov_b32_e32 v2, s18
; SI-NEXT:    v_mov_b32_e32 v3, s19
; SI-NEXT:    v_mov_b32_e32 v4, s20
; SI-NEXT:    v_mov_b32_e32 v5, s21
; SI-NEXT:    v_mov_b32_e32 v6, s22
; SI-NEXT:    v_mov_b32_e32 v7, s23
; SI-NEXT:    v_mov_b32_e32 v8, s24
; SI-NEXT:    v_mov_b32_e32 v9, s25
; SI-NEXT:    v_mov_b32_e32 v20, s28
; SI-NEXT:    v_mov_b32_e32 v19, s27
; SI-NEXT:    v_mov_b32_e32 v18, s26
; SI-NEXT:    v_mov_b32_e32 v17, s15
; SI-NEXT:    v_mov_b32_e32 v16, s14
; SI-NEXT:    v_mov_b32_e32 v14, s12
; SI-NEXT:    v_mov_b32_e32 v13, s10
; SI-NEXT:    v_mov_b32_e32 v12, s8
; SI-NEXT:    v_mov_b32_e32 v11, s6
; SI-NEXT:    v_mov_b32_e32 v10, s4
; SI-NEXT:    s_branch .LBB25_3
; SI-NEXT:  .LBB25_2: ; %cmp.true
; SI-NEXT:    v_add_f32_e64 v9, s25, 1.0
; SI-NEXT:    v_add_f32_e64 v8, s24, 1.0
; SI-NEXT:    v_add_f32_e64 v7, s23, 1.0
; SI-NEXT:    v_add_f32_e64 v6, s22, 1.0
; SI-NEXT:    v_lshr_b64 v[10:11], v[8:9], 16
; SI-NEXT:    v_add_f32_e64 v5, s21, 1.0
; SI-NEXT:    v_add_f32_e64 v4, s20, 1.0
; SI-NEXT:    v_lshr_b64 v[11:12], v[6:7], 16
; SI-NEXT:    v_add_f32_e64 v3, s19, 1.0
; SI-NEXT:    v_add_f32_e64 v2, s18, 1.0
; SI-NEXT:    v_lshr_b64 v[12:13], v[4:5], 16
; SI-NEXT:    v_add_f32_e64 v1, s17, 1.0
; SI-NEXT:    v_add_f32_e64 v0, s16, 1.0
; SI-NEXT:    v_lshr_b64 v[13:14], v[2:3], 16
; SI-NEXT:    v_lshrrev_b32_e32 v16, 16, v9
; SI-NEXT:    v_lshrrev_b32_e32 v17, 16, v7
; SI-NEXT:    v_lshrrev_b32_e32 v18, 16, v5
; SI-NEXT:    v_lshrrev_b32_e32 v19, 16, v3
; SI-NEXT:    v_lshrrev_b32_e32 v20, 16, v1
; SI-NEXT:    v_lshr_b64 v[14:15], v[0:1], 16
; SI-NEXT:  .LBB25_3: ; %end
; SI-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT:    v_or_b32_e32 v0, v0, v14
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_lshlrev_b32_e32 v14, 16, v20
; SI-NEXT:    v_or_b32_e32 v2, v2, v13
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT:    v_lshlrev_b32_e32 v13, 16, v19
; SI-NEXT:    v_or_b32_e32 v4, v4, v12
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT:    v_lshlrev_b32_e32 v12, 16, v18
; SI-NEXT:    v_or_b32_e32 v6, v6, v11
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT:    v_lshlrev_b32_e32 v11, 16, v17
; SI-NEXT:    v_or_b32_e32 v8, v8, v10
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v16
; SI-NEXT:    v_or_b32_e32 v1, v1, v14
; SI-NEXT:    v_or_b32_e32 v3, v3, v13
; SI-NEXT:    v_or_b32_e32 v5, v5, v12
; SI-NEXT:    v_or_b32_e32 v7, v7, v11
; SI-NEXT:    v_or_b32_e32 v9, v9, v10
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v10f32_to_v20i16_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc0 .LBB25_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s17
; VI-NEXT:    v_mov_b32_e32 v2, s18
; VI-NEXT:    v_mov_b32_e32 v3, s19
; VI-NEXT:    v_mov_b32_e32 v4, s20
; VI-NEXT:    v_mov_b32_e32 v5, s21
; VI-NEXT:    v_mov_b32_e32 v6, s22
; VI-NEXT:    v_mov_b32_e32 v7, s23
; VI-NEXT:    v_mov_b32_e32 v8, s24
; VI-NEXT:    v_mov_b32_e32 v9, s25
; VI-NEXT:    v_mov_b32_e32 v10, s26
; VI-NEXT:    v_mov_b32_e32 v11, s27
; VI-NEXT:    v_mov_b32_e32 v12, s28
; VI-NEXT:    v_mov_b32_e32 v13, s29
; VI-NEXT:    v_mov_b32_e32 v14, s30
; VI-NEXT:    v_mov_b32_e32 v15, s31
; VI-NEXT:    s_setpc_b64 s[30:31]
; VI-NEXT:  .LBB25_2: ; %cmp.true
; VI-NEXT:    v_add_f32_e64 v9, s25, 1.0
; VI-NEXT:    v_add_f32_e64 v8, s24, 1.0
; VI-NEXT:    v_add_f32_e64 v7, s23, 1.0
; VI-NEXT:    v_add_f32_e64 v6, s22, 1.0
; VI-NEXT:    v_add_f32_e64 v5, s21, 1.0
; VI-NEXT:    v_add_f32_e64 v4, s20, 1.0
; VI-NEXT:    v_add_f32_e64 v3, s19, 1.0
; VI-NEXT:    v_add_f32_e64 v2, s18, 1.0
; VI-NEXT:    v_add_f32_e64 v1, s17, 1.0
; VI-NEXT:    v_add_f32_e64 v0, s16, 1.0
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v10f32_to_v20i16_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc0 .LBB25_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s17
; GFX9-NEXT:    v_mov_b32_e32 v2, s18
; GFX9-NEXT:    v_mov_b32_e32 v3, s19
; GFX9-NEXT:    v_mov_b32_e32 v4, s20
; GFX9-NEXT:    v_mov_b32_e32 v5, s21
; GFX9-NEXT:    v_mov_b32_e32 v6, s22
; GFX9-NEXT:    v_mov_b32_e32 v7, s23
; GFX9-NEXT:    v_mov_b32_e32 v8, s24
; GFX9-NEXT:    v_mov_b32_e32 v9, s25
; GFX9-NEXT:    v_mov_b32_e32 v10, s26
; GFX9-NEXT:    v_mov_b32_e32 v11, s27
; GFX9-NEXT:    v_mov_b32_e32 v12, s28
; GFX9-NEXT:    v_mov_b32_e32 v13, s29
; GFX9-NEXT:    v_mov_b32_e32 v14, s30
; GFX9-NEXT:    v_mov_b32_e32 v15, s31
; GFX9-NEXT:    s_setpc_b64 s[30:31]
; GFX9-NEXT:  .LBB25_2: ; %cmp.true
; GFX9-NEXT:    v_add_f32_e64 v9, s25, 1.0
; GFX9-NEXT:    v_add_f32_e64 v8, s24, 1.0
; GFX9-NEXT:    v_add_f32_e64 v7, s23, 1.0
; GFX9-NEXT:    v_add_f32_e64 v6, s22, 1.0
; GFX9-NEXT:    v_add_f32_e64 v5, s21, 1.0
; GFX9-NEXT:    v_add_f32_e64 v4, s20, 1.0
; GFX9-NEXT:    v_add_f32_e64 v3, s19, 1.0
; GFX9-NEXT:    v_add_f32_e64 v2, s18, 1.0
; GFX9-NEXT:    v_add_f32_e64 v1, s17, 1.0
; GFX9-NEXT:    v_add_f32_e64 v0, s16, 1.0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v10f32_to_v20i16_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s15, s3
; GFX11-NEXT:    s_mov_b32 s14, s2
; GFX11-NEXT:    s_mov_b32 s13, s1
; GFX11-NEXT:    s_mov_b32 s12, s0
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc0 .LBB25_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-NEXT:    v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
; GFX11-NEXT:    v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT:    v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
; GFX11-NEXT:    v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
; GFX11-NEXT:    v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
; GFX11-NEXT:    s_setpc_b64 s[30:31]
; GFX11-NEXT:  .LBB25_2: ; %cmp.true
; GFX11-NEXT:    v_add_f32_e64 v9, s21, 1.0
; GFX11-NEXT:    v_add_f32_e64 v8, s20, 1.0
; GFX11-NEXT:    v_add_f32_e64 v7, s19, 1.0
; GFX11-NEXT:    v_add_f32_e64 v6, s18, 1.0
; GFX11-NEXT:    v_add_f32_e64 v5, s17, 1.0
; GFX11-NEXT:    v_add_f32_e64 v4, s16, 1.0
; GFX11-NEXT:    v_add_f32_e64 v3, s15, 1.0
; GFX11-NEXT:    v_add_f32_e64 v2, s14, 1.0
; GFX11-NEXT:    v_add_f32_e64 v1, s13, 1.0
; GFX11-NEXT:    v_add_f32_e64 v0, s12, 1.0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <10 x float> %a, splat (float 1.000000e+00)
  %a2 = bitcast <10 x float> %a1 to <20 x i16>
  br label %end

cmp.false:
  %a3 = bitcast <10 x float> %a to <20 x i16>
  br label %end

end:
  %phi = phi <20 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <20 x i16> %phi
}

define <10 x float> @bitcast_v20i16_to_v10f32(<20 x i16> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v20i16_to_v10f32:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_mov_b32_e32 v20, v9
; SI-NEXT:    v_mov_b32_e32 v11, v8
; SI-NEXT:    v_mov_b32_e32 v12, v7
; SI-NEXT:    v_mov_b32_e32 v13, v6
; SI-NEXT:    v_mov_b32_e32 v14, v5
; SI-NEXT:    v_mov_b32_e32 v15, v4
; SI-NEXT:    v_mov_b32_e32 v16, v3
; SI-NEXT:    v_mov_b32_e32 v17, v2
; SI-NEXT:    v_mov_b32_e32 v18, v1
; SI-NEXT:    v_mov_b32_e32 v19, v0
; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v20
; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v11
; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v12
; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v13
; SI-NEXT:    v_lshrrev_b32_e32 v4, 16, v14
; SI-NEXT:    v_lshrrev_b32_e32 v5, 16, v15
; SI-NEXT:    v_lshrrev_b32_e32 v6, 16, v16
; SI-NEXT:    v_lshrrev_b32_e32 v7, 16, v17
; SI-NEXT:    v_lshrrev_b32_e32 v8, 16, v18
; SI-NEXT:    v_lshrrev_b32_e32 v9, 16, v19
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; SI-NEXT:    v_lshlrev_b32_e32 v29, 16, v9
; SI-NEXT:    v_lshlrev_b32_e32 v28, 16, v8
; SI-NEXT:    v_lshlrev_b32_e32 v27, 16, v7
; SI-NEXT:    v_lshlrev_b32_e32 v26, 16, v6
; SI-NEXT:    v_lshlrev_b32_e32 v25, 16, v5
; SI-NEXT:    v_lshlrev_b32_e32 v24, 16, v4
; SI-NEXT:    v_lshlrev_b32_e32 v23, 16, v3
; SI-NEXT:    v_lshlrev_b32_e32 v22, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v21, 16, v1
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v0
; SI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_cbranch_execnz .LBB26_3
; SI-NEXT:  ; %bb.1: ; %Flow
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execnz .LBB26_4
; SI-NEXT:  .LBB26_2: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    s_setpc_b64 s[30:31]
; SI-NEXT:  .LBB26_3: ; %cmp.false
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v19
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v18
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v17
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v16
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v15
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v14
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v13
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v12
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v11
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v20
; SI-NEXT:    v_or_b32_e32 v0, v0, v29
; SI-NEXT:    v_or_b32_e32 v1, v1, v28
; SI-NEXT:    v_or_b32_e32 v2, v2, v27
; SI-NEXT:    v_or_b32_e32 v3, v3, v26
; SI-NEXT:    v_or_b32_e32 v4, v4, v25
; SI-NEXT:    v_or_b32_e32 v5, v5, v24
; SI-NEXT:    v_or_b32_e32 v6, v6, v23
; SI-NEXT:    v_or_b32_e32 v7, v7, v22
; SI-NEXT:    v_or_b32_e32 v8, v8, v21
; SI-NEXT:    v_or_b32_e32 v9, v9, v10
; SI-NEXT:    ; implicit-def: $vgpr19
; SI-NEXT:    ; implicit-def: $vgpr18
; SI-NEXT:    ; implicit-def: $vgpr17
; SI-NEXT:    ; implicit-def: $vgpr16
; SI-NEXT:    ; implicit-def: $vgpr15
; SI-NEXT:    ; implicit-def: $vgpr14
; SI-NEXT:    ; implicit-def: $vgpr13
; SI-NEXT:    ; implicit-def: $vgpr12
; SI-NEXT:    ; implicit-def: $vgpr11
; SI-NEXT:    ; implicit-def: $vgpr20
; SI-NEXT:    ; implicit-def: $vgpr29
; SI-NEXT:    ; implicit-def: $vgpr28
; SI-NEXT:    ; implicit-def: $vgpr27
; SI-NEXT:    ; implicit-def: $vgpr26
; SI-NEXT:    ; implicit-def: $vgpr25
; SI-NEXT:    ; implicit-def: $vgpr24
; SI-NEXT:    ; implicit-def: $vgpr23
; SI-NEXT:    ; implicit-def: $vgpr22
; SI-NEXT:    ; implicit-def: $vgpr21
; SI-NEXT:    ; implicit-def: $vgpr10
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB26_2
; SI-NEXT:  .LBB26_4: ; %cmp.true
; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v19
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v18
; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v17
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v16
; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v15
; SI-NEXT:    v_add_i32_e32 v5, vcc, 3, v14
; SI-NEXT:    v_add_i32_e32 v6, vcc, 3, v13
; SI-NEXT:    v_add_i32_e32 v7, vcc, 3, v12
; SI-NEXT:    v_add_i32_e32 v8, vcc, 3, v11
; SI-NEXT:    v_add_i32_e32 v9, vcc, 3, v20
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT:    v_or_b32_e32 v0, v29, v0
; SI-NEXT:    v_or_b32_e32 v1, v28, v1
; SI-NEXT:    v_or_b32_e32 v2, v27, v2
; SI-NEXT:    v_or_b32_e32 v3, v26, v3
; SI-NEXT:    v_or_b32_e32 v4, v25, v4
; SI-NEXT:    v_or_b32_e32 v5, v24, v5
; SI-NEXT:    v_or_b32_e32 v6, v23, v6
; SI-NEXT:    v_or_b32_e32 v7, v22, v7
; SI-NEXT:    v_or_b32_e32 v8, v21, v8
; SI-NEXT:    v_or_b32_e32 v9, v10, v9
; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT:    v_add_i32_e32 v1, vcc, 0x30000, v1
; SI-NEXT:    v_add_i32_e32 v2, vcc, 0x30000, v2
; SI-NEXT:    v_add_i32_e32 v3, vcc, 0x30000, v3
; SI-NEXT:    v_add_i32_e32 v4, vcc, 0x30000, v4
; SI-NEXT:    v_add_i32_e32 v5, vcc, 0x30000, v5
; SI-NEXT:    v_add_i32_e32 v6, vcc, 0x30000, v6
; SI-NEXT:    v_add_i32_e32 v7, vcc, 0x30000, v7
; SI-NEXT:    v_add_i32_e32 v8, vcc, 0x30000, v8
; SI-NEXT:    v_add_i32_e32 v9, vcc, 0x30000, v9
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v20i16_to_v10f32:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB26_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    v_mov_b32_e32 v11, 3
; VI-NEXT:    v_add_u16_e32 v10, 3, v9
; VI-NEXT:    v_add_u16_sdwa v9, v9, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v9, v10, v9
; VI-NEXT:    v_add_u16_e32 v10, 3, v8
; VI-NEXT:    v_add_u16_sdwa v8, v8, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v8, v10, v8
; VI-NEXT:    v_add_u16_e32 v10, 3, v7
; VI-NEXT:    v_add_u16_sdwa v7, v7, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v7, v10, v7
; VI-NEXT:    v_add_u16_e32 v10, 3, v6
; VI-NEXT:    v_add_u16_sdwa v6, v6, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v6, v10, v6
; VI-NEXT:    v_add_u16_e32 v10, 3, v5
; VI-NEXT:    v_add_u16_sdwa v5, v5, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v5, v10, v5
; VI-NEXT:    v_add_u16_e32 v10, 3, v4
; VI-NEXT:    v_add_u16_sdwa v4, v4, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v4, v10, v4
; VI-NEXT:    v_add_u16_e32 v10, 3, v3
; VI-NEXT:    v_add_u16_sdwa v3, v3, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v3, v10, v3
; VI-NEXT:    v_add_u16_e32 v10, 3, v2
; VI-NEXT:    v_add_u16_sdwa v2, v2, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v2, v10, v2
; VI-NEXT:    v_add_u16_e32 v10, 3, v1
; VI-NEXT:    v_add_u16_sdwa v1, v1, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v1, v10, v1
; VI-NEXT:    v_add_u16_e32 v10, 3, v0
; VI-NEXT:    v_add_u16_sdwa v0, v0, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v0, v10, v0
; VI-NEXT:  .LBB26_2: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v20i16_to_v10f32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB26_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX9-NEXT:  .LBB26_2: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v20i16_to_v10f32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB26_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-NEXT:  .LBB26_2: ; %end
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <20 x i16> %a, splat (i16 3)
  %a2 = bitcast <20 x i16> %a1 to <10 x float>
  br label %end

cmp.false:
  %a3 = bitcast <20 x i16> %a to <10 x float>
  br label %end

end:
  %phi = phi <10 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <10 x float> %phi
}

define inreg <10 x float> @bitcast_v20i16_to_v10f32_scalar(<20 x i16> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v20i16_to_v10f32_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_lshr_b32 s11, s25, 16
; SI-NEXT:    s_lshr_b32 s13, s24, 16
; SI-NEXT:    s_lshr_b32 s12, s23, 16
; SI-NEXT:    s_lshr_b32 s10, s22, 16
; SI-NEXT:    s_lshr_b32 s9, s21, 16
; SI-NEXT:    s_lshr_b32 s8, s20, 16
; SI-NEXT:    s_lshr_b32 s7, s19, 16
; SI-NEXT:    s_lshr_b32 s6, s18, 16
; SI-NEXT:    s_lshr_b32 s5, s17, 16
; SI-NEXT:    s_lshr_b32 s4, s16, 16
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc0 .LBB27_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    s_and_b32 s14, s16, 0xffff
; SI-NEXT:    s_lshl_b32 s4, s4, 16
; SI-NEXT:    s_or_b32 s4, s14, s4
; SI-NEXT:    s_and_b32 s14, s17, 0xffff
; SI-NEXT:    s_lshl_b32 s5, s5, 16
; SI-NEXT:    s_or_b32 s5, s14, s5
; SI-NEXT:    s_and_b32 s14, s18, 0xffff
; SI-NEXT:    s_lshl_b32 s6, s6, 16
; SI-NEXT:    s_or_b32 s6, s14, s6
; SI-NEXT:    s_and_b32 s14, s19, 0xffff
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_or_b32 s7, s14, s7
; SI-NEXT:    s_and_b32 s14, s20, 0xffff
; SI-NEXT:    s_lshl_b32 s8, s8, 16
; SI-NEXT:    s_or_b32 s8, s14, s8
; SI-NEXT:    s_and_b32 s14, s21, 0xffff
; SI-NEXT:    s_lshl_b32 s9, s9, 16
; SI-NEXT:    s_or_b32 s9, s14, s9
; SI-NEXT:    s_and_b32 s14, s22, 0xffff
; SI-NEXT:    s_lshl_b32 s10, s10, 16
; SI-NEXT:    s_or_b32 s10, s14, s10
; SI-NEXT:    s_and_b32 s14, s23, 0xffff
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_or_b32 s12, s14, s12
; SI-NEXT:    s_and_b32 s14, s24, 0xffff
; SI-NEXT:    s_lshl_b32 s13, s13, 16
; SI-NEXT:    s_or_b32 s13, s14, s13
; SI-NEXT:    s_and_b32 s14, s25, 0xffff
; SI-NEXT:    s_lshl_b32 s11, s11, 16
; SI-NEXT:    s_or_b32 s11, s14, s11
; SI-NEXT:    s_branch .LBB27_3
; SI-NEXT:  .LBB27_2: ; %cmp.true
; SI-NEXT:    s_add_i32 s16, s16, 3
; SI-NEXT:    s_and_b32 s14, s16, 0xffff
; SI-NEXT:    s_lshl_b32 s4, s4, 16
; SI-NEXT:    s_add_i32 s17, s17, 3
; SI-NEXT:    s_or_b32 s4, s4, s14
; SI-NEXT:    s_and_b32 s14, s17, 0xffff
; SI-NEXT:    s_lshl_b32 s5, s5, 16
; SI-NEXT:    s_add_i32 s18, s18, 3
; SI-NEXT:    s_or_b32 s5, s5, s14
; SI-NEXT:    s_and_b32 s14, s18, 0xffff
; SI-NEXT:    s_lshl_b32 s6, s6, 16
; SI-NEXT:    s_add_i32 s19, s19, 3
; SI-NEXT:    s_or_b32 s6, s6, s14
; SI-NEXT:    s_and_b32 s14, s19, 0xffff
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_add_i32 s20, s20, 3
; SI-NEXT:    s_or_b32 s7, s7, s14
; SI-NEXT:    s_and_b32 s14, s20, 0xffff
; SI-NEXT:    s_lshl_b32 s8, s8, 16
; SI-NEXT:    s_add_i32 s21, s21, 3
; SI-NEXT:    s_or_b32 s8, s8, s14
; SI-NEXT:    s_and_b32 s14, s21, 0xffff
; SI-NEXT:    s_lshl_b32 s9, s9, 16
; SI-NEXT:    s_add_i32 s22, s22, 3
; SI-NEXT:    s_or_b32 s9, s9, s14
; SI-NEXT:    s_and_b32 s14, s22, 0xffff
; SI-NEXT:    s_lshl_b32 s10, s10, 16
; SI-NEXT:    s_add_i32 s23, s23, 3
; SI-NEXT:    s_or_b32 s10, s10, s14
; SI-NEXT:    s_and_b32 s14, s23, 0xffff
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_add_i32 s24, s24, 3
; SI-NEXT:    s_or_b32 s12, s12, s14
; SI-NEXT:    s_and_b32 s14, s24, 0xffff
; SI-NEXT:    s_lshl_b32 s13, s13, 16
; SI-NEXT:    s_add_i32 s25, s25, 3
; SI-NEXT:    s_or_b32 s13, s13, s14
; SI-NEXT:    s_and_b32 s14, s25, 0xffff
; SI-NEXT:    s_lshl_b32 s11, s11, 16
; SI-NEXT:    s_or_b32 s11, s11, s14
; SI-NEXT:    s_add_i32 s4, s4, 0x30000
; SI-NEXT:    s_add_i32 s5, s5, 0x30000
; SI-NEXT:    s_add_i32 s6, s6, 0x30000
; SI-NEXT:    s_add_i32 s7, s7, 0x30000
; SI-NEXT:    s_add_i32 s8, s8, 0x30000
; SI-NEXT:    s_add_i32 s9, s9, 0x30000
; SI-NEXT:    s_add_i32 s10, s10, 0x30000
; SI-NEXT:    s_add_i32 s12, s12, 0x30000
; SI-NEXT:    s_add_i32 s13, s13, 0x30000
; SI-NEXT:    s_add_i32 s11, s11, 0x30000
; SI-NEXT:  .LBB27_3: ; %end
; SI-NEXT:    v_mov_b32_e32 v0, s4
; SI-NEXT:    v_mov_b32_e32 v1, s5
; SI-NEXT:    v_mov_b32_e32 v2, s6
; SI-NEXT:    v_mov_b32_e32 v3, s7
; SI-NEXT:    v_mov_b32_e32 v4, s8
; SI-NEXT:    v_mov_b32_e32 v5, s9
; SI-NEXT:    v_mov_b32_e32 v6, s10
; SI-NEXT:    v_mov_b32_e32 v7, s12
; SI-NEXT:    v_mov_b32_e32 v8, s13
; SI-NEXT:    v_mov_b32_e32 v9, s11
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v20i16_to_v10f32_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc1 .LBB27_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    s_add_i32 s5, s25, 3
; VI-NEXT:    s_and_b32 s4, s25, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s24, 3
; VI-NEXT:    s_add_i32 s25, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s24, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s23, 3
; VI-NEXT:    s_add_i32 s24, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s23, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s22, 3
; VI-NEXT:    s_add_i32 s23, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s22, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s21, 3
; VI-NEXT:    s_add_i32 s22, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s21, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s20, 3
; VI-NEXT:    s_add_i32 s21, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s20, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s19, 3
; VI-NEXT:    s_add_i32 s20, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s19, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s18, 3
; VI-NEXT:    s_add_i32 s19, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s18, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s17, 3
; VI-NEXT:    s_add_i32 s18, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s17, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s16, 3
; VI-NEXT:    s_add_i32 s17, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s16, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s16, s4, 0x30000
; VI-NEXT:  .LBB27_2: ; %end
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s17
; VI-NEXT:    v_mov_b32_e32 v2, s18
; VI-NEXT:    v_mov_b32_e32 v3, s19
; VI-NEXT:    v_mov_b32_e32 v4, s20
; VI-NEXT:    v_mov_b32_e32 v5, s21
; VI-NEXT:    v_mov_b32_e32 v6, s22
; VI-NEXT:    v_mov_b32_e32 v7, s23
; VI-NEXT:    v_mov_b32_e32 v8, s24
; VI-NEXT:    v_mov_b32_e32 v9, s25
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v20i16_to_v10f32_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc0 .LBB27_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s17
; GFX9-NEXT:    v_mov_b32_e32 v2, s18
; GFX9-NEXT:    v_mov_b32_e32 v3, s19
; GFX9-NEXT:    v_mov_b32_e32 v4, s20
; GFX9-NEXT:    v_mov_b32_e32 v5, s21
; GFX9-NEXT:    v_mov_b32_e32 v6, s22
; GFX9-NEXT:    v_mov_b32_e32 v7, s23
; GFX9-NEXT:    v_mov_b32_e32 v8, s24
; GFX9-NEXT:    v_mov_b32_e32 v9, s25
; GFX9-NEXT:    s_setpc_b64 s[30:31]
; GFX9-NEXT:  .LBB27_2: ; %cmp.true
; GFX9-NEXT:    v_pk_add_u16 v9, s25, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v8, s24, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v7, s23, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v6, s22, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v5, s21, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v4, s20, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v3, s19, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v20i16_to_v10f32_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s15, s3
; GFX11-NEXT:    s_mov_b32 s14, s2
; GFX11-NEXT:    s_mov_b32 s13, s1
; GFX11-NEXT:    s_mov_b32 s12, s0
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc0 .LBB27_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-NEXT:    v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
; GFX11-NEXT:    v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT:    s_setpc_b64 s[30:31]
; GFX11-NEXT:  .LBB27_2: ; %cmp.true
; GFX11-NEXT:    v_pk_add_u16 v9, s21, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v8, s20, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v7, s19, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v6, s18, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v5, s17, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v4, s16, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v3, s15, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v2, s14, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v1, s13, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v0, s12, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <20 x i16> %a, splat (i16 3)
  %a2 = bitcast <20 x i16> %a1 to <10 x float>
  br label %end

cmp.false:
  %a3 = bitcast <20 x i16> %a to <10 x float>
  br label %end

end:
  %phi = phi <10 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <10 x float> %phi
}

define <20 x half> @bitcast_v10f32_to_v20f16(<10 x float> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v10f32_to_v20f16:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; SI-NEXT:    ; implicit-def: $vgpr16
; SI-NEXT:    ; implicit-def: $vgpr19
; SI-NEXT:    ; implicit-def: $vgpr14
; SI-NEXT:    ; implicit-def: $vgpr18
; SI-NEXT:    ; implicit-def: $vgpr12
; SI-NEXT:    ; implicit-def: $vgpr17
; SI-NEXT:    ; implicit-def: $vgpr11
; SI-NEXT:    ; implicit-def: $vgpr15
; SI-NEXT:    ; implicit-def: $vgpr10
; SI-NEXT:    ; implicit-def: $vgpr13
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB28_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    v_alignbit_b32 v10, v9, v8, 16
; SI-NEXT:    v_alignbit_b32 v11, v7, v6, 16
; SI-NEXT:    v_alignbit_b32 v12, v5, v4, 16
; SI-NEXT:    v_alignbit_b32 v14, v3, v2, 16
; SI-NEXT:    v_alignbit_b32 v16, v1, v0, 16
; SI-NEXT:    v_lshrrev_b32_e32 v13, 16, v9
; SI-NEXT:    v_lshrrev_b32_e32 v15, 16, v7
; SI-NEXT:    v_lshrrev_b32_e32 v17, 16, v5
; SI-NEXT:    v_lshrrev_b32_e32 v18, 16, v3
; SI-NEXT:    v_lshrrev_b32_e32 v19, 16, v1
; SI-NEXT:  .LBB28_2: ; %Flow
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB28_4
; SI-NEXT:  ; %bb.3: ; %cmp.true
; SI-NEXT:    v_add_f32_e32 v1, 1.0, v1
; SI-NEXT:    v_add_f32_e32 v0, 1.0, v0
; SI-NEXT:    v_add_f32_e32 v3, 1.0, v3
; SI-NEXT:    v_add_f32_e32 v2, 1.0, v2
; SI-NEXT:    v_add_f32_e32 v5, 1.0, v5
; SI-NEXT:    v_add_f32_e32 v4, 1.0, v4
; SI-NEXT:    v_add_f32_e32 v7, 1.0, v7
; SI-NEXT:    v_add_f32_e32 v6, 1.0, v6
; SI-NEXT:    v_add_f32_e32 v9, 1.0, v9
; SI-NEXT:    v_add_f32_e32 v8, 1.0, v8
; SI-NEXT:    v_alignbit_b32 v10, v9, v8, 16
; SI-NEXT:    v_alignbit_b32 v11, v7, v6, 16
; SI-NEXT:    v_alignbit_b32 v12, v5, v4, 16
; SI-NEXT:    v_alignbit_b32 v14, v3, v2, 16
; SI-NEXT:    v_alignbit_b32 v16, v1, v0, 16
; SI-NEXT:    v_lshrrev_b32_e32 v13, 16, v9
; SI-NEXT:    v_lshrrev_b32_e32 v15, 16, v7
; SI-NEXT:    v_lshrrev_b32_e32 v17, 16, v5
; SI-NEXT:    v_lshrrev_b32_e32 v18, 16, v3
; SI-NEXT:    v_lshrrev_b32_e32 v19, 16, v1
; SI-NEXT:  .LBB28_4: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT:    v_or_b32_e32 v0, v0, v16
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_lshlrev_b32_e32 v16, 16, v19
; SI-NEXT:    v_or_b32_e32 v2, v2, v14
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT:    v_lshlrev_b32_e32 v14, 16, v18
; SI-NEXT:    v_or_b32_e32 v4, v4, v12
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT:    v_lshlrev_b32_e32 v12, 16, v17
; SI-NEXT:    v_or_b32_e32 v6, v6, v11
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT:    v_lshlrev_b32_e32 v11, 16, v15
; SI-NEXT:    v_or_b32_e32 v8, v8, v10
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v13
; SI-NEXT:    v_or_b32_e32 v1, v1, v16
; SI-NEXT:    v_or_b32_e32 v3, v3, v14
; SI-NEXT:    v_or_b32_e32 v5, v5, v12
; SI-NEXT:    v_or_b32_e32 v7, v7, v11
; SI-NEXT:    v_or_b32_e32 v9, v9, v10
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v10f32_to_v20f16:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB28_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    v_add_f32_e32 v9, 1.0, v9
; VI-NEXT:    v_add_f32_e32 v8, 1.0, v8
; VI-NEXT:    v_add_f32_e32 v7, 1.0, v7
; VI-NEXT:    v_add_f32_e32 v6, 1.0, v6
; VI-NEXT:    v_add_f32_e32 v5, 1.0, v5
; VI-NEXT:    v_add_f32_e32 v4, 1.0, v4
; VI-NEXT:    v_add_f32_e32 v3, 1.0, v3
; VI-NEXT:    v_add_f32_e32 v2, 1.0, v2
; VI-NEXT:    v_add_f32_e32 v1, 1.0, v1
; VI-NEXT:    v_add_f32_e32 v0, 1.0, v0
; VI-NEXT:  .LBB28_2: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v10f32_to_v20f16:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB28_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    v_add_f32_e32 v9, 1.0, v9
; GFX9-NEXT:    v_add_f32_e32 v8, 1.0, v8
; GFX9-NEXT:    v_add_f32_e32 v7, 1.0, v7
; GFX9-NEXT:    v_add_f32_e32 v6, 1.0, v6
; GFX9-NEXT:    v_add_f32_e32 v5, 1.0, v5
; GFX9-NEXT:    v_add_f32_e32 v4, 1.0, v4
; GFX9-NEXT:    v_add_f32_e32 v3, 1.0, v3
; GFX9-NEXT:    v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT:    v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT:    v_add_f32_e32 v0, 1.0, v0
; GFX9-NEXT:  .LBB28_2: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v10f32_to_v20f16:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8
; GFX11-NEXT:    v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
; GFX11-NEXT:    v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT:    v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT:    v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
; GFX11-NEXT:  ; %bb.2: ; %end
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <10 x float> %a, splat (float 1.000000e+00)
  %a2 = bitcast <10 x float> %a1 to <20 x half>
  br label %end

cmp.false:
  %a3 = bitcast <10 x float> %a to <20 x half>
  br label %end

end:
  %phi = phi <20 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <20 x half> %phi
}

define inreg <20 x half> @bitcast_v10f32_to_v20f16_scalar(<10 x float> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v10f32_to_v20f16_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc0 .LBB29_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    s_lshr_b32 s14, s25, 16
; SI-NEXT:    s_lshr_b32 s15, s23, 16
; SI-NEXT:    s_lshr_b32 s26, s21, 16
; SI-NEXT:    s_lshr_b32 s27, s19, 16
; SI-NEXT:    s_lshr_b32 s28, s17, 16
; SI-NEXT:    s_lshr_b64 s[4:5], s[24:25], 16
; SI-NEXT:    s_lshr_b64 s[6:7], s[22:23], 16
; SI-NEXT:    s_lshr_b64 s[8:9], s[20:21], 16
; SI-NEXT:    s_lshr_b64 s[10:11], s[18:19], 16
; SI-NEXT:    s_lshr_b64 s[12:13], s[16:17], 16
; SI-NEXT:    v_mov_b32_e32 v0, s16
; SI-NEXT:    v_mov_b32_e32 v1, s17
; SI-NEXT:    v_mov_b32_e32 v2, s18
; SI-NEXT:    v_mov_b32_e32 v3, s19
; SI-NEXT:    v_mov_b32_e32 v4, s20
; SI-NEXT:    v_mov_b32_e32 v5, s21
; SI-NEXT:    v_mov_b32_e32 v6, s22
; SI-NEXT:    v_mov_b32_e32 v7, s23
; SI-NEXT:    v_mov_b32_e32 v8, s24
; SI-NEXT:    v_mov_b32_e32 v9, s25
; SI-NEXT:    v_mov_b32_e32 v20, s28
; SI-NEXT:    v_mov_b32_e32 v19, s27
; SI-NEXT:    v_mov_b32_e32 v18, s26
; SI-NEXT:    v_mov_b32_e32 v17, s15
; SI-NEXT:    v_mov_b32_e32 v16, s14
; SI-NEXT:    v_mov_b32_e32 v14, s12
; SI-NEXT:    v_mov_b32_e32 v13, s10
; SI-NEXT:    v_mov_b32_e32 v12, s8
; SI-NEXT:    v_mov_b32_e32 v11, s6
; SI-NEXT:    v_mov_b32_e32 v10, s4
; SI-NEXT:    s_branch .LBB29_3
; SI-NEXT:  .LBB29_2: ; %cmp.true
; SI-NEXT:    v_add_f32_e64 v9, s25, 1.0
; SI-NEXT:    v_add_f32_e64 v8, s24, 1.0
; SI-NEXT:    v_add_f32_e64 v7, s23, 1.0
; SI-NEXT:    v_add_f32_e64 v6, s22, 1.0
; SI-NEXT:    v_lshr_b64 v[10:11], v[8:9], 16
; SI-NEXT:    v_add_f32_e64 v5, s21, 1.0
; SI-NEXT:    v_add_f32_e64 v4, s20, 1.0
; SI-NEXT:    v_lshr_b64 v[11:12], v[6:7], 16
; SI-NEXT:    v_add_f32_e64 v3, s19, 1.0
; SI-NEXT:    v_add_f32_e64 v2, s18, 1.0
; SI-NEXT:    v_lshr_b64 v[12:13], v[4:5], 16
; SI-NEXT:    v_add_f32_e64 v1, s17, 1.0
; SI-NEXT:    v_add_f32_e64 v0, s16, 1.0
; SI-NEXT:    v_lshr_b64 v[13:14], v[2:3], 16
; SI-NEXT:    v_lshrrev_b32_e32 v16, 16, v9
; SI-NEXT:    v_lshrrev_b32_e32 v17, 16, v7
; SI-NEXT:    v_lshrrev_b32_e32 v18, 16, v5
; SI-NEXT:    v_lshrrev_b32_e32 v19, 16, v3
; SI-NEXT:    v_lshrrev_b32_e32 v20, 16, v1
; SI-NEXT:    v_lshr_b64 v[14:15], v[0:1], 16
; SI-NEXT:  .LBB29_3: ; %end
; SI-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT:    v_or_b32_e32 v0, v0, v14
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_lshlrev_b32_e32 v14, 16, v20
; SI-NEXT:    v_or_b32_e32 v2, v2, v13
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT:    v_lshlrev_b32_e32 v13, 16, v19
; SI-NEXT:    v_or_b32_e32 v4, v4, v12
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT:    v_lshlrev_b32_e32 v12, 16, v18
; SI-NEXT:    v_or_b32_e32 v6, v6, v11
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT:    v_lshlrev_b32_e32 v11, 16, v17
; SI-NEXT:    v_or_b32_e32 v8, v8, v10
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v16
; SI-NEXT:    v_or_b32_e32 v1, v1, v14
; SI-NEXT:    v_or_b32_e32 v3, v3, v13
; SI-NEXT:    v_or_b32_e32 v5, v5, v12
; SI-NEXT:    v_or_b32_e32 v7, v7, v11
; SI-NEXT:    v_or_b32_e32 v9, v9, v10
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v10f32_to_v20f16_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc0 .LBB29_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s17
; VI-NEXT:    v_mov_b32_e32 v2, s18
; VI-NEXT:    v_mov_b32_e32 v3, s19
; VI-NEXT:    v_mov_b32_e32 v4, s20
; VI-NEXT:    v_mov_b32_e32 v5, s21
; VI-NEXT:    v_mov_b32_e32 v6, s22
; VI-NEXT:    v_mov_b32_e32 v7, s23
; VI-NEXT:    v_mov_b32_e32 v8, s24
; VI-NEXT:    v_mov_b32_e32 v9, s25
; VI-NEXT:    v_mov_b32_e32 v10, s26
; VI-NEXT:    v_mov_b32_e32 v11, s27
; VI-NEXT:    v_mov_b32_e32 v12, s28
; VI-NEXT:    v_mov_b32_e32 v13, s29
; VI-NEXT:    v_mov_b32_e32 v14, s30
; VI-NEXT:    v_mov_b32_e32 v15, s31
; VI-NEXT:    s_setpc_b64 s[30:31]
; VI-NEXT:  .LBB29_2: ; %cmp.true
; VI-NEXT:    v_add_f32_e64 v9, s25, 1.0
; VI-NEXT:    v_add_f32_e64 v8, s24, 1.0
; VI-NEXT:    v_add_f32_e64 v7, s23, 1.0
; VI-NEXT:    v_add_f32_e64 v6, s22, 1.0
; VI-NEXT:    v_add_f32_e64 v5, s21, 1.0
; VI-NEXT:    v_add_f32_e64 v4, s20, 1.0
; VI-NEXT:    v_add_f32_e64 v3, s19, 1.0
; VI-NEXT:    v_add_f32_e64 v2, s18, 1.0
; VI-NEXT:    v_add_f32_e64 v1, s17, 1.0
; VI-NEXT:    v_add_f32_e64 v0, s16, 1.0
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v10f32_to_v20f16_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc0 .LBB29_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s17
; GFX9-NEXT:    v_mov_b32_e32 v2, s18
; GFX9-NEXT:    v_mov_b32_e32 v3, s19
; GFX9-NEXT:    v_mov_b32_e32 v4, s20
; GFX9-NEXT:    v_mov_b32_e32 v5, s21
; GFX9-NEXT:    v_mov_b32_e32 v6, s22
; GFX9-NEXT:    v_mov_b32_e32 v7, s23
; GFX9-NEXT:    v_mov_b32_e32 v8, s24
; GFX9-NEXT:    v_mov_b32_e32 v9, s25
; GFX9-NEXT:    v_mov_b32_e32 v10, s26
; GFX9-NEXT:    v_mov_b32_e32 v11, s27
; GFX9-NEXT:    v_mov_b32_e32 v12, s28
; GFX9-NEXT:    v_mov_b32_e32 v13, s29
; GFX9-NEXT:    v_mov_b32_e32 v14, s30
; GFX9-NEXT:    v_mov_b32_e32 v15, s31
; GFX9-NEXT:    s_setpc_b64 s[30:31]
; GFX9-NEXT:  .LBB29_2: ; %cmp.true
; GFX9-NEXT:    v_add_f32_e64 v9, s25, 1.0
; GFX9-NEXT:    v_add_f32_e64 v8, s24, 1.0
; GFX9-NEXT:    v_add_f32_e64 v7, s23, 1.0
; GFX9-NEXT:    v_add_f32_e64 v6, s22, 1.0
; GFX9-NEXT:    v_add_f32_e64 v5, s21, 1.0
; GFX9-NEXT:    v_add_f32_e64 v4, s20, 1.0
; GFX9-NEXT:    v_add_f32_e64 v3, s19, 1.0
; GFX9-NEXT:    v_add_f32_e64 v2, s18, 1.0
; GFX9-NEXT:    v_add_f32_e64 v1, s17, 1.0
; GFX9-NEXT:    v_add_f32_e64 v0, s16, 1.0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v10f32_to_v20f16_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s15, s3
; GFX11-NEXT:    s_mov_b32 s14, s2
; GFX11-NEXT:    s_mov_b32 s13, s1
; GFX11-NEXT:    s_mov_b32 s12, s0
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc0 .LBB29_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-NEXT:    v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
; GFX11-NEXT:    v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT:    v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
; GFX11-NEXT:    v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
; GFX11-NEXT:    v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
; GFX11-NEXT:    s_setpc_b64 s[30:31]
; GFX11-NEXT:  .LBB29_2: ; %cmp.true
; GFX11-NEXT:    v_add_f32_e64 v9, s21, 1.0
; GFX11-NEXT:    v_add_f32_e64 v8, s20, 1.0
; GFX11-NEXT:    v_add_f32_e64 v7, s19, 1.0
; GFX11-NEXT:    v_add_f32_e64 v6, s18, 1.0
; GFX11-NEXT:    v_add_f32_e64 v5, s17, 1.0
; GFX11-NEXT:    v_add_f32_e64 v4, s16, 1.0
; GFX11-NEXT:    v_add_f32_e64 v3, s15, 1.0
; GFX11-NEXT:    v_add_f32_e64 v2, s14, 1.0
; GFX11-NEXT:    v_add_f32_e64 v1, s13, 1.0
; GFX11-NEXT:    v_add_f32_e64 v0, s12, 1.0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <10 x float> %a, splat (float 1.000000e+00)
  %a2 = bitcast <10 x float> %a1 to <20 x half>
  br label %end

cmp.false:
  %a3 = bitcast <10 x float> %a to <20 x half>
  br label %end

end:
  %phi = phi <20 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <20 x half> %phi
}

define <10 x float> @bitcast_v20f16_to_v10f32(<20 x half> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v20f16_to_v10f32:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_mov_b32_e32 v20, v9
; SI-NEXT:    v_mov_b32_e32 v11, v8
; SI-NEXT:    v_mov_b32_e32 v12, v7
; SI-NEXT:    v_mov_b32_e32 v13, v6
; SI-NEXT:    v_mov_b32_e32 v14, v5
; SI-NEXT:    v_mov_b32_e32 v15, v4
; SI-NEXT:    v_mov_b32_e32 v16, v3
; SI-NEXT:    v_mov_b32_e32 v17, v2
; SI-NEXT:    v_mov_b32_e32 v18, v1
; SI-NEXT:    v_mov_b32_e32 v19, v0
; SI-NEXT:    v_lshrrev_b32_e32 v21, 16, v20
; SI-NEXT:    v_lshrrev_b32_e32 v22, 16, v11
; SI-NEXT:    v_lshrrev_b32_e32 v23, 16, v12
; SI-NEXT:    v_lshrrev_b32_e32 v24, 16, v13
; SI-NEXT:    v_lshrrev_b32_e32 v25, 16, v14
; SI-NEXT:    v_lshrrev_b32_e32 v26, 16, v15
; SI-NEXT:    v_lshrrev_b32_e32 v27, 16, v16
; SI-NEXT:    v_lshrrev_b32_e32 v28, 16, v17
; SI-NEXT:    v_lshrrev_b32_e32 v29, 16, v18
; SI-NEXT:    v_lshrrev_b32_e32 v30, 16, v19
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; SI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_cbranch_execnz .LBB30_3
; SI-NEXT:  ; %bb.1: ; %Flow
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execnz .LBB30_4
; SI-NEXT:  .LBB30_2: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    s_setpc_b64 s[30:31]
; SI-NEXT:  .LBB30_3: ; %cmp.false
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v19
; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v30
; SI-NEXT:    v_or_b32_e32 v0, v0, v1
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v18
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v29
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v17
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v28
; SI-NEXT:    v_or_b32_e32 v2, v2, v3
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v16
; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v27
; SI-NEXT:    v_or_b32_e32 v3, v3, v4
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v15
; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v26
; SI-NEXT:    v_or_b32_e32 v4, v4, v5
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v14
; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v25
; SI-NEXT:    v_or_b32_e32 v5, v5, v6
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v13
; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v24
; SI-NEXT:    v_or_b32_e32 v6, v6, v7
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v12
; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v23
; SI-NEXT:    v_or_b32_e32 v7, v7, v8
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v11
; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v22
; SI-NEXT:    v_or_b32_e32 v8, v8, v9
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v20
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v21
; SI-NEXT:    v_or_b32_e32 v9, v9, v10
; SI-NEXT:    ; implicit-def: $vgpr19
; SI-NEXT:    ; implicit-def: $vgpr18
; SI-NEXT:    ; implicit-def: $vgpr17
; SI-NEXT:    ; implicit-def: $vgpr16
; SI-NEXT:    ; implicit-def: $vgpr15
; SI-NEXT:    ; implicit-def: $vgpr14
; SI-NEXT:    ; implicit-def: $vgpr13
; SI-NEXT:    ; implicit-def: $vgpr12
; SI-NEXT:    ; implicit-def: $vgpr11
; SI-NEXT:    ; implicit-def: $vgpr20
; SI-NEXT:    ; implicit-def: $vgpr30
; SI-NEXT:    ; implicit-def: $vgpr29
; SI-NEXT:    ; implicit-def: $vgpr28
; SI-NEXT:    ; implicit-def: $vgpr27
; SI-NEXT:    ; implicit-def: $vgpr26
; SI-NEXT:    ; implicit-def: $vgpr25
; SI-NEXT:    ; implicit-def: $vgpr24
; SI-NEXT:    ; implicit-def: $vgpr23
; SI-NEXT:    ; implicit-def: $vgpr22
; SI-NEXT:    ; implicit-def: $vgpr21
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB30_2
; SI-NEXT:  .LBB30_4: ; %cmp.true
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v30
; SI-NEXT:    v_cvt_f32_f16_e32 v1, v19
; SI-NEXT:    v_cvt_f32_f16_e32 v2, v29
; SI-NEXT:    v_cvt_f32_f16_e32 v3, v18
; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1
; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT:    v_cvt_f16_f32_e32 v3, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v4, v28
; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT:    v_or_b32_e32 v0, v1, v0
; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v2
; SI-NEXT:    v_or_b32_e32 v1, v3, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v2, v17
; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v4
; SI-NEXT:    v_cvt_f32_f16_e32 v4, v27
; SI-NEXT:    v_cvt_f16_f32_e32 v3, v3
; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT:    v_cvt_f16_f32_e32 v4, v4
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v5, v16
; SI-NEXT:    v_or_b32_e32 v2, v2, v3
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v4
; SI-NEXT:    v_cvt_f32_f16_e32 v4, v26
; SI-NEXT:    v_cvt_f32_f16_e32 v6, v15
; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT:    v_cvt_f16_f32_e32 v5, v5
; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT:    v_cvt_f16_f32_e32 v4, v4
; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT:    v_cvt_f16_f32_e32 v6, v6
; SI-NEXT:    v_or_b32_e32 v3, v5, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v5, v25
; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT:    v_or_b32_e32 v4, v6, v4
; SI-NEXT:    v_cvt_f32_f16_e32 v6, v14
; SI-NEXT:    v_cvt_f32_f16_e32 v7, v24
; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT:    v_cvt_f16_f32_e32 v5, v5
; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT:    v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT:    v_cvt_f16_f32_e32 v6, v6
; SI-NEXT:    v_cvt_f16_f32_e32 v7, v7
; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT:    v_cvt_f32_f16_e32 v8, v13
; SI-NEXT:    v_or_b32_e32 v5, v6, v5
; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v7
; SI-NEXT:    v_cvt_f32_f16_e32 v7, v23
; SI-NEXT:    v_cvt_f32_f16_e32 v9, v12
; SI-NEXT:    v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT:    v_cvt_f16_f32_e32 v8, v8
; SI-NEXT:    v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT:    v_cvt_f16_f32_e32 v7, v7
; SI-NEXT:    v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT:    v_cvt_f16_f32_e32 v9, v9
; SI-NEXT:    v_or_b32_e32 v6, v8, v6
; SI-NEXT:    v_cvt_f32_f16_e32 v8, v22
; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT:    v_or_b32_e32 v7, v9, v7
; SI-NEXT:    v_cvt_f32_f16_e32 v9, v11
; SI-NEXT:    v_cvt_f32_f16_e32 v10, v21
; SI-NEXT:    v_cvt_f32_f16_e32 v11, v20
; SI-NEXT:    v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT:    v_cvt_f16_f32_e32 v8, v8
; SI-NEXT:    v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT:    v_add_f32_e32 v10, 0x38000000, v10
; SI-NEXT:    v_cvt_f16_f32_e32 v9, v9
; SI-NEXT:    v_cvt_f16_f32_e32 v10, v10
; SI-NEXT:    v_add_f32_e32 v11, 0x38000000, v11
; SI-NEXT:    v_cvt_f16_f32_e32 v11, v11
; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT:    v_or_b32_e32 v8, v9, v8
; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v10
; SI-NEXT:    v_or_b32_e32 v9, v11, v9
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v20f16_to_v10f32:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB30_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    v_mov_b32_e32 v10, 0x200
; VI-NEXT:    v_add_f16_sdwa v11, v9, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v9, 0x200, v9
; VI-NEXT:    v_or_b32_e32 v9, v9, v11
; VI-NEXT:    v_add_f16_sdwa v11, v8, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v8, 0x200, v8
; VI-NEXT:    v_or_b32_e32 v8, v8, v11
; VI-NEXT:    v_add_f16_sdwa v11, v7, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v7, 0x200, v7
; VI-NEXT:    v_or_b32_e32 v7, v7, v11
; VI-NEXT:    v_add_f16_sdwa v11, v6, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v6, 0x200, v6
; VI-NEXT:    v_or_b32_e32 v6, v6, v11
; VI-NEXT:    v_add_f16_sdwa v11, v5, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v5, 0x200, v5
; VI-NEXT:    v_or_b32_e32 v5, v5, v11
; VI-NEXT:    v_add_f16_sdwa v11, v4, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v4, 0x200, v4
; VI-NEXT:    v_or_b32_e32 v4, v4, v11
; VI-NEXT:    v_add_f16_sdwa v11, v3, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v3, 0x200, v3
; VI-NEXT:    v_or_b32_e32 v3, v3, v11
; VI-NEXT:    v_add_f16_sdwa v11, v2, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, 0x200, v2
; VI-NEXT:    v_or_b32_e32 v2, v2, v11
; VI-NEXT:    v_add_f16_sdwa v11, v1, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v1, 0x200, v1
; VI-NEXT:    v_add_f16_sdwa v10, v0, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v0, 0x200, v0
; VI-NEXT:    v_or_b32_e32 v1, v1, v11
; VI-NEXT:    v_or_b32_e32 v0, v0, v10
; VI-NEXT:  .LBB30_2: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v20f16_to_v10f32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB30_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    s_movk_i32 s6, 0x200
; GFX9-NEXT:    v_pk_add_f16 v9, v9, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v8, v8, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
; GFX9-NEXT:  .LBB30_2: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v20f16_to_v10f32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB30_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    v_pk_add_f16 v9, v9, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v8, v8, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v7, v7, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v6, v6, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v5, v5, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v4, v4, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v3, v3, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v2, v2, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v1, v1, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v0, v0, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:  .LBB30_2: ; %end
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <20 x half> %a, splat (half 0xH0200)
  %a2 = bitcast <20 x half> %a1 to <10 x float>
  br label %end

cmp.false:
  %a3 = bitcast <20 x half> %a to <10 x float>
  br label %end

end:
  %phi = phi <10 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <10 x float> %phi
}

define inreg <10 x float> @bitcast_v20f16_to_v10f32_scalar(<20 x half> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v20f16_to_v10f32_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_lshr_b32 s13, s25, 16
; SI-NEXT:    s_lshr_b32 s12, s24, 16
; SI-NEXT:    s_lshr_b32 s11, s23, 16
; SI-NEXT:    s_lshr_b32 s10, s22, 16
; SI-NEXT:    s_lshr_b32 s9, s21, 16
; SI-NEXT:    s_lshr_b32 s8, s20, 16
; SI-NEXT:    s_lshr_b32 s7, s19, 16
; SI-NEXT:    s_lshr_b32 s6, s18, 16
; SI-NEXT:    s_lshr_b32 s5, s17, 16
; SI-NEXT:    s_lshr_b32 s4, s16, 16
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc0 .LBB31_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    s_and_b32 s14, s16, 0xffff
; SI-NEXT:    s_lshl_b32 s4, s4, 16
; SI-NEXT:    s_or_b32 s4, s14, s4
; SI-NEXT:    s_and_b32 s14, s17, 0xffff
; SI-NEXT:    s_lshl_b32 s5, s5, 16
; SI-NEXT:    s_or_b32 s5, s14, s5
; SI-NEXT:    s_and_b32 s14, s18, 0xffff
; SI-NEXT:    s_lshl_b32 s6, s6, 16
; SI-NEXT:    s_or_b32 s6, s14, s6
; SI-NEXT:    s_and_b32 s14, s19, 0xffff
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_or_b32 s7, s14, s7
; SI-NEXT:    s_and_b32 s14, s20, 0xffff
; SI-NEXT:    s_lshl_b32 s8, s8, 16
; SI-NEXT:    s_or_b32 s8, s14, s8
; SI-NEXT:    s_and_b32 s14, s21, 0xffff
; SI-NEXT:    s_lshl_b32 s9, s9, 16
; SI-NEXT:    s_or_b32 s9, s14, s9
; SI-NEXT:    s_and_b32 s14, s22, 0xffff
; SI-NEXT:    s_lshl_b32 s10, s10, 16
; SI-NEXT:    s_or_b32 s10, s14, s10
; SI-NEXT:    s_and_b32 s14, s23, 0xffff
; SI-NEXT:    s_lshl_b32 s11, s11, 16
; SI-NEXT:    s_or_b32 s11, s14, s11
; SI-NEXT:    s_and_b32 s14, s24, 0xffff
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_or_b32 s12, s14, s12
; SI-NEXT:    s_and_b32 s14, s25, 0xffff
; SI-NEXT:    s_lshl_b32 s13, s13, 16
; SI-NEXT:    s_or_b32 s13, s14, s13
; SI-NEXT:    v_mov_b32_e32 v0, s4
; SI-NEXT:    v_mov_b32_e32 v1, s5
; SI-NEXT:    v_mov_b32_e32 v2, s6
; SI-NEXT:    v_mov_b32_e32 v3, s7
; SI-NEXT:    v_mov_b32_e32 v4, s8
; SI-NEXT:    v_mov_b32_e32 v5, s9
; SI-NEXT:    v_mov_b32_e32 v6, s10
; SI-NEXT:    v_mov_b32_e32 v7, s11
; SI-NEXT:    v_mov_b32_e32 v8, s12
; SI-NEXT:    v_mov_b32_e32 v9, s13
; SI-NEXT:    s_setpc_b64 s[30:31]
; SI-NEXT:  .LBB31_2: ; %cmp.true
; SI-NEXT:    v_cvt_f32_f16_e32 v0, s4
; SI-NEXT:    v_cvt_f32_f16_e32 v1, s16
; SI-NEXT:    v_cvt_f32_f16_e32 v2, s5
; SI-NEXT:    v_cvt_f32_f16_e32 v3, s17
; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1
; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT:    v_cvt_f16_f32_e32 v3, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v4, s6
; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT:    v_or_b32_e32 v0, v1, v0
; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v2
; SI-NEXT:    v_or_b32_e32 v1, v3, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v2, s18
; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v4
; SI-NEXT:    v_cvt_f32_f16_e32 v4, s7
; SI-NEXT:    v_cvt_f16_f32_e32 v3, v3
; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT:    v_cvt_f16_f32_e32 v4, v4
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v5, s19
; SI-NEXT:    v_or_b32_e32 v2, v2, v3
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v4
; SI-NEXT:    v_cvt_f32_f16_e32 v4, s8
; SI-NEXT:    v_cvt_f32_f16_e32 v6, s20
; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT:    v_cvt_f16_f32_e32 v5, v5
; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT:    v_cvt_f16_f32_e32 v4, v4
; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT:    v_cvt_f16_f32_e32 v6, v6
; SI-NEXT:    v_or_b32_e32 v3, v5, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v5, s9
; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT:    v_or_b32_e32 v4, v6, v4
; SI-NEXT:    v_cvt_f32_f16_e32 v6, s21
; SI-NEXT:    v_cvt_f32_f16_e32 v7, s10
; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT:    v_cvt_f16_f32_e32 v5, v5
; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT:    v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT:    v_cvt_f16_f32_e32 v6, v6
; SI-NEXT:    v_cvt_f16_f32_e32 v7, v7
; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT:    v_cvt_f32_f16_e32 v8, s22
; SI-NEXT:    v_or_b32_e32 v5, v6, v5
; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v7
; SI-NEXT:    v_cvt_f32_f16_e32 v7, s11
; SI-NEXT:    v_cvt_f32_f16_e32 v9, s23
; SI-NEXT:    v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT:    v_cvt_f16_f32_e32 v8, v8
; SI-NEXT:    v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT:    v_cvt_f16_f32_e32 v7, v7
; SI-NEXT:    v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT:    v_cvt_f16_f32_e32 v9, v9
; SI-NEXT:    v_or_b32_e32 v6, v8, v6
; SI-NEXT:    v_cvt_f32_f16_e32 v8, s12
; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT:    v_or_b32_e32 v7, v9, v7
; SI-NEXT:    v_cvt_f32_f16_e32 v9, s24
; SI-NEXT:    v_cvt_f32_f16_e32 v10, s13
; SI-NEXT:    v_cvt_f32_f16_e32 v11, s25
; SI-NEXT:    v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT:    v_cvt_f16_f32_e32 v8, v8
; SI-NEXT:    v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT:    v_add_f32_e32 v10, 0x38000000, v10
; SI-NEXT:    v_cvt_f16_f32_e32 v9, v9
; SI-NEXT:    v_cvt_f16_f32_e32 v10, v10
; SI-NEXT:    v_add_f32_e32 v11, 0x38000000, v11
; SI-NEXT:    v_cvt_f16_f32_e32 v11, v11
; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT:    v_or_b32_e32 v8, v9, v8
; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v10
; SI-NEXT:    v_or_b32_e32 v9, v11, v9
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v20f16_to_v10f32_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc0 .LBB31_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s17
; VI-NEXT:    v_mov_b32_e32 v2, s18
; VI-NEXT:    v_mov_b32_e32 v3, s19
; VI-NEXT:    v_mov_b32_e32 v4, s20
; VI-NEXT:    v_mov_b32_e32 v5, s21
; VI-NEXT:    v_mov_b32_e32 v6, s22
; VI-NEXT:    v_mov_b32_e32 v7, s23
; VI-NEXT:    v_mov_b32_e32 v8, s24
; VI-NEXT:    v_mov_b32_e32 v9, s25
; VI-NEXT:    s_setpc_b64 s[30:31]
; VI-NEXT:  .LBB31_2: ; %cmp.true
; VI-NEXT:    s_lshr_b32 s4, s25, 16
; VI-NEXT:    v_mov_b32_e32 v0, 0x200
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, s25, v0
; VI-NEXT:    s_lshr_b32 s4, s24, 16
; VI-NEXT:    v_or_b32_e32 v9, v2, v1
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, s24, v0
; VI-NEXT:    s_lshr_b32 s4, s23, 16
; VI-NEXT:    v_or_b32_e32 v8, v2, v1
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, s23, v0
; VI-NEXT:    s_lshr_b32 s4, s22, 16
; VI-NEXT:    v_or_b32_e32 v7, v2, v1
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, s22, v0
; VI-NEXT:    s_lshr_b32 s4, s21, 16
; VI-NEXT:    v_or_b32_e32 v6, v2, v1
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, s21, v0
; VI-NEXT:    s_lshr_b32 s4, s20, 16
; VI-NEXT:    v_or_b32_e32 v5, v2, v1
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, s20, v0
; VI-NEXT:    s_lshr_b32 s4, s19, 16
; VI-NEXT:    v_or_b32_e32 v4, v2, v1
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, s19, v0
; VI-NEXT:    s_lshr_b32 s4, s18, 16
; VI-NEXT:    v_or_b32_e32 v3, v2, v1
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, s18, v0
; VI-NEXT:    s_lshr_b32 s4, s17, 16
; VI-NEXT:    v_or_b32_e32 v2, v2, v1
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v10, s17, v0
; VI-NEXT:    s_lshr_b32 s4, s16, 16
; VI-NEXT:    v_or_b32_e32 v1, v10, v1
; VI-NEXT:    v_mov_b32_e32 v10, s4
; VI-NEXT:    v_add_f16_sdwa v10, v10, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v0, s16, v0
; VI-NEXT:    v_or_b32_e32 v0, v0, v10
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v20f16_to_v10f32_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc0 .LBB31_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s17
; GFX9-NEXT:    v_mov_b32_e32 v2, s18
; GFX9-NEXT:    v_mov_b32_e32 v3, s19
; GFX9-NEXT:    v_mov_b32_e32 v4, s20
; GFX9-NEXT:    v_mov_b32_e32 v5, s21
; GFX9-NEXT:    v_mov_b32_e32 v6, s22
; GFX9-NEXT:    v_mov_b32_e32 v7, s23
; GFX9-NEXT:    v_mov_b32_e32 v8, s24
; GFX9-NEXT:    v_mov_b32_e32 v9, s25
; GFX9-NEXT:    s_setpc_b64 s[30:31]
; GFX9-NEXT:  .LBB31_2: ; %cmp.true
; GFX9-NEXT:    v_mov_b32_e32 v0, 0x200
; GFX9-NEXT:    v_pk_add_f16 v9, s25, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v8, s24, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v7, s23, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v6, s22, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v5, s21, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v4, s20, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v3, s19, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v20f16_to_v10f32_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s15, s3
; GFX11-NEXT:    s_mov_b32 s14, s2
; GFX11-NEXT:    s_mov_b32 s13, s1
; GFX11-NEXT:    s_mov_b32 s12, s0
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc0 .LBB31_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-NEXT:    v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
; GFX11-NEXT:    v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT:    s_setpc_b64 s[30:31]
; GFX11-NEXT:  .LBB31_2: ; %cmp.true
; GFX11-NEXT:    v_pk_add_f16 v9, s21, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v8, s20, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v7, s19, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v6, s18, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v5, s17, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v4, s16, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v3, s15, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v2, s14, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v1, s13, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v0, s12, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <20 x half> %a, splat (half 0xH0200)
  %a2 = bitcast <20 x half> %a1 to <10 x float>
  br label %end

cmp.false:
  %a3 = bitcast <20 x half> %a to <10 x float>
  br label %end

end:
  %phi = phi <10 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <10 x float> %phi
}

define <40 x i8> @bitcast_v10f32_to_v40i8(<10 x float> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v10f32_to_v40i8:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
; SI-NEXT:    ; implicit-def: $vgpr35
; SI-NEXT:    ; implicit-def: $vgpr33
; SI-NEXT:    ; implicit-def: $vgpr32
; SI-NEXT:    ; implicit-def: $vgpr48
; SI-NEXT:    ; implicit-def: $vgpr39
; SI-NEXT:    ; implicit-def: $vgpr38
; SI-NEXT:    ; implicit-def: $vgpr28
; SI-NEXT:    ; implicit-def: $vgpr27
; SI-NEXT:    ; implicit-def: $vgpr26
; SI-NEXT:    ; implicit-def: $vgpr37
; SI-NEXT:    ; implicit-def: $vgpr36
; SI-NEXT:    ; implicit-def: $vgpr34
; SI-NEXT:    ; implicit-def: $vgpr22
; SI-NEXT:    ; implicit-def: $vgpr21
; SI-NEXT:    ; implicit-def: $vgpr20
; SI-NEXT:    ; implicit-def: $vgpr31
; SI-NEXT:    ; implicit-def: $vgpr30
; SI-NEXT:    ; implicit-def: $vgpr29
; SI-NEXT:    ; implicit-def: $vgpr16
; SI-NEXT:    ; implicit-def: $vgpr15
; SI-NEXT:    ; implicit-def: $vgpr14
; SI-NEXT:    ; implicit-def: $vgpr25
; SI-NEXT:    ; implicit-def: $vgpr24
; SI-NEXT:    ; implicit-def: $vgpr23
; SI-NEXT:    ; implicit-def: $vgpr13
; SI-NEXT:    ; implicit-def: $vgpr12
; SI-NEXT:    ; implicit-def: $vgpr11
; SI-NEXT:    ; implicit-def: $vgpr19
; SI-NEXT:    ; implicit-def: $vgpr18
; SI-NEXT:    ; implicit-def: $vgpr17
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB32_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    v_alignbit_b32 v11, v10, v9, 24
; SI-NEXT:    v_alignbit_b32 v12, v10, v9, 16
; SI-NEXT:    v_alignbit_b32 v13, v10, v9, 8
; SI-NEXT:    v_alignbit_b32 v14, v8, v7, 24
; SI-NEXT:    v_alignbit_b32 v15, v8, v7, 16
; SI-NEXT:    v_alignbit_b32 v16, v8, v7, 8
; SI-NEXT:    v_alignbit_b32 v20, v6, v5, 24
; SI-NEXT:    v_alignbit_b32 v21, v6, v5, 16
; SI-NEXT:    v_alignbit_b32 v22, v6, v5, 8
; SI-NEXT:    v_alignbit_b32 v26, v4, v3, 24
; SI-NEXT:    v_alignbit_b32 v27, v4, v3, 16
; SI-NEXT:    v_alignbit_b32 v28, v4, v3, 8
; SI-NEXT:    v_alignbit_b32 v32, v2, v1, 24
; SI-NEXT:    v_alignbit_b32 v33, v2, v1, 16
; SI-NEXT:    v_alignbit_b32 v35, v2, v1, 8
; SI-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; SI-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; SI-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; SI-NEXT:    v_lshrrev_b32_e32 v23, 24, v8
; SI-NEXT:    v_lshrrev_b32_e32 v24, 16, v8
; SI-NEXT:    v_lshrrev_b32_e32 v25, 8, v8
; SI-NEXT:    v_lshrrev_b32_e32 v29, 24, v6
; SI-NEXT:    v_lshrrev_b32_e32 v30, 16, v6
; SI-NEXT:    v_lshrrev_b32_e32 v31, 8, v6
; SI-NEXT:    v_lshrrev_b32_e32 v34, 24, v4
; SI-NEXT:    v_lshrrev_b32_e32 v36, 16, v4
; SI-NEXT:    v_lshrrev_b32_e32 v37, 8, v4
; SI-NEXT:    v_lshrrev_b32_e32 v38, 24, v2
; SI-NEXT:    v_lshrrev_b32_e32 v39, 16, v2
; SI-NEXT:    v_lshrrev_b32_e32 v48, 8, v2
; SI-NEXT:  .LBB32_2: ; %Flow
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB32_4
; SI-NEXT:  ; %bb.3: ; %cmp.true
; SI-NEXT:    v_add_f32_e32 v2, 1.0, v2
; SI-NEXT:    v_add_f32_e32 v1, 1.0, v1
; SI-NEXT:    v_add_f32_e32 v4, 1.0, v4
; SI-NEXT:    v_add_f32_e32 v3, 1.0, v3
; SI-NEXT:    v_add_f32_e32 v6, 1.0, v6
; SI-NEXT:    v_add_f32_e32 v5, 1.0, v5
; SI-NEXT:    v_add_f32_e32 v8, 1.0, v8
; SI-NEXT:    v_add_f32_e32 v7, 1.0, v7
; SI-NEXT:    v_add_f32_e32 v10, 1.0, v10
; SI-NEXT:    v_add_f32_e32 v9, 1.0, v9
; SI-NEXT:    v_alignbit_b32 v11, v10, v9, 24
; SI-NEXT:    v_alignbit_b32 v12, v10, v9, 16
; SI-NEXT:    v_alignbit_b32 v13, v10, v9, 8
; SI-NEXT:    v_alignbit_b32 v14, v8, v7, 24
; SI-NEXT:    v_alignbit_b32 v15, v8, v7, 16
; SI-NEXT:    v_alignbit_b32 v16, v8, v7, 8
; SI-NEXT:    v_alignbit_b32 v20, v6, v5, 24
; SI-NEXT:    v_alignbit_b32 v21, v6, v5, 16
; SI-NEXT:    v_alignbit_b32 v22, v6, v5, 8
; SI-NEXT:    v_alignbit_b32 v26, v4, v3, 24
; SI-NEXT:    v_alignbit_b32 v27, v4, v3, 16
; SI-NEXT:    v_alignbit_b32 v28, v4, v3, 8
; SI-NEXT:    v_alignbit_b32 v32, v2, v1, 24
; SI-NEXT:    v_alignbit_b32 v33, v2, v1, 16
; SI-NEXT:    v_alignbit_b32 v35, v2, v1, 8
; SI-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; SI-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; SI-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; SI-NEXT:    v_lshrrev_b32_e32 v23, 24, v8
; SI-NEXT:    v_lshrrev_b32_e32 v24, 16, v8
; SI-NEXT:    v_lshrrev_b32_e32 v25, 8, v8
; SI-NEXT:    v_lshrrev_b32_e32 v29, 24, v6
; SI-NEXT:    v_lshrrev_b32_e32 v30, 16, v6
; SI-NEXT:    v_lshrrev_b32_e32 v31, 8, v6
; SI-NEXT:    v_lshrrev_b32_e32 v34, 24, v4
; SI-NEXT:    v_lshrrev_b32_e32 v36, 16, v4
; SI-NEXT:    v_lshrrev_b32_e32 v37, 8, v4
; SI-NEXT:    v_lshrrev_b32_e32 v38, 24, v2
; SI-NEXT:    v_lshrrev_b32_e32 v39, 16, v2
; SI-NEXT:    v_lshrrev_b32_e32 v48, 8, v2
; SI-NEXT:  .LBB32_4: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1
; SI-NEXT:    v_lshlrev_b32_e32 v35, 8, v35
; SI-NEXT:    v_and_b32_e32 v33, 0xff, v33
; SI-NEXT:    v_or_b32_e32 v1, v1, v35
; SI-NEXT:    v_lshlrev_b32_e32 v33, 16, v33
; SI-NEXT:    v_lshlrev_b32_e32 v32, 24, v32
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v32, v32, v33
; SI-NEXT:    v_or_b32_e32 v1, v1, v32
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v2
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v48
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v39
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v32, 24, v38
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v32, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v3
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v28
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v27
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v26
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v4
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v37
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v36
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v34
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v5
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v22
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v21
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v20
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v6
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v31
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v30
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v29
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v7
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v16
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v15
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v14
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v8
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v25
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v24
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v23
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v9
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v13
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v12
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v11
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v10
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v19
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v18
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v17
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v10f32_to_v40i8:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
; VI-NEXT:    ; implicit-def: $vgpr16
; VI-NEXT:    ; implicit-def: $vgpr48
; VI-NEXT:    ; implicit-def: $vgpr15
; VI-NEXT:    ; implicit-def: $vgpr39
; VI-NEXT:    ; implicit-def: $vgpr38
; VI-NEXT:    ; implicit-def: $vgpr37
; VI-NEXT:    ; implicit-def: $vgpr36
; VI-NEXT:    ; implicit-def: $vgpr35
; VI-NEXT:    ; implicit-def: $vgpr14
; VI-NEXT:    ; implicit-def: $vgpr34
; VI-NEXT:    ; implicit-def: $vgpr33
; VI-NEXT:    ; implicit-def: $vgpr32
; VI-NEXT:    ; implicit-def: $vgpr31
; VI-NEXT:    ; implicit-def: $vgpr30
; VI-NEXT:    ; implicit-def: $vgpr13
; VI-NEXT:    ; implicit-def: $vgpr29
; VI-NEXT:    ; implicit-def: $vgpr28
; VI-NEXT:    ; implicit-def: $vgpr27
; VI-NEXT:    ; implicit-def: $vgpr26
; VI-NEXT:    ; implicit-def: $vgpr25
; VI-NEXT:    ; implicit-def: $vgpr12
; VI-NEXT:    ; implicit-def: $vgpr24
; VI-NEXT:    ; implicit-def: $vgpr23
; VI-NEXT:    ; implicit-def: $vgpr22
; VI-NEXT:    ; implicit-def: $vgpr21
; VI-NEXT:    ; implicit-def: $vgpr20
; VI-NEXT:    ; implicit-def: $vgpr19
; VI-NEXT:    ; implicit-def: $vgpr18
; VI-NEXT:    ; implicit-def: $vgpr17
; VI-NEXT:    ; implicit-def: $vgpr11
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB32_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; VI-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; VI-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; VI-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; VI-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; VI-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; VI-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; VI-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; VI-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
; VI-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
; VI-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
; VI-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
; VI-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
; VI-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
; VI-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
; VI-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
; VI-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
; VI-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; VI-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; VI-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; VI-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
; VI-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
; VI-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
; VI-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
; VI-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
; VI-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
; VI-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
; VI-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
; VI-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
; VI-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; VI-NEXT:  .LBB32_2: ; %Flow
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB32_4
; VI-NEXT:  ; %bb.3: ; %cmp.true
; VI-NEXT:    v_add_f32_e32 v10, 1.0, v10
; VI-NEXT:    v_add_f32_e32 v9, 1.0, v9
; VI-NEXT:    v_add_f32_e32 v8, 1.0, v8
; VI-NEXT:    v_add_f32_e32 v7, 1.0, v7
; VI-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; VI-NEXT:    v_add_f32_e32 v6, 1.0, v6
; VI-NEXT:    v_add_f32_e32 v5, 1.0, v5
; VI-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; VI-NEXT:    v_add_f32_e32 v4, 1.0, v4
; VI-NEXT:    v_add_f32_e32 v3, 1.0, v3
; VI-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; VI-NEXT:    v_add_f32_e32 v2, 1.0, v2
; VI-NEXT:    v_add_f32_e32 v1, 1.0, v1
; VI-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; VI-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; VI-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; VI-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; VI-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; VI-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
; VI-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
; VI-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
; VI-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
; VI-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
; VI-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
; VI-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
; VI-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
; VI-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
; VI-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; VI-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; VI-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; VI-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
; VI-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
; VI-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
; VI-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
; VI-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
; VI-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
; VI-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
; VI-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
; VI-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
; VI-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; VI-NEXT:  .LBB32_4: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_mov_b32 s4, 0xc0c0004
; VI-NEXT:    v_perm_b32 v15, v48, v15, s4
; VI-NEXT:    v_perm_b32 v1, v1, v16, s4
; VI-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT:    v_or_b32_e32 v1, v1, v15
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT:    v_perm_b32 v1, v2, v39, s4
; VI-NEXT:    v_perm_b32 v2, v38, v37, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v35, v14, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
; VI-NEXT:    v_perm_b32 v1, v3, v36, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v33, v32, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; VI-NEXT:    v_perm_b32 v1, v4, v34, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v30, v13, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; VI-NEXT:    v_perm_b32 v1, v5, v31, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v28, v27, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; VI-NEXT:    v_perm_b32 v1, v6, v29, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v25, v12, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; VI-NEXT:    v_perm_b32 v1, v7, v26, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v23, v22, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; VI-NEXT:    v_perm_b32 v1, v8, v24, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v20, v11, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; VI-NEXT:    v_perm_b32 v1, v9, v21, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v18, v17, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; VI-NEXT:    v_perm_b32 v1, v10, v19, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v10f32_to_v40i8:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
; GFX9-NEXT:    ; implicit-def: $vgpr16
; GFX9-NEXT:    ; implicit-def: $vgpr48
; GFX9-NEXT:    ; implicit-def: $vgpr15
; GFX9-NEXT:    ; implicit-def: $vgpr39
; GFX9-NEXT:    ; implicit-def: $vgpr38
; GFX9-NEXT:    ; implicit-def: $vgpr37
; GFX9-NEXT:    ; implicit-def: $vgpr36
; GFX9-NEXT:    ; implicit-def: $vgpr35
; GFX9-NEXT:    ; implicit-def: $vgpr14
; GFX9-NEXT:    ; implicit-def: $vgpr34
; GFX9-NEXT:    ; implicit-def: $vgpr33
; GFX9-NEXT:    ; implicit-def: $vgpr32
; GFX9-NEXT:    ; implicit-def: $vgpr31
; GFX9-NEXT:    ; implicit-def: $vgpr30
; GFX9-NEXT:    ; implicit-def: $vgpr13
; GFX9-NEXT:    ; implicit-def: $vgpr29
; GFX9-NEXT:    ; implicit-def: $vgpr28
; GFX9-NEXT:    ; implicit-def: $vgpr27
; GFX9-NEXT:    ; implicit-def: $vgpr26
; GFX9-NEXT:    ; implicit-def: $vgpr25
; GFX9-NEXT:    ; implicit-def: $vgpr12
; GFX9-NEXT:    ; implicit-def: $vgpr24
; GFX9-NEXT:    ; implicit-def: $vgpr23
; GFX9-NEXT:    ; implicit-def: $vgpr22
; GFX9-NEXT:    ; implicit-def: $vgpr21
; GFX9-NEXT:    ; implicit-def: $vgpr20
; GFX9-NEXT:    ; implicit-def: $vgpr19
; GFX9-NEXT:    ; implicit-def: $vgpr18
; GFX9-NEXT:    ; implicit-def: $vgpr17
; GFX9-NEXT:    ; implicit-def: $vgpr11
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB32_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX9-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX9-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX9-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX9-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX9-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
; GFX9-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
; GFX9-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
; GFX9-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
; GFX9-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; GFX9-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; GFX9-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
; GFX9-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
; GFX9-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
; GFX9-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX9-NEXT:  .LBB32_2: ; %Flow
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB32_4
; GFX9-NEXT:  ; %bb.3: ; %cmp.true
; GFX9-NEXT:    v_add_f32_e32 v10, 1.0, v10
; GFX9-NEXT:    v_add_f32_e32 v9, 1.0, v9
; GFX9-NEXT:    v_add_f32_e32 v8, 1.0, v8
; GFX9-NEXT:    v_add_f32_e32 v7, 1.0, v7
; GFX9-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX9-NEXT:    v_add_f32_e32 v6, 1.0, v6
; GFX9-NEXT:    v_add_f32_e32 v5, 1.0, v5
; GFX9-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX9-NEXT:    v_add_f32_e32 v4, 1.0, v4
; GFX9-NEXT:    v_add_f32_e32 v3, 1.0, v3
; GFX9-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX9-NEXT:    v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT:    v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX9-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX9-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
; GFX9-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
; GFX9-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
; GFX9-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
; GFX9-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; GFX9-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; GFX9-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
; GFX9-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
; GFX9-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
; GFX9-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX9-NEXT:  .LBB32_4: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_mov_b32 s4, 0xc0c0004
; GFX9-NEXT:    v_perm_b32 v15, v48, v15, s4
; GFX9-NEXT:    v_perm_b32 v1, v1, v16, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v15, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen
; GFX9-NEXT:    v_perm_b32 v1, v2, v39, s4
; GFX9-NEXT:    v_perm_b32 v2, v38, v37, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT:    v_perm_b32 v1, v3, v36, s4
; GFX9-NEXT:    v_perm_b32 v2, v35, v14, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT:    v_perm_b32 v1, v4, v34, s4
; GFX9-NEXT:    v_perm_b32 v2, v33, v32, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; GFX9-NEXT:    v_perm_b32 v1, v5, v31, s4
; GFX9-NEXT:    v_perm_b32 v2, v30, v13, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT:    v_perm_b32 v1, v6, v29, s4
; GFX9-NEXT:    v_perm_b32 v2, v28, v27, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; GFX9-NEXT:    v_perm_b32 v1, v7, v26, s4
; GFX9-NEXT:    v_perm_b32 v2, v25, v12, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT:    v_perm_b32 v1, v8, v24, s4
; GFX9-NEXT:    v_perm_b32 v2, v23, v22, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; GFX9-NEXT:    v_perm_b32 v1, v9, v21, s4
; GFX9-NEXT:    v_perm_b32 v2, v20, v11, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT:    v_perm_b32 v1, v10, v19, s4
; GFX9-NEXT:    v_perm_b32 v2, v18, v17, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v10f32_to_v40i8:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v11
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr11_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB32_2
; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v18, 8, v10
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v9
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v20, 24, v8
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v8
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v22, 8, v7
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v6
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v6
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v5
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v4
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v4
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v3
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v28, 24, v2
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v2
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX11-TRUE16-NEXT:  .LBB32_2: ; %Flow
; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB32_4
; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
; GFX11-TRUE16-NEXT:    v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v9, 1.0, v9
; GFX11-TRUE16-NEXT:    v_dual_add_f32 v10, 1.0, v10 :: v_dual_add_f32 v1, 1.0, v1
; GFX11-TRUE16-NEXT:    v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v7, 1.0, v7
; GFX11-TRUE16-NEXT:    v_dual_add_f32 v8, 1.0, v8 :: v_dual_add_f32 v3, 1.0, v3
; GFX11-TRUE16-NEXT:    v_dual_add_f32 v6, 1.0, v6 :: v_dual_add_f32 v5, 1.0, v5
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v18, 8, v10
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v9
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v20, 24, v8
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v8
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v22, 8, v7
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v6
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v6
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v5
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v4
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v4
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v3
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v28, 24, v2
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v2
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX11-TRUE16-NEXT:  .LBB32_4: ; %end
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v31.l, v1.h
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_perm_b32 v1, v1, v16, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v16, v2, v30, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v29, v3, v29, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v3.h
; GFX11-TRUE16-NEXT:    v_perm_b32 v15, v31, v15, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v31.l, v5.h
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v30.l, v4.h
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
; GFX11-TRUE16-NEXT:    v_perm_b32 v5, v5, v25, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v1, v15, 16, v1
; GFX11-TRUE16-NEXT:    v_perm_b32 v13, v31, v13, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v3, v3, v14, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v4, v4, v27, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v14, v30, v26, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v15.l, v6.h
; GFX11-TRUE16-NEXT:    v_perm_b32 v2, v2, v28, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v5, v13, 16, v5
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v7.h
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v4, v14, 16, v4
; GFX11-TRUE16-NEXT:    v_perm_b32 v14, v15, v23, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v15.l, v8.h
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v2, v2, 16, v16
; GFX11-TRUE16-NEXT:    v_perm_b32 v12, v13, v12, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v9.h
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.l, v10.h
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, v6, v24, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, v7, v22, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v8, v8, v21, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v15, v15, v20, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v9, v9, v19, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v11, v13, v11, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v10, v10, v18, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v13, v16, v17, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v3, v3, 16, v29
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v6, v14, 16, v6
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v7, v12, 16, v7
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v8, v15, 16, v8
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v9, v11, 16, v9
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v10, v13, 16, v10
; GFX11-TRUE16-NEXT:    s_clause 0x2
; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[1:4], off
; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
; GFX11-TRUE16-NEXT:    scratch_store_b64 v0, v[9:10], off offset:32
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v10f32_to_v40i8:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v11
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB32_2
; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX11-FAKE16-NEXT:  .LBB32_2: ; %Flow
; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB32_4
; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
; GFX11-FAKE16-NEXT:    v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v9, 1.0, v9
; GFX11-FAKE16-NEXT:    v_dual_add_f32 v10, 1.0, v10 :: v_dual_add_f32 v1, 1.0, v1
; GFX11-FAKE16-NEXT:    v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v7, 1.0, v7
; GFX11-FAKE16-NEXT:    v_dual_add_f32 v8, 1.0, v8 :: v_dual_add_f32 v3, 1.0, v3
; GFX11-FAKE16-NEXT:    v_dual_add_f32 v6, 1.0, v6 :: v_dual_add_f32 v5, 1.0, v5
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX11-FAKE16-NEXT:  .LBB32_4: ; %end
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v3, v36, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v35, v14, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v5, v31, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v30, v13, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v1, v16, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v48, v15, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v2, v39, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v16, v38, v37, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v4, v34, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v32, v33, v32, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v3, v14, 16, v3
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v5, v13, 16, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v6, v29, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v28, v27, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v7, v26, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v25, v12, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v8, v24, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v23, v22, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v15, 16, v1
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v9, v21, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v20, v11, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v10, v19, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v18, v17, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, v16, 16, v2
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v4, v32, 16, v4
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v6, v13, 16, v6
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v7, v12, 16, v7
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v8, v14, 16, v8
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v9, v11, 16, v9
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v10, v15, 16, v10
; GFX11-FAKE16-NEXT:    s_clause 0x2
; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[1:4], off
; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
; GFX11-FAKE16-NEXT:    scratch_store_b64 v0, v[9:10], off offset:32
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <10 x float> %a, splat (float 1.000000e+00)
  %a2 = bitcast <10 x float> %a1 to <40 x i8>
  br label %end

cmp.false:
  %a3 = bitcast <10 x float> %a to <40 x i8>
  br label %end

end:
  %phi = phi <40 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <40 x i8> %phi
}

define inreg <40 x i8> @bitcast_v10f32_to_v40i8_scalar(<10 x float> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v10f32_to_v40i8_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc0 .LBB33_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    s_lshr_b32 s58, s25, 24
; SI-NEXT:    s_lshr_b32 s59, s25, 16
; SI-NEXT:    s_lshr_b32 s60, s25, 8
; SI-NEXT:    s_lshr_b32 s61, s23, 24
; SI-NEXT:    s_lshr_b32 s62, s23, 16
; SI-NEXT:    s_lshr_b32 s63, s23, 8
; SI-NEXT:    s_lshr_b32 s72, s21, 24
; SI-NEXT:    s_lshr_b32 s73, s21, 16
; SI-NEXT:    s_lshr_b32 s74, s21, 8
; SI-NEXT:    s_lshr_b32 s75, s19, 24
; SI-NEXT:    s_lshr_b32 s76, s19, 16
; SI-NEXT:    s_lshr_b32 s77, s19, 8
; SI-NEXT:    s_lshr_b32 s78, s17, 24
; SI-NEXT:    s_lshr_b32 s79, s17, 16
; SI-NEXT:    s_lshr_b32 s88, s17, 8
; SI-NEXT:    s_lshr_b64 s[4:5], s[24:25], 24
; SI-NEXT:    s_lshr_b64 s[6:7], s[24:25], 16
; SI-NEXT:    s_lshr_b64 s[8:9], s[24:25], 8
; SI-NEXT:    s_lshr_b64 s[10:11], s[22:23], 24
; SI-NEXT:    s_lshr_b64 s[12:13], s[22:23], 16
; SI-NEXT:    s_lshr_b64 s[14:15], s[22:23], 8
; SI-NEXT:    s_lshr_b64 s[26:27], s[20:21], 24
; SI-NEXT:    s_lshr_b64 s[28:29], s[20:21], 16
; SI-NEXT:    s_lshr_b64 s[40:41], s[20:21], 8
; SI-NEXT:    s_lshr_b64 s[42:43], s[18:19], 24
; SI-NEXT:    s_lshr_b64 s[44:45], s[18:19], 16
; SI-NEXT:    s_lshr_b64 s[46:47], s[18:19], 8
; SI-NEXT:    s_lshr_b64 s[56:57], s[16:17], 24
; SI-NEXT:    v_mov_b32_e32 v8, s18
; SI-NEXT:    v_mov_b32_e32 v7, s19
; SI-NEXT:    s_lshr_b64 s[18:19], s[16:17], 16
; SI-NEXT:    v_mov_b32_e32 v10, s16
; SI-NEXT:    v_mov_b32_e32 v9, s17
; SI-NEXT:    s_lshr_b64 s[16:17], s[16:17], 8
; SI-NEXT:    v_mov_b32_e32 v6, s20
; SI-NEXT:    v_mov_b32_e32 v5, s21
; SI-NEXT:    v_mov_b32_e32 v4, s22
; SI-NEXT:    v_mov_b32_e32 v3, s23
; SI-NEXT:    v_mov_b32_e32 v2, s24
; SI-NEXT:    v_mov_b32_e32 v1, s25
; SI-NEXT:    v_mov_b32_e32 v25, s88
; SI-NEXT:    v_mov_b32_e32 v24, s79
; SI-NEXT:    v_mov_b32_e32 v23, s78
; SI-NEXT:    v_mov_b32_e32 v22, s77
; SI-NEXT:    v_mov_b32_e32 v21, s76
; SI-NEXT:    v_mov_b32_e32 v20, s75
; SI-NEXT:    v_mov_b32_e32 v19, s74
; SI-NEXT:    v_mov_b32_e32 v18, s73
; SI-NEXT:    v_mov_b32_e32 v17, s72
; SI-NEXT:    v_mov_b32_e32 v16, s63
; SI-NEXT:    v_mov_b32_e32 v15, s62
; SI-NEXT:    v_mov_b32_e32 v14, s61
; SI-NEXT:    v_mov_b32_e32 v13, s60
; SI-NEXT:    v_mov_b32_e32 v12, s59
; SI-NEXT:    v_mov_b32_e32 v11, s58
; SI-NEXT:    s_branch .LBB33_3
; SI-NEXT:  .LBB33_2: ; %cmp.true
; SI-NEXT:    v_add_f32_e64 v5, s21, 1.0
; SI-NEXT:    v_add_f32_e64 v6, s20, 1.0
; SI-NEXT:    v_add_f32_e64 v9, s17, 1.0
; SI-NEXT:    v_add_f32_e64 v10, s16, 1.0
; SI-NEXT:    v_add_f32_e64 v7, s19, 1.0
; SI-NEXT:    v_add_f32_e64 v8, s18, 1.0
; SI-NEXT:    v_readfirstlane_b32 s16, v6
; SI-NEXT:    v_readfirstlane_b32 s17, v5
; SI-NEXT:    v_add_f32_e64 v3, s23, 1.0
; SI-NEXT:    v_add_f32_e64 v4, s22, 1.0
; SI-NEXT:    v_add_f32_e64 v1, s25, 1.0
; SI-NEXT:    v_add_f32_e64 v2, s24, 1.0
; SI-NEXT:    s_lshr_b64 s[26:27], s[16:17], 24
; SI-NEXT:    s_lshr_b64 s[28:29], s[16:17], 16
; SI-NEXT:    s_lshr_b64 s[40:41], s[16:17], 8
; SI-NEXT:    v_readfirstlane_b32 s16, v8
; SI-NEXT:    v_readfirstlane_b32 s17, v7
; SI-NEXT:    v_readfirstlane_b32 s8, v2
; SI-NEXT:    v_readfirstlane_b32 s9, v1
; SI-NEXT:    v_readfirstlane_b32 s14, v4
; SI-NEXT:    v_readfirstlane_b32 s15, v3
; SI-NEXT:    s_lshr_b64 s[42:43], s[16:17], 24
; SI-NEXT:    s_lshr_b64 s[44:45], s[16:17], 16
; SI-NEXT:    s_lshr_b64 s[46:47], s[16:17], 8
; SI-NEXT:    v_readfirstlane_b32 s16, v10
; SI-NEXT:    v_readfirstlane_b32 s17, v9
; SI-NEXT:    s_lshr_b64 s[4:5], s[8:9], 24
; SI-NEXT:    s_lshr_b64 s[6:7], s[8:9], 16
; SI-NEXT:    s_lshr_b64 s[8:9], s[8:9], 8
; SI-NEXT:    s_lshr_b64 s[10:11], s[14:15], 24
; SI-NEXT:    s_lshr_b64 s[12:13], s[14:15], 16
; SI-NEXT:    s_lshr_b64 s[14:15], s[14:15], 8
; SI-NEXT:    s_lshr_b64 s[56:57], s[16:17], 24
; SI-NEXT:    s_lshr_b64 s[18:19], s[16:17], 16
; SI-NEXT:    s_lshr_b64 s[16:17], s[16:17], 8
; SI-NEXT:    v_lshrrev_b32_e32 v11, 24, v1
; SI-NEXT:    v_lshrrev_b32_e32 v12, 16, v1
; SI-NEXT:    v_lshrrev_b32_e32 v13, 8, v1
; SI-NEXT:    v_lshrrev_b32_e32 v14, 24, v3
; SI-NEXT:    v_lshrrev_b32_e32 v15, 16, v3
; SI-NEXT:    v_lshrrev_b32_e32 v16, 8, v3
; SI-NEXT:    v_lshrrev_b32_e32 v17, 24, v5
; SI-NEXT:    v_lshrrev_b32_e32 v18, 16, v5
; SI-NEXT:    v_lshrrev_b32_e32 v19, 8, v5
; SI-NEXT:    v_lshrrev_b32_e32 v20, 24, v7
; SI-NEXT:    v_lshrrev_b32_e32 v21, 16, v7
; SI-NEXT:    v_lshrrev_b32_e32 v22, 8, v7
; SI-NEXT:    v_lshrrev_b32_e32 v23, 24, v9
; SI-NEXT:    v_lshrrev_b32_e32 v24, 16, v9
; SI-NEXT:    v_lshrrev_b32_e32 v25, 8, v9
; SI-NEXT:  .LBB33_3: ; %end
; SI-NEXT:    v_and_b32_e32 v10, 0xff, v10
; SI-NEXT:    s_lshl_b32 s5, s16, 8
; SI-NEXT:    v_or_b32_e32 v10, s5, v10
; SI-NEXT:    s_and_b32 s5, s18, 0xff
; SI-NEXT:    s_lshl_b32 s5, s5, 16
; SI-NEXT:    s_lshl_b32 s7, s56, 24
; SI-NEXT:    v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT:    s_or_b32 s5, s7, s5
; SI-NEXT:    v_or_b32_e32 v10, s5, v10
; SI-NEXT:    v_and_b32_e32 v8, 0xff, v8
; SI-NEXT:    s_lshl_b32 s5, s46, 8
; SI-NEXT:    v_or_b32_e32 v8, s5, v8
; SI-NEXT:    s_and_b32 s5, s44, 0xff
; SI-NEXT:    s_lshl_b32 s5, s5, 16
; SI-NEXT:    s_lshl_b32 s7, s42, 24
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT:    s_or_b32 s5, s7, s5
; SI-NEXT:    v_or_b32_e32 v8, s5, v8
; SI-NEXT:    v_and_b32_e32 v6, 0xff, v6
; SI-NEXT:    s_lshl_b32 s5, s40, 8
; SI-NEXT:    buffer_store_dword v10, v0, s[0:3], 0 offen
; SI-NEXT:    v_and_b32_e32 v9, 0xff, v9
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_lshlrev_b32_e32 v10, 8, v25
; SI-NEXT:    v_or_b32_e32 v6, s5, v6
; SI-NEXT:    s_and_b32 s5, s28, 0xff
; SI-NEXT:    v_or_b32_e32 v9, v9, v10
; SI-NEXT:    v_and_b32_e32 v10, 0xff, v24
; SI-NEXT:    s_lshl_b32 s5, s5, 16
; SI-NEXT:    s_lshl_b32 s7, s26, 24
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT:    v_lshlrev_b32_e32 v23, 24, v23
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT:    s_or_b32 s5, s7, s5
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT:    v_or_b32_e32 v10, v23, v10
; SI-NEXT:    buffer_store_dword v8, v0, s[0:3], 0 offen offset:8
; SI-NEXT:    v_and_b32_e32 v7, 0xff, v7
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_lshlrev_b32_e32 v8, 8, v22
; SI-NEXT:    v_or_b32_e32 v6, s5, v6
; SI-NEXT:    v_and_b32_e32 v4, 0xff, v4
; SI-NEXT:    s_lshl_b32 s5, s14, 8
; SI-NEXT:    v_or_b32_e32 v9, v9, v10
; SI-NEXT:    v_or_b32_e32 v7, v7, v8
; SI-NEXT:    v_and_b32_e32 v8, 0xff, v21
; SI-NEXT:    v_or_b32_e32 v4, s5, v4
; SI-NEXT:    s_and_b32 s5, s12, 0xff
; SI-NEXT:    buffer_store_dword v9, v0, s[0:3], 0 offen offset:4
; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_lshlrev_b32_e32 v9, 24, v20
; SI-NEXT:    s_lshl_b32 s5, s5, 16
; SI-NEXT:    s_lshl_b32 s7, s10, 24
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT:    v_or_b32_e32 v8, v9, v8
; SI-NEXT:    buffer_store_dword v6, v0, s[0:3], 0 offen offset:16
; SI-NEXT:    v_and_b32_e32 v5, 0xff, v5
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_lshlrev_b32_e32 v6, 8, v19
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT:    s_or_b32 s5, s7, s5
; SI-NEXT:    v_or_b32_e32 v7, v7, v8
; SI-NEXT:    v_or_b32_e32 v5, v5, v6
; SI-NEXT:    v_and_b32_e32 v6, 0xff, v18
; SI-NEXT:    v_or_b32_e32 v4, s5, v4
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v2
; SI-NEXT:    s_lshl_b32 s5, s8, 8
; SI-NEXT:    buffer_store_dword v7, v0, s[0:3], 0 offen offset:12
; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_lshlrev_b32_e32 v7, 24, v17
; SI-NEXT:    v_or_b32_e32 v2, s5, v2
; SI-NEXT:    s_and_b32 s5, s6, 0xff
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT:    v_or_b32_e32 v6, v7, v6
; SI-NEXT:    buffer_store_dword v4, v0, s[0:3], 0 offen offset:24
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v3
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_lshlrev_b32_e32 v4, 8, v16
; SI-NEXT:    s_lshl_b32 s5, s5, 16
; SI-NEXT:    s_lshl_b32 s4, s4, 24
; SI-NEXT:    v_or_b32_e32 v5, v5, v6
; SI-NEXT:    v_or_b32_e32 v3, v3, v4
; SI-NEXT:    v_and_b32_e32 v4, 0xff, v15
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    s_or_b32 s4, s4, s5
; SI-NEXT:    buffer_store_dword v5, v0, s[0:3], 0 offen offset:20
; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_lshlrev_b32_e32 v5, 24, v14
; SI-NEXT:    v_or_b32_e32 v2, s4, v2
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT:    v_or_b32_e32 v4, v5, v4
; SI-NEXT:    buffer_store_dword v2, v0, s[0:3], 0 offen offset:32
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v13
; SI-NEXT:    v_or_b32_e32 v3, v3, v4
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v12
; SI-NEXT:    buffer_store_dword v3, v0, s[0:3], 0 offen offset:28
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v11
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v10f32_to_v40i8_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc0 .LBB33_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    s_lshr_b32 s14, s25, 24
; VI-NEXT:    s_lshr_b32 s15, s25, 16
; VI-NEXT:    s_lshr_b32 s26, s25, 8
; VI-NEXT:    s_lshr_b32 s27, s24, 16
; VI-NEXT:    s_lshr_b32 s28, s24, 8
; VI-NEXT:    s_lshr_b32 s29, s23, 24
; VI-NEXT:    s_lshr_b32 s40, s23, 16
; VI-NEXT:    s_lshr_b32 s41, s23, 8
; VI-NEXT:    s_lshr_b32 s42, s22, 16
; VI-NEXT:    s_lshr_b32 s43, s22, 8
; VI-NEXT:    s_lshr_b32 s44, s21, 24
; VI-NEXT:    s_lshr_b32 s45, s21, 16
; VI-NEXT:    s_lshr_b32 s46, s21, 8
; VI-NEXT:    s_lshr_b32 s47, s20, 16
; VI-NEXT:    s_lshr_b32 s56, s20, 8
; VI-NEXT:    s_lshr_b32 s57, s19, 24
; VI-NEXT:    s_lshr_b32 s58, s19, 16
; VI-NEXT:    s_lshr_b32 s59, s19, 8
; VI-NEXT:    s_lshr_b32 s60, s18, 16
; VI-NEXT:    s_lshr_b32 s61, s18, 8
; VI-NEXT:    s_lshr_b32 s62, s17, 24
; VI-NEXT:    s_lshr_b32 s63, s17, 16
; VI-NEXT:    s_lshr_b32 s72, s17, 8
; VI-NEXT:    s_lshr_b32 s73, s16, 16
; VI-NEXT:    s_lshr_b32 s74, s16, 8
; VI-NEXT:    s_lshr_b64 s[4:5], s[24:25], 24
; VI-NEXT:    s_lshr_b64 s[6:7], s[22:23], 24
; VI-NEXT:    s_lshr_b64 s[8:9], s[20:21], 24
; VI-NEXT:    s_lshr_b64 s[10:11], s[18:19], 24
; VI-NEXT:    s_lshr_b64 s[12:13], s[16:17], 24
; VI-NEXT:    v_mov_b32_e32 v9, s16
; VI-NEXT:    v_mov_b32_e32 v10, s17
; VI-NEXT:    v_mov_b32_e32 v7, s18
; VI-NEXT:    v_mov_b32_e32 v8, s19
; VI-NEXT:    v_mov_b32_e32 v5, s20
; VI-NEXT:    v_mov_b32_e32 v6, s21
; VI-NEXT:    v_mov_b32_e32 v3, s22
; VI-NEXT:    v_mov_b32_e32 v4, s23
; VI-NEXT:    v_mov_b32_e32 v1, s24
; VI-NEXT:    v_mov_b32_e32 v2, s25
; VI-NEXT:    v_mov_b32_e32 v16, s74
; VI-NEXT:    v_mov_b32_e32 v48, s73
; VI-NEXT:    v_mov_b32_e32 v39, s72
; VI-NEXT:    v_mov_b32_e32 v37, s63
; VI-NEXT:    v_mov_b32_e32 v38, s62
; VI-NEXT:    v_mov_b32_e32 v36, s61
; VI-NEXT:    v_mov_b32_e32 v35, s60
; VI-NEXT:    v_mov_b32_e32 v34, s59
; VI-NEXT:    v_mov_b32_e32 v32, s58
; VI-NEXT:    v_mov_b32_e32 v33, s57
; VI-NEXT:    v_mov_b32_e32 v31, s56
; VI-NEXT:    v_mov_b32_e32 v30, s47
; VI-NEXT:    v_mov_b32_e32 v29, s46
; VI-NEXT:    v_mov_b32_e32 v27, s45
; VI-NEXT:    v_mov_b32_e32 v28, s44
; VI-NEXT:    v_mov_b32_e32 v26, s43
; VI-NEXT:    v_mov_b32_e32 v25, s42
; VI-NEXT:    v_mov_b32_e32 v24, s41
; VI-NEXT:    v_mov_b32_e32 v22, s40
; VI-NEXT:    v_mov_b32_e32 v23, s29
; VI-NEXT:    v_mov_b32_e32 v21, s28
; VI-NEXT:    v_mov_b32_e32 v20, s27
; VI-NEXT:    v_mov_b32_e32 v19, s26
; VI-NEXT:    v_mov_b32_e32 v17, s15
; VI-NEXT:    v_mov_b32_e32 v18, s14
; VI-NEXT:    v_mov_b32_e32 v15, s12
; VI-NEXT:    v_mov_b32_e32 v14, s10
; VI-NEXT:    v_mov_b32_e32 v13, s8
; VI-NEXT:    v_mov_b32_e32 v12, s6
; VI-NEXT:    v_mov_b32_e32 v11, s4
; VI-NEXT:    s_branch .LBB33_3
; VI-NEXT:  .LBB33_2: ; %cmp.true
; VI-NEXT:    v_add_f32_e64 v2, s25, 1.0
; VI-NEXT:    v_add_f32_e64 v1, s24, 1.0
; VI-NEXT:    v_add_f32_e64 v4, s23, 1.0
; VI-NEXT:    v_add_f32_e64 v3, s22, 1.0
; VI-NEXT:    v_lshrrev_b64 v[11:12], 24, v[1:2]
; VI-NEXT:    v_add_f32_e64 v6, s21, 1.0
; VI-NEXT:    v_add_f32_e64 v5, s20, 1.0
; VI-NEXT:    v_lshrrev_b64 v[12:13], 24, v[3:4]
; VI-NEXT:    v_add_f32_e64 v8, s19, 1.0
; VI-NEXT:    v_add_f32_e64 v7, s18, 1.0
; VI-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; VI-NEXT:    v_add_f32_e64 v10, s17, 1.0
; VI-NEXT:    v_add_f32_e64 v9, s16, 1.0
; VI-NEXT:    v_lshrrev_b64 v[14:15], 24, v[7:8]
; VI-NEXT:    v_lshrrev_b64 v[15:16], 24, v[9:10]
; VI-NEXT:    v_lshrrev_b32_e32 v18, 24, v2
; VI-NEXT:    v_lshrrev_b32_e32 v17, 16, v2
; VI-NEXT:    v_lshrrev_b32_e32 v19, 8, v2
; VI-NEXT:    v_lshrrev_b32_e32 v20, 16, v1
; VI-NEXT:    v_lshrrev_b32_e32 v21, 8, v1
; VI-NEXT:    v_lshrrev_b32_e32 v23, 24, v4
; VI-NEXT:    v_lshrrev_b32_e32 v22, 16, v4
; VI-NEXT:    v_lshrrev_b32_e32 v24, 8, v4
; VI-NEXT:    v_lshrrev_b32_e32 v25, 16, v3
; VI-NEXT:    v_lshrrev_b32_e32 v26, 8, v3
; VI-NEXT:    v_lshrrev_b32_e32 v28, 24, v6
; VI-NEXT:    v_lshrrev_b32_e32 v27, 16, v6
; VI-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; VI-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; VI-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; VI-NEXT:    v_lshrrev_b32_e32 v33, 24, v8
; VI-NEXT:    v_lshrrev_b32_e32 v32, 16, v8
; VI-NEXT:    v_lshrrev_b32_e32 v34, 8, v8
; VI-NEXT:    v_lshrrev_b32_e32 v35, 16, v7
; VI-NEXT:    v_lshrrev_b32_e32 v36, 8, v7
; VI-NEXT:    v_lshrrev_b32_e32 v38, 24, v10
; VI-NEXT:    v_lshrrev_b32_e32 v37, 16, v10
; VI-NEXT:    v_lshrrev_b32_e32 v39, 8, v10
; VI-NEXT:    v_lshrrev_b32_e32 v48, 16, v9
; VI-NEXT:    v_lshrrev_b32_e32 v16, 8, v9
; VI-NEXT:  .LBB33_3: ; %end
; VI-NEXT:    s_mov_b32 s4, 0xc0c0004
; VI-NEXT:    v_perm_b32 v15, v48, v15, s4
; VI-NEXT:    v_perm_b32 v9, v9, v16, s4
; VI-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT:    v_or_b32_e32 v9, v9, v15
; VI-NEXT:    buffer_store_dword v9, v0, s[0:3], 0 offen
; VI-NEXT:    v_perm_b32 v9, v10, v39, s4
; VI-NEXT:    v_perm_b32 v10, v37, v38, s4
; VI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT:    v_or_b32_e32 v9, v9, v10
; VI-NEXT:    buffer_store_dword v9, v0, s[0:3], 0 offen offset:4
; VI-NEXT:    v_perm_b32 v9, v35, v14, s4
; VI-NEXT:    v_perm_b32 v7, v7, v36, s4
; VI-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT:    v_or_b32_e32 v7, v7, v9
; VI-NEXT:    buffer_store_dword v7, v0, s[0:3], 0 offen offset:8
; VI-NEXT:    v_perm_b32 v7, v8, v34, s4
; VI-NEXT:    v_perm_b32 v8, v32, v33, s4
; VI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT:    v_or_b32_e32 v7, v7, v8
; VI-NEXT:    buffer_store_dword v7, v0, s[0:3], 0 offen offset:12
; VI-NEXT:    v_perm_b32 v7, v30, v13, s4
; VI-NEXT:    v_perm_b32 v5, v5, v31, s4
; VI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT:    v_or_b32_e32 v5, v5, v7
; VI-NEXT:    buffer_store_dword v5, v0, s[0:3], 0 offen offset:16
; VI-NEXT:    v_perm_b32 v5, v6, v29, s4
; VI-NEXT:    v_perm_b32 v6, v27, v28, s4
; VI-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT:    v_or_b32_e32 v5, v5, v6
; VI-NEXT:    buffer_store_dword v5, v0, s[0:3], 0 offen offset:20
; VI-NEXT:    v_perm_b32 v5, v25, v12, s4
; VI-NEXT:    v_perm_b32 v3, v3, v26, s4
; VI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT:    v_or_b32_e32 v3, v3, v5
; VI-NEXT:    buffer_store_dword v3, v0, s[0:3], 0 offen offset:24
; VI-NEXT:    v_perm_b32 v3, v4, v24, s4
; VI-NEXT:    v_perm_b32 v4, v22, v23, s4
; VI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT:    v_or_b32_e32 v3, v3, v4
; VI-NEXT:    buffer_store_dword v3, v0, s[0:3], 0 offen offset:28
; VI-NEXT:    v_perm_b32 v3, v20, v11, s4
; VI-NEXT:    v_perm_b32 v1, v1, v21, s4
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_e32 v1, v1, v3
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; VI-NEXT:    v_perm_b32 v1, v2, v19, s4
; VI-NEXT:    v_perm_b32 v2, v17, v18, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v10f32_to_v40i8_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc0 .LBB33_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    s_lshr_b32 s14, s25, 24
; GFX9-NEXT:    s_lshr_b32 s15, s25, 16
; GFX9-NEXT:    s_lshr_b32 s26, s25, 8
; GFX9-NEXT:    s_lshr_b32 s27, s24, 16
; GFX9-NEXT:    s_lshr_b32 s28, s24, 8
; GFX9-NEXT:    s_lshr_b32 s29, s23, 24
; GFX9-NEXT:    s_lshr_b32 s40, s23, 16
; GFX9-NEXT:    s_lshr_b32 s41, s23, 8
; GFX9-NEXT:    s_lshr_b32 s42, s22, 16
; GFX9-NEXT:    s_lshr_b32 s43, s22, 8
; GFX9-NEXT:    s_lshr_b32 s44, s21, 24
; GFX9-NEXT:    s_lshr_b32 s45, s21, 16
; GFX9-NEXT:    s_lshr_b32 s46, s21, 8
; GFX9-NEXT:    s_lshr_b32 s47, s20, 16
; GFX9-NEXT:    s_lshr_b32 s56, s20, 8
; GFX9-NEXT:    s_lshr_b32 s57, s19, 24
; GFX9-NEXT:    s_lshr_b32 s58, s19, 16
; GFX9-NEXT:    s_lshr_b32 s59, s19, 8
; GFX9-NEXT:    s_lshr_b32 s60, s18, 16
; GFX9-NEXT:    s_lshr_b32 s61, s18, 8
; GFX9-NEXT:    s_lshr_b32 s62, s17, 24
; GFX9-NEXT:    s_lshr_b32 s63, s17, 16
; GFX9-NEXT:    s_lshr_b32 s72, s17, 8
; GFX9-NEXT:    s_lshr_b32 s73, s16, 16
; GFX9-NEXT:    s_lshr_b32 s74, s16, 8
; GFX9-NEXT:    s_lshr_b64 s[4:5], s[24:25], 24
; GFX9-NEXT:    s_lshr_b64 s[6:7], s[22:23], 24
; GFX9-NEXT:    s_lshr_b64 s[8:9], s[20:21], 24
; GFX9-NEXT:    s_lshr_b64 s[10:11], s[18:19], 24
; GFX9-NEXT:    s_lshr_b64 s[12:13], s[16:17], 24
; GFX9-NEXT:    v_mov_b32_e32 v9, s16
; GFX9-NEXT:    v_mov_b32_e32 v10, s17
; GFX9-NEXT:    v_mov_b32_e32 v7, s18
; GFX9-NEXT:    v_mov_b32_e32 v8, s19
; GFX9-NEXT:    v_mov_b32_e32 v5, s20
; GFX9-NEXT:    v_mov_b32_e32 v6, s21
; GFX9-NEXT:    v_mov_b32_e32 v3, s22
; GFX9-NEXT:    v_mov_b32_e32 v4, s23
; GFX9-NEXT:    v_mov_b32_e32 v1, s24
; GFX9-NEXT:    v_mov_b32_e32 v2, s25
; GFX9-NEXT:    v_mov_b32_e32 v16, s74
; GFX9-NEXT:    v_mov_b32_e32 v48, s73
; GFX9-NEXT:    v_mov_b32_e32 v39, s72
; GFX9-NEXT:    v_mov_b32_e32 v37, s63
; GFX9-NEXT:    v_mov_b32_e32 v38, s62
; GFX9-NEXT:    v_mov_b32_e32 v36, s61
; GFX9-NEXT:    v_mov_b32_e32 v35, s60
; GFX9-NEXT:    v_mov_b32_e32 v34, s59
; GFX9-NEXT:    v_mov_b32_e32 v32, s58
; GFX9-NEXT:    v_mov_b32_e32 v33, s57
; GFX9-NEXT:    v_mov_b32_e32 v31, s56
; GFX9-NEXT:    v_mov_b32_e32 v30, s47
; GFX9-NEXT:    v_mov_b32_e32 v29, s46
; GFX9-NEXT:    v_mov_b32_e32 v27, s45
; GFX9-NEXT:    v_mov_b32_e32 v28, s44
; GFX9-NEXT:    v_mov_b32_e32 v26, s43
; GFX9-NEXT:    v_mov_b32_e32 v25, s42
; GFX9-NEXT:    v_mov_b32_e32 v24, s41
; GFX9-NEXT:    v_mov_b32_e32 v22, s40
; GFX9-NEXT:    v_mov_b32_e32 v23, s29
; GFX9-NEXT:    v_mov_b32_e32 v21, s28
; GFX9-NEXT:    v_mov_b32_e32 v20, s27
; GFX9-NEXT:    v_mov_b32_e32 v19, s26
; GFX9-NEXT:    v_mov_b32_e32 v17, s15
; GFX9-NEXT:    v_mov_b32_e32 v18, s14
; GFX9-NEXT:    v_mov_b32_e32 v15, s12
; GFX9-NEXT:    v_mov_b32_e32 v14, s10
; GFX9-NEXT:    v_mov_b32_e32 v13, s8
; GFX9-NEXT:    v_mov_b32_e32 v12, s6
; GFX9-NEXT:    v_mov_b32_e32 v11, s4
; GFX9-NEXT:    s_branch .LBB33_3
; GFX9-NEXT:  .LBB33_2: ; %cmp.true
; GFX9-NEXT:    v_add_f32_e64 v2, s25, 1.0
; GFX9-NEXT:    v_add_f32_e64 v1, s24, 1.0
; GFX9-NEXT:    v_add_f32_e64 v4, s23, 1.0
; GFX9-NEXT:    v_add_f32_e64 v3, s22, 1.0
; GFX9-NEXT:    v_lshrrev_b64 v[11:12], 24, v[1:2]
; GFX9-NEXT:    v_add_f32_e64 v6, s21, 1.0
; GFX9-NEXT:    v_add_f32_e64 v5, s20, 1.0
; GFX9-NEXT:    v_lshrrev_b64 v[12:13], 24, v[3:4]
; GFX9-NEXT:    v_add_f32_e64 v8, s19, 1.0
; GFX9-NEXT:    v_add_f32_e64 v7, s18, 1.0
; GFX9-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX9-NEXT:    v_add_f32_e64 v10, s17, 1.0
; GFX9-NEXT:    v_add_f32_e64 v9, s16, 1.0
; GFX9-NEXT:    v_lshrrev_b64 v[14:15], 24, v[7:8]
; GFX9-NEXT:    v_lshrrev_b64 v[15:16], 24, v[9:10]
; GFX9-NEXT:    v_lshrrev_b32_e32 v18, 24, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v17, 16, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v19, 8, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v20, 16, v1
; GFX9-NEXT:    v_lshrrev_b32_e32 v21, 8, v1
; GFX9-NEXT:    v_lshrrev_b32_e32 v23, 24, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v22, 16, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v24, 8, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v25, 16, v3
; GFX9-NEXT:    v_lshrrev_b32_e32 v26, 8, v3
; GFX9-NEXT:    v_lshrrev_b32_e32 v28, 24, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v27, 16, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; GFX9-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; GFX9-NEXT:    v_lshrrev_b32_e32 v33, 24, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v32, 16, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v34, 8, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v35, 16, v7
; GFX9-NEXT:    v_lshrrev_b32_e32 v36, 8, v7
; GFX9-NEXT:    v_lshrrev_b32_e32 v38, 24, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v37, 16, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v39, 8, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v48, 16, v9
; GFX9-NEXT:    v_lshrrev_b32_e32 v16, 8, v9
; GFX9-NEXT:  .LBB33_3: ; %end
; GFX9-NEXT:    s_mov_b32 s4, 0xc0c0004
; GFX9-NEXT:    v_perm_b32 v15, v48, v15, s4
; GFX9-NEXT:    v_perm_b32 v9, v9, v16, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
; GFX9-NEXT:    v_or_b32_e32 v9, v9, v15
; GFX9-NEXT:    buffer_store_dword v9, v0, s[0:3], 0 offen
; GFX9-NEXT:    v_perm_b32 v9, v10, v39, s4
; GFX9-NEXT:    v_perm_b32 v10, v37, v38, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; GFX9-NEXT:    v_or_b32_e32 v9, v9, v10
; GFX9-NEXT:    buffer_store_dword v9, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT:    v_perm_b32 v9, v35, v14, s4
; GFX9-NEXT:    v_perm_b32 v7, v7, v36, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; GFX9-NEXT:    v_or_b32_e32 v7, v7, v9
; GFX9-NEXT:    buffer_store_dword v7, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT:    v_perm_b32 v7, v8, v34, s4
; GFX9-NEXT:    v_perm_b32 v8, v32, v33, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; GFX9-NEXT:    v_or_b32_e32 v7, v7, v8
; GFX9-NEXT:    buffer_store_dword v7, v0, s[0:3], 0 offen offset:12
; GFX9-NEXT:    v_perm_b32 v7, v30, v13, s4
; GFX9-NEXT:    v_perm_b32 v5, v5, v31, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; GFX9-NEXT:    v_or_b32_e32 v5, v5, v7
; GFX9-NEXT:    buffer_store_dword v5, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT:    v_perm_b32 v5, v6, v29, s4
; GFX9-NEXT:    v_perm_b32 v6, v27, v28, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; GFX9-NEXT:    v_or_b32_e32 v5, v5, v6
; GFX9-NEXT:    buffer_store_dword v5, v0, s[0:3], 0 offen offset:20
; GFX9-NEXT:    v_perm_b32 v5, v25, v12, s4
; GFX9-NEXT:    v_perm_b32 v3, v3, v26, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; GFX9-NEXT:    v_or_b32_e32 v3, v3, v5
; GFX9-NEXT:    buffer_store_dword v3, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT:    v_perm_b32 v3, v4, v24, s4
; GFX9-NEXT:    v_perm_b32 v4, v22, v23, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; GFX9-NEXT:    v_or_b32_e32 v3, v3, v4
; GFX9-NEXT:    buffer_store_dword v3, v0, s[0:3], 0 offen offset:28
; GFX9-NEXT:    v_perm_b32 v3, v20, v11, s4
; GFX9-NEXT:    v_perm_b32 v1, v1, v21, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT:    v_perm_b32 v1, v2, v19, s4
; GFX9-NEXT:    v_perm_b32 v2, v17, v18, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v2
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v10f32_to_v40i8_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc0 .LBB33_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-NEXT:    s_lshr_b32 s14, s21, 24
; GFX11-NEXT:    s_lshr_b32 s15, s21, 16
; GFX11-NEXT:    s_lshr_b32 s22, s21, 8
; GFX11-NEXT:    s_lshr_b32 s23, s20, 16
; GFX11-NEXT:    s_lshr_b32 s24, s20, 8
; GFX11-NEXT:    s_lshr_b32 s25, s19, 24
; GFX11-NEXT:    s_lshr_b32 s26, s19, 16
; GFX11-NEXT:    s_lshr_b32 s27, s19, 8
; GFX11-NEXT:    s_lshr_b32 s28, s18, 16
; GFX11-NEXT:    s_lshr_b32 s29, s18, 8
; GFX11-NEXT:    s_lshr_b32 s40, s17, 24
; GFX11-NEXT:    s_lshr_b32 s41, s17, 16
; GFX11-NEXT:    s_lshr_b32 s42, s17, 8
; GFX11-NEXT:    s_lshr_b32 s43, s16, 16
; GFX11-NEXT:    s_lshr_b32 s44, s16, 8
; GFX11-NEXT:    s_lshr_b32 s45, s3, 24
; GFX11-NEXT:    s_lshr_b32 s46, s3, 16
; GFX11-NEXT:    s_lshr_b32 s47, s3, 8
; GFX11-NEXT:    s_lshr_b32 s56, s2, 16
; GFX11-NEXT:    s_lshr_b32 s57, s2, 8
; GFX11-NEXT:    s_lshr_b32 s58, s1, 24
; GFX11-NEXT:    s_lshr_b32 s59, s1, 16
; GFX11-NEXT:    s_lshr_b32 s60, s1, 8
; GFX11-NEXT:    s_lshr_b32 s61, s0, 16
; GFX11-NEXT:    s_lshr_b32 s62, s0, 8
; GFX11-NEXT:    s_lshr_b64 s[4:5], s[20:21], 24
; GFX11-NEXT:    s_lshr_b64 s[6:7], s[18:19], 24
; GFX11-NEXT:    s_lshr_b64 s[8:9], s[16:17], 24
; GFX11-NEXT:    s_lshr_b64 s[10:11], s[2:3], 24
; GFX11-NEXT:    s_lshr_b64 s[12:13], s[0:1], 24
; GFX11-NEXT:    v_dual_mov_b32 v11, s0 :: v_dual_mov_b32 v12, s1
; GFX11-NEXT:    v_dual_mov_b32 v7, s2 :: v_dual_mov_b32 v8, s3
; GFX11-NEXT:    v_dual_mov_b32 v5, s16 :: v_dual_mov_b32 v6, s17
; GFX11-NEXT:    v_dual_mov_b32 v3, s18 :: v_dual_mov_b32 v4, s19
; GFX11-NEXT:    v_dual_mov_b32 v1, s20 :: v_dual_mov_b32 v2, s21
; GFX11-NEXT:    v_dual_mov_b32 v39, s62 :: v_dual_mov_b32 v48, s61
; GFX11-NEXT:    v_dual_mov_b32 v38, s60 :: v_dual_mov_b32 v37, s58
; GFX11-NEXT:    v_dual_mov_b32 v36, s59 :: v_dual_mov_b32 v35, s57
; GFX11-NEXT:    v_dual_mov_b32 v34, s56 :: v_dual_mov_b32 v33, s45
; GFX11-NEXT:    v_dual_mov_b32 v30, s47 :: v_dual_mov_b32 v29, s44
; GFX11-NEXT:    v_dual_mov_b32 v32, s46 :: v_dual_mov_b32 v31, s43
; GFX11-NEXT:    v_dual_mov_b32 v25, s42 :: v_dual_mov_b32 v28, s40
; GFX11-NEXT:    v_dual_mov_b32 v27, s41 :: v_dual_mov_b32 v24, s29
; GFX11-NEXT:    v_dual_mov_b32 v26, s28 :: v_dual_mov_b32 v23, s25
; GFX11-NEXT:    v_dual_mov_b32 v20, s27 :: v_dual_mov_b32 v17, s24
; GFX11-NEXT:    v_dual_mov_b32 v22, s26 :: v_dual_mov_b32 v21, s23
; GFX11-NEXT:    v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v19, s14
; GFX11-NEXT:    v_dual_mov_b32 v18, s15 :: v_dual_mov_b32 v15, s10
; GFX11-NEXT:    v_dual_mov_b32 v16, s12 :: v_dual_mov_b32 v13, s6
; GFX11-NEXT:    v_dual_mov_b32 v14, s8 :: v_dual_mov_b32 v9, s4
; GFX11-NEXT:    s_branch .LBB33_3
; GFX11-NEXT:  .LBB33_2: ; %cmp.true
; GFX11-NEXT:    v_add_f32_e64 v4, s19, 1.0
; GFX11-NEXT:    v_add_f32_e64 v3, s18, 1.0
; GFX11-NEXT:    v_add_f32_e64 v6, s17, 1.0
; GFX11-NEXT:    v_add_f32_e64 v5, s16, 1.0
; GFX11-NEXT:    v_add_f32_e64 v8, s3, 1.0
; GFX11-NEXT:    v_add_f32_e64 v7, s2, 1.0
; GFX11-NEXT:    v_add_f32_e64 v12, s1, 1.0
; GFX11-NEXT:    v_add_f32_e64 v2, s21, 1.0
; GFX11-NEXT:    v_add_f32_e64 v1, s20, 1.0
; GFX11-NEXT:    v_add_f32_e64 v11, s0, 1.0
; GFX11-NEXT:    v_lshrrev_b64 v[13:14], 24, v[3:4]
; GFX11-NEXT:    v_lshrrev_b64 v[14:15], 24, v[5:6]
; GFX11-NEXT:    v_lshrrev_b64 v[15:16], 24, v[7:8]
; GFX11-NEXT:    v_lshrrev_b64 v[9:10], 24, v[1:2]
; GFX11-NEXT:    v_lshrrev_b64 v[16:17], 24, v[11:12]
; GFX11-NEXT:    v_lshrrev_b32_e32 v19, 24, v2
; GFX11-NEXT:    v_lshrrev_b32_e32 v18, 16, v2
; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 8, v2
; GFX11-NEXT:    v_lshrrev_b32_e32 v21, 16, v1
; GFX11-NEXT:    v_lshrrev_b32_e32 v17, 8, v1
; GFX11-NEXT:    v_lshrrev_b32_e32 v23, 24, v4
; GFX11-NEXT:    v_lshrrev_b32_e32 v22, 16, v4
; GFX11-NEXT:    v_lshrrev_b32_e32 v20, 8, v4
; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 16, v3
; GFX11-NEXT:    v_lshrrev_b32_e32 v24, 8, v3
; GFX11-NEXT:    v_lshrrev_b32_e32 v28, 24, v6
; GFX11-NEXT:    v_lshrrev_b32_e32 v27, 16, v6
; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 8, v6
; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 16, v5
; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 8, v5
; GFX11-NEXT:    v_lshrrev_b32_e32 v33, 24, v8
; GFX11-NEXT:    v_lshrrev_b32_e32 v32, 16, v8
; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 8, v8
; GFX11-NEXT:    v_lshrrev_b32_e32 v34, 16, v7
; GFX11-NEXT:    v_lshrrev_b32_e32 v35, 8, v7
; GFX11-NEXT:    v_lshrrev_b32_e32 v37, 24, v12
; GFX11-NEXT:    v_lshrrev_b32_e32 v36, 16, v12
; GFX11-NEXT:    v_lshrrev_b32_e32 v38, 8, v12
; GFX11-NEXT:    v_lshrrev_b32_e32 v48, 16, v11
; GFX11-NEXT:    v_lshrrev_b32_e32 v39, 8, v11
; GFX11-NEXT:  .LBB33_3: ; %end
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT:    v_perm_b32 v16, v48, v16, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v11, v11, v39, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v36, v36, v37, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v15, v34, v15, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v32, v32, v33, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
; GFX11-NEXT:    v_perm_b32 v12, v12, v38, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v7, v7, v35, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v14, v31, v14, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v33, 16, v36
; GFX11-NEXT:    v_or_b32_e32 v31, v11, v16
; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v15
; GFX11-NEXT:    v_perm_b32 v8, v8, v30, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v32
; GFX11-NEXT:    v_or_b32_e32 v32, v12, v33
; GFX11-NEXT:    v_perm_b32 v9, v21, v9, 0xc0c0004
; GFX11-NEXT:    v_or_b32_e32 v33, v7, v11
; GFX11-NEXT:    v_perm_b32 v7, v27, v28, 0xc0c0004
; GFX11-NEXT:    v_or_b32_e32 v34, v8, v15
; GFX11-NEXT:    v_perm_b32 v8, v26, v13, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v11, v22, v23, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v12, v18, v19, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v5, v5, v29, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
; GFX11-NEXT:    v_perm_b32 v6, v6, v25, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; GFX11-NEXT:    v_perm_b32 v3, v3, v24, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; GFX11-NEXT:    v_perm_b32 v4, v4, v20, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; GFX11-NEXT:    v_perm_b32 v1, v1, v17, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; GFX11-NEXT:    v_perm_b32 v2, v2, v10, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v12
; GFX11-NEXT:    v_or_b32_e32 v5, v5, v14
; GFX11-NEXT:    v_or_b32_e32 v6, v6, v7
; GFX11-NEXT:    v_or_b32_e32 v7, v3, v8
; GFX11-NEXT:    v_or_b32_e32 v8, v4, v11
; GFX11-NEXT:    v_or_b32_e32 v1, v1, v9
; GFX11-NEXT:    v_or_b32_e32 v2, v2, v10
; GFX11-NEXT:    s_clause 0x2
; GFX11-NEXT:    scratch_store_b128 v0, v[31:34], off
; GFX11-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
; GFX11-NEXT:    scratch_store_b64 v0, v[1:2], off offset:32
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <10 x float> %a, splat (float 1.000000e+00)
  %a2 = bitcast <10 x float> %a1 to <40 x i8>
  br label %end

cmp.false:
  %a3 = bitcast <10 x float> %a to <40 x i8>
  br label %end

end:
  %phi = phi <40 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <40 x i8> %phi
}

define <10 x float> @bitcast_v40i8_to_v10f32(<40 x i8> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v40i8_to_v10f32:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; SI-NEXT:    v_mov_b32_e32 v35, v8
; SI-NEXT:    v_mov_b32_e32 v34, v6
; SI-NEXT:    v_mov_b32_e32 v33, v4
; SI-NEXT:    v_mov_b32_e32 v32, v2
; SI-NEXT:    v_mov_b32_e32 v31, v0
; SI-NEXT:    buffer_load_dword v0, off, s[0:3], s32
; SI-NEXT:    buffer_load_dword v2, off, s[0:3], s32 offset:36
; SI-NEXT:    buffer_load_dword v4, off, s[0:3], s32 offset:32
; SI-NEXT:    buffer_load_dword v36, off, s[0:3], s32 offset:28
; SI-NEXT:    buffer_load_dword v6, off, s[0:3], s32 offset:24
; SI-NEXT:    buffer_load_dword v8, off, s[0:3], s32 offset:8
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    buffer_load_dword v44, off, s[0:3], s32 offset:16
; SI-NEXT:    buffer_load_dword v37, off, s[0:3], s32 offset:20
; SI-NEXT:    buffer_load_dword v38, off, s[0:3], s32 offset:12
; SI-NEXT:    buffer_load_dword v39, off, s[0:3], s32 offset:4
; SI-NEXT:    v_lshlrev_b32_e32 v43, 8, v1
; SI-NEXT:    v_lshlrev_b32_e32 v42, 24, v3
; SI-NEXT:    v_lshlrev_b32_e32 v41, 8, v5
; SI-NEXT:    v_lshlrev_b32_e32 v40, 24, v7
; SI-NEXT:    v_lshlrev_b32_e32 v55, 8, v9
; SI-NEXT:    v_lshlrev_b32_e32 v54, 24, v11
; SI-NEXT:    v_lshlrev_b32_e32 v53, 8, v13
; SI-NEXT:    v_lshlrev_b32_e32 v52, 24, v15
; SI-NEXT:    v_lshlrev_b32_e32 v51, 8, v17
; SI-NEXT:    v_lshlrev_b32_e32 v50, 24, v19
; SI-NEXT:    v_lshlrev_b32_e32 v49, 8, v21
; SI-NEXT:    v_lshlrev_b32_e32 v48, 24, v23
; SI-NEXT:    v_lshlrev_b32_e32 v25, 8, v25
; SI-NEXT:    v_lshlrev_b32_e32 v23, 24, v27
; SI-NEXT:    v_lshlrev_b32_e32 v21, 8, v29
; SI-NEXT:    s_waitcnt vmcnt(9)
; SI-NEXT:    v_lshlrev_b32_e32 v19, 24, v0
; SI-NEXT:    s_waitcnt vmcnt(8)
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
; SI-NEXT:    s_waitcnt vmcnt(7)
; SI-NEXT:    v_lshlrev_b32_e32 v11, 24, v4
; SI-NEXT:    s_waitcnt vmcnt(5)
; SI-NEXT:    v_lshlrev_b32_e32 v13, 8, v6
; SI-NEXT:    s_waitcnt vmcnt(4)
; SI-NEXT:    v_lshlrev_b32_e32 v17, 8, v8
; SI-NEXT:    s_waitcnt vmcnt(3)
; SI-NEXT:    v_lshlrev_b32_e32 v15, 24, v44
; SI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB34_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    v_and_b32_e32 v0, 0xff, v31
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v32
; SI-NEXT:    v_or_b32_e32 v0, v0, v43
; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_or_b32_e32 v1, v42, v1
; SI-NEXT:    v_or_b32_e32 v0, v0, v1
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v33
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v34
; SI-NEXT:    v_or_b32_e32 v1, v1, v41
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v40, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v35
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v10
; SI-NEXT:    v_or_b32_e32 v2, v2, v55
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    v_or_b32_e32 v3, v54, v3
; SI-NEXT:    v_or_b32_e32 v2, v2, v3
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v12
; SI-NEXT:    v_and_b32_e32 v4, 0xff, v14
; SI-NEXT:    v_or_b32_e32 v3, v3, v53
; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT:    v_or_b32_e32 v4, v52, v4
; SI-NEXT:    v_or_b32_e32 v3, v3, v4
; SI-NEXT:    v_and_b32_e32 v4, 0xff, v16
; SI-NEXT:    v_and_b32_e32 v5, 0xff, v18
; SI-NEXT:    v_or_b32_e32 v4, v4, v51
; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT:    v_or_b32_e32 v5, v50, v5
; SI-NEXT:    v_or_b32_e32 v4, v4, v5
; SI-NEXT:    v_and_b32_e32 v5, 0xff, v20
; SI-NEXT:    v_and_b32_e32 v6, 0xff, v22
; SI-NEXT:    v_or_b32_e32 v5, v5, v49
; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT:    v_or_b32_e32 v6, v48, v6
; SI-NEXT:    v_or_b32_e32 v5, v5, v6
; SI-NEXT:    v_and_b32_e32 v6, 0xff, v24
; SI-NEXT:    v_and_b32_e32 v7, 0xff, v26
; SI-NEXT:    v_or_b32_e32 v6, v6, v25
; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT:    v_or_b32_e32 v7, v23, v7
; SI-NEXT:    v_or_b32_e32 v6, v6, v7
; SI-NEXT:    v_and_b32_e32 v7, 0xff, v28
; SI-NEXT:    v_and_b32_e32 v8, 0xff, v30
; SI-NEXT:    v_or_b32_e32 v7, v7, v21
; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT:    v_or_b32_e32 v8, v19, v8
; SI-NEXT:    v_or_b32_e32 v7, v7, v8
; SI-NEXT:    s_waitcnt vmcnt(0)
; SI-NEXT:    v_and_b32_e32 v8, 0xff, v39
; SI-NEXT:    v_and_b32_e32 v9, 0xff, v38
; SI-NEXT:    v_or_b32_e32 v8, v8, v17
; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT:    v_or_b32_e32 v9, v15, v9
; SI-NEXT:    v_or_b32_e32 v8, v8, v9
; SI-NEXT:    v_and_b32_e32 v9, 0xff, v37
; SI-NEXT:    v_and_b32_e32 v10, 0xff, v36
; SI-NEXT:    v_or_b32_e32 v9, v9, v13
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT:    v_or_b32_e32 v10, v11, v10
; SI-NEXT:    v_or_b32_e32 v9, v9, v10
; SI-NEXT:    ; implicit-def: $vgpr31
; SI-NEXT:    ; implicit-def: $vgpr32
; SI-NEXT:    ; implicit-def: $vgpr33
; SI-NEXT:    ; implicit-def: $vgpr34
; SI-NEXT:    ; implicit-def: $vgpr35
; SI-NEXT:    ; implicit-def: $vgpr10
; SI-NEXT:    ; implicit-def: $vgpr12
; SI-NEXT:    ; implicit-def: $vgpr14
; SI-NEXT:    ; implicit-def: $vgpr16
; SI-NEXT:    ; implicit-def: $vgpr18
; SI-NEXT:    ; implicit-def: $vgpr20
; SI-NEXT:    ; implicit-def: $vgpr22
; SI-NEXT:    ; implicit-def: $vgpr24
; SI-NEXT:    ; implicit-def: $vgpr26
; SI-NEXT:    ; implicit-def: $vgpr28
; SI-NEXT:    ; implicit-def: $vgpr30
; SI-NEXT:    ; implicit-def: $vgpr39
; SI-NEXT:    ; implicit-def: $vgpr38
; SI-NEXT:    ; implicit-def: $vgpr37
; SI-NEXT:    ; implicit-def: $vgpr36
; SI-NEXT:    ; implicit-def: $vgpr43
; SI-NEXT:    ; implicit-def: $vgpr42
; SI-NEXT:    ; implicit-def: $vgpr41
; SI-NEXT:    ; implicit-def: $vgpr40
; SI-NEXT:    ; implicit-def: $vgpr55
; SI-NEXT:    ; implicit-def: $vgpr54
; SI-NEXT:    ; implicit-def: $vgpr53
; SI-NEXT:    ; implicit-def: $vgpr52
; SI-NEXT:    ; implicit-def: $vgpr51
; SI-NEXT:    ; implicit-def: $vgpr50
; SI-NEXT:    ; implicit-def: $vgpr49
; SI-NEXT:    ; implicit-def: $vgpr48
; SI-NEXT:    ; implicit-def: $vgpr25
; SI-NEXT:    ; implicit-def: $vgpr23
; SI-NEXT:    ; implicit-def: $vgpr21
; SI-NEXT:    ; implicit-def: $vgpr19
; SI-NEXT:    ; implicit-def: $vgpr17
; SI-NEXT:    ; implicit-def: $vgpr15
; SI-NEXT:    ; implicit-def: $vgpr13
; SI-NEXT:    ; implicit-def: $vgpr11
; SI-NEXT:  .LBB34_2: ; %Flow
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB34_4
; SI-NEXT:  ; %bb.3: ; %cmp.true
; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v31
; SI-NEXT:    v_and_b32_e32 v0, 0xff, v0
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v32
; SI-NEXT:    v_or_b32_e32 v0, v43, v0
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1
; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x300, v0
; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_or_b32_e32 v1, v42, v1
; SI-NEXT:    v_or_b32_e32 v0, v1, v0
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v33
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1
; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v34
; SI-NEXT:    s_movk_i32 s6, 0x300
; SI-NEXT:    v_or_b32_e32 v1, v41, v1
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v2
; SI-NEXT:    v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v40, v2
; SI-NEXT:    v_or_b32_e32 v1, v2, v1
; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v35
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v2
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v10
; SI-NEXT:    v_or_b32_e32 v2, v55, v2
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v3
; SI-NEXT:    v_add_i32_e32 v2, vcc, s6, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    v_or_b32_e32 v3, v54, v3
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v12
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v3
; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v14
; SI-NEXT:    v_or_b32_e32 v3, v53, v3
; SI-NEXT:    v_and_b32_e32 v4, 0xff, v4
; SI-NEXT:    v_add_i32_e32 v3, vcc, s6, v3
; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT:    v_or_b32_e32 v4, v52, v4
; SI-NEXT:    v_or_b32_e32 v3, v4, v3
; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v16
; SI-NEXT:    v_and_b32_e32 v4, 0xff, v4
; SI-NEXT:    v_add_i32_e32 v5, vcc, 3, v18
; SI-NEXT:    v_or_b32_e32 v4, v51, v4
; SI-NEXT:    v_and_b32_e32 v5, 0xff, v5
; SI-NEXT:    v_add_i32_e32 v4, vcc, s6, v4
; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT:    v_or_b32_e32 v5, v50, v5
; SI-NEXT:    v_or_b32_e32 v4, v5, v4
; SI-NEXT:    v_add_i32_e32 v5, vcc, 3, v20
; SI-NEXT:    v_and_b32_e32 v5, 0xff, v5
; SI-NEXT:    v_add_i32_e32 v6, vcc, 3, v22
; SI-NEXT:    v_or_b32_e32 v5, v49, v5
; SI-NEXT:    v_and_b32_e32 v6, 0xff, v6
; SI-NEXT:    v_add_i32_e32 v5, vcc, s6, v5
; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT:    v_or_b32_e32 v6, v48, v6
; SI-NEXT:    v_or_b32_e32 v5, v6, v5
; SI-NEXT:    v_add_i32_e32 v6, vcc, 3, v24
; SI-NEXT:    v_and_b32_e32 v6, 0xff, v6
; SI-NEXT:    v_add_i32_e32 v7, vcc, 3, v26
; SI-NEXT:    v_or_b32_e32 v6, v25, v6
; SI-NEXT:    v_and_b32_e32 v7, 0xff, v7
; SI-NEXT:    v_add_i32_e32 v6, vcc, s6, v6
; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT:    v_or_b32_e32 v7, v23, v7
; SI-NEXT:    v_or_b32_e32 v6, v7, v6
; SI-NEXT:    v_add_i32_e32 v7, vcc, 3, v28
; SI-NEXT:    v_and_b32_e32 v7, 0xff, v7
; SI-NEXT:    v_add_i32_e32 v8, vcc, 3, v30
; SI-NEXT:    v_or_b32_e32 v7, v21, v7
; SI-NEXT:    v_and_b32_e32 v8, 0xff, v8
; SI-NEXT:    v_add_i32_e32 v7, vcc, s6, v7
; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT:    v_or_b32_e32 v8, v19, v8
; SI-NEXT:    v_or_b32_e32 v7, v8, v7
; SI-NEXT:    s_waitcnt vmcnt(0)
; SI-NEXT:    v_add_i32_e32 v8, vcc, 3, v39
; SI-NEXT:    v_and_b32_e32 v8, 0xff, v8
; SI-NEXT:    v_add_i32_e32 v9, vcc, 3, v38
; SI-NEXT:    v_or_b32_e32 v8, v17, v8
; SI-NEXT:    v_and_b32_e32 v9, 0xff, v9
; SI-NEXT:    v_add_i32_e32 v8, vcc, s6, v8
; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT:    v_or_b32_e32 v9, v15, v9
; SI-NEXT:    v_or_b32_e32 v8, v9, v8
; SI-NEXT:    v_add_i32_e32 v9, vcc, 3, v37
; SI-NEXT:    v_and_b32_e32 v9, 0xff, v9
; SI-NEXT:    v_add_i32_e32 v10, vcc, 3, v36
; SI-NEXT:    v_or_b32_e32 v9, v13, v9
; SI-NEXT:    v_and_b32_e32 v10, 0xff, v10
; SI-NEXT:    v_add_i32_e32 v9, vcc, 0x300, v9
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT:    v_or_b32_e32 v10, v11, v10
; SI-NEXT:    v_or_b32_e32 v9, v10, v9
; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x3000000, v0
; SI-NEXT:    v_add_i32_e32 v1, vcc, 0x3000000, v1
; SI-NEXT:    v_add_i32_e32 v2, vcc, 0x3000000, v2
; SI-NEXT:    v_add_i32_e32 v3, vcc, 0x3000000, v3
; SI-NEXT:    v_add_i32_e32 v4, vcc, 0x3000000, v4
; SI-NEXT:    v_add_i32_e32 v5, vcc, 0x3000000, v5
; SI-NEXT:    v_add_i32_e32 v6, vcc, 0x3000000, v6
; SI-NEXT:    v_add_i32_e32 v7, vcc, 0x3000000, v7
; SI-NEXT:    v_add_i32_e32 v8, vcc, 0x3000000, v8
; SI-NEXT:    v_add_i32_e32 v9, vcc, 0x3000000, v9
; SI-NEXT:  .LBB34_4: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    buffer_load_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; SI-NEXT:    s_waitcnt vmcnt(0)
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v40i8_to_v10f32:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; VI-NEXT:    buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; VI-NEXT:    v_mov_b32_e32 v48, v0
; VI-NEXT:    buffer_load_ushort v55, off, s[0:3], s32
; VI-NEXT:    buffer_load_dword v0, off, s[0:3], s32 offset:36
; VI-NEXT:    buffer_load_ushort v49, off, s[0:3], s32 offset:32
; VI-NEXT:    buffer_load_ushort v50, off, s[0:3], s32 offset:28
; VI-NEXT:    buffer_load_ushort v51, off, s[0:3], s32 offset:24
; VI-NEXT:    buffer_load_ushort v52, off, s[0:3], s32 offset:20
; VI-NEXT:    buffer_load_ushort v53, off, s[0:3], s32 offset:16
; VI-NEXT:    buffer_load_ushort v54, off, s[0:3], s32 offset:12
; VI-NEXT:    buffer_load_ushort v40, off, s[0:3], s32 offset:8
; VI-NEXT:    buffer_load_ushort v41, off, s[0:3], s32 offset:4
; VI-NEXT:    v_mov_b32_e32 v31, v9
; VI-NEXT:    v_mov_b32_e32 v32, v8
; VI-NEXT:    v_mov_b32_e32 v33, v7
; VI-NEXT:    v_mov_b32_e32 v34, v6
; VI-NEXT:    v_mov_b32_e32 v35, v5
; VI-NEXT:    v_mov_b32_e32 v36, v4
; VI-NEXT:    v_mov_b32_e32 v37, v3
; VI-NEXT:    v_mov_b32_e32 v38, v2
; VI-NEXT:    v_mov_b32_e32 v39, v1
; VI-NEXT:    s_waitcnt vmcnt(8)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; VI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB34_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    s_mov_b32 s6, 0xc0c0004
; VI-NEXT:    v_perm_b32 v1, v38, v37, s6
; VI-NEXT:    v_perm_b32 v0, v48, v39, s6
; VI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT:    v_perm_b32 v2, v34, v33, s6
; VI-NEXT:    v_or_b32_e32 v0, v0, v1
; VI-NEXT:    v_perm_b32 v1, v36, v35, s6
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_perm_b32 v3, v10, v11, s6
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v32, v31, s6
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_perm_b32 v4, v14, v15, s6
; VI-NEXT:    v_or_b32_e32 v2, v2, v3
; VI-NEXT:    v_perm_b32 v3, v12, v13, s6
; VI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT:    v_perm_b32 v5, v18, v19, s6
; VI-NEXT:    v_or_b32_e32 v3, v3, v4
; VI-NEXT:    v_perm_b32 v4, v16, v17, s6
; VI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT:    v_perm_b32 v6, v22, v23, s6
; VI-NEXT:    v_or_b32_e32 v4, v4, v5
; VI-NEXT:    v_perm_b32 v5, v20, v21, s6
; VI-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT:    v_perm_b32 v7, v26, v27, s6
; VI-NEXT:    v_or_b32_e32 v5, v5, v6
; VI-NEXT:    v_perm_b32 v6, v24, v25, s6
; VI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT:    v_perm_b32 v8, v30, v55, s6
; VI-NEXT:    v_or_b32_e32 v6, v6, v7
; VI-NEXT:    v_perm_b32 v7, v28, v29, s6
; VI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT:    s_waitcnt vmcnt(2)
; VI-NEXT:    v_perm_b32 v9, v54, v53, s6
; VI-NEXT:    v_or_b32_e32 v7, v7, v8
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    v_perm_b32 v8, v41, v40, s6
; VI-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT:    v_perm_b32 v10, v50, v49, s6
; VI-NEXT:    v_or_b32_e32 v8, v8, v9
; VI-NEXT:    v_perm_b32 v9, v52, v51, s6
; VI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT:    v_or_b32_e32 v9, v9, v10
; VI-NEXT:    ; implicit-def: $vgpr48
; VI-NEXT:    ; implicit-def: $vgpr39
; VI-NEXT:    ; implicit-def: $vgpr38
; VI-NEXT:    ; implicit-def: $vgpr37
; VI-NEXT:    ; implicit-def: $vgpr36
; VI-NEXT:    ; implicit-def: $vgpr35
; VI-NEXT:    ; implicit-def: $vgpr34
; VI-NEXT:    ; implicit-def: $vgpr33
; VI-NEXT:    ; implicit-def: $vgpr32
; VI-NEXT:    ; implicit-def: $vgpr31
; VI-NEXT:    ; implicit-def: $vgpr10
; VI-NEXT:    ; implicit-def: $vgpr11
; VI-NEXT:    ; implicit-def: $vgpr12
; VI-NEXT:    ; implicit-def: $vgpr13
; VI-NEXT:    ; implicit-def: $vgpr14
; VI-NEXT:    ; implicit-def: $vgpr15
; VI-NEXT:    ; implicit-def: $vgpr16
; VI-NEXT:    ; implicit-def: $vgpr17
; VI-NEXT:    ; implicit-def: $vgpr18
; VI-NEXT:    ; implicit-def: $vgpr19
; VI-NEXT:    ; implicit-def: $vgpr20
; VI-NEXT:    ; implicit-def: $vgpr21
; VI-NEXT:    ; implicit-def: $vgpr22
; VI-NEXT:    ; implicit-def: $vgpr23
; VI-NEXT:    ; implicit-def: $vgpr24
; VI-NEXT:    ; implicit-def: $vgpr25
; VI-NEXT:    ; implicit-def: $vgpr26
; VI-NEXT:    ; implicit-def: $vgpr27
; VI-NEXT:    ; implicit-def: $vgpr28
; VI-NEXT:    ; implicit-def: $vgpr29
; VI-NEXT:    ; implicit-def: $vgpr30
; VI-NEXT:    ; implicit-def: $vgpr55
; VI-NEXT:    ; implicit-def: $vgpr41
; VI-NEXT:    ; implicit-def: $vgpr40
; VI-NEXT:    ; implicit-def: $vgpr54
; VI-NEXT:    ; implicit-def: $vgpr53
; VI-NEXT:    ; implicit-def: $vgpr52
; VI-NEXT:    ; implicit-def: $vgpr51
; VI-NEXT:    ; implicit-def: $vgpr50
; VI-NEXT:    ; implicit-def: $vgpr49
; VI-NEXT:  .LBB34_2: ; %Flow
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB34_4
; VI-NEXT:  ; %bb.3: ; %cmp.true
; VI-NEXT:    v_add_u16_e32 v0, 3, v48
; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v39
; VI-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v1, 3, v38
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v37
; VI-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_mov_b32_e32 v9, 0x300
; VI-NEXT:    v_add_u16_e32 v0, 0x300, v0
; VI-NEXT:    v_add_u16_sdwa v1, v1, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v0, v0, v1
; VI-NEXT:    v_add_u16_e32 v1, 3, v36
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v35
; VI-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v2, 3, v34
; VI-NEXT:    v_lshlrev_b16_e32 v3, 8, v33
; VI-NEXT:    v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v1, 0x300, v1
; VI-NEXT:    v_add_u16_sdwa v2, v2, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_add_u16_e32 v2, 3, v32
; VI-NEXT:    v_lshlrev_b16_e32 v3, 8, v31
; VI-NEXT:    v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v3, 3, v10
; VI-NEXT:    v_lshlrev_b16_e32 v4, 8, v11
; VI-NEXT:    v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v2, 0x300, v2
; VI-NEXT:    v_add_u16_sdwa v3, v3, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v2, v2, v3
; VI-NEXT:    v_add_u16_e32 v3, 3, v12
; VI-NEXT:    v_lshlrev_b16_e32 v4, 8, v13
; VI-NEXT:    v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v4, 3, v14
; VI-NEXT:    v_lshlrev_b16_e32 v5, 8, v15
; VI-NEXT:    v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v3, 0x300, v3
; VI-NEXT:    v_add_u16_sdwa v4, v4, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v3, v3, v4
; VI-NEXT:    v_add_u16_e32 v4, 3, v16
; VI-NEXT:    v_lshlrev_b16_e32 v5, 8, v17
; VI-NEXT:    v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v5, 3, v18
; VI-NEXT:    v_lshlrev_b16_e32 v6, 8, v19
; VI-NEXT:    v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v4, 0x300, v4
; VI-NEXT:    v_add_u16_sdwa v5, v5, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v4, v4, v5
; VI-NEXT:    v_add_u16_e32 v5, 3, v20
; VI-NEXT:    v_lshlrev_b16_e32 v6, 8, v21
; VI-NEXT:    v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v6, 3, v22
; VI-NEXT:    v_lshlrev_b16_e32 v7, 8, v23
; VI-NEXT:    v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v5, 0x300, v5
; VI-NEXT:    v_add_u16_sdwa v6, v6, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v5, v5, v6
; VI-NEXT:    v_add_u16_e32 v6, 3, v24
; VI-NEXT:    v_lshlrev_b16_e32 v7, 8, v25
; VI-NEXT:    v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v7, 3, v26
; VI-NEXT:    v_lshlrev_b16_e32 v8, 8, v27
; VI-NEXT:    v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v6, 0x300, v6
; VI-NEXT:    v_add_u16_sdwa v7, v7, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v6, v6, v7
; VI-NEXT:    v_add_u16_e32 v7, 3, v28
; VI-NEXT:    v_lshlrev_b16_e32 v8, 8, v29
; VI-NEXT:    v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v8, 3, v30
; VI-NEXT:    v_lshlrev_b16_e32 v10, 8, v55
; VI-NEXT:    v_or_b32_sdwa v8, v10, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v7, 0x300, v7
; VI-NEXT:    v_add_u16_sdwa v8, v8, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v7, v7, v8
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    v_add_u16_e32 v8, 3, v41
; VI-NEXT:    v_lshlrev_b16_e32 v10, 8, v40
; VI-NEXT:    v_or_b32_sdwa v8, v10, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v10, 3, v54
; VI-NEXT:    v_lshlrev_b16_e32 v11, 8, v53
; VI-NEXT:    v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v8, 0x300, v8
; VI-NEXT:    v_add_u16_sdwa v10, v10, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v8, v8, v10
; VI-NEXT:    v_add_u16_e32 v10, 3, v52
; VI-NEXT:    v_lshlrev_b16_e32 v11, 8, v51
; VI-NEXT:    v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v11, 3, v50
; VI-NEXT:    v_lshlrev_b16_e32 v12, 8, v49
; VI-NEXT:    v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v10, 0x300, v10
; VI-NEXT:    v_add_u16_sdwa v9, v11, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v9, v10, v9
; VI-NEXT:  .LBB34_4: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; VI-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v40i8_to_v10f32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; GFX9-NEXT:    buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; GFX9-NEXT:    v_mov_b32_e32 v48, v0
; GFX9-NEXT:    buffer_load_ushort v55, off, s[0:3], s32
; GFX9-NEXT:    buffer_load_dword v0, off, s[0:3], s32 offset:36
; GFX9-NEXT:    buffer_load_ushort v49, off, s[0:3], s32 offset:32
; GFX9-NEXT:    buffer_load_ushort v50, off, s[0:3], s32 offset:28
; GFX9-NEXT:    buffer_load_ushort v51, off, s[0:3], s32 offset:24
; GFX9-NEXT:    buffer_load_ushort v52, off, s[0:3], s32 offset:20
; GFX9-NEXT:    buffer_load_ushort v53, off, s[0:3], s32 offset:16
; GFX9-NEXT:    buffer_load_ushort v54, off, s[0:3], s32 offset:12
; GFX9-NEXT:    buffer_load_ushort v40, off, s[0:3], s32 offset:8
; GFX9-NEXT:    buffer_load_ushort v41, off, s[0:3], s32 offset:4
; GFX9-NEXT:    v_mov_b32_e32 v31, v9
; GFX9-NEXT:    v_mov_b32_e32 v32, v8
; GFX9-NEXT:    v_mov_b32_e32 v33, v7
; GFX9-NEXT:    v_mov_b32_e32 v34, v6
; GFX9-NEXT:    v_mov_b32_e32 v35, v5
; GFX9-NEXT:    v_mov_b32_e32 v36, v4
; GFX9-NEXT:    v_mov_b32_e32 v37, v3
; GFX9-NEXT:    v_mov_b32_e32 v38, v2
; GFX9-NEXT:    v_mov_b32_e32 v39, v1
; GFX9-NEXT:    s_waitcnt vmcnt(8)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB34_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    s_mov_b32 s6, 0xc0c0004
; GFX9-NEXT:    v_perm_b32 v0, v48, v39, s6
; GFX9-NEXT:    v_perm_b32 v1, v38, v37, s6
; GFX9-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT:    v_perm_b32 v1, v36, v35, s6
; GFX9-NEXT:    v_perm_b32 v2, v34, v33, s6
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    v_perm_b32 v2, v32, v31, s6
; GFX9-NEXT:    v_perm_b32 v3, v10, v11, s6
; GFX9-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT:    v_perm_b32 v3, v12, v13, s6
; GFX9-NEXT:    v_perm_b32 v4, v14, v15, s6
; GFX9-NEXT:    v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT:    v_perm_b32 v4, v16, v17, s6
; GFX9-NEXT:    v_perm_b32 v5, v18, v19, s6
; GFX9-NEXT:    v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT:    v_perm_b32 v5, v20, v21, s6
; GFX9-NEXT:    v_perm_b32 v6, v22, v23, s6
; GFX9-NEXT:    v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT:    v_perm_b32 v6, v24, v25, s6
; GFX9-NEXT:    v_perm_b32 v7, v26, v27, s6
; GFX9-NEXT:    v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT:    v_perm_b32 v7, v28, v29, s6
; GFX9-NEXT:    v_perm_b32 v8, v30, v55, s6
; GFX9-NEXT:    v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    v_perm_b32 v8, v41, v40, s6
; GFX9-NEXT:    v_perm_b32 v9, v54, v53, s6
; GFX9-NEXT:    v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT:    v_perm_b32 v9, v52, v51, s6
; GFX9-NEXT:    v_perm_b32 v10, v50, v49, s6
; GFX9-NEXT:    v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT:    ; implicit-def: $vgpr48
; GFX9-NEXT:    ; implicit-def: $vgpr39
; GFX9-NEXT:    ; implicit-def: $vgpr38
; GFX9-NEXT:    ; implicit-def: $vgpr37
; GFX9-NEXT:    ; implicit-def: $vgpr36
; GFX9-NEXT:    ; implicit-def: $vgpr35
; GFX9-NEXT:    ; implicit-def: $vgpr34
; GFX9-NEXT:    ; implicit-def: $vgpr33
; GFX9-NEXT:    ; implicit-def: $vgpr32
; GFX9-NEXT:    ; implicit-def: $vgpr31
; GFX9-NEXT:    ; implicit-def: $vgpr10
; GFX9-NEXT:    ; implicit-def: $vgpr11
; GFX9-NEXT:    ; implicit-def: $vgpr12
; GFX9-NEXT:    ; implicit-def: $vgpr13
; GFX9-NEXT:    ; implicit-def: $vgpr14
; GFX9-NEXT:    ; implicit-def: $vgpr15
; GFX9-NEXT:    ; implicit-def: $vgpr16
; GFX9-NEXT:    ; implicit-def: $vgpr17
; GFX9-NEXT:    ; implicit-def: $vgpr18
; GFX9-NEXT:    ; implicit-def: $vgpr19
; GFX9-NEXT:    ; implicit-def: $vgpr20
; GFX9-NEXT:    ; implicit-def: $vgpr21
; GFX9-NEXT:    ; implicit-def: $vgpr22
; GFX9-NEXT:    ; implicit-def: $vgpr23
; GFX9-NEXT:    ; implicit-def: $vgpr24
; GFX9-NEXT:    ; implicit-def: $vgpr25
; GFX9-NEXT:    ; implicit-def: $vgpr26
; GFX9-NEXT:    ; implicit-def: $vgpr27
; GFX9-NEXT:    ; implicit-def: $vgpr28
; GFX9-NEXT:    ; implicit-def: $vgpr29
; GFX9-NEXT:    ; implicit-def: $vgpr30
; GFX9-NEXT:    ; implicit-def: $vgpr55
; GFX9-NEXT:    ; implicit-def: $vgpr41
; GFX9-NEXT:    ; implicit-def: $vgpr40
; GFX9-NEXT:    ; implicit-def: $vgpr54
; GFX9-NEXT:    ; implicit-def: $vgpr53
; GFX9-NEXT:    ; implicit-def: $vgpr52
; GFX9-NEXT:    ; implicit-def: $vgpr51
; GFX9-NEXT:    ; implicit-def: $vgpr50
; GFX9-NEXT:    ; implicit-def: $vgpr49
; GFX9-NEXT:  .LBB34_2: ; %Flow
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB34_4
; GFX9-NEXT:  ; %bb.3: ; %cmp.true
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v48
; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v39
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v1, 3, v38
; GFX9-NEXT:    v_lshlrev_b16_e32 v2, 8, v37
; GFX9-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v0, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v1, 0x300, v1
; GFX9-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT:    v_add_u16_e32 v1, 3, v36
; GFX9-NEXT:    v_lshlrev_b16_e32 v2, 8, v35
; GFX9-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v2, 3, v34
; GFX9-NEXT:    v_lshlrev_b16_e32 v3, 8, v33
; GFX9-NEXT:    v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v1, 0x300, v1
; GFX9-NEXT:    v_add_u16_e32 v2, 0x300, v2
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    v_add_u16_e32 v2, 3, v32
; GFX9-NEXT:    v_lshlrev_b16_e32 v3, 8, v31
; GFX9-NEXT:    v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v3, 3, v10
; GFX9-NEXT:    v_lshlrev_b16_e32 v4, 8, v11
; GFX9-NEXT:    v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v2, 0x300, v2
; GFX9-NEXT:    v_add_u16_e32 v3, 0x300, v3
; GFX9-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT:    v_add_u16_e32 v3, 3, v12
; GFX9-NEXT:    v_lshlrev_b16_e32 v4, 8, v13
; GFX9-NEXT:    v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v4, 3, v14
; GFX9-NEXT:    v_lshlrev_b16_e32 v5, 8, v15
; GFX9-NEXT:    v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v3, 0x300, v3
; GFX9-NEXT:    v_add_u16_e32 v4, 0x300, v4
; GFX9-NEXT:    v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT:    v_add_u16_e32 v4, 3, v16
; GFX9-NEXT:    v_lshlrev_b16_e32 v5, 8, v17
; GFX9-NEXT:    v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v5, 3, v18
; GFX9-NEXT:    v_lshlrev_b16_e32 v6, 8, v19
; GFX9-NEXT:    v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v4, 0x300, v4
; GFX9-NEXT:    v_add_u16_e32 v5, 0x300, v5
; GFX9-NEXT:    v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT:    v_add_u16_e32 v5, 3, v20
; GFX9-NEXT:    v_lshlrev_b16_e32 v6, 8, v21
; GFX9-NEXT:    v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v6, 3, v22
; GFX9-NEXT:    v_lshlrev_b16_e32 v7, 8, v23
; GFX9-NEXT:    v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v5, 0x300, v5
; GFX9-NEXT:    v_add_u16_e32 v6, 0x300, v6
; GFX9-NEXT:    v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT:    v_add_u16_e32 v6, 3, v24
; GFX9-NEXT:    v_lshlrev_b16_e32 v7, 8, v25
; GFX9-NEXT:    v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v7, 3, v26
; GFX9-NEXT:    v_lshlrev_b16_e32 v8, 8, v27
; GFX9-NEXT:    v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v6, 0x300, v6
; GFX9-NEXT:    v_add_u16_e32 v7, 0x300, v7
; GFX9-NEXT:    v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT:    v_add_u16_e32 v7, 3, v28
; GFX9-NEXT:    v_lshlrev_b16_e32 v8, 8, v29
; GFX9-NEXT:    v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v8, 3, v30
; GFX9-NEXT:    v_lshlrev_b16_e32 v9, 8, v55
; GFX9-NEXT:    v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v7, 0x300, v7
; GFX9-NEXT:    v_add_u16_e32 v8, 0x300, v8
; GFX9-NEXT:    v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    v_add_u16_e32 v8, 3, v41
; GFX9-NEXT:    v_lshlrev_b16_e32 v9, 8, v40
; GFX9-NEXT:    v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v9, 3, v54
; GFX9-NEXT:    v_lshlrev_b16_e32 v10, 8, v53
; GFX9-NEXT:    v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v8, 0x300, v8
; GFX9-NEXT:    v_add_u16_e32 v9, 0x300, v9
; GFX9-NEXT:    v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT:    v_add_u16_e32 v9, 3, v52
; GFX9-NEXT:    v_lshlrev_b16_e32 v10, 8, v51
; GFX9-NEXT:    v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v10, 3, v50
; GFX9-NEXT:    v_lshlrev_b16_e32 v11, 8, v49
; GFX9-NEXT:    v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v9, 0x300, v9
; GFX9-NEXT:    v_add_u16_e32 v10, 0x300, v10
; GFX9-NEXT:    v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT:  .LBB34_4: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; GFX9-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v40i8_to_v10f32:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    s_clause 0x9
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v31, off, s32 offset:32
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v32, off, s32 offset:28
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v33, off, s32 offset:24
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v34, off, s32 offset:20
; GFX11-TRUE16-NEXT:    scratch_load_b32 v66, off, s32 offset:36
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v35, off, s32 offset:16
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v37, off, s32 offset:12
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v36, off, s32 offset:8
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v38, off, s32 offset:4
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v39, off, s32
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v48.l, v9.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v49.l, v8.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v50.l, v7.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v51.l, v6.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v52.l, v5.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v53.l, v4.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v54.l, v3.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v2.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v64.l, v1.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v65.l, v0.l
; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(5)
; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v66
; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB34_3
; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB34_4
; GFX11-TRUE16-NEXT:  .LBB34_2: ; %end
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT:  .LBB34_3: ; %cmp.false
; GFX11-TRUE16-NEXT:    v_perm_b32 v0, v65, v64, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v1, v55, v54, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v2, v53, v52, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v3, v51, v50, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v4, v49, v48, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v5, v10, v11, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, v12, v13, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, v14, v15, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v8, v16, v17, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v9, v18, v19, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v1, v3, 16, v2
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v2, v5, 16, v4
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v3, v7, 16, v6
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v4, v9, 16, v8
; GFX11-TRUE16-NEXT:    v_perm_b32 v5, v20, v21, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, v22, v23, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, v24, v25, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v8, v26, v27, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v9, v28, v29, 0xc0c0004
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT:    v_perm_b32 v10, v30, v39, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v11, v38, v36, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v12, v37, v35, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v13, v34, v33, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v14, v32, v31, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v5, v6, 16, v5
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v6, v8, 16, v7
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v7, v10, 16, v9
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v8, v12, 16, v11
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v9, v14, 16, v13
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr65_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr11_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_lo16
; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB34_2
; GFX11-TRUE16-NEXT:  .LBB34_4: ; %cmp.true
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v65.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v55.l, 3
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v64.l
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 8, v54.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v53.l, 3
; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, 0xff
; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, v0.h, 0xff
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v51.l, 3
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v52.l
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v50.l
; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v1.h, v0.h
; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, v2.l, 0xff
; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, v3.l, 0xff
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v49.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v10.l, 3
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.l, 8, v13.l
; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v2.h, v1.l
; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v3.h, v1.h
; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, v2.l, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v48.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, v12.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.h, v14.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, v16.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, v18.l, 3
; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.h, v2.l
; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, v3.l, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.l, 8, v11.l
; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, v3.h, 0xff
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, v22.l, 3
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v23.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, v24.l, 3
; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v3.l, v2.h
; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v4.l, v3.h
; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, v4.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.l, 8, v15.l
; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, v5.l, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.l, 8, v17.l
; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, v6.l, 0xff
; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, v7.l, 0xff
; GFX11-TRUE16-NEXT:    v_or_b16 v3.h, v4.l, v3.h
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v25.l
; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v5.l, v4.h
; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, v5.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.l, 8, v19.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, v20.l, 3
; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.h, v6.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, v28.l, 3
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.l, 8, v27.l
; GFX11-TRUE16-NEXT:    v_or_b16 v4.h, v5.l, v4.h
; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, v5.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v21.l
; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, v6.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v29.l
; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.h, v7.l
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(3)
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, v37.l, 3
; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.h, v5.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, v26.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.h, v34.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v10.h, v32.l, 3
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(2)
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.l, 8, v36.l
; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, v9.l, 0xff
; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, v5.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.l, 8, v35.l
; GFX11-TRUE16-NEXT:    v_and_b16 v9.h, v9.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v33.l
; GFX11-TRUE16-NEXT:    v_and_b16 v10.h, v10.h, 0xff
; GFX11-TRUE16-NEXT:    v_or_b16 v7.h, v8.l, v5.h
; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.h, v6.h
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.h, v30.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, v6.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, v7.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, v7.h, 0x300
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, v38.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, v8.l, 0x300
; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, v8.h, 0xff
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v39.l
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.l, 8, v31.l
; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, v7.h, 0xff
; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v11.l, v9.l
; GFX11-TRUE16-NEXT:    v_or_b16 v9.h, v11.h, v9.h
; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.h, v8.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, 0x300
; GFX11-TRUE16-NEXT:    v_or_b16 v8.h, v10.l, v7.h
; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v12.l, v10.h
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v0.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v1.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v1.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v2.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v2.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v3.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, v3.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, v4.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.h, v4.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, v5.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, v8.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, v8.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.h, v9.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, v9.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.h, v10.l, 0x300
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v40i8_to_v10f32:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v39, v1 :: v_dual_mov_b32 v48, v0
; GFX11-FAKE16-NEXT:    s_clause 0x9
; GFX11-FAKE16-NEXT:    scratch_load_u16 v49, off, s32 offset:32
; GFX11-FAKE16-NEXT:    scratch_load_u16 v50, off, s32 offset:28
; GFX11-FAKE16-NEXT:    scratch_load_u16 v51, off, s32 offset:24
; GFX11-FAKE16-NEXT:    scratch_load_u16 v53, off, s32 offset:20
; GFX11-FAKE16-NEXT:    scratch_load_b32 v0, off, s32 offset:36
; GFX11-FAKE16-NEXT:    scratch_load_u16 v52, off, s32 offset:16
; GFX11-FAKE16-NEXT:    scratch_load_u16 v54, off, s32 offset:12
; GFX11-FAKE16-NEXT:    scratch_load_u16 v55, off, s32 offset:8
; GFX11-FAKE16-NEXT:    scratch_load_u16 v65, off, s32 offset:4
; GFX11-FAKE16-NEXT:    scratch_load_u16 v64, off, s32
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v31, v9 :: v_dual_mov_b32 v32, v8
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v34, v6
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v35, v5 :: v_dual_mov_b32 v36, v4
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v37, v3 :: v_dual_mov_b32 v38, v2
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(5)
; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB34_3
; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB34_4
; GFX11-FAKE16-NEXT:  .LBB34_2: ; %end
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT:  .LBB34_3: ; %cmp.false
; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v48, v39, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v38, v37, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v36, v35, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v34, v33, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v32, v31, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v10, v11, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v12, v13, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v14, v15, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v16, v17, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v18, v19, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, v5, 16, v4
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v3, v7, 16, v6
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v4, v9, 16, v8
; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v20, v21, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v22, v23, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v24, v25, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v26, v27, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v28, v29, 0xc0c0004
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v30, v64, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v65, v55, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v54, v52, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v53, v51, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v50, v49, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v5, v6, 16, v5
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v6, v8, 16, v7
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v7, v10, 16, v9
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v8, v12, 16, v11
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v9, v14, 16, v13
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr55
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB34_2
; GFX11-FAKE16-NEXT:  .LBB34_4: ; %cmp.true
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v48, 3
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v39
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v36, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v32, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v38, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v35
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v34, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v10, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v1, v0
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v31
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v37
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v33
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v5, v4
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v8
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v9
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 8, v11
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v0, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v3, v2
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v4, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v7, v6
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v1, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v8, v5
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v2, 0x300
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v4, 0x300
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v1
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v5, 0x300
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v12, 3
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v2, 16, v0
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v4, 16, v3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v16, 3
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, v5, 16, v6
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v7
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v13
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v14, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v17
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v18, 3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v5, v4
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v6
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v6, 8, v15
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v7, v3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v8
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 8, v19
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v4, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v6, v5
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v20, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v3, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v8, v7
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v5, 0x300
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v9
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 8, v21
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v6, 0x300
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v3, v5, 16, v4
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v24, 3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v22, 3
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v4, v6, 16, v9
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v9, 8, v25
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v7, 0x300
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v8
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v28, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v26, 3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v9, v5
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v23
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v12, 8, v29
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v10
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v5, 0x300
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v10, 8, v27
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v11, v7
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v12, v8
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, v53, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v5
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v65, 3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v10, v9
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v30, 3
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v14, 8, v55
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, v54, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v51
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, v50, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v64
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v14, v5
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v15
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v52
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v16, v12
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v17
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v49
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v8, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v13, v10
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v5, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v15, v14
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, v12, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v17, v16
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v7, 0x300
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v9, 0x300
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v10, 0x300
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v5
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, v13, 0x300
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, v14, 0x300
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v5, v7, 16, v6
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v6, v9, 16, v11
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v7, v10, 16, v8
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v8, v13, 16, v15
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v9, v14, 16, v12
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <40 x i8> %a, splat (i8 3)
  %a2 = bitcast <40 x i8> %a1 to <10 x float>
  br label %end

cmp.false:
  %a3 = bitcast <40 x i8> %a to <10 x float>
  br label %end

end:
  %phi = phi <10 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <10 x float> %phi
}

define inreg <10 x float> @bitcast_v40i8_to_v10f32_scalar(<40 x i8> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v40i8_to_v10f32_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_readfirstlane_b32 s4, v26
; SI-NEXT:    v_readfirstlane_b32 s5, v25
; SI-NEXT:    v_readfirstlane_b32 s6, v24
; SI-NEXT:    v_readfirstlane_b32 s8, v23
; SI-NEXT:    v_readfirstlane_b32 s9, v22
; SI-NEXT:    v_readfirstlane_b32 s10, v21
; SI-NEXT:    v_readfirstlane_b32 s11, v20
; SI-NEXT:    v_readfirstlane_b32 s13, v19
; SI-NEXT:    v_readfirstlane_b32 s14, v18
; SI-NEXT:    v_readfirstlane_b32 s40, v17
; SI-NEXT:    v_readfirstlane_b32 s41, v16
; SI-NEXT:    v_readfirstlane_b32 s42, v15
; SI-NEXT:    v_readfirstlane_b32 s43, v14
; SI-NEXT:    v_readfirstlane_b32 s44, v13
; SI-NEXT:    v_readfirstlane_b32 s45, v12
; SI-NEXT:    v_readfirstlane_b32 s46, v11
; SI-NEXT:    v_readfirstlane_b32 s47, v10
; SI-NEXT:    v_readfirstlane_b32 s56, v9
; SI-NEXT:    v_readfirstlane_b32 s57, v8
; SI-NEXT:    v_readfirstlane_b32 s58, v7
; SI-NEXT:    v_readfirstlane_b32 s59, v6
; SI-NEXT:    v_readfirstlane_b32 s60, v5
; SI-NEXT:    v_readfirstlane_b32 s61, v4
; SI-NEXT:    s_cmp_lg_u32 s4, 0
; SI-NEXT:    v_readfirstlane_b32 s62, v3
; SI-NEXT:    v_readfirstlane_b32 s63, v2
; SI-NEXT:    v_readfirstlane_b32 s15, v1
; SI-NEXT:    v_readfirstlane_b32 s72, v0
; SI-NEXT:    s_cbranch_scc0 .LBB35_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    s_and_b32 s4, s16, 0xff
; SI-NEXT:    s_lshl_b32 s7, s17, 8
; SI-NEXT:    s_or_b32 s4, s4, s7
; SI-NEXT:    s_and_b32 s7, s18, 0xff
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_lshl_b32 s12, s19, 24
; SI-NEXT:    s_and_b32 s4, s4, 0xffff
; SI-NEXT:    s_or_b32 s7, s12, s7
; SI-NEXT:    s_or_b32 s4, s4, s7
; SI-NEXT:    s_and_b32 s7, s20, 0xff
; SI-NEXT:    s_lshl_b32 s12, s21, 8
; SI-NEXT:    s_or_b32 s7, s7, s12
; SI-NEXT:    s_and_b32 s12, s22, 0xff
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_lshl_b32 s16, s23, 24
; SI-NEXT:    s_and_b32 s7, s7, 0xffff
; SI-NEXT:    s_or_b32 s12, s16, s12
; SI-NEXT:    s_or_b32 s7, s7, s12
; SI-NEXT:    s_and_b32 s12, s24, 0xff
; SI-NEXT:    s_lshl_b32 s16, s25, 8
; SI-NEXT:    s_or_b32 s12, s12, s16
; SI-NEXT:    s_and_b32 s16, s26, 0xff
; SI-NEXT:    s_lshl_b32 s16, s16, 16
; SI-NEXT:    s_lshl_b32 s17, s27, 24
; SI-NEXT:    s_and_b32 s12, s12, 0xffff
; SI-NEXT:    s_or_b32 s16, s17, s16
; SI-NEXT:    s_or_b32 s12, s12, s16
; SI-NEXT:    s_and_b32 s16, s28, 0xff
; SI-NEXT:    s_lshl_b32 s17, s29, 8
; SI-NEXT:    s_or_b32 s16, s16, s17
; SI-NEXT:    s_and_b32 s17, s72, 0xff
; SI-NEXT:    s_lshl_b32 s17, s17, 16
; SI-NEXT:    s_lshl_b32 s15, s15, 24
; SI-NEXT:    s_and_b32 s16, s16, 0xffff
; SI-NEXT:    s_or_b32 s15, s15, s17
; SI-NEXT:    s_or_b32 s15, s16, s15
; SI-NEXT:    s_and_b32 s16, s63, 0xff
; SI-NEXT:    s_lshl_b32 s17, s62, 8
; SI-NEXT:    s_or_b32 s16, s16, s17
; SI-NEXT:    s_and_b32 s17, s61, 0xff
; SI-NEXT:    s_lshl_b32 s17, s17, 16
; SI-NEXT:    s_lshl_b32 s18, s60, 24
; SI-NEXT:    s_and_b32 s16, s16, 0xffff
; SI-NEXT:    s_or_b32 s17, s18, s17
; SI-NEXT:    s_or_b32 s16, s16, s17
; SI-NEXT:    s_and_b32 s17, s59, 0xff
; SI-NEXT:    s_lshl_b32 s18, s58, 8
; SI-NEXT:    s_or_b32 s17, s17, s18
; SI-NEXT:    s_and_b32 s18, s57, 0xff
; SI-NEXT:    s_lshl_b32 s18, s18, 16
; SI-NEXT:    s_lshl_b32 s19, s56, 24
; SI-NEXT:    s_and_b32 s17, s17, 0xffff
; SI-NEXT:    s_or_b32 s18, s19, s18
; SI-NEXT:    s_or_b32 s17, s17, s18
; SI-NEXT:    s_and_b32 s18, s47, 0xff
; SI-NEXT:    s_lshl_b32 s19, s46, 8
; SI-NEXT:    s_or_b32 s18, s18, s19
; SI-NEXT:    s_and_b32 s19, s45, 0xff
; SI-NEXT:    s_lshl_b32 s19, s19, 16
; SI-NEXT:    s_lshl_b32 s20, s44, 24
; SI-NEXT:    s_and_b32 s18, s18, 0xffff
; SI-NEXT:    s_or_b32 s19, s20, s19
; SI-NEXT:    s_or_b32 s18, s18, s19
; SI-NEXT:    s_and_b32 s19, s43, 0xff
; SI-NEXT:    s_lshl_b32 s20, s42, 8
; SI-NEXT:    s_or_b32 s19, s19, s20
; SI-NEXT:    s_and_b32 s20, s41, 0xff
; SI-NEXT:    s_and_b32 s14, s14, 0xff
; SI-NEXT:    s_lshl_b32 s13, s13, 8
; SI-NEXT:    s_and_b32 s11, s11, 0xff
; SI-NEXT:    s_and_b32 s9, s9, 0xff
; SI-NEXT:    s_lshl_b32 s8, s8, 8
; SI-NEXT:    s_and_b32 s6, s6, 0xff
; SI-NEXT:    s_lshl_b32 s20, s20, 16
; SI-NEXT:    s_lshl_b32 s21, s40, 24
; SI-NEXT:    s_or_b32 s13, s14, s13
; SI-NEXT:    s_lshl_b32 s11, s11, 16
; SI-NEXT:    s_lshl_b32 s10, s10, 24
; SI-NEXT:    s_or_b32 s8, s9, s8
; SI-NEXT:    s_lshl_b32 s6, s6, 16
; SI-NEXT:    s_lshl_b32 s5, s5, 24
; SI-NEXT:    s_and_b32 s19, s19, 0xffff
; SI-NEXT:    s_or_b32 s20, s21, s20
; SI-NEXT:    s_and_b32 s13, s13, 0xffff
; SI-NEXT:    s_or_b32 s10, s10, s11
; SI-NEXT:    s_and_b32 s8, s8, 0xffff
; SI-NEXT:    s_or_b32 s5, s5, s6
; SI-NEXT:    s_or_b32 s19, s19, s20
; SI-NEXT:    s_or_b32 s10, s13, s10
; SI-NEXT:    s_or_b32 s5, s8, s5
; SI-NEXT:    s_branch .LBB35_3
; SI-NEXT:  .LBB35_2: ; %cmp.true
; SI-NEXT:    s_add_i32 s16, s16, 3
; SI-NEXT:    s_and_b32 s4, s16, 0xff
; SI-NEXT:    s_lshl_b32 s7, s17, 8
; SI-NEXT:    s_add_i32 s18, s18, 3
; SI-NEXT:    s_or_b32 s4, s7, s4
; SI-NEXT:    s_and_b32 s12, s18, 0xff
; SI-NEXT:    s_addk_i32 s4, 0x300
; SI-NEXT:    s_lshl_b32 s7, s19, 24
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_and_b32 s4, s4, 0xffff
; SI-NEXT:    s_or_b32 s7, s7, s12
; SI-NEXT:    s_add_i32 s20, s20, 3
; SI-NEXT:    s_or_b32 s4, s7, s4
; SI-NEXT:    s_and_b32 s7, s20, 0xff
; SI-NEXT:    s_lshl_b32 s12, s21, 8
; SI-NEXT:    s_add_i32 s22, s22, 3
; SI-NEXT:    s_or_b32 s7, s12, s7
; SI-NEXT:    s_and_b32 s16, s22, 0xff
; SI-NEXT:    s_addk_i32 s7, 0x300
; SI-NEXT:    s_lshl_b32 s12, s23, 24
; SI-NEXT:    s_lshl_b32 s16, s16, 16
; SI-NEXT:    s_and_b32 s7, s7, 0xffff
; SI-NEXT:    s_or_b32 s12, s12, s16
; SI-NEXT:    s_add_i32 s24, s24, 3
; SI-NEXT:    s_or_b32 s7, s12, s7
; SI-NEXT:    s_and_b32 s12, s24, 0xff
; SI-NEXT:    s_lshl_b32 s16, s25, 8
; SI-NEXT:    s_add_i32 s26, s26, 3
; SI-NEXT:    s_or_b32 s12, s16, s12
; SI-NEXT:    s_and_b32 s17, s26, 0xff
; SI-NEXT:    s_addk_i32 s12, 0x300
; SI-NEXT:    s_lshl_b32 s16, s27, 24
; SI-NEXT:    s_lshl_b32 s17, s17, 16
; SI-NEXT:    s_and_b32 s12, s12, 0xffff
; SI-NEXT:    s_or_b32 s16, s16, s17
; SI-NEXT:    s_add_i32 s28, s28, 3
; SI-NEXT:    s_or_b32 s12, s16, s12
; SI-NEXT:    s_and_b32 s16, s28, 0xff
; SI-NEXT:    s_lshl_b32 s17, s29, 8
; SI-NEXT:    s_add_i32 s72, s72, 3
; SI-NEXT:    s_or_b32 s16, s17, s16
; SI-NEXT:    s_and_b32 s17, s72, 0xff
; SI-NEXT:    s_addk_i32 s16, 0x300
; SI-NEXT:    s_lshl_b32 s15, s15, 24
; SI-NEXT:    s_lshl_b32 s17, s17, 16
; SI-NEXT:    s_and_b32 s16, s16, 0xffff
; SI-NEXT:    s_or_b32 s15, s15, s17
; SI-NEXT:    s_add_i32 s63, s63, 3
; SI-NEXT:    s_or_b32 s15, s15, s16
; SI-NEXT:    s_and_b32 s16, s63, 0xff
; SI-NEXT:    s_lshl_b32 s17, s62, 8
; SI-NEXT:    s_add_i32 s61, s61, 3
; SI-NEXT:    s_or_b32 s16, s17, s16
; SI-NEXT:    s_and_b32 s18, s61, 0xff
; SI-NEXT:    s_addk_i32 s16, 0x300
; SI-NEXT:    s_lshl_b32 s17, s60, 24
; SI-NEXT:    s_lshl_b32 s18, s18, 16
; SI-NEXT:    s_and_b32 s16, s16, 0xffff
; SI-NEXT:    s_or_b32 s17, s17, s18
; SI-NEXT:    s_add_i32 s59, s59, 3
; SI-NEXT:    s_or_b32 s16, s17, s16
; SI-NEXT:    s_and_b32 s17, s59, 0xff
; SI-NEXT:    s_lshl_b32 s18, s58, 8
; SI-NEXT:    s_add_i32 s57, s57, 3
; SI-NEXT:    s_or_b32 s17, s18, s17
; SI-NEXT:    s_and_b32 s19, s57, 0xff
; SI-NEXT:    s_addk_i32 s17, 0x300
; SI-NEXT:    s_lshl_b32 s18, s56, 24
; SI-NEXT:    s_lshl_b32 s19, s19, 16
; SI-NEXT:    s_and_b32 s17, s17, 0xffff
; SI-NEXT:    s_or_b32 s18, s18, s19
; SI-NEXT:    s_add_i32 s47, s47, 3
; SI-NEXT:    s_or_b32 s17, s18, s17
; SI-NEXT:    s_and_b32 s18, s47, 0xff
; SI-NEXT:    s_lshl_b32 s19, s46, 8
; SI-NEXT:    s_add_i32 s45, s45, 3
; SI-NEXT:    s_or_b32 s18, s19, s18
; SI-NEXT:    s_and_b32 s20, s45, 0xff
; SI-NEXT:    s_addk_i32 s18, 0x300
; SI-NEXT:    s_lshl_b32 s19, s44, 24
; SI-NEXT:    s_lshl_b32 s20, s20, 16
; SI-NEXT:    s_and_b32 s18, s18, 0xffff
; SI-NEXT:    s_or_b32 s19, s19, s20
; SI-NEXT:    s_add_i32 s43, s43, 3
; SI-NEXT:    s_add_i32 s14, s14, 3
; SI-NEXT:    s_add_i32 s9, s9, 3
; SI-NEXT:    s_or_b32 s18, s19, s18
; SI-NEXT:    s_and_b32 s19, s43, 0xff
; SI-NEXT:    s_lshl_b32 s20, s42, 8
; SI-NEXT:    s_add_i32 s41, s41, 3
; SI-NEXT:    s_and_b32 s14, s14, 0xff
; SI-NEXT:    s_lshl_b32 s13, s13, 8
; SI-NEXT:    s_add_i32 s11, s11, 3
; SI-NEXT:    s_and_b32 s9, s9, 0xff
; SI-NEXT:    s_lshl_b32 s8, s8, 8
; SI-NEXT:    s_add_i32 s6, s6, 3
; SI-NEXT:    s_or_b32 s19, s20, s19
; SI-NEXT:    s_and_b32 s21, s41, 0xff
; SI-NEXT:    s_or_b32 s13, s13, s14
; SI-NEXT:    s_and_b32 s11, s11, 0xff
; SI-NEXT:    s_or_b32 s8, s8, s9
; SI-NEXT:    s_and_b32 s6, s6, 0xff
; SI-NEXT:    s_addk_i32 s19, 0x300
; SI-NEXT:    s_lshl_b32 s20, s40, 24
; SI-NEXT:    s_lshl_b32 s21, s21, 16
; SI-NEXT:    s_addk_i32 s13, 0x300
; SI-NEXT:    s_lshl_b32 s10, s10, 24
; SI-NEXT:    s_lshl_b32 s11, s11, 16
; SI-NEXT:    s_addk_i32 s8, 0x300
; SI-NEXT:    s_lshl_b32 s5, s5, 24
; SI-NEXT:    s_lshl_b32 s6, s6, 16
; SI-NEXT:    s_and_b32 s19, s19, 0xffff
; SI-NEXT:    s_or_b32 s20, s20, s21
; SI-NEXT:    s_and_b32 s13, s13, 0xffff
; SI-NEXT:    s_or_b32 s10, s10, s11
; SI-NEXT:    s_and_b32 s8, s8, 0xffff
; SI-NEXT:    s_or_b32 s5, s5, s6
; SI-NEXT:    s_or_b32 s19, s20, s19
; SI-NEXT:    s_or_b32 s10, s10, s13
; SI-NEXT:    s_or_b32 s5, s5, s8
; SI-NEXT:    s_add_i32 s4, s4, 0x3000000
; SI-NEXT:    s_add_i32 s7, s7, 0x3000000
; SI-NEXT:    s_add_i32 s12, s12, 0x3000000
; SI-NEXT:    s_add_i32 s15, s15, 0x3000000
; SI-NEXT:    s_add_i32 s16, s16, 0x3000000
; SI-NEXT:    s_add_i32 s17, s17, 0x3000000
; SI-NEXT:    s_add_i32 s18, s18, 0x3000000
; SI-NEXT:    s_add_i32 s19, s19, 0x3000000
; SI-NEXT:    s_add_i32 s10, s10, 0x3000000
; SI-NEXT:    s_add_i32 s5, s5, 0x3000000
; SI-NEXT:  .LBB35_3: ; %end
; SI-NEXT:    v_mov_b32_e32 v0, s4
; SI-NEXT:    v_mov_b32_e32 v1, s7
; SI-NEXT:    v_mov_b32_e32 v2, s12
; SI-NEXT:    v_mov_b32_e32 v3, s15
; SI-NEXT:    v_mov_b32_e32 v4, s16
; SI-NEXT:    v_mov_b32_e32 v5, s17
; SI-NEXT:    v_mov_b32_e32 v6, s18
; SI-NEXT:    v_mov_b32_e32 v7, s19
; SI-NEXT:    v_mov_b32_e32 v8, s10
; SI-NEXT:    v_mov_b32_e32 v9, s5
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v40i8_to_v10f32_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_readfirstlane_b32 s61, v26
; VI-NEXT:    v_readfirstlane_b32 s4, v25
; VI-NEXT:    v_readfirstlane_b32 s5, v24
; VI-NEXT:    v_readfirstlane_b32 s6, v23
; VI-NEXT:    v_readfirstlane_b32 s7, v22
; VI-NEXT:    v_readfirstlane_b32 s8, v21
; VI-NEXT:    v_readfirstlane_b32 s9, v20
; VI-NEXT:    v_readfirstlane_b32 s10, v19
; VI-NEXT:    v_readfirstlane_b32 s11, v18
; VI-NEXT:    v_readfirstlane_b32 s12, v17
; VI-NEXT:    v_readfirstlane_b32 s13, v16
; VI-NEXT:    v_readfirstlane_b32 s14, v15
; VI-NEXT:    v_readfirstlane_b32 s15, v14
; VI-NEXT:    v_readfirstlane_b32 s40, v13
; VI-NEXT:    v_readfirstlane_b32 s41, v12
; VI-NEXT:    v_readfirstlane_b32 s42, v11
; VI-NEXT:    v_readfirstlane_b32 s43, v10
; VI-NEXT:    v_readfirstlane_b32 s44, v9
; VI-NEXT:    v_readfirstlane_b32 s45, v8
; VI-NEXT:    v_readfirstlane_b32 s46, v7
; VI-NEXT:    v_readfirstlane_b32 s47, v6
; VI-NEXT:    v_readfirstlane_b32 s56, v5
; VI-NEXT:    v_readfirstlane_b32 s57, v4
; VI-NEXT:    v_readfirstlane_b32 s58, v3
; VI-NEXT:    v_readfirstlane_b32 s59, v2
; VI-NEXT:    v_readfirstlane_b32 s60, v1
; VI-NEXT:    s_cmp_lg_u32 s61, 0
; VI-NEXT:    v_readfirstlane_b32 s61, v0
; VI-NEXT:    s_cbranch_scc0 .LBB35_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    v_mov_b32_e32 v9, 0xc0c0004
; VI-NEXT:    v_mov_b32_e32 v1, s19
; VI-NEXT:    v_mov_b32_e32 v0, s17
; VI-NEXT:    v_perm_b32 v1, s18, v1, v9
; VI-NEXT:    v_perm_b32 v0, s16, v0, v9
; VI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT:    v_mov_b32_e32 v2, s23
; VI-NEXT:    v_or_b32_e32 v0, v0, v1
; VI-NEXT:    v_mov_b32_e32 v1, s21
; VI-NEXT:    v_perm_b32 v2, s22, v2, v9
; VI-NEXT:    v_perm_b32 v1, s20, v1, v9
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_mov_b32_e32 v3, s27
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_mov_b32_e32 v2, s25
; VI-NEXT:    v_perm_b32 v3, s26, v3, v9
; VI-NEXT:    v_perm_b32 v2, s24, v2, v9
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_mov_b32_e32 v4, s60
; VI-NEXT:    v_or_b32_e32 v2, v2, v3
; VI-NEXT:    v_mov_b32_e32 v3, s29
; VI-NEXT:    v_perm_b32 v4, s61, v4, v9
; VI-NEXT:    v_perm_b32 v3, s28, v3, v9
; VI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT:    v_mov_b32_e32 v5, s56
; VI-NEXT:    v_or_b32_e32 v3, v3, v4
; VI-NEXT:    v_mov_b32_e32 v4, s58
; VI-NEXT:    v_perm_b32 v5, s57, v5, v9
; VI-NEXT:    v_perm_b32 v4, s59, v4, v9
; VI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT:    v_mov_b32_e32 v6, s44
; VI-NEXT:    v_or_b32_e32 v4, v4, v5
; VI-NEXT:    v_mov_b32_e32 v5, s46
; VI-NEXT:    v_perm_b32 v6, s45, v6, v9
; VI-NEXT:    v_perm_b32 v5, s47, v5, v9
; VI-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT:    v_mov_b32_e32 v7, s40
; VI-NEXT:    v_or_b32_e32 v5, v5, v6
; VI-NEXT:    v_mov_b32_e32 v6, s42
; VI-NEXT:    v_perm_b32 v7, s41, v7, v9
; VI-NEXT:    v_perm_b32 v6, s43, v6, v9
; VI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT:    v_mov_b32_e32 v8, s12
; VI-NEXT:    v_or_b32_e32 v6, v6, v7
; VI-NEXT:    v_mov_b32_e32 v7, s14
; VI-NEXT:    v_perm_b32 v8, s13, v8, v9
; VI-NEXT:    v_perm_b32 v7, s15, v7, v9
; VI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT:    v_mov_b32_e32 v10, s8
; VI-NEXT:    v_or_b32_e32 v7, v7, v8
; VI-NEXT:    v_mov_b32_e32 v8, s10
; VI-NEXT:    v_perm_b32 v10, s9, v10, v9
; VI-NEXT:    v_perm_b32 v8, s11, v8, v9
; VI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT:    v_or_b32_e32 v8, v8, v10
; VI-NEXT:    v_mov_b32_e32 v10, s6
; VI-NEXT:    v_mov_b32_e32 v11, s4
; VI-NEXT:    v_perm_b32 v10, s7, v10, v9
; VI-NEXT:    v_perm_b32 v9, s5, v11, v9
; VI-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT:    v_or_b32_e32 v9, v10, v9
; VI-NEXT:    s_setpc_b64 s[30:31]
; VI-NEXT:  .LBB35_2: ; %cmp.true
; VI-NEXT:    s_add_i32 s16, s16, 3
; VI-NEXT:    v_mov_b32_e32 v0, s17
; VI-NEXT:    v_mov_b32_e32 v9, 0xc0c0004
; VI-NEXT:    s_add_i32 s18, s18, 3
; VI-NEXT:    v_mov_b32_e32 v1, s19
; VI-NEXT:    v_perm_b32 v0, s16, v0, v9
; VI-NEXT:    v_perm_b32 v1, s18, v1, v9
; VI-NEXT:    v_add_u32_e32 v0, vcc, 0x300, v0
; VI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s20, s20, 3
; VI-NEXT:    v_mov_b32_e32 v1, s21
; VI-NEXT:    s_add_i32 s22, s22, 3
; VI-NEXT:    v_mov_b32_e32 v2, s23
; VI-NEXT:    v_perm_b32 v1, s20, v1, v9
; VI-NEXT:    v_perm_b32 v2, s22, v2, v9
; VI-NEXT:    v_add_u32_e32 v1, vcc, 0x300, v1
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s24, s24, 3
; VI-NEXT:    v_mov_b32_e32 v2, s25
; VI-NEXT:    s_add_i32 s26, s26, 3
; VI-NEXT:    v_mov_b32_e32 v3, s27
; VI-NEXT:    v_perm_b32 v2, s24, v2, v9
; VI-NEXT:    v_perm_b32 v3, s26, v3, v9
; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x300, v2
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s28, s28, 3
; VI-NEXT:    v_mov_b32_e32 v3, s29
; VI-NEXT:    s_add_i32 s61, s61, 3
; VI-NEXT:    v_mov_b32_e32 v4, s60
; VI-NEXT:    v_perm_b32 v3, s28, v3, v9
; VI-NEXT:    v_perm_b32 v4, s61, v4, v9
; VI-NEXT:    v_add_u32_e32 v3, vcc, 0x300, v3
; VI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT:    v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s59, s59, 3
; VI-NEXT:    v_mov_b32_e32 v4, s58
; VI-NEXT:    s_add_i32 s57, s57, 3
; VI-NEXT:    v_mov_b32_e32 v5, s56
; VI-NEXT:    v_perm_b32 v4, s59, v4, v9
; VI-NEXT:    v_perm_b32 v5, s57, v5, v9
; VI-NEXT:    v_add_u32_e32 v4, vcc, 0x300, v4
; VI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT:    v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s47, s47, 3
; VI-NEXT:    v_mov_b32_e32 v5, s46
; VI-NEXT:    s_add_i32 s45, s45, 3
; VI-NEXT:    v_mov_b32_e32 v6, s44
; VI-NEXT:    v_perm_b32 v5, s47, v5, v9
; VI-NEXT:    v_perm_b32 v6, s45, v6, v9
; VI-NEXT:    v_add_u32_e32 v5, vcc, 0x300, v5
; VI-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT:    v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s43, s43, 3
; VI-NEXT:    v_mov_b32_e32 v6, s42
; VI-NEXT:    s_add_i32 s41, s41, 3
; VI-NEXT:    v_mov_b32_e32 v7, s40
; VI-NEXT:    v_perm_b32 v6, s43, v6, v9
; VI-NEXT:    v_perm_b32 v7, s41, v7, v9
; VI-NEXT:    v_add_u32_e32 v6, vcc, 0x300, v6
; VI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT:    v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s15, s15, 3
; VI-NEXT:    v_mov_b32_e32 v7, s14
; VI-NEXT:    s_add_i32 s13, s13, 3
; VI-NEXT:    v_mov_b32_e32 v8, s12
; VI-NEXT:    v_perm_b32 v7, s15, v7, v9
; VI-NEXT:    v_perm_b32 v8, s13, v8, v9
; VI-NEXT:    v_add_u32_e32 v7, vcc, 0x300, v7
; VI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT:    v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s11, s11, 3
; VI-NEXT:    v_mov_b32_e32 v8, s10
; VI-NEXT:    s_add_i32 s9, s9, 3
; VI-NEXT:    v_mov_b32_e32 v10, s8
; VI-NEXT:    v_perm_b32 v8, s11, v8, v9
; VI-NEXT:    v_perm_b32 v10, s9, v10, v9
; VI-NEXT:    v_add_u32_e32 v8, vcc, 0x300, v8
; VI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT:    v_or_b32_sdwa v8, v10, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s7, s7, 3
; VI-NEXT:    v_mov_b32_e32 v10, s6
; VI-NEXT:    s_add_i32 s5, s5, 3
; VI-NEXT:    v_mov_b32_e32 v11, s4
; VI-NEXT:    v_perm_b32 v10, s7, v10, v9
; VI-NEXT:    v_perm_b32 v9, s5, v11, v9
; VI-NEXT:    v_add_u32_e32 v10, vcc, 0x300, v10
; VI-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT:    v_or_b32_sdwa v9, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    v_add_u32_e32 v0, vcc, 0x3000000, v0
; VI-NEXT:    v_add_u32_e32 v1, vcc, 0x3000000, v1
; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x3000000, v2
; VI-NEXT:    v_add_u32_e32 v3, vcc, 0x3000000, v3
; VI-NEXT:    v_add_u32_e32 v4, vcc, 0x3000000, v4
; VI-NEXT:    v_add_u32_e32 v5, vcc, 0x3000000, v5
; VI-NEXT:    v_add_u32_e32 v6, vcc, 0x3000000, v6
; VI-NEXT:    v_add_u32_e32 v7, vcc, 0x3000000, v7
; VI-NEXT:    v_add_u32_e32 v8, vcc, 0x3000000, v8
; VI-NEXT:    v_add_u32_e32 v9, vcc, 0x3000000, v9
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v40i8_to_v10f32_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_readfirstlane_b32 s61, v26
; GFX9-NEXT:    v_readfirstlane_b32 s4, v25
; GFX9-NEXT:    v_readfirstlane_b32 s5, v24
; GFX9-NEXT:    v_readfirstlane_b32 s6, v23
; GFX9-NEXT:    v_readfirstlane_b32 s7, v22
; GFX9-NEXT:    v_readfirstlane_b32 s8, v21
; GFX9-NEXT:    v_readfirstlane_b32 s9, v20
; GFX9-NEXT:    v_readfirstlane_b32 s10, v19
; GFX9-NEXT:    v_readfirstlane_b32 s11, v18
; GFX9-NEXT:    v_readfirstlane_b32 s12, v17
; GFX9-NEXT:    v_readfirstlane_b32 s13, v16
; GFX9-NEXT:    v_readfirstlane_b32 s14, v15
; GFX9-NEXT:    v_readfirstlane_b32 s15, v14
; GFX9-NEXT:    v_readfirstlane_b32 s40, v13
; GFX9-NEXT:    v_readfirstlane_b32 s41, v12
; GFX9-NEXT:    v_readfirstlane_b32 s42, v11
; GFX9-NEXT:    v_readfirstlane_b32 s43, v10
; GFX9-NEXT:    v_readfirstlane_b32 s44, v9
; GFX9-NEXT:    v_readfirstlane_b32 s45, v8
; GFX9-NEXT:    v_readfirstlane_b32 s46, v7
; GFX9-NEXT:    v_readfirstlane_b32 s47, v6
; GFX9-NEXT:    v_readfirstlane_b32 s56, v5
; GFX9-NEXT:    v_readfirstlane_b32 s57, v4
; GFX9-NEXT:    v_readfirstlane_b32 s58, v3
; GFX9-NEXT:    v_readfirstlane_b32 s59, v2
; GFX9-NEXT:    v_readfirstlane_b32 s60, v1
; GFX9-NEXT:    s_cmp_lg_u32 s61, 0
; GFX9-NEXT:    v_readfirstlane_b32 s61, v0
; GFX9-NEXT:    s_cbranch_scc0 .LBB35_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    v_mov_b32_e32 v9, 0xc0c0004
; GFX9-NEXT:    v_mov_b32_e32 v1, s19
; GFX9-NEXT:    v_mov_b32_e32 v0, s17
; GFX9-NEXT:    v_perm_b32 v1, s18, v1, v9
; GFX9-NEXT:    v_perm_b32 v0, s16, v0, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT:    v_mov_b32_e32 v2, s23
; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
; GFX9-NEXT:    v_mov_b32_e32 v1, s21
; GFX9-NEXT:    v_perm_b32 v2, s22, v2, v9
; GFX9-NEXT:    v_perm_b32 v1, s20, v1, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT:    v_mov_b32_e32 v3, s27
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v2
; GFX9-NEXT:    v_mov_b32_e32 v2, s25
; GFX9-NEXT:    v_perm_b32 v3, s26, v3, v9
; GFX9-NEXT:    v_perm_b32 v2, s24, v2, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT:    v_mov_b32_e32 v4, s60
; GFX9-NEXT:    v_or_b32_e32 v2, v2, v3
; GFX9-NEXT:    v_mov_b32_e32 v3, s29
; GFX9-NEXT:    v_perm_b32 v4, s61, v4, v9
; GFX9-NEXT:    v_perm_b32 v3, s28, v3, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; GFX9-NEXT:    v_mov_b32_e32 v5, s56
; GFX9-NEXT:    v_or_b32_e32 v3, v3, v4
; GFX9-NEXT:    v_mov_b32_e32 v4, s58
; GFX9-NEXT:    v_perm_b32 v5, s57, v5, v9
; GFX9-NEXT:    v_perm_b32 v4, s59, v4, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; GFX9-NEXT:    v_mov_b32_e32 v6, s44
; GFX9-NEXT:    v_or_b32_e32 v4, v4, v5
; GFX9-NEXT:    v_mov_b32_e32 v5, s46
; GFX9-NEXT:    v_perm_b32 v6, s45, v6, v9
; GFX9-NEXT:    v_perm_b32 v5, s47, v5, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; GFX9-NEXT:    v_mov_b32_e32 v7, s40
; GFX9-NEXT:    v_or_b32_e32 v5, v5, v6
; GFX9-NEXT:    v_mov_b32_e32 v6, s42
; GFX9-NEXT:    v_perm_b32 v7, s41, v7, v9
; GFX9-NEXT:    v_perm_b32 v6, s43, v6, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; GFX9-NEXT:    v_mov_b32_e32 v8, s12
; GFX9-NEXT:    v_or_b32_e32 v6, v6, v7
; GFX9-NEXT:    v_mov_b32_e32 v7, s14
; GFX9-NEXT:    v_perm_b32 v8, s13, v8, v9
; GFX9-NEXT:    v_perm_b32 v7, s15, v7, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; GFX9-NEXT:    v_mov_b32_e32 v10, s8
; GFX9-NEXT:    v_or_b32_e32 v7, v7, v8
; GFX9-NEXT:    v_mov_b32_e32 v8, s10
; GFX9-NEXT:    v_perm_b32 v10, s9, v10, v9
; GFX9-NEXT:    v_perm_b32 v8, s11, v8, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; GFX9-NEXT:    v_or_b32_e32 v8, v8, v10
; GFX9-NEXT:    v_mov_b32_e32 v10, s6
; GFX9-NEXT:    v_mov_b32_e32 v11, s4
; GFX9-NEXT:    v_perm_b32 v10, s7, v10, v9
; GFX9-NEXT:    v_perm_b32 v9, s5, v11, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; GFX9-NEXT:    v_or_b32_e32 v9, v10, v9
; GFX9-NEXT:    s_setpc_b64 s[30:31]
; GFX9-NEXT:  .LBB35_2: ; %cmp.true
; GFX9-NEXT:    s_add_i32 s16, s16, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s17
; GFX9-NEXT:    v_mov_b32_e32 v9, 0xc0c0004
; GFX9-NEXT:    s_add_i32 s18, s18, 3
; GFX9-NEXT:    v_mov_b32_e32 v1, s19
; GFX9-NEXT:    v_perm_b32 v0, s16, v0, v9
; GFX9-NEXT:    s_movk_i32 s16, 0x300
; GFX9-NEXT:    v_perm_b32 v1, s18, v1, v9
; GFX9-NEXT:    v_add_u32_e32 v0, 0x300, v0
; GFX9-NEXT:    v_add_u32_sdwa v1, v1, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s20, s20, 3
; GFX9-NEXT:    v_mov_b32_e32 v1, s21
; GFX9-NEXT:    s_add_i32 s22, s22, 3
; GFX9-NEXT:    v_mov_b32_e32 v2, s23
; GFX9-NEXT:    v_perm_b32 v1, s20, v1, v9
; GFX9-NEXT:    v_perm_b32 v2, s22, v2, v9
; GFX9-NEXT:    v_add_u32_e32 v1, 0x300, v1
; GFX9-NEXT:    v_add_u32_sdwa v2, v2, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s24, s24, 3
; GFX9-NEXT:    v_mov_b32_e32 v2, s25
; GFX9-NEXT:    s_add_i32 s26, s26, 3
; GFX9-NEXT:    v_mov_b32_e32 v3, s27
; GFX9-NEXT:    v_perm_b32 v2, s24, v2, v9
; GFX9-NEXT:    v_perm_b32 v3, s26, v3, v9
; GFX9-NEXT:    v_add_u32_e32 v2, 0x300, v2
; GFX9-NEXT:    v_add_u32_sdwa v3, v3, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s28, s28, 3
; GFX9-NEXT:    v_mov_b32_e32 v3, s29
; GFX9-NEXT:    s_add_i32 s61, s61, 3
; GFX9-NEXT:    v_mov_b32_e32 v4, s60
; GFX9-NEXT:    v_perm_b32 v3, s28, v3, v9
; GFX9-NEXT:    v_perm_b32 v4, s61, v4, v9
; GFX9-NEXT:    v_add_u32_e32 v3, 0x300, v3
; GFX9-NEXT:    v_add_u32_sdwa v4, v4, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s59, s59, 3
; GFX9-NEXT:    v_mov_b32_e32 v4, s58
; GFX9-NEXT:    s_add_i32 s57, s57, 3
; GFX9-NEXT:    v_mov_b32_e32 v5, s56
; GFX9-NEXT:    v_perm_b32 v4, s59, v4, v9
; GFX9-NEXT:    v_perm_b32 v5, s57, v5, v9
; GFX9-NEXT:    v_add_u32_e32 v4, 0x300, v4
; GFX9-NEXT:    v_add_u32_sdwa v5, v5, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s47, s47, 3
; GFX9-NEXT:    v_mov_b32_e32 v5, s46
; GFX9-NEXT:    s_add_i32 s45, s45, 3
; GFX9-NEXT:    v_mov_b32_e32 v6, s44
; GFX9-NEXT:    v_perm_b32 v5, s47, v5, v9
; GFX9-NEXT:    v_perm_b32 v6, s45, v6, v9
; GFX9-NEXT:    v_add_u32_e32 v5, 0x300, v5
; GFX9-NEXT:    v_add_u32_sdwa v6, v6, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v5, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s43, s43, 3
; GFX9-NEXT:    v_mov_b32_e32 v6, s42
; GFX9-NEXT:    s_add_i32 s41, s41, 3
; GFX9-NEXT:    v_mov_b32_e32 v7, s40
; GFX9-NEXT:    v_perm_b32 v6, s43, v6, v9
; GFX9-NEXT:    v_perm_b32 v7, s41, v7, v9
; GFX9-NEXT:    v_add_u32_e32 v6, 0x300, v6
; GFX9-NEXT:    v_add_u32_sdwa v7, v7, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v6, v6, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s15, s15, 3
; GFX9-NEXT:    v_mov_b32_e32 v7, s14
; GFX9-NEXT:    s_add_i32 s13, s13, 3
; GFX9-NEXT:    v_mov_b32_e32 v8, s12
; GFX9-NEXT:    v_perm_b32 v7, s15, v7, v9
; GFX9-NEXT:    v_perm_b32 v8, s13, v8, v9
; GFX9-NEXT:    v_add_u32_e32 v7, 0x300, v7
; GFX9-NEXT:    v_add_u32_sdwa v8, v8, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s11, s11, 3
; GFX9-NEXT:    v_mov_b32_e32 v8, s10
; GFX9-NEXT:    s_add_i32 s9, s9, 3
; GFX9-NEXT:    v_mov_b32_e32 v10, s8
; GFX9-NEXT:    v_perm_b32 v8, s11, v8, v9
; GFX9-NEXT:    v_perm_b32 v10, s9, v10, v9
; GFX9-NEXT:    v_add_u32_e32 v8, 0x300, v8
; GFX9-NEXT:    v_add_u32_sdwa v10, v10, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v8, v8, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s7, s7, 3
; GFX9-NEXT:    v_mov_b32_e32 v10, s6
; GFX9-NEXT:    s_add_i32 s5, s5, 3
; GFX9-NEXT:    v_mov_b32_e32 v11, s4
; GFX9-NEXT:    v_perm_b32 v10, s7, v10, v9
; GFX9-NEXT:    v_perm_b32 v9, s5, v11, v9
; GFX9-NEXT:    v_add_u32_e32 v10, 0x300, v10
; GFX9-NEXT:    v_add_u32_sdwa v9, v9, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v40i8_to_v10f32_scalar:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s58, v22
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s4, v21
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s5, v20
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s6, v19
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s7, v18
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s9, v17
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s10, v16
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s8, v15
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s11, v14
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s12, v13
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s13, v12
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s14, v11
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s15, v10
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s40, v9
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s41, v8
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s42, v7
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s43, v6
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s44, v5
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s45, v4
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s46, v3
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s47, v2
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s56, v1
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s57, v0
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v5, 0xc0c0004
; GFX11-TRUE16-NEXT:    s_cmp_lg_u32 s58, 0
; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB35_2
; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_perm_b32 v1, s2, s3, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v3, s18, s19, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, s22, s23, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v8, s26, s27, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v10, s57, s56, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v0, s0, s1, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v2, s16, s17, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v4, s20, s21, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, s24, s25, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v9, s28, s29, v5
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v1
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v2, v3
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v4, v6
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, s45, s44, v5
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v7, v8
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v9, v10
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, s41, s40, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v10, s13, s12, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v11, s10, s9, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v13, s5, s4, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v8, s47, s46, v5
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; GFX11-TRUE16-NEXT:    v_perm_b32 v9, s43, s42, v5
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; GFX11-TRUE16-NEXT:    v_perm_b32 v12, s15, s14, v5
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT:    v_perm_b32 v14, s11, s8, v5
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; GFX11-TRUE16-NEXT:    v_perm_b32 v15, s7, s6, v5
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v8, v6
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v9, v7
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v12, v10
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v14, v11
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v15, v13
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT:  .LBB35_2: ; %cmp.true
; GFX11-TRUE16-NEXT:    s_add_i32 s0, s0, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s16, s16, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s18, s18, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s20, s20, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s22, s22, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s24, s24, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s26, s26, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s28, s28, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s57, s57, 3
; GFX11-TRUE16-NEXT:    v_perm_b32 v0, s0, s1, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v1, s2, s3, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v2, s16, s17, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v3, s18, s19, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v4, s20, s21, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, s22, s23, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, s24, s25, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v8, s26, s27, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v9, s28, s29, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v10, s57, s56, v5
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v4, 0x300, v4
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v6, 0x300, v6
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v8, 0x300, v8
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v9, 0x300, v9
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v10, 0x300, v10
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT:    s_add_i32 s47, s47, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s45, s45, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s43, s43, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s41, s41, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s15, s15, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s13, s13, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s11, s11, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s10, s10, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s7, s7, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s5, s5, 3
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v1
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v2, v3
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v4, v6
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v7, v8
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v9, v10
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, s47, s46, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, s45, s44, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v8, s43, s42, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v9, s41, s40, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v10, s15, s14, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v11, s13, s12, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v12, s11, s8, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v13, s10, s9, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v14, s7, s6, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v5, s5, s4, v5
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v6, 0x300, v6
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v8, 0x300, v8
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v9, 0x300, v9
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v10, 0x300, v10
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v11, 0x300, v11
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v13, 0x300, v13
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v14, 0x300, v14
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v5
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v6, v7
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v8, v9
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v10, v11
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v12, v13
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v14, v15
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v40i8_to_v10f32_scalar:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s58, v22
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s5, v21
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s6, v20
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s4, v19
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s7, v18
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s9, v17
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s11, v16
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s8, v15
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s10, v14
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s12, v13
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s13, v12
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s14, v11
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s15, v10
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s40, v9
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s42, v8
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s41, v7
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s43, v6
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s45, v5
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s46, v4
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s44, v3
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s47, v2
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s56, v1
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s57, v0
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, 0xc0c0004
; GFX11-FAKE16-NEXT:    s_cmp_lg_u32 s58, 0
; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB35_2
; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_perm_b32 v1, s2, s3, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v3, s18, s19, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, s22, s23, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, s26, s27, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v10, s57, s56, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v0, s0, s1, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v2, s16, s17, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v4, s20, s21, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, s24, s25, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, s28, s29, v5
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v6
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, s46, s45, v5
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v7, v8
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v9, v10
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, s42, s40, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v10, s13, s12, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v11, s11, s9, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v13, s6, s5, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, s47, s44, v5
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, s43, s41, v5
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; GFX11-FAKE16-NEXT:    v_perm_b32 v12, s15, s14, v5
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; GFX11-FAKE16-NEXT:    v_perm_b32 v14, s10, s8, v5
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; GFX11-FAKE16-NEXT:    v_perm_b32 v15, s7, s4, v5
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v8, v6
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v9, v7
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v12, v10
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v14, v11
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v15, v13
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT:  .LBB35_2: ; %cmp.true
; GFX11-FAKE16-NEXT:    s_add_i32 s0, s0, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s2, s2, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s16, s16, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s18, s18, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s20, s20, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s22, s22, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s24, s24, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s26, s26, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s28, s28, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s57, s57, 3
; GFX11-FAKE16-NEXT:    v_perm_b32 v0, s0, s1, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v1, s2, s3, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v2, s16, s17, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v3, s18, s19, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v4, s20, s21, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, s22, s23, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, s24, s25, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, s26, s27, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, s28, s29, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v10, s57, s56, v5
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, 0x300, v4
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v6, 0x300, v6
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v8, 0x300, v8
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v9, 0x300, v9
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v10, 0x300, v10
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; GFX11-FAKE16-NEXT:    s_add_i32 s47, s47, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s46, s46, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s43, s43, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s42, s42, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s15, s15, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s13, s13, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s10, s10, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s11, s11, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s7, s7, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s6, s6, 3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v6
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v7, v8
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v9, v10
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, s47, s44, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, s46, s45, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, s43, s41, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, s42, s40, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v10, s15, s14, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v11, s13, s12, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v12, s10, s8, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v13, s11, s9, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v14, s7, s4, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v5, s6, s5, v5
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v6, 0x300, v6
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v8, 0x300, v8
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v9, 0x300, v9
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v10, 0x300, v10
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v11, 0x300, v11
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v13, 0x300, v13
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v14, 0x300, v14
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v5
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v6, v7
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v8, v9
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v10, v11
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v12, v13
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v14, v15
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <40 x i8> %a, splat (i8 3)
  %a2 = bitcast <40 x i8> %a1 to <10 x float>
  br label %end

cmp.false:
  %a3 = bitcast <40 x i8> %a to <10 x float>
  br label %end

end:
  %phi = phi <10 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <10 x float> %phi
}

define <5 x double> @bitcast_v10f32_to_v5f64(<10 x float> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v10f32_to_v5f64:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB36_2
; SI-NEXT:  ; %bb.1: ; %cmp.true
; SI-NEXT:    v_add_f32_e32 v9, 1.0, v9
; SI-NEXT:    v_add_f32_e32 v8, 1.0, v8
; SI-NEXT:    v_add_f32_e32 v7, 1.0, v7
; SI-NEXT:    v_add_f32_e32 v6, 1.0, v6
; SI-NEXT:    v_add_f32_e32 v5, 1.0, v5
; SI-NEXT:    v_add_f32_e32 v4, 1.0, v4
; SI-NEXT:    v_add_f32_e32 v3, 1.0, v3
; SI-NEXT:    v_add_f32_e32 v2, 1.0, v2
; SI-NEXT:    v_add_f32_e32 v1, 1.0, v1
; SI-NEXT:    v_add_f32_e32 v0, 1.0, v0
; SI-NEXT:  .LBB36_2: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v10f32_to_v5f64:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB36_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    v_add_f32_e32 v9, 1.0, v9
; VI-NEXT:    v_add_f32_e32 v8, 1.0, v8
; VI-NEXT:    v_add_f32_e32 v7, 1.0, v7
; VI-NEXT:    v_add_f32_e32 v6, 1.0, v6
; VI-NEXT:    v_add_f32_e32 v5, 1.0, v5
; VI-NEXT:    v_add_f32_e32 v4, 1.0, v4
; VI-NEXT:    v_add_f32_e32 v3, 1.0, v3
; VI-NEXT:    v_add_f32_e32 v2, 1.0, v2
; VI-NEXT:    v_add_f32_e32 v1, 1.0, v1
; VI-NEXT:    v_add_f32_e32 v0, 1.0, v0
; VI-NEXT:  .LBB36_2: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v10f32_to_v5f64:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB36_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    v_add_f32_e32 v9, 1.0, v9
; GFX9-NEXT:    v_add_f32_e32 v8, 1.0, v8
; GFX9-NEXT:    v_add_f32_e32 v7, 1.0, v7
; GFX9-NEXT:    v_add_f32_e32 v6, 1.0, v6
; GFX9-NEXT:    v_add_f32_e32 v5, 1.0, v5
; GFX9-NEXT:    v_add_f32_e32 v4, 1.0, v4
; GFX9-NEXT:    v_add_f32_e32 v3, 1.0, v3
; GFX9-NEXT:    v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT:    v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT:    v_add_f32_e32 v0, 1.0, v0
; GFX9-NEXT:  .LBB36_2: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v10f32_to_v5f64:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8
; GFX11-NEXT:    v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
; GFX11-NEXT:    v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT:    v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT:    v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
; GFX11-NEXT:  ; %bb.2: ; %end
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <10 x float> %a, splat (float 1.000000e+00)
  %a2 = bitcast <10 x float> %a1 to <5 x double>
  br label %end

cmp.false:
  %a3 = bitcast <10 x float> %a to <5 x double>
  br label %end

end:
  %phi = phi <5 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <5 x double> %phi
}

define inreg <5 x double> @bitcast_v10f32_to_v5f64_scalar(<10 x float> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v10f32_to_v5f64_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc0 .LBB37_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    v_mov_b32_e32 v0, s16
; SI-NEXT:    v_mov_b32_e32 v1, s17
; SI-NEXT:    v_mov_b32_e32 v2, s18
; SI-NEXT:    v_mov_b32_e32 v3, s19
; SI-NEXT:    v_mov_b32_e32 v4, s20
; SI-NEXT:    v_mov_b32_e32 v5, s21
; SI-NEXT:    v_mov_b32_e32 v6, s22
; SI-NEXT:    v_mov_b32_e32 v7, s23
; SI-NEXT:    v_mov_b32_e32 v8, s24
; SI-NEXT:    v_mov_b32_e32 v9, s25
; SI-NEXT:    v_mov_b32_e32 v10, s26
; SI-NEXT:    v_mov_b32_e32 v11, s27
; SI-NEXT:    v_mov_b32_e32 v12, s28
; SI-NEXT:    v_mov_b32_e32 v13, s29
; SI-NEXT:    v_mov_b32_e32 v14, s30
; SI-NEXT:    v_mov_b32_e32 v15, s31
; SI-NEXT:    s_setpc_b64 s[30:31]
; SI-NEXT:  .LBB37_2: ; %cmp.true
; SI-NEXT:    v_add_f32_e64 v9, s25, 1.0
; SI-NEXT:    v_add_f32_e64 v8, s24, 1.0
; SI-NEXT:    v_add_f32_e64 v7, s23, 1.0
; SI-NEXT:    v_add_f32_e64 v6, s22, 1.0
; SI-NEXT:    v_add_f32_e64 v5, s21, 1.0
; SI-NEXT:    v_add_f32_e64 v4, s20, 1.0
; SI-NEXT:    v_add_f32_e64 v3, s19, 1.0
; SI-NEXT:    v_add_f32_e64 v2, s18, 1.0
; SI-NEXT:    v_add_f32_e64 v1, s17, 1.0
; SI-NEXT:    v_add_f32_e64 v0, s16, 1.0
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v10f32_to_v5f64_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc0 .LBB37_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s17
; VI-NEXT:    v_mov_b32_e32 v2, s18
; VI-NEXT:    v_mov_b32_e32 v3, s19
; VI-NEXT:    v_mov_b32_e32 v4, s20
; VI-NEXT:    v_mov_b32_e32 v5, s21
; VI-NEXT:    v_mov_b32_e32 v6, s22
; VI-NEXT:    v_mov_b32_e32 v7, s23
; VI-NEXT:    v_mov_b32_e32 v8, s24
; VI-NEXT:    v_mov_b32_e32 v9, s25
; VI-NEXT:    v_mov_b32_e32 v10, s26
; VI-NEXT:    v_mov_b32_e32 v11, s27
; VI-NEXT:    v_mov_b32_e32 v12, s28
; VI-NEXT:    v_mov_b32_e32 v13, s29
; VI-NEXT:    v_mov_b32_e32 v14, s30
; VI-NEXT:    v_mov_b32_e32 v15, s31
; VI-NEXT:    s_setpc_b64 s[30:31]
; VI-NEXT:  .LBB37_2: ; %cmp.true
; VI-NEXT:    v_add_f32_e64 v9, s25, 1.0
; VI-NEXT:    v_add_f32_e64 v8, s24, 1.0
; VI-NEXT:    v_add_f32_e64 v7, s23, 1.0
; VI-NEXT:    v_add_f32_e64 v6, s22, 1.0
; VI-NEXT:    v_add_f32_e64 v5, s21, 1.0
; VI-NEXT:    v_add_f32_e64 v4, s20, 1.0
; VI-NEXT:    v_add_f32_e64 v3, s19, 1.0
; VI-NEXT:    v_add_f32_e64 v2, s18, 1.0
; VI-NEXT:    v_add_f32_e64 v1, s17, 1.0
; VI-NEXT:    v_add_f32_e64 v0, s16, 1.0
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v10f32_to_v5f64_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc0 .LBB37_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s17
; GFX9-NEXT:    v_mov_b32_e32 v2, s18
; GFX9-NEXT:    v_mov_b32_e32 v3, s19
; GFX9-NEXT:    v_mov_b32_e32 v4, s20
; GFX9-NEXT:    v_mov_b32_e32 v5, s21
; GFX9-NEXT:    v_mov_b32_e32 v6, s22
; GFX9-NEXT:    v_mov_b32_e32 v7, s23
; GFX9-NEXT:    v_mov_b32_e32 v8, s24
; GFX9-NEXT:    v_mov_b32_e32 v9, s25
; GFX9-NEXT:    v_mov_b32_e32 v10, s26
; GFX9-NEXT:    v_mov_b32_e32 v11, s27
; GFX9-NEXT:    v_mov_b32_e32 v12, s28
; GFX9-NEXT:    v_mov_b32_e32 v13, s29
; GFX9-NEXT:    v_mov_b32_e32 v14, s30
; GFX9-NEXT:    v_mov_b32_e32 v15, s31
; GFX9-NEXT:    s_setpc_b64 s[30:31]
; GFX9-NEXT:  .LBB37_2: ; %cmp.true
; GFX9-NEXT:    v_add_f32_e64 v9, s25, 1.0
; GFX9-NEXT:    v_add_f32_e64 v8, s24, 1.0
; GFX9-NEXT:    v_add_f32_e64 v7, s23, 1.0
; GFX9-NEXT:    v_add_f32_e64 v6, s22, 1.0
; GFX9-NEXT:    v_add_f32_e64 v5, s21, 1.0
; GFX9-NEXT:    v_add_f32_e64 v4, s20, 1.0
; GFX9-NEXT:    v_add_f32_e64 v3, s19, 1.0
; GFX9-NEXT:    v_add_f32_e64 v2, s18, 1.0
; GFX9-NEXT:    v_add_f32_e64 v1, s17, 1.0
; GFX9-NEXT:    v_add_f32_e64 v0, s16, 1.0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v10f32_to_v5f64_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s15, s3
; GFX11-NEXT:    s_mov_b32 s14, s2
; GFX11-NEXT:    s_mov_b32 s13, s1
; GFX11-NEXT:    s_mov_b32 s12, s0
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc0 .LBB37_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-NEXT:    v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
; GFX11-NEXT:    v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT:    v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
; GFX11-NEXT:    v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
; GFX11-NEXT:    v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
; GFX11-NEXT:    s_setpc_b64 s[30:31]
; GFX11-NEXT:  .LBB37_2: ; %cmp.true
; GFX11-NEXT:    v_add_f32_e64 v9, s21, 1.0
; GFX11-NEXT:    v_add_f32_e64 v8, s20, 1.0
; GFX11-NEXT:    v_add_f32_e64 v7, s19, 1.0
; GFX11-NEXT:    v_add_f32_e64 v6, s18, 1.0
; GFX11-NEXT:    v_add_f32_e64 v5, s17, 1.0
; GFX11-NEXT:    v_add_f32_e64 v4, s16, 1.0
; GFX11-NEXT:    v_add_f32_e64 v3, s15, 1.0
; GFX11-NEXT:    v_add_f32_e64 v2, s14, 1.0
; GFX11-NEXT:    v_add_f32_e64 v1, s13, 1.0
; GFX11-NEXT:    v_add_f32_e64 v0, s12, 1.0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <10 x float> %a, splat (float 1.000000e+00)
  %a2 = bitcast <10 x float> %a1 to <5 x double>
  br label %end

cmp.false:
  %a3 = bitcast <10 x float> %a to <5 x double>
  br label %end

end:
  %phi = phi <5 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <5 x double> %phi
}

define <10 x float> @bitcast_v5f64_to_v10f32(<5 x double> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v5f64_to_v10f32:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB38_2
; SI-NEXT:  ; %bb.1: ; %cmp.true
; SI-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
; SI-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
; SI-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
; SI-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
; SI-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
; SI-NEXT:  .LBB38_2: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v5f64_to_v10f32:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB38_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
; VI-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
; VI-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
; VI-NEXT:  .LBB38_2: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v5f64_to_v10f32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB38_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
; GFX9-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
; GFX9-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
; GFX9-NEXT:  .LBB38_2: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v5f64_to_v10f32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB38_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
; GFX11-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
; GFX11-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
; GFX11-NEXT:  .LBB38_2: ; %end
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <5 x double> %a, splat (double 1.000000e+00)
  %a2 = bitcast <5 x double> %a1 to <10 x float>
  br label %end

cmp.false:
  %a3 = bitcast <5 x double> %a to <10 x float>
  br label %end

end:
  %phi = phi <10 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <10 x float> %phi
}

define inreg <10 x float> @bitcast_v5f64_to_v10f32_scalar(<5 x double> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v5f64_to_v10f32_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc0 .LBB39_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    v_mov_b32_e32 v0, s16
; SI-NEXT:    v_mov_b32_e32 v1, s17
; SI-NEXT:    v_mov_b32_e32 v2, s18
; SI-NEXT:    v_mov_b32_e32 v3, s19
; SI-NEXT:    v_mov_b32_e32 v4, s20
; SI-NEXT:    v_mov_b32_e32 v5, s21
; SI-NEXT:    v_mov_b32_e32 v6, s22
; SI-NEXT:    v_mov_b32_e32 v7, s23
; SI-NEXT:    v_mov_b32_e32 v8, s24
; SI-NEXT:    v_mov_b32_e32 v9, s25
; SI-NEXT:    s_setpc_b64 s[30:31]
; SI-NEXT:  .LBB39_2: ; %cmp.true
; SI-NEXT:    v_add_f64 v[8:9], s[24:25], 1.0
; SI-NEXT:    v_add_f64 v[6:7], s[22:23], 1.0
; SI-NEXT:    v_add_f64 v[4:5], s[20:21], 1.0
; SI-NEXT:    v_add_f64 v[2:3], s[18:19], 1.0
; SI-NEXT:    v_add_f64 v[0:1], s[16:17], 1.0
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v5f64_to_v10f32_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc0 .LBB39_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s17
; VI-NEXT:    v_mov_b32_e32 v2, s18
; VI-NEXT:    v_mov_b32_e32 v3, s19
; VI-NEXT:    v_mov_b32_e32 v4, s20
; VI-NEXT:    v_mov_b32_e32 v5, s21
; VI-NEXT:    v_mov_b32_e32 v6, s22
; VI-NEXT:    v_mov_b32_e32 v7, s23
; VI-NEXT:    v_mov_b32_e32 v8, s24
; VI-NEXT:    v_mov_b32_e32 v9, s25
; VI-NEXT:    s_setpc_b64 s[30:31]
; VI-NEXT:  .LBB39_2: ; %cmp.true
; VI-NEXT:    v_add_f64 v[8:9], s[24:25], 1.0
; VI-NEXT:    v_add_f64 v[6:7], s[22:23], 1.0
; VI-NEXT:    v_add_f64 v[4:5], s[20:21], 1.0
; VI-NEXT:    v_add_f64 v[2:3], s[18:19], 1.0
; VI-NEXT:    v_add_f64 v[0:1], s[16:17], 1.0
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v5f64_to_v10f32_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc0 .LBB39_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s17
; GFX9-NEXT:    v_mov_b32_e32 v2, s18
; GFX9-NEXT:    v_mov_b32_e32 v3, s19
; GFX9-NEXT:    v_mov_b32_e32 v4, s20
; GFX9-NEXT:    v_mov_b32_e32 v5, s21
; GFX9-NEXT:    v_mov_b32_e32 v6, s22
; GFX9-NEXT:    v_mov_b32_e32 v7, s23
; GFX9-NEXT:    v_mov_b32_e32 v8, s24
; GFX9-NEXT:    v_mov_b32_e32 v9, s25
; GFX9-NEXT:    s_setpc_b64 s[30:31]
; GFX9-NEXT:  .LBB39_2: ; %cmp.true
; GFX9-NEXT:    v_add_f64 v[8:9], s[24:25], 1.0
; GFX9-NEXT:    v_add_f64 v[6:7], s[22:23], 1.0
; GFX9-NEXT:    v_add_f64 v[4:5], s[20:21], 1.0
; GFX9-NEXT:    v_add_f64 v[2:3], s[18:19], 1.0
; GFX9-NEXT:    v_add_f64 v[0:1], s[16:17], 1.0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v5f64_to_v10f32_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s15, s3
; GFX11-NEXT:    s_mov_b32 s14, s2
; GFX11-NEXT:    s_mov_b32 s13, s1
; GFX11-NEXT:    s_mov_b32 s12, s0
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc0 .LBB39_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-NEXT:    v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
; GFX11-NEXT:    v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT:    s_setpc_b64 s[30:31]
; GFX11-NEXT:  .LBB39_2: ; %cmp.true
; GFX11-NEXT:    v_add_f64 v[8:9], s[20:21], 1.0
; GFX11-NEXT:    v_add_f64 v[6:7], s[18:19], 1.0
; GFX11-NEXT:    v_add_f64 v[4:5], s[16:17], 1.0
; GFX11-NEXT:    v_add_f64 v[2:3], s[14:15], 1.0
; GFX11-NEXT:    v_add_f64 v[0:1], s[12:13], 1.0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <5 x double> %a, splat (double 1.000000e+00)
  %a2 = bitcast <5 x double> %a1 to <10 x float>
  br label %end

cmp.false:
  %a3 = bitcast <5 x double> %a to <10 x float>
  br label %end

end:
  %phi = phi <10 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <10 x float> %phi
}

define <5 x i64> @bitcast_v10f32_to_v5i64(<10 x float> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v10f32_to_v5i64:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB40_2
; SI-NEXT:  ; %bb.1: ; %cmp.true
; SI-NEXT:    v_add_f32_e32 v9, 1.0, v9
; SI-NEXT:    v_add_f32_e32 v8, 1.0, v8
; SI-NEXT:    v_add_f32_e32 v7, 1.0, v7
; SI-NEXT:    v_add_f32_e32 v6, 1.0, v6
; SI-NEXT:    v_add_f32_e32 v5, 1.0, v5
; SI-NEXT:    v_add_f32_e32 v4, 1.0, v4
; SI-NEXT:    v_add_f32_e32 v3, 1.0, v3
; SI-NEXT:    v_add_f32_e32 v2, 1.0, v2
; SI-NEXT:    v_add_f32_e32 v1, 1.0, v1
; SI-NEXT:    v_add_f32_e32 v0, 1.0, v0
; SI-NEXT:  .LBB40_2: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v10f32_to_v5i64:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB40_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    v_add_f32_e32 v9, 1.0, v9
; VI-NEXT:    v_add_f32_e32 v8, 1.0, v8
; VI-NEXT:    v_add_f32_e32 v7, 1.0, v7
; VI-NEXT:    v_add_f32_e32 v6, 1.0, v6
; VI-NEXT:    v_add_f32_e32 v5, 1.0, v5
; VI-NEXT:    v_add_f32_e32 v4, 1.0, v4
; VI-NEXT:    v_add_f32_e32 v3, 1.0, v3
; VI-NEXT:    v_add_f32_e32 v2, 1.0, v2
; VI-NEXT:    v_add_f32_e32 v1, 1.0, v1
; VI-NEXT:    v_add_f32_e32 v0, 1.0, v0
; VI-NEXT:  .LBB40_2: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v10f32_to_v5i64:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB40_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    v_add_f32_e32 v9, 1.0, v9
; GFX9-NEXT:    v_add_f32_e32 v8, 1.0, v8
; GFX9-NEXT:    v_add_f32_e32 v7, 1.0, v7
; GFX9-NEXT:    v_add_f32_e32 v6, 1.0, v6
; GFX9-NEXT:    v_add_f32_e32 v5, 1.0, v5
; GFX9-NEXT:    v_add_f32_e32 v4, 1.0, v4
; GFX9-NEXT:    v_add_f32_e32 v3, 1.0, v3
; GFX9-NEXT:    v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT:    v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT:    v_add_f32_e32 v0, 1.0, v0
; GFX9-NEXT:  .LBB40_2: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v10f32_to_v5i64:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8
; GFX11-NEXT:    v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
; GFX11-NEXT:    v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT:    v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT:    v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
; GFX11-NEXT:  ; %bb.2: ; %end
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <10 x float> %a, splat (float 1.000000e+00)
  %a2 = bitcast <10 x float> %a1 to <5 x i64>
  br label %end

cmp.false:
  %a3 = bitcast <10 x float> %a to <5 x i64>
  br label %end

end:
  %phi = phi <5 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <5 x i64> %phi
}

define inreg <5 x i64> @bitcast_v10f32_to_v5i64_scalar(<10 x float> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v10f32_to_v5i64_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc0 .LBB41_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    v_mov_b32_e32 v0, s16
; SI-NEXT:    v_mov_b32_e32 v1, s17
; SI-NEXT:    v_mov_b32_e32 v2, s18
; SI-NEXT:    v_mov_b32_e32 v3, s19
; SI-NEXT:    v_mov_b32_e32 v4, s20
; SI-NEXT:    v_mov_b32_e32 v5, s21
; SI-NEXT:    v_mov_b32_e32 v6, s22
; SI-NEXT:    v_mov_b32_e32 v7, s23
; SI-NEXT:    v_mov_b32_e32 v8, s24
; SI-NEXT:    v_mov_b32_e32 v9, s25
; SI-NEXT:    v_mov_b32_e32 v10, s26
; SI-NEXT:    v_mov_b32_e32 v11, s27
; SI-NEXT:    v_mov_b32_e32 v12, s28
; SI-NEXT:    v_mov_b32_e32 v13, s29
; SI-NEXT:    v_mov_b32_e32 v14, s30
; SI-NEXT:    v_mov_b32_e32 v15, s31
; SI-NEXT:    s_setpc_b64 s[30:31]
; SI-NEXT:  .LBB41_2: ; %cmp.true
; SI-NEXT:    v_add_f32_e64 v9, s25, 1.0
; SI-NEXT:    v_add_f32_e64 v8, s24, 1.0
; SI-NEXT:    v_add_f32_e64 v7, s23, 1.0
; SI-NEXT:    v_add_f32_e64 v6, s22, 1.0
; SI-NEXT:    v_add_f32_e64 v5, s21, 1.0
; SI-NEXT:    v_add_f32_e64 v4, s20, 1.0
; SI-NEXT:    v_add_f32_e64 v3, s19, 1.0
; SI-NEXT:    v_add_f32_e64 v2, s18, 1.0
; SI-NEXT:    v_add_f32_e64 v1, s17, 1.0
; SI-NEXT:    v_add_f32_e64 v0, s16, 1.0
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v10f32_to_v5i64_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc0 .LBB41_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s17
; VI-NEXT:    v_mov_b32_e32 v2, s18
; VI-NEXT:    v_mov_b32_e32 v3, s19
; VI-NEXT:    v_mov_b32_e32 v4, s20
; VI-NEXT:    v_mov_b32_e32 v5, s21
; VI-NEXT:    v_mov_b32_e32 v6, s22
; VI-NEXT:    v_mov_b32_e32 v7, s23
; VI-NEXT:    v_mov_b32_e32 v8, s24
; VI-NEXT:    v_mov_b32_e32 v9, s25
; VI-NEXT:    v_mov_b32_e32 v10, s26
; VI-NEXT:    v_mov_b32_e32 v11, s27
; VI-NEXT:    v_mov_b32_e32 v12, s28
; VI-NEXT:    v_mov_b32_e32 v13, s29
; VI-NEXT:    v_mov_b32_e32 v14, s30
; VI-NEXT:    v_mov_b32_e32 v15, s31
; VI-NEXT:    s_setpc_b64 s[30:31]
; VI-NEXT:  .LBB41_2: ; %cmp.true
; VI-NEXT:    v_add_f32_e64 v9, s25, 1.0
; VI-NEXT:    v_add_f32_e64 v8, s24, 1.0
; VI-NEXT:    v_add_f32_e64 v7, s23, 1.0
; VI-NEXT:    v_add_f32_e64 v6, s22, 1.0
; VI-NEXT:    v_add_f32_e64 v5, s21, 1.0
; VI-NEXT:    v_add_f32_e64 v4, s20, 1.0
; VI-NEXT:    v_add_f32_e64 v3, s19, 1.0
; VI-NEXT:    v_add_f32_e64 v2, s18, 1.0
; VI-NEXT:    v_add_f32_e64 v1, s17, 1.0
; VI-NEXT:    v_add_f32_e64 v0, s16, 1.0
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v10f32_to_v5i64_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc0 .LBB41_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s17
; GFX9-NEXT:    v_mov_b32_e32 v2, s18
; GFX9-NEXT:    v_mov_b32_e32 v3, s19
; GFX9-NEXT:    v_mov_b32_e32 v4, s20
; GFX9-NEXT:    v_mov_b32_e32 v5, s21
; GFX9-NEXT:    v_mov_b32_e32 v6, s22
; GFX9-NEXT:    v_mov_b32_e32 v7, s23
; GFX9-NEXT:    v_mov_b32_e32 v8, s24
; GFX9-NEXT:    v_mov_b32_e32 v9, s25
; GFX9-NEXT:    v_mov_b32_e32 v10, s26
; GFX9-NEXT:    v_mov_b32_e32 v11, s27
; GFX9-NEXT:    v_mov_b32_e32 v12, s28
; GFX9-NEXT:    v_mov_b32_e32 v13, s29
; GFX9-NEXT:    v_mov_b32_e32 v14, s30
; GFX9-NEXT:    v_mov_b32_e32 v15, s31
; GFX9-NEXT:    s_setpc_b64 s[30:31]
; GFX9-NEXT:  .LBB41_2: ; %cmp.true
; GFX9-NEXT:    v_add_f32_e64 v9, s25, 1.0
; GFX9-NEXT:    v_add_f32_e64 v8, s24, 1.0
; GFX9-NEXT:    v_add_f32_e64 v7, s23, 1.0
; GFX9-NEXT:    v_add_f32_e64 v6, s22, 1.0
; GFX9-NEXT:    v_add_f32_e64 v5, s21, 1.0
; GFX9-NEXT:    v_add_f32_e64 v4, s20, 1.0
; GFX9-NEXT:    v_add_f32_e64 v3, s19, 1.0
; GFX9-NEXT:    v_add_f32_e64 v2, s18, 1.0
; GFX9-NEXT:    v_add_f32_e64 v1, s17, 1.0
; GFX9-NEXT:    v_add_f32_e64 v0, s16, 1.0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v10f32_to_v5i64_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s15, s3
; GFX11-NEXT:    s_mov_b32 s14, s2
; GFX11-NEXT:    s_mov_b32 s13, s1
; GFX11-NEXT:    s_mov_b32 s12, s0
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc0 .LBB41_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-NEXT:    v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
; GFX11-NEXT:    v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT:    v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
; GFX11-NEXT:    v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
; GFX11-NEXT:    v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
; GFX11-NEXT:    s_setpc_b64 s[30:31]
; GFX11-NEXT:  .LBB41_2: ; %cmp.true
; GFX11-NEXT:    v_add_f32_e64 v9, s21, 1.0
; GFX11-NEXT:    v_add_f32_e64 v8, s20, 1.0
; GFX11-NEXT:    v_add_f32_e64 v7, s19, 1.0
; GFX11-NEXT:    v_add_f32_e64 v6, s18, 1.0
; GFX11-NEXT:    v_add_f32_e64 v5, s17, 1.0
; GFX11-NEXT:    v_add_f32_e64 v4, s16, 1.0
; GFX11-NEXT:    v_add_f32_e64 v3, s15, 1.0
; GFX11-NEXT:    v_add_f32_e64 v2, s14, 1.0
; GFX11-NEXT:    v_add_f32_e64 v1, s13, 1.0
; GFX11-NEXT:    v_add_f32_e64 v0, s12, 1.0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <10 x float> %a, splat (float 1.000000e+00)
  %a2 = bitcast <10 x float> %a1 to <5 x i64>
  br label %end

cmp.false:
  %a3 = bitcast <10 x float> %a to <5 x i64>
  br label %end

end:
  %phi = phi <5 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <5 x i64> %phi
}

define <10 x float> @bitcast_v5i64_to_v10f32(<5 x i64> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v5i64_to_v10f32:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB42_2
; SI-NEXT:  ; %bb.1: ; %cmp.true
; SI-NEXT:    v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
; SI-NEXT:    v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
; SI-NEXT:  .LBB42_2: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v5i64_to_v10f32:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB42_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    v_add_u32_e32 v8, vcc, 3, v8
; VI-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
; VI-NEXT:    v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
; VI-NEXT:    v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT:    v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT:  .LBB42_2: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v5i64_to_v10f32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB42_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, 3, v8
; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v9, vcc
; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, 3, v6
; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, 3, v4
; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, 3, v2
; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT:  .LBB42_2: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v5i64_to_v10f32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB42_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    v_add_co_u32 v8, vcc_lo, v8, 3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo
; GFX11-NEXT:    v_add_co_u32 v6, vcc_lo, v6, 3
; GFX11-NEXT:    v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo
; GFX11-NEXT:    v_add_co_u32 v4, vcc_lo, v4, 3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
; GFX11-NEXT:    v_add_co_u32 v2, vcc_lo, v2, 3
; GFX11-NEXT:    v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX11-NEXT:  .LBB42_2: ; %end
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <5 x i64> %a, splat (i64 3)
  %a2 = bitcast <5 x i64> %a1 to <10 x float>
  br label %end

cmp.false:
  %a3 = bitcast <5 x i64> %a to <10 x float>
  br label %end

end:
  %phi = phi <10 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <10 x float> %phi
}

define inreg <10 x float> @bitcast_v5i64_to_v10f32_scalar(<5 x i64> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v5i64_to_v10f32_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc1 .LBB43_2
; SI-NEXT:  ; %bb.1: ; %cmp.true
; SI-NEXT:    s_add_u32 s24, s24, 3
; SI-NEXT:    s_addc_u32 s25, s25, 0
; SI-NEXT:    s_add_u32 s22, s22, 3
; SI-NEXT:    s_addc_u32 s23, s23, 0
; SI-NEXT:    s_add_u32 s20, s20, 3
; SI-NEXT:    s_addc_u32 s21, s21, 0
; SI-NEXT:    s_add_u32 s18, s18, 3
; SI-NEXT:    s_addc_u32 s19, s19, 0
; SI-NEXT:    s_add_u32 s16, s16, 3
; SI-NEXT:    s_addc_u32 s17, s17, 0
; SI-NEXT:  .LBB43_2: ; %end
; SI-NEXT:    v_mov_b32_e32 v0, s16
; SI-NEXT:    v_mov_b32_e32 v1, s17
; SI-NEXT:    v_mov_b32_e32 v2, s18
; SI-NEXT:    v_mov_b32_e32 v3, s19
; SI-NEXT:    v_mov_b32_e32 v4, s20
; SI-NEXT:    v_mov_b32_e32 v5, s21
; SI-NEXT:    v_mov_b32_e32 v6, s22
; SI-NEXT:    v_mov_b32_e32 v7, s23
; SI-NEXT:    v_mov_b32_e32 v8, s24
; SI-NEXT:    v_mov_b32_e32 v9, s25
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v5i64_to_v10f32_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc1 .LBB43_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    s_add_u32 s24, s24, 3
; VI-NEXT:    s_addc_u32 s25, s25, 0
; VI-NEXT:    s_add_u32 s22, s22, 3
; VI-NEXT:    s_addc_u32 s23, s23, 0
; VI-NEXT:    s_add_u32 s20, s20, 3
; VI-NEXT:    s_addc_u32 s21, s21, 0
; VI-NEXT:    s_add_u32 s18, s18, 3
; VI-NEXT:    s_addc_u32 s19, s19, 0
; VI-NEXT:    s_add_u32 s16, s16, 3
; VI-NEXT:    s_addc_u32 s17, s17, 0
; VI-NEXT:  .LBB43_2: ; %end
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s17
; VI-NEXT:    v_mov_b32_e32 v2, s18
; VI-NEXT:    v_mov_b32_e32 v3, s19
; VI-NEXT:    v_mov_b32_e32 v4, s20
; VI-NEXT:    v_mov_b32_e32 v5, s21
; VI-NEXT:    v_mov_b32_e32 v6, s22
; VI-NEXT:    v_mov_b32_e32 v7, s23
; VI-NEXT:    v_mov_b32_e32 v8, s24
; VI-NEXT:    v_mov_b32_e32 v9, s25
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v5i64_to_v10f32_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc1 .LBB43_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    s_add_u32 s24, s24, 3
; GFX9-NEXT:    s_addc_u32 s25, s25, 0
; GFX9-NEXT:    s_add_u32 s22, s22, 3
; GFX9-NEXT:    s_addc_u32 s23, s23, 0
; GFX9-NEXT:    s_add_u32 s20, s20, 3
; GFX9-NEXT:    s_addc_u32 s21, s21, 0
; GFX9-NEXT:    s_add_u32 s18, s18, 3
; GFX9-NEXT:    s_addc_u32 s19, s19, 0
; GFX9-NEXT:    s_add_u32 s16, s16, 3
; GFX9-NEXT:    s_addc_u32 s17, s17, 0
; GFX9-NEXT:  .LBB43_2: ; %end
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s17
; GFX9-NEXT:    v_mov_b32_e32 v2, s18
; GFX9-NEXT:    v_mov_b32_e32 v3, s19
; GFX9-NEXT:    v_mov_b32_e32 v4, s20
; GFX9-NEXT:    v_mov_b32_e32 v5, s21
; GFX9-NEXT:    v_mov_b32_e32 v6, s22
; GFX9-NEXT:    v_mov_b32_e32 v7, s23
; GFX9-NEXT:    v_mov_b32_e32 v8, s24
; GFX9-NEXT:    v_mov_b32_e32 v9, s25
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v5i64_to_v10f32_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc1 .LBB43_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    s_add_u32 s20, s20, 3
; GFX11-NEXT:    s_addc_u32 s21, s21, 0
; GFX11-NEXT:    s_add_u32 s18, s18, 3
; GFX11-NEXT:    s_addc_u32 s19, s19, 0
; GFX11-NEXT:    s_add_u32 s16, s16, 3
; GFX11-NEXT:    s_addc_u32 s17, s17, 0
; GFX11-NEXT:    s_add_u32 s2, s2, 3
; GFX11-NEXT:    s_addc_u32 s3, s3, 0
; GFX11-NEXT:    s_add_u32 s0, s0, 3
; GFX11-NEXT:    s_addc_u32 s1, s1, 0
; GFX11-NEXT:  .LBB43_2: ; %end
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <5 x i64> %a, splat (i64 3)
  %a2 = bitcast <5 x i64> %a1 to <10 x float>
  br label %end

cmp.false:
  %a3 = bitcast <5 x i64> %a to <10 x float>
  br label %end

end:
  %phi = phi <10 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <10 x float> %phi
}

define <20 x half> @bitcast_v20i16_to_v20f16(<20 x i16> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v20i16_to_v20f16:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_lshrrev_b32_e32 v11, 16, v9
; SI-NEXT:    v_lshrrev_b32_e32 v14, 16, v8
; SI-NEXT:    v_lshrrev_b32_e32 v12, 16, v7
; SI-NEXT:    v_lshrrev_b32_e32 v15, 16, v6
; SI-NEXT:    v_lshrrev_b32_e32 v13, 16, v5
; SI-NEXT:    v_lshrrev_b32_e32 v17, 16, v4
; SI-NEXT:    v_lshrrev_b32_e32 v16, 16, v3
; SI-NEXT:    v_lshrrev_b32_e32 v19, 16, v2
; SI-NEXT:    v_lshrrev_b32_e32 v18, 16, v1
; SI-NEXT:    v_lshrrev_b32_e32 v20, 16, v0
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; SI-NEXT:    v_lshlrev_b32_e32 v31, 16, v18
; SI-NEXT:    v_lshlrev_b32_e32 v30, 16, v20
; SI-NEXT:    v_lshlrev_b32_e32 v33, 16, v16
; SI-NEXT:    v_lshlrev_b32_e32 v32, 16, v19
; SI-NEXT:    v_lshlrev_b32_e32 v35, 16, v13
; SI-NEXT:    v_lshlrev_b32_e32 v34, 16, v17
; SI-NEXT:    v_lshlrev_b32_e32 v37, 16, v12
; SI-NEXT:    v_lshlrev_b32_e32 v36, 16, v15
; SI-NEXT:    v_lshlrev_b32_e32 v39, 16, v11
; SI-NEXT:    v_lshlrev_b32_e32 v38, 16, v14
; SI-NEXT:    ; implicit-def: $vgpr29
; SI-NEXT:    ; implicit-def: $vgpr23
; SI-NEXT:    ; implicit-def: $vgpr22
; SI-NEXT:    ; implicit-def: $vgpr24
; SI-NEXT:    ; implicit-def: $vgpr25
; SI-NEXT:    ; implicit-def: $vgpr20
; SI-NEXT:    ; implicit-def: $vgpr21
; SI-NEXT:    ; implicit-def: $vgpr26
; SI-NEXT:    ; implicit-def: $vgpr17
; SI-NEXT:    ; implicit-def: $vgpr19
; SI-NEXT:    ; implicit-def: $vgpr27
; SI-NEXT:    ; implicit-def: $vgpr14
; SI-NEXT:    ; implicit-def: $vgpr15
; SI-NEXT:    ; implicit-def: $vgpr28
; SI-NEXT:    ; implicit-def: $vgpr10
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB44_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v22, v1, v31
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v3
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_or_b32_e32 v20, v1, v33
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v5
; SI-NEXT:    v_or_b32_e32 v29, v0, v30
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v2
; SI-NEXT:    v_or_b32_e32 v17, v1, v35
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v7
; SI-NEXT:    v_or_b32_e32 v24, v0, v32
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v4
; SI-NEXT:    v_or_b32_e32 v14, v1, v37
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v9
; SI-NEXT:    v_or_b32_e32 v21, v0, v34
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v6
; SI-NEXT:    v_or_b32_e32 v10, v1, v39
; SI-NEXT:    v_or_b32_e32 v19, v0, v36
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v8
; SI-NEXT:    v_alignbit_b32 v23, v22, v30, 16
; SI-NEXT:    v_alignbit_b32 v25, v20, v32, 16
; SI-NEXT:    v_alignbit_b32 v26, v17, v34, 16
; SI-NEXT:    v_alignbit_b32 v27, v14, v36, 16
; SI-NEXT:    v_alignbit_b32 v28, v10, v38, 16
; SI-NEXT:    v_or_b32_e32 v15, v0, v38
; SI-NEXT:    ; implicit-def: $vgpr0
; SI-NEXT:    ; implicit-def: $vgpr1
; SI-NEXT:    ; implicit-def: $vgpr2
; SI-NEXT:    ; implicit-def: $vgpr3
; SI-NEXT:    ; implicit-def: $vgpr4
; SI-NEXT:    ; implicit-def: $vgpr5
; SI-NEXT:    ; implicit-def: $vgpr6
; SI-NEXT:    ; implicit-def: $vgpr7
; SI-NEXT:    ; implicit-def: $vgpr8
; SI-NEXT:    ; implicit-def: $vgpr9
; SI-NEXT:    ; implicit-def: $vgpr31
; SI-NEXT:    ; implicit-def: $vgpr30
; SI-NEXT:    ; implicit-def: $vgpr33
; SI-NEXT:    ; implicit-def: $vgpr32
; SI-NEXT:    ; implicit-def: $vgpr35
; SI-NEXT:    ; implicit-def: $vgpr34
; SI-NEXT:    ; implicit-def: $vgpr37
; SI-NEXT:    ; implicit-def: $vgpr36
; SI-NEXT:    ; implicit-def: $vgpr39
; SI-NEXT:    ; implicit-def: $vgpr38
; SI-NEXT:  .LBB44_2: ; %Flow
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB44_4
; SI-NEXT:  ; %bb.3: ; %cmp.true
; SI-NEXT:    v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT:    v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_or_b32_e32 v8, v38, v8
; SI-NEXT:    v_or_b32_e32 v6, v36, v6
; SI-NEXT:    v_or_b32_e32 v4, v34, v4
; SI-NEXT:    v_or_b32_e32 v2, v32, v2
; SI-NEXT:    v_or_b32_e32 v0, v30, v0
; SI-NEXT:    v_add_i32_e32 v15, vcc, 0x30000, v8
; SI-NEXT:    v_add_i32_e32 v8, vcc, 3, v9
; SI-NEXT:    v_add_i32_e32 v19, vcc, 0x30000, v6
; SI-NEXT:    v_add_i32_e32 v6, vcc, 3, v7
; SI-NEXT:    v_add_i32_e32 v21, vcc, 0x30000, v4
; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v5
; SI-NEXT:    v_add_i32_e32 v24, vcc, 0x30000, v2
; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v3
; SI-NEXT:    v_add_i32_e32 v29, vcc, 0x30000, v0
; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v1
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_or_b32_e32 v8, v39, v8
; SI-NEXT:    v_or_b32_e32 v6, v37, v6
; SI-NEXT:    v_or_b32_e32 v4, v35, v4
; SI-NEXT:    v_or_b32_e32 v2, v33, v2
; SI-NEXT:    v_or_b32_e32 v0, v31, v0
; SI-NEXT:    v_add_i32_e32 v10, vcc, 0x30000, v8
; SI-NEXT:    v_add_i32_e32 v14, vcc, 0x30000, v6
; SI-NEXT:    v_add_i32_e32 v17, vcc, 0x30000, v4
; SI-NEXT:    v_add_i32_e32 v20, vcc, 0x30000, v2
; SI-NEXT:    v_add_i32_e32 v22, vcc, 0x30000, v0
; SI-NEXT:    v_alignbit_b32 v23, v22, v29, 16
; SI-NEXT:    v_alignbit_b32 v25, v20, v24, 16
; SI-NEXT:    v_alignbit_b32 v26, v17, v21, 16
; SI-NEXT:    v_alignbit_b32 v27, v14, v19, 16
; SI-NEXT:    v_alignbit_b32 v28, v10, v15, 16
; SI-NEXT:    v_lshrrev_b32_e32 v18, 16, v22
; SI-NEXT:    v_lshrrev_b32_e32 v16, 16, v20
; SI-NEXT:    v_lshrrev_b32_e32 v13, 16, v17
; SI-NEXT:    v_lshrrev_b32_e32 v12, 16, v14
; SI-NEXT:    v_lshrrev_b32_e32 v11, 16, v10
; SI-NEXT:  .LBB44_4: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v29
; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v23
; SI-NEXT:    v_or_b32_e32 v0, v0, v1
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v22
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v18
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v24
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v25
; SI-NEXT:    v_or_b32_e32 v2, v2, v3
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v20
; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v16
; SI-NEXT:    v_or_b32_e32 v3, v3, v4
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v21
; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v26
; SI-NEXT:    v_or_b32_e32 v4, v4, v5
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v17
; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v13
; SI-NEXT:    v_or_b32_e32 v5, v5, v6
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v19
; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v27
; SI-NEXT:    v_or_b32_e32 v6, v6, v7
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v14
; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v12
; SI-NEXT:    v_or_b32_e32 v7, v7, v8
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v15
; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v28
; SI-NEXT:    v_or_b32_e32 v8, v8, v9
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v10
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v11
; SI-NEXT:    v_or_b32_e32 v9, v9, v10
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v20i16_to_v20f16:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB44_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    v_mov_b32_e32 v10, 3
; VI-NEXT:    v_add_u16_sdwa v11, v0, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_u16_sdwa v12, v1, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_u16_sdwa v13, v2, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_u16_sdwa v14, v3, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_u16_sdwa v15, v4, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_u16_sdwa v16, v5, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_u16_sdwa v17, v6, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_u16_sdwa v18, v7, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_u16_sdwa v19, v8, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_u16_sdwa v10, v9, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_u16_e32 v9, 3, v9
; VI-NEXT:    v_add_u16_e32 v8, 3, v8
; VI-NEXT:    v_add_u16_e32 v7, 3, v7
; VI-NEXT:    v_add_u16_e32 v6, 3, v6
; VI-NEXT:    v_add_u16_e32 v5, 3, v5
; VI-NEXT:    v_add_u16_e32 v4, 3, v4
; VI-NEXT:    v_add_u16_e32 v3, 3, v3
; VI-NEXT:    v_add_u16_e32 v2, 3, v2
; VI-NEXT:    v_add_u16_e32 v1, 3, v1
; VI-NEXT:    v_add_u16_e32 v0, 3, v0
; VI-NEXT:    v_or_b32_e32 v9, v9, v10
; VI-NEXT:    v_or_b32_e32 v8, v8, v19
; VI-NEXT:    v_or_b32_e32 v7, v7, v18
; VI-NEXT:    v_or_b32_e32 v6, v6, v17
; VI-NEXT:    v_or_b32_e32 v5, v5, v16
; VI-NEXT:    v_or_b32_e32 v4, v4, v15
; VI-NEXT:    v_or_b32_e32 v3, v3, v14
; VI-NEXT:    v_or_b32_e32 v2, v2, v13
; VI-NEXT:    v_or_b32_e32 v1, v1, v12
; VI-NEXT:    v_or_b32_e32 v0, v0, v11
; VI-NEXT:  .LBB44_2: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v20i16_to_v20f16:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB44_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX9-NEXT:  .LBB44_2: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v20i16_to_v20f16:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB44_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-NEXT:  .LBB44_2: ; %end
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <20 x i16> %a, splat (i16 3)
  %a2 = bitcast <20 x i16> %a1 to <20 x half>
  br label %end

cmp.false:
  %a3 = bitcast <20 x i16> %a to <20 x half>
  br label %end

end:
  %phi = phi <20 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <20 x half> %phi
}

define inreg <20 x half> @bitcast_v20i16_to_v20f16_scalar(<20 x i16> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v20i16_to_v20f16_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_lshr_b32 s41, s25, 16
; SI-NEXT:    s_lshr_b32 s4, s24, 16
; SI-NEXT:    s_lshr_b32 s40, s23, 16
; SI-NEXT:    s_lshr_b32 s6, s22, 16
; SI-NEXT:    s_lshr_b32 s29, s21, 16
; SI-NEXT:    s_lshr_b32 s8, s20, 16
; SI-NEXT:    s_lshr_b32 s28, s19, 16
; SI-NEXT:    s_lshr_b32 s10, s18, 16
; SI-NEXT:    s_lshr_b32 s27, s17, 16
; SI-NEXT:    s_lshr_b32 s12, s16, 16
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc0 .LBB45_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    s_and_b32 s5, s16, 0xffff
; SI-NEXT:    s_lshl_b32 s42, s12, 16
; SI-NEXT:    s_or_b32 s12, s5, s42
; SI-NEXT:    s_and_b32 s5, s18, 0xffff
; SI-NEXT:    s_lshl_b32 s44, s10, 16
; SI-NEXT:    s_or_b32 s10, s5, s44
; SI-NEXT:    s_and_b32 s5, s20, 0xffff
; SI-NEXT:    s_lshl_b32 s46, s8, 16
; SI-NEXT:    s_or_b32 s8, s5, s46
; SI-NEXT:    s_and_b32 s5, s22, 0xffff
; SI-NEXT:    s_lshl_b32 s56, s6, 16
; SI-NEXT:    s_or_b32 s6, s5, s56
; SI-NEXT:    s_and_b32 s5, s24, 0xffff
; SI-NEXT:    s_lshl_b32 s24, s4, 16
; SI-NEXT:    s_or_b32 s4, s5, s24
; SI-NEXT:    s_and_b32 s5, s17, 0xffff
; SI-NEXT:    s_lshl_b32 s7, s27, 16
; SI-NEXT:    s_or_b32 s43, s5, s7
; SI-NEXT:    s_and_b32 s5, s19, 0xffff
; SI-NEXT:    s_lshl_b32 s7, s28, 16
; SI-NEXT:    s_or_b32 s45, s5, s7
; SI-NEXT:    s_and_b32 s5, s21, 0xffff
; SI-NEXT:    s_lshl_b32 s7, s29, 16
; SI-NEXT:    s_or_b32 s47, s5, s7
; SI-NEXT:    s_and_b32 s5, s23, 0xffff
; SI-NEXT:    s_lshl_b32 s7, s40, 16
; SI-NEXT:    s_or_b32 s57, s5, s7
; SI-NEXT:    s_and_b32 s5, s25, 0xffff
; SI-NEXT:    s_lshl_b32 s7, s41, 16
; SI-NEXT:    s_or_b32 s25, s5, s7
; SI-NEXT:    s_lshr_b64 s[14:15], s[42:43], 16
; SI-NEXT:    s_lshr_b64 s[16:17], s[44:45], 16
; SI-NEXT:    s_lshr_b64 s[18:19], s[46:47], 16
; SI-NEXT:    s_lshr_b64 s[20:21], s[56:57], 16
; SI-NEXT:    s_lshr_b64 s[22:23], s[24:25], 16
; SI-NEXT:    s_mov_b32 s13, s43
; SI-NEXT:    s_mov_b32 s11, s45
; SI-NEXT:    s_mov_b32 s9, s47
; SI-NEXT:    s_mov_b32 s7, s57
; SI-NEXT:    s_mov_b32 s5, s25
; SI-NEXT:    s_branch .LBB45_3
; SI-NEXT:  .LBB45_2: ; %cmp.true
; SI-NEXT:    s_add_i32 s24, s24, 3
; SI-NEXT:    s_and_b32 s5, s24, 0xffff
; SI-NEXT:    s_lshl_b32 s4, s4, 16
; SI-NEXT:    s_add_i32 s25, s25, 3
; SI-NEXT:    s_or_b32 s4, s4, s5
; SI-NEXT:    s_and_b32 s5, s25, 0xffff
; SI-NEXT:    s_lshl_b32 s7, s41, 16
; SI-NEXT:    s_add_i32 s22, s22, 3
; SI-NEXT:    s_or_b32 s5, s7, s5
; SI-NEXT:    s_and_b32 s7, s22, 0xffff
; SI-NEXT:    s_lshl_b32 s6, s6, 16
; SI-NEXT:    s_add_i32 s23, s23, 3
; SI-NEXT:    s_or_b32 s6, s6, s7
; SI-NEXT:    s_and_b32 s7, s23, 0xffff
; SI-NEXT:    s_lshl_b32 s9, s40, 16
; SI-NEXT:    s_add_i32 s20, s20, 3
; SI-NEXT:    s_or_b32 s7, s9, s7
; SI-NEXT:    s_and_b32 s9, s20, 0xffff
; SI-NEXT:    s_lshl_b32 s8, s8, 16
; SI-NEXT:    s_add_i32 s21, s21, 3
; SI-NEXT:    s_or_b32 s8, s8, s9
; SI-NEXT:    s_and_b32 s9, s21, 0xffff
; SI-NEXT:    s_lshl_b32 s11, s29, 16
; SI-NEXT:    s_add_i32 s18, s18, 3
; SI-NEXT:    s_or_b32 s9, s11, s9
; SI-NEXT:    s_and_b32 s11, s18, 0xffff
; SI-NEXT:    s_lshl_b32 s10, s10, 16
; SI-NEXT:    s_add_i32 s19, s19, 3
; SI-NEXT:    s_or_b32 s10, s10, s11
; SI-NEXT:    s_and_b32 s11, s19, 0xffff
; SI-NEXT:    s_lshl_b32 s13, s28, 16
; SI-NEXT:    s_add_i32 s16, s16, 3
; SI-NEXT:    s_or_b32 s11, s13, s11
; SI-NEXT:    s_and_b32 s13, s16, 0xffff
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_add_i32 s17, s17, 3
; SI-NEXT:    s_or_b32 s12, s12, s13
; SI-NEXT:    s_and_b32 s13, s17, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s27, 16
; SI-NEXT:    s_or_b32 s13, s14, s13
; SI-NEXT:    s_add_i32 s4, s4, 0x30000
; SI-NEXT:    s_add_i32 s5, s5, 0x30000
; SI-NEXT:    s_add_i32 s6, s6, 0x30000
; SI-NEXT:    s_add_i32 s7, s7, 0x30000
; SI-NEXT:    s_add_i32 s8, s8, 0x30000
; SI-NEXT:    s_add_i32 s9, s9, 0x30000
; SI-NEXT:    s_add_i32 s10, s10, 0x30000
; SI-NEXT:    s_add_i32 s11, s11, 0x30000
; SI-NEXT:    s_add_i32 s12, s12, 0x30000
; SI-NEXT:    s_add_i32 s13, s13, 0x30000
; SI-NEXT:    s_lshr_b64 s[14:15], s[12:13], 16
; SI-NEXT:    s_lshr_b64 s[16:17], s[10:11], 16
; SI-NEXT:    s_lshr_b64 s[18:19], s[8:9], 16
; SI-NEXT:    s_lshr_b64 s[20:21], s[6:7], 16
; SI-NEXT:    s_lshr_b64 s[22:23], s[4:5], 16
; SI-NEXT:    s_lshr_b32 s27, s13, 16
; SI-NEXT:    s_lshr_b32 s28, s11, 16
; SI-NEXT:    s_lshr_b32 s29, s9, 16
; SI-NEXT:    s_lshr_b32 s40, s7, 16
; SI-NEXT:    s_lshr_b32 s41, s5, 16
; SI-NEXT:  .LBB45_3: ; %end
; SI-NEXT:    s_and_b32 s12, s12, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s14, 16
; SI-NEXT:    s_or_b32 s12, s12, s14
; SI-NEXT:    s_and_b32 s13, s13, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s27, 16
; SI-NEXT:    s_or_b32 s13, s13, s14
; SI-NEXT:    s_and_b32 s10, s10, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s16, 16
; SI-NEXT:    s_or_b32 s10, s10, s14
; SI-NEXT:    s_and_b32 s11, s11, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s28, 16
; SI-NEXT:    s_or_b32 s11, s11, s14
; SI-NEXT:    s_and_b32 s8, s8, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s18, 16
; SI-NEXT:    s_or_b32 s8, s8, s14
; SI-NEXT:    s_and_b32 s9, s9, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s29, 16
; SI-NEXT:    s_or_b32 s9, s9, s14
; SI-NEXT:    s_and_b32 s6, s6, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s20, 16
; SI-NEXT:    s_or_b32 s6, s6, s14
; SI-NEXT:    s_and_b32 s7, s7, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s40, 16
; SI-NEXT:    s_or_b32 s7, s7, s14
; SI-NEXT:    s_and_b32 s4, s4, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s22, 16
; SI-NEXT:    s_or_b32 s4, s4, s14
; SI-NEXT:    s_and_b32 s5, s5, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s41, 16
; SI-NEXT:    s_or_b32 s5, s5, s14
; SI-NEXT:    v_mov_b32_e32 v0, s12
; SI-NEXT:    v_mov_b32_e32 v1, s13
; SI-NEXT:    v_mov_b32_e32 v2, s10
; SI-NEXT:    v_mov_b32_e32 v3, s11
; SI-NEXT:    v_mov_b32_e32 v4, s8
; SI-NEXT:    v_mov_b32_e32 v5, s9
; SI-NEXT:    v_mov_b32_e32 v6, s6
; SI-NEXT:    v_mov_b32_e32 v7, s7
; SI-NEXT:    v_mov_b32_e32 v8, s4
; SI-NEXT:    v_mov_b32_e32 v9, s5
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v20i16_to_v20f16_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc1 .LBB45_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    s_add_i32 s5, s16, 3
; VI-NEXT:    s_and_b32 s6, s17, 0xffff0000
; VI-NEXT:    s_add_i32 s7, s17, 3
; VI-NEXT:    s_and_b32 s8, s18, 0xffff0000
; VI-NEXT:    s_add_i32 s9, s18, 3
; VI-NEXT:    s_and_b32 s10, s19, 0xffff0000
; VI-NEXT:    s_add_i32 s11, s19, 3
; VI-NEXT:    s_add_i32 s13, s20, 3
; VI-NEXT:    s_and_b32 s14, s21, 0xffff0000
; VI-NEXT:    s_add_i32 s15, s21, 3
; VI-NEXT:    s_add_i32 s17, s22, 3
; VI-NEXT:    s_and_b32 s18, s23, 0xffff0000
; VI-NEXT:    s_add_i32 s19, s23, 3
; VI-NEXT:    s_add_i32 s21, s24, 3
; VI-NEXT:    s_add_i32 s23, s25, 3
; VI-NEXT:    s_and_b32 s4, s16, 0xffff0000
; VI-NEXT:    s_and_b32 s12, s20, 0xffff0000
; VI-NEXT:    s_and_b32 s16, s22, 0xffff0000
; VI-NEXT:    s_and_b32 s20, s24, 0xffff0000
; VI-NEXT:    s_and_b32 s22, s25, 0xffff0000
; VI-NEXT:    s_and_b32 s23, s23, 0xffff
; VI-NEXT:    s_and_b32 s21, s21, 0xffff
; VI-NEXT:    s_and_b32 s19, s19, 0xffff
; VI-NEXT:    s_and_b32 s17, s17, 0xffff
; VI-NEXT:    s_and_b32 s15, s15, 0xffff
; VI-NEXT:    s_and_b32 s13, s13, 0xffff
; VI-NEXT:    s_and_b32 s11, s11, 0xffff
; VI-NEXT:    s_and_b32 s9, s9, 0xffff
; VI-NEXT:    s_and_b32 s7, s7, 0xffff
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s22, s22, s23
; VI-NEXT:    s_or_b32 s20, s20, s21
; VI-NEXT:    s_or_b32 s18, s18, s19
; VI-NEXT:    s_or_b32 s16, s16, s17
; VI-NEXT:    s_or_b32 s14, s14, s15
; VI-NEXT:    s_or_b32 s12, s12, s13
; VI-NEXT:    s_or_b32 s10, s10, s11
; VI-NEXT:    s_or_b32 s8, s8, s9
; VI-NEXT:    s_or_b32 s6, s6, s7
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s25, s22, 0x30000
; VI-NEXT:    s_add_i32 s24, s20, 0x30000
; VI-NEXT:    s_add_i32 s23, s18, 0x30000
; VI-NEXT:    s_add_i32 s22, s16, 0x30000
; VI-NEXT:    s_add_i32 s21, s14, 0x30000
; VI-NEXT:    s_add_i32 s20, s12, 0x30000
; VI-NEXT:    s_add_i32 s19, s10, 0x30000
; VI-NEXT:    s_add_i32 s18, s8, 0x30000
; VI-NEXT:    s_add_i32 s17, s6, 0x30000
; VI-NEXT:    s_add_i32 s16, s4, 0x30000
; VI-NEXT:  .LBB45_2: ; %end
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s17
; VI-NEXT:    v_mov_b32_e32 v2, s18
; VI-NEXT:    v_mov_b32_e32 v3, s19
; VI-NEXT:    v_mov_b32_e32 v4, s20
; VI-NEXT:    v_mov_b32_e32 v5, s21
; VI-NEXT:    v_mov_b32_e32 v6, s22
; VI-NEXT:    v_mov_b32_e32 v7, s23
; VI-NEXT:    v_mov_b32_e32 v8, s24
; VI-NEXT:    v_mov_b32_e32 v9, s25
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v20i16_to_v20f16_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc0 .LBB45_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s17
; GFX9-NEXT:    v_mov_b32_e32 v2, s18
; GFX9-NEXT:    v_mov_b32_e32 v3, s19
; GFX9-NEXT:    v_mov_b32_e32 v4, s20
; GFX9-NEXT:    v_mov_b32_e32 v5, s21
; GFX9-NEXT:    v_mov_b32_e32 v6, s22
; GFX9-NEXT:    v_mov_b32_e32 v7, s23
; GFX9-NEXT:    v_mov_b32_e32 v8, s24
; GFX9-NEXT:    v_mov_b32_e32 v9, s25
; GFX9-NEXT:    v_mov_b32_e32 v10, s26
; GFX9-NEXT:    v_mov_b32_e32 v11, s27
; GFX9-NEXT:    v_mov_b32_e32 v12, s28
; GFX9-NEXT:    v_mov_b32_e32 v13, s29
; GFX9-NEXT:    v_mov_b32_e32 v14, s30
; GFX9-NEXT:    v_mov_b32_e32 v15, s31
; GFX9-NEXT:    s_setpc_b64 s[30:31]
; GFX9-NEXT:  .LBB45_2: ; %cmp.true
; GFX9-NEXT:    v_pk_add_u16 v9, s25, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v8, s24, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v7, s23, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v6, s22, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v5, s21, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v4, s20, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v3, s19, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v20i16_to_v20f16_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s15, s3
; GFX11-NEXT:    s_mov_b32 s14, s2
; GFX11-NEXT:    s_mov_b32 s13, s1
; GFX11-NEXT:    s_mov_b32 s12, s0
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc0 .LBB45_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-NEXT:    v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
; GFX11-NEXT:    v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT:    v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
; GFX11-NEXT:    v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
; GFX11-NEXT:    v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
; GFX11-NEXT:    s_setpc_b64 s[30:31]
; GFX11-NEXT:  .LBB45_2: ; %cmp.true
; GFX11-NEXT:    v_pk_add_u16 v9, s21, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v8, s20, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v7, s19, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v6, s18, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v5, s17, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v4, s16, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v3, s15, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v2, s14, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v1, s13, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v0, s12, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <20 x i16> %a, splat (i16 3)
  %a2 = bitcast <20 x i16> %a1 to <20 x half>
  br label %end

cmp.false:
  %a3 = bitcast <20 x i16> %a to <20 x half>
  br label %end

end:
  %phi = phi <20 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <20 x half> %phi
}

define <20 x i16> @bitcast_v20f16_to_v20i16(<20 x half> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v20f16_to_v20i16:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_lshrrev_b32_e32 v11, 16, v9
; SI-NEXT:    v_lshrrev_b32_e32 v13, 16, v8
; SI-NEXT:    v_lshrrev_b32_e32 v12, 16, v7
; SI-NEXT:    v_lshrrev_b32_e32 v16, 16, v6
; SI-NEXT:    v_lshrrev_b32_e32 v14, 16, v5
; SI-NEXT:    v_lshrrev_b32_e32 v18, 16, v4
; SI-NEXT:    v_lshrrev_b32_e32 v15, 16, v3
; SI-NEXT:    v_lshrrev_b32_e32 v19, 16, v2
; SI-NEXT:    v_lshrrev_b32_e32 v17, 16, v1
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; SI-NEXT:    v_lshrrev_b32_e32 v10, 16, v0
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB46_2
; SI-NEXT:  ; %bb.1: ; %cmp.true
; SI-NEXT:    v_cvt_f32_f16_e32 v11, v11
; SI-NEXT:    v_cvt_f32_f16_e32 v9, v9
; SI-NEXT:    v_cvt_f32_f16_e32 v12, v12
; SI-NEXT:    v_cvt_f32_f16_e32 v7, v7
; SI-NEXT:    v_cvt_f32_f16_e32 v14, v14
; SI-NEXT:    v_cvt_f32_f16_e32 v5, v5
; SI-NEXT:    v_cvt_f32_f16_e32 v15, v15
; SI-NEXT:    v_add_f32_e32 v11, 0x38000000, v11
; SI-NEXT:    v_cvt_f32_f16_e32 v3, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v17, v17
; SI-NEXT:    v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT:    v_cvt_f16_f32_e32 v11, v11
; SI-NEXT:    v_add_f32_e32 v12, 0x38000000, v12
; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v10, v10
; SI-NEXT:    v_cvt_f32_f16_e32 v19, v19
; SI-NEXT:    v_cvt_f32_f16_e32 v18, v18
; SI-NEXT:    v_cvt_f32_f16_e32 v16, v16
; SI-NEXT:    v_cvt_f32_f16_e32 v13, v13
; SI-NEXT:    v_cvt_f16_f32_e32 v9, v9
; SI-NEXT:    v_cvt_f16_f32_e32 v12, v12
; SI-NEXT:    v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT:    v_add_f32_e32 v14, 0x38000000, v14
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; SI-NEXT:    v_cvt_f32_f16_e32 v2, v2
; SI-NEXT:    v_cvt_f32_f16_e32 v4, v4
; SI-NEXT:    v_cvt_f32_f16_e32 v6, v6
; SI-NEXT:    v_cvt_f32_f16_e32 v8, v8
; SI-NEXT:    v_cvt_f16_f32_e32 v7, v7
; SI-NEXT:    v_cvt_f16_f32_e32 v14, v14
; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT:    v_add_f32_e32 v15, 0x38000000, v15
; SI-NEXT:    v_cvt_f16_f32_e32 v5, v5
; SI-NEXT:    v_cvt_f16_f32_e32 v15, v15
; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT:    v_add_f32_e32 v17, 0x38000000, v17
; SI-NEXT:    v_lshlrev_b32_e32 v20, 16, v11
; SI-NEXT:    v_cvt_f16_f32_e32 v3, v3
; SI-NEXT:    v_cvt_f16_f32_e32 v17, v17
; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT:    v_add_f32_e32 v10, 0x38000000, v10
; SI-NEXT:    v_add_f32_e32 v19, 0x38000000, v19
; SI-NEXT:    v_add_f32_e32 v18, 0x38000000, v18
; SI-NEXT:    v_add_f32_e32 v16, 0x38000000, v16
; SI-NEXT:    v_add_f32_e32 v13, 0x38000000, v13
; SI-NEXT:    v_or_b32_e32 v9, v9, v20
; SI-NEXT:    v_lshlrev_b32_e32 v20, 16, v12
; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1
; SI-NEXT:    v_cvt_f16_f32_e32 v10, v10
; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT:    v_cvt_f16_f32_e32 v19, v19
; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT:    v_cvt_f16_f32_e32 v18, v18
; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT:    v_cvt_f16_f32_e32 v16, v16
; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT:    v_cvt_f16_f32_e32 v13, v13
; SI-NEXT:    v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT:    v_or_b32_e32 v7, v7, v20
; SI-NEXT:    v_lshlrev_b32_e32 v20, 16, v14
; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; SI-NEXT:    v_cvt_f16_f32_e32 v4, v4
; SI-NEXT:    v_cvt_f16_f32_e32 v6, v6
; SI-NEXT:    v_cvt_f16_f32_e32 v8, v8
; SI-NEXT:    v_or_b32_e32 v5, v5, v20
; SI-NEXT:    v_lshlrev_b32_e32 v20, 16, v15
; SI-NEXT:    v_or_b32_e32 v3, v3, v20
; SI-NEXT:    v_lshlrev_b32_e32 v20, 16, v17
; SI-NEXT:    v_or_b32_e32 v1, v1, v20
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT:    v_or_b32_e32 v0, v0, v10
; SI-NEXT:    v_or_b32_e32 v2, v2, v19
; SI-NEXT:    v_or_b32_e32 v4, v4, v18
; SI-NEXT:    v_or_b32_e32 v6, v6, v16
; SI-NEXT:    v_or_b32_e32 v8, v8, v13
; SI-NEXT:    v_alignbit_b32 v10, v1, v10, 16
; SI-NEXT:    v_alignbit_b32 v19, v3, v19, 16
; SI-NEXT:    v_alignbit_b32 v18, v5, v18, 16
; SI-NEXT:    v_alignbit_b32 v16, v7, v16, 16
; SI-NEXT:    v_alignbit_b32 v13, v9, v13, 16
; SI-NEXT:  .LBB46_2: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT:    v_or_b32_e32 v0, v0, v10
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v17
; SI-NEXT:    v_or_b32_e32 v1, v1, v10
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v19
; SI-NEXT:    v_or_b32_e32 v2, v2, v10
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v15
; SI-NEXT:    v_or_b32_e32 v3, v3, v10
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v18
; SI-NEXT:    v_or_b32_e32 v4, v4, v10
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v14
; SI-NEXT:    v_or_b32_e32 v5, v5, v10
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v16
; SI-NEXT:    v_or_b32_e32 v6, v6, v10
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v12
; SI-NEXT:    v_or_b32_e32 v7, v7, v10
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v13
; SI-NEXT:    v_or_b32_e32 v8, v8, v10
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v11
; SI-NEXT:    v_or_b32_e32 v9, v9, v10
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v20f16_to_v20i16:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB46_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    v_mov_b32_e32 v11, 0x200
; VI-NEXT:    v_add_f16_e32 v10, 0x200, v0
; VI-NEXT:    v_add_f16_sdwa v0, v0, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v12, 0x200, v1
; VI-NEXT:    v_add_f16_sdwa v1, v1, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v13, 0x200, v2
; VI-NEXT:    v_add_f16_sdwa v2, v2, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v14, 0x200, v3
; VI-NEXT:    v_add_f16_sdwa v3, v3, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v15, 0x200, v4
; VI-NEXT:    v_add_f16_sdwa v4, v4, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v16, 0x200, v5
; VI-NEXT:    v_add_f16_sdwa v5, v5, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v17, 0x200, v6
; VI-NEXT:    v_add_f16_sdwa v6, v6, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v18, 0x200, v7
; VI-NEXT:    v_add_f16_sdwa v7, v7, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v19, 0x200, v8
; VI-NEXT:    v_add_f16_sdwa v8, v8, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_sdwa v11, v9, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v9, 0x200, v9
; VI-NEXT:    v_or_b32_e32 v9, v9, v11
; VI-NEXT:    v_or_b32_e32 v8, v19, v8
; VI-NEXT:    v_or_b32_e32 v7, v18, v7
; VI-NEXT:    v_or_b32_e32 v6, v17, v6
; VI-NEXT:    v_or_b32_e32 v5, v16, v5
; VI-NEXT:    v_or_b32_e32 v4, v15, v4
; VI-NEXT:    v_or_b32_e32 v3, v14, v3
; VI-NEXT:    v_or_b32_e32 v2, v13, v2
; VI-NEXT:    v_or_b32_e32 v1, v12, v1
; VI-NEXT:    v_or_b32_e32 v0, v10, v0
; VI-NEXT:  .LBB46_2: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v20f16_to_v20i16:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB46_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    s_movk_i32 s6, 0x200
; GFX9-NEXT:    v_pk_add_f16 v9, v9, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v8, v8, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
; GFX9-NEXT:  .LBB46_2: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v20f16_to_v20i16:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB46_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    v_pk_add_f16 v9, v9, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v8, v8, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v7, v7, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v6, v6, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v5, v5, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v4, v4, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v3, v3, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v2, v2, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v1, v1, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v0, v0, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:  .LBB46_2: ; %end
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <20 x half> %a, splat (half 0xH0200)
  %a2 = bitcast <20 x half> %a1 to <20 x i16>
  br label %end

cmp.false:
  %a3 = bitcast <20 x half> %a to <20 x i16>
  br label %end

end:
  %phi = phi <20 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <20 x i16> %phi
}

define inreg <20 x i16> @bitcast_v20f16_to_v20i16_scalar(<20 x half> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v20f16_to_v20i16_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_lshr_b32 s9, s25, 16
; SI-NEXT:    s_lshr_b32 s8, s24, 16
; SI-NEXT:    s_lshr_b32 s7, s23, 16
; SI-NEXT:    s_lshr_b32 s10, s22, 16
; SI-NEXT:    s_lshr_b32 s6, s21, 16
; SI-NEXT:    s_lshr_b32 s11, s20, 16
; SI-NEXT:    s_lshr_b32 s5, s19, 16
; SI-NEXT:    s_lshr_b32 s12, s18, 16
; SI-NEXT:    s_lshr_b32 s4, s17, 16
; SI-NEXT:    s_lshr_b32 s13, s16, 16
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc0 .LBB47_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    v_mov_b32_e32 v21, s9
; SI-NEXT:    v_mov_b32_e32 v22, s7
; SI-NEXT:    v_mov_b32_e32 v23, s6
; SI-NEXT:    v_mov_b32_e32 v24, s5
; SI-NEXT:    v_mov_b32_e32 v25, s4
; SI-NEXT:    v_mov_b32_e32 v1, s17
; SI-NEXT:    v_mov_b32_e32 v3, s19
; SI-NEXT:    v_mov_b32_e32 v5, s21
; SI-NEXT:    v_mov_b32_e32 v7, s23
; SI-NEXT:    v_mov_b32_e32 v9, s25
; SI-NEXT:    v_mov_b32_e32 v26, s24
; SI-NEXT:    v_mov_b32_e32 v27, s22
; SI-NEXT:    v_mov_b32_e32 v28, s20
; SI-NEXT:    v_mov_b32_e32 v29, s18
; SI-NEXT:    v_mov_b32_e32 v20, s16
; SI-NEXT:    v_mov_b32_e32 v18, s13
; SI-NEXT:    v_mov_b32_e32 v16, s12
; SI-NEXT:    v_mov_b32_e32 v14, s11
; SI-NEXT:    v_mov_b32_e32 v12, s10
; SI-NEXT:    v_mov_b32_e32 v10, s8
; SI-NEXT:    s_branch .LBB47_3
; SI-NEXT:  .LBB47_2: ; %cmp.true
; SI-NEXT:    v_cvt_f32_f16_e32 v0, s13
; SI-NEXT:    v_cvt_f32_f16_e32 v1, s16
; SI-NEXT:    v_cvt_f32_f16_e32 v3, s18
; SI-NEXT:    v_cvt_f32_f16_e32 v5, s20
; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1
; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT:    v_cvt_f16_f32_e32 v10, v3
; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT:    v_or_b32_e32 v20, v1, v0
; SI-NEXT:    v_cvt_f32_f16_e32 v1, s11
; SI-NEXT:    v_cvt_f32_f16_e32 v3, s10
; SI-NEXT:    v_add_f32_e32 v11, 0x38000000, v5
; SI-NEXT:    v_cvt_f32_f16_e32 v5, s6
; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1
; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT:    v_cvt_f16_f32_e32 v3, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v9, s19
; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v1, s8
; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v3, s9
; SI-NEXT:    v_cvt_f32_f16_e32 v12, s25
; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT:    v_cvt_f16_f32_e32 v8, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v1, s7
; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT:    v_cvt_f16_f32_e32 v21, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v3, s23
; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT:    v_cvt_f16_f32_e32 v22, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v2, s12
; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v3
; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1
; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v5
; SI-NEXT:    v_cvt_f16_f32_e32 v23, v3
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v22
; SI-NEXT:    v_cvt_f32_f16_e32 v5, s21
; SI-NEXT:    v_or_b32_e32 v7, v1, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v3, s5
; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v23
; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT:    v_cvt_f16_f32_e32 v5, v5
; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT:    v_cvt_f16_f32_e32 v24, v3
; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v9
; SI-NEXT:    v_cvt_f16_f32_e32 v3, v3
; SI-NEXT:    v_or_b32_e32 v5, v5, v1
; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v24
; SI-NEXT:    v_cvt_f32_f16_e32 v9, s4
; SI-NEXT:    v_or_b32_e32 v3, v3, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v1, s17
; SI-NEXT:    v_lshlrev_b32_e32 v13, 16, v21
; SI-NEXT:    v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT:    v_cvt_f16_f32_e32 v25, v9
; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT:    v_add_f32_e32 v9, 0x38000000, v12
; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1
; SI-NEXT:    v_cvt_f16_f32_e32 v9, v9
; SI-NEXT:    v_lshlrev_b32_e32 v12, 16, v25
; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v12
; SI-NEXT:    v_cvt_f32_f16_e32 v12, s22
; SI-NEXT:    v_or_b32_e32 v9, v9, v13
; SI-NEXT:    v_cvt_f32_f16_e32 v13, s24
; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; SI-NEXT:    v_add_f32_e32 v12, 0x38000000, v12
; SI-NEXT:    v_cvt_f16_f32_e32 v11, v11
; SI-NEXT:    v_add_f32_e32 v13, 0x38000000, v13
; SI-NEXT:    v_cvt_f16_f32_e32 v12, v12
; SI-NEXT:    v_cvt_f16_f32_e32 v13, v13
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT:    v_or_b32_e32 v29, v10, v2
; SI-NEXT:    v_or_b32_e32 v28, v11, v4
; SI-NEXT:    v_or_b32_e32 v27, v12, v6
; SI-NEXT:    v_or_b32_e32 v26, v13, v8
; SI-NEXT:    v_lshr_b64 v[18:19], v[0:1], 16
; SI-NEXT:    v_lshr_b64 v[16:17], v[2:3], 16
; SI-NEXT:    v_lshr_b64 v[14:15], v[4:5], 16
; SI-NEXT:    v_lshr_b64 v[12:13], v[6:7], 16
; SI-NEXT:    v_lshr_b64 v[10:11], v[8:9], 16
; SI-NEXT:  .LBB47_3: ; %end
; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v18
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v20
; SI-NEXT:    v_or_b32_e32 v0, v2, v0
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v25
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v16
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v29
; SI-NEXT:    v_or_b32_e32 v2, v4, v2
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v24
; SI-NEXT:    v_or_b32_e32 v3, v3, v4
; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v14
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v28
; SI-NEXT:    v_or_b32_e32 v4, v6, v4
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v23
; SI-NEXT:    v_or_b32_e32 v5, v5, v6
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v27
; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v12
; SI-NEXT:    v_or_b32_e32 v6, v6, v8
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v22
; SI-NEXT:    v_or_b32_e32 v7, v7, v8
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v26
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT:    v_or_b32_e32 v8, v8, v10
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v21
; SI-NEXT:    v_or_b32_e32 v9, v9, v10
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v20f16_to_v20i16_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc0 .LBB47_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s17
; VI-NEXT:    v_mov_b32_e32 v2, s18
; VI-NEXT:    v_mov_b32_e32 v3, s19
; VI-NEXT:    v_mov_b32_e32 v4, s20
; VI-NEXT:    v_mov_b32_e32 v5, s21
; VI-NEXT:    v_mov_b32_e32 v6, s22
; VI-NEXT:    v_mov_b32_e32 v7, s23
; VI-NEXT:    v_mov_b32_e32 v8, s24
; VI-NEXT:    v_mov_b32_e32 v9, s25
; VI-NEXT:    v_mov_b32_e32 v10, s26
; VI-NEXT:    v_mov_b32_e32 v11, s27
; VI-NEXT:    v_mov_b32_e32 v12, s28
; VI-NEXT:    v_mov_b32_e32 v13, s29
; VI-NEXT:    v_mov_b32_e32 v14, s30
; VI-NEXT:    v_mov_b32_e32 v15, s31
; VI-NEXT:    s_setpc_b64 s[30:31]
; VI-NEXT:  .LBB47_2: ; %cmp.true
; VI-NEXT:    s_lshr_b32 s5, s24, 16
; VI-NEXT:    v_mov_b32_e32 v0, 0x200
; VI-NEXT:    v_mov_b32_e32 v2, s5
; VI-NEXT:    s_lshr_b32 s5, s25, 16
; VI-NEXT:    v_add_f16_e32 v1, s24, v0
; VI-NEXT:    v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_mov_b32_e32 v4, s5
; VI-NEXT:    s_lshr_b32 s5, s23, 16
; VI-NEXT:    v_or_b32_e32 v8, v1, v2
; VI-NEXT:    v_mov_b32_e32 v2, s5
; VI-NEXT:    v_add_f16_e32 v1, s23, v0
; VI-NEXT:    v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    s_lshr_b32 s5, s22, 16
; VI-NEXT:    v_or_b32_e32 v7, v1, v2
; VI-NEXT:    v_mov_b32_e32 v2, s5
; VI-NEXT:    v_add_f16_e32 v1, s22, v0
; VI-NEXT:    v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    s_lshr_b32 s5, s21, 16
; VI-NEXT:    v_or_b32_e32 v6, v1, v2
; VI-NEXT:    v_mov_b32_e32 v2, s5
; VI-NEXT:    v_add_f16_e32 v1, s21, v0
; VI-NEXT:    v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    s_lshr_b32 s5, s20, 16
; VI-NEXT:    v_or_b32_e32 v5, v1, v2
; VI-NEXT:    v_mov_b32_e32 v2, s5
; VI-NEXT:    v_add_f16_e32 v3, s25, v0
; VI-NEXT:    v_add_f16_sdwa v4, v4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v1, s20, v0
; VI-NEXT:    v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    s_lshr_b32 s5, s19, 16
; VI-NEXT:    v_or_b32_e32 v9, v3, v4
; VI-NEXT:    v_or_b32_e32 v4, v1, v2
; VI-NEXT:    v_mov_b32_e32 v2, s5
; VI-NEXT:    v_add_f16_e32 v1, s19, v0
; VI-NEXT:    v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    s_lshr_b32 s5, s18, 16
; VI-NEXT:    v_or_b32_e32 v3, v1, v2
; VI-NEXT:    v_mov_b32_e32 v2, s5
; VI-NEXT:    s_lshr_b32 s4, s16, 16
; VI-NEXT:    v_add_f16_e32 v1, s18, v0
; VI-NEXT:    v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v2, v1, v2
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    s_lshr_b32 s4, s17, 16
; VI-NEXT:    v_add_f16_sdwa v11, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_e32 v10, s16, v0
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v0, s17, v0
; VI-NEXT:    v_or_b32_e32 v1, v0, v1
; VI-NEXT:    v_or_b32_e32 v0, v10, v11
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v20f16_to_v20i16_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc0 .LBB47_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s17
; GFX9-NEXT:    v_mov_b32_e32 v2, s18
; GFX9-NEXT:    v_mov_b32_e32 v3, s19
; GFX9-NEXT:    v_mov_b32_e32 v4, s20
; GFX9-NEXT:    v_mov_b32_e32 v5, s21
; GFX9-NEXT:    v_mov_b32_e32 v6, s22
; GFX9-NEXT:    v_mov_b32_e32 v7, s23
; GFX9-NEXT:    v_mov_b32_e32 v8, s24
; GFX9-NEXT:    v_mov_b32_e32 v9, s25
; GFX9-NEXT:    v_mov_b32_e32 v10, s26
; GFX9-NEXT:    v_mov_b32_e32 v11, s27
; GFX9-NEXT:    v_mov_b32_e32 v12, s28
; GFX9-NEXT:    v_mov_b32_e32 v13, s29
; GFX9-NEXT:    v_mov_b32_e32 v14, s30
; GFX9-NEXT:    v_mov_b32_e32 v15, s31
; GFX9-NEXT:    s_setpc_b64 s[30:31]
; GFX9-NEXT:  .LBB47_2: ; %cmp.true
; GFX9-NEXT:    v_mov_b32_e32 v0, 0x200
; GFX9-NEXT:    v_pk_add_f16 v9, s25, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v8, s24, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v7, s23, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v6, s22, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v5, s21, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v4, s20, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v3, s19, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v20f16_to_v20i16_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s15, s3
; GFX11-NEXT:    s_mov_b32 s14, s2
; GFX11-NEXT:    s_mov_b32 s13, s1
; GFX11-NEXT:    s_mov_b32 s12, s0
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc0 .LBB47_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-NEXT:    v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
; GFX11-NEXT:    v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT:    v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
; GFX11-NEXT:    v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
; GFX11-NEXT:    v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
; GFX11-NEXT:    s_setpc_b64 s[30:31]
; GFX11-NEXT:  .LBB47_2: ; %cmp.true
; GFX11-NEXT:    v_pk_add_f16 v9, s21, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v8, s20, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v7, s19, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v6, s18, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v5, s17, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v4, s16, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v3, s15, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v2, s14, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v1, s13, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v0, s12, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <20 x half> %a, splat (half 0xH0200)
  %a2 = bitcast <20 x half> %a1 to <20 x i16>
  br label %end

cmp.false:
  %a3 = bitcast <20 x half> %a to <20 x i16>
  br label %end

end:
  %phi = phi <20 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <20 x i16> %phi
}

define <40 x i8> @bitcast_v20i16_to_v40i8(<20 x i16> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v20i16_to_v40i8:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    buffer_store_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v43, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v44, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v45, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v46, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v47, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v56, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v57, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v60, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT:    v_lshrrev_b32_e32 v12, 16, v10
; SI-NEXT:    v_lshrrev_b32_e32 v14, 16, v9
; SI-NEXT:    v_lshrrev_b32_e32 v13, 16, v8
; SI-NEXT:    v_lshrrev_b32_e32 v16, 16, v7
; SI-NEXT:    v_lshrrev_b32_e32 v15, 16, v6
; SI-NEXT:    v_lshrrev_b32_e32 v17, 16, v5
; SI-NEXT:    v_lshrrev_b32_e32 v18, 16, v4
; SI-NEXT:    v_lshrrev_b32_e32 v19, 16, v3
; SI-NEXT:    v_lshrrev_b32_e32 v23, 16, v2
; SI-NEXT:    v_lshrrev_b32_e32 v20, 16, v1
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
; SI-NEXT:    v_lshlrev_b32_e32 v44, 16, v20
; SI-NEXT:    v_lshlrev_b32_e32 v43, 16, v23
; SI-NEXT:    s_waitcnt expcnt(6)
; SI-NEXT:    v_lshlrev_b32_e32 v46, 16, v19
; SI-NEXT:    v_lshlrev_b32_e32 v45, 16, v18
; SI-NEXT:    s_waitcnt expcnt(4)
; SI-NEXT:    v_lshlrev_b32_e32 v56, 16, v17
; SI-NEXT:    v_lshlrev_b32_e32 v47, 16, v15
; SI-NEXT:    s_waitcnt expcnt(2)
; SI-NEXT:    v_lshlrev_b32_e32 v58, 16, v16
; SI-NEXT:    v_lshlrev_b32_e32 v57, 16, v13
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_lshlrev_b32_e32 v60, 16, v14
; SI-NEXT:    v_lshlrev_b32_e32 v59, 16, v12
; SI-NEXT:    ; implicit-def: $vgpr26
; SI-NEXT:    ; implicit-def: $vgpr48
; SI-NEXT:    ; implicit-def: $vgpr37
; SI-NEXT:    ; implicit-def: $vgpr34
; SI-NEXT:    ; implicit-def: $vgpr27
; SI-NEXT:    ; implicit-def: $vgpr41
; SI-NEXT:    ; implicit-def: $vgpr42
; SI-NEXT:    ; implicit-def: $vgpr21
; SI-NEXT:    ; implicit-def: $vgpr39
; SI-NEXT:    ; implicit-def: $vgpr35
; SI-NEXT:    ; implicit-def: $vgpr31
; SI-NEXT:    ; implicit-def: $vgpr22
; SI-NEXT:    ; implicit-def: $vgpr55
; SI-NEXT:    ; implicit-def: $vgpr40
; SI-NEXT:    ; implicit-def: $vgpr19
; SI-NEXT:    ; implicit-def: $vgpr38
; SI-NEXT:    ; implicit-def: $vgpr32
; SI-NEXT:    ; implicit-def: $vgpr29
; SI-NEXT:    ; implicit-def: $vgpr20
; SI-NEXT:    ; implicit-def: $vgpr53
; SI-NEXT:    ; implicit-def: $vgpr54
; SI-NEXT:    ; implicit-def: $vgpr16
; SI-NEXT:    ; implicit-def: $vgpr36
; SI-NEXT:    ; implicit-def: $vgpr30
; SI-NEXT:    ; implicit-def: $vgpr25
; SI-NEXT:    ; implicit-def: $vgpr17
; SI-NEXT:    ; implicit-def: $vgpr51
; SI-NEXT:    ; implicit-def: $vgpr52
; SI-NEXT:    ; implicit-def: $vgpr11
; SI-NEXT:    ; implicit-def: $vgpr33
; SI-NEXT:    ; implicit-def: $vgpr28
; SI-NEXT:    ; implicit-def: $vgpr24
; SI-NEXT:    ; implicit-def: $vgpr14
; SI-NEXT:    ; implicit-def: $vgpr49
; SI-NEXT:    ; implicit-def: $vgpr50
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB48_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v26, v1, v44
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v2
; SI-NEXT:    v_or_b32_e32 v27, v1, v43
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v3
; SI-NEXT:    v_or_b32_e32 v21, v1, v46
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v4
; SI-NEXT:    v_or_b32_e32 v22, v1, v45
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v5
; SI-NEXT:    v_or_b32_e32 v19, v1, v56
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v6
; SI-NEXT:    v_or_b32_e32 v20, v1, v47
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v7
; SI-NEXT:    v_or_b32_e32 v16, v1, v58
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v8
; SI-NEXT:    v_or_b32_e32 v17, v1, v57
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v9
; SI-NEXT:    v_or_b32_e32 v11, v1, v60
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v10
; SI-NEXT:    v_or_b32_e32 v14, v1, v59
; SI-NEXT:    v_alignbit_b32 v34, v27, v26, 24
; SI-NEXT:    v_alignbit_b32 v37, v27, v26, 16
; SI-NEXT:    v_alignbit_b32 v48, v27, v26, 8
; SI-NEXT:    v_alignbit_b32 v31, v22, v21, 24
; SI-NEXT:    v_alignbit_b32 v35, v22, v21, 16
; SI-NEXT:    v_alignbit_b32 v39, v22, v21, 8
; SI-NEXT:    v_alignbit_b32 v29, v20, v19, 24
; SI-NEXT:    v_alignbit_b32 v32, v20, v19, 16
; SI-NEXT:    v_alignbit_b32 v38, v20, v19, 8
; SI-NEXT:    v_alignbit_b32 v25, v17, v16, 24
; SI-NEXT:    v_alignbit_b32 v30, v17, v16, 16
; SI-NEXT:    v_alignbit_b32 v36, v17, v16, 8
; SI-NEXT:    v_alignbit_b32 v24, v14, v11, 24
; SI-NEXT:    v_alignbit_b32 v28, v14, v11, 16
; SI-NEXT:    v_alignbit_b32 v33, v14, v11, 8
; SI-NEXT:    v_lshrrev_b32_e32 v41, 8, v27
; SI-NEXT:    v_lshrrev_b32_e32 v55, 8, v22
; SI-NEXT:    v_lshrrev_b32_e32 v53, 8, v20
; SI-NEXT:    v_lshrrev_b32_e32 v51, 8, v17
; SI-NEXT:    v_lshrrev_b32_e32 v49, 8, v14
; SI-NEXT:    v_bfe_u32 v42, v23, 8, 8
; SI-NEXT:    v_bfe_u32 v40, v18, 8, 8
; SI-NEXT:    v_bfe_u32 v54, v15, 8, 8
; SI-NEXT:    v_bfe_u32 v52, v13, 8, 8
; SI-NEXT:    v_bfe_u32 v50, v12, 8, 8
; SI-NEXT:    ; implicit-def: $vgpr1
; SI-NEXT:    ; implicit-def: $vgpr2
; SI-NEXT:    ; implicit-def: $vgpr3
; SI-NEXT:    ; implicit-def: $vgpr4
; SI-NEXT:    ; implicit-def: $vgpr5
; SI-NEXT:    ; implicit-def: $vgpr6
; SI-NEXT:    ; implicit-def: $vgpr7
; SI-NEXT:    ; implicit-def: $vgpr8
; SI-NEXT:    ; implicit-def: $vgpr9
; SI-NEXT:    ; implicit-def: $vgpr10
; SI-NEXT:    ; implicit-def: $vgpr44
; SI-NEXT:    ; implicit-def: $vgpr43
; SI-NEXT:    ; implicit-def: $vgpr46
; SI-NEXT:    ; implicit-def: $vgpr45
; SI-NEXT:    ; implicit-def: $vgpr56
; SI-NEXT:    ; implicit-def: $vgpr47
; SI-NEXT:    ; implicit-def: $vgpr58
; SI-NEXT:    ; implicit-def: $vgpr57
; SI-NEXT:    ; implicit-def: $vgpr60
; SI-NEXT:    ; implicit-def: $vgpr59
; SI-NEXT:  .LBB48_2: ; %Flow
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB48_4
; SI-NEXT:  ; %bb.3: ; %cmp.true
; SI-NEXT:    v_add_i32_e32 v9, vcc, 3, v9
; SI-NEXT:    v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT:    v_add_i32_e32 v5, vcc, 3, v5
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v3
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v9, v60, v9
; SI-NEXT:    v_or_b32_e32 v7, v58, v7
; SI-NEXT:    v_or_b32_e32 v5, v56, v5
; SI-NEXT:    v_or_b32_e32 v3, v46, v3
; SI-NEXT:    v_or_b32_e32 v1, v44, v1
; SI-NEXT:    v_add_i32_e32 v11, vcc, 0x30000, v9
; SI-NEXT:    v_add_i32_e32 v9, vcc, 3, v10
; SI-NEXT:    v_add_i32_e32 v16, vcc, 0x30000, v7
; SI-NEXT:    v_add_i32_e32 v7, vcc, 3, v8
; SI-NEXT:    v_add_i32_e32 v19, vcc, 0x30000, v5
; SI-NEXT:    v_add_i32_e32 v5, vcc, 3, v6
; SI-NEXT:    v_add_i32_e32 v21, vcc, 0x30000, v3
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v4
; SI-NEXT:    v_add_i32_e32 v26, vcc, 0x30000, v1
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v2
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v9, v59, v9
; SI-NEXT:    v_or_b32_e32 v7, v57, v7
; SI-NEXT:    v_or_b32_e32 v5, v47, v5
; SI-NEXT:    v_or_b32_e32 v3, v45, v3
; SI-NEXT:    v_or_b32_e32 v1, v43, v1
; SI-NEXT:    v_add_i32_e32 v14, vcc, 0x30000, v9
; SI-NEXT:    v_add_i32_e32 v17, vcc, 0x30000, v7
; SI-NEXT:    v_add_i32_e32 v20, vcc, 0x30000, v5
; SI-NEXT:    v_add_i32_e32 v22, vcc, 0x30000, v3
; SI-NEXT:    v_add_i32_e32 v27, vcc, 0x30000, v1
; SI-NEXT:    v_alignbit_b32 v34, v27, v26, 24
; SI-NEXT:    v_alignbit_b32 v37, v27, v26, 16
; SI-NEXT:    v_alignbit_b32 v48, v27, v26, 8
; SI-NEXT:    v_alignbit_b32 v31, v22, v21, 24
; SI-NEXT:    v_alignbit_b32 v35, v22, v21, 16
; SI-NEXT:    v_alignbit_b32 v39, v22, v21, 8
; SI-NEXT:    v_alignbit_b32 v29, v20, v19, 24
; SI-NEXT:    v_alignbit_b32 v32, v20, v19, 16
; SI-NEXT:    v_alignbit_b32 v38, v20, v19, 8
; SI-NEXT:    v_alignbit_b32 v25, v17, v16, 24
; SI-NEXT:    v_alignbit_b32 v30, v17, v16, 16
; SI-NEXT:    v_alignbit_b32 v36, v17, v16, 8
; SI-NEXT:    v_alignbit_b32 v24, v14, v11, 24
; SI-NEXT:    v_alignbit_b32 v28, v14, v11, 16
; SI-NEXT:    v_alignbit_b32 v33, v14, v11, 8
; SI-NEXT:    v_lshrrev_b32_e32 v42, 24, v27
; SI-NEXT:    v_lshrrev_b32_e32 v23, 16, v27
; SI-NEXT:    v_lshrrev_b32_e32 v41, 8, v27
; SI-NEXT:    v_lshrrev_b32_e32 v40, 24, v22
; SI-NEXT:    v_lshrrev_b32_e32 v18, 16, v22
; SI-NEXT:    v_lshrrev_b32_e32 v55, 8, v22
; SI-NEXT:    v_lshrrev_b32_e32 v54, 24, v20
; SI-NEXT:    v_lshrrev_b32_e32 v15, 16, v20
; SI-NEXT:    v_lshrrev_b32_e32 v53, 8, v20
; SI-NEXT:    v_lshrrev_b32_e32 v52, 24, v17
; SI-NEXT:    v_lshrrev_b32_e32 v13, 16, v17
; SI-NEXT:    v_lshrrev_b32_e32 v51, 8, v17
; SI-NEXT:    v_lshrrev_b32_e32 v50, 24, v14
; SI-NEXT:    v_lshrrev_b32_e32 v12, 16, v14
; SI-NEXT:    v_lshrrev_b32_e32 v49, 8, v14
; SI-NEXT:  .LBB48_4: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v26
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v48
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v37
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v34
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v27
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v41
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v23
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v42
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v21
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v39
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v35
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v31
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v22
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v55
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v18
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v40
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v19
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v38
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v32
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v29
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v20
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v53
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v15
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v54
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v16
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v36
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v30
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v25
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v17
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v51
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v13
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v52
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v11
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v33
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v28
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v24
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v14
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v49
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v12
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v50
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; SI-NEXT:    buffer_load_dword v60, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v57, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v56, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v47, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v46, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v45, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v44, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v43, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v20i16_to_v40i8:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT:    buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT:    buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
; VI-NEXT:    v_lshrrev_b32_e32 v21, 16, v10
; VI-NEXT:    v_lshrrev_b32_e32 v26, 16, v9
; VI-NEXT:    v_lshrrev_b32_e32 v20, 16, v8
; VI-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
; VI-NEXT:    v_lshrrev_b32_e32 v19, 16, v6
; VI-NEXT:    v_lshrrev_b32_e32 v24, 16, v5
; VI-NEXT:    v_lshrrev_b32_e32 v18, 16, v4
; VI-NEXT:    v_lshrrev_b32_e32 v23, 16, v3
; VI-NEXT:    v_lshrrev_b32_e32 v17, 16, v2
; VI-NEXT:    v_lshrrev_b32_e32 v22, 16, v1
; VI-NEXT:    ; implicit-def: $vgpr32
; VI-NEXT:    ; implicit-def: $vgpr54
; VI-NEXT:    ; implicit-def: $vgpr15
; VI-NEXT:    ; implicit-def: $vgpr30
; VI-NEXT:    ; implicit-def: $vgpr51
; VI-NEXT:    ; implicit-def: $vgpr55
; VI-NEXT:    ; implicit-def: $vgpr38
; VI-NEXT:    ; implicit-def: $vgpr49
; VI-NEXT:    ; implicit-def: $vgpr14
; VI-NEXT:    ; implicit-def: $vgpr37
; VI-NEXT:    ; implicit-def: $vgpr39
; VI-NEXT:    ; implicit-def: $vgpr50
; VI-NEXT:    ; implicit-def: $vgpr53
; VI-NEXT:    ; implicit-def: $vgpr36
; VI-NEXT:    ; implicit-def: $vgpr13
; VI-NEXT:    ; implicit-def: $vgpr52
; VI-NEXT:    ; implicit-def: $vgpr34
; VI-NEXT:    ; implicit-def: $vgpr48
; VI-NEXT:    ; implicit-def: $vgpr16
; VI-NEXT:    ; implicit-def: $vgpr33
; VI-NEXT:    ; implicit-def: $vgpr12
; VI-NEXT:    ; implicit-def: $vgpr40
; VI-NEXT:    ; implicit-def: $vgpr29
; VI-NEXT:    ; implicit-def: $vgpr35
; VI-NEXT:    ; implicit-def: $vgpr41
; VI-NEXT:    ; implicit-def: $vgpr28
; VI-NEXT:    ; implicit-def: $vgpr11
; VI-NEXT:    ; implicit-def: $vgpr42
; VI-NEXT:    ; implicit-def: $vgpr27
; VI-NEXT:    ; implicit-def: $vgpr31
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB48_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; VI-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; VI-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; VI-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; VI-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; VI-NEXT:    v_lshrrev_b32_e32 v31, 24, v10
; VI-NEXT:    v_lshrrev_b32_e32 v27, 8, v10
; VI-NEXT:    v_lshrrev_b32_e32 v28, 8, v9
; VI-NEXT:    v_lshrrev_b32_e32 v35, 24, v8
; VI-NEXT:    v_lshrrev_b32_e32 v29, 8, v8
; VI-NEXT:    v_lshrrev_b32_e32 v33, 8, v7
; VI-NEXT:    v_lshrrev_b32_e32 v48, 24, v6
; VI-NEXT:    v_lshrrev_b32_e32 v34, 8, v6
; VI-NEXT:    v_lshrrev_b32_e32 v36, 8, v5
; VI-NEXT:    v_lshrrev_b32_e32 v50, 24, v4
; VI-NEXT:    v_lshrrev_b32_e32 v39, 8, v4
; VI-NEXT:    v_lshrrev_b32_e32 v49, 8, v3
; VI-NEXT:    v_lshrrev_b32_e32 v55, 24, v2
; VI-NEXT:    v_lshrrev_b32_e32 v51, 8, v2
; VI-NEXT:    v_lshrrev_b32_e32 v54, 8, v1
; VI-NEXT:    v_mov_b32_e32 v32, v1
; VI-NEXT:    v_mov_b32_e32 v30, v2
; VI-NEXT:    v_mov_b32_e32 v38, v3
; VI-NEXT:    v_mov_b32_e32 v37, v4
; VI-NEXT:    v_mov_b32_e32 v53, v5
; VI-NEXT:    v_mov_b32_e32 v52, v6
; VI-NEXT:    v_mov_b32_e32 v16, v7
; VI-NEXT:    v_mov_b32_e32 v40, v8
; VI-NEXT:    v_mov_b32_e32 v41, v9
; VI-NEXT:    v_mov_b32_e32 v42, v10
; VI-NEXT:    ; implicit-def: $vgpr1
; VI-NEXT:    ; implicit-def: $vgpr3
; VI-NEXT:    ; implicit-def: $vgpr5
; VI-NEXT:    ; implicit-def: $vgpr7
; VI-NEXT:    ; implicit-def: $vgpr9
; VI-NEXT:  .LBB48_2: ; %Flow
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB48_4
; VI-NEXT:  ; %bb.3: ; %cmp.true
; VI-NEXT:    v_mov_b32_e32 v11, 3
; VI-NEXT:    v_add_u16_sdwa v21, v10, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_u16_sdwa v26, v9, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_u16_sdwa v20, v8, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_u16_sdwa v25, v7, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_u16_e32 v42, 3, v10
; VI-NEXT:    v_lshlrev_b32_e32 v10, 16, v21
; VI-NEXT:    v_add_u16_e32 v41, 3, v9
; VI-NEXT:    v_lshlrev_b32_e32 v9, 16, v26
; VI-NEXT:    v_add_u16_sdwa v19, v6, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_u16_sdwa v24, v5, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_u16_e32 v40, 3, v8
; VI-NEXT:    v_lshlrev_b32_e32 v8, 16, v20
; VI-NEXT:    v_add_u16_e32 v27, 3, v7
; VI-NEXT:    v_lshlrev_b32_e32 v7, 16, v25
; VI-NEXT:    v_or_b32_e32 v10, v42, v10
; VI-NEXT:    v_or_b32_e32 v9, v41, v9
; VI-NEXT:    v_add_u16_sdwa v17, v2, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_u16_sdwa v22, v1, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_u16_sdwa v18, v4, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_u16_sdwa v23, v3, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_u16_e32 v52, 3, v6
; VI-NEXT:    v_lshlrev_b32_e32 v6, 16, v19
; VI-NEXT:    v_add_u16_e32 v53, 3, v5
; VI-NEXT:    v_lshlrev_b32_e32 v5, 16, v24
; VI-NEXT:    v_or_b32_e32 v8, v40, v8
; VI-NEXT:    v_or_b32_e32 v7, v27, v7
; VI-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; VI-NEXT:    v_add_u16_e32 v37, 3, v4
; VI-NEXT:    v_lshlrev_b32_e32 v4, 16, v18
; VI-NEXT:    v_add_u16_e32 v38, 3, v3
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v23
; VI-NEXT:    v_or_b32_e32 v6, v52, v6
; VI-NEXT:    v_or_b32_e32 v5, v53, v5
; VI-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; VI-NEXT:    v_add_u16_e32 v30, 3, v2
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v17
; VI-NEXT:    v_add_u16_e32 v32, 3, v1
; VI-NEXT:    v_lshlrev_b32_e32 v1, 16, v22
; VI-NEXT:    v_or_b32_e32 v4, v37, v4
; VI-NEXT:    v_or_b32_e32 v3, v38, v3
; VI-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; VI-NEXT:    v_or_b32_e32 v2, v30, v2
; VI-NEXT:    v_or_b32_e32 v1, v32, v1
; VI-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; VI-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; VI-NEXT:    v_mov_b32_e32 v16, v27
; VI-NEXT:    v_lshrrev_b32_e32 v27, 8, v10
; VI-NEXT:    v_lshrrev_b32_e32 v28, 8, v9
; VI-NEXT:    v_lshrrev_b32_e32 v29, 8, v8
; VI-NEXT:    v_lshrrev_b32_e32 v33, 8, v7
; VI-NEXT:    v_lshrrev_b32_e32 v34, 8, v6
; VI-NEXT:    v_lshrrev_b32_e32 v36, 8, v5
; VI-NEXT:    v_lshrrev_b32_e32 v39, 8, v4
; VI-NEXT:    v_lshrrev_b32_e32 v49, 8, v3
; VI-NEXT:    v_lshrrev_b32_e32 v51, 8, v2
; VI-NEXT:    v_lshrrev_b32_e32 v54, 8, v1
; VI-NEXT:    v_bfe_u32 v31, v21, 8, 8
; VI-NEXT:    v_bfe_u32 v35, v20, 8, 8
; VI-NEXT:    v_bfe_u32 v48, v19, 8, 8
; VI-NEXT:    v_bfe_u32 v50, v18, 8, 8
; VI-NEXT:    v_bfe_u32 v55, v17, 8, 8
; VI-NEXT:  .LBB48_4: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_mov_b32 s4, 0xc0c0004
; VI-NEXT:    v_perm_b32 v2, v22, v15, s4
; VI-NEXT:    v_perm_b32 v1, v32, v54, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v17, v55, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT:    v_perm_b32 v1, v30, v51, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v23, v14, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
; VI-NEXT:    v_perm_b32 v1, v38, v49, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v18, v50, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; VI-NEXT:    v_perm_b32 v1, v37, v39, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v24, v13, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; VI-NEXT:    v_perm_b32 v1, v53, v36, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v19, v48, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; VI-NEXT:    v_perm_b32 v1, v52, v34, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v25, v12, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; VI-NEXT:    v_perm_b32 v1, v16, v33, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v20, v35, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; VI-NEXT:    v_perm_b32 v1, v40, v29, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v26, v11, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; VI-NEXT:    v_perm_b32 v1, v41, v28, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v21, v31, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; VI-NEXT:    v_perm_b32 v1, v42, v27, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; VI-NEXT:    buffer_load_dword v42, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; VI-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v20i16_to_v40i8:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
; GFX9-NEXT:    ; implicit-def: $vgpr16
; GFX9-NEXT:    ; implicit-def: $vgpr48
; GFX9-NEXT:    ; implicit-def: $vgpr15
; GFX9-NEXT:    ; implicit-def: $vgpr39
; GFX9-NEXT:    ; implicit-def: $vgpr38
; GFX9-NEXT:    ; implicit-def: $vgpr37
; GFX9-NEXT:    ; implicit-def: $vgpr36
; GFX9-NEXT:    ; implicit-def: $vgpr35
; GFX9-NEXT:    ; implicit-def: $vgpr14
; GFX9-NEXT:    ; implicit-def: $vgpr34
; GFX9-NEXT:    ; implicit-def: $vgpr33
; GFX9-NEXT:    ; implicit-def: $vgpr32
; GFX9-NEXT:    ; implicit-def: $vgpr31
; GFX9-NEXT:    ; implicit-def: $vgpr30
; GFX9-NEXT:    ; implicit-def: $vgpr13
; GFX9-NEXT:    ; implicit-def: $vgpr29
; GFX9-NEXT:    ; implicit-def: $vgpr28
; GFX9-NEXT:    ; implicit-def: $vgpr27
; GFX9-NEXT:    ; implicit-def: $vgpr26
; GFX9-NEXT:    ; implicit-def: $vgpr25
; GFX9-NEXT:    ; implicit-def: $vgpr12
; GFX9-NEXT:    ; implicit-def: $vgpr24
; GFX9-NEXT:    ; implicit-def: $vgpr23
; GFX9-NEXT:    ; implicit-def: $vgpr22
; GFX9-NEXT:    ; implicit-def: $vgpr21
; GFX9-NEXT:    ; implicit-def: $vgpr20
; GFX9-NEXT:    ; implicit-def: $vgpr19
; GFX9-NEXT:    ; implicit-def: $vgpr18
; GFX9-NEXT:    ; implicit-def: $vgpr17
; GFX9-NEXT:    ; implicit-def: $vgpr11
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB48_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX9-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX9-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX9-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX9-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX9-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
; GFX9-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
; GFX9-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
; GFX9-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
; GFX9-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; GFX9-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; GFX9-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
; GFX9-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
; GFX9-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
; GFX9-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX9-NEXT:  .LBB48_2: ; %Flow
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB48_4
; GFX9-NEXT:  ; %bb.3: ; %cmp.true
; GFX9-NEXT:    v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX9-NEXT:    v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX9-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX9-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX9-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX9-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
; GFX9-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
; GFX9-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
; GFX9-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
; GFX9-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; GFX9-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; GFX9-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
; GFX9-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
; GFX9-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
; GFX9-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX9-NEXT:  .LBB48_4: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_mov_b32 s4, 0xc0c0004
; GFX9-NEXT:    v_perm_b32 v15, v48, v15, s4
; GFX9-NEXT:    v_perm_b32 v1, v1, v16, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v15, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen
; GFX9-NEXT:    v_perm_b32 v1, v2, v39, s4
; GFX9-NEXT:    v_perm_b32 v2, v38, v37, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT:    v_perm_b32 v1, v3, v36, s4
; GFX9-NEXT:    v_perm_b32 v2, v35, v14, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT:    v_perm_b32 v1, v4, v34, s4
; GFX9-NEXT:    v_perm_b32 v2, v33, v32, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; GFX9-NEXT:    v_perm_b32 v1, v5, v31, s4
; GFX9-NEXT:    v_perm_b32 v2, v30, v13, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT:    v_perm_b32 v1, v6, v29, s4
; GFX9-NEXT:    v_perm_b32 v2, v28, v27, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; GFX9-NEXT:    v_perm_b32 v1, v7, v26, s4
; GFX9-NEXT:    v_perm_b32 v2, v25, v12, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT:    v_perm_b32 v1, v8, v24, s4
; GFX9-NEXT:    v_perm_b32 v2, v23, v22, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; GFX9-NEXT:    v_perm_b32 v1, v9, v21, s4
; GFX9-NEXT:    v_perm_b32 v2, v20, v11, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT:    v_perm_b32 v1, v10, v19, s4
; GFX9-NEXT:    v_perm_b32 v2, v18, v17, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v20i16_to_v40i8:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v11
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr11_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB48_2
; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v18, 8, v10
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v9
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v20, 24, v8
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v8
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v22, 8, v7
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v6
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v6
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v5
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v4
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v4
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v3
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v28, 24, v2
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v2
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX11-TRUE16-NEXT:  .LBB48_2: ; %Flow
; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB48_4
; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
; GFX11-TRUE16-NEXT:    v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT:    v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT:    v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT:    v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v18, 8, v10
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v9
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v20, 24, v8
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v8
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v22, 8, v7
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v6
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v6
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v5
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v4
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v4
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v3
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v28, 24, v2
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v2
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX11-TRUE16-NEXT:  .LBB48_4: ; %end
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v31.l, v1.h
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_perm_b32 v1, v1, v16, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v16, v2, v30, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v29, v3, v29, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v3.h
; GFX11-TRUE16-NEXT:    v_perm_b32 v15, v31, v15, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v31.l, v5.h
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v30.l, v4.h
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
; GFX11-TRUE16-NEXT:    v_perm_b32 v5, v5, v25, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v1, v15, 16, v1
; GFX11-TRUE16-NEXT:    v_perm_b32 v13, v31, v13, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v3, v3, v14, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v4, v4, v27, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v14, v30, v26, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v15.l, v6.h
; GFX11-TRUE16-NEXT:    v_perm_b32 v2, v2, v28, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v5, v13, 16, v5
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v7.h
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v4, v14, 16, v4
; GFX11-TRUE16-NEXT:    v_perm_b32 v14, v15, v23, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v15.l, v8.h
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v2, v2, 16, v16
; GFX11-TRUE16-NEXT:    v_perm_b32 v12, v13, v12, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v9.h
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.l, v10.h
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, v6, v24, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, v7, v22, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v8, v8, v21, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v15, v15, v20, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v9, v9, v19, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v11, v13, v11, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v10, v10, v18, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v13, v16, v17, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v3, v3, 16, v29
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v6, v14, 16, v6
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v7, v12, 16, v7
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v8, v15, 16, v8
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v9, v11, 16, v9
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v10, v13, 16, v10
; GFX11-TRUE16-NEXT:    s_clause 0x2
; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[1:4], off
; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
; GFX11-TRUE16-NEXT:    scratch_store_b64 v0, v[9:10], off offset:32
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v20i16_to_v40i8:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v11
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB48_2
; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX11-FAKE16-NEXT:  .LBB48_2: ; %Flow
; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB48_4
; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
; GFX11-FAKE16-NEXT:    v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT:    v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT:    v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT:    v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX11-FAKE16-NEXT:  .LBB48_4: ; %end
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v3, v36, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v35, v14, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v5, v31, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v30, v13, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v1, v16, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v48, v15, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v2, v39, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v16, v38, v37, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v4, v34, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v32, v33, v32, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v3, v14, 16, v3
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v5, v13, 16, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v6, v29, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v28, v27, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v7, v26, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v25, v12, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v8, v24, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v23, v22, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v15, 16, v1
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v9, v21, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v20, v11, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v10, v19, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v18, v17, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, v16, 16, v2
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v4, v32, 16, v4
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v6, v13, 16, v6
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v7, v12, 16, v7
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v8, v14, 16, v8
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v9, v11, 16, v9
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v10, v15, 16, v10
; GFX11-FAKE16-NEXT:    s_clause 0x2
; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[1:4], off
; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
; GFX11-FAKE16-NEXT:    scratch_store_b64 v0, v[9:10], off offset:32
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <20 x i16> %a, splat (i16 3)
  %a2 = bitcast <20 x i16> %a1 to <40 x i8>
  br label %end

cmp.false:
  %a3 = bitcast <20 x i16> %a to <40 x i8>
  br label %end

end:
  %phi = phi <40 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <40 x i8> %phi
}

define inreg <40 x i8> @bitcast_v20i16_to_v40i8_scalar(<20 x i16> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v20i16_to_v40i8_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_lshr_b32 s62, s25, 16
; SI-NEXT:    s_lshr_b32 s4, s24, 16
; SI-NEXT:    s_lshr_b32 s63, s23, 16
; SI-NEXT:    s_lshr_b32 s6, s22, 16
; SI-NEXT:    s_lshr_b32 s72, s21, 16
; SI-NEXT:    s_lshr_b32 s8, s20, 16
; SI-NEXT:    s_lshr_b32 s73, s19, 16
; SI-NEXT:    s_lshr_b32 s10, s18, 16
; SI-NEXT:    s_lshr_b32 s74, s17, 16
; SI-NEXT:    s_lshr_b32 s12, s16, 16
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc0 .LBB49_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    s_and_b32 s5, s16, 0xffff
; SI-NEXT:    s_lshl_b32 s7, s12, 16
; SI-NEXT:    s_or_b32 s12, s5, s7
; SI-NEXT:    s_and_b32 s5, s17, 0xffff
; SI-NEXT:    s_lshl_b32 s7, s74, 16
; SI-NEXT:    s_or_b32 s13, s5, s7
; SI-NEXT:    s_and_b32 s5, s18, 0xffff
; SI-NEXT:    s_lshl_b32 s7, s10, 16
; SI-NEXT:    s_or_b32 s10, s5, s7
; SI-NEXT:    s_and_b32 s5, s19, 0xffff
; SI-NEXT:    s_lshl_b32 s7, s73, 16
; SI-NEXT:    s_or_b32 s11, s5, s7
; SI-NEXT:    s_and_b32 s5, s20, 0xffff
; SI-NEXT:    s_lshl_b32 s7, s8, 16
; SI-NEXT:    s_or_b32 s8, s5, s7
; SI-NEXT:    s_and_b32 s5, s21, 0xffff
; SI-NEXT:    s_lshl_b32 s7, s72, 16
; SI-NEXT:    s_or_b32 s9, s5, s7
; SI-NEXT:    s_and_b32 s5, s22, 0xffff
; SI-NEXT:    s_lshl_b32 s6, s6, 16
; SI-NEXT:    s_or_b32 s6, s5, s6
; SI-NEXT:    s_and_b32 s5, s23, 0xffff
; SI-NEXT:    s_lshl_b32 s7, s63, 16
; SI-NEXT:    s_lshr_b64 s[14:15], s[10:11], 24
; SI-NEXT:    s_or_b32 s7, s5, s7
; SI-NEXT:    s_and_b32 s5, s24, 0xffff
; SI-NEXT:    s_lshl_b32 s4, s4, 16
; SI-NEXT:    s_or_b32 s4, s5, s4
; SI-NEXT:    s_and_b32 s5, s25, 0xffff
; SI-NEXT:    s_lshl_b32 s15, s62, 16
; SI-NEXT:    s_lshr_b64 s[26:27], s[12:13], 24
; SI-NEXT:    s_lshr_b64 s[40:41], s[12:13], 16
; SI-NEXT:    s_lshr_b64 s[46:47], s[12:13], 8
; SI-NEXT:    s_lshr_b64 s[28:29], s[10:11], 16
; SI-NEXT:    s_lshr_b64 s[42:43], s[10:11], 8
; SI-NEXT:    s_lshr_b64 s[16:17], s[8:9], 24
; SI-NEXT:    s_lshr_b64 s[20:21], s[8:9], 16
; SI-NEXT:    s_lshr_b64 s[44:45], s[8:9], 8
; SI-NEXT:    s_lshr_b64 s[18:19], s[6:7], 24
; SI-NEXT:    s_or_b32 s5, s5, s15
; SI-NEXT:    s_lshr_b32 s47, s13, 8
; SI-NEXT:    s_lshr_b32 s43, s11, 8
; SI-NEXT:    s_lshr_b32 s29, s9, 8
; SI-NEXT:    s_lshr_b32 s21, s7, 8
; SI-NEXT:    s_lshr_b32 s17, s5, 8
; SI-NEXT:    s_bfe_u32 s45, s74, 0x80008
; SI-NEXT:    s_bfe_u32 s41, s73, 0x80008
; SI-NEXT:    s_bfe_u32 s27, s72, 0x80008
; SI-NEXT:    s_bfe_u32 s19, s63, 0x80008
; SI-NEXT:    s_bfe_u32 s15, s62, 0x80008
; SI-NEXT:    s_branch .LBB49_3
; SI-NEXT:  .LBB49_2: ; %cmp.true
; SI-NEXT:    s_add_i32 s24, s24, 3
; SI-NEXT:    s_and_b32 s5, s24, 0xffff
; SI-NEXT:    s_lshl_b32 s4, s4, 16
; SI-NEXT:    s_add_i32 s25, s25, 3
; SI-NEXT:    s_or_b32 s4, s4, s5
; SI-NEXT:    s_and_b32 s5, s25, 0xffff
; SI-NEXT:    s_lshl_b32 s7, s62, 16
; SI-NEXT:    s_add_i32 s22, s22, 3
; SI-NEXT:    s_or_b32 s5, s7, s5
; SI-NEXT:    s_and_b32 s7, s22, 0xffff
; SI-NEXT:    s_lshl_b32 s6, s6, 16
; SI-NEXT:    s_add_i32 s23, s23, 3
; SI-NEXT:    s_or_b32 s6, s6, s7
; SI-NEXT:    s_and_b32 s7, s23, 0xffff
; SI-NEXT:    s_lshl_b32 s9, s63, 16
; SI-NEXT:    s_add_i32 s20, s20, 3
; SI-NEXT:    s_or_b32 s7, s9, s7
; SI-NEXT:    s_and_b32 s9, s20, 0xffff
; SI-NEXT:    s_lshl_b32 s8, s8, 16
; SI-NEXT:    s_add_i32 s21, s21, 3
; SI-NEXT:    s_or_b32 s8, s8, s9
; SI-NEXT:    s_and_b32 s9, s21, 0xffff
; SI-NEXT:    s_lshl_b32 s11, s72, 16
; SI-NEXT:    s_add_i32 s18, s18, 3
; SI-NEXT:    s_or_b32 s9, s11, s9
; SI-NEXT:    s_and_b32 s11, s18, 0xffff
; SI-NEXT:    s_lshl_b32 s10, s10, 16
; SI-NEXT:    s_add_i32 s19, s19, 3
; SI-NEXT:    s_or_b32 s10, s10, s11
; SI-NEXT:    s_and_b32 s11, s19, 0xffff
; SI-NEXT:    s_lshl_b32 s13, s73, 16
; SI-NEXT:    s_add_i32 s16, s16, 3
; SI-NEXT:    s_or_b32 s11, s13, s11
; SI-NEXT:    s_and_b32 s13, s16, 0xffff
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_add_i32 s17, s17, 3
; SI-NEXT:    s_or_b32 s12, s12, s13
; SI-NEXT:    s_and_b32 s13, s17, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s74, 16
; SI-NEXT:    s_or_b32 s13, s14, s13
; SI-NEXT:    s_add_i32 s6, s6, 0x30000
; SI-NEXT:    s_add_i32 s7, s7, 0x30000
; SI-NEXT:    s_add_i32 s8, s8, 0x30000
; SI-NEXT:    s_add_i32 s9, s9, 0x30000
; SI-NEXT:    s_add_i32 s10, s10, 0x30000
; SI-NEXT:    s_add_i32 s11, s11, 0x30000
; SI-NEXT:    s_add_i32 s12, s12, 0x30000
; SI-NEXT:    s_add_i32 s13, s13, 0x30000
; SI-NEXT:    s_add_i32 s5, s5, 0x30000
; SI-NEXT:    s_lshr_b64 s[26:27], s[12:13], 24
; SI-NEXT:    s_lshr_b64 s[40:41], s[12:13], 16
; SI-NEXT:    s_lshr_b64 s[46:47], s[12:13], 8
; SI-NEXT:    s_lshr_b64 s[14:15], s[10:11], 24
; SI-NEXT:    s_lshr_b64 s[28:29], s[10:11], 16
; SI-NEXT:    s_lshr_b64 s[42:43], s[10:11], 8
; SI-NEXT:    s_lshr_b64 s[16:17], s[8:9], 24
; SI-NEXT:    s_lshr_b64 s[20:21], s[8:9], 16
; SI-NEXT:    s_lshr_b64 s[44:45], s[8:9], 8
; SI-NEXT:    s_lshr_b64 s[18:19], s[6:7], 24
; SI-NEXT:    s_add_i32 s4, s4, 0x30000
; SI-NEXT:    s_lshr_b32 s45, s13, 24
; SI-NEXT:    s_lshr_b32 s74, s13, 16
; SI-NEXT:    s_lshr_b32 s47, s13, 8
; SI-NEXT:    s_lshr_b32 s41, s11, 24
; SI-NEXT:    s_lshr_b32 s73, s11, 16
; SI-NEXT:    s_lshr_b32 s43, s11, 8
; SI-NEXT:    s_lshr_b32 s27, s9, 24
; SI-NEXT:    s_lshr_b32 s72, s9, 16
; SI-NEXT:    s_lshr_b32 s29, s9, 8
; SI-NEXT:    s_lshr_b32 s19, s7, 24
; SI-NEXT:    s_lshr_b32 s63, s7, 16
; SI-NEXT:    s_lshr_b32 s21, s7, 8
; SI-NEXT:    s_lshr_b32 s15, s5, 24
; SI-NEXT:    s_lshr_b32 s62, s5, 16
; SI-NEXT:    s_lshr_b32 s17, s5, 8
; SI-NEXT:  .LBB49_3: ; %end
; SI-NEXT:    s_lshr_b64 s[22:23], s[4:5], 24
; SI-NEXT:    s_lshl_b32 s23, s46, 8
; SI-NEXT:    s_and_b32 s12, s12, 0xff
; SI-NEXT:    s_lshr_b64 s[24:25], s[4:5], 16
; SI-NEXT:    s_or_b32 s12, s12, s23
; SI-NEXT:    s_and_b32 s23, s40, 0xff
; SI-NEXT:    s_lshl_b32 s25, s26, 24
; SI-NEXT:    s_lshl_b32 s23, s23, 16
; SI-NEXT:    s_or_b32 s23, s25, s23
; SI-NEXT:    s_and_b32 s12, s12, 0xffff
; SI-NEXT:    s_or_b32 s12, s12, s23
; SI-NEXT:    v_mov_b32_e32 v1, s12
; SI-NEXT:    s_and_b32 s12, s13, 0xff
; SI-NEXT:    s_lshl_b32 s13, s47, 8
; SI-NEXT:    s_or_b32 s12, s12, s13
; SI-NEXT:    s_and_b32 s13, s74, 0xff
; SI-NEXT:    s_lshl_b32 s13, s13, 16
; SI-NEXT:    s_lshl_b32 s23, s45, 24
; SI-NEXT:    s_or_b32 s13, s23, s13
; SI-NEXT:    s_and_b32 s12, s12, 0xffff
; SI-NEXT:    s_or_b32 s12, s12, s13
; SI-NEXT:    v_mov_b32_e32 v2, s12
; SI-NEXT:    s_lshl_b32 s12, s42, 8
; SI-NEXT:    s_and_b32 s10, s10, 0xff
; SI-NEXT:    s_or_b32 s10, s10, s12
; SI-NEXT:    s_and_b32 s12, s28, 0xff
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_lshl_b32 s13, s14, 24
; SI-NEXT:    s_and_b32 s10, s10, 0xffff
; SI-NEXT:    s_or_b32 s12, s13, s12
; SI-NEXT:    s_or_b32 s10, s10, s12
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen
; SI-NEXT:    buffer_store_dword v2, v0, s[0:3], 0 offen offset:4
; SI-NEXT:    s_waitcnt expcnt(1)
; SI-NEXT:    v_mov_b32_e32 v1, s10
; SI-NEXT:    s_and_b32 s10, s11, 0xff
; SI-NEXT:    s_lshl_b32 s11, s43, 8
; SI-NEXT:    s_or_b32 s10, s10, s11
; SI-NEXT:    s_and_b32 s11, s73, 0xff
; SI-NEXT:    s_lshl_b32 s11, s11, 16
; SI-NEXT:    s_lshl_b32 s12, s41, 24
; SI-NEXT:    s_and_b32 s10, s10, 0xffff
; SI-NEXT:    s_or_b32 s11, s12, s11
; SI-NEXT:    s_or_b32 s10, s10, s11
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_mov_b32_e32 v1, s10
; SI-NEXT:    s_and_b32 s8, s8, 0xff
; SI-NEXT:    s_lshl_b32 s10, s44, 8
; SI-NEXT:    s_or_b32 s8, s8, s10
; SI-NEXT:    s_and_b32 s10, s20, 0xff
; SI-NEXT:    s_lshl_b32 s10, s10, 16
; SI-NEXT:    s_lshl_b32 s11, s16, 24
; SI-NEXT:    s_and_b32 s8, s8, 0xffff
; SI-NEXT:    s_or_b32 s10, s11, s10
; SI-NEXT:    s_or_b32 s8, s8, s10
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_mov_b32_e32 v1, s8
; SI-NEXT:    s_and_b32 s8, s9, 0xff
; SI-NEXT:    s_lshl_b32 s9, s29, 8
; SI-NEXT:    s_or_b32 s8, s8, s9
; SI-NEXT:    s_and_b32 s9, s72, 0xff
; SI-NEXT:    s_lshl_b32 s9, s9, 16
; SI-NEXT:    s_lshl_b32 s10, s27, 24
; SI-NEXT:    s_and_b32 s8, s8, 0xffff
; SI-NEXT:    s_or_b32 s9, s10, s9
; SI-NEXT:    s_lshr_b64 s[60:61], s[6:7], 8
; SI-NEXT:    s_or_b32 s8, s8, s9
; SI-NEXT:    s_lshr_b64 s[58:59], s[6:7], 16
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_mov_b32_e32 v1, s8
; SI-NEXT:    s_and_b32 s6, s6, 0xff
; SI-NEXT:    s_lshl_b32 s8, s60, 8
; SI-NEXT:    s_or_b32 s6, s6, s8
; SI-NEXT:    s_and_b32 s8, s58, 0xff
; SI-NEXT:    s_lshl_b32 s8, s8, 16
; SI-NEXT:    s_lshl_b32 s9, s18, 24
; SI-NEXT:    s_and_b32 s6, s6, 0xffff
; SI-NEXT:    s_or_b32 s8, s9, s8
; SI-NEXT:    s_or_b32 s6, s6, s8
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_mov_b32_e32 v1, s6
; SI-NEXT:    s_and_b32 s6, s7, 0xff
; SI-NEXT:    s_lshl_b32 s7, s21, 8
; SI-NEXT:    s_or_b32 s6, s6, s7
; SI-NEXT:    s_and_b32 s7, s63, 0xff
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_lshl_b32 s8, s19, 24
; SI-NEXT:    s_and_b32 s6, s6, 0xffff
; SI-NEXT:    s_or_b32 s7, s8, s7
; SI-NEXT:    s_lshr_b64 s[56:57], s[4:5], 8
; SI-NEXT:    s_or_b32 s6, s6, s7
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_mov_b32_e32 v1, s6
; SI-NEXT:    s_and_b32 s4, s4, 0xff
; SI-NEXT:    s_lshl_b32 s6, s56, 8
; SI-NEXT:    s_or_b32 s4, s4, s6
; SI-NEXT:    s_and_b32 s6, s24, 0xff
; SI-NEXT:    s_lshl_b32 s6, s6, 16
; SI-NEXT:    s_lshl_b32 s7, s22, 24
; SI-NEXT:    s_and_b32 s4, s4, 0xffff
; SI-NEXT:    s_or_b32 s6, s7, s6
; SI-NEXT:    s_or_b32 s4, s4, s6
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_mov_b32_e32 v1, s4
; SI-NEXT:    s_and_b32 s4, s5, 0xff
; SI-NEXT:    s_lshl_b32 s5, s17, 8
; SI-NEXT:    s_or_b32 s4, s4, s5
; SI-NEXT:    s_and_b32 s5, s62, 0xff
; SI-NEXT:    s_lshl_b32 s5, s5, 16
; SI-NEXT:    s_lshl_b32 s6, s15, 24
; SI-NEXT:    s_and_b32 s4, s4, 0xffff
; SI-NEXT:    s_or_b32 s5, s6, s5
; SI-NEXT:    s_or_b32 s4, s4, s5
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_mov_b32_e32 v1, s4
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v20i16_to_v40i8_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc0 .LBB49_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    s_lshr_b32 s14, s25, 24
; VI-NEXT:    s_lshr_b32 s15, s25, 16
; VI-NEXT:    s_lshr_b32 s26, s25, 8
; VI-NEXT:    s_lshr_b32 s27, s24, 16
; VI-NEXT:    s_lshr_b32 s28, s24, 8
; VI-NEXT:    s_lshr_b32 s29, s23, 24
; VI-NEXT:    s_lshr_b32 s40, s23, 16
; VI-NEXT:    s_lshr_b32 s41, s23, 8
; VI-NEXT:    s_lshr_b32 s42, s22, 16
; VI-NEXT:    s_lshr_b32 s43, s22, 8
; VI-NEXT:    s_lshr_b32 s44, s21, 24
; VI-NEXT:    s_lshr_b32 s45, s21, 16
; VI-NEXT:    s_lshr_b32 s46, s21, 8
; VI-NEXT:    s_lshr_b32 s47, s20, 16
; VI-NEXT:    s_lshr_b32 s56, s20, 8
; VI-NEXT:    s_lshr_b32 s57, s19, 24
; VI-NEXT:    s_lshr_b32 s58, s19, 16
; VI-NEXT:    s_lshr_b32 s59, s19, 8
; VI-NEXT:    s_lshr_b32 s60, s18, 16
; VI-NEXT:    s_lshr_b32 s61, s18, 8
; VI-NEXT:    s_lshr_b32 s62, s17, 24
; VI-NEXT:    s_lshr_b32 s63, s17, 16
; VI-NEXT:    s_lshr_b32 s72, s17, 8
; VI-NEXT:    s_lshr_b32 s73, s16, 16
; VI-NEXT:    s_lshr_b32 s74, s16, 8
; VI-NEXT:    s_lshr_b64 s[4:5], s[24:25], 24
; VI-NEXT:    s_lshr_b64 s[6:7], s[22:23], 24
; VI-NEXT:    s_lshr_b64 s[8:9], s[20:21], 24
; VI-NEXT:    s_lshr_b64 s[10:11], s[18:19], 24
; VI-NEXT:    s_lshr_b64 s[12:13], s[16:17], 24
; VI-NEXT:    s_branch .LBB49_3
; VI-NEXT:  .LBB49_2: ; %cmp.true
; VI-NEXT:    s_add_i32 s5, s17, 3
; VI-NEXT:    s_and_b32 s4, s17, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s16, 3
; VI-NEXT:    s_add_i32 s17, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s16, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s19, 3
; VI-NEXT:    s_add_i32 s16, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s19, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s18, 3
; VI-NEXT:    s_add_i32 s19, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s18, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s21, 3
; VI-NEXT:    s_add_i32 s18, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s21, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s20, 3
; VI-NEXT:    s_add_i32 s21, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s20, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s23, 3
; VI-NEXT:    s_add_i32 s20, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s23, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s22, 3
; VI-NEXT:    s_add_i32 s23, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s22, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s25, 3
; VI-NEXT:    s_add_i32 s22, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s25, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s24, 3
; VI-NEXT:    s_add_i32 s25, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s24, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s24, s4, 0x30000
; VI-NEXT:    s_lshr_b64 s[4:5], s[24:25], 24
; VI-NEXT:    s_lshr_b64 s[6:7], s[22:23], 24
; VI-NEXT:    s_lshr_b64 s[8:9], s[20:21], 24
; VI-NEXT:    s_lshr_b64 s[10:11], s[18:19], 24
; VI-NEXT:    s_lshr_b64 s[12:13], s[16:17], 24
; VI-NEXT:    s_lshr_b32 s14, s25, 24
; VI-NEXT:    s_lshr_b32 s15, s25, 16
; VI-NEXT:    s_lshr_b32 s26, s25, 8
; VI-NEXT:    s_lshr_b32 s27, s24, 16
; VI-NEXT:    s_lshr_b32 s28, s24, 8
; VI-NEXT:    s_lshr_b32 s29, s23, 24
; VI-NEXT:    s_lshr_b32 s40, s23, 16
; VI-NEXT:    s_lshr_b32 s41, s23, 8
; VI-NEXT:    s_lshr_b32 s42, s22, 16
; VI-NEXT:    s_lshr_b32 s43, s22, 8
; VI-NEXT:    s_lshr_b32 s44, s21, 24
; VI-NEXT:    s_lshr_b32 s45, s21, 16
; VI-NEXT:    s_lshr_b32 s46, s21, 8
; VI-NEXT:    s_lshr_b32 s47, s20, 16
; VI-NEXT:    s_lshr_b32 s56, s20, 8
; VI-NEXT:    s_lshr_b32 s57, s19, 24
; VI-NEXT:    s_lshr_b32 s58, s19, 16
; VI-NEXT:    s_lshr_b32 s59, s19, 8
; VI-NEXT:    s_lshr_b32 s60, s18, 16
; VI-NEXT:    s_lshr_b32 s61, s18, 8
; VI-NEXT:    s_lshr_b32 s62, s17, 24
; VI-NEXT:    s_lshr_b32 s63, s17, 16
; VI-NEXT:    s_lshr_b32 s72, s17, 8
; VI-NEXT:    s_lshr_b32 s73, s16, 16
; VI-NEXT:    s_lshr_b32 s74, s16, 8
; VI-NEXT:  .LBB49_3: ; %end
; VI-NEXT:    v_mov_b32_e32 v2, 0xc0c0004
; VI-NEXT:    v_mov_b32_e32 v3, s12
; VI-NEXT:    v_mov_b32_e32 v1, s74
; VI-NEXT:    v_perm_b32 v3, s73, v3, v2
; VI-NEXT:    v_perm_b32 v1, s16, v1, v2
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_e32 v1, v1, v3
; VI-NEXT:    v_mov_b32_e32 v3, s62
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT:    v_mov_b32_e32 v1, s72
; VI-NEXT:    v_perm_b32 v3, s63, v3, v2
; VI-NEXT:    v_perm_b32 v1, s17, v1, v2
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_e32 v1, v1, v3
; VI-NEXT:    v_mov_b32_e32 v3, s10
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
; VI-NEXT:    v_mov_b32_e32 v1, s61
; VI-NEXT:    v_perm_b32 v3, s60, v3, v2
; VI-NEXT:    v_perm_b32 v1, s18, v1, v2
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_e32 v1, v1, v3
; VI-NEXT:    v_mov_b32_e32 v3, s57
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; VI-NEXT:    v_mov_b32_e32 v1, s59
; VI-NEXT:    v_perm_b32 v3, s58, v3, v2
; VI-NEXT:    v_perm_b32 v1, s19, v1, v2
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_e32 v1, v1, v3
; VI-NEXT:    v_mov_b32_e32 v3, s8
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; VI-NEXT:    v_mov_b32_e32 v1, s56
; VI-NEXT:    v_perm_b32 v3, s47, v3, v2
; VI-NEXT:    v_perm_b32 v1, s20, v1, v2
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_e32 v1, v1, v3
; VI-NEXT:    v_mov_b32_e32 v3, s44
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; VI-NEXT:    v_mov_b32_e32 v1, s46
; VI-NEXT:    v_perm_b32 v3, s45, v3, v2
; VI-NEXT:    v_perm_b32 v1, s21, v1, v2
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_e32 v1, v1, v3
; VI-NEXT:    v_mov_b32_e32 v3, s6
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; VI-NEXT:    v_mov_b32_e32 v1, s43
; VI-NEXT:    v_perm_b32 v3, s42, v3, v2
; VI-NEXT:    v_perm_b32 v1, s22, v1, v2
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_e32 v1, v1, v3
; VI-NEXT:    v_mov_b32_e32 v3, s29
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; VI-NEXT:    v_mov_b32_e32 v1, s41
; VI-NEXT:    v_perm_b32 v3, s40, v3, v2
; VI-NEXT:    v_perm_b32 v1, s23, v1, v2
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_e32 v1, v1, v3
; VI-NEXT:    v_mov_b32_e32 v3, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; VI-NEXT:    v_mov_b32_e32 v1, s28
; VI-NEXT:    v_perm_b32 v3, s27, v3, v2
; VI-NEXT:    v_perm_b32 v1, s24, v1, v2
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_e32 v1, v1, v3
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; VI-NEXT:    v_mov_b32_e32 v1, s26
; VI-NEXT:    v_mov_b32_e32 v3, s14
; VI-NEXT:    v_perm_b32 v1, s25, v1, v2
; VI-NEXT:    v_perm_b32 v2, s15, v3, v2
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v20i16_to_v40i8_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc0 .LBB49_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    s_lshr_b32 s14, s25, 24
; GFX9-NEXT:    s_lshr_b32 s15, s25, 16
; GFX9-NEXT:    s_lshr_b32 s26, s25, 8
; GFX9-NEXT:    s_lshr_b32 s27, s24, 16
; GFX9-NEXT:    s_lshr_b32 s28, s24, 8
; GFX9-NEXT:    s_lshr_b32 s29, s23, 24
; GFX9-NEXT:    s_lshr_b32 s40, s23, 16
; GFX9-NEXT:    s_lshr_b32 s41, s23, 8
; GFX9-NEXT:    s_lshr_b32 s42, s22, 16
; GFX9-NEXT:    s_lshr_b32 s43, s22, 8
; GFX9-NEXT:    s_lshr_b32 s44, s21, 24
; GFX9-NEXT:    s_lshr_b32 s45, s21, 16
; GFX9-NEXT:    s_lshr_b32 s46, s21, 8
; GFX9-NEXT:    s_lshr_b32 s47, s20, 16
; GFX9-NEXT:    s_lshr_b32 s56, s20, 8
; GFX9-NEXT:    s_lshr_b32 s57, s19, 24
; GFX9-NEXT:    s_lshr_b32 s58, s19, 16
; GFX9-NEXT:    s_lshr_b32 s59, s19, 8
; GFX9-NEXT:    s_lshr_b32 s60, s18, 16
; GFX9-NEXT:    s_lshr_b32 s61, s18, 8
; GFX9-NEXT:    s_lshr_b32 s62, s17, 24
; GFX9-NEXT:    s_lshr_b32 s63, s17, 16
; GFX9-NEXT:    s_lshr_b32 s72, s17, 8
; GFX9-NEXT:    s_lshr_b32 s73, s16, 16
; GFX9-NEXT:    s_lshr_b32 s74, s16, 8
; GFX9-NEXT:    s_lshr_b64 s[4:5], s[24:25], 24
; GFX9-NEXT:    s_lshr_b64 s[6:7], s[22:23], 24
; GFX9-NEXT:    s_lshr_b64 s[8:9], s[20:21], 24
; GFX9-NEXT:    s_lshr_b64 s[10:11], s[18:19], 24
; GFX9-NEXT:    s_lshr_b64 s[12:13], s[16:17], 24
; GFX9-NEXT:    v_mov_b32_e32 v9, s16
; GFX9-NEXT:    v_mov_b32_e32 v10, s17
; GFX9-NEXT:    v_mov_b32_e32 v7, s18
; GFX9-NEXT:    v_mov_b32_e32 v8, s19
; GFX9-NEXT:    v_mov_b32_e32 v5, s20
; GFX9-NEXT:    v_mov_b32_e32 v6, s21
; GFX9-NEXT:    v_mov_b32_e32 v3, s22
; GFX9-NEXT:    v_mov_b32_e32 v4, s23
; GFX9-NEXT:    v_mov_b32_e32 v1, s24
; GFX9-NEXT:    v_mov_b32_e32 v2, s25
; GFX9-NEXT:    v_mov_b32_e32 v16, s74
; GFX9-NEXT:    v_mov_b32_e32 v48, s73
; GFX9-NEXT:    v_mov_b32_e32 v39, s72
; GFX9-NEXT:    v_mov_b32_e32 v37, s63
; GFX9-NEXT:    v_mov_b32_e32 v38, s62
; GFX9-NEXT:    v_mov_b32_e32 v36, s61
; GFX9-NEXT:    v_mov_b32_e32 v35, s60
; GFX9-NEXT:    v_mov_b32_e32 v34, s59
; GFX9-NEXT:    v_mov_b32_e32 v32, s58
; GFX9-NEXT:    v_mov_b32_e32 v33, s57
; GFX9-NEXT:    v_mov_b32_e32 v31, s56
; GFX9-NEXT:    v_mov_b32_e32 v30, s47
; GFX9-NEXT:    v_mov_b32_e32 v29, s46
; GFX9-NEXT:    v_mov_b32_e32 v27, s45
; GFX9-NEXT:    v_mov_b32_e32 v28, s44
; GFX9-NEXT:    v_mov_b32_e32 v26, s43
; GFX9-NEXT:    v_mov_b32_e32 v25, s42
; GFX9-NEXT:    v_mov_b32_e32 v24, s41
; GFX9-NEXT:    v_mov_b32_e32 v22, s40
; GFX9-NEXT:    v_mov_b32_e32 v23, s29
; GFX9-NEXT:    v_mov_b32_e32 v21, s28
; GFX9-NEXT:    v_mov_b32_e32 v20, s27
; GFX9-NEXT:    v_mov_b32_e32 v19, s26
; GFX9-NEXT:    v_mov_b32_e32 v17, s15
; GFX9-NEXT:    v_mov_b32_e32 v18, s14
; GFX9-NEXT:    v_mov_b32_e32 v11, s4
; GFX9-NEXT:    v_mov_b32_e32 v12, s6
; GFX9-NEXT:    v_mov_b32_e32 v13, s8
; GFX9-NEXT:    v_mov_b32_e32 v14, s10
; GFX9-NEXT:    v_mov_b32_e32 v15, s12
; GFX9-NEXT:    s_branch .LBB49_3
; GFX9-NEXT:  .LBB49_2: ; %cmp.true
; GFX9-NEXT:    v_pk_add_u16 v2, s25, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v1, s24, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v4, s23, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v3, s22, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_lshrrev_b64 v[11:12], 24, v[1:2]
; GFX9-NEXT:    v_pk_add_u16 v6, s21, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v5, s20, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_lshrrev_b64 v[12:13], 24, v[3:4]
; GFX9-NEXT:    v_pk_add_u16 v8, s19, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v7, s18, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX9-NEXT:    v_pk_add_u16 v10, s17, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v9, s16, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_lshrrev_b64 v[14:15], 24, v[7:8]
; GFX9-NEXT:    v_lshrrev_b64 v[15:16], 24, v[9:10]
; GFX9-NEXT:    v_lshrrev_b32_e32 v18, 24, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v17, 16, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v19, 8, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v20, 16, v1
; GFX9-NEXT:    v_lshrrev_b32_e32 v21, 8, v1
; GFX9-NEXT:    v_lshrrev_b32_e32 v23, 24, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v22, 16, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v24, 8, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v25, 16, v3
; GFX9-NEXT:    v_lshrrev_b32_e32 v26, 8, v3
; GFX9-NEXT:    v_lshrrev_b32_e32 v28, 24, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v27, 16, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; GFX9-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; GFX9-NEXT:    v_lshrrev_b32_e32 v33, 24, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v32, 16, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v34, 8, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v35, 16, v7
; GFX9-NEXT:    v_lshrrev_b32_e32 v36, 8, v7
; GFX9-NEXT:    v_lshrrev_b32_e32 v38, 24, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v37, 16, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v39, 8, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v48, 16, v9
; GFX9-NEXT:    v_lshrrev_b32_e32 v16, 8, v9
; GFX9-NEXT:  .LBB49_3: ; %end
; GFX9-NEXT:    s_mov_b32 s4, 0xc0c0004
; GFX9-NEXT:    v_perm_b32 v15, v48, v15, s4
; GFX9-NEXT:    v_perm_b32 v9, v9, v16, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
; GFX9-NEXT:    v_or_b32_e32 v9, v9, v15
; GFX9-NEXT:    buffer_store_dword v9, v0, s[0:3], 0 offen
; GFX9-NEXT:    v_perm_b32 v9, v10, v39, s4
; GFX9-NEXT:    v_perm_b32 v10, v37, v38, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; GFX9-NEXT:    v_or_b32_e32 v9, v9, v10
; GFX9-NEXT:    buffer_store_dword v9, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT:    v_perm_b32 v9, v35, v14, s4
; GFX9-NEXT:    v_perm_b32 v7, v7, v36, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; GFX9-NEXT:    v_or_b32_e32 v7, v7, v9
; GFX9-NEXT:    buffer_store_dword v7, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT:    v_perm_b32 v7, v8, v34, s4
; GFX9-NEXT:    v_perm_b32 v8, v32, v33, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; GFX9-NEXT:    v_or_b32_e32 v7, v7, v8
; GFX9-NEXT:    buffer_store_dword v7, v0, s[0:3], 0 offen offset:12
; GFX9-NEXT:    v_perm_b32 v7, v30, v13, s4
; GFX9-NEXT:    v_perm_b32 v5, v5, v31, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; GFX9-NEXT:    v_or_b32_e32 v5, v5, v7
; GFX9-NEXT:    buffer_store_dword v5, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT:    v_perm_b32 v5, v6, v29, s4
; GFX9-NEXT:    v_perm_b32 v6, v27, v28, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; GFX9-NEXT:    v_or_b32_e32 v5, v5, v6
; GFX9-NEXT:    buffer_store_dword v5, v0, s[0:3], 0 offen offset:20
; GFX9-NEXT:    v_perm_b32 v5, v25, v12, s4
; GFX9-NEXT:    v_perm_b32 v3, v3, v26, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; GFX9-NEXT:    v_or_b32_e32 v3, v3, v5
; GFX9-NEXT:    buffer_store_dword v3, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT:    v_perm_b32 v3, v4, v24, s4
; GFX9-NEXT:    v_perm_b32 v4, v22, v23, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; GFX9-NEXT:    v_or_b32_e32 v3, v3, v4
; GFX9-NEXT:    buffer_store_dword v3, v0, s[0:3], 0 offen offset:28
; GFX9-NEXT:    v_perm_b32 v3, v20, v11, s4
; GFX9-NEXT:    v_perm_b32 v1, v1, v21, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT:    v_perm_b32 v1, v2, v19, s4
; GFX9-NEXT:    v_perm_b32 v2, v17, v18, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v2
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v20i16_to_v40i8_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc0 .LBB49_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-NEXT:    s_lshr_b32 s14, s21, 24
; GFX11-NEXT:    s_lshr_b32 s15, s21, 16
; GFX11-NEXT:    s_lshr_b32 s22, s21, 8
; GFX11-NEXT:    s_lshr_b32 s23, s20, 16
; GFX11-NEXT:    s_lshr_b32 s24, s20, 8
; GFX11-NEXT:    s_lshr_b32 s25, s19, 24
; GFX11-NEXT:    s_lshr_b32 s26, s19, 16
; GFX11-NEXT:    s_lshr_b32 s27, s19, 8
; GFX11-NEXT:    s_lshr_b32 s28, s18, 16
; GFX11-NEXT:    s_lshr_b32 s29, s18, 8
; GFX11-NEXT:    s_lshr_b32 s40, s17, 24
; GFX11-NEXT:    s_lshr_b32 s41, s17, 16
; GFX11-NEXT:    s_lshr_b32 s42, s17, 8
; GFX11-NEXT:    s_lshr_b32 s43, s16, 16
; GFX11-NEXT:    s_lshr_b32 s44, s16, 8
; GFX11-NEXT:    s_lshr_b32 s45, s3, 24
; GFX11-NEXT:    s_lshr_b32 s46, s3, 16
; GFX11-NEXT:    s_lshr_b32 s47, s3, 8
; GFX11-NEXT:    s_lshr_b32 s56, s2, 16
; GFX11-NEXT:    s_lshr_b32 s57, s2, 8
; GFX11-NEXT:    s_lshr_b32 s58, s1, 24
; GFX11-NEXT:    s_lshr_b32 s59, s1, 16
; GFX11-NEXT:    s_lshr_b32 s60, s1, 8
; GFX11-NEXT:    s_lshr_b32 s61, s0, 16
; GFX11-NEXT:    s_lshr_b32 s62, s0, 8
; GFX11-NEXT:    s_lshr_b64 s[4:5], s[20:21], 24
; GFX11-NEXT:    s_lshr_b64 s[6:7], s[18:19], 24
; GFX11-NEXT:    s_lshr_b64 s[8:9], s[16:17], 24
; GFX11-NEXT:    s_lshr_b64 s[10:11], s[2:3], 24
; GFX11-NEXT:    s_lshr_b64 s[12:13], s[0:1], 24
; GFX11-NEXT:    v_dual_mov_b32 v9, s0 :: v_dual_mov_b32 v10, s1
; GFX11-NEXT:    v_dual_mov_b32 v7, s2 :: v_dual_mov_b32 v8, s3
; GFX11-NEXT:    v_dual_mov_b32 v5, s16 :: v_dual_mov_b32 v6, s17
; GFX11-NEXT:    v_dual_mov_b32 v3, s18 :: v_dual_mov_b32 v4, s19
; GFX11-NEXT:    v_dual_mov_b32 v1, s20 :: v_dual_mov_b32 v2, s21
; GFX11-NEXT:    v_dual_mov_b32 v39, s62 :: v_dual_mov_b32 v48, s61
; GFX11-NEXT:    v_dual_mov_b32 v38, s60 :: v_dual_mov_b32 v37, s58
; GFX11-NEXT:    v_dual_mov_b32 v36, s59 :: v_dual_mov_b32 v35, s57
; GFX11-NEXT:    v_dual_mov_b32 v34, s56 :: v_dual_mov_b32 v33, s45
; GFX11-NEXT:    v_dual_mov_b32 v30, s47 :: v_dual_mov_b32 v29, s44
; GFX11-NEXT:    v_dual_mov_b32 v32, s46 :: v_dual_mov_b32 v31, s43
; GFX11-NEXT:    v_dual_mov_b32 v25, s42 :: v_dual_mov_b32 v28, s40
; GFX11-NEXT:    v_dual_mov_b32 v27, s41 :: v_dual_mov_b32 v24, s29
; GFX11-NEXT:    v_dual_mov_b32 v26, s28 :: v_dual_mov_b32 v23, s25
; GFX11-NEXT:    v_dual_mov_b32 v20, s27 :: v_dual_mov_b32 v17, s24
; GFX11-NEXT:    v_dual_mov_b32 v22, s26 :: v_dual_mov_b32 v21, s23
; GFX11-NEXT:    v_dual_mov_b32 v16, s22 :: v_dual_mov_b32 v19, s14
; GFX11-NEXT:    v_dual_mov_b32 v18, s15 :: v_dual_mov_b32 v11, s4
; GFX11-NEXT:    v_dual_mov_b32 v12, s6 :: v_dual_mov_b32 v13, s8
; GFX11-NEXT:    v_dual_mov_b32 v14, s10 :: v_dual_mov_b32 v15, s12
; GFX11-NEXT:    s_branch .LBB49_3
; GFX11-NEXT:  .LBB49_2: ; %cmp.true
; GFX11-NEXT:    v_pk_add_u16 v2, s21, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v1, s20, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v4, s19, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v3, s18, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v6, s17, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v5, s16, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v8, s3, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v7, s2, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v10, s1, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v9, s0, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[1:2]
; GFX11-NEXT:    v_lshrrev_b64 v[12:13], 24, v[3:4]
; GFX11-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX11-NEXT:    v_lshrrev_b64 v[14:15], 24, v[7:8]
; GFX11-NEXT:    v_lshrrev_b64 v[15:16], 24, v[9:10]
; GFX11-NEXT:    v_lshrrev_b32_e32 v19, 24, v2
; GFX11-NEXT:    v_lshrrev_b32_e32 v18, 16, v2
; GFX11-NEXT:    v_lshrrev_b32_e32 v16, 8, v2
; GFX11-NEXT:    v_lshrrev_b32_e32 v21, 16, v1
; GFX11-NEXT:    v_lshrrev_b32_e32 v17, 8, v1
; GFX11-NEXT:    v_lshrrev_b32_e32 v23, 24, v4
; GFX11-NEXT:    v_lshrrev_b32_e32 v22, 16, v4
; GFX11-NEXT:    v_lshrrev_b32_e32 v20, 8, v4
; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 16, v3
; GFX11-NEXT:    v_lshrrev_b32_e32 v24, 8, v3
; GFX11-NEXT:    v_lshrrev_b32_e32 v28, 24, v6
; GFX11-NEXT:    v_lshrrev_b32_e32 v27, 16, v6
; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 8, v6
; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 16, v5
; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 8, v5
; GFX11-NEXT:    v_lshrrev_b32_e32 v33, 24, v8
; GFX11-NEXT:    v_lshrrev_b32_e32 v32, 16, v8
; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 8, v8
; GFX11-NEXT:    v_lshrrev_b32_e32 v34, 16, v7
; GFX11-NEXT:    v_lshrrev_b32_e32 v35, 8, v7
; GFX11-NEXT:    v_lshrrev_b32_e32 v37, 24, v10
; GFX11-NEXT:    v_lshrrev_b32_e32 v36, 16, v10
; GFX11-NEXT:    v_lshrrev_b32_e32 v38, 8, v10
; GFX11-NEXT:    v_lshrrev_b32_e32 v48, 16, v9
; GFX11-NEXT:    v_lshrrev_b32_e32 v39, 8, v9
; GFX11-NEXT:  .LBB49_3: ; %end
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT:    v_perm_b32 v15, v48, v15, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v9, v9, v39, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v36, v36, v37, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v35, v7, v35, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v14, v34, v14, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v15
; GFX11-NEXT:    v_perm_b32 v15, v32, v33, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v13, v31, v13, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v10, v10, v38, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v31, 16, v36
; GFX11-NEXT:    v_or_b32_e32 v7, v9, v7
; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v14
; GFX11-NEXT:    v_perm_b32 v14, v8, v30, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
; GFX11-NEXT:    v_perm_b32 v5, v5, v29, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
; GFX11-NEXT:    v_or_b32_e32 v8, v10, v31
; GFX11-NEXT:    v_perm_b32 v27, v27, v28, 0xc0c0004
; GFX11-NEXT:    v_or_b32_e32 v10, v14, v15
; GFX11-NEXT:    v_perm_b32 v14, v22, v23, 0xc0c0004
; GFX11-NEXT:    v_or_b32_e32 v13, v5, v13
; GFX11-NEXT:    v_perm_b32 v5, v26, v12, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v11, v21, v11, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v15, v18, v19, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v6, v6, v25, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v27
; GFX11-NEXT:    v_perm_b32 v3, v3, v24, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; GFX11-NEXT:    v_perm_b32 v4, v4, v20, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v14
; GFX11-NEXT:    v_perm_b32 v1, v1, v17, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; GFX11-NEXT:    v_perm_b32 v2, v2, v16, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v17, 16, v15
; GFX11-NEXT:    v_or_b32_e32 v9, v35, v9
; GFX11-NEXT:    v_or_b32_e32 v14, v6, v12
; GFX11-NEXT:    v_or_b32_e32 v15, v3, v5
; GFX11-NEXT:    v_or_b32_e32 v16, v4, v18
; GFX11-NEXT:    v_or_b32_e32 v1, v1, v11
; GFX11-NEXT:    v_or_b32_e32 v2, v2, v17
; GFX11-NEXT:    s_clause 0x2
; GFX11-NEXT:    scratch_store_b128 v0, v[7:10], off
; GFX11-NEXT:    scratch_store_b128 v0, v[13:16], off offset:16
; GFX11-NEXT:    scratch_store_b64 v0, v[1:2], off offset:32
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <20 x i16> %a, splat (i16 3)
  %a2 = bitcast <20 x i16> %a1 to <40 x i8>
  br label %end

cmp.false:
  %a3 = bitcast <20 x i16> %a to <40 x i8>
  br label %end

end:
  %phi = phi <40 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <40 x i8> %phi
}

define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v40i8_to_v20i16:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    buffer_store_dword v40, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v41, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v42, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v43, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v44, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v45, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v46, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v47, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v56, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v57, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v58, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v59, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; SI-NEXT:    buffer_load_dword v31, off, s[0:3], s32
; SI-NEXT:    buffer_load_dword v37, off, s[0:3], s32 offset:36
; SI-NEXT:    buffer_load_dword v38, off, s[0:3], s32 offset:32
; SI-NEXT:    buffer_load_dword v55, off, s[0:3], s32 offset:28
; SI-NEXT:    buffer_load_dword v39, off, s[0:3], s32 offset:24
; SI-NEXT:    buffer_load_dword v43, off, s[0:3], s32 offset:20
; SI-NEXT:    buffer_load_dword v48, off, s[0:3], s32 offset:16
; SI-NEXT:    buffer_load_dword v42, off, s[0:3], s32 offset:12
; SI-NEXT:    buffer_load_dword v49, off, s[0:3], s32 offset:8
; SI-NEXT:    buffer_load_dword v52, off, s[0:3], s32 offset:4
; SI-NEXT:    v_lshlrev_b32_e32 v33, 8, v5
; SI-NEXT:    v_lshlrev_b32_e32 v32, 24, v7
; SI-NEXT:    v_lshlrev_b32_e32 v34, 24, v3
; SI-NEXT:    v_lshlrev_b32_e32 v50, 8, v13
; SI-NEXT:    v_lshlrev_b32_e32 v36, 24, v15
; SI-NEXT:    v_lshlrev_b32_e32 v51, 24, v11
; SI-NEXT:    v_lshlrev_b32_e32 v40, 8, v21
; SI-NEXT:    v_lshlrev_b32_e32 v53, 24, v23
; SI-NEXT:    v_lshlrev_b32_e32 v41, 24, v19
; SI-NEXT:    s_waitcnt expcnt(6)
; SI-NEXT:    v_lshlrev_b32_e32 v45, 8, v29
; SI-NEXT:    s_waitcnt expcnt(5)
; SI-NEXT:    v_lshlrev_b32_e32 v46, 24, v27
; SI-NEXT:    v_lshlrev_b32_e32 v29, 8, v1
; SI-NEXT:    v_lshlrev_b32_e32 v35, 8, v9
; SI-NEXT:    v_lshlrev_b32_e32 v54, 8, v17
; SI-NEXT:    v_lshlrev_b32_e32 v44, 8, v25
; SI-NEXT:    ; implicit-def: $vgpr27
; SI-NEXT:    ; implicit-def: $vgpr17
; SI-NEXT:    ; implicit-def: $vgpr1
; SI-NEXT:    ; implicit-def: $vgpr21
; SI-NEXT:    ; implicit-def: $vgpr19
; SI-NEXT:    ; implicit-def: $vgpr3
; SI-NEXT:    ; implicit-def: $vgpr15
; SI-NEXT:    ; implicit-def: $vgpr23
; SI-NEXT:    ; implicit-def: $vgpr5
; SI-NEXT:    ; implicit-def: $vgpr13
; SI-NEXT:    ; implicit-def: $vgpr25
; SI-NEXT:    ; implicit-def: $vgpr7
; SI-NEXT:    ; implicit-def: $vgpr11
; SI-NEXT:    ; implicit-def: $vgpr9
; SI-NEXT:    s_waitcnt vmcnt(9) expcnt(4)
; SI-NEXT:    v_lshlrev_b32_e32 v47, 24, v31
; SI-NEXT:    s_waitcnt vmcnt(8)
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v37
; SI-NEXT:    s_waitcnt vmcnt(7) expcnt(3)
; SI-NEXT:    v_lshlrev_b32_e32 v56, 24, v38
; SI-NEXT:    ; implicit-def: $vgpr37
; SI-NEXT:    ; implicit-def: $vgpr38
; SI-NEXT:    ; implicit-def: $vgpr31
; SI-NEXT:    s_waitcnt vmcnt(5) expcnt(1)
; SI-NEXT:    v_lshlrev_b32_e32 v58, 8, v39
; SI-NEXT:    ; implicit-def: $vgpr39
; SI-NEXT:    s_waitcnt vmcnt(3) expcnt(0)
; SI-NEXT:    v_lshlrev_b32_e32 v59, 24, v48
; SI-NEXT:    ; implicit-def: $vgpr48
; SI-NEXT:    s_waitcnt vmcnt(1)
; SI-NEXT:    v_lshlrev_b32_e32 v57, 8, v49
; SI-NEXT:    ; implicit-def: $vgpr49
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB50_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v2
; SI-NEXT:    v_and_b32_e32 v0, 0xff, v0
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_and_b32_e32 v5, 0xff, v14
; SI-NEXT:    v_or_b32_e32 v0, v0, v29
; SI-NEXT:    v_or_b32_e32 v2, v34, v2
; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v6
; SI-NEXT:    v_or_b32_e32 v6, v36, v5
; SI-NEXT:    v_and_b32_e32 v5, 0xff, v10
; SI-NEXT:    v_or_b32_e32 v27, v0, v2
; SI-NEXT:    v_and_b32_e32 v0, 0xff, v8
; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT:    v_and_b32_e32 v7, 0xff, v22
; SI-NEXT:    v_or_b32_e32 v0, v0, v35
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_or_b32_e32 v10, v51, v5
; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT:    v_and_b32_e32 v15, 0xff, v55
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v4
; SI-NEXT:    v_or_b32_e32 v4, v32, v3
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v12
; SI-NEXT:    v_or_b32_e32 v12, v53, v7
; SI-NEXT:    v_and_b32_e32 v7, 0xff, v18
; SI-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT:    v_or_b32_e32 v21, v0, v10
; SI-NEXT:    v_and_b32_e32 v0, 0xff, v16
; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT:    v_and_b32_e32 v9, 0xff, v30
; SI-NEXT:    v_or_b32_e32 v18, v56, v15
; SI-NEXT:    v_and_b32_e32 v15, 0xff, v42
; SI-NEXT:    v_or_b32_e32 v0, v0, v54
; SI-NEXT:    v_or_b32_e32 v11, v41, v7
; SI-NEXT:    v_and_b32_e32 v7, 0xff, v28
; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_and_b32_e32 v5, 0xff, v20
; SI-NEXT:    v_or_b32_e32 v7, v7, v45
; SI-NEXT:    v_or_b32_e32 v14, v47, v9
; SI-NEXT:    v_and_b32_e32 v9, 0xff, v26
; SI-NEXT:    v_or_b32_e32 v20, v59, v15
; SI-NEXT:    v_or_b32_e32 v15, v0, v11
; SI-NEXT:    v_and_b32_e32 v0, 0xff, v24
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT:    v_or_b32_e32 v0, v0, v44
; SI-NEXT:    v_or_b32_e32 v7, v7, v14
; SI-NEXT:    v_or_b32_e32 v13, v46, v9
; SI-NEXT:    v_and_b32_e32 v9, 0xff, v43
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_or_b32_e32 v1, v1, v33
; SI-NEXT:    v_or_b32_e32 v3, v3, v50
; SI-NEXT:    v_or_b32_e32 v5, v5, v40
; SI-NEXT:    v_alignbit_b32 v25, v7, v13, 16
; SI-NEXT:    v_or_b32_e32 v9, v9, v58
; SI-NEXT:    v_or_b32_e32 v13, v0, v13
; SI-NEXT:    s_waitcnt vmcnt(0)
; SI-NEXT:    v_and_b32_e32 v0, 0xff, v52
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT:    v_or_b32_e32 v0, v0, v57
; SI-NEXT:    v_or_b32_e32 v1, v1, v4
; SI-NEXT:    v_or_b32_e32 v3, v3, v6
; SI-NEXT:    v_or_b32_e32 v5, v5, v12
; SI-NEXT:    v_or_b32_e32 v9, v9, v18
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_alignbit_b32 v17, v1, v2, 16
; SI-NEXT:    v_alignbit_b32 v19, v3, v10, 16
; SI-NEXT:    v_alignbit_b32 v23, v5, v11, 16
; SI-NEXT:    v_alignbit_b32 v31, v9, v20, 16
; SI-NEXT:    v_or_b32_e32 v11, v0, v20
; SI-NEXT:    v_lshrrev_b32_e32 v37, 16, v4
; SI-NEXT:    v_lshrrev_b32_e32 v38, 16, v6
; SI-NEXT:    v_lshrrev_b32_e32 v39, 16, v12
; SI-NEXT:    v_lshrrev_b32_e32 v48, 16, v14
; SI-NEXT:    v_lshrrev_b32_e32 v49, 16, v18
; SI-NEXT:    ; implicit-def: $vgpr0
; SI-NEXT:    ; implicit-def: $vgpr2
; SI-NEXT:    ; implicit-def: $vgpr4
; SI-NEXT:    ; implicit-def: $vgpr6
; SI-NEXT:    ; implicit-def: $vgpr8
; SI-NEXT:    ; implicit-def: $vgpr10
; SI-NEXT:    ; implicit-def: $vgpr12
; SI-NEXT:    ; implicit-def: $vgpr14
; SI-NEXT:    ; implicit-def: $vgpr16
; SI-NEXT:    ; implicit-def: $vgpr18
; SI-NEXT:    ; implicit-def: $vgpr20
; SI-NEXT:    ; implicit-def: $vgpr22
; SI-NEXT:    ; implicit-def: $vgpr24
; SI-NEXT:    ; implicit-def: $vgpr26
; SI-NEXT:    ; implicit-def: $vgpr28
; SI-NEXT:    ; implicit-def: $vgpr30
; SI-NEXT:    ; implicit-def: $vgpr52
; SI-NEXT:    ; implicit-def: $vgpr42
; SI-NEXT:    ; implicit-def: $vgpr43
; SI-NEXT:    ; implicit-def: $vgpr55
; SI-NEXT:    ; implicit-def: $vgpr33
; SI-NEXT:    ; implicit-def: $vgpr32
; SI-NEXT:    ; implicit-def: $vgpr34
; SI-NEXT:    ; implicit-def: $vgpr50
; SI-NEXT:    ; implicit-def: $vgpr36
; SI-NEXT:    ; implicit-def: $vgpr51
; SI-NEXT:    ; implicit-def: $vgpr40
; SI-NEXT:    ; implicit-def: $vgpr53
; SI-NEXT:    ; implicit-def: $vgpr41
; SI-NEXT:    ; implicit-def: $vgpr45
; SI-NEXT:    ; implicit-def: $vgpr47
; SI-NEXT:    ; implicit-def: $vgpr46
; SI-NEXT:    ; implicit-def: $vgpr58
; SI-NEXT:    ; implicit-def: $vgpr56
; SI-NEXT:    ; implicit-def: $vgpr59
; SI-NEXT:    ; implicit-def: $vgpr29
; SI-NEXT:    ; implicit-def: $vgpr35
; SI-NEXT:    ; implicit-def: $vgpr54
; SI-NEXT:    ; implicit-def: $vgpr44
; SI-NEXT:    ; implicit-def: $vgpr57
; SI-NEXT:  .LBB50_2: ; %Flow
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB50_4
; SI-NEXT:  ; %bb.3: ; %cmp.true
; SI-NEXT:    s_waitcnt vmcnt(0)
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v52
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v42
; SI-NEXT:    v_or_b32_e32 v1, v57, v1
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v3
; SI-NEXT:    v_add_i32_e32 v1, vcc, 0x300, v1
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v3, v59, v3
; SI-NEXT:    v_or_b32_e32 v1, v3, v1
; SI-NEXT:    v_add_i32_e32 v11, vcc, 0x3000000, v1
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v43
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v55
; SI-NEXT:    s_movk_i32 s6, 0x300
; SI-NEXT:    v_or_b32_e32 v1, v58, v1
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v3
; SI-NEXT:    v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v3, v56, v3
; SI-NEXT:    v_or_b32_e32 v1, v3, v1
; SI-NEXT:    v_add_i32_e32 v9, vcc, 0x3000000, v1
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v24
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v26
; SI-NEXT:    v_or_b32_e32 v1, v44, v1
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v3
; SI-NEXT:    v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v3, v46, v3
; SI-NEXT:    v_or_b32_e32 v1, v3, v1
; SI-NEXT:    v_add_i32_e32 v13, vcc, 0x3000000, v1
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v28
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v30
; SI-NEXT:    v_or_b32_e32 v1, v45, v1
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v3
; SI-NEXT:    v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v3, v47, v3
; SI-NEXT:    v_or_b32_e32 v1, v3, v1
; SI-NEXT:    v_add_i32_e32 v7, vcc, 0x3000000, v1
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v16
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v18
; SI-NEXT:    v_or_b32_e32 v1, v54, v1
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v3
; SI-NEXT:    v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v3, v41, v3
; SI-NEXT:    v_or_b32_e32 v1, v3, v1
; SI-NEXT:    v_add_i32_e32 v15, vcc, 0x3000000, v1
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v20
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v22
; SI-NEXT:    v_or_b32_e32 v1, v40, v1
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v3
; SI-NEXT:    v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v3, v53, v3
; SI-NEXT:    v_or_b32_e32 v1, v3, v1
; SI-NEXT:    v_add_i32_e32 v5, vcc, 0x3000000, v1
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v8
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v10
; SI-NEXT:    v_or_b32_e32 v1, v35, v1
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v3
; SI-NEXT:    v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v3, v51, v3
; SI-NEXT:    v_or_b32_e32 v1, v3, v1
; SI-NEXT:    v_add_i32_e32 v21, vcc, 0x3000000, v1
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v12
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v14
; SI-NEXT:    v_or_b32_e32 v1, v50, v1
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v3
; SI-NEXT:    v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v3, v36, v3
; SI-NEXT:    v_or_b32_e32 v1, v3, v1
; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT:    v_add_i32_e32 v3, vcc, 0x3000000, v1
; SI-NEXT:    v_and_b32_e32 v0, 0xff, v0
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v2
; SI-NEXT:    v_or_b32_e32 v0, v29, v0
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1
; SI-NEXT:    v_add_i32_e32 v0, vcc, s6, v0
; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_or_b32_e32 v1, v34, v1
; SI-NEXT:    v_or_b32_e32 v0, v1, v0
; SI-NEXT:    v_add_i32_e32 v27, vcc, 0x3000000, v0
; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v4
; SI-NEXT:    v_and_b32_e32 v0, 0xff, v0
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v6
; SI-NEXT:    v_or_b32_e32 v0, v33, v0
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1
; SI-NEXT:    v_add_i32_e32 v0, vcc, s6, v0
; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_or_b32_e32 v1, v32, v1
; SI-NEXT:    v_or_b32_e32 v0, v1, v0
; SI-NEXT:    v_add_i32_e32 v1, vcc, 0x3000000, v0
; SI-NEXT:    v_alignbit_b32 v17, v1, v27, 16
; SI-NEXT:    v_alignbit_b32 v19, v3, v21, 16
; SI-NEXT:    v_alignbit_b32 v23, v5, v15, 16
; SI-NEXT:    v_alignbit_b32 v25, v7, v13, 16
; SI-NEXT:    v_alignbit_b32 v31, v9, v11, 16
; SI-NEXT:    v_lshrrev_b32_e32 v37, 16, v1
; SI-NEXT:    v_lshrrev_b32_e32 v38, 16, v3
; SI-NEXT:    v_lshrrev_b32_e32 v39, 16, v5
; SI-NEXT:    v_lshrrev_b32_e32 v48, 16, v7
; SI-NEXT:    v_lshrrev_b32_e32 v49, 16, v9
; SI-NEXT:  .LBB50_4: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    buffer_load_dword v59, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v58, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v57, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v56, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v47, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v46, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v45, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v44, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v43, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v42, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v27
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v17
; SI-NEXT:    v_or_b32_e32 v0, v0, v2
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v37
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v21
; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v19
; SI-NEXT:    v_or_b32_e32 v2, v2, v4
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v38
; SI-NEXT:    v_or_b32_e32 v3, v3, v4
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v15
; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v23
; SI-NEXT:    v_or_b32_e32 v4, v4, v6
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v39
; SI-NEXT:    v_or_b32_e32 v5, v5, v6
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v13
; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v25
; SI-NEXT:    v_or_b32_e32 v6, v6, v8
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v48
; SI-NEXT:    v_or_b32_e32 v7, v7, v8
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v11
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v31
; SI-NEXT:    v_or_b32_e32 v8, v8, v10
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v49
; SI-NEXT:    v_or_b32_e32 v9, v9, v10
; SI-NEXT:    s_waitcnt vmcnt(0)
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v40i8_to_v20i16:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; VI-NEXT:    buffer_store_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; VI-NEXT:    buffer_store_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; VI-NEXT:    buffer_store_dword v43, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; VI-NEXT:    buffer_store_dword v44, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; VI-NEXT:    buffer_store_dword v45, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; VI-NEXT:    buffer_store_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; VI-NEXT:    buffer_store_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; VI-NEXT:    v_mov_b32_e32 v31, v0
; VI-NEXT:    buffer_load_ushort v55, off, s[0:3], s32
; VI-NEXT:    buffer_load_dword v0, off, s[0:3], s32 offset:36
; VI-NEXT:    buffer_load_ushort v46, off, s[0:3], s32 offset:32
; VI-NEXT:    buffer_load_ushort v47, off, s[0:3], s32 offset:28
; VI-NEXT:    buffer_load_ushort v43, off, s[0:3], s32 offset:24
; VI-NEXT:    buffer_load_ushort v45, off, s[0:3], s32 offset:20
; VI-NEXT:    buffer_load_ushort v42, off, s[0:3], s32 offset:16
; VI-NEXT:    buffer_load_ushort v44, off, s[0:3], s32 offset:12
; VI-NEXT:    buffer_load_ushort v40, off, s[0:3], s32 offset:8
; VI-NEXT:    buffer_load_ushort v41, off, s[0:3], s32 offset:4
; VI-NEXT:    v_mov_b32_e32 v54, v15
; VI-NEXT:    v_mov_b32_e32 v32, v14
; VI-NEXT:    v_mov_b32_e32 v50, v13
; VI-NEXT:    v_mov_b32_e32 v51, v12
; VI-NEXT:    v_mov_b32_e32 v52, v11
; VI-NEXT:    v_mov_b32_e32 v53, v10
; VI-NEXT:    v_mov_b32_e32 v38, v9
; VI-NEXT:    v_mov_b32_e32 v39, v8
; VI-NEXT:    v_mov_b32_e32 v48, v7
; VI-NEXT:    v_mov_b32_e32 v49, v6
; VI-NEXT:    v_mov_b32_e32 v34, v5
; VI-NEXT:    v_mov_b32_e32 v35, v4
; VI-NEXT:    v_mov_b32_e32 v36, v3
; VI-NEXT:    v_mov_b32_e32 v37, v2
; VI-NEXT:    v_mov_b32_e32 v33, v1
; VI-NEXT:    s_waitcnt vmcnt(8)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; VI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB50_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    s_mov_b32 s6, 0xc0c0004
; VI-NEXT:    v_perm_b32 v1, v37, v36, s6
; VI-NEXT:    v_perm_b32 v0, v31, v33, s6
; VI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT:    v_perm_b32 v2, v49, v48, s6
; VI-NEXT:    v_or_b32_e32 v0, v0, v1
; VI-NEXT:    v_perm_b32 v1, v35, v34, s6
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_perm_b32 v3, v53, v52, s6
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v39, v38, s6
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_perm_b32 v4, v32, v54, s6
; VI-NEXT:    v_or_b32_e32 v2, v2, v3
; VI-NEXT:    v_perm_b32 v3, v51, v50, s6
; VI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT:    v_perm_b32 v5, v18, v19, s6
; VI-NEXT:    v_or_b32_e32 v3, v3, v4
; VI-NEXT:    v_perm_b32 v4, v16, v17, s6
; VI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT:    v_perm_b32 v6, v22, v23, s6
; VI-NEXT:    v_or_b32_e32 v4, v4, v5
; VI-NEXT:    v_perm_b32 v5, v20, v21, s6
; VI-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT:    v_perm_b32 v7, v26, v27, s6
; VI-NEXT:    v_or_b32_e32 v5, v5, v6
; VI-NEXT:    v_perm_b32 v6, v24, v25, s6
; VI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT:    v_perm_b32 v8, v30, v55, s6
; VI-NEXT:    v_or_b32_e32 v6, v6, v7
; VI-NEXT:    v_perm_b32 v7, v28, v29, s6
; VI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT:    s_waitcnt vmcnt(2)
; VI-NEXT:    v_perm_b32 v9, v44, v42, s6
; VI-NEXT:    v_or_b32_e32 v7, v7, v8
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    v_perm_b32 v8, v41, v40, s6
; VI-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT:    v_perm_b32 v10, v47, v46, s6
; VI-NEXT:    v_or_b32_e32 v8, v8, v9
; VI-NEXT:    v_perm_b32 v9, v45, v43, s6
; VI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT:    v_or_b32_e32 v9, v9, v10
; VI-NEXT:    ; implicit-def: $vgpr31
; VI-NEXT:    ; implicit-def: $vgpr33
; VI-NEXT:    ; implicit-def: $vgpr37
; VI-NEXT:    ; implicit-def: $vgpr36
; VI-NEXT:    ; implicit-def: $vgpr35
; VI-NEXT:    ; implicit-def: $vgpr34
; VI-NEXT:    ; implicit-def: $vgpr49
; VI-NEXT:    ; implicit-def: $vgpr48
; VI-NEXT:    ; implicit-def: $vgpr39
; VI-NEXT:    ; implicit-def: $vgpr38
; VI-NEXT:    ; implicit-def: $vgpr53
; VI-NEXT:    ; implicit-def: $vgpr52
; VI-NEXT:    ; implicit-def: $vgpr51
; VI-NEXT:    ; implicit-def: $vgpr50
; VI-NEXT:    ; implicit-def: $vgpr32
; VI-NEXT:    ; implicit-def: $vgpr54
; VI-NEXT:    ; implicit-def: $vgpr16
; VI-NEXT:    ; implicit-def: $vgpr17
; VI-NEXT:    ; implicit-def: $vgpr18
; VI-NEXT:    ; implicit-def: $vgpr19
; VI-NEXT:    ; implicit-def: $vgpr20
; VI-NEXT:    ; implicit-def: $vgpr21
; VI-NEXT:    ; implicit-def: $vgpr22
; VI-NEXT:    ; implicit-def: $vgpr23
; VI-NEXT:    ; implicit-def: $vgpr24
; VI-NEXT:    ; implicit-def: $vgpr25
; VI-NEXT:    ; implicit-def: $vgpr26
; VI-NEXT:    ; implicit-def: $vgpr27
; VI-NEXT:    ; implicit-def: $vgpr28
; VI-NEXT:    ; implicit-def: $vgpr29
; VI-NEXT:    ; implicit-def: $vgpr30
; VI-NEXT:    ; implicit-def: $vgpr55
; VI-NEXT:    ; implicit-def: $vgpr41
; VI-NEXT:    ; implicit-def: $vgpr40
; VI-NEXT:    ; implicit-def: $vgpr44
; VI-NEXT:    ; implicit-def: $vgpr42
; VI-NEXT:    ; implicit-def: $vgpr45
; VI-NEXT:    ; implicit-def: $vgpr43
; VI-NEXT:    ; implicit-def: $vgpr47
; VI-NEXT:    ; implicit-def: $vgpr46
; VI-NEXT:  .LBB50_2: ; %Flow
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB50_4
; VI-NEXT:  ; %bb.3: ; %cmp.true
; VI-NEXT:    s_waitcnt vmcnt(6)
; VI-NEXT:    v_add_u16_e32 v0, 3, v47
; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v46
; VI-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_mov_b32_e32 v1, 0x300
; VI-NEXT:    v_add_u16_sdwa v9, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    s_waitcnt vmcnt(4)
; VI-NEXT:    v_add_u16_e32 v0, 3, v45
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v43
; VI-NEXT:    v_or_b32_sdwa v10, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    s_waitcnt vmcnt(2)
; VI-NEXT:    v_add_u16_e32 v0, 3, v44
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v42
; VI-NEXT:    v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_sdwa v8, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    v_add_u16_e32 v0, 3, v41
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v40
; VI-NEXT:    v_or_b32_sdwa v11, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v0, 3, v30
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v55
; VI-NEXT:    v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_sdwa v7, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_u16_e32 v0, 3, v28
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v29
; VI-NEXT:    v_or_b32_sdwa v12, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v0, 3, v26
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v27
; VI-NEXT:    v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_sdwa v6, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_u16_e32 v0, 3, v24
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v25
; VI-NEXT:    v_or_b32_sdwa v13, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v0, 3, v22
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v23
; VI-NEXT:    v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_sdwa v5, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_u16_e32 v0, 3, v20
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v21
; VI-NEXT:    v_or_b32_sdwa v14, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v0, 3, v18
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v19
; VI-NEXT:    v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_sdwa v4, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_u16_e32 v0, 3, v16
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v17
; VI-NEXT:    v_or_b32_sdwa v15, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v0, 3, v32
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v54
; VI-NEXT:    v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_sdwa v3, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_u16_e32 v0, 3, v51
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v50
; VI-NEXT:    v_or_b32_sdwa v16, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v0, 3, v53
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v52
; VI-NEXT:    v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_u16_e32 v0, 3, v39
; VI-NEXT:    v_lshlrev_b16_e32 v17, 8, v38
; VI-NEXT:    v_or_b32_sdwa v17, v17, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v0, 3, v49
; VI-NEXT:    v_lshlrev_b16_e32 v18, 8, v48
; VI-NEXT:    v_or_b32_sdwa v0, v18, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_sdwa v18, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_u16_e32 v0, 3, v35
; VI-NEXT:    v_lshlrev_b16_e32 v19, 8, v34
; VI-NEXT:    v_or_b32_sdwa v19, v19, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v0, 3, v37
; VI-NEXT:    v_lshlrev_b16_e32 v20, 8, v36
; VI-NEXT:    v_or_b32_sdwa v0, v20, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_u16_e32 v1, 3, v31
; VI-NEXT:    v_lshlrev_b16_e32 v20, 8, v33
; VI-NEXT:    v_or_b32_sdwa v1, v20, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v1, 0x300, v1
; VI-NEXT:    v_or_b32_e32 v0, v1, v0
; VI-NEXT:    v_add_u16_e32 v1, 0x300, v19
; VI-NEXT:    v_add_u16_e32 v17, 0x300, v17
; VI-NEXT:    v_add_u16_e32 v16, 0x300, v16
; VI-NEXT:    v_add_u16_e32 v15, 0x300, v15
; VI-NEXT:    v_add_u16_e32 v14, 0x300, v14
; VI-NEXT:    v_add_u16_e32 v13, 0x300, v13
; VI-NEXT:    v_add_u16_e32 v12, 0x300, v12
; VI-NEXT:    v_add_u16_e32 v11, 0x300, v11
; VI-NEXT:    v_add_u16_e32 v10, 0x300, v10
; VI-NEXT:    v_or_b32_e32 v1, v1, v18
; VI-NEXT:    v_or_b32_e32 v2, v17, v2
; VI-NEXT:    v_or_b32_e32 v3, v16, v3
; VI-NEXT:    v_or_b32_e32 v4, v15, v4
; VI-NEXT:    v_or_b32_e32 v5, v14, v5
; VI-NEXT:    v_or_b32_e32 v6, v13, v6
; VI-NEXT:    v_or_b32_e32 v7, v12, v7
; VI-NEXT:    v_or_b32_e32 v8, v11, v8
; VI-NEXT:    v_or_b32_e32 v9, v10, v9
; VI-NEXT:  .LBB50_4: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    buffer_load_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; VI-NEXT:    buffer_load_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; VI-NEXT:    buffer_load_dword v45, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; VI-NEXT:    buffer_load_dword v44, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; VI-NEXT:    buffer_load_dword v43, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; VI-NEXT:    buffer_load_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; VI-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; VI-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v40i8_to_v20i16:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; GFX9-NEXT:    buffer_store_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; GFX9-NEXT:    buffer_store_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT:    buffer_store_dword v43, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT:    buffer_store_dword v44, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; GFX9-NEXT:    buffer_store_dword v45, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; GFX9-NEXT:    buffer_store_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; GFX9-NEXT:    buffer_store_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; GFX9-NEXT:    v_mov_b32_e32 v36, v3
; GFX9-NEXT:    v_mov_b32_e32 v34, v2
; GFX9-NEXT:    v_mov_b32_e32 v31, v1
; GFX9-NEXT:    v_mov_b32_e32 v38, v0
; GFX9-NEXT:    buffer_load_ushort v55, off, s[0:3], s32
; GFX9-NEXT:    buffer_load_dword v0, off, s[0:3], s32 offset:36
; GFX9-NEXT:    buffer_load_ushort v1, off, s[0:3], s32 offset:32
; GFX9-NEXT:    buffer_load_ushort v41, off, s[0:3], s32 offset:28
; GFX9-NEXT:    buffer_load_ushort v43, off, s[0:3], s32 offset:24
; GFX9-NEXT:    buffer_load_ushort v44, off, s[0:3], s32 offset:20
; GFX9-NEXT:    buffer_load_ushort v2, off, s[0:3], s32 offset:8
; GFX9-NEXT:    buffer_load_ushort v3, off, s[0:3], s32 offset:16
; GFX9-NEXT:    buffer_load_ushort v40, off, s[0:3], s32 offset:12
; GFX9-NEXT:    buffer_load_ushort v42, off, s[0:3], s32 offset:4
; GFX9-NEXT:    v_mov_b32_e32 v39, v15
; GFX9-NEXT:    v_mov_b32_e32 v53, v14
; GFX9-NEXT:    v_mov_b32_e32 v52, v13
; GFX9-NEXT:    v_mov_b32_e32 v32, v12
; GFX9-NEXT:    v_mov_b32_e32 v35, v11
; GFX9-NEXT:    v_mov_b32_e32 v50, v10
; GFX9-NEXT:    v_mov_b32_e32 v49, v9
; GFX9-NEXT:    v_mov_b32_e32 v54, v8
; GFX9-NEXT:    v_mov_b32_e32 v33, v7
; GFX9-NEXT:    v_mov_b32_e32 v48, v6
; GFX9-NEXT:    v_mov_b32_e32 v37, v5
; GFX9-NEXT:    v_mov_b32_e32 v51, v4
; GFX9-NEXT:    s_waitcnt vmcnt(8)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-NEXT:    s_waitcnt vmcnt(7)
; GFX9-NEXT:    v_lshlrev_b16_e32 v47, 8, v1
; GFX9-NEXT:    s_waitcnt vmcnt(3)
; GFX9-NEXT:    v_lshlrev_b16_e32 v46, 8, v2
; GFX9-NEXT:    s_waitcnt vmcnt(2)
; GFX9-NEXT:    v_lshlrev_b16_e32 v45, 8, v3
; GFX9-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB50_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    s_mov_b32 s6, 0xc0c0004
; GFX9-NEXT:    v_perm_b32 v0, v38, v31, s6
; GFX9-NEXT:    v_perm_b32 v1, v34, v36, s6
; GFX9-NEXT:    s_mov_b32 s7, 0x5040100
; GFX9-NEXT:    v_perm_b32 v0, v1, v0, s7
; GFX9-NEXT:    v_perm_b32 v1, v51, v37, s6
; GFX9-NEXT:    v_perm_b32 v2, v48, v33, s6
; GFX9-NEXT:    v_perm_b32 v1, v2, v1, s7
; GFX9-NEXT:    v_perm_b32 v2, v54, v49, s6
; GFX9-NEXT:    v_perm_b32 v3, v50, v35, s6
; GFX9-NEXT:    v_perm_b32 v2, v3, v2, s7
; GFX9-NEXT:    v_perm_b32 v3, v32, v52, s6
; GFX9-NEXT:    v_perm_b32 v4, v53, v39, s6
; GFX9-NEXT:    v_perm_b32 v3, v4, v3, s7
; GFX9-NEXT:    v_perm_b32 v4, v16, v17, s6
; GFX9-NEXT:    v_perm_b32 v5, v18, v19, s6
; GFX9-NEXT:    v_perm_b32 v4, v5, v4, s7
; GFX9-NEXT:    v_perm_b32 v5, v20, v21, s6
; GFX9-NEXT:    v_perm_b32 v6, v22, v23, s6
; GFX9-NEXT:    v_perm_b32 v5, v6, v5, s7
; GFX9-NEXT:    v_perm_b32 v6, v24, v25, s6
; GFX9-NEXT:    v_perm_b32 v7, v26, v27, s6
; GFX9-NEXT:    v_perm_b32 v6, v7, v6, s7
; GFX9-NEXT:    v_perm_b32 v7, v28, v29, s6
; GFX9-NEXT:    v_perm_b32 v8, v30, v55, s6
; GFX9-NEXT:    v_perm_b32 v7, v8, v7, s7
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    v_or_b32_sdwa v8, v42, v46 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v9, v40, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT:    v_perm_b32 v8, v9, v8, s7
; GFX9-NEXT:    v_or_b32_sdwa v9, v41, v47 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT:    v_perm_b32 v10, v44, v43, s6
; GFX9-NEXT:    v_perm_b32 v9, v9, v10, s7
; GFX9-NEXT:    ; implicit-def: $vgpr38
; GFX9-NEXT:    ; implicit-def: $vgpr31
; GFX9-NEXT:    ; implicit-def: $vgpr34
; GFX9-NEXT:    ; implicit-def: $vgpr36
; GFX9-NEXT:    ; implicit-def: $vgpr51
; GFX9-NEXT:    ; implicit-def: $vgpr37
; GFX9-NEXT:    ; implicit-def: $vgpr48
; GFX9-NEXT:    ; implicit-def: $vgpr33
; GFX9-NEXT:    ; implicit-def: $vgpr54
; GFX9-NEXT:    ; implicit-def: $vgpr49
; GFX9-NEXT:    ; implicit-def: $vgpr50
; GFX9-NEXT:    ; implicit-def: $vgpr35
; GFX9-NEXT:    ; implicit-def: $vgpr32
; GFX9-NEXT:    ; implicit-def: $vgpr52
; GFX9-NEXT:    ; implicit-def: $vgpr53
; GFX9-NEXT:    ; implicit-def: $vgpr39
; GFX9-NEXT:    ; implicit-def: $vgpr16
; GFX9-NEXT:    ; implicit-def: $vgpr17
; GFX9-NEXT:    ; implicit-def: $vgpr18
; GFX9-NEXT:    ; implicit-def: $vgpr19
; GFX9-NEXT:    ; implicit-def: $vgpr20
; GFX9-NEXT:    ; implicit-def: $vgpr21
; GFX9-NEXT:    ; implicit-def: $vgpr22
; GFX9-NEXT:    ; implicit-def: $vgpr23
; GFX9-NEXT:    ; implicit-def: $vgpr24
; GFX9-NEXT:    ; implicit-def: $vgpr25
; GFX9-NEXT:    ; implicit-def: $vgpr26
; GFX9-NEXT:    ; implicit-def: $vgpr27
; GFX9-NEXT:    ; implicit-def: $vgpr28
; GFX9-NEXT:    ; implicit-def: $vgpr29
; GFX9-NEXT:    ; implicit-def: $vgpr30
; GFX9-NEXT:    ; implicit-def: $vgpr55
; GFX9-NEXT:    ; implicit-def: $vgpr42
; GFX9-NEXT:    ; implicit-def: $vgpr40
; GFX9-NEXT:    ; implicit-def: $vgpr44
; GFX9-NEXT:    ; implicit-def: $vgpr43
; GFX9-NEXT:    ; implicit-def: $vgpr41
; GFX9-NEXT:    ; implicit-def: $vgpr46
; GFX9-NEXT:    ; implicit-def: $vgpr45
; GFX9-NEXT:    ; implicit-def: $vgpr47
; GFX9-NEXT:  .LBB50_2: ; %Flow
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB50_4
; GFX9-NEXT:  ; %bb.3: ; %cmp.true
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v44
; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v43
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v9, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v41
; GFX9-NEXT:    v_or_b32_sdwa v0, v47, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v10, 0x300, v0
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v42
; GFX9-NEXT:    v_or_b32_sdwa v0, v46, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v8, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v40
; GFX9-NEXT:    v_or_b32_sdwa v0, v45, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v11, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v28
; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v29
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v7, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v30
; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v55
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v12, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v24
; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v25
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v6, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v26
; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v27
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v13, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v20
; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v21
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v5, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v22
; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v23
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v14, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v16
; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v17
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v4, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v18
; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v19
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v15, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v32
; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v52
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v3, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v53
; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v39
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v16, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v54
; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v49
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v2, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v50
; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v35
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v17, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v51
; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v37
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v1, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v48
; GFX9-NEXT:    v_lshlrev_b16_e32 v18, 8, v33
; GFX9-NEXT:    v_or_b32_sdwa v0, v18, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v18, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v38
; GFX9-NEXT:    v_lshlrev_b16_e32 v19, 8, v31
; GFX9-NEXT:    v_or_b32_sdwa v0, v19, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v19, 3, v34
; GFX9-NEXT:    v_lshlrev_b16_e32 v20, 8, v36
; GFX9-NEXT:    v_or_b32_sdwa v19, v20, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v0, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v19, 0x300, v19
; GFX9-NEXT:    s_mov_b32 s6, 0x5040100
; GFX9-NEXT:    v_perm_b32 v0, v19, v0, s6
; GFX9-NEXT:    v_perm_b32 v1, v18, v1, s6
; GFX9-NEXT:    v_perm_b32 v2, v17, v2, s6
; GFX9-NEXT:    v_perm_b32 v3, v16, v3, s6
; GFX9-NEXT:    v_perm_b32 v4, v15, v4, s6
; GFX9-NEXT:    v_perm_b32 v5, v14, v5, s6
; GFX9-NEXT:    v_perm_b32 v6, v13, v6, s6
; GFX9-NEXT:    v_perm_b32 v7, v12, v7, s6
; GFX9-NEXT:    v_perm_b32 v8, v11, v8, s6
; GFX9-NEXT:    v_perm_b32 v9, v10, v9, s6
; GFX9-NEXT:  .LBB50_4: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    buffer_load_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; GFX9-NEXT:    buffer_load_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; GFX9-NEXT:    buffer_load_dword v45, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; GFX9-NEXT:    buffer_load_dword v44, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; GFX9-NEXT:    buffer_load_dword v43, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; GFX9-NEXT:    buffer_load_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; GFX9-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v40i8_to_v20i16:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    s_clause 0x9
; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v32, off, s32 offset:32
; GFX11-TRUE16-NEXT:    scratch_load_b32 v70, off, s32 offset:36
; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v33, off, s32 offset:8
; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v34, off, s32 offset:16
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v32, off, s32 offset:28
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v34, off, s32 offset:24
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v35, off, s32 offset:20
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v31, off, s32 offset:12
; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v31, off, s32 offset:4
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v33, off, s32
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v37.l, v22.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.l, v19.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v51.l, v18.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v18.l, v17.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.l, v16.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v39.l, v15.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v53.l, v14.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v38.l, v13.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v65.l, v12.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v50.l, v11.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v64.l, v10.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v22.l, v9.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v49.l, v8.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v52.l, v7.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v66.l, v6.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v54.l, v5.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v68.l, v4.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v67.l, v3.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v69.l, v2.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v48.l, v1.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v0.l
; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(5)
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.l, 8, v32.h
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.l, 8, v33.h
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v34.h
; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v70
; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB50_3
; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB50_4
; GFX11-TRUE16-NEXT:  .LBB50_2: ; %end
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT:  .LBB50_3: ; %cmp.false
; GFX11-TRUE16-NEXT:    v_perm_b32 v2, v69, v67, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v4, v64, v50, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, v51, v36, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v8, v26, v27, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v0, v55, v48, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v2.l
; GFX11-TRUE16-NEXT:    v_perm_b32 v2, v49, v22, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v4.l
; GFX11-TRUE16-NEXT:    v_perm_b32 v4, v19, v18, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v6.l
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, v24, v25, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v8.l
; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, v32.l, 0xff
; GFX11-TRUE16-NEXT:    v_perm_b32 v3, v66, v52, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v5, v53, v39, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, v37, v23, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_and_b16 v8.h, v31.h, 0xff
; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, v31.l, 0xff
; GFX11-TRUE16-NEXT:    v_perm_b32 v11, v30, v33, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v8.l, v17.l
; GFX11-TRUE16-NEXT:    v_perm_b32 v1, v68, v54, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v3.l
; GFX11-TRUE16-NEXT:    v_perm_b32 v3, v65, v38, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v5.l
; GFX11-TRUE16-NEXT:    v_perm_b32 v5, v20, v21, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v7.l
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, v28, v29, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.h, v16.l
; GFX11-TRUE16-NEXT:    v_or_b16 v8.h, v9.l, v16.h
; GFX11-TRUE16-NEXT:    v_perm_b32 v9, v35, v34, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.h, v11.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.h, v10.l
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr69_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr67_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr68_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr66_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr65_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_hi16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_hi16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB50_2
; GFX11-TRUE16-NEXT:  .LBB50_4: ; %cmp.true
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v35.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v32.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v31.h, 3
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v34.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v31.l, 3
; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, 0xff
; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, v0.h, 0xff
; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, v1.h, 0xff
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v26.l, 3
; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, v2.l, 0xff
; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v17.l, v0.h
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v28.l, 3
; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v16.l, v1.h
; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v16.h, v2.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, v0.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.h, v0.h, 0x300
; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, v1.l, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 8, v29.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v30.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, v1.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v24.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.h, v2.l, 0x300
; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.h, v0.l
; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, v1.l, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v33.l
; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, v1.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 8, v25.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, v0.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v20.l, 3
; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v1.l, v0.h
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v37.l, 3
; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v2.l, v1.h
; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, v2.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 8, v27.l
; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v21.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, v0.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, v1.l, 0x300
; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v2.l, v1.h
; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, v3.l, 0xff
; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v2.h, v0.l
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 8, v23.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v19.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, v0.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v51.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, v0.l, 0x300
; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v1.h, v1.l
; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, v2.l, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 8, v18.l
; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, v0.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 8, v36.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, v0.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v65.l, 3
; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.h, v1.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v53.l, 3
; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v2.l, v0.h
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v49.l, 3
; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v38.l
; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, v1.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.l, 8, v39.l
; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, v2.l, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v22.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, v1.l, 0x300
; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v2.h, v0.l
; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v3.l, v1.h
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.h, v0.h, 0x300
; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v3.h, v2.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v64.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v0.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v68.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v55.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v0.h, 0x300
; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, v1.h, 0xff
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v66.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v10.h, v69.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, v1.l, 0x300
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v50.l
; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.l, 8, v54.l
; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, v1.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.l, 8, v52.l
; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, v2.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v48.l
; GFX11-TRUE16-NEXT:    v_and_b16 v10.h, v10.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.l, 8, v67.l
; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v1.l, v0.h
; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v10.l, v0.l
; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v11.l, v1.h
; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v11.h, v2.h
; GFX11-TRUE16-NEXT:    v_or_b16 v10.h, v12.l, v10.h
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v0.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v0.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v1.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v10.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v10.h, 0x300
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v40i8_to_v20i16:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v36, v7 :: v_dual_mov_b32 v35, v2
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v52, v4 :: v_dual_mov_b32 v33, v3
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v48, v1 :: v_dual_mov_b32 v37, v0
; GFX11-FAKE16-NEXT:    s_clause 0x9
; GFX11-FAKE16-NEXT:    scratch_load_u16 v0, off, s32 offset:32
; GFX11-FAKE16-NEXT:    scratch_load_b32 v1, off, s32 offset:36
; GFX11-FAKE16-NEXT:    scratch_load_u16 v2, off, s32 offset:8
; GFX11-FAKE16-NEXT:    scratch_load_u16 v3, off, s32 offset:16
; GFX11-FAKE16-NEXT:    scratch_load_u16 v70, off, s32 offset:28
; GFX11-FAKE16-NEXT:    scratch_load_u16 v68, off, s32 offset:24
; GFX11-FAKE16-NEXT:    scratch_load_u16 v69, off, s32 offset:20
; GFX11-FAKE16-NEXT:    scratch_load_u16 v67, off, s32 offset:12
; GFX11-FAKE16-NEXT:    scratch_load_u16 v71, off, s32 offset:4
; GFX11-FAKE16-NEXT:    scratch_load_u16 v55, off, s32
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v50, v15 :: v_dual_mov_b32 v49, v10
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v54, v14 :: v_dual_mov_b32 v51, v13
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v32, v12 :: v_dual_mov_b32 v53, v9
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v38, v11 :: v_dual_mov_b32 v31, v8
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v34, v6 :: v_dual_mov_b32 v39, v5
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(9)
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v66, 8, v0
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(8)
; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v1
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(7)
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v65, 8, v2
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(6)
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v64, 8, v3
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB50_3
; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB50_4
; GFX11-FAKE16-NEXT:  .LBB50_2: ; %end
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT:  .LBB50_3: ; %cmp.false
; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v37, v48, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v35, v33, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v52, v39, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v34, v36, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v31, v53, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v49, v38, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v16, v17, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v18, v19, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v32, v51, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v54, v50, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v3, v2, 0x5040100
; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v5, v4, 0x5040100
; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v9, v8, 0x5040100
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v71
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v67
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v70
; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v7, v6, 0x5040100
; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v20, v21, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v22, v23, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v24, v25, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v26, v27, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v28, v29, 0xc0c0004
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v30, v55, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v65
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v64
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v66
; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v69, v68, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v6, v5, 0x5040100
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v8, v7, 0x5040100
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v13, v12, 0x5040100
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v10, v9, 0x5040100
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v11, v14, 0x5040100
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr55
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr71
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr67
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr69
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr68
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr70
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr66
; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB50_2
; GFX11-FAKE16-NEXT:  .LBB50_4: ; %cmp.true
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(3)
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v69, 3
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v68
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v71, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v70, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v67, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v28, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v6, 8, v29
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v1, v0
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v4
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v65, v3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v66, v2
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v5
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v0, 0x300
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v30, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v3, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v64, v1
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v55
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v2, 0x300
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v6, v4
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v24, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, v1, 0x300
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v26, 3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v3, v0
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v2, 0x300
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v4
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v25
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v4, 8, v27
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, v0, 0x300
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v20, 3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v3, v2
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v22, 3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v4, v1
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v16, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v21
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v6, 8, v23
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v17
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v5, v0
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, v2, 0x300
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, v1, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v6, v3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v13, v4
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v18, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v0, 0x300
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v32, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v1, 0x300
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v2, 0x300
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v31, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v51
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, v54, 3
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v19
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v53
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v3, v0
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v13
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v50
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v16, v1
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, v49, 3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v17, v2
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, v0, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v13, v3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v52, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v16
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, v34, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, v37, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v19, v35, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v20, 8, v39
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v16
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v18
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v48
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v19
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v33
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v36
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v38
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v20, v3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v21, v18
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v22, v19
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v23, v16
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v24, v13
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v2, 0x300
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v3, 0x300
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, v18, 0x300
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v19, v19, 0x300
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, v16, 0x300
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, v13, 0x300
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v20, v0, 0x300
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v21, v1, 0x300
; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v19, v18, 0x5040100
; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v16, v3, 0x5040100
; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v13, v2, 0x5040100
; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v20, v17, 0x5040100
; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v21, v4, 0x5040100
; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v6, v5, 0x5040100
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v15, v14, 0x5040100
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v12, v7, 0x5040100
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v11, v8, 0x5040100
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v10, v9, 0x5040100
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <40 x i8> %a, splat (i8 3)
  %a2 = bitcast <40 x i8> %a1 to <20 x i16>
  br label %end

cmp.false:
  %a3 = bitcast <40 x i8> %a to <20 x i16>
  br label %end

end:
  %phi = phi <20 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <20 x i16> %phi
}

define inreg <20 x i16> @bitcast_v40i8_to_v20i16_scalar(<40 x i8> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v40i8_to_v20i16_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_readfirstlane_b32 s10, v26
; SI-NEXT:    v_readfirstlane_b32 s5, v25
; SI-NEXT:    v_readfirstlane_b32 s56, v24
; SI-NEXT:    v_readfirstlane_b32 s59, v23
; SI-NEXT:    v_readfirstlane_b32 s60, v22
; SI-NEXT:    v_readfirstlane_b32 s4, v21
; SI-NEXT:    v_readfirstlane_b32 s62, v20
; SI-NEXT:    v_readfirstlane_b32 s63, v19
; SI-NEXT:    v_readfirstlane_b32 s72, v18
; SI-NEXT:    v_readfirstlane_b32 s7, v17
; SI-NEXT:    v_readfirstlane_b32 s45, v16
; SI-NEXT:    v_readfirstlane_b32 s57, v15
; SI-NEXT:    v_readfirstlane_b32 s58, v14
; SI-NEXT:    v_readfirstlane_b32 s6, v13
; SI-NEXT:    v_readfirstlane_b32 s15, v12
; SI-NEXT:    v_readfirstlane_b32 s44, v11
; SI-NEXT:    v_readfirstlane_b32 s61, v10
; SI-NEXT:    v_readfirstlane_b32 s9, v9
; SI-NEXT:    v_readfirstlane_b32 s43, v8
; SI-NEXT:    v_readfirstlane_b32 s46, v7
; SI-NEXT:    v_readfirstlane_b32 s47, v6
; SI-NEXT:    v_readfirstlane_b32 s8, v5
; SI-NEXT:    v_readfirstlane_b32 s14, v4
; SI-NEXT:    s_cmp_lg_u32 s10, 0
; SI-NEXT:    v_readfirstlane_b32 s41, v3
; SI-NEXT:    v_readfirstlane_b32 s42, v2
; SI-NEXT:    v_readfirstlane_b32 s11, v1
; SI-NEXT:    v_readfirstlane_b32 s13, v0
; SI-NEXT:    s_cbranch_scc0 .LBB51_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    s_and_b32 s10, s16, 0xff
; SI-NEXT:    s_lshl_b32 s12, s17, 8
; SI-NEXT:    s_or_b32 s10, s10, s12
; SI-NEXT:    s_and_b32 s12, s18, 0xff
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_lshl_b32 s16, s19, 24
; SI-NEXT:    s_and_b32 s10, s10, 0xffff
; SI-NEXT:    s_or_b32 s40, s16, s12
; SI-NEXT:    s_or_b32 s12, s10, s40
; SI-NEXT:    s_and_b32 s10, s24, 0xff
; SI-NEXT:    s_lshl_b32 s16, s25, 8
; SI-NEXT:    s_or_b32 s10, s10, s16
; SI-NEXT:    s_and_b32 s16, s26, 0xff
; SI-NEXT:    s_lshl_b32 s16, s16, 16
; SI-NEXT:    s_lshl_b32 s17, s27, 24
; SI-NEXT:    s_or_b32 s24, s17, s16
; SI-NEXT:    s_and_b32 s16, s42, 0xff
; SI-NEXT:    s_lshl_b32 s17, s41, 8
; SI-NEXT:    s_and_b32 s14, s14, 0xff
; SI-NEXT:    s_or_b32 s16, s16, s17
; SI-NEXT:    s_lshl_b32 s14, s14, 16
; SI-NEXT:    s_lshl_b32 s8, s8, 24
; SI-NEXT:    s_and_b32 s16, s16, 0xffff
; SI-NEXT:    s_or_b32 s26, s8, s14
; SI-NEXT:    s_or_b32 s8, s16, s26
; SI-NEXT:    s_and_b32 s14, s61, 0xff
; SI-NEXT:    s_lshl_b32 s16, s44, 8
; SI-NEXT:    s_and_b32 s15, s15, 0xff
; SI-NEXT:    s_or_b32 s14, s14, s16
; SI-NEXT:    s_lshl_b32 s15, s15, 16
; SI-NEXT:    s_lshl_b32 s6, s6, 24
; SI-NEXT:    s_and_b32 s14, s14, 0xffff
; SI-NEXT:    s_or_b32 s42, s6, s15
; SI-NEXT:    s_or_b32 s6, s14, s42
; SI-NEXT:    s_and_b32 s14, s72, 0xff
; SI-NEXT:    s_lshl_b32 s15, s63, 8
; SI-NEXT:    s_or_b32 s14, s14, s15
; SI-NEXT:    s_and_b32 s15, s62, 0xff
; SI-NEXT:    s_lshl_b32 s15, s15, 16
; SI-NEXT:    s_lshl_b32 s4, s4, 24
; SI-NEXT:    s_and_b32 s14, s14, 0xffff
; SI-NEXT:    s_or_b32 s44, s4, s15
; SI-NEXT:    s_or_b32 s4, s14, s44
; SI-NEXT:    s_and_b32 s14, s20, 0xff
; SI-NEXT:    s_lshl_b32 s15, s21, 8
; SI-NEXT:    s_or_b32 s14, s14, s15
; SI-NEXT:    s_and_b32 s15, s22, 0xff
; SI-NEXT:    s_lshl_b32 s15, s15, 16
; SI-NEXT:    s_lshl_b32 s16, s23, 24
; SI-NEXT:    s_and_b32 s14, s14, 0xffff
; SI-NEXT:    s_or_b32 s61, s16, s15
; SI-NEXT:    s_or_b32 s41, s14, s61
; SI-NEXT:    s_lshr_b64 s[14:15], s[40:41], 16
; SI-NEXT:    s_and_b32 s15, s28, 0xff
; SI-NEXT:    s_lshl_b32 s16, s29, 8
; SI-NEXT:    s_and_b32 s13, s13, 0xff
; SI-NEXT:    s_or_b32 s15, s15, s16
; SI-NEXT:    s_lshl_b32 s13, s13, 16
; SI-NEXT:    s_lshl_b32 s11, s11, 24
; SI-NEXT:    s_and_b32 s15, s15, 0xffff
; SI-NEXT:    s_or_b32 s11, s11, s13
; SI-NEXT:    s_or_b32 s25, s15, s11
; SI-NEXT:    s_and_b32 s13, s47, 0xff
; SI-NEXT:    s_lshl_b32 s15, s46, 8
; SI-NEXT:    s_or_b32 s13, s13, s15
; SI-NEXT:    s_and_b32 s15, s43, 0xff
; SI-NEXT:    s_lshl_b32 s15, s15, 16
; SI-NEXT:    s_lshl_b32 s9, s9, 24
; SI-NEXT:    s_and_b32 s13, s13, 0xffff
; SI-NEXT:    s_or_b32 s9, s9, s15
; SI-NEXT:    s_or_b32 s27, s13, s9
; SI-NEXT:    s_and_b32 s13, s58, 0xff
; SI-NEXT:    s_lshl_b32 s15, s57, 8
; SI-NEXT:    s_or_b32 s13, s13, s15
; SI-NEXT:    s_and_b32 s15, s45, 0xff
; SI-NEXT:    s_lshl_b32 s15, s15, 16
; SI-NEXT:    s_lshl_b32 s7, s7, 24
; SI-NEXT:    s_and_b32 s13, s13, 0xffff
; SI-NEXT:    s_or_b32 s7, s7, s15
; SI-NEXT:    s_or_b32 s43, s13, s7
; SI-NEXT:    s_and_b32 s13, s60, 0xff
; SI-NEXT:    s_lshl_b32 s15, s59, 8
; SI-NEXT:    s_or_b32 s13, s13, s15
; SI-NEXT:    s_and_b32 s15, s56, 0xff
; SI-NEXT:    s_lshl_b32 s15, s15, 16
; SI-NEXT:    s_lshl_b32 s5, s5, 24
; SI-NEXT:    s_and_b32 s13, s13, 0xffff
; SI-NEXT:    s_or_b32 s5, s5, s15
; SI-NEXT:    s_or_b32 s45, s13, s5
; SI-NEXT:    s_and_b32 s10, s10, 0xffff
; SI-NEXT:    s_lshr_b64 s[16:17], s[24:25], 16
; SI-NEXT:    s_lshr_b64 s[18:19], s[26:27], 16
; SI-NEXT:    s_lshr_b64 s[20:21], s[42:43], 16
; SI-NEXT:    s_lshr_b64 s[22:23], s[44:45], 16
; SI-NEXT:    s_or_b32 s10, s10, s24
; SI-NEXT:    s_lshr_b32 s23, s61, 16
; SI-NEXT:    s_lshr_b32 s21, s11, 16
; SI-NEXT:    s_lshr_b32 s19, s9, 16
; SI-NEXT:    s_lshr_b32 s17, s7, 16
; SI-NEXT:    s_lshr_b32 s15, s5, 16
; SI-NEXT:    s_mov_b32 s13, s41
; SI-NEXT:    s_mov_b32 s11, s25
; SI-NEXT:    s_mov_b32 s9, s27
; SI-NEXT:    s_mov_b32 s7, s43
; SI-NEXT:    s_mov_b32 s5, s45
; SI-NEXT:    s_branch .LBB51_3
; SI-NEXT:  .LBB51_2: ; %cmp.true
; SI-NEXT:    s_add_i32 s72, s72, 3
; SI-NEXT:    s_and_b32 s10, s72, 0xff
; SI-NEXT:    s_lshl_b32 s12, s63, 8
; SI-NEXT:    s_add_i32 s62, s62, 3
; SI-NEXT:    s_or_b32 s10, s12, s10
; SI-NEXT:    s_and_b32 s12, s62, 0xff
; SI-NEXT:    s_addk_i32 s10, 0x300
; SI-NEXT:    s_lshl_b32 s4, s4, 24
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_and_b32 s10, s10, 0xffff
; SI-NEXT:    s_or_b32 s4, s4, s12
; SI-NEXT:    s_add_i32 s60, s60, 3
; SI-NEXT:    s_or_b32 s4, s4, s10
; SI-NEXT:    s_and_b32 s10, s60, 0xff
; SI-NEXT:    s_lshl_b32 s12, s59, 8
; SI-NEXT:    s_add_i32 s56, s56, 3
; SI-NEXT:    s_or_b32 s10, s12, s10
; SI-NEXT:    s_and_b32 s12, s56, 0xff
; SI-NEXT:    s_addk_i32 s10, 0x300
; SI-NEXT:    s_lshl_b32 s5, s5, 24
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_and_b32 s10, s10, 0xffff
; SI-NEXT:    s_or_b32 s5, s5, s12
; SI-NEXT:    s_add_i32 s61, s61, 3
; SI-NEXT:    s_or_b32 s5, s5, s10
; SI-NEXT:    s_and_b32 s10, s61, 0xff
; SI-NEXT:    s_lshl_b32 s12, s44, 8
; SI-NEXT:    s_add_i32 s15, s15, 3
; SI-NEXT:    s_or_b32 s10, s12, s10
; SI-NEXT:    s_and_b32 s12, s15, 0xff
; SI-NEXT:    s_addk_i32 s10, 0x300
; SI-NEXT:    s_lshl_b32 s6, s6, 24
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_and_b32 s10, s10, 0xffff
; SI-NEXT:    s_or_b32 s6, s6, s12
; SI-NEXT:    s_add_i32 s58, s58, 3
; SI-NEXT:    s_or_b32 s6, s6, s10
; SI-NEXT:    s_and_b32 s10, s58, 0xff
; SI-NEXT:    s_lshl_b32 s12, s57, 8
; SI-NEXT:    s_add_i32 s45, s45, 3
; SI-NEXT:    s_or_b32 s10, s12, s10
; SI-NEXT:    s_and_b32 s12, s45, 0xff
; SI-NEXT:    s_addk_i32 s10, 0x300
; SI-NEXT:    s_lshl_b32 s7, s7, 24
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_and_b32 s10, s10, 0xffff
; SI-NEXT:    s_or_b32 s7, s7, s12
; SI-NEXT:    s_add_i32 s42, s42, 3
; SI-NEXT:    s_or_b32 s7, s7, s10
; SI-NEXT:    s_and_b32 s10, s42, 0xff
; SI-NEXT:    s_lshl_b32 s12, s41, 8
; SI-NEXT:    s_add_i32 s14, s14, 3
; SI-NEXT:    s_or_b32 s10, s12, s10
; SI-NEXT:    s_and_b32 s12, s14, 0xff
; SI-NEXT:    s_addk_i32 s10, 0x300
; SI-NEXT:    s_lshl_b32 s8, s8, 24
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_and_b32 s10, s10, 0xffff
; SI-NEXT:    s_or_b32 s8, s8, s12
; SI-NEXT:    s_add_i32 s47, s47, 3
; SI-NEXT:    s_or_b32 s8, s8, s10
; SI-NEXT:    s_and_b32 s10, s47, 0xff
; SI-NEXT:    s_lshl_b32 s12, s46, 8
; SI-NEXT:    s_add_i32 s43, s43, 3
; SI-NEXT:    s_or_b32 s10, s12, s10
; SI-NEXT:    s_and_b32 s12, s43, 0xff
; SI-NEXT:    s_addk_i32 s10, 0x300
; SI-NEXT:    s_lshl_b32 s9, s9, 24
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_and_b32 s10, s10, 0xffff
; SI-NEXT:    s_or_b32 s9, s9, s12
; SI-NEXT:    s_add_i32 s24, s24, 3
; SI-NEXT:    s_or_b32 s9, s9, s10
; SI-NEXT:    s_and_b32 s10, s24, 0xff
; SI-NEXT:    s_lshl_b32 s12, s25, 8
; SI-NEXT:    s_add_i32 s26, s26, 3
; SI-NEXT:    s_or_b32 s10, s12, s10
; SI-NEXT:    s_and_b32 s14, s26, 0xff
; SI-NEXT:    s_addk_i32 s10, 0x300
; SI-NEXT:    s_lshl_b32 s12, s27, 24
; SI-NEXT:    s_lshl_b32 s14, s14, 16
; SI-NEXT:    s_and_b32 s10, s10, 0xffff
; SI-NEXT:    s_or_b32 s12, s12, s14
; SI-NEXT:    s_add_i32 s28, s28, 3
; SI-NEXT:    s_or_b32 s10, s12, s10
; SI-NEXT:    s_and_b32 s12, s28, 0xff
; SI-NEXT:    s_lshl_b32 s14, s29, 8
; SI-NEXT:    s_add_i32 s13, s13, 3
; SI-NEXT:    s_or_b32 s12, s14, s12
; SI-NEXT:    s_and_b32 s13, s13, 0xff
; SI-NEXT:    s_addk_i32 s12, 0x300
; SI-NEXT:    s_lshl_b32 s11, s11, 24
; SI-NEXT:    s_lshl_b32 s13, s13, 16
; SI-NEXT:    s_and_b32 s12, s12, 0xffff
; SI-NEXT:    s_or_b32 s11, s11, s13
; SI-NEXT:    s_add_i32 s16, s16, 3
; SI-NEXT:    s_or_b32 s11, s11, s12
; SI-NEXT:    s_and_b32 s12, s16, 0xff
; SI-NEXT:    s_lshl_b32 s13, s17, 8
; SI-NEXT:    s_add_i32 s18, s18, 3
; SI-NEXT:    s_or_b32 s12, s13, s12
; SI-NEXT:    s_and_b32 s14, s18, 0xff
; SI-NEXT:    s_addk_i32 s12, 0x300
; SI-NEXT:    s_lshl_b32 s13, s19, 24
; SI-NEXT:    s_lshl_b32 s14, s14, 16
; SI-NEXT:    s_and_b32 s12, s12, 0xffff
; SI-NEXT:    s_or_b32 s13, s13, s14
; SI-NEXT:    s_add_i32 s20, s20, 3
; SI-NEXT:    s_or_b32 s12, s13, s12
; SI-NEXT:    s_and_b32 s13, s20, 0xff
; SI-NEXT:    s_lshl_b32 s14, s21, 8
; SI-NEXT:    s_add_i32 s22, s22, 3
; SI-NEXT:    s_or_b32 s13, s14, s13
; SI-NEXT:    s_and_b32 s15, s22, 0xff
; SI-NEXT:    s_addk_i32 s13, 0x300
; SI-NEXT:    s_lshl_b32 s14, s23, 24
; SI-NEXT:    s_lshl_b32 s15, s15, 16
; SI-NEXT:    s_and_b32 s13, s13, 0xffff
; SI-NEXT:    s_or_b32 s14, s14, s15
; SI-NEXT:    s_or_b32 s13, s14, s13
; SI-NEXT:    s_add_i32 s4, s4, 0x3000000
; SI-NEXT:    s_add_i32 s5, s5, 0x3000000
; SI-NEXT:    s_add_i32 s6, s6, 0x3000000
; SI-NEXT:    s_add_i32 s7, s7, 0x3000000
; SI-NEXT:    s_add_i32 s8, s8, 0x3000000
; SI-NEXT:    s_add_i32 s9, s9, 0x3000000
; SI-NEXT:    s_add_i32 s10, s10, 0x3000000
; SI-NEXT:    s_add_i32 s11, s11, 0x3000000
; SI-NEXT:    s_add_i32 s12, s12, 0x3000000
; SI-NEXT:    s_add_i32 s13, s13, 0x3000000
; SI-NEXT:    s_lshr_b64 s[14:15], s[12:13], 16
; SI-NEXT:    s_lshr_b64 s[16:17], s[10:11], 16
; SI-NEXT:    s_lshr_b64 s[18:19], s[8:9], 16
; SI-NEXT:    s_lshr_b64 s[20:21], s[6:7], 16
; SI-NEXT:    s_lshr_b64 s[22:23], s[4:5], 16
; SI-NEXT:    s_lshr_b32 s23, s13, 16
; SI-NEXT:    s_lshr_b32 s21, s11, 16
; SI-NEXT:    s_lshr_b32 s19, s9, 16
; SI-NEXT:    s_lshr_b32 s17, s7, 16
; SI-NEXT:    s_lshr_b32 s15, s5, 16
; SI-NEXT:  .LBB51_3: ; %end
; SI-NEXT:    s_and_b32 s12, s12, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s14, 16
; SI-NEXT:    s_or_b32 s12, s12, s14
; SI-NEXT:    s_and_b32 s13, s13, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s23, 16
; SI-NEXT:    s_or_b32 s13, s13, s14
; SI-NEXT:    s_and_b32 s10, s10, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s16, 16
; SI-NEXT:    s_or_b32 s10, s10, s14
; SI-NEXT:    s_and_b32 s11, s11, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s21, 16
; SI-NEXT:    s_or_b32 s11, s11, s14
; SI-NEXT:    s_and_b32 s8, s8, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s18, 16
; SI-NEXT:    s_or_b32 s8, s8, s14
; SI-NEXT:    s_and_b32 s9, s9, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s19, 16
; SI-NEXT:    s_or_b32 s9, s9, s14
; SI-NEXT:    s_and_b32 s6, s6, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s20, 16
; SI-NEXT:    s_or_b32 s6, s6, s14
; SI-NEXT:    s_and_b32 s7, s7, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s17, 16
; SI-NEXT:    s_or_b32 s7, s7, s14
; SI-NEXT:    s_and_b32 s4, s4, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s22, 16
; SI-NEXT:    s_or_b32 s4, s4, s14
; SI-NEXT:    s_and_b32 s5, s5, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s15, 16
; SI-NEXT:    s_or_b32 s5, s5, s14
; SI-NEXT:    v_mov_b32_e32 v0, s12
; SI-NEXT:    v_mov_b32_e32 v1, s13
; SI-NEXT:    v_mov_b32_e32 v2, s10
; SI-NEXT:    v_mov_b32_e32 v3, s11
; SI-NEXT:    v_mov_b32_e32 v4, s8
; SI-NEXT:    v_mov_b32_e32 v5, s9
; SI-NEXT:    v_mov_b32_e32 v6, s6
; SI-NEXT:    v_mov_b32_e32 v7, s7
; SI-NEXT:    v_mov_b32_e32 v8, s4
; SI-NEXT:    v_mov_b32_e32 v9, s5
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v40i8_to_v20i16_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_readfirstlane_b32 s61, v26
; VI-NEXT:    v_readfirstlane_b32 s5, v25
; VI-NEXT:    v_readfirstlane_b32 s7, v24
; VI-NEXT:    v_readfirstlane_b32 s4, v23
; VI-NEXT:    v_readfirstlane_b32 s6, v22
; VI-NEXT:    v_readfirstlane_b32 s8, v21
; VI-NEXT:    v_readfirstlane_b32 s10, v20
; VI-NEXT:    v_readfirstlane_b32 s9, v19
; VI-NEXT:    v_readfirstlane_b32 s11, v18
; VI-NEXT:    v_readfirstlane_b32 s12, v17
; VI-NEXT:    v_readfirstlane_b32 s14, v16
; VI-NEXT:    v_readfirstlane_b32 s13, v15
; VI-NEXT:    v_readfirstlane_b32 s15, v14
; VI-NEXT:    v_readfirstlane_b32 s40, v13
; VI-NEXT:    v_readfirstlane_b32 s42, v12
; VI-NEXT:    v_readfirstlane_b32 s41, v11
; VI-NEXT:    v_readfirstlane_b32 s43, v10
; VI-NEXT:    v_readfirstlane_b32 s44, v9
; VI-NEXT:    v_readfirstlane_b32 s46, v8
; VI-NEXT:    v_readfirstlane_b32 s45, v7
; VI-NEXT:    v_readfirstlane_b32 s47, v6
; VI-NEXT:    v_readfirstlane_b32 s56, v5
; VI-NEXT:    v_readfirstlane_b32 s58, v4
; VI-NEXT:    v_readfirstlane_b32 s57, v3
; VI-NEXT:    v_readfirstlane_b32 s59, v2
; VI-NEXT:    v_readfirstlane_b32 s60, v1
; VI-NEXT:    s_cmp_lg_u32 s61, 0
; VI-NEXT:    v_readfirstlane_b32 s61, v0
; VI-NEXT:    s_cbranch_scc0 .LBB51_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    v_mov_b32_e32 v9, 0xc0c0004
; VI-NEXT:    v_mov_b32_e32 v1, s19
; VI-NEXT:    v_mov_b32_e32 v0, s17
; VI-NEXT:    v_perm_b32 v1, s18, v1, v9
; VI-NEXT:    v_perm_b32 v0, s16, v0, v9
; VI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT:    v_mov_b32_e32 v2, s23
; VI-NEXT:    v_or_b32_e32 v0, v0, v1
; VI-NEXT:    v_mov_b32_e32 v1, s21
; VI-NEXT:    v_perm_b32 v2, s22, v2, v9
; VI-NEXT:    v_perm_b32 v1, s20, v1, v9
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_mov_b32_e32 v3, s27
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_mov_b32_e32 v2, s25
; VI-NEXT:    v_perm_b32 v3, s26, v3, v9
; VI-NEXT:    v_perm_b32 v2, s24, v2, v9
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_mov_b32_e32 v4, s60
; VI-NEXT:    v_or_b32_e32 v2, v2, v3
; VI-NEXT:    v_mov_b32_e32 v3, s29
; VI-NEXT:    v_perm_b32 v4, s61, v4, v9
; VI-NEXT:    v_perm_b32 v3, s28, v3, v9
; VI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT:    v_mov_b32_e32 v5, s56
; VI-NEXT:    v_or_b32_e32 v3, v3, v4
; VI-NEXT:    v_mov_b32_e32 v4, s57
; VI-NEXT:    v_perm_b32 v5, s58, v5, v9
; VI-NEXT:    v_perm_b32 v4, s59, v4, v9
; VI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT:    v_mov_b32_e32 v6, s44
; VI-NEXT:    v_or_b32_e32 v4, v4, v5
; VI-NEXT:    v_mov_b32_e32 v5, s45
; VI-NEXT:    v_perm_b32 v6, s46, v6, v9
; VI-NEXT:    v_perm_b32 v5, s47, v5, v9
; VI-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT:    v_mov_b32_e32 v7, s40
; VI-NEXT:    v_or_b32_e32 v5, v5, v6
; VI-NEXT:    v_mov_b32_e32 v6, s41
; VI-NEXT:    v_perm_b32 v7, s42, v7, v9
; VI-NEXT:    v_perm_b32 v6, s43, v6, v9
; VI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT:    v_mov_b32_e32 v8, s12
; VI-NEXT:    v_or_b32_e32 v6, v6, v7
; VI-NEXT:    v_mov_b32_e32 v7, s13
; VI-NEXT:    v_perm_b32 v8, s14, v8, v9
; VI-NEXT:    v_perm_b32 v7, s15, v7, v9
; VI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT:    v_mov_b32_e32 v10, s8
; VI-NEXT:    v_or_b32_e32 v7, v7, v8
; VI-NEXT:    v_mov_b32_e32 v8, s9
; VI-NEXT:    v_perm_b32 v10, s10, v10, v9
; VI-NEXT:    v_perm_b32 v8, s11, v8, v9
; VI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT:    v_or_b32_e32 v8, v8, v10
; VI-NEXT:    v_mov_b32_e32 v10, s4
; VI-NEXT:    v_mov_b32_e32 v11, s5
; VI-NEXT:    v_perm_b32 v10, s6, v10, v9
; VI-NEXT:    v_perm_b32 v9, s7, v11, v9
; VI-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT:    v_or_b32_e32 v9, v10, v9
; VI-NEXT:    s_setpc_b64 s[30:31]
; VI-NEXT:  .LBB51_2: ; %cmp.true
; VI-NEXT:    s_add_i32 s7, s7, 3
; VI-NEXT:    v_mov_b32_e32 v0, s5
; VI-NEXT:    v_mov_b32_e32 v1, 0xc0c0004
; VI-NEXT:    v_perm_b32 v0, s7, v0, v1
; VI-NEXT:    v_lshlrev_b32_e32 v9, 16, v0
; VI-NEXT:    s_add_i32 s6, s6, 3
; VI-NEXT:    v_mov_b32_e32 v0, s4
; VI-NEXT:    v_perm_b32 v0, s6, v0, v1
; VI-NEXT:    v_add_u32_e32 v10, vcc, 0x300, v0
; VI-NEXT:    s_add_i32 s10, s10, 3
; VI-NEXT:    v_mov_b32_e32 v0, s8
; VI-NEXT:    v_perm_b32 v0, s10, v0, v1
; VI-NEXT:    v_lshlrev_b32_e32 v8, 16, v0
; VI-NEXT:    s_add_i32 s11, s11, 3
; VI-NEXT:    v_mov_b32_e32 v0, s9
; VI-NEXT:    v_perm_b32 v0, s11, v0, v1
; VI-NEXT:    v_add_u32_e32 v11, vcc, 0x300, v0
; VI-NEXT:    s_add_i32 s14, s14, 3
; VI-NEXT:    v_mov_b32_e32 v0, s12
; VI-NEXT:    v_perm_b32 v0, s14, v0, v1
; VI-NEXT:    v_lshlrev_b32_e32 v7, 16, v0
; VI-NEXT:    s_add_i32 s15, s15, 3
; VI-NEXT:    v_mov_b32_e32 v0, s13
; VI-NEXT:    v_perm_b32 v0, s15, v0, v1
; VI-NEXT:    v_add_u32_e32 v12, vcc, 0x300, v0
; VI-NEXT:    s_add_i32 s42, s42, 3
; VI-NEXT:    v_mov_b32_e32 v0, s40
; VI-NEXT:    v_perm_b32 v0, s42, v0, v1
; VI-NEXT:    v_lshlrev_b32_e32 v6, 16, v0
; VI-NEXT:    s_add_i32 s43, s43, 3
; VI-NEXT:    v_mov_b32_e32 v0, s41
; VI-NEXT:    v_perm_b32 v0, s43, v0, v1
; VI-NEXT:    v_add_u32_e32 v13, vcc, 0x300, v0
; VI-NEXT:    s_add_i32 s46, s46, 3
; VI-NEXT:    v_mov_b32_e32 v0, s44
; VI-NEXT:    v_perm_b32 v0, s46, v0, v1
; VI-NEXT:    v_lshlrev_b32_e32 v5, 16, v0
; VI-NEXT:    s_add_i32 s47, s47, 3
; VI-NEXT:    v_mov_b32_e32 v0, s45
; VI-NEXT:    v_perm_b32 v0, s47, v0, v1
; VI-NEXT:    v_add_u32_e32 v14, vcc, 0x300, v0
; VI-NEXT:    s_add_i32 s58, s58, 3
; VI-NEXT:    v_mov_b32_e32 v0, s56
; VI-NEXT:    v_perm_b32 v0, s58, v0, v1
; VI-NEXT:    v_lshlrev_b32_e32 v4, 16, v0
; VI-NEXT:    s_add_i32 s59, s59, 3
; VI-NEXT:    v_mov_b32_e32 v0, s57
; VI-NEXT:    v_perm_b32 v0, s59, v0, v1
; VI-NEXT:    v_add_u32_e32 v15, vcc, 0x300, v0
; VI-NEXT:    s_add_i32 s61, s61, 3
; VI-NEXT:    v_mov_b32_e32 v0, s60
; VI-NEXT:    v_perm_b32 v0, s61, v0, v1
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v0
; VI-NEXT:    s_add_i32 s28, s28, 3
; VI-NEXT:    v_mov_b32_e32 v0, s29
; VI-NEXT:    v_perm_b32 v0, s28, v0, v1
; VI-NEXT:    v_add_u32_e32 v16, vcc, 0x300, v0
; VI-NEXT:    s_add_i32 s26, s26, 3
; VI-NEXT:    v_mov_b32_e32 v0, s27
; VI-NEXT:    v_perm_b32 v0, s26, v0, v1
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v0
; VI-NEXT:    s_add_i32 s24, s24, 3
; VI-NEXT:    v_mov_b32_e32 v0, s25
; VI-NEXT:    v_perm_b32 v0, s24, v0, v1
; VI-NEXT:    v_add_u32_e32 v17, vcc, 0x300, v0
; VI-NEXT:    s_add_i32 s22, s22, 3
; VI-NEXT:    v_mov_b32_e32 v0, s23
; VI-NEXT:    v_perm_b32 v0, s22, v0, v1
; VI-NEXT:    v_lshlrev_b32_e32 v18, 16, v0
; VI-NEXT:    s_add_i32 s20, s20, 3
; VI-NEXT:    v_mov_b32_e32 v0, s21
; VI-NEXT:    v_perm_b32 v0, s20, v0, v1
; VI-NEXT:    v_add_u32_e32 v19, vcc, 0x300, v0
; VI-NEXT:    s_add_i32 s18, s18, 3
; VI-NEXT:    v_mov_b32_e32 v0, s19
; VI-NEXT:    s_add_i32 s16, s16, 3
; VI-NEXT:    v_mov_b32_e32 v20, s17
; VI-NEXT:    v_perm_b32 v0, s18, v0, v1
; VI-NEXT:    v_perm_b32 v1, s16, v20, v1
; VI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
; VI-NEXT:    v_add_u32_e32 v1, vcc, 0x300, v1
; VI-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    v_or_b32_sdwa v1, v18, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    v_or_b32_sdwa v2, v2, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    v_or_b32_sdwa v3, v3, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    v_or_b32_sdwa v4, v4, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    v_or_b32_sdwa v5, v5, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    v_or_b32_sdwa v6, v6, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    v_or_b32_sdwa v7, v7, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    v_or_b32_sdwa v8, v8, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    v_or_b32_sdwa v9, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    v_add_u32_e32 v0, vcc, 0x3000000, v0
; VI-NEXT:    v_add_u32_e32 v1, vcc, 0x3000000, v1
; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x3000000, v2
; VI-NEXT:    v_add_u32_e32 v3, vcc, 0x3000000, v3
; VI-NEXT:    v_add_u32_e32 v4, vcc, 0x3000000, v4
; VI-NEXT:    v_add_u32_e32 v5, vcc, 0x3000000, v5
; VI-NEXT:    v_add_u32_e32 v6, vcc, 0x3000000, v6
; VI-NEXT:    v_add_u32_e32 v7, vcc, 0x3000000, v7
; VI-NEXT:    v_add_u32_e32 v8, vcc, 0x3000000, v8
; VI-NEXT:    v_add_u32_e32 v9, vcc, 0x3000000, v9
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v40i8_to_v20i16_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_readfirstlane_b32 s58, v26
; GFX9-NEXT:    v_readfirstlane_b32 s4, v25
; GFX9-NEXT:    v_readfirstlane_b32 s6, v24
; GFX9-NEXT:    v_readfirstlane_b32 s14, v23
; GFX9-NEXT:    v_readfirstlane_b32 s40, v22
; GFX9-NEXT:    v_readfirstlane_b32 s5, v21
; GFX9-NEXT:    v_readfirstlane_b32 s7, v20
; GFX9-NEXT:    v_readfirstlane_b32 s12, v19
; GFX9-NEXT:    v_readfirstlane_b32 s43, v18
; GFX9-NEXT:    v_readfirstlane_b32 s8, v17
; GFX9-NEXT:    v_readfirstlane_b32 s9, v16
; GFX9-NEXT:    v_readfirstlane_b32 s44, v15
; GFX9-NEXT:    v_readfirstlane_b32 s46, v14
; GFX9-NEXT:    v_readfirstlane_b32 s10, v13
; GFX9-NEXT:    v_readfirstlane_b32 s11, v12
; GFX9-NEXT:    v_readfirstlane_b32 s47, v11
; GFX9-NEXT:    v_readfirstlane_b32 s56, v10
; GFX9-NEXT:    v_readfirstlane_b32 s13, v9
; GFX9-NEXT:    v_readfirstlane_b32 s15, v8
; GFX9-NEXT:    v_readfirstlane_b32 s57, v7
; GFX9-NEXT:    v_readfirstlane_b32 s59, v6
; GFX9-NEXT:    v_readfirstlane_b32 s41, v5
; GFX9-NEXT:    v_readfirstlane_b32 s42, v4
; GFX9-NEXT:    v_readfirstlane_b32 s60, v3
; GFX9-NEXT:    v_readfirstlane_b32 s61, v2
; GFX9-NEXT:    v_readfirstlane_b32 s45, v1
; GFX9-NEXT:    s_cmp_lg_u32 s58, 0
; GFX9-NEXT:    v_readfirstlane_b32 s58, v0
; GFX9-NEXT:    s_cbranch_scc0 .LBB51_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    v_mov_b32_e32 v9, 0xc0c0004
; GFX9-NEXT:    v_mov_b32_e32 v1, s19
; GFX9-NEXT:    v_mov_b32_e32 v0, s17
; GFX9-NEXT:    v_perm_b32 v1, s18, v1, v9
; GFX9-NEXT:    v_perm_b32 v0, s16, v0, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT:    v_mov_b32_e32 v2, s23
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_mov_b32_e32 v1, s21
; GFX9-NEXT:    v_perm_b32 v2, s22, v2, v9
; GFX9-NEXT:    v_perm_b32 v1, s20, v1, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT:    v_mov_b32_e32 v3, s27
; GFX9-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_mov_b32_e32 v2, s25
; GFX9-NEXT:    v_perm_b32 v3, s26, v3, v9
; GFX9-NEXT:    v_perm_b32 v2, s24, v2, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT:    v_mov_b32_e32 v4, s45
; GFX9-NEXT:    v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_mov_b32_e32 v3, s29
; GFX9-NEXT:    v_perm_b32 v4, s58, v4, v9
; GFX9-NEXT:    v_perm_b32 v3, s28, v3, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; GFX9-NEXT:    v_mov_b32_e32 v5, s41
; GFX9-NEXT:    v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_mov_b32_e32 v4, s60
; GFX9-NEXT:    v_perm_b32 v5, s42, v5, v9
; GFX9-NEXT:    v_perm_b32 v4, s61, v4, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; GFX9-NEXT:    v_mov_b32_e32 v6, s13
; GFX9-NEXT:    v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_mov_b32_e32 v5, s57
; GFX9-NEXT:    v_perm_b32 v6, s15, v6, v9
; GFX9-NEXT:    v_perm_b32 v5, s59, v5, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; GFX9-NEXT:    v_mov_b32_e32 v7, s10
; GFX9-NEXT:    v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_mov_b32_e32 v6, s47
; GFX9-NEXT:    v_perm_b32 v7, s11, v7, v9
; GFX9-NEXT:    v_perm_b32 v6, s56, v6, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; GFX9-NEXT:    v_mov_b32_e32 v8, s8
; GFX9-NEXT:    v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_mov_b32_e32 v7, s44
; GFX9-NEXT:    v_perm_b32 v8, s9, v8, v9
; GFX9-NEXT:    v_perm_b32 v7, s46, v7, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; GFX9-NEXT:    v_mov_b32_e32 v10, 0x6050400
; GFX9-NEXT:    v_mov_b32_e32 v11, s7
; GFX9-NEXT:    v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_mov_b32_e32 v8, s43
; GFX9-NEXT:    v_perm_b32 v11, s5, v11, v10
; GFX9-NEXT:    v_perm_b32 v8, s12, v8, v10
; GFX9-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; GFX9-NEXT:    v_or_b32_sdwa v8, v11, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_mov_b32_e32 v11, s14
; GFX9-NEXT:    v_perm_b32 v9, s40, v11, v9
; GFX9-NEXT:    v_mov_b32_e32 v11, s6
; GFX9-NEXT:    v_perm_b32 v10, s4, v11, v10
; GFX9-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; GFX9-NEXT:    v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
; GFX9-NEXT:  .LBB51_2: ; %cmp.true
; GFX9-NEXT:    s_add_i32 s40, s40, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s14
; GFX9-NEXT:    v_mov_b32_e32 v1, 0xc0c0004
; GFX9-NEXT:    v_perm_b32 v0, s40, v0, v1
; GFX9-NEXT:    v_add_u32_e32 v9, 0x300, v0
; GFX9-NEXT:    s_add_i32 s6, s6, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s4
; GFX9-NEXT:    s_movk_i32 s14, 0x300
; GFX9-NEXT:    v_perm_b32 v0, s6, v0, v1
; GFX9-NEXT:    v_add_u32_sdwa v10, v0, s14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s43, s43, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s12
; GFX9-NEXT:    v_perm_b32 v0, s43, v0, v1
; GFX9-NEXT:    v_add_u32_e32 v8, 0x300, v0
; GFX9-NEXT:    s_add_i32 s7, s7, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s5
; GFX9-NEXT:    v_perm_b32 v0, s7, v0, v1
; GFX9-NEXT:    v_add_u32_sdwa v11, v0, s14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s46, s46, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s44
; GFX9-NEXT:    v_perm_b32 v0, s46, v0, v1
; GFX9-NEXT:    v_add_u32_e32 v7, 0x300, v0
; GFX9-NEXT:    s_add_i32 s9, s9, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s8
; GFX9-NEXT:    v_perm_b32 v0, s9, v0, v1
; GFX9-NEXT:    v_add_u32_sdwa v12, v0, s14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s56, s56, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s47
; GFX9-NEXT:    v_perm_b32 v0, s56, v0, v1
; GFX9-NEXT:    v_add_u32_e32 v6, 0x300, v0
; GFX9-NEXT:    s_add_i32 s11, s11, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s10
; GFX9-NEXT:    v_perm_b32 v0, s11, v0, v1
; GFX9-NEXT:    v_add_u32_sdwa v13, v0, s14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s59, s59, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s57
; GFX9-NEXT:    v_perm_b32 v0, s59, v0, v1
; GFX9-NEXT:    v_add_u32_e32 v5, 0x300, v0
; GFX9-NEXT:    s_add_i32 s15, s15, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s13
; GFX9-NEXT:    v_perm_b32 v0, s15, v0, v1
; GFX9-NEXT:    v_add_u32_sdwa v14, v0, s14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s61, s61, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s60
; GFX9-NEXT:    v_perm_b32 v0, s61, v0, v1
; GFX9-NEXT:    v_add_u32_e32 v4, 0x300, v0
; GFX9-NEXT:    s_add_i32 s42, s42, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s41
; GFX9-NEXT:    v_perm_b32 v0, s42, v0, v1
; GFX9-NEXT:    v_add_u32_sdwa v15, v0, s14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s28, s28, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s29
; GFX9-NEXT:    v_perm_b32 v0, s28, v0, v1
; GFX9-NEXT:    v_add_u32_e32 v3, 0x300, v0
; GFX9-NEXT:    s_add_i32 s58, s58, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s45
; GFX9-NEXT:    v_perm_b32 v0, s58, v0, v1
; GFX9-NEXT:    v_add_u32_sdwa v16, v0, s14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s24, s24, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s25
; GFX9-NEXT:    v_perm_b32 v0, s24, v0, v1
; GFX9-NEXT:    v_add_u32_e32 v2, 0x300, v0
; GFX9-NEXT:    s_add_i32 s26, s26, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s27
; GFX9-NEXT:    v_perm_b32 v0, s26, v0, v1
; GFX9-NEXT:    v_add_u32_sdwa v17, v0, s14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s20, s20, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s21
; GFX9-NEXT:    v_perm_b32 v0, s20, v0, v1
; GFX9-NEXT:    v_add_u32_e32 v18, 0x300, v0
; GFX9-NEXT:    s_add_i32 s22, s22, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s23
; GFX9-NEXT:    v_perm_b32 v0, s22, v0, v1
; GFX9-NEXT:    v_add_u32_sdwa v19, v0, s14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s16, s16, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s17
; GFX9-NEXT:    s_add_i32 s18, s18, 3
; GFX9-NEXT:    v_mov_b32_e32 v20, s19
; GFX9-NEXT:    v_perm_b32 v0, s16, v0, v1
; GFX9-NEXT:    v_perm_b32 v1, s18, v20, v1
; GFX9-NEXT:    v_add_u32_e32 v0, 0x300, v0
; GFX9-NEXT:    v_add_u32_sdwa v1, v1, s14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_or_b32_sdwa v1, v19, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_or_b32_sdwa v2, v17, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_or_b32_sdwa v3, v16, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_or_b32_sdwa v4, v15, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_or_b32_sdwa v5, v14, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_or_b32_sdwa v6, v13, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_or_b32_sdwa v7, v12, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_or_b32_sdwa v8, v11, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v40i8_to_v20i16_scalar:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s58, v22
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s4, v21
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s6, v20
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s5, v19
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s8, v18
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s9, v17
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s11, v16
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s7, v15
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s10, v14
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s12, v13
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s13, v12
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s14, v11
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s15, v10
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s40, v9
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s43, v8
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s41, v7
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s42, v6
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s44, v5
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s45, v4
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s46, v3
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s56, v2
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s47, v1
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s57, v0
; GFX11-TRUE16-NEXT:    s_cmp_lg_u32 s58, 0
; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB51_2
; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v9, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v8, 0x6050400
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_perm_b32 v3, s2, s3, v9
; GFX11-TRUE16-NEXT:    v_perm_b32 v5, s22, s23, v9
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, s26, s27, v9
; GFX11-TRUE16-NEXT:    v_perm_b32 v0, s0, s1, v9
; GFX11-TRUE16-NEXT:    v_perm_b32 v4, s18, s19, v9
; GFX11-TRUE16-NEXT:    v_perm_b32 v2, s20, s21, v9
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v3.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v5.l
; GFX11-TRUE16-NEXT:    v_perm_b32 v5, s57, s47, v9
; GFX11-TRUE16-NEXT:    v_perm_b32 v3, s24, s25, v9
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v6.l
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, s45, s44, v9
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, s43, s40, v9
; GFX11-TRUE16-NEXT:    v_perm_b32 v1, s16, s17, v9
; GFX11-TRUE16-NEXT:    v_perm_b32 v10, s13, s12, v9
; GFX11-TRUE16-NEXT:    v_perm_b32 v11, s9, s11, v8
; GFX11-TRUE16-NEXT:    v_perm_b32 v12, s4, s6, v8
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT:    v_perm_b32 v4, s28, s29, v9
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v5.l
; GFX11-TRUE16-NEXT:    v_perm_b32 v5, s56, s46, v9
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v6.l
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, s42, s41, v9
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v7.l
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, s15, s14, v9
; GFX11-TRUE16-NEXT:    v_perm_b32 v8, s7, s10, v8
; GFX11-TRUE16-NEXT:    v_perm_b32 v9, s8, s5, v9
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.h, v10.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.h, v11.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.h, v12.l
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT:  .LBB51_2: ; %cmp.true
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, 0xc0c0004
; GFX11-TRUE16-NEXT:    s_add_i32 s8, s8, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s15, s15, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s6, s6, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s11, s11, 3
; GFX11-TRUE16-NEXT:    v_perm_b32 v1, s8, s5, v0
; GFX11-TRUE16-NEXT:    s_add_i32 s13, s13, 3
; GFX11-TRUE16-NEXT:    v_perm_b32 v2, s6, s4, v0
; GFX11-TRUE16-NEXT:    v_perm_b32 v4, s11, s9, v0
; GFX11-TRUE16-NEXT:    s_add_i32 s42, s42, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v9, 0x300, v1
; GFX11-TRUE16-NEXT:    v_perm_b32 v1, s15, s14, v0
; GFX11-TRUE16-NEXT:    s_add_i32 s56, s56, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s28, s28, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v10, 0x300, v2
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v11, 0x300, v4
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v7, 0x300, v1
; GFX11-TRUE16-NEXT:    v_perm_b32 v1, s13, s12, v0
; GFX11-TRUE16-NEXT:    v_perm_b32 v2, s42, s41, v0
; GFX11-TRUE16-NEXT:    v_perm_b32 v4, s56, s46, v0
; GFX11-TRUE16-NEXT:    s_add_i32 s10, s10, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s57, s57, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v13, 0x300, v1
; GFX11-TRUE16-NEXT:    v_perm_b32 v1, s28, s29, v0
; GFX11-TRUE16-NEXT:    s_add_i32 s20, s20, 3
; GFX11-TRUE16-NEXT:    v_perm_b32 v3, s10, s7, v0
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v6, 0x300, v2
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v5, 0x300, v4
; GFX11-TRUE16-NEXT:    v_perm_b32 v2, s57, s47, v0
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v4, 0x300, v1
; GFX11-TRUE16-NEXT:    v_perm_b32 v1, s20, s21, v0
; GFX11-TRUE16-NEXT:    s_add_i32 s43, s43, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s45, s45, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s26, s26, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s22, s22, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s18, s18, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v8, 0x300, v3
; GFX11-TRUE16-NEXT:    v_perm_b32 v3, s43, s40, v0
; GFX11-TRUE16-NEXT:    v_perm_b32 v12, s45, s44, v0
; GFX11-TRUE16-NEXT:    v_perm_b32 v15, s26, s27, v0
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v16, 0x300, v2
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, 0x300, v1
; GFX11-TRUE16-NEXT:    v_perm_b32 v1, s22, s23, v0
; GFX11-TRUE16-NEXT:    v_perm_b32 v17, s2, s3, v0
; GFX11-TRUE16-NEXT:    v_perm_b32 v18, s18, s19, v0
; GFX11-TRUE16-NEXT:    s_add_i32 s24, s24, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s16, s16, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s0, s0, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v14, 0x300, v3
; GFX11-TRUE16-NEXT:    v_perm_b32 v3, s24, s25, v0
; GFX11-TRUE16-NEXT:    v_perm_b32 v19, s16, s17, v0
; GFX11-TRUE16-NEXT:    v_perm_b32 v0, s0, s1, v0
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v15, 0x300, v15
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v17, 0x300, v17
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v18, 0x300, v18
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v20, 0x300, v1
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v1, 0x300, v19
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v17.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v18.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v20.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v15.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v16.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v12.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v14.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.h, v13.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.h, v11.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.h, v10.l
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v40i8_to_v20i16_scalar:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s58, v22
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s4, v21
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s11, v20
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s10, v19
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s42, v18
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s5, v17
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s12, v16
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s13, v15
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s45, v14
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s6, v13
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s8, v12
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s15, v11
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s44, v10
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s7, v9
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s9, v8
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s40, v7
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s46, v6
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s14, v5
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s41, v4
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s43, v3
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s57, v2
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s47, v1
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s56, v0
; GFX11-FAKE16-NEXT:    s_cmp_lg_u32 s58, 0
; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB51_2
; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, 0xc0c0004
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_perm_b32 v0, s0, s1, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v2, s16, s17, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v4, s20, s21, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, s28, s29, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v1, s2, s3, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v3, s18, s19, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, s22, s23, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, s24, s25, v5
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT:    v_perm_b32 v10, s56, s47, v5
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, s26, s27, v5
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, v6, 16, v4
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v4, v10, 16, v9
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v9, 0x6050400
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v3, v8, 16, v7
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, s57, s43, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, s41, s14, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, s46, s40, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v10, s9, s7, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v11, s44, s15, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v12, s13, s45, v9
; GFX11-FAKE16-NEXT:    v_perm_b32 v13, s8, s6, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v5, s42, s10, v5
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
; GFX11-FAKE16-NEXT:    v_perm_b32 v14, s5, s12, v9
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, s4, s11, v9
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v5
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v5, v7, 16, v6
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v6, v10, 16, v8
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v7, v13, 16, v11
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v8, v14, 16, v12
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v9, v9, 16, v15
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT:  .LBB51_2: ; %cmp.true
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 0xc0c0004
; GFX11-FAKE16-NEXT:    s_add_i32 s42, s42, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s11, s11, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s45, s45, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s12, s12, 3
; GFX11-FAKE16-NEXT:    v_perm_b32 v1, s42, s10, v0
; GFX11-FAKE16-NEXT:    s_add_i32 s44, s44, 3
; GFX11-FAKE16-NEXT:    v_perm_b32 v2, s11, s4, v0
; GFX11-FAKE16-NEXT:    v_perm_b32 v3, s45, s13, v0
; GFX11-FAKE16-NEXT:    v_perm_b32 v4, s12, s5, v0
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v5, 0x300, v1
; GFX11-FAKE16-NEXT:    v_perm_b32 v1, s44, s15, v0
; GFX11-FAKE16-NEXT:    s_add_i32 s8, s8, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s46, s46, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s9, s9, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s57, s57, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v9, 0x300, v2
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v6, 0x300, v3
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v8, 0x300, v4
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v7, 0x300, v1
; GFX11-FAKE16-NEXT:    v_perm_b32 v1, s8, s6, v0
; GFX11-FAKE16-NEXT:    v_perm_b32 v2, s46, s40, v0
; GFX11-FAKE16-NEXT:    v_perm_b32 v3, s9, s7, v0
; GFX11-FAKE16-NEXT:    v_perm_b32 v4, s57, s43, v0
; GFX11-FAKE16-NEXT:    s_add_i32 s28, s28, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s56, s56, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s24, s24, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s26, s26, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s20, s20, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v11, 0x300, v1
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v12, 0x300, v2
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v13, 0x300, v3
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v14, 0x300, v4
; GFX11-FAKE16-NEXT:    v_perm_b32 v1, s28, s29, v0
; GFX11-FAKE16-NEXT:    v_perm_b32 v2, s56, s47, v0
; GFX11-FAKE16-NEXT:    v_perm_b32 v3, s24, s25, v0
; GFX11-FAKE16-NEXT:    v_perm_b32 v4, s26, s27, v0
; GFX11-FAKE16-NEXT:    v_perm_b32 v15, s20, s21, v0
; GFX11-FAKE16-NEXT:    s_add_i32 s22, s22, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s16, s16, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s0, s0, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v16, 0x300, v2
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v2, 0x300, v3
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v3, 0x300, v4
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, 0x300, v15
; GFX11-FAKE16-NEXT:    v_perm_b32 v15, s22, s23, v0
; GFX11-FAKE16-NEXT:    v_perm_b32 v17, s16, s17, v0
; GFX11-FAKE16-NEXT:    v_perm_b32 v18, s0, s1, v0
; GFX11-FAKE16-NEXT:    s_add_i32 s41, s41, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s18, s18, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s2, s2, 3
; GFX11-FAKE16-NEXT:    v_perm_b32 v10, s41, s14, v0
; GFX11-FAKE16-NEXT:    v_perm_b32 v19, s18, s19, v0
; GFX11-FAKE16-NEXT:    v_perm_b32 v0, s2, s3, v0
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v18, 0x300, v18
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v17, 0x300, v17
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v15, 0x300, v15
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xffff, v1
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v10, 0x300, v10
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v19, 0x300, v19
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xffff, v18
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xffff, v17
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xffff, v2
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, v15, 16, v4
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v4, v16, 16, v21
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v6
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff, v5
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v0, 16, v18
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v19, 16, v17
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v3, v3, 16, v20
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v5, v10, 16, v14
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v6, v13, 16, v12
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v7, v11, 16, v7
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v8, v8, 16, v15
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v9, v9, 16, v16
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <40 x i8> %a, splat (i8 3)
  %a2 = bitcast <40 x i8> %a1 to <20 x i16>
  br label %end

cmp.false:
  %a3 = bitcast <40 x i8> %a to <20 x i16>
  br label %end

end:
  %phi = phi <20 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <20 x i16> %phi
}

define <5 x double> @bitcast_v20i16_to_v5f64(<20 x i16> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v20i16_to_v5f64:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_mov_b32_e32 v16, v9
; SI-NEXT:    v_mov_b32_e32 v17, v8
; SI-NEXT:    v_mov_b32_e32 v18, v7
; SI-NEXT:    v_mov_b32_e32 v19, v6
; SI-NEXT:    v_mov_b32_e32 v20, v5
; SI-NEXT:    v_mov_b32_e32 v21, v4
; SI-NEXT:    v_mov_b32_e32 v22, v3
; SI-NEXT:    v_mov_b32_e32 v23, v2
; SI-NEXT:    v_mov_b32_e32 v24, v1
; SI-NEXT:    v_mov_b32_e32 v25, v0
; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v16
; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v17
; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v18
; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v19
; SI-NEXT:    v_lshrrev_b32_e32 v4, 16, v20
; SI-NEXT:    v_lshrrev_b32_e32 v5, 16, v21
; SI-NEXT:    v_lshrrev_b32_e32 v6, 16, v22
; SI-NEXT:    v_lshrrev_b32_e32 v7, 16, v23
; SI-NEXT:    v_lshrrev_b32_e32 v8, 16, v24
; SI-NEXT:    v_lshrrev_b32_e32 v9, 16, v25
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; SI-NEXT:    v_lshlrev_b32_e32 v35, 16, v9
; SI-NEXT:    v_lshlrev_b32_e32 v34, 16, v8
; SI-NEXT:    v_lshlrev_b32_e32 v33, 16, v7
; SI-NEXT:    v_lshlrev_b32_e32 v32, 16, v6
; SI-NEXT:    v_lshlrev_b32_e32 v31, 16, v5
; SI-NEXT:    v_lshlrev_b32_e32 v30, 16, v4
; SI-NEXT:    v_lshlrev_b32_e32 v29, 16, v3
; SI-NEXT:    v_lshlrev_b32_e32 v28, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v27, 16, v1
; SI-NEXT:    v_lshlrev_b32_e32 v26, 16, v0
; SI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_cbranch_execnz .LBB52_3
; SI-NEXT:  ; %bb.1: ; %Flow
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execnz .LBB52_4
; SI-NEXT:  .LBB52_2: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    s_setpc_b64 s[30:31]
; SI-NEXT:  .LBB52_3: ; %cmp.false
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v25
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v24
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v23
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v22
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v21
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v20
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v19
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v18
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v17
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v16
; SI-NEXT:    v_or_b32_e32 v0, v0, v35
; SI-NEXT:    v_or_b32_e32 v1, v1, v34
; SI-NEXT:    v_or_b32_e32 v2, v2, v33
; SI-NEXT:    v_or_b32_e32 v3, v3, v32
; SI-NEXT:    v_or_b32_e32 v4, v4, v31
; SI-NEXT:    v_or_b32_e32 v5, v5, v30
; SI-NEXT:    v_or_b32_e32 v6, v6, v29
; SI-NEXT:    v_or_b32_e32 v7, v7, v28
; SI-NEXT:    v_or_b32_e32 v8, v8, v27
; SI-NEXT:    v_or_b32_e32 v9, v9, v26
; SI-NEXT:    ; implicit-def: $vgpr25
; SI-NEXT:    ; implicit-def: $vgpr24
; SI-NEXT:    ; implicit-def: $vgpr23
; SI-NEXT:    ; implicit-def: $vgpr22
; SI-NEXT:    ; implicit-def: $vgpr21
; SI-NEXT:    ; implicit-def: $vgpr20
; SI-NEXT:    ; implicit-def: $vgpr19
; SI-NEXT:    ; implicit-def: $vgpr18
; SI-NEXT:    ; implicit-def: $vgpr17
; SI-NEXT:    ; implicit-def: $vgpr16
; SI-NEXT:    ; implicit-def: $vgpr35
; SI-NEXT:    ; implicit-def: $vgpr34
; SI-NEXT:    ; implicit-def: $vgpr33
; SI-NEXT:    ; implicit-def: $vgpr32
; SI-NEXT:    ; implicit-def: $vgpr31
; SI-NEXT:    ; implicit-def: $vgpr30
; SI-NEXT:    ; implicit-def: $vgpr29
; SI-NEXT:    ; implicit-def: $vgpr28
; SI-NEXT:    ; implicit-def: $vgpr27
; SI-NEXT:    ; implicit-def: $vgpr26
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB52_2
; SI-NEXT:  .LBB52_4: ; %cmp.true
; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v25
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v24
; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v23
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v22
; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v21
; SI-NEXT:    v_add_i32_e32 v5, vcc, 3, v20
; SI-NEXT:    v_add_i32_e32 v6, vcc, 3, v19
; SI-NEXT:    v_add_i32_e32 v7, vcc, 3, v18
; SI-NEXT:    v_add_i32_e32 v8, vcc, 3, v17
; SI-NEXT:    v_add_i32_e32 v9, vcc, 3, v16
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT:    v_or_b32_e32 v0, v35, v0
; SI-NEXT:    v_or_b32_e32 v1, v34, v1
; SI-NEXT:    v_or_b32_e32 v2, v33, v2
; SI-NEXT:    v_or_b32_e32 v3, v32, v3
; SI-NEXT:    v_or_b32_e32 v4, v31, v4
; SI-NEXT:    v_or_b32_e32 v5, v30, v5
; SI-NEXT:    v_or_b32_e32 v6, v29, v6
; SI-NEXT:    v_or_b32_e32 v7, v28, v7
; SI-NEXT:    v_or_b32_e32 v8, v27, v8
; SI-NEXT:    v_or_b32_e32 v9, v26, v9
; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT:    v_add_i32_e32 v1, vcc, 0x30000, v1
; SI-NEXT:    v_add_i32_e32 v2, vcc, 0x30000, v2
; SI-NEXT:    v_add_i32_e32 v3, vcc, 0x30000, v3
; SI-NEXT:    v_add_i32_e32 v4, vcc, 0x30000, v4
; SI-NEXT:    v_add_i32_e32 v5, vcc, 0x30000, v5
; SI-NEXT:    v_add_i32_e32 v6, vcc, 0x30000, v6
; SI-NEXT:    v_add_i32_e32 v7, vcc, 0x30000, v7
; SI-NEXT:    v_add_i32_e32 v8, vcc, 0x30000, v8
; SI-NEXT:    v_add_i32_e32 v9, vcc, 0x30000, v9
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v20i16_to_v5f64:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB52_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    v_mov_b32_e32 v11, 3
; VI-NEXT:    v_add_u16_e32 v10, 3, v9
; VI-NEXT:    v_add_u16_sdwa v9, v9, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v9, v10, v9
; VI-NEXT:    v_add_u16_e32 v10, 3, v8
; VI-NEXT:    v_add_u16_sdwa v8, v8, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v8, v10, v8
; VI-NEXT:    v_add_u16_e32 v10, 3, v7
; VI-NEXT:    v_add_u16_sdwa v7, v7, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v7, v10, v7
; VI-NEXT:    v_add_u16_e32 v10, 3, v6
; VI-NEXT:    v_add_u16_sdwa v6, v6, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v6, v10, v6
; VI-NEXT:    v_add_u16_e32 v10, 3, v5
; VI-NEXT:    v_add_u16_sdwa v5, v5, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v5, v10, v5
; VI-NEXT:    v_add_u16_e32 v10, 3, v4
; VI-NEXT:    v_add_u16_sdwa v4, v4, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v4, v10, v4
; VI-NEXT:    v_add_u16_e32 v10, 3, v3
; VI-NEXT:    v_add_u16_sdwa v3, v3, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v3, v10, v3
; VI-NEXT:    v_add_u16_e32 v10, 3, v2
; VI-NEXT:    v_add_u16_sdwa v2, v2, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v2, v10, v2
; VI-NEXT:    v_add_u16_e32 v10, 3, v1
; VI-NEXT:    v_add_u16_sdwa v1, v1, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v1, v10, v1
; VI-NEXT:    v_add_u16_e32 v10, 3, v0
; VI-NEXT:    v_add_u16_sdwa v0, v0, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v0, v10, v0
; VI-NEXT:  .LBB52_2: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v20i16_to_v5f64:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB52_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX9-NEXT:  .LBB52_2: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v20i16_to_v5f64:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB52_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-NEXT:  .LBB52_2: ; %end
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <20 x i16> %a, splat (i16 3)
  %a2 = bitcast <20 x i16> %a1 to <5 x double>
  br label %end

cmp.false:
  %a3 = bitcast <20 x i16> %a to <5 x double>
  br label %end

end:
  %phi = phi <5 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <5 x double> %phi
}

define inreg <5 x double> @bitcast_v20i16_to_v5f64_scalar(<20 x i16> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v20i16_to_v5f64_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_lshr_b32 s11, s25, 16
; SI-NEXT:    s_lshr_b32 s13, s24, 16
; SI-NEXT:    s_lshr_b32 s12, s23, 16
; SI-NEXT:    s_lshr_b32 s10, s22, 16
; SI-NEXT:    s_lshr_b32 s9, s21, 16
; SI-NEXT:    s_lshr_b32 s8, s20, 16
; SI-NEXT:    s_lshr_b32 s7, s19, 16
; SI-NEXT:    s_lshr_b32 s6, s18, 16
; SI-NEXT:    s_lshr_b32 s5, s17, 16
; SI-NEXT:    s_lshr_b32 s4, s16, 16
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc0 .LBB53_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    s_and_b32 s14, s16, 0xffff
; SI-NEXT:    s_lshl_b32 s4, s4, 16
; SI-NEXT:    s_or_b32 s4, s14, s4
; SI-NEXT:    s_and_b32 s14, s17, 0xffff
; SI-NEXT:    s_lshl_b32 s5, s5, 16
; SI-NEXT:    s_or_b32 s5, s14, s5
; SI-NEXT:    s_and_b32 s14, s18, 0xffff
; SI-NEXT:    s_lshl_b32 s6, s6, 16
; SI-NEXT:    s_or_b32 s6, s14, s6
; SI-NEXT:    s_and_b32 s14, s19, 0xffff
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_or_b32 s7, s14, s7
; SI-NEXT:    s_and_b32 s14, s20, 0xffff
; SI-NEXT:    s_lshl_b32 s8, s8, 16
; SI-NEXT:    s_or_b32 s8, s14, s8
; SI-NEXT:    s_and_b32 s14, s21, 0xffff
; SI-NEXT:    s_lshl_b32 s9, s9, 16
; SI-NEXT:    s_or_b32 s9, s14, s9
; SI-NEXT:    s_and_b32 s14, s22, 0xffff
; SI-NEXT:    s_lshl_b32 s10, s10, 16
; SI-NEXT:    s_or_b32 s10, s14, s10
; SI-NEXT:    s_and_b32 s14, s23, 0xffff
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_or_b32 s12, s14, s12
; SI-NEXT:    s_and_b32 s14, s24, 0xffff
; SI-NEXT:    s_lshl_b32 s13, s13, 16
; SI-NEXT:    s_or_b32 s13, s14, s13
; SI-NEXT:    s_and_b32 s14, s25, 0xffff
; SI-NEXT:    s_lshl_b32 s11, s11, 16
; SI-NEXT:    s_or_b32 s11, s14, s11
; SI-NEXT:    s_branch .LBB53_3
; SI-NEXT:  .LBB53_2: ; %cmp.true
; SI-NEXT:    s_add_i32 s16, s16, 3
; SI-NEXT:    s_and_b32 s14, s16, 0xffff
; SI-NEXT:    s_lshl_b32 s4, s4, 16
; SI-NEXT:    s_add_i32 s17, s17, 3
; SI-NEXT:    s_or_b32 s4, s4, s14
; SI-NEXT:    s_and_b32 s14, s17, 0xffff
; SI-NEXT:    s_lshl_b32 s5, s5, 16
; SI-NEXT:    s_add_i32 s18, s18, 3
; SI-NEXT:    s_or_b32 s5, s5, s14
; SI-NEXT:    s_and_b32 s14, s18, 0xffff
; SI-NEXT:    s_lshl_b32 s6, s6, 16
; SI-NEXT:    s_add_i32 s19, s19, 3
; SI-NEXT:    s_or_b32 s6, s6, s14
; SI-NEXT:    s_and_b32 s14, s19, 0xffff
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_add_i32 s20, s20, 3
; SI-NEXT:    s_or_b32 s7, s7, s14
; SI-NEXT:    s_and_b32 s14, s20, 0xffff
; SI-NEXT:    s_lshl_b32 s8, s8, 16
; SI-NEXT:    s_add_i32 s21, s21, 3
; SI-NEXT:    s_or_b32 s8, s8, s14
; SI-NEXT:    s_and_b32 s14, s21, 0xffff
; SI-NEXT:    s_lshl_b32 s9, s9, 16
; SI-NEXT:    s_add_i32 s22, s22, 3
; SI-NEXT:    s_or_b32 s9, s9, s14
; SI-NEXT:    s_and_b32 s14, s22, 0xffff
; SI-NEXT:    s_lshl_b32 s10, s10, 16
; SI-NEXT:    s_add_i32 s23, s23, 3
; SI-NEXT:    s_or_b32 s10, s10, s14
; SI-NEXT:    s_and_b32 s14, s23, 0xffff
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_add_i32 s24, s24, 3
; SI-NEXT:    s_or_b32 s12, s12, s14
; SI-NEXT:    s_and_b32 s14, s24, 0xffff
; SI-NEXT:    s_lshl_b32 s13, s13, 16
; SI-NEXT:    s_add_i32 s25, s25, 3
; SI-NEXT:    s_or_b32 s13, s13, s14
; SI-NEXT:    s_and_b32 s14, s25, 0xffff
; SI-NEXT:    s_lshl_b32 s11, s11, 16
; SI-NEXT:    s_or_b32 s11, s11, s14
; SI-NEXT:    s_add_i32 s4, s4, 0x30000
; SI-NEXT:    s_add_i32 s5, s5, 0x30000
; SI-NEXT:    s_add_i32 s6, s6, 0x30000
; SI-NEXT:    s_add_i32 s7, s7, 0x30000
; SI-NEXT:    s_add_i32 s8, s8, 0x30000
; SI-NEXT:    s_add_i32 s9, s9, 0x30000
; SI-NEXT:    s_add_i32 s10, s10, 0x30000
; SI-NEXT:    s_add_i32 s12, s12, 0x30000
; SI-NEXT:    s_add_i32 s13, s13, 0x30000
; SI-NEXT:    s_add_i32 s11, s11, 0x30000
; SI-NEXT:  .LBB53_3: ; %end
; SI-NEXT:    v_mov_b32_e32 v0, s4
; SI-NEXT:    v_mov_b32_e32 v1, s5
; SI-NEXT:    v_mov_b32_e32 v2, s6
; SI-NEXT:    v_mov_b32_e32 v3, s7
; SI-NEXT:    v_mov_b32_e32 v4, s8
; SI-NEXT:    v_mov_b32_e32 v5, s9
; SI-NEXT:    v_mov_b32_e32 v6, s10
; SI-NEXT:    v_mov_b32_e32 v7, s12
; SI-NEXT:    v_mov_b32_e32 v8, s13
; SI-NEXT:    v_mov_b32_e32 v9, s11
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v20i16_to_v5f64_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc1 .LBB53_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    s_add_i32 s5, s25, 3
; VI-NEXT:    s_and_b32 s4, s25, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s24, 3
; VI-NEXT:    s_add_i32 s25, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s24, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s23, 3
; VI-NEXT:    s_add_i32 s24, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s23, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s22, 3
; VI-NEXT:    s_add_i32 s23, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s22, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s21, 3
; VI-NEXT:    s_add_i32 s22, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s21, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s20, 3
; VI-NEXT:    s_add_i32 s21, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s20, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s19, 3
; VI-NEXT:    s_add_i32 s20, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s19, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s18, 3
; VI-NEXT:    s_add_i32 s19, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s18, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s17, 3
; VI-NEXT:    s_add_i32 s18, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s17, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s16, 3
; VI-NEXT:    s_add_i32 s17, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s16, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s16, s4, 0x30000
; VI-NEXT:  .LBB53_2: ; %end
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s17
; VI-NEXT:    v_mov_b32_e32 v2, s18
; VI-NEXT:    v_mov_b32_e32 v3, s19
; VI-NEXT:    v_mov_b32_e32 v4, s20
; VI-NEXT:    v_mov_b32_e32 v5, s21
; VI-NEXT:    v_mov_b32_e32 v6, s22
; VI-NEXT:    v_mov_b32_e32 v7, s23
; VI-NEXT:    v_mov_b32_e32 v8, s24
; VI-NEXT:    v_mov_b32_e32 v9, s25
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v20i16_to_v5f64_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc0 .LBB53_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s17
; GFX9-NEXT:    v_mov_b32_e32 v2, s18
; GFX9-NEXT:    v_mov_b32_e32 v3, s19
; GFX9-NEXT:    v_mov_b32_e32 v4, s20
; GFX9-NEXT:    v_mov_b32_e32 v5, s21
; GFX9-NEXT:    v_mov_b32_e32 v6, s22
; GFX9-NEXT:    v_mov_b32_e32 v7, s23
; GFX9-NEXT:    v_mov_b32_e32 v8, s24
; GFX9-NEXT:    v_mov_b32_e32 v9, s25
; GFX9-NEXT:    v_mov_b32_e32 v10, s26
; GFX9-NEXT:    v_mov_b32_e32 v11, s27
; GFX9-NEXT:    v_mov_b32_e32 v12, s28
; GFX9-NEXT:    v_mov_b32_e32 v13, s29
; GFX9-NEXT:    v_mov_b32_e32 v14, s30
; GFX9-NEXT:    v_mov_b32_e32 v15, s31
; GFX9-NEXT:    s_setpc_b64 s[30:31]
; GFX9-NEXT:  .LBB53_2: ; %cmp.true
; GFX9-NEXT:    v_pk_add_u16 v9, s25, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v8, s24, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v7, s23, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v6, s22, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v5, s21, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v4, s20, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v3, s19, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v20i16_to_v5f64_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s15, s3
; GFX11-NEXT:    s_mov_b32 s14, s2
; GFX11-NEXT:    s_mov_b32 s13, s1
; GFX11-NEXT:    s_mov_b32 s12, s0
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc0 .LBB53_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-NEXT:    v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
; GFX11-NEXT:    v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT:    v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
; GFX11-NEXT:    v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
; GFX11-NEXT:    v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
; GFX11-NEXT:    s_setpc_b64 s[30:31]
; GFX11-NEXT:  .LBB53_2: ; %cmp.true
; GFX11-NEXT:    v_pk_add_u16 v9, s21, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v8, s20, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v7, s19, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v6, s18, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v5, s17, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v4, s16, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v3, s15, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v2, s14, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v1, s13, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v0, s12, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <20 x i16> %a, splat (i16 3)
  %a2 = bitcast <20 x i16> %a1 to <5 x double>
  br label %end

cmp.false:
  %a3 = bitcast <20 x i16> %a to <5 x double>
  br label %end

end:
  %phi = phi <5 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <5 x double> %phi
}

define <20 x i16> @bitcast_v5f64_to_v20i16(<5 x double> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v5f64_to_v20i16:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; SI-NEXT:    ; implicit-def: $vgpr16
; SI-NEXT:    ; implicit-def: $vgpr19
; SI-NEXT:    ; implicit-def: $vgpr13
; SI-NEXT:    ; implicit-def: $vgpr18
; SI-NEXT:    ; implicit-def: $vgpr12
; SI-NEXT:    ; implicit-def: $vgpr17
; SI-NEXT:    ; implicit-def: $vgpr11
; SI-NEXT:    ; implicit-def: $vgpr15
; SI-NEXT:    ; implicit-def: $vgpr10
; SI-NEXT:    ; implicit-def: $vgpr14
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB54_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    v_alignbit_b32 v10, v9, v8, 16
; SI-NEXT:    v_alignbit_b32 v11, v7, v6, 16
; SI-NEXT:    v_alignbit_b32 v12, v5, v4, 16
; SI-NEXT:    v_alignbit_b32 v13, v3, v2, 16
; SI-NEXT:    v_alignbit_b32 v16, v1, v0, 16
; SI-NEXT:    v_lshrrev_b32_e32 v14, 16, v9
; SI-NEXT:    v_lshrrev_b32_e32 v15, 16, v7
; SI-NEXT:    v_lshrrev_b32_e32 v17, 16, v5
; SI-NEXT:    v_lshrrev_b32_e32 v18, 16, v3
; SI-NEXT:    v_lshrrev_b32_e32 v19, 16, v1
; SI-NEXT:  .LBB54_2: ; %Flow
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB54_4
; SI-NEXT:  ; %bb.3: ; %cmp.true
; SI-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
; SI-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
; SI-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
; SI-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
; SI-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
; SI-NEXT:    v_alignbit_b32 v10, v9, v8, 16
; SI-NEXT:    v_alignbit_b32 v11, v7, v6, 16
; SI-NEXT:    v_alignbit_b32 v12, v5, v4, 16
; SI-NEXT:    v_alignbit_b32 v13, v3, v2, 16
; SI-NEXT:    v_alignbit_b32 v16, v1, v0, 16
; SI-NEXT:    v_lshrrev_b32_e32 v14, 16, v9
; SI-NEXT:    v_lshrrev_b32_e32 v15, 16, v7
; SI-NEXT:    v_lshrrev_b32_e32 v17, 16, v5
; SI-NEXT:    v_lshrrev_b32_e32 v18, 16, v3
; SI-NEXT:    v_lshrrev_b32_e32 v19, 16, v1
; SI-NEXT:  .LBB54_4: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT:    v_or_b32_e32 v0, v0, v16
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_lshlrev_b32_e32 v16, 16, v19
; SI-NEXT:    v_or_b32_e32 v2, v2, v13
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT:    v_lshlrev_b32_e32 v13, 16, v18
; SI-NEXT:    v_or_b32_e32 v4, v4, v12
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT:    v_lshlrev_b32_e32 v12, 16, v17
; SI-NEXT:    v_or_b32_e32 v6, v6, v11
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT:    v_lshlrev_b32_e32 v11, 16, v15
; SI-NEXT:    v_or_b32_e32 v8, v8, v10
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v14
; SI-NEXT:    v_or_b32_e32 v1, v1, v16
; SI-NEXT:    v_or_b32_e32 v3, v3, v13
; SI-NEXT:    v_or_b32_e32 v5, v5, v12
; SI-NEXT:    v_or_b32_e32 v7, v7, v11
; SI-NEXT:    v_or_b32_e32 v9, v9, v10
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v5f64_to_v20i16:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB54_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
; VI-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
; VI-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
; VI-NEXT:  .LBB54_2: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v5f64_to_v20i16:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB54_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
; GFX9-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
; GFX9-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
; GFX9-NEXT:  .LBB54_2: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v5f64_to_v20i16:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB54_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
; GFX11-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
; GFX11-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
; GFX11-NEXT:  .LBB54_2: ; %end
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <5 x double> %a, splat (double 1.000000e+00)
  %a2 = bitcast <5 x double> %a1 to <20 x i16>
  br label %end

cmp.false:
  %a3 = bitcast <5 x double> %a to <20 x i16>
  br label %end

end:
  %phi = phi <20 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <20 x i16> %phi
}

define inreg <20 x i16> @bitcast_v5f64_to_v20i16_scalar(<5 x double> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v5f64_to_v20i16_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc0 .LBB55_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    s_lshr_b32 s14, s25, 16
; SI-NEXT:    s_lshr_b32 s15, s23, 16
; SI-NEXT:    s_lshr_b32 s26, s21, 16
; SI-NEXT:    s_lshr_b32 s27, s19, 16
; SI-NEXT:    s_lshr_b32 s28, s17, 16
; SI-NEXT:    s_lshr_b64 s[4:5], s[24:25], 16
; SI-NEXT:    s_lshr_b64 s[6:7], s[22:23], 16
; SI-NEXT:    s_lshr_b64 s[8:9], s[20:21], 16
; SI-NEXT:    s_lshr_b64 s[10:11], s[18:19], 16
; SI-NEXT:    s_lshr_b64 s[12:13], s[16:17], 16
; SI-NEXT:    v_mov_b32_e32 v9, s25
; SI-NEXT:    v_mov_b32_e32 v7, s23
; SI-NEXT:    v_mov_b32_e32 v5, s21
; SI-NEXT:    v_mov_b32_e32 v3, s19
; SI-NEXT:    v_mov_b32_e32 v1, s17
; SI-NEXT:    v_mov_b32_e32 v0, s16
; SI-NEXT:    v_mov_b32_e32 v2, s18
; SI-NEXT:    v_mov_b32_e32 v4, s20
; SI-NEXT:    v_mov_b32_e32 v6, s22
; SI-NEXT:    v_mov_b32_e32 v8, s24
; SI-NEXT:    v_mov_b32_e32 v16, s14
; SI-NEXT:    v_mov_b32_e32 v17, s15
; SI-NEXT:    v_mov_b32_e32 v18, s26
; SI-NEXT:    v_mov_b32_e32 v19, s27
; SI-NEXT:    v_mov_b32_e32 v20, s28
; SI-NEXT:    v_mov_b32_e32 v14, s12
; SI-NEXT:    v_mov_b32_e32 v13, s10
; SI-NEXT:    v_mov_b32_e32 v12, s8
; SI-NEXT:    v_mov_b32_e32 v11, s6
; SI-NEXT:    v_mov_b32_e32 v10, s4
; SI-NEXT:    s_branch .LBB55_3
; SI-NEXT:  .LBB55_2: ; %cmp.true
; SI-NEXT:    v_add_f64 v[8:9], s[24:25], 1.0
; SI-NEXT:    v_add_f64 v[6:7], s[22:23], 1.0
; SI-NEXT:    v_add_f64 v[4:5], s[20:21], 1.0
; SI-NEXT:    v_lshr_b64 v[10:11], v[8:9], 16
; SI-NEXT:    v_add_f64 v[2:3], s[18:19], 1.0
; SI-NEXT:    v_lshr_b64 v[11:12], v[6:7], 16
; SI-NEXT:    v_add_f64 v[0:1], s[16:17], 1.0
; SI-NEXT:    v_lshr_b64 v[12:13], v[4:5], 16
; SI-NEXT:    v_lshr_b64 v[13:14], v[2:3], 16
; SI-NEXT:    v_lshrrev_b32_e32 v16, 16, v9
; SI-NEXT:    v_lshrrev_b32_e32 v17, 16, v7
; SI-NEXT:    v_lshrrev_b32_e32 v18, 16, v5
; SI-NEXT:    v_lshrrev_b32_e32 v19, 16, v3
; SI-NEXT:    v_lshrrev_b32_e32 v20, 16, v1
; SI-NEXT:    v_lshr_b64 v[14:15], v[0:1], 16
; SI-NEXT:  .LBB55_3: ; %end
; SI-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT:    v_or_b32_e32 v0, v0, v14
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_lshlrev_b32_e32 v14, 16, v20
; SI-NEXT:    v_or_b32_e32 v2, v2, v13
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT:    v_lshlrev_b32_e32 v13, 16, v19
; SI-NEXT:    v_or_b32_e32 v4, v4, v12
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT:    v_lshlrev_b32_e32 v12, 16, v18
; SI-NEXT:    v_or_b32_e32 v6, v6, v11
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT:    v_lshlrev_b32_e32 v11, 16, v17
; SI-NEXT:    v_or_b32_e32 v8, v8, v10
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v16
; SI-NEXT:    v_or_b32_e32 v1, v1, v14
; SI-NEXT:    v_or_b32_e32 v3, v3, v13
; SI-NEXT:    v_or_b32_e32 v5, v5, v12
; SI-NEXT:    v_or_b32_e32 v7, v7, v11
; SI-NEXT:    v_or_b32_e32 v9, v9, v10
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v5f64_to_v20i16_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc0 .LBB55_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s17
; VI-NEXT:    v_mov_b32_e32 v2, s18
; VI-NEXT:    v_mov_b32_e32 v3, s19
; VI-NEXT:    v_mov_b32_e32 v4, s20
; VI-NEXT:    v_mov_b32_e32 v5, s21
; VI-NEXT:    v_mov_b32_e32 v6, s22
; VI-NEXT:    v_mov_b32_e32 v7, s23
; VI-NEXT:    v_mov_b32_e32 v8, s24
; VI-NEXT:    v_mov_b32_e32 v9, s25
; VI-NEXT:    v_mov_b32_e32 v10, s26
; VI-NEXT:    v_mov_b32_e32 v11, s27
; VI-NEXT:    v_mov_b32_e32 v12, s28
; VI-NEXT:    v_mov_b32_e32 v13, s29
; VI-NEXT:    v_mov_b32_e32 v14, s30
; VI-NEXT:    v_mov_b32_e32 v15, s31
; VI-NEXT:    s_setpc_b64 s[30:31]
; VI-NEXT:  .LBB55_2: ; %cmp.true
; VI-NEXT:    v_add_f64 v[8:9], s[24:25], 1.0
; VI-NEXT:    v_add_f64 v[6:7], s[22:23], 1.0
; VI-NEXT:    v_add_f64 v[4:5], s[20:21], 1.0
; VI-NEXT:    v_add_f64 v[2:3], s[18:19], 1.0
; VI-NEXT:    v_add_f64 v[0:1], s[16:17], 1.0
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v5f64_to_v20i16_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc0 .LBB55_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s17
; GFX9-NEXT:    v_mov_b32_e32 v2, s18
; GFX9-NEXT:    v_mov_b32_e32 v3, s19
; GFX9-NEXT:    v_mov_b32_e32 v4, s20
; GFX9-NEXT:    v_mov_b32_e32 v5, s21
; GFX9-NEXT:    v_mov_b32_e32 v6, s22
; GFX9-NEXT:    v_mov_b32_e32 v7, s23
; GFX9-NEXT:    v_mov_b32_e32 v8, s24
; GFX9-NEXT:    v_mov_b32_e32 v9, s25
; GFX9-NEXT:    v_mov_b32_e32 v10, s26
; GFX9-NEXT:    v_mov_b32_e32 v11, s27
; GFX9-NEXT:    v_mov_b32_e32 v12, s28
; GFX9-NEXT:    v_mov_b32_e32 v13, s29
; GFX9-NEXT:    v_mov_b32_e32 v14, s30
; GFX9-NEXT:    v_mov_b32_e32 v15, s31
; GFX9-NEXT:    s_setpc_b64 s[30:31]
; GFX9-NEXT:  .LBB55_2: ; %cmp.true
; GFX9-NEXT:    v_add_f64 v[8:9], s[24:25], 1.0
; GFX9-NEXT:    v_add_f64 v[6:7], s[22:23], 1.0
; GFX9-NEXT:    v_add_f64 v[4:5], s[20:21], 1.0
; GFX9-NEXT:    v_add_f64 v[2:3], s[18:19], 1.0
; GFX9-NEXT:    v_add_f64 v[0:1], s[16:17], 1.0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v5f64_to_v20i16_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s15, s3
; GFX11-NEXT:    s_mov_b32 s14, s2
; GFX11-NEXT:    s_mov_b32 s13, s1
; GFX11-NEXT:    s_mov_b32 s12, s0
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc0 .LBB55_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-NEXT:    v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
; GFX11-NEXT:    v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT:    v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
; GFX11-NEXT:    v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
; GFX11-NEXT:    v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
; GFX11-NEXT:    s_setpc_b64 s[30:31]
; GFX11-NEXT:  .LBB55_2: ; %cmp.true
; GFX11-NEXT:    v_add_f64 v[8:9], s[20:21], 1.0
; GFX11-NEXT:    v_add_f64 v[6:7], s[18:19], 1.0
; GFX11-NEXT:    v_add_f64 v[4:5], s[16:17], 1.0
; GFX11-NEXT:    v_add_f64 v[2:3], s[14:15], 1.0
; GFX11-NEXT:    v_add_f64 v[0:1], s[12:13], 1.0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <5 x double> %a, splat (double 1.000000e+00)
  %a2 = bitcast <5 x double> %a1 to <20 x i16>
  br label %end

cmp.false:
  %a3 = bitcast <5 x double> %a to <20 x i16>
  br label %end

end:
  %phi = phi <20 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <20 x i16> %phi
}

define <5 x i64> @bitcast_v20i16_to_v5i64(<20 x i16> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v20i16_to_v5i64:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_mov_b32_e32 v16, v9
; SI-NEXT:    v_mov_b32_e32 v17, v8
; SI-NEXT:    v_mov_b32_e32 v18, v7
; SI-NEXT:    v_mov_b32_e32 v19, v6
; SI-NEXT:    v_mov_b32_e32 v20, v5
; SI-NEXT:    v_mov_b32_e32 v21, v4
; SI-NEXT:    v_mov_b32_e32 v22, v3
; SI-NEXT:    v_mov_b32_e32 v23, v2
; SI-NEXT:    v_mov_b32_e32 v24, v1
; SI-NEXT:    v_mov_b32_e32 v25, v0
; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v16
; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v17
; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v18
; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v19
; SI-NEXT:    v_lshrrev_b32_e32 v4, 16, v20
; SI-NEXT:    v_lshrrev_b32_e32 v5, 16, v21
; SI-NEXT:    v_lshrrev_b32_e32 v6, 16, v22
; SI-NEXT:    v_lshrrev_b32_e32 v7, 16, v23
; SI-NEXT:    v_lshrrev_b32_e32 v8, 16, v24
; SI-NEXT:    v_lshrrev_b32_e32 v9, 16, v25
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; SI-NEXT:    v_lshlrev_b32_e32 v35, 16, v9
; SI-NEXT:    v_lshlrev_b32_e32 v34, 16, v8
; SI-NEXT:    v_lshlrev_b32_e32 v33, 16, v7
; SI-NEXT:    v_lshlrev_b32_e32 v32, 16, v6
; SI-NEXT:    v_lshlrev_b32_e32 v31, 16, v5
; SI-NEXT:    v_lshlrev_b32_e32 v30, 16, v4
; SI-NEXT:    v_lshlrev_b32_e32 v29, 16, v3
; SI-NEXT:    v_lshlrev_b32_e32 v28, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v27, 16, v1
; SI-NEXT:    v_lshlrev_b32_e32 v26, 16, v0
; SI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_cbranch_execnz .LBB56_3
; SI-NEXT:  ; %bb.1: ; %Flow
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execnz .LBB56_4
; SI-NEXT:  .LBB56_2: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    s_setpc_b64 s[30:31]
; SI-NEXT:  .LBB56_3: ; %cmp.false
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v25
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v24
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v23
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v22
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v21
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v20
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v19
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v18
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v17
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v16
; SI-NEXT:    v_or_b32_e32 v0, v0, v35
; SI-NEXT:    v_or_b32_e32 v1, v1, v34
; SI-NEXT:    v_or_b32_e32 v2, v2, v33
; SI-NEXT:    v_or_b32_e32 v3, v3, v32
; SI-NEXT:    v_or_b32_e32 v4, v4, v31
; SI-NEXT:    v_or_b32_e32 v5, v5, v30
; SI-NEXT:    v_or_b32_e32 v6, v6, v29
; SI-NEXT:    v_or_b32_e32 v7, v7, v28
; SI-NEXT:    v_or_b32_e32 v8, v8, v27
; SI-NEXT:    v_or_b32_e32 v9, v9, v26
; SI-NEXT:    ; implicit-def: $vgpr25
; SI-NEXT:    ; implicit-def: $vgpr24
; SI-NEXT:    ; implicit-def: $vgpr23
; SI-NEXT:    ; implicit-def: $vgpr22
; SI-NEXT:    ; implicit-def: $vgpr21
; SI-NEXT:    ; implicit-def: $vgpr20
; SI-NEXT:    ; implicit-def: $vgpr19
; SI-NEXT:    ; implicit-def: $vgpr18
; SI-NEXT:    ; implicit-def: $vgpr17
; SI-NEXT:    ; implicit-def: $vgpr16
; SI-NEXT:    ; implicit-def: $vgpr35
; SI-NEXT:    ; implicit-def: $vgpr34
; SI-NEXT:    ; implicit-def: $vgpr33
; SI-NEXT:    ; implicit-def: $vgpr32
; SI-NEXT:    ; implicit-def: $vgpr31
; SI-NEXT:    ; implicit-def: $vgpr30
; SI-NEXT:    ; implicit-def: $vgpr29
; SI-NEXT:    ; implicit-def: $vgpr28
; SI-NEXT:    ; implicit-def: $vgpr27
; SI-NEXT:    ; implicit-def: $vgpr26
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB56_2
; SI-NEXT:  .LBB56_4: ; %cmp.true
; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v25
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v24
; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v23
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v22
; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v21
; SI-NEXT:    v_add_i32_e32 v5, vcc, 3, v20
; SI-NEXT:    v_add_i32_e32 v6, vcc, 3, v19
; SI-NEXT:    v_add_i32_e32 v7, vcc, 3, v18
; SI-NEXT:    v_add_i32_e32 v8, vcc, 3, v17
; SI-NEXT:    v_add_i32_e32 v9, vcc, 3, v16
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT:    v_or_b32_e32 v0, v35, v0
; SI-NEXT:    v_or_b32_e32 v1, v34, v1
; SI-NEXT:    v_or_b32_e32 v2, v33, v2
; SI-NEXT:    v_or_b32_e32 v3, v32, v3
; SI-NEXT:    v_or_b32_e32 v4, v31, v4
; SI-NEXT:    v_or_b32_e32 v5, v30, v5
; SI-NEXT:    v_or_b32_e32 v6, v29, v6
; SI-NEXT:    v_or_b32_e32 v7, v28, v7
; SI-NEXT:    v_or_b32_e32 v8, v27, v8
; SI-NEXT:    v_or_b32_e32 v9, v26, v9
; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT:    v_add_i32_e32 v1, vcc, 0x30000, v1
; SI-NEXT:    v_add_i32_e32 v2, vcc, 0x30000, v2
; SI-NEXT:    v_add_i32_e32 v3, vcc, 0x30000, v3
; SI-NEXT:    v_add_i32_e32 v4, vcc, 0x30000, v4
; SI-NEXT:    v_add_i32_e32 v5, vcc, 0x30000, v5
; SI-NEXT:    v_add_i32_e32 v6, vcc, 0x30000, v6
; SI-NEXT:    v_add_i32_e32 v7, vcc, 0x30000, v7
; SI-NEXT:    v_add_i32_e32 v8, vcc, 0x30000, v8
; SI-NEXT:    v_add_i32_e32 v9, vcc, 0x30000, v9
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v20i16_to_v5i64:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB56_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    v_mov_b32_e32 v11, 3
; VI-NEXT:    v_add_u16_e32 v10, 3, v9
; VI-NEXT:    v_add_u16_sdwa v9, v9, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v9, v10, v9
; VI-NEXT:    v_add_u16_e32 v10, 3, v8
; VI-NEXT:    v_add_u16_sdwa v8, v8, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v8, v10, v8
; VI-NEXT:    v_add_u16_e32 v10, 3, v7
; VI-NEXT:    v_add_u16_sdwa v7, v7, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v7, v10, v7
; VI-NEXT:    v_add_u16_e32 v10, 3, v6
; VI-NEXT:    v_add_u16_sdwa v6, v6, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v6, v10, v6
; VI-NEXT:    v_add_u16_e32 v10, 3, v5
; VI-NEXT:    v_add_u16_sdwa v5, v5, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v5, v10, v5
; VI-NEXT:    v_add_u16_e32 v10, 3, v4
; VI-NEXT:    v_add_u16_sdwa v4, v4, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v4, v10, v4
; VI-NEXT:    v_add_u16_e32 v10, 3, v3
; VI-NEXT:    v_add_u16_sdwa v3, v3, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v3, v10, v3
; VI-NEXT:    v_add_u16_e32 v10, 3, v2
; VI-NEXT:    v_add_u16_sdwa v2, v2, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v2, v10, v2
; VI-NEXT:    v_add_u16_e32 v10, 3, v1
; VI-NEXT:    v_add_u16_sdwa v1, v1, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v1, v10, v1
; VI-NEXT:    v_add_u16_e32 v10, 3, v0
; VI-NEXT:    v_add_u16_sdwa v0, v0, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v0, v10, v0
; VI-NEXT:  .LBB56_2: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v20i16_to_v5i64:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB56_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX9-NEXT:  .LBB56_2: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v20i16_to_v5i64:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB56_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-NEXT:  .LBB56_2: ; %end
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <20 x i16> %a, splat (i16 3)
  %a2 = bitcast <20 x i16> %a1 to <5 x i64>
  br label %end

cmp.false:
  %a3 = bitcast <20 x i16> %a to <5 x i64>
  br label %end

end:
  %phi = phi <5 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <5 x i64> %phi
}

define inreg <5 x i64> @bitcast_v20i16_to_v5i64_scalar(<20 x i16> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v20i16_to_v5i64_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_lshr_b32 s11, s25, 16
; SI-NEXT:    s_lshr_b32 s13, s24, 16
; SI-NEXT:    s_lshr_b32 s12, s23, 16
; SI-NEXT:    s_lshr_b32 s10, s22, 16
; SI-NEXT:    s_lshr_b32 s9, s21, 16
; SI-NEXT:    s_lshr_b32 s8, s20, 16
; SI-NEXT:    s_lshr_b32 s7, s19, 16
; SI-NEXT:    s_lshr_b32 s6, s18, 16
; SI-NEXT:    s_lshr_b32 s5, s17, 16
; SI-NEXT:    s_lshr_b32 s4, s16, 16
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc0 .LBB57_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    s_and_b32 s14, s16, 0xffff
; SI-NEXT:    s_lshl_b32 s4, s4, 16
; SI-NEXT:    s_or_b32 s4, s14, s4
; SI-NEXT:    s_and_b32 s14, s17, 0xffff
; SI-NEXT:    s_lshl_b32 s5, s5, 16
; SI-NEXT:    s_or_b32 s5, s14, s5
; SI-NEXT:    s_and_b32 s14, s18, 0xffff
; SI-NEXT:    s_lshl_b32 s6, s6, 16
; SI-NEXT:    s_or_b32 s6, s14, s6
; SI-NEXT:    s_and_b32 s14, s19, 0xffff
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_or_b32 s7, s14, s7
; SI-NEXT:    s_and_b32 s14, s20, 0xffff
; SI-NEXT:    s_lshl_b32 s8, s8, 16
; SI-NEXT:    s_or_b32 s8, s14, s8
; SI-NEXT:    s_and_b32 s14, s21, 0xffff
; SI-NEXT:    s_lshl_b32 s9, s9, 16
; SI-NEXT:    s_or_b32 s9, s14, s9
; SI-NEXT:    s_and_b32 s14, s22, 0xffff
; SI-NEXT:    s_lshl_b32 s10, s10, 16
; SI-NEXT:    s_or_b32 s10, s14, s10
; SI-NEXT:    s_and_b32 s14, s23, 0xffff
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_or_b32 s12, s14, s12
; SI-NEXT:    s_and_b32 s14, s24, 0xffff
; SI-NEXT:    s_lshl_b32 s13, s13, 16
; SI-NEXT:    s_or_b32 s13, s14, s13
; SI-NEXT:    s_and_b32 s14, s25, 0xffff
; SI-NEXT:    s_lshl_b32 s11, s11, 16
; SI-NEXT:    s_or_b32 s11, s14, s11
; SI-NEXT:    s_branch .LBB57_3
; SI-NEXT:  .LBB57_2: ; %cmp.true
; SI-NEXT:    s_add_i32 s16, s16, 3
; SI-NEXT:    s_and_b32 s14, s16, 0xffff
; SI-NEXT:    s_lshl_b32 s4, s4, 16
; SI-NEXT:    s_add_i32 s17, s17, 3
; SI-NEXT:    s_or_b32 s4, s4, s14
; SI-NEXT:    s_and_b32 s14, s17, 0xffff
; SI-NEXT:    s_lshl_b32 s5, s5, 16
; SI-NEXT:    s_add_i32 s18, s18, 3
; SI-NEXT:    s_or_b32 s5, s5, s14
; SI-NEXT:    s_and_b32 s14, s18, 0xffff
; SI-NEXT:    s_lshl_b32 s6, s6, 16
; SI-NEXT:    s_add_i32 s19, s19, 3
; SI-NEXT:    s_or_b32 s6, s6, s14
; SI-NEXT:    s_and_b32 s14, s19, 0xffff
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_add_i32 s20, s20, 3
; SI-NEXT:    s_or_b32 s7, s7, s14
; SI-NEXT:    s_and_b32 s14, s20, 0xffff
; SI-NEXT:    s_lshl_b32 s8, s8, 16
; SI-NEXT:    s_add_i32 s21, s21, 3
; SI-NEXT:    s_or_b32 s8, s8, s14
; SI-NEXT:    s_and_b32 s14, s21, 0xffff
; SI-NEXT:    s_lshl_b32 s9, s9, 16
; SI-NEXT:    s_add_i32 s22, s22, 3
; SI-NEXT:    s_or_b32 s9, s9, s14
; SI-NEXT:    s_and_b32 s14, s22, 0xffff
; SI-NEXT:    s_lshl_b32 s10, s10, 16
; SI-NEXT:    s_add_i32 s23, s23, 3
; SI-NEXT:    s_or_b32 s10, s10, s14
; SI-NEXT:    s_and_b32 s14, s23, 0xffff
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_add_i32 s24, s24, 3
; SI-NEXT:    s_or_b32 s12, s12, s14
; SI-NEXT:    s_and_b32 s14, s24, 0xffff
; SI-NEXT:    s_lshl_b32 s13, s13, 16
; SI-NEXT:    s_add_i32 s25, s25, 3
; SI-NEXT:    s_or_b32 s13, s13, s14
; SI-NEXT:    s_and_b32 s14, s25, 0xffff
; SI-NEXT:    s_lshl_b32 s11, s11, 16
; SI-NEXT:    s_or_b32 s11, s11, s14
; SI-NEXT:    s_add_i32 s4, s4, 0x30000
; SI-NEXT:    s_add_i32 s5, s5, 0x30000
; SI-NEXT:    s_add_i32 s6, s6, 0x30000
; SI-NEXT:    s_add_i32 s7, s7, 0x30000
; SI-NEXT:    s_add_i32 s8, s8, 0x30000
; SI-NEXT:    s_add_i32 s9, s9, 0x30000
; SI-NEXT:    s_add_i32 s10, s10, 0x30000
; SI-NEXT:    s_add_i32 s12, s12, 0x30000
; SI-NEXT:    s_add_i32 s13, s13, 0x30000
; SI-NEXT:    s_add_i32 s11, s11, 0x30000
; SI-NEXT:  .LBB57_3: ; %end
; SI-NEXT:    v_mov_b32_e32 v0, s4
; SI-NEXT:    v_mov_b32_e32 v1, s5
; SI-NEXT:    v_mov_b32_e32 v2, s6
; SI-NEXT:    v_mov_b32_e32 v3, s7
; SI-NEXT:    v_mov_b32_e32 v4, s8
; SI-NEXT:    v_mov_b32_e32 v5, s9
; SI-NEXT:    v_mov_b32_e32 v6, s10
; SI-NEXT:    v_mov_b32_e32 v7, s12
; SI-NEXT:    v_mov_b32_e32 v8, s13
; SI-NEXT:    v_mov_b32_e32 v9, s11
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v20i16_to_v5i64_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc1 .LBB57_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    s_add_i32 s5, s25, 3
; VI-NEXT:    s_and_b32 s4, s25, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s24, 3
; VI-NEXT:    s_add_i32 s25, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s24, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s23, 3
; VI-NEXT:    s_add_i32 s24, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s23, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s22, 3
; VI-NEXT:    s_add_i32 s23, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s22, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s21, 3
; VI-NEXT:    s_add_i32 s22, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s21, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s20, 3
; VI-NEXT:    s_add_i32 s21, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s20, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s19, 3
; VI-NEXT:    s_add_i32 s20, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s19, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s18, 3
; VI-NEXT:    s_add_i32 s19, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s18, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s17, 3
; VI-NEXT:    s_add_i32 s18, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s17, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s5, s16, 3
; VI-NEXT:    s_add_i32 s17, s4, 0x30000
; VI-NEXT:    s_and_b32 s4, s16, 0xffff0000
; VI-NEXT:    s_and_b32 s5, s5, 0xffff
; VI-NEXT:    s_or_b32 s4, s4, s5
; VI-NEXT:    s_add_i32 s16, s4, 0x30000
; VI-NEXT:  .LBB57_2: ; %end
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s17
; VI-NEXT:    v_mov_b32_e32 v2, s18
; VI-NEXT:    v_mov_b32_e32 v3, s19
; VI-NEXT:    v_mov_b32_e32 v4, s20
; VI-NEXT:    v_mov_b32_e32 v5, s21
; VI-NEXT:    v_mov_b32_e32 v6, s22
; VI-NEXT:    v_mov_b32_e32 v7, s23
; VI-NEXT:    v_mov_b32_e32 v8, s24
; VI-NEXT:    v_mov_b32_e32 v9, s25
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v20i16_to_v5i64_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc0 .LBB57_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s17
; GFX9-NEXT:    v_mov_b32_e32 v2, s18
; GFX9-NEXT:    v_mov_b32_e32 v3, s19
; GFX9-NEXT:    v_mov_b32_e32 v4, s20
; GFX9-NEXT:    v_mov_b32_e32 v5, s21
; GFX9-NEXT:    v_mov_b32_e32 v6, s22
; GFX9-NEXT:    v_mov_b32_e32 v7, s23
; GFX9-NEXT:    v_mov_b32_e32 v8, s24
; GFX9-NEXT:    v_mov_b32_e32 v9, s25
; GFX9-NEXT:    v_mov_b32_e32 v10, s26
; GFX9-NEXT:    v_mov_b32_e32 v11, s27
; GFX9-NEXT:    v_mov_b32_e32 v12, s28
; GFX9-NEXT:    v_mov_b32_e32 v13, s29
; GFX9-NEXT:    v_mov_b32_e32 v14, s30
; GFX9-NEXT:    v_mov_b32_e32 v15, s31
; GFX9-NEXT:    s_setpc_b64 s[30:31]
; GFX9-NEXT:  .LBB57_2: ; %cmp.true
; GFX9-NEXT:    v_pk_add_u16 v9, s25, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v8, s24, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v7, s23, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v6, s22, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v5, s21, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v4, s20, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v3, s19, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v20i16_to_v5i64_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s15, s3
; GFX11-NEXT:    s_mov_b32 s14, s2
; GFX11-NEXT:    s_mov_b32 s13, s1
; GFX11-NEXT:    s_mov_b32 s12, s0
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc0 .LBB57_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-NEXT:    v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
; GFX11-NEXT:    v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT:    v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
; GFX11-NEXT:    v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
; GFX11-NEXT:    v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
; GFX11-NEXT:    s_setpc_b64 s[30:31]
; GFX11-NEXT:  .LBB57_2: ; %cmp.true
; GFX11-NEXT:    v_pk_add_u16 v9, s21, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v8, s20, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v7, s19, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v6, s18, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v5, s17, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v4, s16, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v3, s15, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v2, s14, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v1, s13, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_u16 v0, s12, 3 op_sel_hi:[1,0]
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <20 x i16> %a, splat (i16 3)
  %a2 = bitcast <20 x i16> %a1 to <5 x i64>
  br label %end

cmp.false:
  %a3 = bitcast <20 x i16> %a to <5 x i64>
  br label %end

end:
  %phi = phi <5 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <5 x i64> %phi
}

define <20 x i16> @bitcast_v5i64_to_v20i16(<5 x i64> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v5i64_to_v20i16:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; SI-NEXT:    ; implicit-def: $vgpr16
; SI-NEXT:    ; implicit-def: $vgpr19
; SI-NEXT:    ; implicit-def: $vgpr13
; SI-NEXT:    ; implicit-def: $vgpr18
; SI-NEXT:    ; implicit-def: $vgpr12
; SI-NEXT:    ; implicit-def: $vgpr17
; SI-NEXT:    ; implicit-def: $vgpr11
; SI-NEXT:    ; implicit-def: $vgpr15
; SI-NEXT:    ; implicit-def: $vgpr10
; SI-NEXT:    ; implicit-def: $vgpr14
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB58_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    v_alignbit_b32 v10, v9, v8, 16
; SI-NEXT:    v_alignbit_b32 v11, v7, v6, 16
; SI-NEXT:    v_alignbit_b32 v12, v5, v4, 16
; SI-NEXT:    v_alignbit_b32 v13, v3, v2, 16
; SI-NEXT:    v_alignbit_b32 v16, v1, v0, 16
; SI-NEXT:    v_lshrrev_b32_e32 v14, 16, v9
; SI-NEXT:    v_lshrrev_b32_e32 v15, 16, v7
; SI-NEXT:    v_lshrrev_b32_e32 v17, 16, v5
; SI-NEXT:    v_lshrrev_b32_e32 v18, 16, v3
; SI-NEXT:    v_lshrrev_b32_e32 v19, 16, v1
; SI-NEXT:  .LBB58_2: ; %Flow
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB58_4
; SI-NEXT:  ; %bb.3: ; %cmp.true
; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
; SI-NEXT:    v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
; SI-NEXT:    v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
; SI-NEXT:    v_alignbit_b32 v10, v9, v8, 16
; SI-NEXT:    v_alignbit_b32 v11, v7, v6, 16
; SI-NEXT:    v_alignbit_b32 v12, v5, v4, 16
; SI-NEXT:    v_alignbit_b32 v13, v3, v2, 16
; SI-NEXT:    v_alignbit_b32 v16, v1, v0, 16
; SI-NEXT:    v_lshrrev_b32_e32 v14, 16, v9
; SI-NEXT:    v_lshrrev_b32_e32 v15, 16, v7
; SI-NEXT:    v_lshrrev_b32_e32 v17, 16, v5
; SI-NEXT:    v_lshrrev_b32_e32 v18, 16, v3
; SI-NEXT:    v_lshrrev_b32_e32 v19, 16, v1
; SI-NEXT:  .LBB58_4: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT:    v_or_b32_e32 v0, v0, v16
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_lshlrev_b32_e32 v16, 16, v19
; SI-NEXT:    v_or_b32_e32 v2, v2, v13
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT:    v_lshlrev_b32_e32 v13, 16, v18
; SI-NEXT:    v_or_b32_e32 v4, v4, v12
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT:    v_lshlrev_b32_e32 v12, 16, v17
; SI-NEXT:    v_or_b32_e32 v6, v6, v11
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT:    v_lshlrev_b32_e32 v11, 16, v15
; SI-NEXT:    v_or_b32_e32 v8, v8, v10
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v14
; SI-NEXT:    v_or_b32_e32 v1, v1, v16
; SI-NEXT:    v_or_b32_e32 v3, v3, v13
; SI-NEXT:    v_or_b32_e32 v5, v5, v12
; SI-NEXT:    v_or_b32_e32 v7, v7, v11
; SI-NEXT:    v_or_b32_e32 v9, v9, v10
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v5i64_to_v20i16:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB58_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    v_add_u32_e32 v8, vcc, 3, v8
; VI-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
; VI-NEXT:    v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
; VI-NEXT:    v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT:    v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT:  .LBB58_2: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v5i64_to_v20i16:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB58_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, 3, v8
; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v9, vcc
; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, 3, v6
; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, 3, v4
; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, 3, v2
; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT:  .LBB58_2: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v5i64_to_v20i16:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB58_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    v_add_co_u32 v8, vcc_lo, v8, 3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo
; GFX11-NEXT:    v_add_co_u32 v6, vcc_lo, v6, 3
; GFX11-NEXT:    v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo
; GFX11-NEXT:    v_add_co_u32 v4, vcc_lo, v4, 3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
; GFX11-NEXT:    v_add_co_u32 v2, vcc_lo, v2, 3
; GFX11-NEXT:    v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX11-NEXT:  .LBB58_2: ; %end
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <5 x i64> %a, splat (i64 3)
  %a2 = bitcast <5 x i64> %a1 to <20 x i16>
  br label %end

cmp.false:
  %a3 = bitcast <5 x i64> %a to <20 x i16>
  br label %end

end:
  %phi = phi <20 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <20 x i16> %phi
}

define inreg <20 x i16> @bitcast_v5i64_to_v20i16_scalar(<5 x i64> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v5i64_to_v20i16_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc1 .LBB59_2
; SI-NEXT:  ; %bb.1: ; %cmp.true
; SI-NEXT:    s_add_u32 s24, s24, 3
; SI-NEXT:    s_addc_u32 s25, s25, 0
; SI-NEXT:    s_add_u32 s22, s22, 3
; SI-NEXT:    s_addc_u32 s23, s23, 0
; SI-NEXT:    s_add_u32 s20, s20, 3
; SI-NEXT:    s_addc_u32 s21, s21, 0
; SI-NEXT:    s_add_u32 s18, s18, 3
; SI-NEXT:    s_addc_u32 s19, s19, 0
; SI-NEXT:    s_add_u32 s16, s16, 3
; SI-NEXT:    s_addc_u32 s17, s17, 0
; SI-NEXT:  .LBB59_2: ; %cmp.false
; SI-NEXT:    s_lshr_b64 s[4:5], s[24:25], 16
; SI-NEXT:    s_lshr_b64 s[6:7], s[22:23], 16
; SI-NEXT:    s_lshr_b64 s[12:13], s[16:17], 16
; SI-NEXT:    s_lshr_b32 s28, s17, 16
; SI-NEXT:    s_lshr_b64 s[8:9], s[20:21], 16
; SI-NEXT:    s_and_b32 s5, s16, 0xffff
; SI-NEXT:    s_lshl_b32 s7, s12, 16
; SI-NEXT:    s_lshr_b64 s[10:11], s[18:19], 16
; SI-NEXT:    s_or_b32 s5, s5, s7
; SI-NEXT:    s_and_b32 s7, s17, 0xffff
; SI-NEXT:    s_lshl_b32 s9, s28, 16
; SI-NEXT:    s_lshr_b32 s27, s19, 16
; SI-NEXT:    s_or_b32 s7, s7, s9
; SI-NEXT:    s_and_b32 s9, s18, 0xffff
; SI-NEXT:    s_lshl_b32 s10, s10, 16
; SI-NEXT:    s_or_b32 s9, s9, s10
; SI-NEXT:    s_and_b32 s10, s19, 0xffff
; SI-NEXT:    s_lshl_b32 s11, s27, 16
; SI-NEXT:    s_lshr_b32 s26, s21, 16
; SI-NEXT:    s_or_b32 s10, s10, s11
; SI-NEXT:    s_and_b32 s11, s20, 0xffff
; SI-NEXT:    s_lshl_b32 s8, s8, 16
; SI-NEXT:    s_or_b32 s8, s11, s8
; SI-NEXT:    s_and_b32 s11, s21, 0xffff
; SI-NEXT:    s_lshl_b32 s12, s26, 16
; SI-NEXT:    s_lshr_b32 s15, s23, 16
; SI-NEXT:    s_or_b32 s11, s11, s12
; SI-NEXT:    s_and_b32 s12, s22, 0xffff
; SI-NEXT:    s_lshl_b32 s6, s6, 16
; SI-NEXT:    s_or_b32 s6, s12, s6
; SI-NEXT:    s_and_b32 s12, s23, 0xffff
; SI-NEXT:    s_lshl_b32 s13, s15, 16
; SI-NEXT:    s_lshr_b32 s14, s25, 16
; SI-NEXT:    s_or_b32 s12, s12, s13
; SI-NEXT:    s_and_b32 s13, s24, 0xffff
; SI-NEXT:    s_lshl_b32 s4, s4, 16
; SI-NEXT:    s_or_b32 s4, s13, s4
; SI-NEXT:    s_and_b32 s13, s25, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s14, 16
; SI-NEXT:    s_or_b32 s13, s13, s14
; SI-NEXT:    v_mov_b32_e32 v0, s5
; SI-NEXT:    v_mov_b32_e32 v1, s7
; SI-NEXT:    v_mov_b32_e32 v2, s9
; SI-NEXT:    v_mov_b32_e32 v3, s10
; SI-NEXT:    v_mov_b32_e32 v4, s8
; SI-NEXT:    v_mov_b32_e32 v5, s11
; SI-NEXT:    v_mov_b32_e32 v6, s6
; SI-NEXT:    v_mov_b32_e32 v7, s12
; SI-NEXT:    v_mov_b32_e32 v8, s4
; SI-NEXT:    v_mov_b32_e32 v9, s13
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v5i64_to_v20i16_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc1 .LBB59_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    s_add_u32 s24, s24, 3
; VI-NEXT:    s_addc_u32 s25, s25, 0
; VI-NEXT:    s_add_u32 s22, s22, 3
; VI-NEXT:    s_addc_u32 s23, s23, 0
; VI-NEXT:    s_add_u32 s20, s20, 3
; VI-NEXT:    s_addc_u32 s21, s21, 0
; VI-NEXT:    s_add_u32 s18, s18, 3
; VI-NEXT:    s_addc_u32 s19, s19, 0
; VI-NEXT:    s_add_u32 s16, s16, 3
; VI-NEXT:    s_addc_u32 s17, s17, 0
; VI-NEXT:  .LBB59_2: ; %end
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s17
; VI-NEXT:    v_mov_b32_e32 v2, s18
; VI-NEXT:    v_mov_b32_e32 v3, s19
; VI-NEXT:    v_mov_b32_e32 v4, s20
; VI-NEXT:    v_mov_b32_e32 v5, s21
; VI-NEXT:    v_mov_b32_e32 v6, s22
; VI-NEXT:    v_mov_b32_e32 v7, s23
; VI-NEXT:    v_mov_b32_e32 v8, s24
; VI-NEXT:    v_mov_b32_e32 v9, s25
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v5i64_to_v20i16_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc1 .LBB59_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    s_add_u32 s24, s24, 3
; GFX9-NEXT:    s_addc_u32 s25, s25, 0
; GFX9-NEXT:    s_add_u32 s22, s22, 3
; GFX9-NEXT:    s_addc_u32 s23, s23, 0
; GFX9-NEXT:    s_add_u32 s20, s20, 3
; GFX9-NEXT:    s_addc_u32 s21, s21, 0
; GFX9-NEXT:    s_add_u32 s18, s18, 3
; GFX9-NEXT:    s_addc_u32 s19, s19, 0
; GFX9-NEXT:    s_add_u32 s16, s16, 3
; GFX9-NEXT:    s_addc_u32 s17, s17, 0
; GFX9-NEXT:  .LBB59_2: ; %end
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s17
; GFX9-NEXT:    v_mov_b32_e32 v2, s18
; GFX9-NEXT:    v_mov_b32_e32 v3, s19
; GFX9-NEXT:    v_mov_b32_e32 v4, s20
; GFX9-NEXT:    v_mov_b32_e32 v5, s21
; GFX9-NEXT:    v_mov_b32_e32 v6, s22
; GFX9-NEXT:    v_mov_b32_e32 v7, s23
; GFX9-NEXT:    v_mov_b32_e32 v8, s24
; GFX9-NEXT:    v_mov_b32_e32 v9, s25
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v5i64_to_v20i16_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc1 .LBB59_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    s_add_u32 s20, s20, 3
; GFX11-NEXT:    s_addc_u32 s21, s21, 0
; GFX11-NEXT:    s_add_u32 s18, s18, 3
; GFX11-NEXT:    s_addc_u32 s19, s19, 0
; GFX11-NEXT:    s_add_u32 s16, s16, 3
; GFX11-NEXT:    s_addc_u32 s17, s17, 0
; GFX11-NEXT:    s_add_u32 s2, s2, 3
; GFX11-NEXT:    s_addc_u32 s3, s3, 0
; GFX11-NEXT:    s_add_u32 s0, s0, 3
; GFX11-NEXT:    s_addc_u32 s1, s1, 0
; GFX11-NEXT:  .LBB59_2: ; %end
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <5 x i64> %a, splat (i64 3)
  %a2 = bitcast <5 x i64> %a1 to <20 x i16>
  br label %end

cmp.false:
  %a3 = bitcast <5 x i64> %a to <20 x i16>
  br label %end

end:
  %phi = phi <20 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <20 x i16> %phi
}

define <40 x i8> @bitcast_v20f16_to_v40i8(<20 x half> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v20f16_to_v40i8:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT:    v_lshrrev_b32_e32 v12, 16, v10
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_lshrrev_b32_e32 v47, 16, v9
; SI-NEXT:    v_lshrrev_b32_e32 v13, 16, v8
; SI-NEXT:    v_lshrrev_b32_e32 v46, 16, v7
; SI-NEXT:    v_lshrrev_b32_e32 v14, 16, v6
; SI-NEXT:    v_lshrrev_b32_e32 v45, 16, v5
; SI-NEXT:    v_lshrrev_b32_e32 v15, 16, v4
; SI-NEXT:    v_lshrrev_b32_e32 v44, 16, v3
; SI-NEXT:    v_lshrrev_b32_e32 v16, 16, v2
; SI-NEXT:    v_lshrrev_b32_e32 v43, 16, v1
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
; SI-NEXT:    ; implicit-def: $vgpr25
; SI-NEXT:    ; implicit-def: $vgpr36
; SI-NEXT:    ; implicit-def: $vgpr31
; SI-NEXT:    ; implicit-def: $vgpr26
; SI-NEXT:    ; implicit-def: $vgpr24
; SI-NEXT:    ; implicit-def: $vgpr41
; SI-NEXT:    ; implicit-def: $vgpr42
; SI-NEXT:    ; implicit-def: $vgpr22
; SI-NEXT:    ; implicit-def: $vgpr37
; SI-NEXT:    ; implicit-def: $vgpr32
; SI-NEXT:    ; implicit-def: $vgpr27
; SI-NEXT:    ; implicit-def: $vgpr23
; SI-NEXT:    ; implicit-def: $vgpr55
; SI-NEXT:    ; implicit-def: $vgpr40
; SI-NEXT:    ; implicit-def: $vgpr20
; SI-NEXT:    ; implicit-def: $vgpr38
; SI-NEXT:    ; implicit-def: $vgpr33
; SI-NEXT:    ; implicit-def: $vgpr28
; SI-NEXT:    ; implicit-def: $vgpr21
; SI-NEXT:    ; implicit-def: $vgpr53
; SI-NEXT:    ; implicit-def: $vgpr54
; SI-NEXT:    ; implicit-def: $vgpr18
; SI-NEXT:    ; implicit-def: $vgpr39
; SI-NEXT:    ; implicit-def: $vgpr34
; SI-NEXT:    ; implicit-def: $vgpr29
; SI-NEXT:    ; implicit-def: $vgpr19
; SI-NEXT:    ; implicit-def: $vgpr51
; SI-NEXT:    ; implicit-def: $vgpr52
; SI-NEXT:    ; implicit-def: $vgpr11
; SI-NEXT:    ; implicit-def: $vgpr48
; SI-NEXT:    ; implicit-def: $vgpr35
; SI-NEXT:    ; implicit-def: $vgpr30
; SI-NEXT:    ; implicit-def: $vgpr17
; SI-NEXT:    ; implicit-def: $vgpr49
; SI-NEXT:    ; implicit-def: $vgpr50
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB60_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_lshlrev_b32_e32 v11, 16, v43
; SI-NEXT:    v_or_b32_e32 v25, v1, v11
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v2
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v16
; SI-NEXT:    v_or_b32_e32 v24, v1, v2
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v3
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v44
; SI-NEXT:    v_or_b32_e32 v22, v1, v2
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v4
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v15
; SI-NEXT:    v_or_b32_e32 v23, v1, v2
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v5
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v45
; SI-NEXT:    v_or_b32_e32 v20, v1, v2
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v6
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v14
; SI-NEXT:    v_or_b32_e32 v21, v1, v2
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v7
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v46
; SI-NEXT:    v_or_b32_e32 v18, v1, v2
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v8
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v13
; SI-NEXT:    v_or_b32_e32 v19, v1, v2
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v9
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v47
; SI-NEXT:    v_or_b32_e32 v11, v1, v2
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v10
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v12
; SI-NEXT:    v_or_b32_e32 v17, v1, v2
; SI-NEXT:    v_alignbit_b32 v26, v24, v25, 24
; SI-NEXT:    v_alignbit_b32 v31, v24, v25, 16
; SI-NEXT:    v_alignbit_b32 v36, v24, v25, 8
; SI-NEXT:    v_alignbit_b32 v27, v23, v22, 24
; SI-NEXT:    v_alignbit_b32 v32, v23, v22, 16
; SI-NEXT:    v_alignbit_b32 v37, v23, v22, 8
; SI-NEXT:    v_alignbit_b32 v28, v21, v20, 24
; SI-NEXT:    v_alignbit_b32 v33, v21, v20, 16
; SI-NEXT:    v_alignbit_b32 v38, v21, v20, 8
; SI-NEXT:    v_alignbit_b32 v29, v19, v18, 24
; SI-NEXT:    v_alignbit_b32 v34, v19, v18, 16
; SI-NEXT:    v_alignbit_b32 v39, v19, v18, 8
; SI-NEXT:    v_alignbit_b32 v30, v17, v11, 24
; SI-NEXT:    v_alignbit_b32 v35, v17, v11, 16
; SI-NEXT:    v_alignbit_b32 v48, v17, v11, 8
; SI-NEXT:    v_lshrrev_b32_e32 v41, 8, v24
; SI-NEXT:    v_lshrrev_b32_e32 v55, 8, v23
; SI-NEXT:    v_lshrrev_b32_e32 v53, 8, v21
; SI-NEXT:    v_lshrrev_b32_e32 v51, 8, v19
; SI-NEXT:    v_lshrrev_b32_e32 v49, 8, v17
; SI-NEXT:    v_bfe_u32 v42, v16, 8, 8
; SI-NEXT:    v_bfe_u32 v40, v15, 8, 8
; SI-NEXT:    v_bfe_u32 v54, v14, 8, 8
; SI-NEXT:    v_bfe_u32 v52, v13, 8, 8
; SI-NEXT:    v_bfe_u32 v50, v12, 8, 8
; SI-NEXT:    ; implicit-def: $vgpr1
; SI-NEXT:    ; implicit-def: $vgpr2
; SI-NEXT:    ; implicit-def: $vgpr3
; SI-NEXT:    ; implicit-def: $vgpr4
; SI-NEXT:    ; implicit-def: $vgpr5
; SI-NEXT:    ; implicit-def: $vgpr6
; SI-NEXT:    ; implicit-def: $vgpr7
; SI-NEXT:    ; implicit-def: $vgpr8
; SI-NEXT:    ; implicit-def: $vgpr9
; SI-NEXT:    ; implicit-def: $vgpr10
; SI-NEXT:    ; implicit-def: $vgpr43
; SI-NEXT:    ; implicit-def: $vgpr44
; SI-NEXT:    ; implicit-def: $vgpr45
; SI-NEXT:    ; implicit-def: $vgpr46
; SI-NEXT:    ; implicit-def: $vgpr47
; SI-NEXT:  .LBB60_2: ; %Flow
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB60_4
; SI-NEXT:  ; %bb.3: ; %cmp.true
; SI-NEXT:    v_cvt_f32_f16_e32 v11, v47
; SI-NEXT:    v_cvt_f32_f16_e32 v9, v9
; SI-NEXT:    v_cvt_f32_f16_e32 v12, v12
; SI-NEXT:    v_cvt_f32_f16_e32 v10, v10
; SI-NEXT:    v_add_f32_e32 v11, 0x38000000, v11
; SI-NEXT:    v_cvt_f16_f32_e32 v11, v11
; SI-NEXT:    v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT:    v_cvt_f16_f32_e32 v9, v9
; SI-NEXT:    v_add_f32_e32 v12, 0x38000000, v12
; SI-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT:    v_cvt_f16_f32_e32 v12, v12
; SI-NEXT:    v_or_b32_e32 v11, v9, v11
; SI-NEXT:    v_cvt_f32_f16_e32 v9, v46
; SI-NEXT:    v_add_f32_e32 v10, 0x38000000, v10
; SI-NEXT:    v_cvt_f32_f16_e32 v7, v7
; SI-NEXT:    v_cvt_f16_f32_e32 v10, v10
; SI-NEXT:    v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT:    v_lshlrev_b32_e32 v17, 16, v12
; SI-NEXT:    v_cvt_f16_f32_e32 v9, v9
; SI-NEXT:    v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT:    v_or_b32_e32 v17, v10, v17
; SI-NEXT:    v_cvt_f32_f16_e32 v10, v13
; SI-NEXT:    v_cvt_f16_f32_e32 v7, v7
; SI-NEXT:    v_cvt_f32_f16_e32 v8, v8
; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT:    v_add_f32_e32 v10, 0x38000000, v10
; SI-NEXT:    v_or_b32_e32 v18, v7, v9
; SI-NEXT:    v_cvt_f32_f16_e32 v9, v45
; SI-NEXT:    v_cvt_f16_f32_e32 v13, v10
; SI-NEXT:    v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT:    v_cvt_f32_f16_e32 v5, v5
; SI-NEXT:    v_cvt_f16_f32_e32 v8, v8
; SI-NEXT:    v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v13
; SI-NEXT:    v_cvt_f16_f32_e32 v9, v9
; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT:    v_cvt_f16_f32_e32 v5, v5
; SI-NEXT:    v_or_b32_e32 v19, v8, v7
; SI-NEXT:    v_cvt_f32_f16_e32 v7, v14
; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v9
; SI-NEXT:    v_or_b32_e32 v20, v5, v8
; SI-NEXT:    v_cvt_f32_f16_e32 v5, v6
; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v7
; SI-NEXT:    v_cvt_f32_f16_e32 v7, v44
; SI-NEXT:    v_cvt_f16_f32_e32 v14, v6
; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT:    v_cvt_f16_f32_e32 v5, v5
; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v7
; SI-NEXT:    v_cvt_f16_f32_e32 v6, v6
; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v14
; SI-NEXT:    v_cvt_f32_f16_e32 v3, v3
; SI-NEXT:    v_or_b32_e32 v21, v5, v7
; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v6
; SI-NEXT:    v_cvt_f32_f16_e32 v6, v15
; SI-NEXT:    v_cvt_f32_f16_e32 v4, v4
; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT:    v_cvt_f16_f32_e32 v3, v3
; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT:    v_cvt_f16_f32_e32 v15, v6
; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT:    v_cvt_f16_f32_e32 v4, v4
; SI-NEXT:    v_or_b32_e32 v22, v3, v5
; SI-NEXT:    v_cvt_f32_f16_e32 v3, v43
; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v15
; SI-NEXT:    v_or_b32_e32 v23, v4, v5
; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v4, v16
; SI-NEXT:    v_cvt_f32_f16_e32 v2, v2
; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT:    v_cvt_f16_f32_e32 v3, v3
; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1
; SI-NEXT:    v_cvt_f16_f32_e32 v16, v4
; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_or_b32_e32 v25, v1, v3
; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v16
; SI-NEXT:    v_or_b32_e32 v24, v2, v1
; SI-NEXT:    v_alignbit_b32 v26, v24, v25, 24
; SI-NEXT:    v_alignbit_b32 v31, v24, v25, 16
; SI-NEXT:    v_alignbit_b32 v36, v24, v25, 8
; SI-NEXT:    v_alignbit_b32 v27, v23, v22, 24
; SI-NEXT:    v_alignbit_b32 v32, v23, v22, 16
; SI-NEXT:    v_alignbit_b32 v37, v23, v22, 8
; SI-NEXT:    v_alignbit_b32 v28, v21, v20, 24
; SI-NEXT:    v_alignbit_b32 v33, v21, v20, 16
; SI-NEXT:    v_alignbit_b32 v38, v21, v20, 8
; SI-NEXT:    v_alignbit_b32 v29, v19, v18, 24
; SI-NEXT:    v_alignbit_b32 v34, v19, v18, 16
; SI-NEXT:    v_alignbit_b32 v39, v19, v18, 8
; SI-NEXT:    v_alignbit_b32 v30, v17, v11, 24
; SI-NEXT:    v_alignbit_b32 v35, v17, v11, 16
; SI-NEXT:    v_alignbit_b32 v48, v17, v11, 8
; SI-NEXT:    v_lshrrev_b32_e32 v41, 8, v24
; SI-NEXT:    v_lshrrev_b32_e32 v55, 8, v23
; SI-NEXT:    v_lshrrev_b32_e32 v53, 8, v21
; SI-NEXT:    v_lshrrev_b32_e32 v51, 8, v19
; SI-NEXT:    v_lshrrev_b32_e32 v49, 8, v17
; SI-NEXT:    v_bfe_u32 v42, v16, 8, 8
; SI-NEXT:    v_bfe_u32 v40, v15, 8, 8
; SI-NEXT:    v_bfe_u32 v54, v14, 8, 8
; SI-NEXT:    v_bfe_u32 v52, v13, 8, 8
; SI-NEXT:    v_bfe_u32 v50, v12, 8, 8
; SI-NEXT:  .LBB60_4: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v25
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v36
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v31
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v26
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v24
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v41
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v16
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v42
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v22
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v37
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v32
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v27
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v23
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v55
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v15
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v40
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v20
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v38
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v33
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v28
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v21
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v53
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v14
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v54
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v18
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v39
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v34
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v29
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v19
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v51
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v13
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v52
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v11
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v48
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v35
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v30
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v17
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v49
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v12
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v50
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; SI-NEXT:    buffer_load_dword v47, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v20f16_to_v40i8:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
; VI-NEXT:    v_lshrrev_b32_e32 v21, 16, v10
; VI-NEXT:    v_lshrrev_b32_e32 v26, 16, v9
; VI-NEXT:    v_lshrrev_b32_e32 v20, 16, v8
; VI-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
; VI-NEXT:    v_lshrrev_b32_e32 v19, 16, v6
; VI-NEXT:    v_lshrrev_b32_e32 v24, 16, v5
; VI-NEXT:    v_lshrrev_b32_e32 v18, 16, v4
; VI-NEXT:    v_lshrrev_b32_e32 v23, 16, v3
; VI-NEXT:    v_lshrrev_b32_e32 v17, 16, v2
; VI-NEXT:    v_lshrrev_b32_e32 v22, 16, v1
; VI-NEXT:    ; implicit-def: $vgpr16
; VI-NEXT:    ; implicit-def: $vgpr15
; VI-NEXT:    ; implicit-def: $vgpr39
; VI-NEXT:    ; implicit-def: $vgpr48
; VI-NEXT:    ; implicit-def: $vgpr37
; VI-NEXT:    ; implicit-def: $vgpr14
; VI-NEXT:    ; implicit-def: $vgpr35
; VI-NEXT:    ; implicit-def: $vgpr38
; VI-NEXT:    ; implicit-def: $vgpr34
; VI-NEXT:    ; implicit-def: $vgpr13
; VI-NEXT:    ; implicit-def: $vgpr32
; VI-NEXT:    ; implicit-def: $vgpr36
; VI-NEXT:    ; implicit-def: $vgpr31
; VI-NEXT:    ; implicit-def: $vgpr12
; VI-NEXT:    ; implicit-def: $vgpr29
; VI-NEXT:    ; implicit-def: $vgpr33
; VI-NEXT:    ; implicit-def: $vgpr28
; VI-NEXT:    ; implicit-def: $vgpr27
; VI-NEXT:    ; implicit-def: $vgpr30
; VI-NEXT:    ; implicit-def: $vgpr11
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB60_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; VI-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; VI-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; VI-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; VI-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; VI-NEXT:    v_lshrrev_b32_e32 v30, 24, v10
; VI-NEXT:    v_lshrrev_b32_e32 v27, 8, v10
; VI-NEXT:    v_lshrrev_b32_e32 v28, 8, v9
; VI-NEXT:    v_lshrrev_b32_e32 v33, 24, v8
; VI-NEXT:    v_lshrrev_b32_e32 v29, 8, v8
; VI-NEXT:    v_lshrrev_b32_e32 v31, 8, v7
; VI-NEXT:    v_lshrrev_b32_e32 v36, 24, v6
; VI-NEXT:    v_lshrrev_b32_e32 v32, 8, v6
; VI-NEXT:    v_lshrrev_b32_e32 v34, 8, v5
; VI-NEXT:    v_lshrrev_b32_e32 v38, 24, v4
; VI-NEXT:    v_lshrrev_b32_e32 v35, 8, v4
; VI-NEXT:    v_lshrrev_b32_e32 v37, 8, v3
; VI-NEXT:    v_lshrrev_b32_e32 v48, 24, v2
; VI-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
; VI-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; VI-NEXT:  .LBB60_2: ; %Flow
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB60_4
; VI-NEXT:  ; %bb.3: ; %cmp.true
; VI-NEXT:    v_mov_b32_e32 v11, 0x200
; VI-NEXT:    v_add_f16_sdwa v17, v2, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_lshlrev_b32_e32 v12, 16, v17
; VI-NEXT:    v_add_f16_e32 v2, 0x200, v2
; VI-NEXT:    v_add_f16_sdwa v22, v1, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v39, v2, v12
; VI-NEXT:    v_lshlrev_b32_e32 v12, 16, v22
; VI-NEXT:    v_add_f16_e32 v1, 0x200, v1
; VI-NEXT:    v_add_f16_sdwa v18, v4, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v38, v1, v12
; VI-NEXT:    v_lshlrev_b32_e32 v12, 16, v18
; VI-NEXT:    v_add_f16_e32 v4, 0x200, v4
; VI-NEXT:    v_add_f16_sdwa v23, v3, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v37, v4, v12
; VI-NEXT:    v_lshlrev_b32_e32 v12, 16, v23
; VI-NEXT:    v_add_f16_e32 v3, 0x200, v3
; VI-NEXT:    v_add_f16_sdwa v19, v6, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v36, v3, v12
; VI-NEXT:    v_lshlrev_b32_e32 v12, 16, v19
; VI-NEXT:    v_add_f16_e32 v6, 0x200, v6
; VI-NEXT:    v_add_f16_sdwa v24, v5, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v34, v6, v12
; VI-NEXT:    v_lshlrev_b32_e32 v12, 16, v24
; VI-NEXT:    v_add_f16_e32 v5, 0x200, v5
; VI-NEXT:    v_add_f16_sdwa v20, v8, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v33, v5, v12
; VI-NEXT:    v_lshlrev_b32_e32 v12, 16, v20
; VI-NEXT:    v_add_f16_e32 v8, 0x200, v8
; VI-NEXT:    v_add_f16_sdwa v25, v7, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v31, v8, v12
; VI-NEXT:    v_lshlrev_b32_e32 v12, 16, v25
; VI-NEXT:    v_add_f16_e32 v7, 0x200, v7
; VI-NEXT:    v_add_f16_sdwa v21, v10, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_sdwa v26, v9, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v30, v7, v12
; VI-NEXT:    v_lshlrev_b32_e32 v12, 16, v21
; VI-NEXT:    v_add_f16_e32 v10, 0x200, v10
; VI-NEXT:    v_lshlrev_b32_e32 v11, 16, v26
; VI-NEXT:    v_add_f16_e32 v9, 0x200, v9
; VI-NEXT:    v_or_b32_e32 v29, v10, v12
; VI-NEXT:    v_or_b32_e32 v28, v9, v11
; VI-NEXT:    v_lshrrev_b64 v[11:12], 24, v[28:29]
; VI-NEXT:    v_lshrrev_b64 v[12:13], 24, v[30:31]
; VI-NEXT:    v_lshrrev_b64 v[13:14], 24, v[33:34]
; VI-NEXT:    v_lshrrev_b64 v[14:15], 24, v[36:37]
; VI-NEXT:    v_lshrrev_b64 v[15:16], 24, v[38:39]
; VI-NEXT:    v_lshrrev_b32_e32 v27, 8, v29
; VI-NEXT:    v_lshrrev_b32_e32 v28, 8, v28
; VI-NEXT:    v_lshrrev_b32_e32 v29, 8, v31
; VI-NEXT:    v_lshrrev_b32_e32 v31, 8, v30
; VI-NEXT:    v_lshrrev_b32_e32 v32, 8, v34
; VI-NEXT:    v_lshrrev_b32_e32 v34, 8, v33
; VI-NEXT:    v_lshrrev_b32_e32 v35, 8, v37
; VI-NEXT:    v_lshrrev_b32_e32 v37, 8, v36
; VI-NEXT:    v_lshrrev_b32_e32 v39, 8, v39
; VI-NEXT:    v_lshrrev_b32_e32 v16, 8, v38
; VI-NEXT:    v_bfe_u32 v30, v21, 8, 8
; VI-NEXT:    v_bfe_u32 v33, v20, 8, 8
; VI-NEXT:    v_bfe_u32 v36, v19, 8, 8
; VI-NEXT:    v_bfe_u32 v38, v18, 8, 8
; VI-NEXT:    v_bfe_u32 v48, v17, 8, 8
; VI-NEXT:  .LBB60_4: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_mov_b32 s4, 0xc0c0004
; VI-NEXT:    v_perm_b32 v15, v22, v15, s4
; VI-NEXT:    v_perm_b32 v1, v1, v16, s4
; VI-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT:    v_or_b32_e32 v1, v1, v15
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT:    v_perm_b32 v1, v2, v39, s4
; VI-NEXT:    v_perm_b32 v2, v17, v48, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v23, v14, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
; VI-NEXT:    v_perm_b32 v1, v3, v37, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v18, v38, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; VI-NEXT:    v_perm_b32 v1, v4, v35, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v24, v13, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; VI-NEXT:    v_perm_b32 v1, v5, v34, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v19, v36, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; VI-NEXT:    v_perm_b32 v1, v6, v32, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v25, v12, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; VI-NEXT:    v_perm_b32 v1, v7, v31, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v20, v33, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; VI-NEXT:    v_perm_b32 v1, v8, v29, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v26, v11, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; VI-NEXT:    v_perm_b32 v1, v9, v28, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v21, v30, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; VI-NEXT:    v_perm_b32 v1, v10, v27, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v20f16_to_v40i8:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
; GFX9-NEXT:    ; implicit-def: $vgpr16
; GFX9-NEXT:    ; implicit-def: $vgpr48
; GFX9-NEXT:    ; implicit-def: $vgpr15
; GFX9-NEXT:    ; implicit-def: $vgpr39
; GFX9-NEXT:    ; implicit-def: $vgpr38
; GFX9-NEXT:    ; implicit-def: $vgpr37
; GFX9-NEXT:    ; implicit-def: $vgpr36
; GFX9-NEXT:    ; implicit-def: $vgpr35
; GFX9-NEXT:    ; implicit-def: $vgpr14
; GFX9-NEXT:    ; implicit-def: $vgpr34
; GFX9-NEXT:    ; implicit-def: $vgpr33
; GFX9-NEXT:    ; implicit-def: $vgpr32
; GFX9-NEXT:    ; implicit-def: $vgpr31
; GFX9-NEXT:    ; implicit-def: $vgpr30
; GFX9-NEXT:    ; implicit-def: $vgpr13
; GFX9-NEXT:    ; implicit-def: $vgpr29
; GFX9-NEXT:    ; implicit-def: $vgpr28
; GFX9-NEXT:    ; implicit-def: $vgpr27
; GFX9-NEXT:    ; implicit-def: $vgpr26
; GFX9-NEXT:    ; implicit-def: $vgpr25
; GFX9-NEXT:    ; implicit-def: $vgpr12
; GFX9-NEXT:    ; implicit-def: $vgpr24
; GFX9-NEXT:    ; implicit-def: $vgpr23
; GFX9-NEXT:    ; implicit-def: $vgpr22
; GFX9-NEXT:    ; implicit-def: $vgpr21
; GFX9-NEXT:    ; implicit-def: $vgpr20
; GFX9-NEXT:    ; implicit-def: $vgpr19
; GFX9-NEXT:    ; implicit-def: $vgpr18
; GFX9-NEXT:    ; implicit-def: $vgpr17
; GFX9-NEXT:    ; implicit-def: $vgpr11
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB60_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX9-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX9-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX9-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX9-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX9-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
; GFX9-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
; GFX9-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
; GFX9-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
; GFX9-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; GFX9-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; GFX9-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
; GFX9-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
; GFX9-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
; GFX9-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX9-NEXT:  .LBB60_2: ; %Flow
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB60_4
; GFX9-NEXT:  ; %bb.3: ; %cmp.true
; GFX9-NEXT:    s_movk_i32 s6, 0x200
; GFX9-NEXT:    v_pk_add_f16 v10, v10, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v9, v9, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v8, v8, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX9-NEXT:    v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX9-NEXT:    v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX9-NEXT:    v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX9-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX9-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
; GFX9-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
; GFX9-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
; GFX9-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
; GFX9-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; GFX9-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; GFX9-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
; GFX9-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
; GFX9-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
; GFX9-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX9-NEXT:  .LBB60_4: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_mov_b32 s4, 0xc0c0004
; GFX9-NEXT:    v_perm_b32 v15, v48, v15, s4
; GFX9-NEXT:    v_perm_b32 v1, v1, v16, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v15, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen
; GFX9-NEXT:    v_perm_b32 v1, v2, v39, s4
; GFX9-NEXT:    v_perm_b32 v2, v38, v37, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT:    v_perm_b32 v1, v3, v36, s4
; GFX9-NEXT:    v_perm_b32 v2, v35, v14, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT:    v_perm_b32 v1, v4, v34, s4
; GFX9-NEXT:    v_perm_b32 v2, v33, v32, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; GFX9-NEXT:    v_perm_b32 v1, v5, v31, s4
; GFX9-NEXT:    v_perm_b32 v2, v30, v13, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT:    v_perm_b32 v1, v6, v29, s4
; GFX9-NEXT:    v_perm_b32 v2, v28, v27, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; GFX9-NEXT:    v_perm_b32 v1, v7, v26, s4
; GFX9-NEXT:    v_perm_b32 v2, v25, v12, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT:    v_perm_b32 v1, v8, v24, s4
; GFX9-NEXT:    v_perm_b32 v2, v23, v22, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; GFX9-NEXT:    v_perm_b32 v1, v9, v21, s4
; GFX9-NEXT:    v_perm_b32 v2, v20, v11, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT:    v_perm_b32 v1, v10, v19, s4
; GFX9-NEXT:    v_perm_b32 v2, v18, v17, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v20f16_to_v40i8:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v11
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr11_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB60_2
; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v18, 8, v10
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v9
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v20, 24, v8
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v8
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v22, 8, v7
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v6
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v6
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v5
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v4
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v4
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v3
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v28, 24, v2
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v2
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX11-TRUE16-NEXT:  .LBB60_2: ; %Flow
; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB60_4
; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
; GFX11-TRUE16-NEXT:    v_pk_add_f16 v10, v10, 0x200 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT:    v_pk_add_f16 v9, v9, 0x200 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT:    v_pk_add_f16 v8, v8, 0x200 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT:    v_pk_add_f16 v7, v7, 0x200 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT:    v_pk_add_f16 v6, v6, 0x200 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT:    v_pk_add_f16 v5, v5, 0x200 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT:    v_pk_add_f16 v4, v4, 0x200 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT:    v_pk_add_f16 v3, v3, 0x200 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT:    v_pk_add_f16 v2, v2, 0x200 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT:    v_pk_add_f16 v1, v1, 0x200 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v18, 8, v10
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v9
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v20, 24, v8
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v8
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v22, 8, v7
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v6
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v6
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v5
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v4
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v4
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v3
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v28, 24, v2
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v2
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX11-TRUE16-NEXT:  .LBB60_4: ; %end
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v31.l, v1.h
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_perm_b32 v1, v1, v16, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v16, v2, v30, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v29, v3, v29, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v3.h
; GFX11-TRUE16-NEXT:    v_perm_b32 v15, v31, v15, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v31.l, v5.h
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v30.l, v4.h
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
; GFX11-TRUE16-NEXT:    v_perm_b32 v5, v5, v25, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v1, v15, 16, v1
; GFX11-TRUE16-NEXT:    v_perm_b32 v13, v31, v13, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v3, v3, v14, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v4, v4, v27, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v14, v30, v26, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v15.l, v6.h
; GFX11-TRUE16-NEXT:    v_perm_b32 v2, v2, v28, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v5, v13, 16, v5
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v7.h
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v4, v14, 16, v4
; GFX11-TRUE16-NEXT:    v_perm_b32 v14, v15, v23, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v15.l, v8.h
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v2, v2, 16, v16
; GFX11-TRUE16-NEXT:    v_perm_b32 v12, v13, v12, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v9.h
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.l, v10.h
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, v6, v24, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, v7, v22, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v8, v8, v21, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v15, v15, v20, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v9, v9, v19, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v11, v13, v11, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v10, v10, v18, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v13, v16, v17, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v3, v3, 16, v29
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v6, v14, 16, v6
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v7, v12, 16, v7
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v8, v15, 16, v8
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v9, v11, 16, v9
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v10, v13, 16, v10
; GFX11-TRUE16-NEXT:    s_clause 0x2
; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[1:4], off
; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
; GFX11-TRUE16-NEXT:    scratch_store_b64 v0, v[9:10], off offset:32
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v20f16_to_v40i8:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v11
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB60_2
; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX11-FAKE16-NEXT:  .LBB60_2: ; %Flow
; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB60_4
; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
; GFX11-FAKE16-NEXT:    v_pk_add_f16 v10, v10, 0x200 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT:    v_pk_add_f16 v9, v9, 0x200 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT:    v_pk_add_f16 v8, v8, 0x200 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT:    v_pk_add_f16 v7, v7, 0x200 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT:    v_pk_add_f16 v6, v6, 0x200 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT:    v_pk_add_f16 v5, v5, 0x200 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT:    v_pk_add_f16 v4, v4, 0x200 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT:    v_pk_add_f16 v3, v3, 0x200 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT:    v_pk_add_f16 v2, v2, 0x200 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT:    v_pk_add_f16 v1, v1, 0x200 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX11-FAKE16-NEXT:  .LBB60_4: ; %end
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v3, v36, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v35, v14, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v5, v31, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v30, v13, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v1, v16, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v48, v15, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v2, v39, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v16, v38, v37, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v4, v34, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v32, v33, v32, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v3, v14, 16, v3
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v5, v13, 16, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v6, v29, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v28, v27, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v7, v26, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v25, v12, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v8, v24, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v23, v22, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v15, 16, v1
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v9, v21, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v20, v11, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v10, v19, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v18, v17, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, v16, 16, v2
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v4, v32, 16, v4
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v6, v13, 16, v6
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v7, v12, 16, v7
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v8, v14, 16, v8
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v9, v11, 16, v9
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v10, v15, 16, v10
; GFX11-FAKE16-NEXT:    s_clause 0x2
; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[1:4], off
; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
; GFX11-FAKE16-NEXT:    scratch_store_b64 v0, v[9:10], off offset:32
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <20 x half> %a, splat (half 0xH0200)
  %a2 = bitcast <20 x half> %a1 to <40 x i8>
  br label %end

cmp.false:
  %a3 = bitcast <20 x half> %a to <40 x i8>
  br label %end

end:
  %phi = phi <40 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <40 x i8> %phi
}

define inreg <40 x i8> @bitcast_v20f16_to_v40i8_scalar(<20 x half> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v20f16_to_v40i8_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_lshr_b32 s60, s25, 16
; SI-NEXT:    s_lshr_b32 s4, s24, 16
; SI-NEXT:    s_lshr_b32 s73, s23, 16
; SI-NEXT:    s_lshr_b32 s5, s22, 16
; SI-NEXT:    s_lshr_b32 s72, s21, 16
; SI-NEXT:    s_lshr_b32 s7, s20, 16
; SI-NEXT:    s_lshr_b32 s63, s19, 16
; SI-NEXT:    s_lshr_b32 s9, s18, 16
; SI-NEXT:    s_lshr_b32 s62, s17, 16
; SI-NEXT:    s_lshr_b32 s11, s16, 16
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc0 .LBB61_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    s_and_b32 s6, s16, 0xffff
; SI-NEXT:    s_lshl_b32 s8, s11, 16
; SI-NEXT:    s_or_b32 s12, s6, s8
; SI-NEXT:    s_and_b32 s6, s17, 0xffff
; SI-NEXT:    s_lshl_b32 s8, s62, 16
; SI-NEXT:    s_or_b32 s13, s6, s8
; SI-NEXT:    s_and_b32 s6, s18, 0xffff
; SI-NEXT:    s_lshl_b32 s8, s9, 16
; SI-NEXT:    s_or_b32 s10, s6, s8
; SI-NEXT:    s_and_b32 s6, s19, 0xffff
; SI-NEXT:    s_lshl_b32 s8, s63, 16
; SI-NEXT:    s_or_b32 s11, s6, s8
; SI-NEXT:    s_and_b32 s6, s20, 0xffff
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_or_b32 s8, s6, s7
; SI-NEXT:    s_and_b32 s6, s21, 0xffff
; SI-NEXT:    s_lshl_b32 s7, s72, 16
; SI-NEXT:    s_or_b32 s9, s6, s7
; SI-NEXT:    s_and_b32 s6, s22, 0xffff
; SI-NEXT:    s_lshl_b32 s5, s5, 16
; SI-NEXT:    s_or_b32 s6, s6, s5
; SI-NEXT:    s_and_b32 s5, s23, 0xffff
; SI-NEXT:    s_lshl_b32 s7, s73, 16
; SI-NEXT:    s_lshr_b64 s[14:15], s[12:13], 24
; SI-NEXT:    s_or_b32 s7, s5, s7
; SI-NEXT:    s_and_b32 s5, s24, 0xffff
; SI-NEXT:    s_lshl_b32 s4, s4, 16
; SI-NEXT:    s_or_b32 s4, s5, s4
; SI-NEXT:    s_and_b32 s5, s25, 0xffff
; SI-NEXT:    s_lshl_b32 s15, s60, 16
; SI-NEXT:    s_or_b32 s5, s5, s15
; SI-NEXT:    s_bfe_u32 s15, s60, 0x80008
; SI-NEXT:    v_mov_b32_e32 v5, s15
; SI-NEXT:    s_bfe_u32 s15, s73, 0x80008
; SI-NEXT:    v_mov_b32_e32 v6, s15
; SI-NEXT:    s_bfe_u32 s15, s72, 0x80008
; SI-NEXT:    v_mov_b32_e32 v8, s15
; SI-NEXT:    s_bfe_u32 s15, s63, 0x80008
; SI-NEXT:    s_lshr_b64 s[16:17], s[10:11], 24
; SI-NEXT:    s_lshr_b64 s[18:19], s[8:9], 24
; SI-NEXT:    s_lshr_b64 s[20:21], s[6:7], 24
; SI-NEXT:    s_lshr_b64 s[22:23], s[4:5], 24
; SI-NEXT:    v_mov_b32_e32 v9, s15
; SI-NEXT:    s_bfe_u32 s15, s62, 0x80008
; SI-NEXT:    s_lshr_b64 s[26:27], s[12:13], 16
; SI-NEXT:    s_lshr_b64 s[44:45], s[12:13], 8
; SI-NEXT:    s_lshr_b64 s[28:29], s[10:11], 16
; SI-NEXT:    s_lshr_b64 s[46:47], s[10:11], 8
; SI-NEXT:    s_lshr_b64 s[40:41], s[8:9], 16
; SI-NEXT:    s_lshr_b64 s[56:57], s[8:9], 8
; SI-NEXT:    s_lshr_b64 s[42:43], s[6:7], 16
; SI-NEXT:    s_lshr_b64 s[58:59], s[6:7], 8
; SI-NEXT:    s_lshr_b64 s[24:25], s[4:5], 16
; SI-NEXT:    v_mov_b32_e32 v1, s60
; SI-NEXT:    s_lshr_b64 s[60:61], s[4:5], 8
; SI-NEXT:    v_mov_b32_e32 v2, s73
; SI-NEXT:    s_lshr_b32 s23, s13, 8
; SI-NEXT:    v_mov_b32_e32 v3, s72
; SI-NEXT:    s_lshr_b32 s21, s11, 8
; SI-NEXT:    v_mov_b32_e32 v4, s63
; SI-NEXT:    s_lshr_b32 s19, s9, 8
; SI-NEXT:    v_mov_b32_e32 v7, s62
; SI-NEXT:    v_mov_b32_e32 v10, s15
; SI-NEXT:    s_lshr_b32 s17, s7, 8
; SI-NEXT:    s_branch .LBB61_3
; SI-NEXT:  .LBB61_2: ; %cmp.true
; SI-NEXT:    v_cvt_f32_f16_e32 v2, s24
; SI-NEXT:    v_cvt_f32_f16_e32 v1, s4
; SI-NEXT:    v_cvt_f32_f16_e32 v3, s60
; SI-NEXT:    v_cvt_f32_f16_e32 v7, s16
; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT:    v_cvt_f16_f32_e32 v4, v1
; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v3
; SI-NEXT:    v_readfirstlane_b32 s6, v2
; SI-NEXT:    v_cvt_f32_f16_e32 v2, s25
; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v3, s5
; SI-NEXT:    v_readfirstlane_b32 s4, v4
; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; SI-NEXT:    s_lshl_b32 s4, s4, 16
; SI-NEXT:    s_or_b32 s4, s6, s4
; SI-NEXT:    v_readfirstlane_b32 s6, v1
; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT:    s_lshl_b32 s5, s6, 16
; SI-NEXT:    v_cvt_f16_f32_e32 v3, v3
; SI-NEXT:    v_readfirstlane_b32 s6, v2
; SI-NEXT:    v_cvt_f32_f16_e32 v2, s22
; SI-NEXT:    s_or_b32 s5, s6, s5
; SI-NEXT:    v_readfirstlane_b32 s6, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v3, s73
; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT:    v_cvt_f16_f32_e32 v4, v2
; SI-NEXT:    s_lshl_b32 s6, s6, 16
; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v3, s23
; SI-NEXT:    v_readfirstlane_b32 s8, v4
; SI-NEXT:    v_cvt_f32_f16_e32 v4, s7
; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT:    v_cvt_f16_f32_e32 v3, v3
; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT:    v_cvt_f16_f32_e32 v4, v4
; SI-NEXT:    s_or_b32 s6, s8, s6
; SI-NEXT:    v_readfirstlane_b32 s8, v2
; SI-NEXT:    s_lshl_b32 s7, s8, 16
; SI-NEXT:    v_readfirstlane_b32 s8, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v3, s20
; SI-NEXT:    s_or_b32 s7, s8, s7
; SI-NEXT:    v_readfirstlane_b32 s8, v4
; SI-NEXT:    v_cvt_f32_f16_e32 v4, s72
; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT:    v_cvt_f16_f32_e32 v5, v3
; SI-NEXT:    s_lshl_b32 s8, s8, 16
; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v4
; SI-NEXT:    v_cvt_f32_f16_e32 v4, s21
; SI-NEXT:    v_cvt_f16_f32_e32 v3, v3
; SI-NEXT:    v_readfirstlane_b32 s10, v5
; SI-NEXT:    v_cvt_f32_f16_e32 v5, s9
; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT:    v_cvt_f16_f32_e32 v4, v4
; SI-NEXT:    s_or_b32 s8, s10, s8
; SI-NEXT:    v_readfirstlane_b32 s10, v3
; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT:    s_lshl_b32 s9, s10, 16
; SI-NEXT:    v_cvt_f16_f32_e32 v5, v5
; SI-NEXT:    v_readfirstlane_b32 s10, v4
; SI-NEXT:    v_cvt_f32_f16_e32 v4, s18
; SI-NEXT:    s_or_b32 s9, s10, s9
; SI-NEXT:    v_readfirstlane_b32 s10, v5
; SI-NEXT:    v_cvt_f32_f16_e32 v5, s63
; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT:    v_cvt_f16_f32_e32 v6, v4
; SI-NEXT:    s_lshl_b32 s10, s10, 16
; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v5
; SI-NEXT:    v_cvt_f32_f16_e32 v5, s19
; SI-NEXT:    v_readfirstlane_b32 s12, v6
; SI-NEXT:    v_cvt_f32_f16_e32 v6, s11
; SI-NEXT:    v_cvt_f16_f32_e32 v4, v4
; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT:    v_cvt_f16_f32_e32 v5, v5
; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT:    v_cvt_f16_f32_e32 v6, v6
; SI-NEXT:    s_or_b32 s10, s12, s10
; SI-NEXT:    v_readfirstlane_b32 s12, v4
; SI-NEXT:    s_lshl_b32 s11, s12, 16
; SI-NEXT:    v_readfirstlane_b32 s12, v5
; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v7
; SI-NEXT:    s_or_b32 s11, s12, s11
; SI-NEXT:    v_readfirstlane_b32 s12, v6
; SI-NEXT:    v_cvt_f16_f32_e32 v5, v5
; SI-NEXT:    v_cvt_f32_f16_e32 v6, s62
; SI-NEXT:    v_cvt_f32_f16_e32 v8, s17
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    v_readfirstlane_b32 s13, v5
; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v6
; SI-NEXT:    v_cvt_f16_f32_e32 v7, v5
; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v8
; SI-NEXT:    v_cvt_f16_f32_e32 v5, v5
; SI-NEXT:    s_or_b32 s12, s13, s12
; SI-NEXT:    v_readfirstlane_b32 s13, v7
; SI-NEXT:    s_lshl_b32 s13, s13, 16
; SI-NEXT:    v_readfirstlane_b32 s14, v5
; SI-NEXT:    s_or_b32 s13, s14, s13
; SI-NEXT:    s_lshr_b64 s[16:17], s[10:11], 24
; SI-NEXT:    s_lshr_b64 s[18:19], s[8:9], 24
; SI-NEXT:    s_lshr_b64 s[20:21], s[6:7], 24
; SI-NEXT:    s_lshr_b64 s[22:23], s[4:5], 24
; SI-NEXT:    s_lshr_b64 s[14:15], s[12:13], 24
; SI-NEXT:    s_lshr_b64 s[26:27], s[12:13], 16
; SI-NEXT:    s_lshr_b64 s[44:45], s[12:13], 8
; SI-NEXT:    s_lshr_b64 s[28:29], s[10:11], 16
; SI-NEXT:    s_lshr_b64 s[46:47], s[10:11], 8
; SI-NEXT:    s_lshr_b64 s[40:41], s[8:9], 16
; SI-NEXT:    s_lshr_b64 s[56:57], s[8:9], 8
; SI-NEXT:    s_lshr_b64 s[42:43], s[6:7], 16
; SI-NEXT:    s_lshr_b64 s[58:59], s[6:7], 8
; SI-NEXT:    s_lshr_b64 s[24:25], s[4:5], 16
; SI-NEXT:    s_lshr_b64 s[60:61], s[4:5], 8
; SI-NEXT:    s_lshr_b32 s23, s13, 8
; SI-NEXT:    s_lshr_b32 s21, s11, 8
; SI-NEXT:    s_lshr_b32 s19, s9, 8
; SI-NEXT:    s_lshr_b32 s17, s7, 8
; SI-NEXT:    v_bfe_u32 v10, v7, 8, 8
; SI-NEXT:    v_bfe_u32 v9, v4, 8, 8
; SI-NEXT:    v_bfe_u32 v8, v3, 8, 8
; SI-NEXT:    v_bfe_u32 v6, v2, 8, 8
; SI-NEXT:    v_bfe_u32 v5, v1, 8, 8
; SI-NEXT:  .LBB61_3: ; %end
; SI-NEXT:    s_lshl_b32 s25, s44, 8
; SI-NEXT:    s_and_b32 s12, s12, 0xff
; SI-NEXT:    s_or_b32 s12, s12, s25
; SI-NEXT:    s_and_b32 s25, s26, 0xff
; SI-NEXT:    s_lshl_b32 s25, s25, 16
; SI-NEXT:    s_lshl_b32 s14, s14, 24
; SI-NEXT:    s_and_b32 s12, s12, 0xffff
; SI-NEXT:    s_or_b32 s14, s14, s25
; SI-NEXT:    s_or_b32 s12, s12, s14
; SI-NEXT:    v_mov_b32_e32 v11, s12
; SI-NEXT:    s_and_b32 s12, s13, 0xff
; SI-NEXT:    s_lshl_b32 s13, s23, 8
; SI-NEXT:    v_and_b32_e32 v7, 0xff, v7
; SI-NEXT:    s_or_b32 s12, s12, s13
; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT:    v_lshlrev_b32_e32 v10, 24, v10
; SI-NEXT:    s_and_b32 s12, s12, 0xffff
; SI-NEXT:    v_or_b32_e32 v7, v10, v7
; SI-NEXT:    v_or_b32_e32 v7, s12, v7
; SI-NEXT:    s_and_b32 s10, s10, 0xff
; SI-NEXT:    s_lshl_b32 s12, s46, 8
; SI-NEXT:    s_or_b32 s10, s10, s12
; SI-NEXT:    s_and_b32 s12, s28, 0xff
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_lshl_b32 s13, s16, 24
; SI-NEXT:    s_and_b32 s10, s10, 0xffff
; SI-NEXT:    s_or_b32 s12, s13, s12
; SI-NEXT:    s_or_b32 s10, s10, s12
; SI-NEXT:    buffer_store_dword v7, v0, s[0:3], 0 offen offset:4
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_mov_b32_e32 v7, s10
; SI-NEXT:    s_and_b32 s10, s11, 0xff
; SI-NEXT:    s_lshl_b32 s11, s21, 8
; SI-NEXT:    v_and_b32_e32 v4, 0xff, v4
; SI-NEXT:    buffer_store_dword v7, v0, s[0:3], 0 offen offset:8
; SI-NEXT:    s_or_b32 s10, s10, s11
; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_lshlrev_b32_e32 v7, 24, v9
; SI-NEXT:    s_and_b32 s10, s10, 0xffff
; SI-NEXT:    v_or_b32_e32 v4, v7, v4
; SI-NEXT:    v_or_b32_e32 v4, s10, v4
; SI-NEXT:    s_and_b32 s8, s8, 0xff
; SI-NEXT:    s_lshl_b32 s10, s56, 8
; SI-NEXT:    s_or_b32 s8, s8, s10
; SI-NEXT:    s_and_b32 s10, s40, 0xff
; SI-NEXT:    s_lshl_b32 s10, s10, 16
; SI-NEXT:    s_lshl_b32 s11, s18, 24
; SI-NEXT:    s_and_b32 s8, s8, 0xffff
; SI-NEXT:    s_or_b32 s10, s11, s10
; SI-NEXT:    s_or_b32 s8, s8, s10
; SI-NEXT:    buffer_store_dword v4, v0, s[0:3], 0 offen offset:12
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_mov_b32_e32 v4, s8
; SI-NEXT:    s_and_b32 s8, s9, 0xff
; SI-NEXT:    s_lshl_b32 s9, s19, 8
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v3
; SI-NEXT:    buffer_store_dword v4, v0, s[0:3], 0 offen offset:16
; SI-NEXT:    s_or_b32 s8, s8, s9
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_lshlrev_b32_e32 v4, 24, v8
; SI-NEXT:    s_and_b32 s8, s8, 0xffff
; SI-NEXT:    v_or_b32_e32 v3, v4, v3
; SI-NEXT:    v_or_b32_e32 v3, s8, v3
; SI-NEXT:    s_and_b32 s6, s6, 0xff
; SI-NEXT:    s_lshl_b32 s8, s58, 8
; SI-NEXT:    s_or_b32 s6, s6, s8
; SI-NEXT:    s_and_b32 s8, s42, 0xff
; SI-NEXT:    s_lshl_b32 s8, s8, 16
; SI-NEXT:    s_lshl_b32 s9, s20, 24
; SI-NEXT:    s_and_b32 s6, s6, 0xffff
; SI-NEXT:    s_or_b32 s8, s9, s8
; SI-NEXT:    s_or_b32 s6, s6, s8
; SI-NEXT:    buffer_store_dword v3, v0, s[0:3], 0 offen offset:20
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_mov_b32_e32 v3, s6
; SI-NEXT:    s_and_b32 s6, s7, 0xff
; SI-NEXT:    s_lshl_b32 s7, s17, 8
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v2
; SI-NEXT:    buffer_store_dword v3, v0, s[0:3], 0 offen offset:24
; SI-NEXT:    s_or_b32 s6, s6, s7
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v6
; SI-NEXT:    s_and_b32 s6, s6, 0xffff
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v2, s6, v2
; SI-NEXT:    s_and_b32 s4, s4, 0xff
; SI-NEXT:    s_lshl_b32 s6, s60, 8
; SI-NEXT:    s_or_b32 s4, s4, s6
; SI-NEXT:    s_and_b32 s6, s24, 0xff
; SI-NEXT:    s_lshl_b32 s6, s6, 16
; SI-NEXT:    s_lshl_b32 s7, s22, 24
; SI-NEXT:    s_and_b32 s4, s4, 0xffff
; SI-NEXT:    s_or_b32 s6, s7, s6
; SI-NEXT:    s_lshr_b32 s15, s5, 8
; SI-NEXT:    s_or_b32 s4, s4, s6
; SI-NEXT:    buffer_store_dword v2, v0, s[0:3], 0 offen offset:28
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_mov_b32_e32 v2, s4
; SI-NEXT:    s_and_b32 s4, s5, 0xff
; SI-NEXT:    s_lshl_b32 s5, s15, 8
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1
; SI-NEXT:    buffer_store_dword v2, v0, s[0:3], 0 offen offset:32
; SI-NEXT:    s_or_b32 s4, s4, s5
; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_lshlrev_b32_e32 v2, 24, v5
; SI-NEXT:    s_and_b32 s4, s4, 0xffff
; SI-NEXT:    v_or_b32_e32 v1, v2, v1
; SI-NEXT:    v_or_b32_e32 v1, s4, v1
; SI-NEXT:    buffer_store_dword v11, v0, s[0:3], 0 offen
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v20f16_to_v40i8_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc0 .LBB61_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    s_lshr_b32 s14, s25, 24
; VI-NEXT:    s_lshr_b32 s15, s25, 16
; VI-NEXT:    s_lshr_b32 s26, s25, 8
; VI-NEXT:    s_lshr_b32 s27, s24, 16
; VI-NEXT:    s_lshr_b32 s28, s24, 8
; VI-NEXT:    s_lshr_b32 s29, s23, 24
; VI-NEXT:    s_lshr_b32 s40, s23, 16
; VI-NEXT:    s_lshr_b32 s41, s23, 8
; VI-NEXT:    s_lshr_b32 s42, s22, 16
; VI-NEXT:    s_lshr_b32 s43, s22, 8
; VI-NEXT:    s_lshr_b32 s44, s21, 24
; VI-NEXT:    s_lshr_b32 s45, s21, 16
; VI-NEXT:    s_lshr_b32 s46, s21, 8
; VI-NEXT:    s_lshr_b32 s47, s20, 16
; VI-NEXT:    s_lshr_b32 s56, s20, 8
; VI-NEXT:    s_lshr_b32 s57, s19, 24
; VI-NEXT:    s_lshr_b32 s58, s19, 16
; VI-NEXT:    s_lshr_b32 s59, s19, 8
; VI-NEXT:    s_lshr_b32 s60, s18, 16
; VI-NEXT:    s_lshr_b32 s61, s18, 8
; VI-NEXT:    s_lshr_b32 s62, s17, 24
; VI-NEXT:    s_lshr_b32 s63, s17, 16
; VI-NEXT:    s_lshr_b32 s72, s17, 8
; VI-NEXT:    s_lshr_b32 s73, s16, 16
; VI-NEXT:    s_lshr_b32 s74, s16, 8
; VI-NEXT:    s_lshr_b64 s[4:5], s[24:25], 24
; VI-NEXT:    s_lshr_b64 s[6:7], s[22:23], 24
; VI-NEXT:    s_lshr_b64 s[8:9], s[20:21], 24
; VI-NEXT:    s_lshr_b64 s[10:11], s[18:19], 24
; VI-NEXT:    s_lshr_b64 s[12:13], s[16:17], 24
; VI-NEXT:    v_mov_b32_e32 v9, s73
; VI-NEXT:    v_mov_b32_e32 v7, s63
; VI-NEXT:    v_mov_b32_e32 v12, s60
; VI-NEXT:    v_mov_b32_e32 v8, s58
; VI-NEXT:    v_mov_b32_e32 v16, s47
; VI-NEXT:    v_mov_b32_e32 v11, s45
; VI-NEXT:    v_mov_b32_e32 v19, s42
; VI-NEXT:    v_mov_b32_e32 v15, s40
; VI-NEXT:    v_mov_b32_e32 v23, s27
; VI-NEXT:    v_mov_b32_e32 v20, s15
; VI-NEXT:    v_mov_b32_e32 v14, s16
; VI-NEXT:    v_mov_b32_e32 v10, s17
; VI-NEXT:    v_mov_b32_e32 v18, s18
; VI-NEXT:    v_mov_b32_e32 v13, s19
; VI-NEXT:    v_mov_b32_e32 v21, s20
; VI-NEXT:    v_mov_b32_e32 v17, s21
; VI-NEXT:    v_mov_b32_e32 v24, s22
; VI-NEXT:    v_mov_b32_e32 v22, s23
; VI-NEXT:    v_mov_b32_e32 v26, s24
; VI-NEXT:    v_mov_b32_e32 v25, s25
; VI-NEXT:    v_mov_b32_e32 v6, s14
; VI-NEXT:    v_mov_b32_e32 v31, s29
; VI-NEXT:    v_mov_b32_e32 v33, s44
; VI-NEXT:    v_mov_b32_e32 v35, s57
; VI-NEXT:    v_mov_b32_e32 v38, s62
; VI-NEXT:    v_mov_b32_e32 v28, s28
; VI-NEXT:    v_mov_b32_e32 v27, s26
; VI-NEXT:    v_mov_b32_e32 v30, s43
; VI-NEXT:    v_mov_b32_e32 v29, s41
; VI-NEXT:    v_mov_b32_e32 v34, s56
; VI-NEXT:    v_mov_b32_e32 v32, s46
; VI-NEXT:    v_mov_b32_e32 v37, s61
; VI-NEXT:    v_mov_b32_e32 v36, s59
; VI-NEXT:    v_mov_b32_e32 v48, s74
; VI-NEXT:    v_mov_b32_e32 v39, s72
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_mov_b32_e32 v2, s6
; VI-NEXT:    v_mov_b32_e32 v3, s8
; VI-NEXT:    v_mov_b32_e32 v4, s10
; VI-NEXT:    v_mov_b32_e32 v5, s12
; VI-NEXT:    s_branch .LBB61_3
; VI-NEXT:  .LBB61_2: ; %cmp.true
; VI-NEXT:    s_lshr_b32 s4, s17, 16
; VI-NEXT:    v_mov_b32_e32 v1, 0x200
; VI-NEXT:    v_add_f16_e32 v7, s4, v1
; VI-NEXT:    s_lshr_b32 s4, s16, 16
; VI-NEXT:    v_add_f16_e32 v9, s4, v1
; VI-NEXT:    s_lshr_b32 s4, s19, 16
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v7
; VI-NEXT:    v_add_f16_e32 v10, s17, v1
; VI-NEXT:    v_add_f16_e32 v8, s4, v1
; VI-NEXT:    s_lshr_b32 s4, s18, 16
; VI-NEXT:    v_or_b32_e32 v50, v10, v2
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v9
; VI-NEXT:    v_add_f16_e32 v14, s16, v1
; VI-NEXT:    v_add_f16_e32 v12, s4, v1
; VI-NEXT:    s_lshr_b32 s4, s21, 16
; VI-NEXT:    v_or_b32_e32 v49, v14, v2
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v8
; VI-NEXT:    v_add_f16_e32 v13, s19, v1
; VI-NEXT:    v_add_f16_e32 v11, s4, v1
; VI-NEXT:    s_lshr_b32 s4, s20, 16
; VI-NEXT:    v_or_b32_e32 v6, v13, v2
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v12
; VI-NEXT:    v_add_f16_e32 v18, s18, v1
; VI-NEXT:    v_add_f16_e32 v16, s4, v1
; VI-NEXT:    s_lshr_b32 s4, s23, 16
; VI-NEXT:    v_or_b32_e32 v5, v18, v2
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v11
; VI-NEXT:    v_add_f16_e32 v17, s21, v1
; VI-NEXT:    v_add_f16_e32 v15, s4, v1
; VI-NEXT:    s_lshr_b32 s4, s22, 16
; VI-NEXT:    v_or_b32_e32 v36, v17, v2
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v16
; VI-NEXT:    v_add_f16_e32 v21, s20, v1
; VI-NEXT:    v_add_f16_e32 v19, s4, v1
; VI-NEXT:    s_lshr_b32 s4, s25, 16
; VI-NEXT:    v_or_b32_e32 v35, v21, v2
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v15
; VI-NEXT:    v_add_f16_e32 v22, s23, v1
; VI-NEXT:    s_lshr_b32 s5, s24, 16
; VI-NEXT:    v_add_f16_e32 v20, s4, v1
; VI-NEXT:    v_or_b32_e32 v4, v22, v2
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v19
; VI-NEXT:    v_add_f16_e32 v24, s22, v1
; VI-NEXT:    v_add_f16_e32 v25, s25, v1
; VI-NEXT:    v_add_f16_e32 v23, s5, v1
; VI-NEXT:    v_add_f16_e32 v26, s24, v1
; VI-NEXT:    v_lshlrev_b32_e32 v1, 16, v20
; VI-NEXT:    v_or_b32_e32 v3, v24, v2
; VI-NEXT:    v_or_b32_e32 v2, v25, v1
; VI-NEXT:    v_lshlrev_b32_e32 v1, 16, v23
; VI-NEXT:    v_or_b32_e32 v1, v26, v1
; VI-NEXT:    v_lshrrev_b32_e32 v27, 8, v2
; VI-NEXT:    v_lshrrev_b32_e32 v28, 8, v1
; VI-NEXT:    v_lshrrev_b64 v[1:2], 24, v[1:2]
; VI-NEXT:    v_lshrrev_b32_e32 v30, 8, v3
; VI-NEXT:    v_lshrrev_b64 v[2:3], 24, v[3:4]
; VI-NEXT:    v_lshrrev_b32_e32 v29, 8, v4
; VI-NEXT:    v_lshrrev_b64 v[3:4], 24, v[35:36]
; VI-NEXT:    v_lshrrev_b32_e32 v37, 8, v5
; VI-NEXT:    v_lshrrev_b64 v[4:5], 24, v[5:6]
; VI-NEXT:    v_lshrrev_b32_e32 v32, 8, v36
; VI-NEXT:    v_lshrrev_b32_e32 v36, 8, v6
; VI-NEXT:    v_lshrrev_b64 v[5:6], 24, v[49:50]
; VI-NEXT:    v_lshrrev_b32_e32 v34, 8, v35
; VI-NEXT:    v_lshrrev_b32_e32 v39, 8, v50
; VI-NEXT:    v_lshrrev_b32_e32 v48, 8, v49
; VI-NEXT:    v_bfe_u32 v6, v20, 8, 8
; VI-NEXT:    v_bfe_u32 v31, v15, 8, 8
; VI-NEXT:    v_bfe_u32 v33, v11, 8, 8
; VI-NEXT:    v_bfe_u32 v35, v8, 8, 8
; VI-NEXT:    v_bfe_u32 v38, v7, 8, 8
; VI-NEXT:  .LBB61_3: ; %end
; VI-NEXT:    s_mov_b32 s4, 0xc0c0004
; VI-NEXT:    v_perm_b32 v5, v9, v5, s4
; VI-NEXT:    v_perm_b32 v9, v14, v48, s4
; VI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT:    v_or_b32_e32 v5, v9, v5
; VI-NEXT:    v_perm_b32 v7, v7, v38, s4
; VI-NEXT:    buffer_store_dword v5, v0, s[0:3], 0 offen
; VI-NEXT:    v_perm_b32 v5, v10, v39, s4
; VI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT:    v_or_b32_e32 v5, v5, v7
; VI-NEXT:    v_perm_b32 v4, v12, v4, s4
; VI-NEXT:    buffer_store_dword v5, v0, s[0:3], 0 offen offset:4
; VI-NEXT:    v_perm_b32 v5, v18, v37, s4
; VI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT:    v_or_b32_e32 v4, v5, v4
; VI-NEXT:    v_perm_b32 v5, v8, v35, s4
; VI-NEXT:    buffer_store_dword v4, v0, s[0:3], 0 offen offset:8
; VI-NEXT:    v_perm_b32 v4, v13, v36, s4
; VI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT:    v_or_b32_e32 v4, v4, v5
; VI-NEXT:    v_perm_b32 v3, v16, v3, s4
; VI-NEXT:    buffer_store_dword v4, v0, s[0:3], 0 offen offset:12
; VI-NEXT:    v_perm_b32 v4, v21, v34, s4
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_e32 v3, v4, v3
; VI-NEXT:    v_perm_b32 v4, v11, v33, s4
; VI-NEXT:    buffer_store_dword v3, v0, s[0:3], 0 offen offset:16
; VI-NEXT:    v_perm_b32 v3, v17, v32, s4
; VI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT:    v_or_b32_e32 v3, v3, v4
; VI-NEXT:    v_perm_b32 v2, v19, v2, s4
; VI-NEXT:    buffer_store_dword v3, v0, s[0:3], 0 offen offset:20
; VI-NEXT:    v_perm_b32 v3, v24, v30, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v2, v3, v2
; VI-NEXT:    v_perm_b32 v3, v15, v31, s4
; VI-NEXT:    buffer_store_dword v2, v0, s[0:3], 0 offen offset:24
; VI-NEXT:    v_perm_b32 v2, v22, v29, s4
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_e32 v2, v2, v3
; VI-NEXT:    v_perm_b32 v1, v23, v1, s4
; VI-NEXT:    buffer_store_dword v2, v0, s[0:3], 0 offen offset:28
; VI-NEXT:    v_perm_b32 v2, v26, v28, s4
; VI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT:    v_or_b32_e32 v1, v2, v1
; VI-NEXT:    v_perm_b32 v2, v20, v6, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; VI-NEXT:    v_perm_b32 v1, v25, v27, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v20f16_to_v40i8_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc0 .LBB61_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    s_lshr_b32 s14, s25, 24
; GFX9-NEXT:    s_lshr_b32 s15, s25, 16
; GFX9-NEXT:    s_lshr_b32 s26, s25, 8
; GFX9-NEXT:    s_lshr_b32 s27, s24, 16
; GFX9-NEXT:    s_lshr_b32 s28, s24, 8
; GFX9-NEXT:    s_lshr_b32 s29, s23, 24
; GFX9-NEXT:    s_lshr_b32 s40, s23, 16
; GFX9-NEXT:    s_lshr_b32 s41, s23, 8
; GFX9-NEXT:    s_lshr_b32 s42, s22, 16
; GFX9-NEXT:    s_lshr_b32 s43, s22, 8
; GFX9-NEXT:    s_lshr_b32 s44, s21, 24
; GFX9-NEXT:    s_lshr_b32 s45, s21, 16
; GFX9-NEXT:    s_lshr_b32 s46, s21, 8
; GFX9-NEXT:    s_lshr_b32 s47, s20, 16
; GFX9-NEXT:    s_lshr_b32 s56, s20, 8
; GFX9-NEXT:    s_lshr_b32 s57, s19, 24
; GFX9-NEXT:    s_lshr_b32 s58, s19, 16
; GFX9-NEXT:    s_lshr_b32 s59, s19, 8
; GFX9-NEXT:    s_lshr_b32 s60, s18, 16
; GFX9-NEXT:    s_lshr_b32 s61, s18, 8
; GFX9-NEXT:    s_lshr_b32 s62, s17, 24
; GFX9-NEXT:    s_lshr_b32 s63, s17, 16
; GFX9-NEXT:    s_lshr_b32 s72, s17, 8
; GFX9-NEXT:    s_lshr_b32 s73, s16, 16
; GFX9-NEXT:    s_lshr_b32 s74, s16, 8
; GFX9-NEXT:    s_lshr_b64 s[4:5], s[24:25], 24
; GFX9-NEXT:    s_lshr_b64 s[6:7], s[22:23], 24
; GFX9-NEXT:    s_lshr_b64 s[8:9], s[20:21], 24
; GFX9-NEXT:    s_lshr_b64 s[10:11], s[18:19], 24
; GFX9-NEXT:    s_lshr_b64 s[12:13], s[16:17], 24
; GFX9-NEXT:    v_mov_b32_e32 v9, s16
; GFX9-NEXT:    v_mov_b32_e32 v10, s17
; GFX9-NEXT:    v_mov_b32_e32 v7, s18
; GFX9-NEXT:    v_mov_b32_e32 v8, s19
; GFX9-NEXT:    v_mov_b32_e32 v5, s20
; GFX9-NEXT:    v_mov_b32_e32 v6, s21
; GFX9-NEXT:    v_mov_b32_e32 v3, s22
; GFX9-NEXT:    v_mov_b32_e32 v4, s23
; GFX9-NEXT:    v_mov_b32_e32 v1, s24
; GFX9-NEXT:    v_mov_b32_e32 v2, s25
; GFX9-NEXT:    v_mov_b32_e32 v16, s74
; GFX9-NEXT:    v_mov_b32_e32 v48, s73
; GFX9-NEXT:    v_mov_b32_e32 v39, s72
; GFX9-NEXT:    v_mov_b32_e32 v37, s63
; GFX9-NEXT:    v_mov_b32_e32 v38, s62
; GFX9-NEXT:    v_mov_b32_e32 v36, s61
; GFX9-NEXT:    v_mov_b32_e32 v35, s60
; GFX9-NEXT:    v_mov_b32_e32 v34, s59
; GFX9-NEXT:    v_mov_b32_e32 v32, s58
; GFX9-NEXT:    v_mov_b32_e32 v33, s57
; GFX9-NEXT:    v_mov_b32_e32 v31, s56
; GFX9-NEXT:    v_mov_b32_e32 v30, s47
; GFX9-NEXT:    v_mov_b32_e32 v29, s46
; GFX9-NEXT:    v_mov_b32_e32 v27, s45
; GFX9-NEXT:    v_mov_b32_e32 v28, s44
; GFX9-NEXT:    v_mov_b32_e32 v26, s43
; GFX9-NEXT:    v_mov_b32_e32 v25, s42
; GFX9-NEXT:    v_mov_b32_e32 v24, s41
; GFX9-NEXT:    v_mov_b32_e32 v22, s40
; GFX9-NEXT:    v_mov_b32_e32 v23, s29
; GFX9-NEXT:    v_mov_b32_e32 v21, s28
; GFX9-NEXT:    v_mov_b32_e32 v20, s27
; GFX9-NEXT:    v_mov_b32_e32 v19, s26
; GFX9-NEXT:    v_mov_b32_e32 v17, s15
; GFX9-NEXT:    v_mov_b32_e32 v18, s14
; GFX9-NEXT:    v_mov_b32_e32 v11, s4
; GFX9-NEXT:    v_mov_b32_e32 v12, s6
; GFX9-NEXT:    v_mov_b32_e32 v13, s8
; GFX9-NEXT:    v_mov_b32_e32 v14, s10
; GFX9-NEXT:    v_mov_b32_e32 v15, s12
; GFX9-NEXT:    s_branch .LBB61_3
; GFX9-NEXT:  .LBB61_2: ; %cmp.true
; GFX9-NEXT:    v_mov_b32_e32 v1, 0x200
; GFX9-NEXT:    v_pk_add_f16 v10, s17, v1 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v9, s16, v1 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v8, s19, v1 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v7, s18, v1 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v6, s21, v1 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v5, s20, v1 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v4, s23, v1 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v3, s22, v1 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v2, s25, v1 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v1, s24, v1 op_sel_hi:[1,0]
; GFX9-NEXT:    v_lshrrev_b64 v[11:12], 24, v[1:2]
; GFX9-NEXT:    v_lshrrev_b64 v[12:13], 24, v[3:4]
; GFX9-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX9-NEXT:    v_lshrrev_b64 v[14:15], 24, v[7:8]
; GFX9-NEXT:    v_lshrrev_b64 v[15:16], 24, v[9:10]
; GFX9-NEXT:    v_lshrrev_b32_e32 v18, 24, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v17, 16, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v19, 8, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v20, 16, v1
; GFX9-NEXT:    v_lshrrev_b32_e32 v21, 8, v1
; GFX9-NEXT:    v_lshrrev_b32_e32 v23, 24, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v22, 16, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v24, 8, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v25, 16, v3
; GFX9-NEXT:    v_lshrrev_b32_e32 v26, 8, v3
; GFX9-NEXT:    v_lshrrev_b32_e32 v28, 24, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v27, 16, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; GFX9-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; GFX9-NEXT:    v_lshrrev_b32_e32 v33, 24, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v32, 16, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v34, 8, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v35, 16, v7
; GFX9-NEXT:    v_lshrrev_b32_e32 v36, 8, v7
; GFX9-NEXT:    v_lshrrev_b32_e32 v38, 24, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v37, 16, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v39, 8, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v48, 16, v9
; GFX9-NEXT:    v_lshrrev_b32_e32 v16, 8, v9
; GFX9-NEXT:  .LBB61_3: ; %end
; GFX9-NEXT:    s_mov_b32 s4, 0xc0c0004
; GFX9-NEXT:    v_perm_b32 v15, v48, v15, s4
; GFX9-NEXT:    v_perm_b32 v9, v9, v16, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
; GFX9-NEXT:    v_or_b32_e32 v9, v9, v15
; GFX9-NEXT:    buffer_store_dword v9, v0, s[0:3], 0 offen
; GFX9-NEXT:    v_perm_b32 v9, v10, v39, s4
; GFX9-NEXT:    v_perm_b32 v10, v37, v38, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; GFX9-NEXT:    v_or_b32_e32 v9, v9, v10
; GFX9-NEXT:    buffer_store_dword v9, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT:    v_perm_b32 v9, v35, v14, s4
; GFX9-NEXT:    v_perm_b32 v7, v7, v36, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; GFX9-NEXT:    v_or_b32_e32 v7, v7, v9
; GFX9-NEXT:    buffer_store_dword v7, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT:    v_perm_b32 v7, v8, v34, s4
; GFX9-NEXT:    v_perm_b32 v8, v32, v33, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; GFX9-NEXT:    v_or_b32_e32 v7, v7, v8
; GFX9-NEXT:    buffer_store_dword v7, v0, s[0:3], 0 offen offset:12
; GFX9-NEXT:    v_perm_b32 v7, v30, v13, s4
; GFX9-NEXT:    v_perm_b32 v5, v5, v31, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; GFX9-NEXT:    v_or_b32_e32 v5, v5, v7
; GFX9-NEXT:    buffer_store_dword v5, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT:    v_perm_b32 v5, v6, v29, s4
; GFX9-NEXT:    v_perm_b32 v6, v27, v28, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; GFX9-NEXT:    v_or_b32_e32 v5, v5, v6
; GFX9-NEXT:    buffer_store_dword v5, v0, s[0:3], 0 offen offset:20
; GFX9-NEXT:    v_perm_b32 v5, v25, v12, s4
; GFX9-NEXT:    v_perm_b32 v3, v3, v26, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; GFX9-NEXT:    v_or_b32_e32 v3, v3, v5
; GFX9-NEXT:    buffer_store_dword v3, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT:    v_perm_b32 v3, v4, v24, s4
; GFX9-NEXT:    v_perm_b32 v4, v22, v23, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; GFX9-NEXT:    v_or_b32_e32 v3, v3, v4
; GFX9-NEXT:    buffer_store_dword v3, v0, s[0:3], 0 offen offset:28
; GFX9-NEXT:    v_perm_b32 v3, v20, v11, s4
; GFX9-NEXT:    v_perm_b32 v1, v1, v21, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT:    v_perm_b32 v1, v2, v19, s4
; GFX9-NEXT:    v_perm_b32 v2, v17, v18, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v2
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v20f16_to_v40i8_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc0 .LBB61_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-NEXT:    s_lshr_b32 s14, s21, 24
; GFX11-NEXT:    s_lshr_b32 s15, s21, 16
; GFX11-NEXT:    s_lshr_b32 s22, s21, 8
; GFX11-NEXT:    s_lshr_b32 s23, s20, 16
; GFX11-NEXT:    s_lshr_b32 s24, s20, 8
; GFX11-NEXT:    s_lshr_b32 s25, s19, 24
; GFX11-NEXT:    s_lshr_b32 s26, s19, 16
; GFX11-NEXT:    s_lshr_b32 s27, s19, 8
; GFX11-NEXT:    s_lshr_b32 s28, s18, 16
; GFX11-NEXT:    s_lshr_b32 s29, s18, 8
; GFX11-NEXT:    s_lshr_b32 s40, s17, 24
; GFX11-NEXT:    s_lshr_b32 s41, s17, 16
; GFX11-NEXT:    s_lshr_b32 s42, s17, 8
; GFX11-NEXT:    s_lshr_b32 s43, s16, 16
; GFX11-NEXT:    s_lshr_b32 s44, s16, 8
; GFX11-NEXT:    s_lshr_b32 s45, s3, 24
; GFX11-NEXT:    s_lshr_b32 s46, s3, 16
; GFX11-NEXT:    s_lshr_b32 s47, s3, 8
; GFX11-NEXT:    s_lshr_b32 s56, s2, 16
; GFX11-NEXT:    s_lshr_b32 s57, s2, 8
; GFX11-NEXT:    s_lshr_b32 s58, s1, 24
; GFX11-NEXT:    s_lshr_b32 s59, s1, 16
; GFX11-NEXT:    s_lshr_b32 s60, s1, 8
; GFX11-NEXT:    s_lshr_b32 s61, s0, 16
; GFX11-NEXT:    s_lshr_b32 s62, s0, 8
; GFX11-NEXT:    s_lshr_b64 s[4:5], s[20:21], 24
; GFX11-NEXT:    s_lshr_b64 s[6:7], s[18:19], 24
; GFX11-NEXT:    s_lshr_b64 s[8:9], s[16:17], 24
; GFX11-NEXT:    s_lshr_b64 s[10:11], s[2:3], 24
; GFX11-NEXT:    s_lshr_b64 s[12:13], s[0:1], 24
; GFX11-NEXT:    v_dual_mov_b32 v9, s0 :: v_dual_mov_b32 v10, s1
; GFX11-NEXT:    v_dual_mov_b32 v7, s2 :: v_dual_mov_b32 v8, s3
; GFX11-NEXT:    v_dual_mov_b32 v5, s16 :: v_dual_mov_b32 v6, s17
; GFX11-NEXT:    v_dual_mov_b32 v3, s18 :: v_dual_mov_b32 v4, s19
; GFX11-NEXT:    v_dual_mov_b32 v1, s20 :: v_dual_mov_b32 v2, s21
; GFX11-NEXT:    v_dual_mov_b32 v39, s62 :: v_dual_mov_b32 v48, s61
; GFX11-NEXT:    v_dual_mov_b32 v38, s60 :: v_dual_mov_b32 v37, s58
; GFX11-NEXT:    v_dual_mov_b32 v36, s59 :: v_dual_mov_b32 v35, s57
; GFX11-NEXT:    v_dual_mov_b32 v34, s56 :: v_dual_mov_b32 v33, s45
; GFX11-NEXT:    v_dual_mov_b32 v30, s47 :: v_dual_mov_b32 v29, s44
; GFX11-NEXT:    v_dual_mov_b32 v32, s46 :: v_dual_mov_b32 v31, s43
; GFX11-NEXT:    v_dual_mov_b32 v25, s42 :: v_dual_mov_b32 v28, s40
; GFX11-NEXT:    v_dual_mov_b32 v27, s41 :: v_dual_mov_b32 v24, s29
; GFX11-NEXT:    v_dual_mov_b32 v26, s28 :: v_dual_mov_b32 v23, s25
; GFX11-NEXT:    v_dual_mov_b32 v20, s27 :: v_dual_mov_b32 v17, s24
; GFX11-NEXT:    v_dual_mov_b32 v22, s26 :: v_dual_mov_b32 v21, s23
; GFX11-NEXT:    v_dual_mov_b32 v16, s22 :: v_dual_mov_b32 v19, s14
; GFX11-NEXT:    v_dual_mov_b32 v18, s15 :: v_dual_mov_b32 v11, s4
; GFX11-NEXT:    v_dual_mov_b32 v12, s6 :: v_dual_mov_b32 v13, s8
; GFX11-NEXT:    v_dual_mov_b32 v14, s10 :: v_dual_mov_b32 v15, s12
; GFX11-NEXT:    s_branch .LBB61_3
; GFX11-NEXT:  .LBB61_2: ; %cmp.true
; GFX11-NEXT:    v_pk_add_f16 v2, s21, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v1, s20, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v4, s19, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v3, s18, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v6, s17, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v5, s16, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v8, s3, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v7, s2, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v10, s1, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v9, s0, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[1:2]
; GFX11-NEXT:    v_lshrrev_b64 v[12:13], 24, v[3:4]
; GFX11-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX11-NEXT:    v_lshrrev_b64 v[14:15], 24, v[7:8]
; GFX11-NEXT:    v_lshrrev_b64 v[15:16], 24, v[9:10]
; GFX11-NEXT:    v_lshrrev_b32_e32 v19, 24, v2
; GFX11-NEXT:    v_lshrrev_b32_e32 v18, 16, v2
; GFX11-NEXT:    v_lshrrev_b32_e32 v16, 8, v2
; GFX11-NEXT:    v_lshrrev_b32_e32 v21, 16, v1
; GFX11-NEXT:    v_lshrrev_b32_e32 v17, 8, v1
; GFX11-NEXT:    v_lshrrev_b32_e32 v23, 24, v4
; GFX11-NEXT:    v_lshrrev_b32_e32 v22, 16, v4
; GFX11-NEXT:    v_lshrrev_b32_e32 v20, 8, v4
; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 16, v3
; GFX11-NEXT:    v_lshrrev_b32_e32 v24, 8, v3
; GFX11-NEXT:    v_lshrrev_b32_e32 v28, 24, v6
; GFX11-NEXT:    v_lshrrev_b32_e32 v27, 16, v6
; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 8, v6
; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 16, v5
; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 8, v5
; GFX11-NEXT:    v_lshrrev_b32_e32 v33, 24, v8
; GFX11-NEXT:    v_lshrrev_b32_e32 v32, 16, v8
; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 8, v8
; GFX11-NEXT:    v_lshrrev_b32_e32 v34, 16, v7
; GFX11-NEXT:    v_lshrrev_b32_e32 v35, 8, v7
; GFX11-NEXT:    v_lshrrev_b32_e32 v37, 24, v10
; GFX11-NEXT:    v_lshrrev_b32_e32 v36, 16, v10
; GFX11-NEXT:    v_lshrrev_b32_e32 v38, 8, v10
; GFX11-NEXT:    v_lshrrev_b32_e32 v48, 16, v9
; GFX11-NEXT:    v_lshrrev_b32_e32 v39, 8, v9
; GFX11-NEXT:  .LBB61_3: ; %end
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT:    v_perm_b32 v15, v48, v15, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v9, v9, v39, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v36, v36, v37, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v35, v7, v35, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v14, v34, v14, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v15
; GFX11-NEXT:    v_perm_b32 v15, v32, v33, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v13, v31, v13, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v10, v10, v38, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v31, 16, v36
; GFX11-NEXT:    v_or_b32_e32 v7, v9, v7
; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v14
; GFX11-NEXT:    v_perm_b32 v14, v8, v30, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
; GFX11-NEXT:    v_perm_b32 v5, v5, v29, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
; GFX11-NEXT:    v_or_b32_e32 v8, v10, v31
; GFX11-NEXT:    v_perm_b32 v27, v27, v28, 0xc0c0004
; GFX11-NEXT:    v_or_b32_e32 v10, v14, v15
; GFX11-NEXT:    v_perm_b32 v14, v22, v23, 0xc0c0004
; GFX11-NEXT:    v_or_b32_e32 v13, v5, v13
; GFX11-NEXT:    v_perm_b32 v5, v26, v12, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v11, v21, v11, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v15, v18, v19, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v6, v6, v25, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v27
; GFX11-NEXT:    v_perm_b32 v3, v3, v24, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; GFX11-NEXT:    v_perm_b32 v4, v4, v20, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v14
; GFX11-NEXT:    v_perm_b32 v1, v1, v17, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; GFX11-NEXT:    v_perm_b32 v2, v2, v16, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v17, 16, v15
; GFX11-NEXT:    v_or_b32_e32 v9, v35, v9
; GFX11-NEXT:    v_or_b32_e32 v14, v6, v12
; GFX11-NEXT:    v_or_b32_e32 v15, v3, v5
; GFX11-NEXT:    v_or_b32_e32 v16, v4, v18
; GFX11-NEXT:    v_or_b32_e32 v1, v1, v11
; GFX11-NEXT:    v_or_b32_e32 v2, v2, v17
; GFX11-NEXT:    s_clause 0x2
; GFX11-NEXT:    scratch_store_b128 v0, v[7:10], off
; GFX11-NEXT:    scratch_store_b128 v0, v[13:16], off offset:16
; GFX11-NEXT:    scratch_store_b64 v0, v[1:2], off offset:32
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <20 x half> %a, splat (half 0xH0200)
  %a2 = bitcast <20 x half> %a1 to <40 x i8>
  br label %end

cmp.false:
  %a3 = bitcast <20 x half> %a to <40 x i8>
  br label %end

end:
  %phi = phi <40 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <40 x i8> %phi
}

define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v40i8_to_v20f16:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    buffer_store_dword v40, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v41, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v42, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v43, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v44, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v45, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v46, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v47, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v56, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v57, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v58, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v59, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; SI-NEXT:    buffer_load_dword v31, off, s[0:3], s32
; SI-NEXT:    buffer_load_dword v37, off, s[0:3], s32 offset:36
; SI-NEXT:    buffer_load_dword v38, off, s[0:3], s32 offset:32
; SI-NEXT:    buffer_load_dword v55, off, s[0:3], s32 offset:28
; SI-NEXT:    buffer_load_dword v39, off, s[0:3], s32 offset:24
; SI-NEXT:    buffer_load_dword v43, off, s[0:3], s32 offset:20
; SI-NEXT:    buffer_load_dword v48, off, s[0:3], s32 offset:16
; SI-NEXT:    buffer_load_dword v42, off, s[0:3], s32 offset:12
; SI-NEXT:    buffer_load_dword v49, off, s[0:3], s32 offset:8
; SI-NEXT:    buffer_load_dword v52, off, s[0:3], s32 offset:4
; SI-NEXT:    v_lshlrev_b32_e32 v33, 8, v5
; SI-NEXT:    v_lshlrev_b32_e32 v32, 24, v7
; SI-NEXT:    v_lshlrev_b32_e32 v34, 24, v3
; SI-NEXT:    v_lshlrev_b32_e32 v50, 8, v13
; SI-NEXT:    v_lshlrev_b32_e32 v36, 24, v15
; SI-NEXT:    v_lshlrev_b32_e32 v51, 24, v11
; SI-NEXT:    v_lshlrev_b32_e32 v40, 8, v21
; SI-NEXT:    v_lshlrev_b32_e32 v53, 24, v23
; SI-NEXT:    v_lshlrev_b32_e32 v41, 24, v19
; SI-NEXT:    s_waitcnt expcnt(6)
; SI-NEXT:    v_lshlrev_b32_e32 v45, 8, v29
; SI-NEXT:    s_waitcnt expcnt(5)
; SI-NEXT:    v_lshlrev_b32_e32 v46, 24, v27
; SI-NEXT:    v_lshlrev_b32_e32 v29, 8, v1
; SI-NEXT:    v_lshlrev_b32_e32 v35, 8, v9
; SI-NEXT:    v_lshlrev_b32_e32 v54, 8, v17
; SI-NEXT:    v_lshlrev_b32_e32 v44, 8, v25
; SI-NEXT:    ; implicit-def: $vgpr27
; SI-NEXT:    ; implicit-def: $vgpr17
; SI-NEXT:    ; implicit-def: $vgpr1
; SI-NEXT:    ; implicit-def: $vgpr21
; SI-NEXT:    ; implicit-def: $vgpr19
; SI-NEXT:    ; implicit-def: $vgpr3
; SI-NEXT:    ; implicit-def: $vgpr15
; SI-NEXT:    ; implicit-def: $vgpr23
; SI-NEXT:    ; implicit-def: $vgpr5
; SI-NEXT:    ; implicit-def: $vgpr13
; SI-NEXT:    ; implicit-def: $vgpr25
; SI-NEXT:    ; implicit-def: $vgpr7
; SI-NEXT:    ; implicit-def: $vgpr11
; SI-NEXT:    ; implicit-def: $vgpr9
; SI-NEXT:    s_waitcnt vmcnt(9) expcnt(4)
; SI-NEXT:    v_lshlrev_b32_e32 v47, 24, v31
; SI-NEXT:    s_waitcnt vmcnt(8)
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v37
; SI-NEXT:    s_waitcnt vmcnt(7) expcnt(3)
; SI-NEXT:    v_lshlrev_b32_e32 v56, 24, v38
; SI-NEXT:    ; implicit-def: $vgpr37
; SI-NEXT:    ; implicit-def: $vgpr38
; SI-NEXT:    ; implicit-def: $vgpr31
; SI-NEXT:    s_waitcnt vmcnt(5) expcnt(1)
; SI-NEXT:    v_lshlrev_b32_e32 v58, 8, v39
; SI-NEXT:    ; implicit-def: $vgpr39
; SI-NEXT:    s_waitcnt vmcnt(3) expcnt(0)
; SI-NEXT:    v_lshlrev_b32_e32 v59, 24, v48
; SI-NEXT:    ; implicit-def: $vgpr48
; SI-NEXT:    s_waitcnt vmcnt(1)
; SI-NEXT:    v_lshlrev_b32_e32 v57, 8, v49
; SI-NEXT:    ; implicit-def: $vgpr49
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB62_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v2
; SI-NEXT:    v_and_b32_e32 v0, 0xff, v0
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_and_b32_e32 v5, 0xff, v14
; SI-NEXT:    v_or_b32_e32 v0, v0, v29
; SI-NEXT:    v_or_b32_e32 v2, v34, v2
; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v6
; SI-NEXT:    v_or_b32_e32 v6, v36, v5
; SI-NEXT:    v_and_b32_e32 v5, 0xff, v10
; SI-NEXT:    v_or_b32_e32 v27, v0, v2
; SI-NEXT:    v_and_b32_e32 v0, 0xff, v8
; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT:    v_and_b32_e32 v7, 0xff, v22
; SI-NEXT:    v_or_b32_e32 v0, v0, v35
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_or_b32_e32 v10, v51, v5
; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT:    v_and_b32_e32 v15, 0xff, v55
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v4
; SI-NEXT:    v_or_b32_e32 v4, v32, v3
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v12
; SI-NEXT:    v_or_b32_e32 v12, v53, v7
; SI-NEXT:    v_and_b32_e32 v7, 0xff, v18
; SI-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT:    v_or_b32_e32 v21, v0, v10
; SI-NEXT:    v_and_b32_e32 v0, 0xff, v16
; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT:    v_and_b32_e32 v9, 0xff, v30
; SI-NEXT:    v_or_b32_e32 v18, v56, v15
; SI-NEXT:    v_and_b32_e32 v15, 0xff, v42
; SI-NEXT:    v_or_b32_e32 v0, v0, v54
; SI-NEXT:    v_or_b32_e32 v11, v41, v7
; SI-NEXT:    v_and_b32_e32 v7, 0xff, v28
; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_and_b32_e32 v5, 0xff, v20
; SI-NEXT:    v_or_b32_e32 v7, v7, v45
; SI-NEXT:    v_or_b32_e32 v14, v47, v9
; SI-NEXT:    v_and_b32_e32 v9, 0xff, v26
; SI-NEXT:    v_or_b32_e32 v20, v59, v15
; SI-NEXT:    v_or_b32_e32 v15, v0, v11
; SI-NEXT:    v_and_b32_e32 v0, 0xff, v24
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT:    v_or_b32_e32 v0, v0, v44
; SI-NEXT:    v_or_b32_e32 v7, v7, v14
; SI-NEXT:    v_or_b32_e32 v13, v46, v9
; SI-NEXT:    v_and_b32_e32 v9, 0xff, v43
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_or_b32_e32 v1, v1, v33
; SI-NEXT:    v_or_b32_e32 v3, v3, v50
; SI-NEXT:    v_or_b32_e32 v5, v5, v40
; SI-NEXT:    v_alignbit_b32 v25, v7, v13, 16
; SI-NEXT:    v_or_b32_e32 v9, v9, v58
; SI-NEXT:    v_or_b32_e32 v13, v0, v13
; SI-NEXT:    s_waitcnt vmcnt(0)
; SI-NEXT:    v_and_b32_e32 v0, 0xff, v52
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT:    v_or_b32_e32 v0, v0, v57
; SI-NEXT:    v_or_b32_e32 v1, v1, v4
; SI-NEXT:    v_or_b32_e32 v3, v3, v6
; SI-NEXT:    v_or_b32_e32 v5, v5, v12
; SI-NEXT:    v_or_b32_e32 v9, v9, v18
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_alignbit_b32 v17, v1, v2, 16
; SI-NEXT:    v_alignbit_b32 v19, v3, v10, 16
; SI-NEXT:    v_alignbit_b32 v23, v5, v11, 16
; SI-NEXT:    v_alignbit_b32 v31, v9, v20, 16
; SI-NEXT:    v_or_b32_e32 v11, v0, v20
; SI-NEXT:    v_lshrrev_b32_e32 v37, 16, v4
; SI-NEXT:    v_lshrrev_b32_e32 v38, 16, v6
; SI-NEXT:    v_lshrrev_b32_e32 v39, 16, v12
; SI-NEXT:    v_lshrrev_b32_e32 v48, 16, v14
; SI-NEXT:    v_lshrrev_b32_e32 v49, 16, v18
; SI-NEXT:    ; implicit-def: $vgpr0
; SI-NEXT:    ; implicit-def: $vgpr2
; SI-NEXT:    ; implicit-def: $vgpr4
; SI-NEXT:    ; implicit-def: $vgpr6
; SI-NEXT:    ; implicit-def: $vgpr8
; SI-NEXT:    ; implicit-def: $vgpr10
; SI-NEXT:    ; implicit-def: $vgpr12
; SI-NEXT:    ; implicit-def: $vgpr14
; SI-NEXT:    ; implicit-def: $vgpr16
; SI-NEXT:    ; implicit-def: $vgpr18
; SI-NEXT:    ; implicit-def: $vgpr20
; SI-NEXT:    ; implicit-def: $vgpr22
; SI-NEXT:    ; implicit-def: $vgpr24
; SI-NEXT:    ; implicit-def: $vgpr26
; SI-NEXT:    ; implicit-def: $vgpr28
; SI-NEXT:    ; implicit-def: $vgpr30
; SI-NEXT:    ; implicit-def: $vgpr52
; SI-NEXT:    ; implicit-def: $vgpr42
; SI-NEXT:    ; implicit-def: $vgpr43
; SI-NEXT:    ; implicit-def: $vgpr55
; SI-NEXT:    ; implicit-def: $vgpr33
; SI-NEXT:    ; implicit-def: $vgpr32
; SI-NEXT:    ; implicit-def: $vgpr34
; SI-NEXT:    ; implicit-def: $vgpr50
; SI-NEXT:    ; implicit-def: $vgpr36
; SI-NEXT:    ; implicit-def: $vgpr51
; SI-NEXT:    ; implicit-def: $vgpr40
; SI-NEXT:    ; implicit-def: $vgpr53
; SI-NEXT:    ; implicit-def: $vgpr41
; SI-NEXT:    ; implicit-def: $vgpr45
; SI-NEXT:    ; implicit-def: $vgpr47
; SI-NEXT:    ; implicit-def: $vgpr46
; SI-NEXT:    ; implicit-def: $vgpr58
; SI-NEXT:    ; implicit-def: $vgpr56
; SI-NEXT:    ; implicit-def: $vgpr59
; SI-NEXT:    ; implicit-def: $vgpr29
; SI-NEXT:    ; implicit-def: $vgpr35
; SI-NEXT:    ; implicit-def: $vgpr54
; SI-NEXT:    ; implicit-def: $vgpr44
; SI-NEXT:    ; implicit-def: $vgpr57
; SI-NEXT:  .LBB62_2: ; %Flow
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB62_4
; SI-NEXT:  ; %bb.3: ; %cmp.true
; SI-NEXT:    s_waitcnt vmcnt(0)
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v52
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v42
; SI-NEXT:    v_or_b32_e32 v1, v57, v1
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v3
; SI-NEXT:    v_add_i32_e32 v1, vcc, 0x300, v1
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v3, v59, v3
; SI-NEXT:    v_or_b32_e32 v1, v3, v1
; SI-NEXT:    v_add_i32_e32 v11, vcc, 0x3000000, v1
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v43
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v55
; SI-NEXT:    s_movk_i32 s6, 0x300
; SI-NEXT:    v_or_b32_e32 v1, v58, v1
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v3
; SI-NEXT:    v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v3, v56, v3
; SI-NEXT:    v_or_b32_e32 v1, v3, v1
; SI-NEXT:    v_add_i32_e32 v9, vcc, 0x3000000, v1
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v24
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v26
; SI-NEXT:    v_or_b32_e32 v1, v44, v1
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v3
; SI-NEXT:    v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v3, v46, v3
; SI-NEXT:    v_or_b32_e32 v1, v3, v1
; SI-NEXT:    v_add_i32_e32 v13, vcc, 0x3000000, v1
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v28
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v30
; SI-NEXT:    v_or_b32_e32 v1, v45, v1
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v3
; SI-NEXT:    v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v3, v47, v3
; SI-NEXT:    v_or_b32_e32 v1, v3, v1
; SI-NEXT:    v_add_i32_e32 v7, vcc, 0x3000000, v1
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v16
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v18
; SI-NEXT:    v_or_b32_e32 v1, v54, v1
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v3
; SI-NEXT:    v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v3, v41, v3
; SI-NEXT:    v_or_b32_e32 v1, v3, v1
; SI-NEXT:    v_add_i32_e32 v15, vcc, 0x3000000, v1
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v20
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v22
; SI-NEXT:    v_or_b32_e32 v1, v40, v1
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v3
; SI-NEXT:    v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v3, v53, v3
; SI-NEXT:    v_or_b32_e32 v1, v3, v1
; SI-NEXT:    v_add_i32_e32 v5, vcc, 0x3000000, v1
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v8
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v10
; SI-NEXT:    v_or_b32_e32 v1, v35, v1
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v3
; SI-NEXT:    v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v3, v51, v3
; SI-NEXT:    v_or_b32_e32 v1, v3, v1
; SI-NEXT:    v_add_i32_e32 v21, vcc, 0x3000000, v1
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v12
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v14
; SI-NEXT:    v_or_b32_e32 v1, v50, v1
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v3
; SI-NEXT:    v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v3, v36, v3
; SI-NEXT:    v_or_b32_e32 v1, v3, v1
; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT:    v_add_i32_e32 v3, vcc, 0x3000000, v1
; SI-NEXT:    v_and_b32_e32 v0, 0xff, v0
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v2
; SI-NEXT:    v_or_b32_e32 v0, v29, v0
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1
; SI-NEXT:    v_add_i32_e32 v0, vcc, s6, v0
; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_or_b32_e32 v1, v34, v1
; SI-NEXT:    v_or_b32_e32 v0, v1, v0
; SI-NEXT:    v_add_i32_e32 v27, vcc, 0x3000000, v0
; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v4
; SI-NEXT:    v_and_b32_e32 v0, 0xff, v0
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v6
; SI-NEXT:    v_or_b32_e32 v0, v33, v0
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1
; SI-NEXT:    v_add_i32_e32 v0, vcc, s6, v0
; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_or_b32_e32 v1, v32, v1
; SI-NEXT:    v_or_b32_e32 v0, v1, v0
; SI-NEXT:    v_add_i32_e32 v1, vcc, 0x3000000, v0
; SI-NEXT:    v_alignbit_b32 v17, v1, v27, 16
; SI-NEXT:    v_alignbit_b32 v19, v3, v21, 16
; SI-NEXT:    v_alignbit_b32 v23, v5, v15, 16
; SI-NEXT:    v_alignbit_b32 v25, v7, v13, 16
; SI-NEXT:    v_alignbit_b32 v31, v9, v11, 16
; SI-NEXT:    v_lshrrev_b32_e32 v37, 16, v1
; SI-NEXT:    v_lshrrev_b32_e32 v38, 16, v3
; SI-NEXT:    v_lshrrev_b32_e32 v39, 16, v5
; SI-NEXT:    v_lshrrev_b32_e32 v48, 16, v7
; SI-NEXT:    v_lshrrev_b32_e32 v49, 16, v9
; SI-NEXT:  .LBB62_4: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    buffer_load_dword v59, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v58, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v57, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v56, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v47, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v46, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v45, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v44, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v43, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v42, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v27
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v17
; SI-NEXT:    v_or_b32_e32 v0, v0, v2
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v37
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v21
; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v19
; SI-NEXT:    v_or_b32_e32 v2, v2, v4
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v38
; SI-NEXT:    v_or_b32_e32 v3, v3, v4
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v15
; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v23
; SI-NEXT:    v_or_b32_e32 v4, v4, v6
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v39
; SI-NEXT:    v_or_b32_e32 v5, v5, v6
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v13
; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v25
; SI-NEXT:    v_or_b32_e32 v6, v6, v8
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v48
; SI-NEXT:    v_or_b32_e32 v7, v7, v8
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v11
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v31
; SI-NEXT:    v_or_b32_e32 v8, v8, v10
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v49
; SI-NEXT:    v_or_b32_e32 v9, v9, v10
; SI-NEXT:    s_waitcnt vmcnt(0)
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v40i8_to_v20f16:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; VI-NEXT:    buffer_store_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; VI-NEXT:    buffer_store_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; VI-NEXT:    buffer_store_dword v43, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; VI-NEXT:    buffer_store_dword v44, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; VI-NEXT:    buffer_store_dword v45, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; VI-NEXT:    buffer_store_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; VI-NEXT:    buffer_store_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; VI-NEXT:    v_mov_b32_e32 v31, v0
; VI-NEXT:    buffer_load_ushort v55, off, s[0:3], s32
; VI-NEXT:    buffer_load_dword v0, off, s[0:3], s32 offset:36
; VI-NEXT:    buffer_load_ushort v46, off, s[0:3], s32 offset:32
; VI-NEXT:    buffer_load_ushort v47, off, s[0:3], s32 offset:28
; VI-NEXT:    buffer_load_ushort v43, off, s[0:3], s32 offset:24
; VI-NEXT:    buffer_load_ushort v45, off, s[0:3], s32 offset:20
; VI-NEXT:    buffer_load_ushort v42, off, s[0:3], s32 offset:16
; VI-NEXT:    buffer_load_ushort v44, off, s[0:3], s32 offset:12
; VI-NEXT:    buffer_load_ushort v40, off, s[0:3], s32 offset:8
; VI-NEXT:    buffer_load_ushort v41, off, s[0:3], s32 offset:4
; VI-NEXT:    v_mov_b32_e32 v54, v15
; VI-NEXT:    v_mov_b32_e32 v32, v14
; VI-NEXT:    v_mov_b32_e32 v50, v13
; VI-NEXT:    v_mov_b32_e32 v51, v12
; VI-NEXT:    v_mov_b32_e32 v52, v11
; VI-NEXT:    v_mov_b32_e32 v53, v10
; VI-NEXT:    v_mov_b32_e32 v38, v9
; VI-NEXT:    v_mov_b32_e32 v39, v8
; VI-NEXT:    v_mov_b32_e32 v48, v7
; VI-NEXT:    v_mov_b32_e32 v49, v6
; VI-NEXT:    v_mov_b32_e32 v34, v5
; VI-NEXT:    v_mov_b32_e32 v35, v4
; VI-NEXT:    v_mov_b32_e32 v36, v3
; VI-NEXT:    v_mov_b32_e32 v37, v2
; VI-NEXT:    v_mov_b32_e32 v33, v1
; VI-NEXT:    s_waitcnt vmcnt(8)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; VI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB62_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    s_mov_b32 s6, 0xc0c0004
; VI-NEXT:    v_perm_b32 v1, v37, v36, s6
; VI-NEXT:    v_perm_b32 v0, v31, v33, s6
; VI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT:    v_perm_b32 v2, v49, v48, s6
; VI-NEXT:    v_or_b32_e32 v0, v0, v1
; VI-NEXT:    v_perm_b32 v1, v35, v34, s6
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_perm_b32 v3, v53, v52, s6
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v39, v38, s6
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_perm_b32 v4, v32, v54, s6
; VI-NEXT:    v_or_b32_e32 v2, v2, v3
; VI-NEXT:    v_perm_b32 v3, v51, v50, s6
; VI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT:    v_perm_b32 v5, v18, v19, s6
; VI-NEXT:    v_or_b32_e32 v3, v3, v4
; VI-NEXT:    v_perm_b32 v4, v16, v17, s6
; VI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT:    v_perm_b32 v6, v22, v23, s6
; VI-NEXT:    v_or_b32_e32 v4, v4, v5
; VI-NEXT:    v_perm_b32 v5, v20, v21, s6
; VI-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT:    v_perm_b32 v7, v26, v27, s6
; VI-NEXT:    v_or_b32_e32 v5, v5, v6
; VI-NEXT:    v_perm_b32 v6, v24, v25, s6
; VI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT:    v_perm_b32 v8, v30, v55, s6
; VI-NEXT:    v_or_b32_e32 v6, v6, v7
; VI-NEXT:    v_perm_b32 v7, v28, v29, s6
; VI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT:    s_waitcnt vmcnt(2)
; VI-NEXT:    v_perm_b32 v9, v44, v42, s6
; VI-NEXT:    v_or_b32_e32 v7, v7, v8
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    v_perm_b32 v8, v41, v40, s6
; VI-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT:    v_perm_b32 v10, v47, v46, s6
; VI-NEXT:    v_or_b32_e32 v8, v8, v9
; VI-NEXT:    v_perm_b32 v9, v45, v43, s6
; VI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT:    v_or_b32_e32 v9, v9, v10
; VI-NEXT:    ; implicit-def: $vgpr31
; VI-NEXT:    ; implicit-def: $vgpr33
; VI-NEXT:    ; implicit-def: $vgpr37
; VI-NEXT:    ; implicit-def: $vgpr36
; VI-NEXT:    ; implicit-def: $vgpr35
; VI-NEXT:    ; implicit-def: $vgpr34
; VI-NEXT:    ; implicit-def: $vgpr49
; VI-NEXT:    ; implicit-def: $vgpr48
; VI-NEXT:    ; implicit-def: $vgpr39
; VI-NEXT:    ; implicit-def: $vgpr38
; VI-NEXT:    ; implicit-def: $vgpr53
; VI-NEXT:    ; implicit-def: $vgpr52
; VI-NEXT:    ; implicit-def: $vgpr51
; VI-NEXT:    ; implicit-def: $vgpr50
; VI-NEXT:    ; implicit-def: $vgpr32
; VI-NEXT:    ; implicit-def: $vgpr54
; VI-NEXT:    ; implicit-def: $vgpr16
; VI-NEXT:    ; implicit-def: $vgpr17
; VI-NEXT:    ; implicit-def: $vgpr18
; VI-NEXT:    ; implicit-def: $vgpr19
; VI-NEXT:    ; implicit-def: $vgpr20
; VI-NEXT:    ; implicit-def: $vgpr21
; VI-NEXT:    ; implicit-def: $vgpr22
; VI-NEXT:    ; implicit-def: $vgpr23
; VI-NEXT:    ; implicit-def: $vgpr24
; VI-NEXT:    ; implicit-def: $vgpr25
; VI-NEXT:    ; implicit-def: $vgpr26
; VI-NEXT:    ; implicit-def: $vgpr27
; VI-NEXT:    ; implicit-def: $vgpr28
; VI-NEXT:    ; implicit-def: $vgpr29
; VI-NEXT:    ; implicit-def: $vgpr30
; VI-NEXT:    ; implicit-def: $vgpr55
; VI-NEXT:    ; implicit-def: $vgpr41
; VI-NEXT:    ; implicit-def: $vgpr40
; VI-NEXT:    ; implicit-def: $vgpr44
; VI-NEXT:    ; implicit-def: $vgpr42
; VI-NEXT:    ; implicit-def: $vgpr45
; VI-NEXT:    ; implicit-def: $vgpr43
; VI-NEXT:    ; implicit-def: $vgpr47
; VI-NEXT:    ; implicit-def: $vgpr46
; VI-NEXT:  .LBB62_2: ; %Flow
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB62_4
; VI-NEXT:  ; %bb.3: ; %cmp.true
; VI-NEXT:    s_waitcnt vmcnt(6)
; VI-NEXT:    v_add_u16_e32 v0, 3, v47
; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v46
; VI-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_mov_b32_e32 v1, 0x300
; VI-NEXT:    v_add_u16_sdwa v9, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    s_waitcnt vmcnt(4)
; VI-NEXT:    v_add_u16_e32 v0, 3, v45
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v43
; VI-NEXT:    v_or_b32_sdwa v10, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    s_waitcnt vmcnt(2)
; VI-NEXT:    v_add_u16_e32 v0, 3, v44
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v42
; VI-NEXT:    v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_sdwa v8, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    v_add_u16_e32 v0, 3, v41
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v40
; VI-NEXT:    v_or_b32_sdwa v11, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v0, 3, v30
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v55
; VI-NEXT:    v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_sdwa v7, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_u16_e32 v0, 3, v28
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v29
; VI-NEXT:    v_or_b32_sdwa v12, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v0, 3, v26
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v27
; VI-NEXT:    v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_sdwa v6, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_u16_e32 v0, 3, v24
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v25
; VI-NEXT:    v_or_b32_sdwa v13, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v0, 3, v22
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v23
; VI-NEXT:    v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_sdwa v5, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_u16_e32 v0, 3, v20
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v21
; VI-NEXT:    v_or_b32_sdwa v14, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v0, 3, v18
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v19
; VI-NEXT:    v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_sdwa v4, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_u16_e32 v0, 3, v16
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v17
; VI-NEXT:    v_or_b32_sdwa v15, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v0, 3, v32
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v54
; VI-NEXT:    v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_sdwa v3, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_u16_e32 v0, 3, v51
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v50
; VI-NEXT:    v_or_b32_sdwa v16, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v0, 3, v53
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v52
; VI-NEXT:    v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_u16_e32 v0, 3, v39
; VI-NEXT:    v_lshlrev_b16_e32 v17, 8, v38
; VI-NEXT:    v_or_b32_sdwa v17, v17, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v0, 3, v49
; VI-NEXT:    v_lshlrev_b16_e32 v18, 8, v48
; VI-NEXT:    v_or_b32_sdwa v0, v18, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_sdwa v18, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_u16_e32 v0, 3, v35
; VI-NEXT:    v_lshlrev_b16_e32 v19, 8, v34
; VI-NEXT:    v_or_b32_sdwa v19, v19, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v0, 3, v37
; VI-NEXT:    v_lshlrev_b16_e32 v20, 8, v36
; VI-NEXT:    v_or_b32_sdwa v0, v20, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_u16_e32 v1, 3, v31
; VI-NEXT:    v_lshlrev_b16_e32 v20, 8, v33
; VI-NEXT:    v_or_b32_sdwa v1, v20, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v1, 0x300, v1
; VI-NEXT:    v_or_b32_e32 v0, v1, v0
; VI-NEXT:    v_add_u16_e32 v1, 0x300, v19
; VI-NEXT:    v_add_u16_e32 v17, 0x300, v17
; VI-NEXT:    v_add_u16_e32 v16, 0x300, v16
; VI-NEXT:    v_add_u16_e32 v15, 0x300, v15
; VI-NEXT:    v_add_u16_e32 v14, 0x300, v14
; VI-NEXT:    v_add_u16_e32 v13, 0x300, v13
; VI-NEXT:    v_add_u16_e32 v12, 0x300, v12
; VI-NEXT:    v_add_u16_e32 v11, 0x300, v11
; VI-NEXT:    v_add_u16_e32 v10, 0x300, v10
; VI-NEXT:    v_or_b32_e32 v1, v1, v18
; VI-NEXT:    v_or_b32_e32 v2, v17, v2
; VI-NEXT:    v_or_b32_e32 v3, v16, v3
; VI-NEXT:    v_or_b32_e32 v4, v15, v4
; VI-NEXT:    v_or_b32_e32 v5, v14, v5
; VI-NEXT:    v_or_b32_e32 v6, v13, v6
; VI-NEXT:    v_or_b32_e32 v7, v12, v7
; VI-NEXT:    v_or_b32_e32 v8, v11, v8
; VI-NEXT:    v_or_b32_e32 v9, v10, v9
; VI-NEXT:  .LBB62_4: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    buffer_load_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; VI-NEXT:    buffer_load_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; VI-NEXT:    buffer_load_dword v45, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; VI-NEXT:    buffer_load_dword v44, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; VI-NEXT:    buffer_load_dword v43, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; VI-NEXT:    buffer_load_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; VI-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; VI-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v40i8_to_v20f16:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; GFX9-NEXT:    buffer_store_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; GFX9-NEXT:    buffer_store_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT:    buffer_store_dword v43, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT:    buffer_store_dword v44, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; GFX9-NEXT:    buffer_store_dword v45, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; GFX9-NEXT:    buffer_store_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; GFX9-NEXT:    buffer_store_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; GFX9-NEXT:    v_mov_b32_e32 v36, v3
; GFX9-NEXT:    v_mov_b32_e32 v34, v2
; GFX9-NEXT:    v_mov_b32_e32 v31, v1
; GFX9-NEXT:    v_mov_b32_e32 v38, v0
; GFX9-NEXT:    buffer_load_ushort v55, off, s[0:3], s32
; GFX9-NEXT:    buffer_load_dword v0, off, s[0:3], s32 offset:36
; GFX9-NEXT:    buffer_load_ushort v1, off, s[0:3], s32 offset:32
; GFX9-NEXT:    buffer_load_ushort v41, off, s[0:3], s32 offset:28
; GFX9-NEXT:    buffer_load_ushort v43, off, s[0:3], s32 offset:24
; GFX9-NEXT:    buffer_load_ushort v44, off, s[0:3], s32 offset:20
; GFX9-NEXT:    buffer_load_ushort v2, off, s[0:3], s32 offset:8
; GFX9-NEXT:    buffer_load_ushort v3, off, s[0:3], s32 offset:16
; GFX9-NEXT:    buffer_load_ushort v40, off, s[0:3], s32 offset:12
; GFX9-NEXT:    buffer_load_ushort v42, off, s[0:3], s32 offset:4
; GFX9-NEXT:    v_mov_b32_e32 v39, v15
; GFX9-NEXT:    v_mov_b32_e32 v53, v14
; GFX9-NEXT:    v_mov_b32_e32 v52, v13
; GFX9-NEXT:    v_mov_b32_e32 v32, v12
; GFX9-NEXT:    v_mov_b32_e32 v35, v11
; GFX9-NEXT:    v_mov_b32_e32 v50, v10
; GFX9-NEXT:    v_mov_b32_e32 v49, v9
; GFX9-NEXT:    v_mov_b32_e32 v54, v8
; GFX9-NEXT:    v_mov_b32_e32 v33, v7
; GFX9-NEXT:    v_mov_b32_e32 v48, v6
; GFX9-NEXT:    v_mov_b32_e32 v37, v5
; GFX9-NEXT:    v_mov_b32_e32 v51, v4
; GFX9-NEXT:    s_waitcnt vmcnt(8)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-NEXT:    s_waitcnt vmcnt(7)
; GFX9-NEXT:    v_lshlrev_b16_e32 v47, 8, v1
; GFX9-NEXT:    s_waitcnt vmcnt(3)
; GFX9-NEXT:    v_lshlrev_b16_e32 v46, 8, v2
; GFX9-NEXT:    s_waitcnt vmcnt(2)
; GFX9-NEXT:    v_lshlrev_b16_e32 v45, 8, v3
; GFX9-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB62_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    s_mov_b32 s6, 0xc0c0004
; GFX9-NEXT:    v_perm_b32 v0, v38, v31, s6
; GFX9-NEXT:    v_perm_b32 v1, v34, v36, s6
; GFX9-NEXT:    s_mov_b32 s7, 0x5040100
; GFX9-NEXT:    v_perm_b32 v0, v1, v0, s7
; GFX9-NEXT:    v_perm_b32 v1, v51, v37, s6
; GFX9-NEXT:    v_perm_b32 v2, v48, v33, s6
; GFX9-NEXT:    v_perm_b32 v1, v2, v1, s7
; GFX9-NEXT:    v_perm_b32 v2, v54, v49, s6
; GFX9-NEXT:    v_perm_b32 v3, v50, v35, s6
; GFX9-NEXT:    v_perm_b32 v2, v3, v2, s7
; GFX9-NEXT:    v_perm_b32 v3, v32, v52, s6
; GFX9-NEXT:    v_perm_b32 v4, v53, v39, s6
; GFX9-NEXT:    v_perm_b32 v3, v4, v3, s7
; GFX9-NEXT:    v_perm_b32 v4, v16, v17, s6
; GFX9-NEXT:    v_perm_b32 v5, v18, v19, s6
; GFX9-NEXT:    v_perm_b32 v4, v5, v4, s7
; GFX9-NEXT:    v_perm_b32 v5, v20, v21, s6
; GFX9-NEXT:    v_perm_b32 v6, v22, v23, s6
; GFX9-NEXT:    v_perm_b32 v5, v6, v5, s7
; GFX9-NEXT:    v_perm_b32 v6, v24, v25, s6
; GFX9-NEXT:    v_perm_b32 v7, v26, v27, s6
; GFX9-NEXT:    v_perm_b32 v6, v7, v6, s7
; GFX9-NEXT:    v_perm_b32 v7, v28, v29, s6
; GFX9-NEXT:    v_perm_b32 v8, v30, v55, s6
; GFX9-NEXT:    v_perm_b32 v7, v8, v7, s7
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    v_or_b32_sdwa v8, v42, v46 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v9, v40, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT:    v_perm_b32 v8, v9, v8, s7
; GFX9-NEXT:    v_or_b32_sdwa v9, v41, v47 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT:    v_perm_b32 v10, v44, v43, s6
; GFX9-NEXT:    v_perm_b32 v9, v9, v10, s7
; GFX9-NEXT:    ; implicit-def: $vgpr38
; GFX9-NEXT:    ; implicit-def: $vgpr31
; GFX9-NEXT:    ; implicit-def: $vgpr34
; GFX9-NEXT:    ; implicit-def: $vgpr36
; GFX9-NEXT:    ; implicit-def: $vgpr51
; GFX9-NEXT:    ; implicit-def: $vgpr37
; GFX9-NEXT:    ; implicit-def: $vgpr48
; GFX9-NEXT:    ; implicit-def: $vgpr33
; GFX9-NEXT:    ; implicit-def: $vgpr54
; GFX9-NEXT:    ; implicit-def: $vgpr49
; GFX9-NEXT:    ; implicit-def: $vgpr50
; GFX9-NEXT:    ; implicit-def: $vgpr35
; GFX9-NEXT:    ; implicit-def: $vgpr32
; GFX9-NEXT:    ; implicit-def: $vgpr52
; GFX9-NEXT:    ; implicit-def: $vgpr53
; GFX9-NEXT:    ; implicit-def: $vgpr39
; GFX9-NEXT:    ; implicit-def: $vgpr16
; GFX9-NEXT:    ; implicit-def: $vgpr17
; GFX9-NEXT:    ; implicit-def: $vgpr18
; GFX9-NEXT:    ; implicit-def: $vgpr19
; GFX9-NEXT:    ; implicit-def: $vgpr20
; GFX9-NEXT:    ; implicit-def: $vgpr21
; GFX9-NEXT:    ; implicit-def: $vgpr22
; GFX9-NEXT:    ; implicit-def: $vgpr23
; GFX9-NEXT:    ; implicit-def: $vgpr24
; GFX9-NEXT:    ; implicit-def: $vgpr25
; GFX9-NEXT:    ; implicit-def: $vgpr26
; GFX9-NEXT:    ; implicit-def: $vgpr27
; GFX9-NEXT:    ; implicit-def: $vgpr28
; GFX9-NEXT:    ; implicit-def: $vgpr29
; GFX9-NEXT:    ; implicit-def: $vgpr30
; GFX9-NEXT:    ; implicit-def: $vgpr55
; GFX9-NEXT:    ; implicit-def: $vgpr42
; GFX9-NEXT:    ; implicit-def: $vgpr40
; GFX9-NEXT:    ; implicit-def: $vgpr44
; GFX9-NEXT:    ; implicit-def: $vgpr43
; GFX9-NEXT:    ; implicit-def: $vgpr41
; GFX9-NEXT:    ; implicit-def: $vgpr46
; GFX9-NEXT:    ; implicit-def: $vgpr45
; GFX9-NEXT:    ; implicit-def: $vgpr47
; GFX9-NEXT:  .LBB62_2: ; %Flow
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB62_4
; GFX9-NEXT:  ; %bb.3: ; %cmp.true
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v44
; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v43
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v9, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v41
; GFX9-NEXT:    v_or_b32_sdwa v0, v47, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v10, 0x300, v0
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v42
; GFX9-NEXT:    v_or_b32_sdwa v0, v46, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v8, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v40
; GFX9-NEXT:    v_or_b32_sdwa v0, v45, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v11, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v28
; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v29
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v7, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v30
; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v55
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v12, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v24
; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v25
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v6, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v26
; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v27
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v13, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v20
; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v21
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v5, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v22
; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v23
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v14, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v16
; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v17
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v4, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v18
; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v19
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v15, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v32
; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v52
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v3, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v53
; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v39
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v16, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v54
; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v49
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v2, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v50
; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v35
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v17, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v51
; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v37
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v1, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v48
; GFX9-NEXT:    v_lshlrev_b16_e32 v18, 8, v33
; GFX9-NEXT:    v_or_b32_sdwa v0, v18, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v18, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v38
; GFX9-NEXT:    v_lshlrev_b16_e32 v19, 8, v31
; GFX9-NEXT:    v_or_b32_sdwa v0, v19, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v19, 3, v34
; GFX9-NEXT:    v_lshlrev_b16_e32 v20, 8, v36
; GFX9-NEXT:    v_or_b32_sdwa v19, v20, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v0, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v19, 0x300, v19
; GFX9-NEXT:    s_mov_b32 s6, 0x5040100
; GFX9-NEXT:    v_perm_b32 v0, v19, v0, s6
; GFX9-NEXT:    v_perm_b32 v1, v18, v1, s6
; GFX9-NEXT:    v_perm_b32 v2, v17, v2, s6
; GFX9-NEXT:    v_perm_b32 v3, v16, v3, s6
; GFX9-NEXT:    v_perm_b32 v4, v15, v4, s6
; GFX9-NEXT:    v_perm_b32 v5, v14, v5, s6
; GFX9-NEXT:    v_perm_b32 v6, v13, v6, s6
; GFX9-NEXT:    v_perm_b32 v7, v12, v7, s6
; GFX9-NEXT:    v_perm_b32 v8, v11, v8, s6
; GFX9-NEXT:    v_perm_b32 v9, v10, v9, s6
; GFX9-NEXT:  .LBB62_4: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    buffer_load_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; GFX9-NEXT:    buffer_load_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; GFX9-NEXT:    buffer_load_dword v45, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; GFX9-NEXT:    buffer_load_dword v44, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; GFX9-NEXT:    buffer_load_dword v43, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; GFX9-NEXT:    buffer_load_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; GFX9-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v40i8_to_v20f16:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    s_clause 0x9
; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v32, off, s32 offset:32
; GFX11-TRUE16-NEXT:    scratch_load_b32 v70, off, s32 offset:36
; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v33, off, s32 offset:8
; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v34, off, s32 offset:16
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v32, off, s32 offset:28
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v34, off, s32 offset:24
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v35, off, s32 offset:20
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v31, off, s32 offset:12
; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v31, off, s32 offset:4
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v33, off, s32
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v37.l, v22.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.l, v19.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v51.l, v18.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v18.l, v17.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.l, v16.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v39.l, v15.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v53.l, v14.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v38.l, v13.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v65.l, v12.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v50.l, v11.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v64.l, v10.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v22.l, v9.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v49.l, v8.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v52.l, v7.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v66.l, v6.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v54.l, v5.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v68.l, v4.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v67.l, v3.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v69.l, v2.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v48.l, v1.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v0.l
; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(5)
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.l, 8, v32.h
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.l, 8, v33.h
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v34.h
; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v70
; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB62_3
; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB62_4
; GFX11-TRUE16-NEXT:  .LBB62_2: ; %end
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT:  .LBB62_3: ; %cmp.false
; GFX11-TRUE16-NEXT:    v_perm_b32 v2, v69, v67, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v4, v64, v50, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, v51, v36, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v8, v26, v27, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v0, v55, v48, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v2.l
; GFX11-TRUE16-NEXT:    v_perm_b32 v2, v49, v22, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v4.l
; GFX11-TRUE16-NEXT:    v_perm_b32 v4, v19, v18, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v6.l
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, v24, v25, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v8.l
; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, v32.l, 0xff
; GFX11-TRUE16-NEXT:    v_perm_b32 v3, v66, v52, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v5, v53, v39, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, v37, v23, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_and_b16 v8.h, v31.h, 0xff
; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, v31.l, 0xff
; GFX11-TRUE16-NEXT:    v_perm_b32 v11, v30, v33, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v8.l, v17.l
; GFX11-TRUE16-NEXT:    v_perm_b32 v1, v68, v54, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v3.l
; GFX11-TRUE16-NEXT:    v_perm_b32 v3, v65, v38, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v5.l
; GFX11-TRUE16-NEXT:    v_perm_b32 v5, v20, v21, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v7.l
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, v28, v29, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.h, v16.l
; GFX11-TRUE16-NEXT:    v_or_b16 v8.h, v9.l, v16.h
; GFX11-TRUE16-NEXT:    v_perm_b32 v9, v35, v34, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.h, v11.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.h, v10.l
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr69_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr67_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr68_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr66_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr65_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_hi16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_hi16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB62_2
; GFX11-TRUE16-NEXT:  .LBB62_4: ; %cmp.true
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v35.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v32.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v31.h, 3
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v34.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v31.l, 3
; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, 0xff
; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, v0.h, 0xff
; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, v1.h, 0xff
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v26.l, 3
; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, v2.l, 0xff
; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v17.l, v0.h
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v28.l, 3
; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v16.l, v1.h
; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v16.h, v2.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, v0.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.h, v0.h, 0x300
; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, v1.l, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 8, v29.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v30.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, v1.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v24.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.h, v2.l, 0x300
; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.h, v0.l
; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, v1.l, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v33.l
; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, v1.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 8, v25.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, v0.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v20.l, 3
; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v1.l, v0.h
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v37.l, 3
; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v2.l, v1.h
; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, v2.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 8, v27.l
; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v21.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, v0.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, v1.l, 0x300
; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v2.l, v1.h
; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, v3.l, 0xff
; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v2.h, v0.l
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 8, v23.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v19.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, v0.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v51.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, v0.l, 0x300
; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v1.h, v1.l
; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, v2.l, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 8, v18.l
; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, v0.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 8, v36.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, v0.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v65.l, 3
; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.h, v1.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v53.l, 3
; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v2.l, v0.h
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v49.l, 3
; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v38.l
; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, v1.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.l, 8, v39.l
; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, v2.l, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v22.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, v1.l, 0x300
; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v2.h, v0.l
; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v3.l, v1.h
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.h, v0.h, 0x300
; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v3.h, v2.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v64.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v0.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v68.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v55.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v0.h, 0x300
; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, v1.h, 0xff
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v66.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v10.h, v69.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, v1.l, 0x300
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v50.l
; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.l, 8, v54.l
; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, v1.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.l, 8, v52.l
; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, v2.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v48.l
; GFX11-TRUE16-NEXT:    v_and_b16 v10.h, v10.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.l, 8, v67.l
; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v1.l, v0.h
; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v10.l, v0.l
; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v11.l, v1.h
; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v11.h, v2.h
; GFX11-TRUE16-NEXT:    v_or_b16 v10.h, v12.l, v10.h
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v0.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v0.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v1.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v10.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v10.h, 0x300
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v40i8_to_v20f16:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v36, v7 :: v_dual_mov_b32 v35, v2
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v52, v4 :: v_dual_mov_b32 v33, v3
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v48, v1 :: v_dual_mov_b32 v37, v0
; GFX11-FAKE16-NEXT:    s_clause 0x9
; GFX11-FAKE16-NEXT:    scratch_load_u16 v0, off, s32 offset:32
; GFX11-FAKE16-NEXT:    scratch_load_b32 v1, off, s32 offset:36
; GFX11-FAKE16-NEXT:    scratch_load_u16 v2, off, s32 offset:8
; GFX11-FAKE16-NEXT:    scratch_load_u16 v3, off, s32 offset:16
; GFX11-FAKE16-NEXT:    scratch_load_u16 v70, off, s32 offset:28
; GFX11-FAKE16-NEXT:    scratch_load_u16 v68, off, s32 offset:24
; GFX11-FAKE16-NEXT:    scratch_load_u16 v69, off, s32 offset:20
; GFX11-FAKE16-NEXT:    scratch_load_u16 v67, off, s32 offset:12
; GFX11-FAKE16-NEXT:    scratch_load_u16 v71, off, s32 offset:4
; GFX11-FAKE16-NEXT:    scratch_load_u16 v55, off, s32
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v50, v15 :: v_dual_mov_b32 v49, v10
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v54, v14 :: v_dual_mov_b32 v51, v13
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v32, v12 :: v_dual_mov_b32 v53, v9
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v38, v11 :: v_dual_mov_b32 v31, v8
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v34, v6 :: v_dual_mov_b32 v39, v5
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(9)
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v66, 8, v0
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(8)
; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v1
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(7)
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v65, 8, v2
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(6)
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v64, 8, v3
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB62_3
; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB62_4
; GFX11-FAKE16-NEXT:  .LBB62_2: ; %end
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT:  .LBB62_3: ; %cmp.false
; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v37, v48, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v35, v33, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v52, v39, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v34, v36, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v31, v53, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v49, v38, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v16, v17, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v18, v19, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v32, v51, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v54, v50, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v3, v2, 0x5040100
; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v5, v4, 0x5040100
; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v9, v8, 0x5040100
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v71
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v67
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v70
; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v7, v6, 0x5040100
; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v20, v21, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v22, v23, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v24, v25, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v26, v27, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v28, v29, 0xc0c0004
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v30, v55, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v65
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v64
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v66
; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v69, v68, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v6, v5, 0x5040100
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v8, v7, 0x5040100
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v13, v12, 0x5040100
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v10, v9, 0x5040100
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v11, v14, 0x5040100
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr55
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr71
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr67
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr69
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr68
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr70
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr66
; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB62_2
; GFX11-FAKE16-NEXT:  .LBB62_4: ; %cmp.true
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(3)
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v69, 3
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v68
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v71, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v70, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v67, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v28, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v6, 8, v29
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v1, v0
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v4
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v65, v3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v66, v2
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v5
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v0, 0x300
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v30, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v3, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v64, v1
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v55
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v2, 0x300
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v6, v4
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v24, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, v1, 0x300
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v26, 3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v3, v0
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v2, 0x300
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v4
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v25
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v4, 8, v27
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, v0, 0x300
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v20, 3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v3, v2
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v22, 3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v4, v1
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v16, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v21
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v6, 8, v23
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v17
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v5, v0
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, v2, 0x300
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, v1, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v6, v3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v13, v4
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v18, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v0, 0x300
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v32, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v1, 0x300
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v2, 0x300
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v31, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v51
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, v54, 3
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v19
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v53
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v3, v0
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v13
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v50
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v16, v1
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, v49, 3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v17, v2
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, v0, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v13, v3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v52, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v16
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, v34, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, v37, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v19, v35, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v20, 8, v39
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v16
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v18
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v48
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v19
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v33
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v36
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v38
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v20, v3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v21, v18
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v22, v19
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v23, v16
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v24, v13
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v2, 0x300
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v3, 0x300
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, v18, 0x300
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v19, v19, 0x300
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, v16, 0x300
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, v13, 0x300
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v20, v0, 0x300
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v21, v1, 0x300
; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v19, v18, 0x5040100
; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v16, v3, 0x5040100
; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v13, v2, 0x5040100
; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v20, v17, 0x5040100
; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v21, v4, 0x5040100
; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v6, v5, 0x5040100
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v15, v14, 0x5040100
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v12, v7, 0x5040100
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v11, v8, 0x5040100
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v10, v9, 0x5040100
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <40 x i8> %a, splat (i8 3)
  %a2 = bitcast <40 x i8> %a1 to <20 x half>
  br label %end

cmp.false:
  %a3 = bitcast <40 x i8> %a to <20 x half>
  br label %end

end:
  %phi = phi <20 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <20 x half> %phi
}

define inreg <20 x half> @bitcast_v40i8_to_v20f16_scalar(<40 x i8> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v40i8_to_v20f16_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_readfirstlane_b32 s10, v26
; SI-NEXT:    v_readfirstlane_b32 s5, v25
; SI-NEXT:    v_readfirstlane_b32 s56, v24
; SI-NEXT:    v_readfirstlane_b32 s59, v23
; SI-NEXT:    v_readfirstlane_b32 s60, v22
; SI-NEXT:    v_readfirstlane_b32 s4, v21
; SI-NEXT:    v_readfirstlane_b32 s62, v20
; SI-NEXT:    v_readfirstlane_b32 s63, v19
; SI-NEXT:    v_readfirstlane_b32 s72, v18
; SI-NEXT:    v_readfirstlane_b32 s7, v17
; SI-NEXT:    v_readfirstlane_b32 s45, v16
; SI-NEXT:    v_readfirstlane_b32 s57, v15
; SI-NEXT:    v_readfirstlane_b32 s58, v14
; SI-NEXT:    v_readfirstlane_b32 s6, v13
; SI-NEXT:    v_readfirstlane_b32 s15, v12
; SI-NEXT:    v_readfirstlane_b32 s44, v11
; SI-NEXT:    v_readfirstlane_b32 s61, v10
; SI-NEXT:    v_readfirstlane_b32 s9, v9
; SI-NEXT:    v_readfirstlane_b32 s43, v8
; SI-NEXT:    v_readfirstlane_b32 s46, v7
; SI-NEXT:    v_readfirstlane_b32 s47, v6
; SI-NEXT:    v_readfirstlane_b32 s8, v5
; SI-NEXT:    v_readfirstlane_b32 s14, v4
; SI-NEXT:    s_cmp_lg_u32 s10, 0
; SI-NEXT:    v_readfirstlane_b32 s41, v3
; SI-NEXT:    v_readfirstlane_b32 s42, v2
; SI-NEXT:    v_readfirstlane_b32 s11, v1
; SI-NEXT:    v_readfirstlane_b32 s13, v0
; SI-NEXT:    s_cbranch_scc0 .LBB63_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    s_and_b32 s10, s16, 0xff
; SI-NEXT:    s_lshl_b32 s12, s17, 8
; SI-NEXT:    s_or_b32 s10, s10, s12
; SI-NEXT:    s_and_b32 s12, s18, 0xff
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_lshl_b32 s16, s19, 24
; SI-NEXT:    s_and_b32 s10, s10, 0xffff
; SI-NEXT:    s_or_b32 s40, s16, s12
; SI-NEXT:    s_or_b32 s12, s10, s40
; SI-NEXT:    s_and_b32 s10, s24, 0xff
; SI-NEXT:    s_lshl_b32 s16, s25, 8
; SI-NEXT:    s_or_b32 s10, s10, s16
; SI-NEXT:    s_and_b32 s16, s26, 0xff
; SI-NEXT:    s_lshl_b32 s16, s16, 16
; SI-NEXT:    s_lshl_b32 s17, s27, 24
; SI-NEXT:    s_or_b32 s24, s17, s16
; SI-NEXT:    s_and_b32 s16, s42, 0xff
; SI-NEXT:    s_lshl_b32 s17, s41, 8
; SI-NEXT:    s_and_b32 s14, s14, 0xff
; SI-NEXT:    s_or_b32 s16, s16, s17
; SI-NEXT:    s_lshl_b32 s14, s14, 16
; SI-NEXT:    s_lshl_b32 s8, s8, 24
; SI-NEXT:    s_and_b32 s16, s16, 0xffff
; SI-NEXT:    s_or_b32 s26, s8, s14
; SI-NEXT:    s_or_b32 s8, s16, s26
; SI-NEXT:    s_and_b32 s14, s61, 0xff
; SI-NEXT:    s_lshl_b32 s16, s44, 8
; SI-NEXT:    s_and_b32 s15, s15, 0xff
; SI-NEXT:    s_or_b32 s14, s14, s16
; SI-NEXT:    s_lshl_b32 s15, s15, 16
; SI-NEXT:    s_lshl_b32 s6, s6, 24
; SI-NEXT:    s_and_b32 s14, s14, 0xffff
; SI-NEXT:    s_or_b32 s42, s6, s15
; SI-NEXT:    s_or_b32 s6, s14, s42
; SI-NEXT:    s_and_b32 s14, s72, 0xff
; SI-NEXT:    s_lshl_b32 s15, s63, 8
; SI-NEXT:    s_or_b32 s14, s14, s15
; SI-NEXT:    s_and_b32 s15, s62, 0xff
; SI-NEXT:    s_lshl_b32 s15, s15, 16
; SI-NEXT:    s_lshl_b32 s4, s4, 24
; SI-NEXT:    s_and_b32 s14, s14, 0xffff
; SI-NEXT:    s_or_b32 s44, s4, s15
; SI-NEXT:    s_or_b32 s4, s14, s44
; SI-NEXT:    s_and_b32 s14, s20, 0xff
; SI-NEXT:    s_lshl_b32 s15, s21, 8
; SI-NEXT:    s_or_b32 s14, s14, s15
; SI-NEXT:    s_and_b32 s15, s22, 0xff
; SI-NEXT:    s_lshl_b32 s15, s15, 16
; SI-NEXT:    s_lshl_b32 s16, s23, 24
; SI-NEXT:    s_and_b32 s14, s14, 0xffff
; SI-NEXT:    s_or_b32 s61, s16, s15
; SI-NEXT:    s_or_b32 s41, s14, s61
; SI-NEXT:    s_lshr_b64 s[14:15], s[40:41], 16
; SI-NEXT:    s_and_b32 s15, s28, 0xff
; SI-NEXT:    s_lshl_b32 s16, s29, 8
; SI-NEXT:    s_and_b32 s13, s13, 0xff
; SI-NEXT:    s_or_b32 s15, s15, s16
; SI-NEXT:    s_lshl_b32 s13, s13, 16
; SI-NEXT:    s_lshl_b32 s11, s11, 24
; SI-NEXT:    s_and_b32 s15, s15, 0xffff
; SI-NEXT:    s_or_b32 s11, s11, s13
; SI-NEXT:    s_or_b32 s25, s15, s11
; SI-NEXT:    s_and_b32 s13, s47, 0xff
; SI-NEXT:    s_lshl_b32 s15, s46, 8
; SI-NEXT:    s_or_b32 s13, s13, s15
; SI-NEXT:    s_and_b32 s15, s43, 0xff
; SI-NEXT:    s_lshl_b32 s15, s15, 16
; SI-NEXT:    s_lshl_b32 s9, s9, 24
; SI-NEXT:    s_and_b32 s13, s13, 0xffff
; SI-NEXT:    s_or_b32 s9, s9, s15
; SI-NEXT:    s_or_b32 s27, s13, s9
; SI-NEXT:    s_and_b32 s13, s58, 0xff
; SI-NEXT:    s_lshl_b32 s15, s57, 8
; SI-NEXT:    s_or_b32 s13, s13, s15
; SI-NEXT:    s_and_b32 s15, s45, 0xff
; SI-NEXT:    s_lshl_b32 s15, s15, 16
; SI-NEXT:    s_lshl_b32 s7, s7, 24
; SI-NEXT:    s_and_b32 s13, s13, 0xffff
; SI-NEXT:    s_or_b32 s7, s7, s15
; SI-NEXT:    s_or_b32 s43, s13, s7
; SI-NEXT:    s_and_b32 s13, s60, 0xff
; SI-NEXT:    s_lshl_b32 s15, s59, 8
; SI-NEXT:    s_or_b32 s13, s13, s15
; SI-NEXT:    s_and_b32 s15, s56, 0xff
; SI-NEXT:    s_lshl_b32 s15, s15, 16
; SI-NEXT:    s_lshl_b32 s5, s5, 24
; SI-NEXT:    s_and_b32 s13, s13, 0xffff
; SI-NEXT:    s_or_b32 s5, s5, s15
; SI-NEXT:    s_or_b32 s45, s13, s5
; SI-NEXT:    s_and_b32 s10, s10, 0xffff
; SI-NEXT:    s_lshr_b64 s[16:17], s[24:25], 16
; SI-NEXT:    s_lshr_b64 s[18:19], s[26:27], 16
; SI-NEXT:    s_lshr_b64 s[20:21], s[42:43], 16
; SI-NEXT:    s_lshr_b64 s[22:23], s[44:45], 16
; SI-NEXT:    s_or_b32 s10, s10, s24
; SI-NEXT:    s_lshr_b32 s23, s61, 16
; SI-NEXT:    s_lshr_b32 s21, s11, 16
; SI-NEXT:    s_lshr_b32 s19, s9, 16
; SI-NEXT:    s_lshr_b32 s17, s7, 16
; SI-NEXT:    s_lshr_b32 s15, s5, 16
; SI-NEXT:    s_mov_b32 s13, s41
; SI-NEXT:    s_mov_b32 s11, s25
; SI-NEXT:    s_mov_b32 s9, s27
; SI-NEXT:    s_mov_b32 s7, s43
; SI-NEXT:    s_mov_b32 s5, s45
; SI-NEXT:    s_branch .LBB63_3
; SI-NEXT:  .LBB63_2: ; %cmp.true
; SI-NEXT:    s_add_i32 s72, s72, 3
; SI-NEXT:    s_and_b32 s10, s72, 0xff
; SI-NEXT:    s_lshl_b32 s12, s63, 8
; SI-NEXT:    s_add_i32 s62, s62, 3
; SI-NEXT:    s_or_b32 s10, s12, s10
; SI-NEXT:    s_and_b32 s12, s62, 0xff
; SI-NEXT:    s_addk_i32 s10, 0x300
; SI-NEXT:    s_lshl_b32 s4, s4, 24
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_and_b32 s10, s10, 0xffff
; SI-NEXT:    s_or_b32 s4, s4, s12
; SI-NEXT:    s_add_i32 s60, s60, 3
; SI-NEXT:    s_or_b32 s4, s4, s10
; SI-NEXT:    s_and_b32 s10, s60, 0xff
; SI-NEXT:    s_lshl_b32 s12, s59, 8
; SI-NEXT:    s_add_i32 s56, s56, 3
; SI-NEXT:    s_or_b32 s10, s12, s10
; SI-NEXT:    s_and_b32 s12, s56, 0xff
; SI-NEXT:    s_addk_i32 s10, 0x300
; SI-NEXT:    s_lshl_b32 s5, s5, 24
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_and_b32 s10, s10, 0xffff
; SI-NEXT:    s_or_b32 s5, s5, s12
; SI-NEXT:    s_add_i32 s61, s61, 3
; SI-NEXT:    s_or_b32 s5, s5, s10
; SI-NEXT:    s_and_b32 s10, s61, 0xff
; SI-NEXT:    s_lshl_b32 s12, s44, 8
; SI-NEXT:    s_add_i32 s15, s15, 3
; SI-NEXT:    s_or_b32 s10, s12, s10
; SI-NEXT:    s_and_b32 s12, s15, 0xff
; SI-NEXT:    s_addk_i32 s10, 0x300
; SI-NEXT:    s_lshl_b32 s6, s6, 24
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_and_b32 s10, s10, 0xffff
; SI-NEXT:    s_or_b32 s6, s6, s12
; SI-NEXT:    s_add_i32 s58, s58, 3
; SI-NEXT:    s_or_b32 s6, s6, s10
; SI-NEXT:    s_and_b32 s10, s58, 0xff
; SI-NEXT:    s_lshl_b32 s12, s57, 8
; SI-NEXT:    s_add_i32 s45, s45, 3
; SI-NEXT:    s_or_b32 s10, s12, s10
; SI-NEXT:    s_and_b32 s12, s45, 0xff
; SI-NEXT:    s_addk_i32 s10, 0x300
; SI-NEXT:    s_lshl_b32 s7, s7, 24
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_and_b32 s10, s10, 0xffff
; SI-NEXT:    s_or_b32 s7, s7, s12
; SI-NEXT:    s_add_i32 s42, s42, 3
; SI-NEXT:    s_or_b32 s7, s7, s10
; SI-NEXT:    s_and_b32 s10, s42, 0xff
; SI-NEXT:    s_lshl_b32 s12, s41, 8
; SI-NEXT:    s_add_i32 s14, s14, 3
; SI-NEXT:    s_or_b32 s10, s12, s10
; SI-NEXT:    s_and_b32 s12, s14, 0xff
; SI-NEXT:    s_addk_i32 s10, 0x300
; SI-NEXT:    s_lshl_b32 s8, s8, 24
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_and_b32 s10, s10, 0xffff
; SI-NEXT:    s_or_b32 s8, s8, s12
; SI-NEXT:    s_add_i32 s47, s47, 3
; SI-NEXT:    s_or_b32 s8, s8, s10
; SI-NEXT:    s_and_b32 s10, s47, 0xff
; SI-NEXT:    s_lshl_b32 s12, s46, 8
; SI-NEXT:    s_add_i32 s43, s43, 3
; SI-NEXT:    s_or_b32 s10, s12, s10
; SI-NEXT:    s_and_b32 s12, s43, 0xff
; SI-NEXT:    s_addk_i32 s10, 0x300
; SI-NEXT:    s_lshl_b32 s9, s9, 24
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_and_b32 s10, s10, 0xffff
; SI-NEXT:    s_or_b32 s9, s9, s12
; SI-NEXT:    s_add_i32 s24, s24, 3
; SI-NEXT:    s_or_b32 s9, s9, s10
; SI-NEXT:    s_and_b32 s10, s24, 0xff
; SI-NEXT:    s_lshl_b32 s12, s25, 8
; SI-NEXT:    s_add_i32 s26, s26, 3
; SI-NEXT:    s_or_b32 s10, s12, s10
; SI-NEXT:    s_and_b32 s14, s26, 0xff
; SI-NEXT:    s_addk_i32 s10, 0x300
; SI-NEXT:    s_lshl_b32 s12, s27, 24
; SI-NEXT:    s_lshl_b32 s14, s14, 16
; SI-NEXT:    s_and_b32 s10, s10, 0xffff
; SI-NEXT:    s_or_b32 s12, s12, s14
; SI-NEXT:    s_add_i32 s28, s28, 3
; SI-NEXT:    s_or_b32 s10, s12, s10
; SI-NEXT:    s_and_b32 s12, s28, 0xff
; SI-NEXT:    s_lshl_b32 s14, s29, 8
; SI-NEXT:    s_add_i32 s13, s13, 3
; SI-NEXT:    s_or_b32 s12, s14, s12
; SI-NEXT:    s_and_b32 s13, s13, 0xff
; SI-NEXT:    s_addk_i32 s12, 0x300
; SI-NEXT:    s_lshl_b32 s11, s11, 24
; SI-NEXT:    s_lshl_b32 s13, s13, 16
; SI-NEXT:    s_and_b32 s12, s12, 0xffff
; SI-NEXT:    s_or_b32 s11, s11, s13
; SI-NEXT:    s_add_i32 s16, s16, 3
; SI-NEXT:    s_or_b32 s11, s11, s12
; SI-NEXT:    s_and_b32 s12, s16, 0xff
; SI-NEXT:    s_lshl_b32 s13, s17, 8
; SI-NEXT:    s_add_i32 s18, s18, 3
; SI-NEXT:    s_or_b32 s12, s13, s12
; SI-NEXT:    s_and_b32 s14, s18, 0xff
; SI-NEXT:    s_addk_i32 s12, 0x300
; SI-NEXT:    s_lshl_b32 s13, s19, 24
; SI-NEXT:    s_lshl_b32 s14, s14, 16
; SI-NEXT:    s_and_b32 s12, s12, 0xffff
; SI-NEXT:    s_or_b32 s13, s13, s14
; SI-NEXT:    s_add_i32 s20, s20, 3
; SI-NEXT:    s_or_b32 s12, s13, s12
; SI-NEXT:    s_and_b32 s13, s20, 0xff
; SI-NEXT:    s_lshl_b32 s14, s21, 8
; SI-NEXT:    s_add_i32 s22, s22, 3
; SI-NEXT:    s_or_b32 s13, s14, s13
; SI-NEXT:    s_and_b32 s15, s22, 0xff
; SI-NEXT:    s_addk_i32 s13, 0x300
; SI-NEXT:    s_lshl_b32 s14, s23, 24
; SI-NEXT:    s_lshl_b32 s15, s15, 16
; SI-NEXT:    s_and_b32 s13, s13, 0xffff
; SI-NEXT:    s_or_b32 s14, s14, s15
; SI-NEXT:    s_or_b32 s13, s14, s13
; SI-NEXT:    s_add_i32 s4, s4, 0x3000000
; SI-NEXT:    s_add_i32 s5, s5, 0x3000000
; SI-NEXT:    s_add_i32 s6, s6, 0x3000000
; SI-NEXT:    s_add_i32 s7, s7, 0x3000000
; SI-NEXT:    s_add_i32 s8, s8, 0x3000000
; SI-NEXT:    s_add_i32 s9, s9, 0x3000000
; SI-NEXT:    s_add_i32 s10, s10, 0x3000000
; SI-NEXT:    s_add_i32 s11, s11, 0x3000000
; SI-NEXT:    s_add_i32 s12, s12, 0x3000000
; SI-NEXT:    s_add_i32 s13, s13, 0x3000000
; SI-NEXT:    s_lshr_b64 s[14:15], s[12:13], 16
; SI-NEXT:    s_lshr_b64 s[16:17], s[10:11], 16
; SI-NEXT:    s_lshr_b64 s[18:19], s[8:9], 16
; SI-NEXT:    s_lshr_b64 s[20:21], s[6:7], 16
; SI-NEXT:    s_lshr_b64 s[22:23], s[4:5], 16
; SI-NEXT:    s_lshr_b32 s23, s13, 16
; SI-NEXT:    s_lshr_b32 s21, s11, 16
; SI-NEXT:    s_lshr_b32 s19, s9, 16
; SI-NEXT:    s_lshr_b32 s17, s7, 16
; SI-NEXT:    s_lshr_b32 s15, s5, 16
; SI-NEXT:  .LBB63_3: ; %end
; SI-NEXT:    s_and_b32 s12, s12, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s14, 16
; SI-NEXT:    s_or_b32 s12, s12, s14
; SI-NEXT:    s_and_b32 s13, s13, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s23, 16
; SI-NEXT:    s_or_b32 s13, s13, s14
; SI-NEXT:    s_and_b32 s10, s10, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s16, 16
; SI-NEXT:    s_or_b32 s10, s10, s14
; SI-NEXT:    s_and_b32 s11, s11, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s21, 16
; SI-NEXT:    s_or_b32 s11, s11, s14
; SI-NEXT:    s_and_b32 s8, s8, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s18, 16
; SI-NEXT:    s_or_b32 s8, s8, s14
; SI-NEXT:    s_and_b32 s9, s9, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s19, 16
; SI-NEXT:    s_or_b32 s9, s9, s14
; SI-NEXT:    s_and_b32 s6, s6, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s20, 16
; SI-NEXT:    s_or_b32 s6, s6, s14
; SI-NEXT:    s_and_b32 s7, s7, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s17, 16
; SI-NEXT:    s_or_b32 s7, s7, s14
; SI-NEXT:    s_and_b32 s4, s4, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s22, 16
; SI-NEXT:    s_or_b32 s4, s4, s14
; SI-NEXT:    s_and_b32 s5, s5, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s15, 16
; SI-NEXT:    s_or_b32 s5, s5, s14
; SI-NEXT:    v_mov_b32_e32 v0, s12
; SI-NEXT:    v_mov_b32_e32 v1, s13
; SI-NEXT:    v_mov_b32_e32 v2, s10
; SI-NEXT:    v_mov_b32_e32 v3, s11
; SI-NEXT:    v_mov_b32_e32 v4, s8
; SI-NEXT:    v_mov_b32_e32 v5, s9
; SI-NEXT:    v_mov_b32_e32 v6, s6
; SI-NEXT:    v_mov_b32_e32 v7, s7
; SI-NEXT:    v_mov_b32_e32 v8, s4
; SI-NEXT:    v_mov_b32_e32 v9, s5
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v40i8_to_v20f16_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_readfirstlane_b32 s61, v26
; VI-NEXT:    v_readfirstlane_b32 s5, v25
; VI-NEXT:    v_readfirstlane_b32 s7, v24
; VI-NEXT:    v_readfirstlane_b32 s4, v23
; VI-NEXT:    v_readfirstlane_b32 s6, v22
; VI-NEXT:    v_readfirstlane_b32 s8, v21
; VI-NEXT:    v_readfirstlane_b32 s10, v20
; VI-NEXT:    v_readfirstlane_b32 s9, v19
; VI-NEXT:    v_readfirstlane_b32 s11, v18
; VI-NEXT:    v_readfirstlane_b32 s12, v17
; VI-NEXT:    v_readfirstlane_b32 s14, v16
; VI-NEXT:    v_readfirstlane_b32 s13, v15
; VI-NEXT:    v_readfirstlane_b32 s15, v14
; VI-NEXT:    v_readfirstlane_b32 s40, v13
; VI-NEXT:    v_readfirstlane_b32 s42, v12
; VI-NEXT:    v_readfirstlane_b32 s41, v11
; VI-NEXT:    v_readfirstlane_b32 s43, v10
; VI-NEXT:    v_readfirstlane_b32 s44, v9
; VI-NEXT:    v_readfirstlane_b32 s46, v8
; VI-NEXT:    v_readfirstlane_b32 s45, v7
; VI-NEXT:    v_readfirstlane_b32 s47, v6
; VI-NEXT:    v_readfirstlane_b32 s56, v5
; VI-NEXT:    v_readfirstlane_b32 s58, v4
; VI-NEXT:    v_readfirstlane_b32 s57, v3
; VI-NEXT:    v_readfirstlane_b32 s59, v2
; VI-NEXT:    v_readfirstlane_b32 s60, v1
; VI-NEXT:    s_cmp_lg_u32 s61, 0
; VI-NEXT:    v_readfirstlane_b32 s61, v0
; VI-NEXT:    s_cbranch_scc0 .LBB63_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    v_mov_b32_e32 v9, 0xc0c0004
; VI-NEXT:    v_mov_b32_e32 v1, s19
; VI-NEXT:    v_mov_b32_e32 v0, s17
; VI-NEXT:    v_perm_b32 v1, s18, v1, v9
; VI-NEXT:    v_perm_b32 v0, s16, v0, v9
; VI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT:    v_mov_b32_e32 v2, s23
; VI-NEXT:    v_or_b32_e32 v0, v0, v1
; VI-NEXT:    v_mov_b32_e32 v1, s21
; VI-NEXT:    v_perm_b32 v2, s22, v2, v9
; VI-NEXT:    v_perm_b32 v1, s20, v1, v9
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_mov_b32_e32 v3, s27
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_mov_b32_e32 v2, s25
; VI-NEXT:    v_perm_b32 v3, s26, v3, v9
; VI-NEXT:    v_perm_b32 v2, s24, v2, v9
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_mov_b32_e32 v4, s60
; VI-NEXT:    v_or_b32_e32 v2, v2, v3
; VI-NEXT:    v_mov_b32_e32 v3, s29
; VI-NEXT:    v_perm_b32 v4, s61, v4, v9
; VI-NEXT:    v_perm_b32 v3, s28, v3, v9
; VI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT:    v_mov_b32_e32 v5, s56
; VI-NEXT:    v_or_b32_e32 v3, v3, v4
; VI-NEXT:    v_mov_b32_e32 v4, s57
; VI-NEXT:    v_perm_b32 v5, s58, v5, v9
; VI-NEXT:    v_perm_b32 v4, s59, v4, v9
; VI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT:    v_mov_b32_e32 v6, s44
; VI-NEXT:    v_or_b32_e32 v4, v4, v5
; VI-NEXT:    v_mov_b32_e32 v5, s45
; VI-NEXT:    v_perm_b32 v6, s46, v6, v9
; VI-NEXT:    v_perm_b32 v5, s47, v5, v9
; VI-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT:    v_mov_b32_e32 v7, s40
; VI-NEXT:    v_or_b32_e32 v5, v5, v6
; VI-NEXT:    v_mov_b32_e32 v6, s41
; VI-NEXT:    v_perm_b32 v7, s42, v7, v9
; VI-NEXT:    v_perm_b32 v6, s43, v6, v9
; VI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT:    v_mov_b32_e32 v8, s12
; VI-NEXT:    v_or_b32_e32 v6, v6, v7
; VI-NEXT:    v_mov_b32_e32 v7, s13
; VI-NEXT:    v_perm_b32 v8, s14, v8, v9
; VI-NEXT:    v_perm_b32 v7, s15, v7, v9
; VI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT:    v_mov_b32_e32 v10, s8
; VI-NEXT:    v_or_b32_e32 v7, v7, v8
; VI-NEXT:    v_mov_b32_e32 v8, s9
; VI-NEXT:    v_perm_b32 v10, s10, v10, v9
; VI-NEXT:    v_perm_b32 v8, s11, v8, v9
; VI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT:    v_or_b32_e32 v8, v8, v10
; VI-NEXT:    v_mov_b32_e32 v10, s4
; VI-NEXT:    v_mov_b32_e32 v11, s5
; VI-NEXT:    v_perm_b32 v10, s6, v10, v9
; VI-NEXT:    v_perm_b32 v9, s7, v11, v9
; VI-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT:    v_or_b32_e32 v9, v10, v9
; VI-NEXT:    s_setpc_b64 s[30:31]
; VI-NEXT:  .LBB63_2: ; %cmp.true
; VI-NEXT:    s_add_i32 s7, s7, 3
; VI-NEXT:    v_mov_b32_e32 v0, s5
; VI-NEXT:    v_mov_b32_e32 v1, 0xc0c0004
; VI-NEXT:    v_perm_b32 v0, s7, v0, v1
; VI-NEXT:    v_lshlrev_b32_e32 v9, 16, v0
; VI-NEXT:    s_add_i32 s6, s6, 3
; VI-NEXT:    v_mov_b32_e32 v0, s4
; VI-NEXT:    v_perm_b32 v0, s6, v0, v1
; VI-NEXT:    v_add_u32_e32 v10, vcc, 0x300, v0
; VI-NEXT:    s_add_i32 s10, s10, 3
; VI-NEXT:    v_mov_b32_e32 v0, s8
; VI-NEXT:    v_perm_b32 v0, s10, v0, v1
; VI-NEXT:    v_lshlrev_b32_e32 v8, 16, v0
; VI-NEXT:    s_add_i32 s11, s11, 3
; VI-NEXT:    v_mov_b32_e32 v0, s9
; VI-NEXT:    v_perm_b32 v0, s11, v0, v1
; VI-NEXT:    v_add_u32_e32 v11, vcc, 0x300, v0
; VI-NEXT:    s_add_i32 s14, s14, 3
; VI-NEXT:    v_mov_b32_e32 v0, s12
; VI-NEXT:    v_perm_b32 v0, s14, v0, v1
; VI-NEXT:    v_lshlrev_b32_e32 v7, 16, v0
; VI-NEXT:    s_add_i32 s15, s15, 3
; VI-NEXT:    v_mov_b32_e32 v0, s13
; VI-NEXT:    v_perm_b32 v0, s15, v0, v1
; VI-NEXT:    v_add_u32_e32 v12, vcc, 0x300, v0
; VI-NEXT:    s_add_i32 s42, s42, 3
; VI-NEXT:    v_mov_b32_e32 v0, s40
; VI-NEXT:    v_perm_b32 v0, s42, v0, v1
; VI-NEXT:    v_lshlrev_b32_e32 v6, 16, v0
; VI-NEXT:    s_add_i32 s43, s43, 3
; VI-NEXT:    v_mov_b32_e32 v0, s41
; VI-NEXT:    v_perm_b32 v0, s43, v0, v1
; VI-NEXT:    v_add_u32_e32 v13, vcc, 0x300, v0
; VI-NEXT:    s_add_i32 s46, s46, 3
; VI-NEXT:    v_mov_b32_e32 v0, s44
; VI-NEXT:    v_perm_b32 v0, s46, v0, v1
; VI-NEXT:    v_lshlrev_b32_e32 v5, 16, v0
; VI-NEXT:    s_add_i32 s47, s47, 3
; VI-NEXT:    v_mov_b32_e32 v0, s45
; VI-NEXT:    v_perm_b32 v0, s47, v0, v1
; VI-NEXT:    v_add_u32_e32 v14, vcc, 0x300, v0
; VI-NEXT:    s_add_i32 s58, s58, 3
; VI-NEXT:    v_mov_b32_e32 v0, s56
; VI-NEXT:    v_perm_b32 v0, s58, v0, v1
; VI-NEXT:    v_lshlrev_b32_e32 v4, 16, v0
; VI-NEXT:    s_add_i32 s59, s59, 3
; VI-NEXT:    v_mov_b32_e32 v0, s57
; VI-NEXT:    v_perm_b32 v0, s59, v0, v1
; VI-NEXT:    v_add_u32_e32 v15, vcc, 0x300, v0
; VI-NEXT:    s_add_i32 s61, s61, 3
; VI-NEXT:    v_mov_b32_e32 v0, s60
; VI-NEXT:    v_perm_b32 v0, s61, v0, v1
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v0
; VI-NEXT:    s_add_i32 s28, s28, 3
; VI-NEXT:    v_mov_b32_e32 v0, s29
; VI-NEXT:    v_perm_b32 v0, s28, v0, v1
; VI-NEXT:    v_add_u32_e32 v16, vcc, 0x300, v0
; VI-NEXT:    s_add_i32 s26, s26, 3
; VI-NEXT:    v_mov_b32_e32 v0, s27
; VI-NEXT:    v_perm_b32 v0, s26, v0, v1
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v0
; VI-NEXT:    s_add_i32 s24, s24, 3
; VI-NEXT:    v_mov_b32_e32 v0, s25
; VI-NEXT:    v_perm_b32 v0, s24, v0, v1
; VI-NEXT:    v_add_u32_e32 v17, vcc, 0x300, v0
; VI-NEXT:    s_add_i32 s22, s22, 3
; VI-NEXT:    v_mov_b32_e32 v0, s23
; VI-NEXT:    v_perm_b32 v0, s22, v0, v1
; VI-NEXT:    v_lshlrev_b32_e32 v18, 16, v0
; VI-NEXT:    s_add_i32 s20, s20, 3
; VI-NEXT:    v_mov_b32_e32 v0, s21
; VI-NEXT:    v_perm_b32 v0, s20, v0, v1
; VI-NEXT:    v_add_u32_e32 v19, vcc, 0x300, v0
; VI-NEXT:    s_add_i32 s18, s18, 3
; VI-NEXT:    v_mov_b32_e32 v0, s19
; VI-NEXT:    s_add_i32 s16, s16, 3
; VI-NEXT:    v_mov_b32_e32 v20, s17
; VI-NEXT:    v_perm_b32 v0, s18, v0, v1
; VI-NEXT:    v_perm_b32 v1, s16, v20, v1
; VI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
; VI-NEXT:    v_add_u32_e32 v1, vcc, 0x300, v1
; VI-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    v_or_b32_sdwa v1, v18, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    v_or_b32_sdwa v2, v2, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    v_or_b32_sdwa v3, v3, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    v_or_b32_sdwa v4, v4, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    v_or_b32_sdwa v5, v5, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    v_or_b32_sdwa v6, v6, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    v_or_b32_sdwa v7, v7, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    v_or_b32_sdwa v8, v8, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    v_or_b32_sdwa v9, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    v_add_u32_e32 v0, vcc, 0x3000000, v0
; VI-NEXT:    v_add_u32_e32 v1, vcc, 0x3000000, v1
; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x3000000, v2
; VI-NEXT:    v_add_u32_e32 v3, vcc, 0x3000000, v3
; VI-NEXT:    v_add_u32_e32 v4, vcc, 0x3000000, v4
; VI-NEXT:    v_add_u32_e32 v5, vcc, 0x3000000, v5
; VI-NEXT:    v_add_u32_e32 v6, vcc, 0x3000000, v6
; VI-NEXT:    v_add_u32_e32 v7, vcc, 0x3000000, v7
; VI-NEXT:    v_add_u32_e32 v8, vcc, 0x3000000, v8
; VI-NEXT:    v_add_u32_e32 v9, vcc, 0x3000000, v9
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v40i8_to_v20f16_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_readfirstlane_b32 s58, v26
; GFX9-NEXT:    v_readfirstlane_b32 s4, v25
; GFX9-NEXT:    v_readfirstlane_b32 s6, v24
; GFX9-NEXT:    v_readfirstlane_b32 s14, v23
; GFX9-NEXT:    v_readfirstlane_b32 s40, v22
; GFX9-NEXT:    v_readfirstlane_b32 s5, v21
; GFX9-NEXT:    v_readfirstlane_b32 s7, v20
; GFX9-NEXT:    v_readfirstlane_b32 s12, v19
; GFX9-NEXT:    v_readfirstlane_b32 s43, v18
; GFX9-NEXT:    v_readfirstlane_b32 s8, v17
; GFX9-NEXT:    v_readfirstlane_b32 s9, v16
; GFX9-NEXT:    v_readfirstlane_b32 s44, v15
; GFX9-NEXT:    v_readfirstlane_b32 s46, v14
; GFX9-NEXT:    v_readfirstlane_b32 s10, v13
; GFX9-NEXT:    v_readfirstlane_b32 s11, v12
; GFX9-NEXT:    v_readfirstlane_b32 s47, v11
; GFX9-NEXT:    v_readfirstlane_b32 s56, v10
; GFX9-NEXT:    v_readfirstlane_b32 s13, v9
; GFX9-NEXT:    v_readfirstlane_b32 s15, v8
; GFX9-NEXT:    v_readfirstlane_b32 s57, v7
; GFX9-NEXT:    v_readfirstlane_b32 s59, v6
; GFX9-NEXT:    v_readfirstlane_b32 s41, v5
; GFX9-NEXT:    v_readfirstlane_b32 s42, v4
; GFX9-NEXT:    v_readfirstlane_b32 s60, v3
; GFX9-NEXT:    v_readfirstlane_b32 s61, v2
; GFX9-NEXT:    v_readfirstlane_b32 s45, v1
; GFX9-NEXT:    s_cmp_lg_u32 s58, 0
; GFX9-NEXT:    v_readfirstlane_b32 s58, v0
; GFX9-NEXT:    s_cbranch_scc0 .LBB63_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    v_mov_b32_e32 v9, 0xc0c0004
; GFX9-NEXT:    v_mov_b32_e32 v1, s19
; GFX9-NEXT:    v_mov_b32_e32 v0, s17
; GFX9-NEXT:    v_perm_b32 v1, s18, v1, v9
; GFX9-NEXT:    v_perm_b32 v0, s16, v0, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT:    v_mov_b32_e32 v2, s23
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_mov_b32_e32 v1, s21
; GFX9-NEXT:    v_perm_b32 v2, s22, v2, v9
; GFX9-NEXT:    v_perm_b32 v1, s20, v1, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT:    v_mov_b32_e32 v3, s27
; GFX9-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_mov_b32_e32 v2, s25
; GFX9-NEXT:    v_perm_b32 v3, s26, v3, v9
; GFX9-NEXT:    v_perm_b32 v2, s24, v2, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT:    v_mov_b32_e32 v4, s45
; GFX9-NEXT:    v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_mov_b32_e32 v3, s29
; GFX9-NEXT:    v_perm_b32 v4, s58, v4, v9
; GFX9-NEXT:    v_perm_b32 v3, s28, v3, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; GFX9-NEXT:    v_mov_b32_e32 v5, s41
; GFX9-NEXT:    v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_mov_b32_e32 v4, s60
; GFX9-NEXT:    v_perm_b32 v5, s42, v5, v9
; GFX9-NEXT:    v_perm_b32 v4, s61, v4, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; GFX9-NEXT:    v_mov_b32_e32 v6, s13
; GFX9-NEXT:    v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_mov_b32_e32 v5, s57
; GFX9-NEXT:    v_perm_b32 v6, s15, v6, v9
; GFX9-NEXT:    v_perm_b32 v5, s59, v5, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; GFX9-NEXT:    v_mov_b32_e32 v7, s10
; GFX9-NEXT:    v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_mov_b32_e32 v6, s47
; GFX9-NEXT:    v_perm_b32 v7, s11, v7, v9
; GFX9-NEXT:    v_perm_b32 v6, s56, v6, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; GFX9-NEXT:    v_mov_b32_e32 v8, s8
; GFX9-NEXT:    v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_mov_b32_e32 v7, s44
; GFX9-NEXT:    v_perm_b32 v8, s9, v8, v9
; GFX9-NEXT:    v_perm_b32 v7, s46, v7, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; GFX9-NEXT:    v_mov_b32_e32 v10, 0x6050400
; GFX9-NEXT:    v_mov_b32_e32 v11, s7
; GFX9-NEXT:    v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_mov_b32_e32 v8, s43
; GFX9-NEXT:    v_perm_b32 v11, s5, v11, v10
; GFX9-NEXT:    v_perm_b32 v8, s12, v8, v10
; GFX9-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; GFX9-NEXT:    v_or_b32_sdwa v8, v11, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_mov_b32_e32 v11, s14
; GFX9-NEXT:    v_perm_b32 v9, s40, v11, v9
; GFX9-NEXT:    v_mov_b32_e32 v11, s6
; GFX9-NEXT:    v_perm_b32 v10, s4, v11, v10
; GFX9-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; GFX9-NEXT:    v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
; GFX9-NEXT:  .LBB63_2: ; %cmp.true
; GFX9-NEXT:    s_add_i32 s40, s40, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s14
; GFX9-NEXT:    v_mov_b32_e32 v1, 0xc0c0004
; GFX9-NEXT:    v_perm_b32 v0, s40, v0, v1
; GFX9-NEXT:    v_add_u32_e32 v9, 0x300, v0
; GFX9-NEXT:    s_add_i32 s6, s6, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s4
; GFX9-NEXT:    s_movk_i32 s14, 0x300
; GFX9-NEXT:    v_perm_b32 v0, s6, v0, v1
; GFX9-NEXT:    v_add_u32_sdwa v10, v0, s14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s43, s43, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s12
; GFX9-NEXT:    v_perm_b32 v0, s43, v0, v1
; GFX9-NEXT:    v_add_u32_e32 v8, 0x300, v0
; GFX9-NEXT:    s_add_i32 s7, s7, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s5
; GFX9-NEXT:    v_perm_b32 v0, s7, v0, v1
; GFX9-NEXT:    v_add_u32_sdwa v11, v0, s14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s46, s46, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s44
; GFX9-NEXT:    v_perm_b32 v0, s46, v0, v1
; GFX9-NEXT:    v_add_u32_e32 v7, 0x300, v0
; GFX9-NEXT:    s_add_i32 s9, s9, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s8
; GFX9-NEXT:    v_perm_b32 v0, s9, v0, v1
; GFX9-NEXT:    v_add_u32_sdwa v12, v0, s14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s56, s56, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s47
; GFX9-NEXT:    v_perm_b32 v0, s56, v0, v1
; GFX9-NEXT:    v_add_u32_e32 v6, 0x300, v0
; GFX9-NEXT:    s_add_i32 s11, s11, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s10
; GFX9-NEXT:    v_perm_b32 v0, s11, v0, v1
; GFX9-NEXT:    v_add_u32_sdwa v13, v0, s14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s59, s59, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s57
; GFX9-NEXT:    v_perm_b32 v0, s59, v0, v1
; GFX9-NEXT:    v_add_u32_e32 v5, 0x300, v0
; GFX9-NEXT:    s_add_i32 s15, s15, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s13
; GFX9-NEXT:    v_perm_b32 v0, s15, v0, v1
; GFX9-NEXT:    v_add_u32_sdwa v14, v0, s14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s61, s61, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s60
; GFX9-NEXT:    v_perm_b32 v0, s61, v0, v1
; GFX9-NEXT:    v_add_u32_e32 v4, 0x300, v0
; GFX9-NEXT:    s_add_i32 s42, s42, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s41
; GFX9-NEXT:    v_perm_b32 v0, s42, v0, v1
; GFX9-NEXT:    v_add_u32_sdwa v15, v0, s14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s28, s28, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s29
; GFX9-NEXT:    v_perm_b32 v0, s28, v0, v1
; GFX9-NEXT:    v_add_u32_e32 v3, 0x300, v0
; GFX9-NEXT:    s_add_i32 s58, s58, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s45
; GFX9-NEXT:    v_perm_b32 v0, s58, v0, v1
; GFX9-NEXT:    v_add_u32_sdwa v16, v0, s14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s24, s24, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s25
; GFX9-NEXT:    v_perm_b32 v0, s24, v0, v1
; GFX9-NEXT:    v_add_u32_e32 v2, 0x300, v0
; GFX9-NEXT:    s_add_i32 s26, s26, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s27
; GFX9-NEXT:    v_perm_b32 v0, s26, v0, v1
; GFX9-NEXT:    v_add_u32_sdwa v17, v0, s14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s20, s20, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s21
; GFX9-NEXT:    v_perm_b32 v0, s20, v0, v1
; GFX9-NEXT:    v_add_u32_e32 v18, 0x300, v0
; GFX9-NEXT:    s_add_i32 s22, s22, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s23
; GFX9-NEXT:    v_perm_b32 v0, s22, v0, v1
; GFX9-NEXT:    v_add_u32_sdwa v19, v0, s14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s16, s16, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s17
; GFX9-NEXT:    s_add_i32 s18, s18, 3
; GFX9-NEXT:    v_mov_b32_e32 v20, s19
; GFX9-NEXT:    v_perm_b32 v0, s16, v0, v1
; GFX9-NEXT:    v_perm_b32 v1, s18, v20, v1
; GFX9-NEXT:    v_add_u32_e32 v0, 0x300, v0
; GFX9-NEXT:    v_add_u32_sdwa v1, v1, s14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_or_b32_sdwa v1, v19, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_or_b32_sdwa v2, v17, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_or_b32_sdwa v3, v16, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_or_b32_sdwa v4, v15, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_or_b32_sdwa v5, v14, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_or_b32_sdwa v6, v13, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_or_b32_sdwa v7, v12, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_or_b32_sdwa v8, v11, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v40i8_to_v20f16_scalar:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s58, v22
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s4, v21
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s6, v20
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s5, v19
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s8, v18
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s9, v17
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s11, v16
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s7, v15
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s10, v14
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s12, v13
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s13, v12
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s14, v11
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s15, v10
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s40, v9
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s43, v8
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s41, v7
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s42, v6
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s44, v5
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s45, v4
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s46, v3
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s56, v2
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s47, v1
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s57, v0
; GFX11-TRUE16-NEXT:    s_cmp_lg_u32 s58, 0
; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB63_2
; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v9, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v8, 0x6050400
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_perm_b32 v3, s2, s3, v9
; GFX11-TRUE16-NEXT:    v_perm_b32 v5, s22, s23, v9
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, s26, s27, v9
; GFX11-TRUE16-NEXT:    v_perm_b32 v0, s0, s1, v9
; GFX11-TRUE16-NEXT:    v_perm_b32 v4, s18, s19, v9
; GFX11-TRUE16-NEXT:    v_perm_b32 v2, s20, s21, v9
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v3.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v5.l
; GFX11-TRUE16-NEXT:    v_perm_b32 v5, s57, s47, v9
; GFX11-TRUE16-NEXT:    v_perm_b32 v3, s24, s25, v9
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v6.l
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, s45, s44, v9
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, s43, s40, v9
; GFX11-TRUE16-NEXT:    v_perm_b32 v1, s16, s17, v9
; GFX11-TRUE16-NEXT:    v_perm_b32 v10, s13, s12, v9
; GFX11-TRUE16-NEXT:    v_perm_b32 v11, s9, s11, v8
; GFX11-TRUE16-NEXT:    v_perm_b32 v12, s4, s6, v8
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT:    v_perm_b32 v4, s28, s29, v9
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v5.l
; GFX11-TRUE16-NEXT:    v_perm_b32 v5, s56, s46, v9
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v6.l
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, s42, s41, v9
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v7.l
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, s15, s14, v9
; GFX11-TRUE16-NEXT:    v_perm_b32 v8, s7, s10, v8
; GFX11-TRUE16-NEXT:    v_perm_b32 v9, s8, s5, v9
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.h, v10.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.h, v11.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.h, v12.l
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT:  .LBB63_2: ; %cmp.true
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, 0xc0c0004
; GFX11-TRUE16-NEXT:    s_add_i32 s8, s8, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s15, s15, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s6, s6, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s11, s11, 3
; GFX11-TRUE16-NEXT:    v_perm_b32 v1, s8, s5, v0
; GFX11-TRUE16-NEXT:    s_add_i32 s13, s13, 3
; GFX11-TRUE16-NEXT:    v_perm_b32 v2, s6, s4, v0
; GFX11-TRUE16-NEXT:    v_perm_b32 v4, s11, s9, v0
; GFX11-TRUE16-NEXT:    s_add_i32 s42, s42, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v9, 0x300, v1
; GFX11-TRUE16-NEXT:    v_perm_b32 v1, s15, s14, v0
; GFX11-TRUE16-NEXT:    s_add_i32 s56, s56, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s28, s28, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v10, 0x300, v2
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v11, 0x300, v4
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v7, 0x300, v1
; GFX11-TRUE16-NEXT:    v_perm_b32 v1, s13, s12, v0
; GFX11-TRUE16-NEXT:    v_perm_b32 v2, s42, s41, v0
; GFX11-TRUE16-NEXT:    v_perm_b32 v4, s56, s46, v0
; GFX11-TRUE16-NEXT:    s_add_i32 s10, s10, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s57, s57, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v13, 0x300, v1
; GFX11-TRUE16-NEXT:    v_perm_b32 v1, s28, s29, v0
; GFX11-TRUE16-NEXT:    s_add_i32 s20, s20, 3
; GFX11-TRUE16-NEXT:    v_perm_b32 v3, s10, s7, v0
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v6, 0x300, v2
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v5, 0x300, v4
; GFX11-TRUE16-NEXT:    v_perm_b32 v2, s57, s47, v0
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v4, 0x300, v1
; GFX11-TRUE16-NEXT:    v_perm_b32 v1, s20, s21, v0
; GFX11-TRUE16-NEXT:    s_add_i32 s43, s43, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s45, s45, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s26, s26, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s22, s22, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s18, s18, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v8, 0x300, v3
; GFX11-TRUE16-NEXT:    v_perm_b32 v3, s43, s40, v0
; GFX11-TRUE16-NEXT:    v_perm_b32 v12, s45, s44, v0
; GFX11-TRUE16-NEXT:    v_perm_b32 v15, s26, s27, v0
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v16, 0x300, v2
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, 0x300, v1
; GFX11-TRUE16-NEXT:    v_perm_b32 v1, s22, s23, v0
; GFX11-TRUE16-NEXT:    v_perm_b32 v17, s2, s3, v0
; GFX11-TRUE16-NEXT:    v_perm_b32 v18, s18, s19, v0
; GFX11-TRUE16-NEXT:    s_add_i32 s24, s24, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s16, s16, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s0, s0, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v14, 0x300, v3
; GFX11-TRUE16-NEXT:    v_perm_b32 v3, s24, s25, v0
; GFX11-TRUE16-NEXT:    v_perm_b32 v19, s16, s17, v0
; GFX11-TRUE16-NEXT:    v_perm_b32 v0, s0, s1, v0
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v15, 0x300, v15
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v17, 0x300, v17
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v18, 0x300, v18
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v20, 0x300, v1
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v1, 0x300, v19
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v17.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v18.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v20.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v15.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v16.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v12.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v14.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.h, v13.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.h, v11.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.h, v10.l
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v40i8_to_v20f16_scalar:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s58, v22
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s4, v21
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s11, v20
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s10, v19
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s42, v18
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s5, v17
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s12, v16
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s13, v15
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s45, v14
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s6, v13
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s8, v12
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s15, v11
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s44, v10
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s7, v9
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s9, v8
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s40, v7
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s46, v6
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s14, v5
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s41, v4
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s43, v3
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s57, v2
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s47, v1
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s56, v0
; GFX11-FAKE16-NEXT:    s_cmp_lg_u32 s58, 0
; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB63_2
; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, 0xc0c0004
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_perm_b32 v0, s0, s1, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v2, s16, s17, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v4, s20, s21, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, s28, s29, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v1, s2, s3, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v3, s18, s19, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, s22, s23, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, s24, s25, v5
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT:    v_perm_b32 v10, s56, s47, v5
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, s26, s27, v5
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, v6, 16, v4
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v4, v10, 16, v9
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v9, 0x6050400
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v3, v8, 16, v7
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, s57, s43, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, s41, s14, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, s46, s40, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v10, s9, s7, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v11, s44, s15, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v12, s13, s45, v9
; GFX11-FAKE16-NEXT:    v_perm_b32 v13, s8, s6, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v5, s42, s10, v5
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
; GFX11-FAKE16-NEXT:    v_perm_b32 v14, s5, s12, v9
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, s4, s11, v9
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v5
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v5, v7, 16, v6
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v6, v10, 16, v8
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v7, v13, 16, v11
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v8, v14, 16, v12
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v9, v9, 16, v15
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT:  .LBB63_2: ; %cmp.true
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 0xc0c0004
; GFX11-FAKE16-NEXT:    s_add_i32 s42, s42, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s11, s11, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s45, s45, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s12, s12, 3
; GFX11-FAKE16-NEXT:    v_perm_b32 v1, s42, s10, v0
; GFX11-FAKE16-NEXT:    s_add_i32 s44, s44, 3
; GFX11-FAKE16-NEXT:    v_perm_b32 v2, s11, s4, v0
; GFX11-FAKE16-NEXT:    v_perm_b32 v3, s45, s13, v0
; GFX11-FAKE16-NEXT:    v_perm_b32 v4, s12, s5, v0
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v5, 0x300, v1
; GFX11-FAKE16-NEXT:    v_perm_b32 v1, s44, s15, v0
; GFX11-FAKE16-NEXT:    s_add_i32 s8, s8, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s46, s46, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s9, s9, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s57, s57, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v9, 0x300, v2
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v6, 0x300, v3
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v8, 0x300, v4
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v7, 0x300, v1
; GFX11-FAKE16-NEXT:    v_perm_b32 v1, s8, s6, v0
; GFX11-FAKE16-NEXT:    v_perm_b32 v2, s46, s40, v0
; GFX11-FAKE16-NEXT:    v_perm_b32 v3, s9, s7, v0
; GFX11-FAKE16-NEXT:    v_perm_b32 v4, s57, s43, v0
; GFX11-FAKE16-NEXT:    s_add_i32 s28, s28, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s56, s56, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s24, s24, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s26, s26, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s20, s20, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v11, 0x300, v1
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v12, 0x300, v2
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v13, 0x300, v3
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v14, 0x300, v4
; GFX11-FAKE16-NEXT:    v_perm_b32 v1, s28, s29, v0
; GFX11-FAKE16-NEXT:    v_perm_b32 v2, s56, s47, v0
; GFX11-FAKE16-NEXT:    v_perm_b32 v3, s24, s25, v0
; GFX11-FAKE16-NEXT:    v_perm_b32 v4, s26, s27, v0
; GFX11-FAKE16-NEXT:    v_perm_b32 v15, s20, s21, v0
; GFX11-FAKE16-NEXT:    s_add_i32 s22, s22, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s16, s16, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s0, s0, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v16, 0x300, v2
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v2, 0x300, v3
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v3, 0x300, v4
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, 0x300, v15
; GFX11-FAKE16-NEXT:    v_perm_b32 v15, s22, s23, v0
; GFX11-FAKE16-NEXT:    v_perm_b32 v17, s16, s17, v0
; GFX11-FAKE16-NEXT:    v_perm_b32 v18, s0, s1, v0
; GFX11-FAKE16-NEXT:    s_add_i32 s41, s41, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s18, s18, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s2, s2, 3
; GFX11-FAKE16-NEXT:    v_perm_b32 v10, s41, s14, v0
; GFX11-FAKE16-NEXT:    v_perm_b32 v19, s18, s19, v0
; GFX11-FAKE16-NEXT:    v_perm_b32 v0, s2, s3, v0
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v18, 0x300, v18
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v17, 0x300, v17
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v15, 0x300, v15
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xffff, v1
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v10, 0x300, v10
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v19, 0x300, v19
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xffff, v18
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xffff, v17
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xffff, v2
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, v15, 16, v4
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v4, v16, 16, v21
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v6
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff, v5
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v0, 16, v18
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v19, 16, v17
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v3, v3, 16, v20
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v5, v10, 16, v14
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v6, v13, 16, v12
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v7, v11, 16, v7
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v8, v8, 16, v15
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v9, v9, 16, v16
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <40 x i8> %a, splat (i8 3)
  %a2 = bitcast <40 x i8> %a1 to <20 x half>
  br label %end

cmp.false:
  %a3 = bitcast <40 x i8> %a to <20 x half>
  br label %end

end:
  %phi = phi <20 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <20 x half> %phi
}

define <5 x double> @bitcast_v20f16_to_v5f64(<20 x half> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v20f16_to_v5f64:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_mov_b32_e32 v16, v9
; SI-NEXT:    v_mov_b32_e32 v17, v8
; SI-NEXT:    v_mov_b32_e32 v18, v7
; SI-NEXT:    v_mov_b32_e32 v19, v6
; SI-NEXT:    v_mov_b32_e32 v20, v5
; SI-NEXT:    v_mov_b32_e32 v21, v4
; SI-NEXT:    v_mov_b32_e32 v22, v3
; SI-NEXT:    v_mov_b32_e32 v23, v2
; SI-NEXT:    v_mov_b32_e32 v24, v1
; SI-NEXT:    v_mov_b32_e32 v25, v0
; SI-NEXT:    v_lshrrev_b32_e32 v26, 16, v16
; SI-NEXT:    v_lshrrev_b32_e32 v27, 16, v17
; SI-NEXT:    v_lshrrev_b32_e32 v28, 16, v18
; SI-NEXT:    v_lshrrev_b32_e32 v29, 16, v19
; SI-NEXT:    v_lshrrev_b32_e32 v30, 16, v20
; SI-NEXT:    v_lshrrev_b32_e32 v31, 16, v21
; SI-NEXT:    v_lshrrev_b32_e32 v32, 16, v22
; SI-NEXT:    v_lshrrev_b32_e32 v33, 16, v23
; SI-NEXT:    v_lshrrev_b32_e32 v34, 16, v24
; SI-NEXT:    v_lshrrev_b32_e32 v35, 16, v25
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; SI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_cbranch_execnz .LBB64_3
; SI-NEXT:  ; %bb.1: ; %Flow
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execnz .LBB64_4
; SI-NEXT:  .LBB64_2: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    s_setpc_b64 s[30:31]
; SI-NEXT:  .LBB64_3: ; %cmp.false
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v25
; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v35
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v24
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v34
; SI-NEXT:    v_or_b32_e32 v0, v0, v1
; SI-NEXT:    v_or_b32_e32 v1, v2, v3
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v23
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v33
; SI-NEXT:    v_or_b32_e32 v2, v2, v3
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v22
; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v32
; SI-NEXT:    v_or_b32_e32 v3, v3, v4
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v21
; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v31
; SI-NEXT:    v_or_b32_e32 v4, v4, v5
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v20
; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v30
; SI-NEXT:    v_or_b32_e32 v5, v5, v6
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v19
; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v29
; SI-NEXT:    v_or_b32_e32 v6, v6, v7
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v18
; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v28
; SI-NEXT:    v_or_b32_e32 v7, v7, v8
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v17
; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v27
; SI-NEXT:    v_or_b32_e32 v8, v8, v9
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v16
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v26
; SI-NEXT:    v_or_b32_e32 v9, v9, v10
; SI-NEXT:    ; implicit-def: $vgpr25
; SI-NEXT:    ; implicit-def: $vgpr24
; SI-NEXT:    ; implicit-def: $vgpr23
; SI-NEXT:    ; implicit-def: $vgpr22
; SI-NEXT:    ; implicit-def: $vgpr21
; SI-NEXT:    ; implicit-def: $vgpr20
; SI-NEXT:    ; implicit-def: $vgpr19
; SI-NEXT:    ; implicit-def: $vgpr18
; SI-NEXT:    ; implicit-def: $vgpr17
; SI-NEXT:    ; implicit-def: $vgpr16
; SI-NEXT:    ; implicit-def: $vgpr35
; SI-NEXT:    ; implicit-def: $vgpr34
; SI-NEXT:    ; implicit-def: $vgpr33
; SI-NEXT:    ; implicit-def: $vgpr32
; SI-NEXT:    ; implicit-def: $vgpr31
; SI-NEXT:    ; implicit-def: $vgpr30
; SI-NEXT:    ; implicit-def: $vgpr29
; SI-NEXT:    ; implicit-def: $vgpr28
; SI-NEXT:    ; implicit-def: $vgpr27
; SI-NEXT:    ; implicit-def: $vgpr26
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB64_2
; SI-NEXT:  .LBB64_4: ; %cmp.true
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v35
; SI-NEXT:    v_cvt_f32_f16_e32 v2, v34
; SI-NEXT:    v_cvt_f32_f16_e32 v1, v25
; SI-NEXT:    v_cvt_f32_f16_e32 v3, v24
; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1
; SI-NEXT:    v_cvt_f16_f32_e32 v3, v3
; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_or_b32_e32 v0, v1, v0
; SI-NEXT:    v_or_b32_e32 v1, v3, v2
; SI-NEXT:    v_cvt_f32_f16_e32 v2, v33
; SI-NEXT:    v_cvt_f32_f16_e32 v3, v23
; SI-NEXT:    v_cvt_f32_f16_e32 v4, v32
; SI-NEXT:    v_cvt_f32_f16_e32 v5, v22
; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT:    v_cvt_f16_f32_e32 v3, v3
; SI-NEXT:    v_cvt_f16_f32_e32 v4, v4
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_cvt_f32_f16_e32 v6, v21
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v4
; SI-NEXT:    v_cvt_f32_f16_e32 v4, v31
; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT:    v_cvt_f16_f32_e32 v5, v5
; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT:    v_cvt_f16_f32_e32 v4, v4
; SI-NEXT:    v_cvt_f16_f32_e32 v6, v6
; SI-NEXT:    v_or_b32_e32 v3, v5, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v5, v30
; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT:    v_or_b32_e32 v4, v6, v4
; SI-NEXT:    v_cvt_f32_f16_e32 v6, v20
; SI-NEXT:    v_cvt_f32_f16_e32 v7, v29
; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT:    v_cvt_f16_f32_e32 v5, v5
; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT:    v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT:    v_cvt_f16_f32_e32 v6, v6
; SI-NEXT:    v_cvt_f16_f32_e32 v7, v7
; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT:    v_cvt_f32_f16_e32 v8, v19
; SI-NEXT:    v_or_b32_e32 v5, v6, v5
; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v7
; SI-NEXT:    v_cvt_f32_f16_e32 v7, v28
; SI-NEXT:    v_cvt_f32_f16_e32 v9, v18
; SI-NEXT:    v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT:    v_cvt_f16_f32_e32 v8, v8
; SI-NEXT:    v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT:    v_cvt_f16_f32_e32 v7, v7
; SI-NEXT:    v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT:    v_cvt_f16_f32_e32 v9, v9
; SI-NEXT:    v_or_b32_e32 v6, v8, v6
; SI-NEXT:    v_cvt_f32_f16_e32 v8, v27
; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT:    v_or_b32_e32 v7, v9, v7
; SI-NEXT:    v_cvt_f32_f16_e32 v9, v17
; SI-NEXT:    v_cvt_f32_f16_e32 v10, v26
; SI-NEXT:    v_cvt_f32_f16_e32 v11, v16
; SI-NEXT:    v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT:    v_cvt_f16_f32_e32 v8, v8
; SI-NEXT:    v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT:    v_add_f32_e32 v10, 0x38000000, v10
; SI-NEXT:    v_cvt_f16_f32_e32 v9, v9
; SI-NEXT:    v_cvt_f16_f32_e32 v10, v10
; SI-NEXT:    v_add_f32_e32 v11, 0x38000000, v11
; SI-NEXT:    v_cvt_f16_f32_e32 v11, v11
; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT:    v_or_b32_e32 v8, v9, v8
; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v10
; SI-NEXT:    v_or_b32_e32 v9, v11, v9
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v20f16_to_v5f64:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB64_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    v_mov_b32_e32 v10, 0x200
; VI-NEXT:    v_add_f16_sdwa v11, v9, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v9, 0x200, v9
; VI-NEXT:    v_or_b32_e32 v9, v9, v11
; VI-NEXT:    v_add_f16_sdwa v11, v8, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v8, 0x200, v8
; VI-NEXT:    v_or_b32_e32 v8, v8, v11
; VI-NEXT:    v_add_f16_sdwa v11, v7, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v7, 0x200, v7
; VI-NEXT:    v_or_b32_e32 v7, v7, v11
; VI-NEXT:    v_add_f16_sdwa v11, v6, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v6, 0x200, v6
; VI-NEXT:    v_or_b32_e32 v6, v6, v11
; VI-NEXT:    v_add_f16_sdwa v11, v5, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v5, 0x200, v5
; VI-NEXT:    v_or_b32_e32 v5, v5, v11
; VI-NEXT:    v_add_f16_sdwa v11, v4, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v4, 0x200, v4
; VI-NEXT:    v_or_b32_e32 v4, v4, v11
; VI-NEXT:    v_add_f16_sdwa v11, v3, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v3, 0x200, v3
; VI-NEXT:    v_or_b32_e32 v3, v3, v11
; VI-NEXT:    v_add_f16_sdwa v11, v2, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, 0x200, v2
; VI-NEXT:    v_or_b32_e32 v2, v2, v11
; VI-NEXT:    v_add_f16_sdwa v11, v1, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v1, 0x200, v1
; VI-NEXT:    v_add_f16_sdwa v10, v0, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v0, 0x200, v0
; VI-NEXT:    v_or_b32_e32 v1, v1, v11
; VI-NEXT:    v_or_b32_e32 v0, v0, v10
; VI-NEXT:  .LBB64_2: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v20f16_to_v5f64:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB64_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    s_movk_i32 s6, 0x200
; GFX9-NEXT:    v_pk_add_f16 v9, v9, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v8, v8, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
; GFX9-NEXT:  .LBB64_2: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v20f16_to_v5f64:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB64_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    v_pk_add_f16 v9, v9, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v8, v8, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v7, v7, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v6, v6, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v5, v5, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v4, v4, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v3, v3, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v2, v2, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v1, v1, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v0, v0, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:  .LBB64_2: ; %end
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <20 x half> %a, splat (half 0xH0200)
  %a2 = bitcast <20 x half> %a1 to <5 x double>
  br label %end

cmp.false:
  %a3 = bitcast <20 x half> %a to <5 x double>
  br label %end

end:
  %phi = phi <5 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <5 x double> %phi
}

define inreg <5 x double> @bitcast_v20f16_to_v5f64_scalar(<20 x half> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v20f16_to_v5f64_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_lshr_b32 s13, s25, 16
; SI-NEXT:    s_lshr_b32 s12, s24, 16
; SI-NEXT:    s_lshr_b32 s11, s23, 16
; SI-NEXT:    s_lshr_b32 s10, s22, 16
; SI-NEXT:    s_lshr_b32 s9, s21, 16
; SI-NEXT:    s_lshr_b32 s8, s20, 16
; SI-NEXT:    s_lshr_b32 s7, s19, 16
; SI-NEXT:    s_lshr_b32 s6, s18, 16
; SI-NEXT:    s_lshr_b32 s5, s17, 16
; SI-NEXT:    s_lshr_b32 s4, s16, 16
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc0 .LBB65_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    s_and_b32 s14, s16, 0xffff
; SI-NEXT:    s_lshl_b32 s4, s4, 16
; SI-NEXT:    s_or_b32 s4, s14, s4
; SI-NEXT:    s_and_b32 s14, s17, 0xffff
; SI-NEXT:    s_lshl_b32 s5, s5, 16
; SI-NEXT:    s_or_b32 s5, s14, s5
; SI-NEXT:    s_and_b32 s14, s18, 0xffff
; SI-NEXT:    s_lshl_b32 s6, s6, 16
; SI-NEXT:    s_or_b32 s6, s14, s6
; SI-NEXT:    s_and_b32 s14, s19, 0xffff
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_or_b32 s7, s14, s7
; SI-NEXT:    s_and_b32 s14, s20, 0xffff
; SI-NEXT:    s_lshl_b32 s8, s8, 16
; SI-NEXT:    s_or_b32 s8, s14, s8
; SI-NEXT:    s_and_b32 s14, s21, 0xffff
; SI-NEXT:    s_lshl_b32 s9, s9, 16
; SI-NEXT:    s_or_b32 s9, s14, s9
; SI-NEXT:    s_and_b32 s14, s22, 0xffff
; SI-NEXT:    s_lshl_b32 s10, s10, 16
; SI-NEXT:    s_or_b32 s10, s14, s10
; SI-NEXT:    s_and_b32 s14, s23, 0xffff
; SI-NEXT:    s_lshl_b32 s11, s11, 16
; SI-NEXT:    s_or_b32 s11, s14, s11
; SI-NEXT:    s_and_b32 s14, s24, 0xffff
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_or_b32 s12, s14, s12
; SI-NEXT:    s_and_b32 s14, s25, 0xffff
; SI-NEXT:    s_lshl_b32 s13, s13, 16
; SI-NEXT:    s_or_b32 s13, s14, s13
; SI-NEXT:    v_mov_b32_e32 v0, s4
; SI-NEXT:    v_mov_b32_e32 v1, s5
; SI-NEXT:    v_mov_b32_e32 v2, s6
; SI-NEXT:    v_mov_b32_e32 v3, s7
; SI-NEXT:    v_mov_b32_e32 v4, s8
; SI-NEXT:    v_mov_b32_e32 v5, s9
; SI-NEXT:    v_mov_b32_e32 v6, s10
; SI-NEXT:    v_mov_b32_e32 v7, s11
; SI-NEXT:    v_mov_b32_e32 v8, s12
; SI-NEXT:    v_mov_b32_e32 v9, s13
; SI-NEXT:    v_mov_b32_e32 v10, s14
; SI-NEXT:    v_mov_b32_e32 v11, s15
; SI-NEXT:    v_mov_b32_e32 v12, s16
; SI-NEXT:    v_mov_b32_e32 v13, s17
; SI-NEXT:    v_mov_b32_e32 v14, s18
; SI-NEXT:    v_mov_b32_e32 v15, s19
; SI-NEXT:    s_setpc_b64 s[30:31]
; SI-NEXT:  .LBB65_2: ; %cmp.true
; SI-NEXT:    v_cvt_f32_f16_e32 v0, s4
; SI-NEXT:    v_cvt_f32_f16_e32 v1, s16
; SI-NEXT:    v_cvt_f32_f16_e32 v2, s5
; SI-NEXT:    v_cvt_f32_f16_e32 v3, s17
; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1
; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT:    v_cvt_f16_f32_e32 v3, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v4, s6
; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT:    v_or_b32_e32 v0, v1, v0
; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v2
; SI-NEXT:    v_or_b32_e32 v1, v3, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v2, s18
; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v4
; SI-NEXT:    v_cvt_f32_f16_e32 v4, s7
; SI-NEXT:    v_cvt_f16_f32_e32 v3, v3
; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT:    v_cvt_f16_f32_e32 v4, v4
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v5, s19
; SI-NEXT:    v_or_b32_e32 v2, v2, v3
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v4
; SI-NEXT:    v_cvt_f32_f16_e32 v4, s8
; SI-NEXT:    v_cvt_f32_f16_e32 v6, s20
; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT:    v_cvt_f16_f32_e32 v5, v5
; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT:    v_cvt_f16_f32_e32 v4, v4
; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT:    v_cvt_f16_f32_e32 v6, v6
; SI-NEXT:    v_or_b32_e32 v3, v5, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v5, s9
; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT:    v_or_b32_e32 v4, v6, v4
; SI-NEXT:    v_cvt_f32_f16_e32 v6, s21
; SI-NEXT:    v_cvt_f32_f16_e32 v7, s10
; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT:    v_cvt_f16_f32_e32 v5, v5
; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT:    v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT:    v_cvt_f16_f32_e32 v6, v6
; SI-NEXT:    v_cvt_f16_f32_e32 v7, v7
; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT:    v_cvt_f32_f16_e32 v8, s22
; SI-NEXT:    v_or_b32_e32 v5, v6, v5
; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v7
; SI-NEXT:    v_cvt_f32_f16_e32 v7, s11
; SI-NEXT:    v_cvt_f32_f16_e32 v9, s23
; SI-NEXT:    v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT:    v_cvt_f16_f32_e32 v8, v8
; SI-NEXT:    v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT:    v_cvt_f16_f32_e32 v7, v7
; SI-NEXT:    v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT:    v_cvt_f16_f32_e32 v9, v9
; SI-NEXT:    v_or_b32_e32 v6, v8, v6
; SI-NEXT:    v_cvt_f32_f16_e32 v8, s12
; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT:    v_or_b32_e32 v7, v9, v7
; SI-NEXT:    v_cvt_f32_f16_e32 v9, s24
; SI-NEXT:    v_cvt_f32_f16_e32 v10, s13
; SI-NEXT:    v_cvt_f32_f16_e32 v11, s25
; SI-NEXT:    v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT:    v_cvt_f16_f32_e32 v8, v8
; SI-NEXT:    v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT:    v_add_f32_e32 v10, 0x38000000, v10
; SI-NEXT:    v_cvt_f16_f32_e32 v9, v9
; SI-NEXT:    v_cvt_f16_f32_e32 v10, v10
; SI-NEXT:    v_add_f32_e32 v11, 0x38000000, v11
; SI-NEXT:    v_cvt_f16_f32_e32 v11, v11
; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT:    v_or_b32_e32 v8, v9, v8
; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v10
; SI-NEXT:    v_or_b32_e32 v9, v11, v9
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v20f16_to_v5f64_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc0 .LBB65_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s17
; VI-NEXT:    v_mov_b32_e32 v2, s18
; VI-NEXT:    v_mov_b32_e32 v3, s19
; VI-NEXT:    v_mov_b32_e32 v4, s20
; VI-NEXT:    v_mov_b32_e32 v5, s21
; VI-NEXT:    v_mov_b32_e32 v6, s22
; VI-NEXT:    v_mov_b32_e32 v7, s23
; VI-NEXT:    v_mov_b32_e32 v8, s24
; VI-NEXT:    v_mov_b32_e32 v9, s25
; VI-NEXT:    v_mov_b32_e32 v10, s26
; VI-NEXT:    v_mov_b32_e32 v11, s27
; VI-NEXT:    v_mov_b32_e32 v12, s28
; VI-NEXT:    v_mov_b32_e32 v13, s29
; VI-NEXT:    v_mov_b32_e32 v14, s30
; VI-NEXT:    v_mov_b32_e32 v15, s31
; VI-NEXT:    s_setpc_b64 s[30:31]
; VI-NEXT:  .LBB65_2: ; %cmp.true
; VI-NEXT:    s_lshr_b32 s4, s25, 16
; VI-NEXT:    v_mov_b32_e32 v0, 0x200
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, s25, v0
; VI-NEXT:    s_lshr_b32 s4, s24, 16
; VI-NEXT:    v_or_b32_e32 v9, v2, v1
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, s24, v0
; VI-NEXT:    s_lshr_b32 s4, s23, 16
; VI-NEXT:    v_or_b32_e32 v8, v2, v1
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, s23, v0
; VI-NEXT:    s_lshr_b32 s4, s22, 16
; VI-NEXT:    v_or_b32_e32 v7, v2, v1
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, s22, v0
; VI-NEXT:    s_lshr_b32 s4, s21, 16
; VI-NEXT:    v_or_b32_e32 v6, v2, v1
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, s21, v0
; VI-NEXT:    s_lshr_b32 s4, s20, 16
; VI-NEXT:    v_or_b32_e32 v5, v2, v1
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, s20, v0
; VI-NEXT:    s_lshr_b32 s4, s19, 16
; VI-NEXT:    v_or_b32_e32 v4, v2, v1
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, s19, v0
; VI-NEXT:    s_lshr_b32 s4, s18, 16
; VI-NEXT:    v_or_b32_e32 v3, v2, v1
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, s18, v0
; VI-NEXT:    s_lshr_b32 s4, s17, 16
; VI-NEXT:    v_or_b32_e32 v2, v2, v1
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v10, s17, v0
; VI-NEXT:    s_lshr_b32 s4, s16, 16
; VI-NEXT:    v_or_b32_e32 v1, v10, v1
; VI-NEXT:    v_mov_b32_e32 v10, s4
; VI-NEXT:    v_add_f16_sdwa v10, v10, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v0, s16, v0
; VI-NEXT:    v_or_b32_e32 v0, v0, v10
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v20f16_to_v5f64_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc0 .LBB65_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s17
; GFX9-NEXT:    v_mov_b32_e32 v2, s18
; GFX9-NEXT:    v_mov_b32_e32 v3, s19
; GFX9-NEXT:    v_mov_b32_e32 v4, s20
; GFX9-NEXT:    v_mov_b32_e32 v5, s21
; GFX9-NEXT:    v_mov_b32_e32 v6, s22
; GFX9-NEXT:    v_mov_b32_e32 v7, s23
; GFX9-NEXT:    v_mov_b32_e32 v8, s24
; GFX9-NEXT:    v_mov_b32_e32 v9, s25
; GFX9-NEXT:    v_mov_b32_e32 v10, s26
; GFX9-NEXT:    v_mov_b32_e32 v11, s27
; GFX9-NEXT:    v_mov_b32_e32 v12, s28
; GFX9-NEXT:    v_mov_b32_e32 v13, s29
; GFX9-NEXT:    v_mov_b32_e32 v14, s30
; GFX9-NEXT:    v_mov_b32_e32 v15, s31
; GFX9-NEXT:    s_setpc_b64 s[30:31]
; GFX9-NEXT:  .LBB65_2: ; %cmp.true
; GFX9-NEXT:    v_mov_b32_e32 v0, 0x200
; GFX9-NEXT:    v_pk_add_f16 v9, s25, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v8, s24, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v7, s23, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v6, s22, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v5, s21, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v4, s20, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v3, s19, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v20f16_to_v5f64_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s15, s3
; GFX11-NEXT:    s_mov_b32 s14, s2
; GFX11-NEXT:    s_mov_b32 s13, s1
; GFX11-NEXT:    s_mov_b32 s12, s0
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc0 .LBB65_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-NEXT:    v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
; GFX11-NEXT:    v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT:    v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
; GFX11-NEXT:    v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
; GFX11-NEXT:    v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
; GFX11-NEXT:    s_setpc_b64 s[30:31]
; GFX11-NEXT:  .LBB65_2: ; %cmp.true
; GFX11-NEXT:    v_pk_add_f16 v9, s21, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v8, s20, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v7, s19, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v6, s18, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v5, s17, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v4, s16, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v3, s15, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v2, s14, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v1, s13, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v0, s12, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <20 x half> %a, splat (half 0xH0200)
  %a2 = bitcast <20 x half> %a1 to <5 x double>
  br label %end

cmp.false:
  %a3 = bitcast <20 x half> %a to <5 x double>
  br label %end

end:
  %phi = phi <5 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <5 x double> %phi
}

define <20 x half> @bitcast_v5f64_to_v20f16(<5 x double> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v5f64_to_v20f16:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; SI-NEXT:    ; implicit-def: $vgpr16
; SI-NEXT:    ; implicit-def: $vgpr19
; SI-NEXT:    ; implicit-def: $vgpr13
; SI-NEXT:    ; implicit-def: $vgpr18
; SI-NEXT:    ; implicit-def: $vgpr12
; SI-NEXT:    ; implicit-def: $vgpr17
; SI-NEXT:    ; implicit-def: $vgpr11
; SI-NEXT:    ; implicit-def: $vgpr15
; SI-NEXT:    ; implicit-def: $vgpr10
; SI-NEXT:    ; implicit-def: $vgpr14
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB66_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    v_alignbit_b32 v10, v9, v8, 16
; SI-NEXT:    v_alignbit_b32 v11, v7, v6, 16
; SI-NEXT:    v_alignbit_b32 v12, v5, v4, 16
; SI-NEXT:    v_alignbit_b32 v13, v3, v2, 16
; SI-NEXT:    v_alignbit_b32 v16, v1, v0, 16
; SI-NEXT:    v_lshrrev_b32_e32 v14, 16, v9
; SI-NEXT:    v_lshrrev_b32_e32 v15, 16, v7
; SI-NEXT:    v_lshrrev_b32_e32 v17, 16, v5
; SI-NEXT:    v_lshrrev_b32_e32 v18, 16, v3
; SI-NEXT:    v_lshrrev_b32_e32 v19, 16, v1
; SI-NEXT:  .LBB66_2: ; %Flow
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB66_4
; SI-NEXT:  ; %bb.3: ; %cmp.true
; SI-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
; SI-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
; SI-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
; SI-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
; SI-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
; SI-NEXT:    v_alignbit_b32 v10, v9, v8, 16
; SI-NEXT:    v_alignbit_b32 v11, v7, v6, 16
; SI-NEXT:    v_alignbit_b32 v12, v5, v4, 16
; SI-NEXT:    v_alignbit_b32 v13, v3, v2, 16
; SI-NEXT:    v_alignbit_b32 v16, v1, v0, 16
; SI-NEXT:    v_lshrrev_b32_e32 v14, 16, v9
; SI-NEXT:    v_lshrrev_b32_e32 v15, 16, v7
; SI-NEXT:    v_lshrrev_b32_e32 v17, 16, v5
; SI-NEXT:    v_lshrrev_b32_e32 v18, 16, v3
; SI-NEXT:    v_lshrrev_b32_e32 v19, 16, v1
; SI-NEXT:  .LBB66_4: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT:    v_or_b32_e32 v0, v0, v16
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_lshlrev_b32_e32 v16, 16, v19
; SI-NEXT:    v_or_b32_e32 v2, v2, v13
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT:    v_lshlrev_b32_e32 v13, 16, v18
; SI-NEXT:    v_or_b32_e32 v4, v4, v12
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT:    v_lshlrev_b32_e32 v12, 16, v17
; SI-NEXT:    v_or_b32_e32 v6, v6, v11
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT:    v_lshlrev_b32_e32 v11, 16, v15
; SI-NEXT:    v_or_b32_e32 v8, v8, v10
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v14
; SI-NEXT:    v_or_b32_e32 v1, v1, v16
; SI-NEXT:    v_or_b32_e32 v3, v3, v13
; SI-NEXT:    v_or_b32_e32 v5, v5, v12
; SI-NEXT:    v_or_b32_e32 v7, v7, v11
; SI-NEXT:    v_or_b32_e32 v9, v9, v10
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v5f64_to_v20f16:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB66_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
; VI-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
; VI-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
; VI-NEXT:  .LBB66_2: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v5f64_to_v20f16:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB66_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
; GFX9-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
; GFX9-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
; GFX9-NEXT:  .LBB66_2: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v5f64_to_v20f16:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB66_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
; GFX11-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
; GFX11-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
; GFX11-NEXT:  .LBB66_2: ; %end
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <5 x double> %a, splat (double 1.000000e+00)
  %a2 = bitcast <5 x double> %a1 to <20 x half>
  br label %end

cmp.false:
  %a3 = bitcast <5 x double> %a to <20 x half>
  br label %end

end:
  %phi = phi <20 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <20 x half> %phi
}

define inreg <20 x half> @bitcast_v5f64_to_v20f16_scalar(<5 x double> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v5f64_to_v20f16_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc0 .LBB67_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    s_lshr_b32 s14, s25, 16
; SI-NEXT:    s_lshr_b32 s15, s23, 16
; SI-NEXT:    s_lshr_b32 s26, s21, 16
; SI-NEXT:    s_lshr_b32 s27, s19, 16
; SI-NEXT:    s_lshr_b32 s28, s17, 16
; SI-NEXT:    s_lshr_b64 s[4:5], s[24:25], 16
; SI-NEXT:    s_lshr_b64 s[6:7], s[22:23], 16
; SI-NEXT:    s_lshr_b64 s[8:9], s[20:21], 16
; SI-NEXT:    s_lshr_b64 s[10:11], s[18:19], 16
; SI-NEXT:    s_lshr_b64 s[12:13], s[16:17], 16
; SI-NEXT:    v_mov_b32_e32 v9, s25
; SI-NEXT:    v_mov_b32_e32 v7, s23
; SI-NEXT:    v_mov_b32_e32 v5, s21
; SI-NEXT:    v_mov_b32_e32 v3, s19
; SI-NEXT:    v_mov_b32_e32 v1, s17
; SI-NEXT:    v_mov_b32_e32 v0, s16
; SI-NEXT:    v_mov_b32_e32 v2, s18
; SI-NEXT:    v_mov_b32_e32 v4, s20
; SI-NEXT:    v_mov_b32_e32 v6, s22
; SI-NEXT:    v_mov_b32_e32 v8, s24
; SI-NEXT:    v_mov_b32_e32 v16, s14
; SI-NEXT:    v_mov_b32_e32 v17, s15
; SI-NEXT:    v_mov_b32_e32 v18, s26
; SI-NEXT:    v_mov_b32_e32 v19, s27
; SI-NEXT:    v_mov_b32_e32 v20, s28
; SI-NEXT:    v_mov_b32_e32 v14, s12
; SI-NEXT:    v_mov_b32_e32 v13, s10
; SI-NEXT:    v_mov_b32_e32 v12, s8
; SI-NEXT:    v_mov_b32_e32 v11, s6
; SI-NEXT:    v_mov_b32_e32 v10, s4
; SI-NEXT:    s_branch .LBB67_3
; SI-NEXT:  .LBB67_2: ; %cmp.true
; SI-NEXT:    v_add_f64 v[8:9], s[24:25], 1.0
; SI-NEXT:    v_add_f64 v[6:7], s[22:23], 1.0
; SI-NEXT:    v_add_f64 v[4:5], s[20:21], 1.0
; SI-NEXT:    v_lshr_b64 v[10:11], v[8:9], 16
; SI-NEXT:    v_add_f64 v[2:3], s[18:19], 1.0
; SI-NEXT:    v_lshr_b64 v[11:12], v[6:7], 16
; SI-NEXT:    v_add_f64 v[0:1], s[16:17], 1.0
; SI-NEXT:    v_lshr_b64 v[12:13], v[4:5], 16
; SI-NEXT:    v_lshr_b64 v[13:14], v[2:3], 16
; SI-NEXT:    v_lshrrev_b32_e32 v16, 16, v9
; SI-NEXT:    v_lshrrev_b32_e32 v17, 16, v7
; SI-NEXT:    v_lshrrev_b32_e32 v18, 16, v5
; SI-NEXT:    v_lshrrev_b32_e32 v19, 16, v3
; SI-NEXT:    v_lshrrev_b32_e32 v20, 16, v1
; SI-NEXT:    v_lshr_b64 v[14:15], v[0:1], 16
; SI-NEXT:  .LBB67_3: ; %end
; SI-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT:    v_or_b32_e32 v0, v0, v14
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_lshlrev_b32_e32 v14, 16, v20
; SI-NEXT:    v_or_b32_e32 v2, v2, v13
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT:    v_lshlrev_b32_e32 v13, 16, v19
; SI-NEXT:    v_or_b32_e32 v4, v4, v12
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT:    v_lshlrev_b32_e32 v12, 16, v18
; SI-NEXT:    v_or_b32_e32 v6, v6, v11
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT:    v_lshlrev_b32_e32 v11, 16, v17
; SI-NEXT:    v_or_b32_e32 v8, v8, v10
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v16
; SI-NEXT:    v_or_b32_e32 v1, v1, v14
; SI-NEXT:    v_or_b32_e32 v3, v3, v13
; SI-NEXT:    v_or_b32_e32 v5, v5, v12
; SI-NEXT:    v_or_b32_e32 v7, v7, v11
; SI-NEXT:    v_or_b32_e32 v9, v9, v10
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v5f64_to_v20f16_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc0 .LBB67_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s17
; VI-NEXT:    v_mov_b32_e32 v2, s18
; VI-NEXT:    v_mov_b32_e32 v3, s19
; VI-NEXT:    v_mov_b32_e32 v4, s20
; VI-NEXT:    v_mov_b32_e32 v5, s21
; VI-NEXT:    v_mov_b32_e32 v6, s22
; VI-NEXT:    v_mov_b32_e32 v7, s23
; VI-NEXT:    v_mov_b32_e32 v8, s24
; VI-NEXT:    v_mov_b32_e32 v9, s25
; VI-NEXT:    v_mov_b32_e32 v10, s26
; VI-NEXT:    v_mov_b32_e32 v11, s27
; VI-NEXT:    v_mov_b32_e32 v12, s28
; VI-NEXT:    v_mov_b32_e32 v13, s29
; VI-NEXT:    v_mov_b32_e32 v14, s30
; VI-NEXT:    v_mov_b32_e32 v15, s31
; VI-NEXT:    s_setpc_b64 s[30:31]
; VI-NEXT:  .LBB67_2: ; %cmp.true
; VI-NEXT:    v_add_f64 v[8:9], s[24:25], 1.0
; VI-NEXT:    v_add_f64 v[6:7], s[22:23], 1.0
; VI-NEXT:    v_add_f64 v[4:5], s[20:21], 1.0
; VI-NEXT:    v_add_f64 v[2:3], s[18:19], 1.0
; VI-NEXT:    v_add_f64 v[0:1], s[16:17], 1.0
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v5f64_to_v20f16_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc0 .LBB67_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s17
; GFX9-NEXT:    v_mov_b32_e32 v2, s18
; GFX9-NEXT:    v_mov_b32_e32 v3, s19
; GFX9-NEXT:    v_mov_b32_e32 v4, s20
; GFX9-NEXT:    v_mov_b32_e32 v5, s21
; GFX9-NEXT:    v_mov_b32_e32 v6, s22
; GFX9-NEXT:    v_mov_b32_e32 v7, s23
; GFX9-NEXT:    v_mov_b32_e32 v8, s24
; GFX9-NEXT:    v_mov_b32_e32 v9, s25
; GFX9-NEXT:    v_mov_b32_e32 v10, s26
; GFX9-NEXT:    v_mov_b32_e32 v11, s27
; GFX9-NEXT:    v_mov_b32_e32 v12, s28
; GFX9-NEXT:    v_mov_b32_e32 v13, s29
; GFX9-NEXT:    v_mov_b32_e32 v14, s30
; GFX9-NEXT:    v_mov_b32_e32 v15, s31
; GFX9-NEXT:    s_setpc_b64 s[30:31]
; GFX9-NEXT:  .LBB67_2: ; %cmp.true
; GFX9-NEXT:    v_add_f64 v[8:9], s[24:25], 1.0
; GFX9-NEXT:    v_add_f64 v[6:7], s[22:23], 1.0
; GFX9-NEXT:    v_add_f64 v[4:5], s[20:21], 1.0
; GFX9-NEXT:    v_add_f64 v[2:3], s[18:19], 1.0
; GFX9-NEXT:    v_add_f64 v[0:1], s[16:17], 1.0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v5f64_to_v20f16_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s15, s3
; GFX11-NEXT:    s_mov_b32 s14, s2
; GFX11-NEXT:    s_mov_b32 s13, s1
; GFX11-NEXT:    s_mov_b32 s12, s0
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc0 .LBB67_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-NEXT:    v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
; GFX11-NEXT:    v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT:    v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
; GFX11-NEXT:    v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
; GFX11-NEXT:    v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
; GFX11-NEXT:    s_setpc_b64 s[30:31]
; GFX11-NEXT:  .LBB67_2: ; %cmp.true
; GFX11-NEXT:    v_add_f64 v[8:9], s[20:21], 1.0
; GFX11-NEXT:    v_add_f64 v[6:7], s[18:19], 1.0
; GFX11-NEXT:    v_add_f64 v[4:5], s[16:17], 1.0
; GFX11-NEXT:    v_add_f64 v[2:3], s[14:15], 1.0
; GFX11-NEXT:    v_add_f64 v[0:1], s[12:13], 1.0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <5 x double> %a, splat (double 1.000000e+00)
  %a2 = bitcast <5 x double> %a1 to <20 x half>
  br label %end

cmp.false:
  %a3 = bitcast <5 x double> %a to <20 x half>
  br label %end

end:
  %phi = phi <20 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <20 x half> %phi
}

define <5 x i64> @bitcast_v20f16_to_v5i64(<20 x half> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v20f16_to_v5i64:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_mov_b32_e32 v16, v9
; SI-NEXT:    v_mov_b32_e32 v17, v8
; SI-NEXT:    v_mov_b32_e32 v18, v7
; SI-NEXT:    v_mov_b32_e32 v19, v6
; SI-NEXT:    v_mov_b32_e32 v20, v5
; SI-NEXT:    v_mov_b32_e32 v21, v4
; SI-NEXT:    v_mov_b32_e32 v22, v3
; SI-NEXT:    v_mov_b32_e32 v23, v2
; SI-NEXT:    v_mov_b32_e32 v24, v1
; SI-NEXT:    v_mov_b32_e32 v25, v0
; SI-NEXT:    v_lshrrev_b32_e32 v26, 16, v16
; SI-NEXT:    v_lshrrev_b32_e32 v27, 16, v17
; SI-NEXT:    v_lshrrev_b32_e32 v28, 16, v18
; SI-NEXT:    v_lshrrev_b32_e32 v29, 16, v19
; SI-NEXT:    v_lshrrev_b32_e32 v30, 16, v20
; SI-NEXT:    v_lshrrev_b32_e32 v31, 16, v21
; SI-NEXT:    v_lshrrev_b32_e32 v32, 16, v22
; SI-NEXT:    v_lshrrev_b32_e32 v33, 16, v23
; SI-NEXT:    v_lshrrev_b32_e32 v34, 16, v24
; SI-NEXT:    v_lshrrev_b32_e32 v35, 16, v25
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; SI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_cbranch_execnz .LBB68_3
; SI-NEXT:  ; %bb.1: ; %Flow
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execnz .LBB68_4
; SI-NEXT:  .LBB68_2: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    s_setpc_b64 s[30:31]
; SI-NEXT:  .LBB68_3: ; %cmp.false
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v25
; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v35
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v24
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v34
; SI-NEXT:    v_or_b32_e32 v0, v0, v1
; SI-NEXT:    v_or_b32_e32 v1, v2, v3
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v23
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v33
; SI-NEXT:    v_or_b32_e32 v2, v2, v3
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v22
; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v32
; SI-NEXT:    v_or_b32_e32 v3, v3, v4
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v21
; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v31
; SI-NEXT:    v_or_b32_e32 v4, v4, v5
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v20
; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v30
; SI-NEXT:    v_or_b32_e32 v5, v5, v6
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v19
; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v29
; SI-NEXT:    v_or_b32_e32 v6, v6, v7
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v18
; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v28
; SI-NEXT:    v_or_b32_e32 v7, v7, v8
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v17
; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v27
; SI-NEXT:    v_or_b32_e32 v8, v8, v9
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v16
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v26
; SI-NEXT:    v_or_b32_e32 v9, v9, v10
; SI-NEXT:    ; implicit-def: $vgpr25
; SI-NEXT:    ; implicit-def: $vgpr24
; SI-NEXT:    ; implicit-def: $vgpr23
; SI-NEXT:    ; implicit-def: $vgpr22
; SI-NEXT:    ; implicit-def: $vgpr21
; SI-NEXT:    ; implicit-def: $vgpr20
; SI-NEXT:    ; implicit-def: $vgpr19
; SI-NEXT:    ; implicit-def: $vgpr18
; SI-NEXT:    ; implicit-def: $vgpr17
; SI-NEXT:    ; implicit-def: $vgpr16
; SI-NEXT:    ; implicit-def: $vgpr35
; SI-NEXT:    ; implicit-def: $vgpr34
; SI-NEXT:    ; implicit-def: $vgpr33
; SI-NEXT:    ; implicit-def: $vgpr32
; SI-NEXT:    ; implicit-def: $vgpr31
; SI-NEXT:    ; implicit-def: $vgpr30
; SI-NEXT:    ; implicit-def: $vgpr29
; SI-NEXT:    ; implicit-def: $vgpr28
; SI-NEXT:    ; implicit-def: $vgpr27
; SI-NEXT:    ; implicit-def: $vgpr26
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB68_2
; SI-NEXT:  .LBB68_4: ; %cmp.true
; SI-NEXT:    v_cvt_f32_f16_e32 v0, v35
; SI-NEXT:    v_cvt_f32_f16_e32 v2, v34
; SI-NEXT:    v_cvt_f32_f16_e32 v1, v25
; SI-NEXT:    v_cvt_f32_f16_e32 v3, v24
; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1
; SI-NEXT:    v_cvt_f16_f32_e32 v3, v3
; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_or_b32_e32 v0, v1, v0
; SI-NEXT:    v_or_b32_e32 v1, v3, v2
; SI-NEXT:    v_cvt_f32_f16_e32 v2, v33
; SI-NEXT:    v_cvt_f32_f16_e32 v3, v23
; SI-NEXT:    v_cvt_f32_f16_e32 v4, v32
; SI-NEXT:    v_cvt_f32_f16_e32 v5, v22
; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT:    v_cvt_f16_f32_e32 v3, v3
; SI-NEXT:    v_cvt_f16_f32_e32 v4, v4
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_cvt_f32_f16_e32 v6, v21
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v4
; SI-NEXT:    v_cvt_f32_f16_e32 v4, v31
; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT:    v_cvt_f16_f32_e32 v5, v5
; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT:    v_cvt_f16_f32_e32 v4, v4
; SI-NEXT:    v_cvt_f16_f32_e32 v6, v6
; SI-NEXT:    v_or_b32_e32 v3, v5, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v5, v30
; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT:    v_or_b32_e32 v4, v6, v4
; SI-NEXT:    v_cvt_f32_f16_e32 v6, v20
; SI-NEXT:    v_cvt_f32_f16_e32 v7, v29
; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT:    v_cvt_f16_f32_e32 v5, v5
; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT:    v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT:    v_cvt_f16_f32_e32 v6, v6
; SI-NEXT:    v_cvt_f16_f32_e32 v7, v7
; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT:    v_cvt_f32_f16_e32 v8, v19
; SI-NEXT:    v_or_b32_e32 v5, v6, v5
; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v7
; SI-NEXT:    v_cvt_f32_f16_e32 v7, v28
; SI-NEXT:    v_cvt_f32_f16_e32 v9, v18
; SI-NEXT:    v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT:    v_cvt_f16_f32_e32 v8, v8
; SI-NEXT:    v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT:    v_cvt_f16_f32_e32 v7, v7
; SI-NEXT:    v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT:    v_cvt_f16_f32_e32 v9, v9
; SI-NEXT:    v_or_b32_e32 v6, v8, v6
; SI-NEXT:    v_cvt_f32_f16_e32 v8, v27
; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT:    v_or_b32_e32 v7, v9, v7
; SI-NEXT:    v_cvt_f32_f16_e32 v9, v17
; SI-NEXT:    v_cvt_f32_f16_e32 v10, v26
; SI-NEXT:    v_cvt_f32_f16_e32 v11, v16
; SI-NEXT:    v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT:    v_cvt_f16_f32_e32 v8, v8
; SI-NEXT:    v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT:    v_add_f32_e32 v10, 0x38000000, v10
; SI-NEXT:    v_cvt_f16_f32_e32 v9, v9
; SI-NEXT:    v_cvt_f16_f32_e32 v10, v10
; SI-NEXT:    v_add_f32_e32 v11, 0x38000000, v11
; SI-NEXT:    v_cvt_f16_f32_e32 v11, v11
; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT:    v_or_b32_e32 v8, v9, v8
; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v10
; SI-NEXT:    v_or_b32_e32 v9, v11, v9
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v20f16_to_v5i64:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB68_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    v_mov_b32_e32 v10, 0x200
; VI-NEXT:    v_add_f16_sdwa v11, v9, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v9, 0x200, v9
; VI-NEXT:    v_or_b32_e32 v9, v9, v11
; VI-NEXT:    v_add_f16_sdwa v11, v8, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v8, 0x200, v8
; VI-NEXT:    v_or_b32_e32 v8, v8, v11
; VI-NEXT:    v_add_f16_sdwa v11, v7, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v7, 0x200, v7
; VI-NEXT:    v_or_b32_e32 v7, v7, v11
; VI-NEXT:    v_add_f16_sdwa v11, v6, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v6, 0x200, v6
; VI-NEXT:    v_or_b32_e32 v6, v6, v11
; VI-NEXT:    v_add_f16_sdwa v11, v5, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v5, 0x200, v5
; VI-NEXT:    v_or_b32_e32 v5, v5, v11
; VI-NEXT:    v_add_f16_sdwa v11, v4, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v4, 0x200, v4
; VI-NEXT:    v_or_b32_e32 v4, v4, v11
; VI-NEXT:    v_add_f16_sdwa v11, v3, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v3, 0x200, v3
; VI-NEXT:    v_or_b32_e32 v3, v3, v11
; VI-NEXT:    v_add_f16_sdwa v11, v2, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, 0x200, v2
; VI-NEXT:    v_or_b32_e32 v2, v2, v11
; VI-NEXT:    v_add_f16_sdwa v11, v1, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v1, 0x200, v1
; VI-NEXT:    v_add_f16_sdwa v10, v0, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v0, 0x200, v0
; VI-NEXT:    v_or_b32_e32 v1, v1, v11
; VI-NEXT:    v_or_b32_e32 v0, v0, v10
; VI-NEXT:  .LBB68_2: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v20f16_to_v5i64:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB68_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    s_movk_i32 s6, 0x200
; GFX9-NEXT:    v_pk_add_f16 v9, v9, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v8, v8, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
; GFX9-NEXT:  .LBB68_2: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v20f16_to_v5i64:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB68_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    v_pk_add_f16 v9, v9, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v8, v8, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v7, v7, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v6, v6, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v5, v5, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v4, v4, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v3, v3, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v2, v2, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v1, v1, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v0, v0, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:  .LBB68_2: ; %end
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <20 x half> %a, splat (half 0xH0200)
  %a2 = bitcast <20 x half> %a1 to <5 x i64>
  br label %end

cmp.false:
  %a3 = bitcast <20 x half> %a to <5 x i64>
  br label %end

end:
  %phi = phi <5 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <5 x i64> %phi
}

define inreg <5 x i64> @bitcast_v20f16_to_v5i64_scalar(<20 x half> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v20f16_to_v5i64_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_lshr_b32 s13, s25, 16
; SI-NEXT:    s_lshr_b32 s12, s24, 16
; SI-NEXT:    s_lshr_b32 s11, s23, 16
; SI-NEXT:    s_lshr_b32 s10, s22, 16
; SI-NEXT:    s_lshr_b32 s9, s21, 16
; SI-NEXT:    s_lshr_b32 s8, s20, 16
; SI-NEXT:    s_lshr_b32 s7, s19, 16
; SI-NEXT:    s_lshr_b32 s6, s18, 16
; SI-NEXT:    s_lshr_b32 s5, s17, 16
; SI-NEXT:    s_lshr_b32 s4, s16, 16
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc0 .LBB69_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    s_and_b32 s14, s16, 0xffff
; SI-NEXT:    s_lshl_b32 s4, s4, 16
; SI-NEXT:    s_or_b32 s4, s14, s4
; SI-NEXT:    s_and_b32 s14, s17, 0xffff
; SI-NEXT:    s_lshl_b32 s5, s5, 16
; SI-NEXT:    s_or_b32 s5, s14, s5
; SI-NEXT:    s_and_b32 s14, s18, 0xffff
; SI-NEXT:    s_lshl_b32 s6, s6, 16
; SI-NEXT:    s_or_b32 s6, s14, s6
; SI-NEXT:    s_and_b32 s14, s19, 0xffff
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_or_b32 s7, s14, s7
; SI-NEXT:    s_and_b32 s14, s20, 0xffff
; SI-NEXT:    s_lshl_b32 s8, s8, 16
; SI-NEXT:    s_or_b32 s8, s14, s8
; SI-NEXT:    s_and_b32 s14, s21, 0xffff
; SI-NEXT:    s_lshl_b32 s9, s9, 16
; SI-NEXT:    s_or_b32 s9, s14, s9
; SI-NEXT:    s_and_b32 s14, s22, 0xffff
; SI-NEXT:    s_lshl_b32 s10, s10, 16
; SI-NEXT:    s_or_b32 s10, s14, s10
; SI-NEXT:    s_and_b32 s14, s23, 0xffff
; SI-NEXT:    s_lshl_b32 s11, s11, 16
; SI-NEXT:    s_or_b32 s11, s14, s11
; SI-NEXT:    s_and_b32 s14, s24, 0xffff
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_or_b32 s12, s14, s12
; SI-NEXT:    s_and_b32 s14, s25, 0xffff
; SI-NEXT:    s_lshl_b32 s13, s13, 16
; SI-NEXT:    s_or_b32 s13, s14, s13
; SI-NEXT:    v_mov_b32_e32 v0, s4
; SI-NEXT:    v_mov_b32_e32 v1, s5
; SI-NEXT:    v_mov_b32_e32 v2, s6
; SI-NEXT:    v_mov_b32_e32 v3, s7
; SI-NEXT:    v_mov_b32_e32 v4, s8
; SI-NEXT:    v_mov_b32_e32 v5, s9
; SI-NEXT:    v_mov_b32_e32 v6, s10
; SI-NEXT:    v_mov_b32_e32 v7, s11
; SI-NEXT:    v_mov_b32_e32 v8, s12
; SI-NEXT:    v_mov_b32_e32 v9, s13
; SI-NEXT:    v_mov_b32_e32 v10, s14
; SI-NEXT:    v_mov_b32_e32 v11, s15
; SI-NEXT:    v_mov_b32_e32 v12, s16
; SI-NEXT:    v_mov_b32_e32 v13, s17
; SI-NEXT:    v_mov_b32_e32 v14, s18
; SI-NEXT:    v_mov_b32_e32 v15, s19
; SI-NEXT:    s_setpc_b64 s[30:31]
; SI-NEXT:  .LBB69_2: ; %cmp.true
; SI-NEXT:    v_cvt_f32_f16_e32 v0, s4
; SI-NEXT:    v_cvt_f32_f16_e32 v1, s16
; SI-NEXT:    v_cvt_f32_f16_e32 v2, s5
; SI-NEXT:    v_cvt_f32_f16_e32 v3, s17
; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1
; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT:    v_cvt_f16_f32_e32 v3, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v4, s6
; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT:    v_or_b32_e32 v0, v1, v0
; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v2
; SI-NEXT:    v_or_b32_e32 v1, v3, v1
; SI-NEXT:    v_cvt_f32_f16_e32 v2, s18
; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v4
; SI-NEXT:    v_cvt_f32_f16_e32 v4, s7
; SI-NEXT:    v_cvt_f16_f32_e32 v3, v3
; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT:    v_cvt_f16_f32_e32 v4, v4
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v5, s19
; SI-NEXT:    v_or_b32_e32 v2, v2, v3
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v4
; SI-NEXT:    v_cvt_f32_f16_e32 v4, s8
; SI-NEXT:    v_cvt_f32_f16_e32 v6, s20
; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT:    v_cvt_f16_f32_e32 v5, v5
; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT:    v_cvt_f16_f32_e32 v4, v4
; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT:    v_cvt_f16_f32_e32 v6, v6
; SI-NEXT:    v_or_b32_e32 v3, v5, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v5, s9
; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT:    v_or_b32_e32 v4, v6, v4
; SI-NEXT:    v_cvt_f32_f16_e32 v6, s21
; SI-NEXT:    v_cvt_f32_f16_e32 v7, s10
; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT:    v_cvt_f16_f32_e32 v5, v5
; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT:    v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT:    v_cvt_f16_f32_e32 v6, v6
; SI-NEXT:    v_cvt_f16_f32_e32 v7, v7
; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT:    v_cvt_f32_f16_e32 v8, s22
; SI-NEXT:    v_or_b32_e32 v5, v6, v5
; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v7
; SI-NEXT:    v_cvt_f32_f16_e32 v7, s11
; SI-NEXT:    v_cvt_f32_f16_e32 v9, s23
; SI-NEXT:    v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT:    v_cvt_f16_f32_e32 v8, v8
; SI-NEXT:    v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT:    v_cvt_f16_f32_e32 v7, v7
; SI-NEXT:    v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT:    v_cvt_f16_f32_e32 v9, v9
; SI-NEXT:    v_or_b32_e32 v6, v8, v6
; SI-NEXT:    v_cvt_f32_f16_e32 v8, s12
; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT:    v_or_b32_e32 v7, v9, v7
; SI-NEXT:    v_cvt_f32_f16_e32 v9, s24
; SI-NEXT:    v_cvt_f32_f16_e32 v10, s13
; SI-NEXT:    v_cvt_f32_f16_e32 v11, s25
; SI-NEXT:    v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT:    v_cvt_f16_f32_e32 v8, v8
; SI-NEXT:    v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT:    v_add_f32_e32 v10, 0x38000000, v10
; SI-NEXT:    v_cvt_f16_f32_e32 v9, v9
; SI-NEXT:    v_cvt_f16_f32_e32 v10, v10
; SI-NEXT:    v_add_f32_e32 v11, 0x38000000, v11
; SI-NEXT:    v_cvt_f16_f32_e32 v11, v11
; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT:    v_or_b32_e32 v8, v9, v8
; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v10
; SI-NEXT:    v_or_b32_e32 v9, v11, v9
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v20f16_to_v5i64_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc0 .LBB69_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s17
; VI-NEXT:    v_mov_b32_e32 v2, s18
; VI-NEXT:    v_mov_b32_e32 v3, s19
; VI-NEXT:    v_mov_b32_e32 v4, s20
; VI-NEXT:    v_mov_b32_e32 v5, s21
; VI-NEXT:    v_mov_b32_e32 v6, s22
; VI-NEXT:    v_mov_b32_e32 v7, s23
; VI-NEXT:    v_mov_b32_e32 v8, s24
; VI-NEXT:    v_mov_b32_e32 v9, s25
; VI-NEXT:    v_mov_b32_e32 v10, s26
; VI-NEXT:    v_mov_b32_e32 v11, s27
; VI-NEXT:    v_mov_b32_e32 v12, s28
; VI-NEXT:    v_mov_b32_e32 v13, s29
; VI-NEXT:    v_mov_b32_e32 v14, s30
; VI-NEXT:    v_mov_b32_e32 v15, s31
; VI-NEXT:    s_setpc_b64 s[30:31]
; VI-NEXT:  .LBB69_2: ; %cmp.true
; VI-NEXT:    s_lshr_b32 s4, s25, 16
; VI-NEXT:    v_mov_b32_e32 v0, 0x200
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, s25, v0
; VI-NEXT:    s_lshr_b32 s4, s24, 16
; VI-NEXT:    v_or_b32_e32 v9, v2, v1
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, s24, v0
; VI-NEXT:    s_lshr_b32 s4, s23, 16
; VI-NEXT:    v_or_b32_e32 v8, v2, v1
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, s23, v0
; VI-NEXT:    s_lshr_b32 s4, s22, 16
; VI-NEXT:    v_or_b32_e32 v7, v2, v1
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, s22, v0
; VI-NEXT:    s_lshr_b32 s4, s21, 16
; VI-NEXT:    v_or_b32_e32 v6, v2, v1
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, s21, v0
; VI-NEXT:    s_lshr_b32 s4, s20, 16
; VI-NEXT:    v_or_b32_e32 v5, v2, v1
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, s20, v0
; VI-NEXT:    s_lshr_b32 s4, s19, 16
; VI-NEXT:    v_or_b32_e32 v4, v2, v1
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, s19, v0
; VI-NEXT:    s_lshr_b32 s4, s18, 16
; VI-NEXT:    v_or_b32_e32 v3, v2, v1
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v2, s18, v0
; VI-NEXT:    s_lshr_b32 s4, s17, 16
; VI-NEXT:    v_or_b32_e32 v2, v2, v1
; VI-NEXT:    v_mov_b32_e32 v1, s4
; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v10, s17, v0
; VI-NEXT:    s_lshr_b32 s4, s16, 16
; VI-NEXT:    v_or_b32_e32 v1, v10, v1
; VI-NEXT:    v_mov_b32_e32 v10, s4
; VI-NEXT:    v_add_f16_sdwa v10, v10, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_add_f16_e32 v0, s16, v0
; VI-NEXT:    v_or_b32_e32 v0, v0, v10
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v20f16_to_v5i64_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc0 .LBB69_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s17
; GFX9-NEXT:    v_mov_b32_e32 v2, s18
; GFX9-NEXT:    v_mov_b32_e32 v3, s19
; GFX9-NEXT:    v_mov_b32_e32 v4, s20
; GFX9-NEXT:    v_mov_b32_e32 v5, s21
; GFX9-NEXT:    v_mov_b32_e32 v6, s22
; GFX9-NEXT:    v_mov_b32_e32 v7, s23
; GFX9-NEXT:    v_mov_b32_e32 v8, s24
; GFX9-NEXT:    v_mov_b32_e32 v9, s25
; GFX9-NEXT:    v_mov_b32_e32 v10, s26
; GFX9-NEXT:    v_mov_b32_e32 v11, s27
; GFX9-NEXT:    v_mov_b32_e32 v12, s28
; GFX9-NEXT:    v_mov_b32_e32 v13, s29
; GFX9-NEXT:    v_mov_b32_e32 v14, s30
; GFX9-NEXT:    v_mov_b32_e32 v15, s31
; GFX9-NEXT:    s_setpc_b64 s[30:31]
; GFX9-NEXT:  .LBB69_2: ; %cmp.true
; GFX9-NEXT:    v_mov_b32_e32 v0, 0x200
; GFX9-NEXT:    v_pk_add_f16 v9, s25, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v8, s24, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v7, s23, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v6, s22, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v5, s21, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v4, s20, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v3, s19, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v20f16_to_v5i64_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s15, s3
; GFX11-NEXT:    s_mov_b32 s14, s2
; GFX11-NEXT:    s_mov_b32 s13, s1
; GFX11-NEXT:    s_mov_b32 s12, s0
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc0 .LBB69_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-NEXT:    v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
; GFX11-NEXT:    v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT:    v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
; GFX11-NEXT:    v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
; GFX11-NEXT:    v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
; GFX11-NEXT:    s_setpc_b64 s[30:31]
; GFX11-NEXT:  .LBB69_2: ; %cmp.true
; GFX11-NEXT:    v_pk_add_f16 v9, s21, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v8, s20, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v7, s19, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v6, s18, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v5, s17, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v4, s16, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v3, s15, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v2, s14, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v1, s13, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    v_pk_add_f16 v0, s12, 0x200 op_sel_hi:[1,0]
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <20 x half> %a, splat (half 0xH0200)
  %a2 = bitcast <20 x half> %a1 to <5 x i64>
  br label %end

cmp.false:
  %a3 = bitcast <20 x half> %a to <5 x i64>
  br label %end

end:
  %phi = phi <5 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <5 x i64> %phi
}

define <20 x half> @bitcast_v5i64_to_v20f16(<5 x i64> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v5i64_to_v20f16:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; SI-NEXT:    ; implicit-def: $vgpr16
; SI-NEXT:    ; implicit-def: $vgpr19
; SI-NEXT:    ; implicit-def: $vgpr13
; SI-NEXT:    ; implicit-def: $vgpr18
; SI-NEXT:    ; implicit-def: $vgpr12
; SI-NEXT:    ; implicit-def: $vgpr17
; SI-NEXT:    ; implicit-def: $vgpr11
; SI-NEXT:    ; implicit-def: $vgpr15
; SI-NEXT:    ; implicit-def: $vgpr10
; SI-NEXT:    ; implicit-def: $vgpr14
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB70_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    v_alignbit_b32 v10, v9, v8, 16
; SI-NEXT:    v_alignbit_b32 v11, v7, v6, 16
; SI-NEXT:    v_alignbit_b32 v12, v5, v4, 16
; SI-NEXT:    v_alignbit_b32 v13, v3, v2, 16
; SI-NEXT:    v_alignbit_b32 v16, v1, v0, 16
; SI-NEXT:    v_lshrrev_b32_e32 v14, 16, v9
; SI-NEXT:    v_lshrrev_b32_e32 v15, 16, v7
; SI-NEXT:    v_lshrrev_b32_e32 v17, 16, v5
; SI-NEXT:    v_lshrrev_b32_e32 v18, 16, v3
; SI-NEXT:    v_lshrrev_b32_e32 v19, 16, v1
; SI-NEXT:  .LBB70_2: ; %Flow
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB70_4
; SI-NEXT:  ; %bb.3: ; %cmp.true
; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
; SI-NEXT:    v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
; SI-NEXT:    v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
; SI-NEXT:    v_alignbit_b32 v10, v9, v8, 16
; SI-NEXT:    v_alignbit_b32 v11, v7, v6, 16
; SI-NEXT:    v_alignbit_b32 v12, v5, v4, 16
; SI-NEXT:    v_alignbit_b32 v13, v3, v2, 16
; SI-NEXT:    v_alignbit_b32 v16, v1, v0, 16
; SI-NEXT:    v_lshrrev_b32_e32 v14, 16, v9
; SI-NEXT:    v_lshrrev_b32_e32 v15, 16, v7
; SI-NEXT:    v_lshrrev_b32_e32 v17, 16, v5
; SI-NEXT:    v_lshrrev_b32_e32 v18, 16, v3
; SI-NEXT:    v_lshrrev_b32_e32 v19, 16, v1
; SI-NEXT:  .LBB70_4: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT:    v_or_b32_e32 v0, v0, v16
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_lshlrev_b32_e32 v16, 16, v19
; SI-NEXT:    v_or_b32_e32 v2, v2, v13
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT:    v_lshlrev_b32_e32 v13, 16, v18
; SI-NEXT:    v_or_b32_e32 v4, v4, v12
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT:    v_lshlrev_b32_e32 v12, 16, v17
; SI-NEXT:    v_or_b32_e32 v6, v6, v11
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT:    v_lshlrev_b32_e32 v11, 16, v15
; SI-NEXT:    v_or_b32_e32 v8, v8, v10
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v14
; SI-NEXT:    v_or_b32_e32 v1, v1, v16
; SI-NEXT:    v_or_b32_e32 v3, v3, v13
; SI-NEXT:    v_or_b32_e32 v5, v5, v12
; SI-NEXT:    v_or_b32_e32 v7, v7, v11
; SI-NEXT:    v_or_b32_e32 v9, v9, v10
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v5i64_to_v20f16:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB70_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    v_add_u32_e32 v8, vcc, 3, v8
; VI-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
; VI-NEXT:    v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
; VI-NEXT:    v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT:    v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT:  .LBB70_2: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v5i64_to_v20f16:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB70_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, 3, v8
; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v9, vcc
; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, 3, v6
; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, 3, v4
; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, 3, v2
; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT:  .LBB70_2: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v5i64_to_v20f16:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB70_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    v_add_co_u32 v8, vcc_lo, v8, 3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo
; GFX11-NEXT:    v_add_co_u32 v6, vcc_lo, v6, 3
; GFX11-NEXT:    v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo
; GFX11-NEXT:    v_add_co_u32 v4, vcc_lo, v4, 3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
; GFX11-NEXT:    v_add_co_u32 v2, vcc_lo, v2, 3
; GFX11-NEXT:    v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX11-NEXT:  .LBB70_2: ; %end
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <5 x i64> %a, splat (i64 3)
  %a2 = bitcast <5 x i64> %a1 to <20 x half>
  br label %end

cmp.false:
  %a3 = bitcast <5 x i64> %a to <20 x half>
  br label %end

end:
  %phi = phi <20 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <20 x half> %phi
}

define inreg <20 x half> @bitcast_v5i64_to_v20f16_scalar(<5 x i64> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v5i64_to_v20f16_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc1 .LBB71_2
; SI-NEXT:  ; %bb.1: ; %cmp.true
; SI-NEXT:    s_add_u32 s24, s24, 3
; SI-NEXT:    s_addc_u32 s25, s25, 0
; SI-NEXT:    s_add_u32 s22, s22, 3
; SI-NEXT:    s_addc_u32 s23, s23, 0
; SI-NEXT:    s_add_u32 s20, s20, 3
; SI-NEXT:    s_addc_u32 s21, s21, 0
; SI-NEXT:    s_add_u32 s18, s18, 3
; SI-NEXT:    s_addc_u32 s19, s19, 0
; SI-NEXT:    s_add_u32 s16, s16, 3
; SI-NEXT:    s_addc_u32 s17, s17, 0
; SI-NEXT:  .LBB71_2: ; %cmp.false
; SI-NEXT:    s_lshr_b64 s[4:5], s[24:25], 16
; SI-NEXT:    s_lshr_b64 s[6:7], s[22:23], 16
; SI-NEXT:    s_lshr_b64 s[12:13], s[16:17], 16
; SI-NEXT:    s_lshr_b32 s28, s17, 16
; SI-NEXT:    s_lshr_b64 s[8:9], s[20:21], 16
; SI-NEXT:    s_and_b32 s5, s16, 0xffff
; SI-NEXT:    s_lshl_b32 s7, s12, 16
; SI-NEXT:    s_lshr_b64 s[10:11], s[18:19], 16
; SI-NEXT:    s_or_b32 s5, s5, s7
; SI-NEXT:    s_and_b32 s7, s17, 0xffff
; SI-NEXT:    s_lshl_b32 s9, s28, 16
; SI-NEXT:    s_lshr_b32 s27, s19, 16
; SI-NEXT:    s_or_b32 s7, s7, s9
; SI-NEXT:    s_and_b32 s9, s18, 0xffff
; SI-NEXT:    s_lshl_b32 s10, s10, 16
; SI-NEXT:    s_or_b32 s9, s9, s10
; SI-NEXT:    s_and_b32 s10, s19, 0xffff
; SI-NEXT:    s_lshl_b32 s11, s27, 16
; SI-NEXT:    s_lshr_b32 s26, s21, 16
; SI-NEXT:    s_or_b32 s10, s10, s11
; SI-NEXT:    s_and_b32 s11, s20, 0xffff
; SI-NEXT:    s_lshl_b32 s8, s8, 16
; SI-NEXT:    s_or_b32 s8, s11, s8
; SI-NEXT:    s_and_b32 s11, s21, 0xffff
; SI-NEXT:    s_lshl_b32 s12, s26, 16
; SI-NEXT:    s_lshr_b32 s15, s23, 16
; SI-NEXT:    s_or_b32 s11, s11, s12
; SI-NEXT:    s_and_b32 s12, s22, 0xffff
; SI-NEXT:    s_lshl_b32 s6, s6, 16
; SI-NEXT:    s_or_b32 s6, s12, s6
; SI-NEXT:    s_and_b32 s12, s23, 0xffff
; SI-NEXT:    s_lshl_b32 s13, s15, 16
; SI-NEXT:    s_lshr_b32 s14, s25, 16
; SI-NEXT:    s_or_b32 s12, s12, s13
; SI-NEXT:    s_and_b32 s13, s24, 0xffff
; SI-NEXT:    s_lshl_b32 s4, s4, 16
; SI-NEXT:    s_or_b32 s4, s13, s4
; SI-NEXT:    s_and_b32 s13, s25, 0xffff
; SI-NEXT:    s_lshl_b32 s14, s14, 16
; SI-NEXT:    s_or_b32 s13, s13, s14
; SI-NEXT:    v_mov_b32_e32 v0, s5
; SI-NEXT:    v_mov_b32_e32 v1, s7
; SI-NEXT:    v_mov_b32_e32 v2, s9
; SI-NEXT:    v_mov_b32_e32 v3, s10
; SI-NEXT:    v_mov_b32_e32 v4, s8
; SI-NEXT:    v_mov_b32_e32 v5, s11
; SI-NEXT:    v_mov_b32_e32 v6, s6
; SI-NEXT:    v_mov_b32_e32 v7, s12
; SI-NEXT:    v_mov_b32_e32 v8, s4
; SI-NEXT:    v_mov_b32_e32 v9, s13
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v5i64_to_v20f16_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc1 .LBB71_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    s_add_u32 s24, s24, 3
; VI-NEXT:    s_addc_u32 s25, s25, 0
; VI-NEXT:    s_add_u32 s22, s22, 3
; VI-NEXT:    s_addc_u32 s23, s23, 0
; VI-NEXT:    s_add_u32 s20, s20, 3
; VI-NEXT:    s_addc_u32 s21, s21, 0
; VI-NEXT:    s_add_u32 s18, s18, 3
; VI-NEXT:    s_addc_u32 s19, s19, 0
; VI-NEXT:    s_add_u32 s16, s16, 3
; VI-NEXT:    s_addc_u32 s17, s17, 0
; VI-NEXT:  .LBB71_2: ; %end
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s17
; VI-NEXT:    v_mov_b32_e32 v2, s18
; VI-NEXT:    v_mov_b32_e32 v3, s19
; VI-NEXT:    v_mov_b32_e32 v4, s20
; VI-NEXT:    v_mov_b32_e32 v5, s21
; VI-NEXT:    v_mov_b32_e32 v6, s22
; VI-NEXT:    v_mov_b32_e32 v7, s23
; VI-NEXT:    v_mov_b32_e32 v8, s24
; VI-NEXT:    v_mov_b32_e32 v9, s25
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v5i64_to_v20f16_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc1 .LBB71_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    s_add_u32 s24, s24, 3
; GFX9-NEXT:    s_addc_u32 s25, s25, 0
; GFX9-NEXT:    s_add_u32 s22, s22, 3
; GFX9-NEXT:    s_addc_u32 s23, s23, 0
; GFX9-NEXT:    s_add_u32 s20, s20, 3
; GFX9-NEXT:    s_addc_u32 s21, s21, 0
; GFX9-NEXT:    s_add_u32 s18, s18, 3
; GFX9-NEXT:    s_addc_u32 s19, s19, 0
; GFX9-NEXT:    s_add_u32 s16, s16, 3
; GFX9-NEXT:    s_addc_u32 s17, s17, 0
; GFX9-NEXT:  .LBB71_2: ; %end
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s17
; GFX9-NEXT:    v_mov_b32_e32 v2, s18
; GFX9-NEXT:    v_mov_b32_e32 v3, s19
; GFX9-NEXT:    v_mov_b32_e32 v4, s20
; GFX9-NEXT:    v_mov_b32_e32 v5, s21
; GFX9-NEXT:    v_mov_b32_e32 v6, s22
; GFX9-NEXT:    v_mov_b32_e32 v7, s23
; GFX9-NEXT:    v_mov_b32_e32 v8, s24
; GFX9-NEXT:    v_mov_b32_e32 v9, s25
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v5i64_to_v20f16_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc1 .LBB71_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    s_add_u32 s20, s20, 3
; GFX11-NEXT:    s_addc_u32 s21, s21, 0
; GFX11-NEXT:    s_add_u32 s18, s18, 3
; GFX11-NEXT:    s_addc_u32 s19, s19, 0
; GFX11-NEXT:    s_add_u32 s16, s16, 3
; GFX11-NEXT:    s_addc_u32 s17, s17, 0
; GFX11-NEXT:    s_add_u32 s2, s2, 3
; GFX11-NEXT:    s_addc_u32 s3, s3, 0
; GFX11-NEXT:    s_add_u32 s0, s0, 3
; GFX11-NEXT:    s_addc_u32 s1, s1, 0
; GFX11-NEXT:  .LBB71_2: ; %end
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <5 x i64> %a, splat (i64 3)
  %a2 = bitcast <5 x i64> %a1 to <20 x half>
  br label %end

cmp.false:
  %a3 = bitcast <5 x i64> %a to <20 x half>
  br label %end

end:
  %phi = phi <20 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <20 x half> %phi
}

define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v40i8_to_v5f64:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    buffer_store_dword v40, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v41, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v42, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v43, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v44, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v45, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v46, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v47, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v56, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; SI-NEXT:    v_mov_b32_e32 v36, v10
; SI-NEXT:    v_mov_b32_e32 v35, v8
; SI-NEXT:    v_mov_b32_e32 v34, v6
; SI-NEXT:    v_mov_b32_e32 v33, v4
; SI-NEXT:    v_mov_b32_e32 v32, v2
; SI-NEXT:    v_mov_b32_e32 v31, v0
; SI-NEXT:    buffer_load_dword v0, off, s[0:3], s32
; SI-NEXT:    buffer_load_dword v2, off, s[0:3], s32 offset:36
; SI-NEXT:    buffer_load_dword v4, off, s[0:3], s32 offset:32
; SI-NEXT:    buffer_load_dword v39, off, s[0:3], s32 offset:28
; SI-NEXT:    buffer_load_dword v6, off, s[0:3], s32 offset:24
; SI-NEXT:    buffer_load_dword v8, off, s[0:3], s32 offset:8
; SI-NEXT:    buffer_load_dword v10, off, s[0:3], s32 offset:16
; SI-NEXT:    buffer_load_dword v48, off, s[0:3], s32 offset:20
; SI-NEXT:    buffer_load_dword v49, off, s[0:3], s32 offset:12
; SI-NEXT:    buffer_load_dword v50, off, s[0:3], s32 offset:4
; SI-NEXT:    v_mov_b32_e32 v38, v14
; SI-NEXT:    v_mov_b32_e32 v37, v12
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_lshlrev_b32_e32 v56, 8, v1
; SI-NEXT:    v_lshlrev_b32_e32 v47, 24, v3
; SI-NEXT:    v_lshlrev_b32_e32 v46, 8, v5
; SI-NEXT:    v_lshlrev_b32_e32 v45, 24, v7
; SI-NEXT:    v_lshlrev_b32_e32 v44, 8, v9
; SI-NEXT:    v_lshlrev_b32_e32 v43, 24, v11
; SI-NEXT:    v_lshlrev_b32_e32 v42, 8, v13
; SI-NEXT:    v_lshlrev_b32_e32 v41, 24, v15
; SI-NEXT:    v_lshlrev_b32_e32 v40, 8, v17
; SI-NEXT:    v_lshlrev_b32_e32 v55, 24, v19
; SI-NEXT:    v_lshlrev_b32_e32 v54, 8, v21
; SI-NEXT:    v_lshlrev_b32_e32 v53, 24, v23
; SI-NEXT:    v_lshlrev_b32_e32 v52, 8, v25
; SI-NEXT:    v_lshlrev_b32_e32 v51, 24, v27
; SI-NEXT:    v_lshlrev_b32_e32 v27, 8, v29
; SI-NEXT:    s_waitcnt vmcnt(9)
; SI-NEXT:    v_lshlrev_b32_e32 v25, 24, v0
; SI-NEXT:    s_waitcnt vmcnt(8)
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
; SI-NEXT:    s_waitcnt vmcnt(7)
; SI-NEXT:    v_lshlrev_b32_e32 v17, 24, v4
; SI-NEXT:    s_waitcnt vmcnt(5)
; SI-NEXT:    v_lshlrev_b32_e32 v19, 8, v6
; SI-NEXT:    s_waitcnt vmcnt(4)
; SI-NEXT:    v_lshlrev_b32_e32 v23, 8, v8
; SI-NEXT:    s_waitcnt vmcnt(3)
; SI-NEXT:    v_lshlrev_b32_e32 v21, 24, v10
; SI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB72_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    v_and_b32_e32 v0, 0xff, v31
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v32
; SI-NEXT:    v_or_b32_e32 v0, v0, v56
; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_or_b32_e32 v1, v47, v1
; SI-NEXT:    v_or_b32_e32 v0, v0, v1
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v33
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v34
; SI-NEXT:    v_or_b32_e32 v1, v1, v46
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v45, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v35
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v36
; SI-NEXT:    v_or_b32_e32 v2, v2, v44
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    v_or_b32_e32 v3, v43, v3
; SI-NEXT:    v_or_b32_e32 v2, v2, v3
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v37
; SI-NEXT:    v_and_b32_e32 v4, 0xff, v38
; SI-NEXT:    v_or_b32_e32 v3, v3, v42
; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT:    v_or_b32_e32 v4, v41, v4
; SI-NEXT:    v_or_b32_e32 v3, v3, v4
; SI-NEXT:    v_and_b32_e32 v4, 0xff, v16
; SI-NEXT:    v_and_b32_e32 v5, 0xff, v18
; SI-NEXT:    v_or_b32_e32 v4, v4, v40
; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT:    v_or_b32_e32 v5, v55, v5
; SI-NEXT:    v_or_b32_e32 v4, v4, v5
; SI-NEXT:    v_and_b32_e32 v5, 0xff, v20
; SI-NEXT:    v_and_b32_e32 v6, 0xff, v22
; SI-NEXT:    v_or_b32_e32 v5, v5, v54
; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT:    v_or_b32_e32 v6, v53, v6
; SI-NEXT:    v_or_b32_e32 v5, v5, v6
; SI-NEXT:    v_and_b32_e32 v6, 0xff, v24
; SI-NEXT:    v_and_b32_e32 v7, 0xff, v26
; SI-NEXT:    v_or_b32_e32 v6, v6, v52
; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT:    v_or_b32_e32 v7, v51, v7
; SI-NEXT:    v_or_b32_e32 v6, v6, v7
; SI-NEXT:    v_and_b32_e32 v7, 0xff, v28
; SI-NEXT:    v_and_b32_e32 v8, 0xff, v30
; SI-NEXT:    v_or_b32_e32 v7, v7, v27
; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT:    v_or_b32_e32 v8, v25, v8
; SI-NEXT:    v_or_b32_e32 v7, v7, v8
; SI-NEXT:    s_waitcnt vmcnt(0)
; SI-NEXT:    v_and_b32_e32 v8, 0xff, v50
; SI-NEXT:    v_and_b32_e32 v9, 0xff, v49
; SI-NEXT:    v_or_b32_e32 v8, v8, v23
; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT:    v_or_b32_e32 v9, v21, v9
; SI-NEXT:    v_or_b32_e32 v8, v8, v9
; SI-NEXT:    v_and_b32_e32 v9, 0xff, v48
; SI-NEXT:    v_and_b32_e32 v10, 0xff, v39
; SI-NEXT:    v_or_b32_e32 v9, v9, v19
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT:    v_or_b32_e32 v10, v17, v10
; SI-NEXT:    v_or_b32_e32 v9, v9, v10
; SI-NEXT:    ; implicit-def: $vgpr31
; SI-NEXT:    ; implicit-def: $vgpr32
; SI-NEXT:    ; implicit-def: $vgpr33
; SI-NEXT:    ; implicit-def: $vgpr34
; SI-NEXT:    ; implicit-def: $vgpr35
; SI-NEXT:    ; implicit-def: $vgpr36
; SI-NEXT:    ; implicit-def: $vgpr37
; SI-NEXT:    ; implicit-def: $vgpr38
; SI-NEXT:    ; implicit-def: $vgpr16
; SI-NEXT:    ; implicit-def: $vgpr18
; SI-NEXT:    ; implicit-def: $vgpr20
; SI-NEXT:    ; implicit-def: $vgpr22
; SI-NEXT:    ; implicit-def: $vgpr24
; SI-NEXT:    ; implicit-def: $vgpr26
; SI-NEXT:    ; implicit-def: $vgpr28
; SI-NEXT:    ; implicit-def: $vgpr30
; SI-NEXT:    ; implicit-def: $vgpr50
; SI-NEXT:    ; implicit-def: $vgpr49
; SI-NEXT:    ; implicit-def: $vgpr48
; SI-NEXT:    ; implicit-def: $vgpr39
; SI-NEXT:    ; implicit-def: $vgpr56
; SI-NEXT:    ; implicit-def: $vgpr47
; SI-NEXT:    ; implicit-def: $vgpr46
; SI-NEXT:    ; implicit-def: $vgpr45
; SI-NEXT:    ; implicit-def: $vgpr44
; SI-NEXT:    ; implicit-def: $vgpr43
; SI-NEXT:    ; implicit-def: $vgpr42
; SI-NEXT:    ; implicit-def: $vgpr41
; SI-NEXT:    ; implicit-def: $vgpr40
; SI-NEXT:    ; implicit-def: $vgpr55
; SI-NEXT:    ; implicit-def: $vgpr54
; SI-NEXT:    ; implicit-def: $vgpr53
; SI-NEXT:    ; implicit-def: $vgpr52
; SI-NEXT:    ; implicit-def: $vgpr51
; SI-NEXT:    ; implicit-def: $vgpr27
; SI-NEXT:    ; implicit-def: $vgpr25
; SI-NEXT:    ; implicit-def: $vgpr23
; SI-NEXT:    ; implicit-def: $vgpr21
; SI-NEXT:    ; implicit-def: $vgpr19
; SI-NEXT:    ; implicit-def: $vgpr17
; SI-NEXT:  .LBB72_2: ; %Flow
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB72_4
; SI-NEXT:  ; %bb.3: ; %cmp.true
; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v31
; SI-NEXT:    v_and_b32_e32 v0, 0xff, v0
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v32
; SI-NEXT:    v_or_b32_e32 v0, v56, v0
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1
; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x300, v0
; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_or_b32_e32 v1, v47, v1
; SI-NEXT:    v_or_b32_e32 v0, v1, v0
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v33
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1
; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v34
; SI-NEXT:    s_movk_i32 s6, 0x300
; SI-NEXT:    v_or_b32_e32 v1, v46, v1
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v2
; SI-NEXT:    v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v45, v2
; SI-NEXT:    v_or_b32_e32 v1, v2, v1
; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v35
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v2
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v36
; SI-NEXT:    v_or_b32_e32 v2, v44, v2
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v3
; SI-NEXT:    v_add_i32_e32 v2, vcc, s6, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    v_or_b32_e32 v3, v43, v3
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v37
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v3
; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v38
; SI-NEXT:    v_or_b32_e32 v3, v42, v3
; SI-NEXT:    v_and_b32_e32 v4, 0xff, v4
; SI-NEXT:    v_add_i32_e32 v3, vcc, s6, v3
; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT:    v_or_b32_e32 v4, v41, v4
; SI-NEXT:    v_or_b32_e32 v3, v4, v3
; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v16
; SI-NEXT:    v_and_b32_e32 v4, 0xff, v4
; SI-NEXT:    v_add_i32_e32 v5, vcc, 3, v18
; SI-NEXT:    v_or_b32_e32 v4, v40, v4
; SI-NEXT:    v_and_b32_e32 v5, 0xff, v5
; SI-NEXT:    v_add_i32_e32 v4, vcc, s6, v4
; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT:    v_or_b32_e32 v5, v55, v5
; SI-NEXT:    v_or_b32_e32 v4, v5, v4
; SI-NEXT:    v_add_i32_e32 v5, vcc, 3, v20
; SI-NEXT:    v_and_b32_e32 v5, 0xff, v5
; SI-NEXT:    v_add_i32_e32 v6, vcc, 3, v22
; SI-NEXT:    v_or_b32_e32 v5, v54, v5
; SI-NEXT:    v_and_b32_e32 v6, 0xff, v6
; SI-NEXT:    v_add_i32_e32 v5, vcc, s6, v5
; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT:    v_or_b32_e32 v6, v53, v6
; SI-NEXT:    v_or_b32_e32 v5, v6, v5
; SI-NEXT:    v_add_i32_e32 v6, vcc, 3, v24
; SI-NEXT:    v_and_b32_e32 v6, 0xff, v6
; SI-NEXT:    v_add_i32_e32 v7, vcc, 3, v26
; SI-NEXT:    v_or_b32_e32 v6, v52, v6
; SI-NEXT:    v_and_b32_e32 v7, 0xff, v7
; SI-NEXT:    v_add_i32_e32 v6, vcc, s6, v6
; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT:    v_or_b32_e32 v7, v51, v7
; SI-NEXT:    v_or_b32_e32 v6, v7, v6
; SI-NEXT:    v_add_i32_e32 v7, vcc, 3, v28
; SI-NEXT:    v_and_b32_e32 v7, 0xff, v7
; SI-NEXT:    v_add_i32_e32 v8, vcc, 3, v30
; SI-NEXT:    v_or_b32_e32 v7, v27, v7
; SI-NEXT:    v_and_b32_e32 v8, 0xff, v8
; SI-NEXT:    v_add_i32_e32 v7, vcc, s6, v7
; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT:    v_or_b32_e32 v8, v25, v8
; SI-NEXT:    v_or_b32_e32 v7, v8, v7
; SI-NEXT:    s_waitcnt vmcnt(0)
; SI-NEXT:    v_add_i32_e32 v8, vcc, 3, v50
; SI-NEXT:    v_and_b32_e32 v8, 0xff, v8
; SI-NEXT:    v_add_i32_e32 v9, vcc, 3, v49
; SI-NEXT:    v_or_b32_e32 v8, v23, v8
; SI-NEXT:    v_and_b32_e32 v9, 0xff, v9
; SI-NEXT:    v_add_i32_e32 v8, vcc, s6, v8
; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT:    v_or_b32_e32 v9, v21, v9
; SI-NEXT:    v_or_b32_e32 v8, v9, v8
; SI-NEXT:    v_add_i32_e32 v9, vcc, 3, v48
; SI-NEXT:    v_and_b32_e32 v9, 0xff, v9
; SI-NEXT:    v_add_i32_e32 v10, vcc, 3, v39
; SI-NEXT:    v_or_b32_e32 v9, v19, v9
; SI-NEXT:    v_and_b32_e32 v10, 0xff, v10
; SI-NEXT:    v_add_i32_e32 v9, vcc, s6, v9
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT:    v_or_b32_e32 v10, v17, v10
; SI-NEXT:    v_or_b32_e32 v9, v10, v9
; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x3000000, v0
; SI-NEXT:    v_add_i32_e32 v1, vcc, 0x3000000, v1
; SI-NEXT:    v_add_i32_e32 v2, vcc, 0x3000000, v2
; SI-NEXT:    v_add_i32_e32 v3, vcc, 0x3000000, v3
; SI-NEXT:    v_add_i32_e32 v4, vcc, 0x3000000, v4
; SI-NEXT:    v_add_i32_e32 v5, vcc, 0x3000000, v5
; SI-NEXT:    v_add_i32_e32 v6, vcc, 0x3000000, v6
; SI-NEXT:    v_add_i32_e32 v7, vcc, 0x3000000, v7
; SI-NEXT:    v_add_i32_e32 v8, vcc, 0x3000000, v8
; SI-NEXT:    v_add_i32_e32 v9, vcc, 0x3000000, v9
; SI-NEXT:  .LBB72_4: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    buffer_load_dword v56, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v47, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v46, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v45, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v44, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v43, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v42, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT:    s_waitcnt vmcnt(0)
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v40i8_to_v5f64:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; VI-NEXT:    buffer_store_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; VI-NEXT:    buffer_store_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; VI-NEXT:    buffer_store_dword v43, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; VI-NEXT:    buffer_store_dword v44, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; VI-NEXT:    buffer_store_dword v45, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; VI-NEXT:    buffer_store_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; VI-NEXT:    buffer_store_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; VI-NEXT:    v_mov_b32_e32 v54, v0
; VI-NEXT:    buffer_load_ushort v45, off, s[0:3], s32
; VI-NEXT:    buffer_load_dword v0, off, s[0:3], s32 offset:36
; VI-NEXT:    buffer_load_ushort v55, off, s[0:3], s32 offset:32
; VI-NEXT:    buffer_load_ushort v40, off, s[0:3], s32 offset:28
; VI-NEXT:    buffer_load_ushort v41, off, s[0:3], s32 offset:24
; VI-NEXT:    buffer_load_ushort v42, off, s[0:3], s32 offset:20
; VI-NEXT:    buffer_load_ushort v43, off, s[0:3], s32 offset:16
; VI-NEXT:    buffer_load_ushort v44, off, s[0:3], s32 offset:12
; VI-NEXT:    buffer_load_ushort v46, off, s[0:3], s32 offset:8
; VI-NEXT:    buffer_load_ushort v47, off, s[0:3], s32 offset:4
; VI-NEXT:    v_mov_b32_e32 v31, v15
; VI-NEXT:    v_mov_b32_e32 v32, v14
; VI-NEXT:    v_mov_b32_e32 v33, v13
; VI-NEXT:    v_mov_b32_e32 v34, v12
; VI-NEXT:    v_mov_b32_e32 v35, v11
; VI-NEXT:    v_mov_b32_e32 v36, v10
; VI-NEXT:    v_mov_b32_e32 v37, v9
; VI-NEXT:    v_mov_b32_e32 v38, v8
; VI-NEXT:    v_mov_b32_e32 v39, v7
; VI-NEXT:    v_mov_b32_e32 v48, v6
; VI-NEXT:    v_mov_b32_e32 v49, v5
; VI-NEXT:    v_mov_b32_e32 v50, v4
; VI-NEXT:    v_mov_b32_e32 v51, v3
; VI-NEXT:    v_mov_b32_e32 v52, v2
; VI-NEXT:    v_mov_b32_e32 v53, v1
; VI-NEXT:    s_waitcnt vmcnt(8)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; VI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB72_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    s_mov_b32 s6, 0xc0c0004
; VI-NEXT:    v_perm_b32 v1, v52, v51, s6
; VI-NEXT:    v_perm_b32 v0, v54, v53, s6
; VI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT:    v_perm_b32 v2, v48, v39, s6
; VI-NEXT:    v_or_b32_e32 v0, v0, v1
; VI-NEXT:    v_perm_b32 v1, v50, v49, s6
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_perm_b32 v3, v36, v35, s6
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v38, v37, s6
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_perm_b32 v4, v32, v31, s6
; VI-NEXT:    v_or_b32_e32 v2, v2, v3
; VI-NEXT:    v_perm_b32 v3, v34, v33, s6
; VI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT:    v_perm_b32 v5, v18, v19, s6
; VI-NEXT:    v_or_b32_e32 v3, v3, v4
; VI-NEXT:    v_perm_b32 v4, v16, v17, s6
; VI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT:    v_perm_b32 v6, v22, v23, s6
; VI-NEXT:    v_or_b32_e32 v4, v4, v5
; VI-NEXT:    v_perm_b32 v5, v20, v21, s6
; VI-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT:    v_perm_b32 v7, v26, v27, s6
; VI-NEXT:    v_or_b32_e32 v5, v5, v6
; VI-NEXT:    v_perm_b32 v6, v24, v25, s6
; VI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT:    v_perm_b32 v8, v30, v45, s6
; VI-NEXT:    v_or_b32_e32 v6, v6, v7
; VI-NEXT:    v_perm_b32 v7, v28, v29, s6
; VI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT:    s_waitcnt vmcnt(2)
; VI-NEXT:    v_perm_b32 v9, v44, v43, s6
; VI-NEXT:    v_or_b32_e32 v7, v7, v8
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    v_perm_b32 v8, v47, v46, s6
; VI-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT:    v_perm_b32 v10, v40, v55, s6
; VI-NEXT:    v_or_b32_e32 v8, v8, v9
; VI-NEXT:    v_perm_b32 v9, v42, v41, s6
; VI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT:    v_or_b32_e32 v9, v9, v10
; VI-NEXT:    ; implicit-def: $vgpr54
; VI-NEXT:    ; implicit-def: $vgpr53
; VI-NEXT:    ; implicit-def: $vgpr52
; VI-NEXT:    ; implicit-def: $vgpr51
; VI-NEXT:    ; implicit-def: $vgpr50
; VI-NEXT:    ; implicit-def: $vgpr49
; VI-NEXT:    ; implicit-def: $vgpr48
; VI-NEXT:    ; implicit-def: $vgpr39
; VI-NEXT:    ; implicit-def: $vgpr38
; VI-NEXT:    ; implicit-def: $vgpr37
; VI-NEXT:    ; implicit-def: $vgpr36
; VI-NEXT:    ; implicit-def: $vgpr35
; VI-NEXT:    ; implicit-def: $vgpr34
; VI-NEXT:    ; implicit-def: $vgpr33
; VI-NEXT:    ; implicit-def: $vgpr32
; VI-NEXT:    ; implicit-def: $vgpr31
; VI-NEXT:    ; implicit-def: $vgpr16
; VI-NEXT:    ; implicit-def: $vgpr17
; VI-NEXT:    ; implicit-def: $vgpr18
; VI-NEXT:    ; implicit-def: $vgpr19
; VI-NEXT:    ; implicit-def: $vgpr20
; VI-NEXT:    ; implicit-def: $vgpr21
; VI-NEXT:    ; implicit-def: $vgpr22
; VI-NEXT:    ; implicit-def: $vgpr23
; VI-NEXT:    ; implicit-def: $vgpr24
; VI-NEXT:    ; implicit-def: $vgpr25
; VI-NEXT:    ; implicit-def: $vgpr26
; VI-NEXT:    ; implicit-def: $vgpr27
; VI-NEXT:    ; implicit-def: $vgpr28
; VI-NEXT:    ; implicit-def: $vgpr29
; VI-NEXT:    ; implicit-def: $vgpr30
; VI-NEXT:    ; implicit-def: $vgpr45
; VI-NEXT:    ; implicit-def: $vgpr47
; VI-NEXT:    ; implicit-def: $vgpr46
; VI-NEXT:    ; implicit-def: $vgpr44
; VI-NEXT:    ; implicit-def: $vgpr43
; VI-NEXT:    ; implicit-def: $vgpr42
; VI-NEXT:    ; implicit-def: $vgpr41
; VI-NEXT:    ; implicit-def: $vgpr40
; VI-NEXT:    ; implicit-def: $vgpr55
; VI-NEXT:  .LBB72_2: ; %Flow
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB72_4
; VI-NEXT:  ; %bb.3: ; %cmp.true
; VI-NEXT:    v_add_u16_e32 v0, 3, v54
; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v53
; VI-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v1, 3, v52
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v51
; VI-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_mov_b32_e32 v9, 0x300
; VI-NEXT:    v_add_u16_e32 v0, 0x300, v0
; VI-NEXT:    v_add_u16_sdwa v1, v1, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v0, v0, v1
; VI-NEXT:    v_add_u16_e32 v1, 3, v50
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v49
; VI-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v2, 3, v48
; VI-NEXT:    v_lshlrev_b16_e32 v3, 8, v39
; VI-NEXT:    v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v1, 0x300, v1
; VI-NEXT:    v_add_u16_sdwa v2, v2, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_add_u16_e32 v2, 3, v38
; VI-NEXT:    v_lshlrev_b16_e32 v3, 8, v37
; VI-NEXT:    v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v3, 3, v36
; VI-NEXT:    v_lshlrev_b16_e32 v4, 8, v35
; VI-NEXT:    v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v2, 0x300, v2
; VI-NEXT:    v_add_u16_sdwa v3, v3, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v2, v2, v3
; VI-NEXT:    v_add_u16_e32 v3, 3, v34
; VI-NEXT:    v_lshlrev_b16_e32 v4, 8, v33
; VI-NEXT:    v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v4, 3, v32
; VI-NEXT:    v_lshlrev_b16_e32 v5, 8, v31
; VI-NEXT:    v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v3, 0x300, v3
; VI-NEXT:    v_add_u16_sdwa v4, v4, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v3, v3, v4
; VI-NEXT:    v_add_u16_e32 v4, 3, v16
; VI-NEXT:    v_lshlrev_b16_e32 v5, 8, v17
; VI-NEXT:    v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v5, 3, v18
; VI-NEXT:    v_lshlrev_b16_e32 v6, 8, v19
; VI-NEXT:    v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v4, 0x300, v4
; VI-NEXT:    v_add_u16_sdwa v5, v5, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v4, v4, v5
; VI-NEXT:    v_add_u16_e32 v5, 3, v20
; VI-NEXT:    v_lshlrev_b16_e32 v6, 8, v21
; VI-NEXT:    v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v6, 3, v22
; VI-NEXT:    v_lshlrev_b16_e32 v7, 8, v23
; VI-NEXT:    v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v5, 0x300, v5
; VI-NEXT:    v_add_u16_sdwa v6, v6, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v5, v5, v6
; VI-NEXT:    v_add_u16_e32 v6, 3, v24
; VI-NEXT:    v_lshlrev_b16_e32 v7, 8, v25
; VI-NEXT:    v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v7, 3, v26
; VI-NEXT:    v_lshlrev_b16_e32 v8, 8, v27
; VI-NEXT:    v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v6, 0x300, v6
; VI-NEXT:    v_add_u16_sdwa v7, v7, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v6, v6, v7
; VI-NEXT:    v_add_u16_e32 v7, 3, v28
; VI-NEXT:    v_lshlrev_b16_e32 v8, 8, v29
; VI-NEXT:    v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v8, 3, v30
; VI-NEXT:    v_lshlrev_b16_e32 v10, 8, v45
; VI-NEXT:    v_or_b32_sdwa v8, v10, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v7, 0x300, v7
; VI-NEXT:    v_add_u16_sdwa v8, v8, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v7, v7, v8
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    v_add_u16_e32 v8, 3, v47
; VI-NEXT:    v_lshlrev_b16_e32 v10, 8, v46
; VI-NEXT:    v_or_b32_sdwa v8, v10, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v10, 3, v44
; VI-NEXT:    v_lshlrev_b16_e32 v11, 8, v43
; VI-NEXT:    v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v8, 0x300, v8
; VI-NEXT:    v_add_u16_sdwa v10, v10, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v8, v8, v10
; VI-NEXT:    v_add_u16_e32 v10, 3, v42
; VI-NEXT:    v_lshlrev_b16_e32 v11, 8, v41
; VI-NEXT:    v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v11, 3, v40
; VI-NEXT:    v_lshlrev_b16_e32 v12, 8, v55
; VI-NEXT:    v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v10, 0x300, v10
; VI-NEXT:    v_add_u16_sdwa v9, v11, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v9, v10, v9
; VI-NEXT:  .LBB72_4: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    buffer_load_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; VI-NEXT:    buffer_load_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; VI-NEXT:    buffer_load_dword v45, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; VI-NEXT:    buffer_load_dword v44, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; VI-NEXT:    buffer_load_dword v43, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; VI-NEXT:    buffer_load_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; VI-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; VI-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v40i8_to_v5f64:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; GFX9-NEXT:    buffer_store_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; GFX9-NEXT:    buffer_store_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT:    buffer_store_dword v43, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT:    buffer_store_dword v44, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; GFX9-NEXT:    buffer_store_dword v45, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; GFX9-NEXT:    buffer_store_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; GFX9-NEXT:    buffer_store_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; GFX9-NEXT:    v_mov_b32_e32 v54, v0
; GFX9-NEXT:    buffer_load_ushort v45, off, s[0:3], s32
; GFX9-NEXT:    buffer_load_dword v0, off, s[0:3], s32 offset:36
; GFX9-NEXT:    buffer_load_ushort v55, off, s[0:3], s32 offset:32
; GFX9-NEXT:    buffer_load_ushort v40, off, s[0:3], s32 offset:28
; GFX9-NEXT:    buffer_load_ushort v41, off, s[0:3], s32 offset:24
; GFX9-NEXT:    buffer_load_ushort v42, off, s[0:3], s32 offset:20
; GFX9-NEXT:    buffer_load_ushort v43, off, s[0:3], s32 offset:16
; GFX9-NEXT:    buffer_load_ushort v44, off, s[0:3], s32 offset:12
; GFX9-NEXT:    buffer_load_ushort v46, off, s[0:3], s32 offset:8
; GFX9-NEXT:    buffer_load_ushort v47, off, s[0:3], s32 offset:4
; GFX9-NEXT:    v_mov_b32_e32 v31, v15
; GFX9-NEXT:    v_mov_b32_e32 v32, v14
; GFX9-NEXT:    v_mov_b32_e32 v33, v13
; GFX9-NEXT:    v_mov_b32_e32 v34, v12
; GFX9-NEXT:    v_mov_b32_e32 v35, v11
; GFX9-NEXT:    v_mov_b32_e32 v36, v10
; GFX9-NEXT:    v_mov_b32_e32 v37, v9
; GFX9-NEXT:    v_mov_b32_e32 v38, v8
; GFX9-NEXT:    v_mov_b32_e32 v39, v7
; GFX9-NEXT:    v_mov_b32_e32 v48, v6
; GFX9-NEXT:    v_mov_b32_e32 v49, v5
; GFX9-NEXT:    v_mov_b32_e32 v50, v4
; GFX9-NEXT:    v_mov_b32_e32 v51, v3
; GFX9-NEXT:    v_mov_b32_e32 v52, v2
; GFX9-NEXT:    v_mov_b32_e32 v53, v1
; GFX9-NEXT:    s_waitcnt vmcnt(8)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB72_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    s_mov_b32 s6, 0xc0c0004
; GFX9-NEXT:    v_perm_b32 v0, v54, v53, s6
; GFX9-NEXT:    v_perm_b32 v1, v52, v51, s6
; GFX9-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT:    v_perm_b32 v1, v50, v49, s6
; GFX9-NEXT:    v_perm_b32 v2, v48, v39, s6
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    v_perm_b32 v2, v38, v37, s6
; GFX9-NEXT:    v_perm_b32 v3, v36, v35, s6
; GFX9-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT:    v_perm_b32 v3, v34, v33, s6
; GFX9-NEXT:    v_perm_b32 v4, v32, v31, s6
; GFX9-NEXT:    v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT:    v_perm_b32 v4, v16, v17, s6
; GFX9-NEXT:    v_perm_b32 v5, v18, v19, s6
; GFX9-NEXT:    v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT:    v_perm_b32 v5, v20, v21, s6
; GFX9-NEXT:    v_perm_b32 v6, v22, v23, s6
; GFX9-NEXT:    v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT:    v_perm_b32 v6, v24, v25, s6
; GFX9-NEXT:    v_perm_b32 v7, v26, v27, s6
; GFX9-NEXT:    v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT:    v_perm_b32 v7, v28, v29, s6
; GFX9-NEXT:    v_perm_b32 v8, v30, v45, s6
; GFX9-NEXT:    v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    v_perm_b32 v8, v47, v46, s6
; GFX9-NEXT:    v_perm_b32 v9, v44, v43, s6
; GFX9-NEXT:    v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT:    v_perm_b32 v9, v42, v41, s6
; GFX9-NEXT:    v_perm_b32 v10, v40, v55, s6
; GFX9-NEXT:    v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT:    ; implicit-def: $vgpr54
; GFX9-NEXT:    ; implicit-def: $vgpr53
; GFX9-NEXT:    ; implicit-def: $vgpr52
; GFX9-NEXT:    ; implicit-def: $vgpr51
; GFX9-NEXT:    ; implicit-def: $vgpr50
; GFX9-NEXT:    ; implicit-def: $vgpr49
; GFX9-NEXT:    ; implicit-def: $vgpr48
; GFX9-NEXT:    ; implicit-def: $vgpr39
; GFX9-NEXT:    ; implicit-def: $vgpr38
; GFX9-NEXT:    ; implicit-def: $vgpr37
; GFX9-NEXT:    ; implicit-def: $vgpr36
; GFX9-NEXT:    ; implicit-def: $vgpr35
; GFX9-NEXT:    ; implicit-def: $vgpr34
; GFX9-NEXT:    ; implicit-def: $vgpr33
; GFX9-NEXT:    ; implicit-def: $vgpr32
; GFX9-NEXT:    ; implicit-def: $vgpr31
; GFX9-NEXT:    ; implicit-def: $vgpr16
; GFX9-NEXT:    ; implicit-def: $vgpr17
; GFX9-NEXT:    ; implicit-def: $vgpr18
; GFX9-NEXT:    ; implicit-def: $vgpr19
; GFX9-NEXT:    ; implicit-def: $vgpr20
; GFX9-NEXT:    ; implicit-def: $vgpr21
; GFX9-NEXT:    ; implicit-def: $vgpr22
; GFX9-NEXT:    ; implicit-def: $vgpr23
; GFX9-NEXT:    ; implicit-def: $vgpr24
; GFX9-NEXT:    ; implicit-def: $vgpr25
; GFX9-NEXT:    ; implicit-def: $vgpr26
; GFX9-NEXT:    ; implicit-def: $vgpr27
; GFX9-NEXT:    ; implicit-def: $vgpr28
; GFX9-NEXT:    ; implicit-def: $vgpr29
; GFX9-NEXT:    ; implicit-def: $vgpr30
; GFX9-NEXT:    ; implicit-def: $vgpr45
; GFX9-NEXT:    ; implicit-def: $vgpr47
; GFX9-NEXT:    ; implicit-def: $vgpr46
; GFX9-NEXT:    ; implicit-def: $vgpr44
; GFX9-NEXT:    ; implicit-def: $vgpr43
; GFX9-NEXT:    ; implicit-def: $vgpr42
; GFX9-NEXT:    ; implicit-def: $vgpr41
; GFX9-NEXT:    ; implicit-def: $vgpr40
; GFX9-NEXT:    ; implicit-def: $vgpr55
; GFX9-NEXT:  .LBB72_2: ; %Flow
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB72_4
; GFX9-NEXT:  ; %bb.3: ; %cmp.true
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v54
; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v53
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v1, 3, v52
; GFX9-NEXT:    v_lshlrev_b16_e32 v2, 8, v51
; GFX9-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v0, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v1, 0x300, v1
; GFX9-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT:    v_add_u16_e32 v1, 3, v50
; GFX9-NEXT:    v_lshlrev_b16_e32 v2, 8, v49
; GFX9-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v2, 3, v48
; GFX9-NEXT:    v_lshlrev_b16_e32 v3, 8, v39
; GFX9-NEXT:    v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v1, 0x300, v1
; GFX9-NEXT:    v_add_u16_e32 v2, 0x300, v2
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    v_add_u16_e32 v2, 3, v38
; GFX9-NEXT:    v_lshlrev_b16_e32 v3, 8, v37
; GFX9-NEXT:    v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v3, 3, v36
; GFX9-NEXT:    v_lshlrev_b16_e32 v4, 8, v35
; GFX9-NEXT:    v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v2, 0x300, v2
; GFX9-NEXT:    v_add_u16_e32 v3, 0x300, v3
; GFX9-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT:    v_add_u16_e32 v3, 3, v34
; GFX9-NEXT:    v_lshlrev_b16_e32 v4, 8, v33
; GFX9-NEXT:    v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v4, 3, v32
; GFX9-NEXT:    v_lshlrev_b16_e32 v5, 8, v31
; GFX9-NEXT:    v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v3, 0x300, v3
; GFX9-NEXT:    v_add_u16_e32 v4, 0x300, v4
; GFX9-NEXT:    v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT:    v_add_u16_e32 v4, 3, v16
; GFX9-NEXT:    v_lshlrev_b16_e32 v5, 8, v17
; GFX9-NEXT:    v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v5, 3, v18
; GFX9-NEXT:    v_lshlrev_b16_e32 v6, 8, v19
; GFX9-NEXT:    v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v4, 0x300, v4
; GFX9-NEXT:    v_add_u16_e32 v5, 0x300, v5
; GFX9-NEXT:    v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT:    v_add_u16_e32 v5, 3, v20
; GFX9-NEXT:    v_lshlrev_b16_e32 v6, 8, v21
; GFX9-NEXT:    v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v6, 3, v22
; GFX9-NEXT:    v_lshlrev_b16_e32 v7, 8, v23
; GFX9-NEXT:    v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v5, 0x300, v5
; GFX9-NEXT:    v_add_u16_e32 v6, 0x300, v6
; GFX9-NEXT:    v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT:    v_add_u16_e32 v6, 3, v24
; GFX9-NEXT:    v_lshlrev_b16_e32 v7, 8, v25
; GFX9-NEXT:    v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v7, 3, v26
; GFX9-NEXT:    v_lshlrev_b16_e32 v8, 8, v27
; GFX9-NEXT:    v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v6, 0x300, v6
; GFX9-NEXT:    v_add_u16_e32 v7, 0x300, v7
; GFX9-NEXT:    v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT:    v_add_u16_e32 v7, 3, v28
; GFX9-NEXT:    v_lshlrev_b16_e32 v8, 8, v29
; GFX9-NEXT:    v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v8, 3, v30
; GFX9-NEXT:    v_lshlrev_b16_e32 v9, 8, v45
; GFX9-NEXT:    v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v7, 0x300, v7
; GFX9-NEXT:    v_add_u16_e32 v8, 0x300, v8
; GFX9-NEXT:    v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    v_add_u16_e32 v8, 3, v47
; GFX9-NEXT:    v_lshlrev_b16_e32 v9, 8, v46
; GFX9-NEXT:    v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v9, 3, v44
; GFX9-NEXT:    v_lshlrev_b16_e32 v10, 8, v43
; GFX9-NEXT:    v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v8, 0x300, v8
; GFX9-NEXT:    v_add_u16_e32 v9, 0x300, v9
; GFX9-NEXT:    v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT:    v_add_u16_e32 v9, 3, v42
; GFX9-NEXT:    v_lshlrev_b16_e32 v10, 8, v41
; GFX9-NEXT:    v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v10, 3, v40
; GFX9-NEXT:    v_lshlrev_b16_e32 v11, 8, v55
; GFX9-NEXT:    v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v9, 0x300, v9
; GFX9-NEXT:    v_add_u16_e32 v10, 0x300, v10
; GFX9-NEXT:    v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT:  .LBB72_4: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    buffer_load_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; GFX9-NEXT:    buffer_load_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; GFX9-NEXT:    buffer_load_dword v45, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; GFX9-NEXT:    buffer_load_dword v44, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; GFX9-NEXT:    buffer_load_dword v43, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; GFX9-NEXT:    buffer_load_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; GFX9-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v40i8_to_v5f64:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    s_clause 0x9
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v31, off, s32 offset:32
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v32, off, s32 offset:28
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v33, off, s32 offset:24
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v34, off, s32 offset:20
; GFX11-TRUE16-NEXT:    scratch_load_b32 v80, off, s32 offset:36
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v35, off, s32 offset:16
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v37, off, s32 offset:12
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v36, off, s32 offset:8
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v38, off, s32 offset:4
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v39, off, s32
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v48.l, v15.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v49.l, v14.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v50.l, v13.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v51.l, v12.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v52.l, v11.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v53.l, v10.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v54.l, v9.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v8.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v64.l, v7.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v65.l, v6.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v66.l, v5.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v67.l, v4.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v68.l, v3.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v69.l, v2.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v70.l, v1.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v71.l, v0.l
; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(5)
; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v80
; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB72_3
; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB72_4
; GFX11-TRUE16-NEXT:  .LBB72_2: ; %end
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT:  .LBB72_3: ; %cmp.false
; GFX11-TRUE16-NEXT:    v_perm_b32 v0, v71, v70, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v1, v69, v68, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v2, v67, v66, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v3, v65, v64, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v4, v55, v54, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v5, v53, v52, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, v51, v50, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, v49, v48, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v8, v16, v17, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v9, v18, v19, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v1, v3, 16, v2
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v2, v5, 16, v4
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v3, v7, 16, v6
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v4, v9, 16, v8
; GFX11-TRUE16-NEXT:    v_perm_b32 v5, v20, v21, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, v22, v23, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, v24, v25, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v8, v26, v27, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v9, v28, v29, 0xc0c0004
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT:    v_perm_b32 v10, v30, v39, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v11, v38, v36, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v12, v37, v35, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v13, v34, v33, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v14, v32, v31, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v5, v6, 16, v5
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v6, v8, 16, v7
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v7, v10, 16, v9
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v8, v12, 16, v11
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v9, v14, 16, v13
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr71_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr70_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr69_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr68_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr67_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr66_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr65_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_lo16
; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB72_2
; GFX11-TRUE16-NEXT:  .LBB72_4: ; %cmp.true
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v71.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v69.l, 3
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v70.l
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 8, v68.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v67.l, 3
; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, 0xff
; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, v0.h, 0xff
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v65.l, 3
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v66.l
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v64.l
; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v1.h, v0.h
; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, v2.l, 0xff
; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, v3.l, 0xff
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v55.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v53.l, 3
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.l, 8, v50.l
; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v2.h, v1.l
; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v3.h, v1.h
; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, v2.l, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v54.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, v51.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.h, v49.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, v16.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, v18.l, 3
; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.h, v2.l
; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, v3.l, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.l, 8, v52.l
; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, v3.h, 0xff
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, v22.l, 3
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v23.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, v24.l, 3
; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v3.l, v2.h
; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v4.l, v3.h
; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, v4.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.l, 8, v48.l
; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, v5.l, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.l, 8, v17.l
; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, v6.l, 0xff
; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, v7.l, 0xff
; GFX11-TRUE16-NEXT:    v_or_b16 v3.h, v4.l, v3.h
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v25.l
; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v5.l, v4.h
; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, v5.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.l, 8, v19.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, v20.l, 3
; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.h, v6.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, v28.l, 3
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.l, 8, v27.l
; GFX11-TRUE16-NEXT:    v_or_b16 v4.h, v5.l, v4.h
; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, v5.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v21.l
; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, v6.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v29.l
; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.h, v7.l
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(3)
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, v37.l, 3
; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.h, v5.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, v26.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.h, v34.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v10.h, v32.l, 3
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(2)
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.l, 8, v36.l
; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, v9.l, 0xff
; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, v5.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.l, 8, v35.l
; GFX11-TRUE16-NEXT:    v_and_b16 v9.h, v9.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v33.l
; GFX11-TRUE16-NEXT:    v_and_b16 v10.h, v10.h, 0xff
; GFX11-TRUE16-NEXT:    v_or_b16 v7.h, v8.l, v5.h
; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.h, v6.h
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.h, v30.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, v6.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, v7.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, v7.h, 0x300
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, v38.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, v8.l, 0x300
; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, v8.h, 0xff
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v39.l
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.l, 8, v31.l
; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, v7.h, 0xff
; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v11.l, v9.l
; GFX11-TRUE16-NEXT:    v_or_b16 v9.h, v11.h, v9.h
; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.h, v8.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, 0x300
; GFX11-TRUE16-NEXT:    v_or_b16 v8.h, v10.l, v7.h
; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v12.l, v10.h
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v0.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v1.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v1.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v2.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v2.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v3.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, v3.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, v4.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.h, v4.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, v5.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, v8.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, v8.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.h, v9.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, v9.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.h, v10.l, 0x300
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v40i8_to_v5f64:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v53, v1 :: v_dual_mov_b32 v54, v0
; GFX11-FAKE16-NEXT:    s_clause 0x9
; GFX11-FAKE16-NEXT:    scratch_load_u16 v55, off, s32 offset:32
; GFX11-FAKE16-NEXT:    scratch_load_u16 v64, off, s32 offset:28
; GFX11-FAKE16-NEXT:    scratch_load_u16 v65, off, s32 offset:24
; GFX11-FAKE16-NEXT:    scratch_load_u16 v67, off, s32 offset:20
; GFX11-FAKE16-NEXT:    scratch_load_b32 v0, off, s32 offset:36
; GFX11-FAKE16-NEXT:    scratch_load_u16 v66, off, s32 offset:16
; GFX11-FAKE16-NEXT:    scratch_load_u16 v68, off, s32 offset:12
; GFX11-FAKE16-NEXT:    scratch_load_u16 v69, off, s32 offset:8
; GFX11-FAKE16-NEXT:    scratch_load_u16 v71, off, s32 offset:4
; GFX11-FAKE16-NEXT:    scratch_load_u16 v70, off, s32
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v33, v15 :: v_dual_mov_b32 v34, v12
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v31, v14 :: v_dual_mov_b32 v32, v13
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v35, v11 :: v_dual_mov_b32 v36, v10
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v37, v9 :: v_dual_mov_b32 v38, v8
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v39, v7 :: v_dual_mov_b32 v48, v6
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v49, v5 :: v_dual_mov_b32 v50, v4
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v51, v3 :: v_dual_mov_b32 v52, v2
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(5)
; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB72_3
; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB72_4
; GFX11-FAKE16-NEXT:  .LBB72_2: ; %end
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT:  .LBB72_3: ; %cmp.false
; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v54, v53, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v52, v51, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v50, v49, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v48, v39, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v38, v37, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v36, v35, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v34, v32, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v31, v33, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v16, v17, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v18, v19, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, v5, 16, v4
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v3, v7, 16, v6
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v4, v9, 16, v8
; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v20, v21, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v22, v23, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v24, v25, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v26, v27, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v28, v29, 0xc0c0004
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v30, v70, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v71, v69, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v68, v66, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v67, v65, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v64, v55, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v5, v6, 16, v5
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v6, v8, 16, v7
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v7, v10, 16, v9
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v8, v12, 16, v11
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v9, v14, 16, v13
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr70
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr71
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr69
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr68
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr66
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr67
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr55
; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB72_2
; GFX11-FAKE16-NEXT:  .LBB72_4: ; %cmp.true
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v54, 3
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v53
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v50, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v38, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v52, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v49
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v48, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v36, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v1, v0
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v37
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v51
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v39
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v5, v4
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v8
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v9
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 8, v35
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v0, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v3, v2
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v4, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v7, v6
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v1, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v8, v5
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v2, 0x300
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v4, 0x300
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v1
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v5, 0x300
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v34, 3
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v2, 16, v0
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v4, 16, v3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v16, 3
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, v5, 16, v6
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v7
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v32
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v31, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v17
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v18, 3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v5, v4
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v6
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v6, 8, v33
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v7, v3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v8
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 8, v19
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v4, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v6, v5
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v20, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v3, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v8, v7
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v5, 0x300
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v9
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 8, v21
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v6, 0x300
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v3, v5, 16, v4
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v24, 3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v22, 3
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v4, v6, 16, v9
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v9, 8, v25
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v7, 0x300
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v8
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v28, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v26, 3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v9, v5
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v23
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v12, 8, v29
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v10
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v5, 0x300
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v10, 8, v27
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v11, v7
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v12, v8
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, v67, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v5
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v71, 3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v10, v9
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v30, 3
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v14, 8, v69
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, v68, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v65
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, v64, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v70
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v14, v5
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v15
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v66
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v16, v12
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v17
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v55
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v8, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v13, v10
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v5, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v15, v14
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, v12, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v17, v16
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v7, 0x300
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v9, 0x300
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v10, 0x300
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v5
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, v13, 0x300
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, v14, 0x300
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v5, v7, 16, v6
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v6, v9, 16, v11
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v7, v10, 16, v8
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v8, v13, 16, v15
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v9, v14, 16, v12
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <40 x i8> %a, splat (i8 3)
  %a2 = bitcast <40 x i8> %a1 to <5 x double>
  br label %end

cmp.false:
  %a3 = bitcast <40 x i8> %a to <5 x double>
  br label %end

end:
  %phi = phi <5 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <5 x double> %phi
}

define inreg <5 x double> @bitcast_v40i8_to_v5f64_scalar(<40 x i8> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v40i8_to_v5f64_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_readfirstlane_b32 s4, v26
; SI-NEXT:    v_readfirstlane_b32 s5, v25
; SI-NEXT:    v_readfirstlane_b32 s6, v24
; SI-NEXT:    v_readfirstlane_b32 s8, v23
; SI-NEXT:    v_readfirstlane_b32 s9, v22
; SI-NEXT:    v_readfirstlane_b32 s10, v21
; SI-NEXT:    v_readfirstlane_b32 s11, v20
; SI-NEXT:    v_readfirstlane_b32 s13, v19
; SI-NEXT:    v_readfirstlane_b32 s14, v18
; SI-NEXT:    v_readfirstlane_b32 s40, v17
; SI-NEXT:    v_readfirstlane_b32 s41, v16
; SI-NEXT:    v_readfirstlane_b32 s42, v15
; SI-NEXT:    v_readfirstlane_b32 s43, v14
; SI-NEXT:    v_readfirstlane_b32 s44, v13
; SI-NEXT:    v_readfirstlane_b32 s45, v12
; SI-NEXT:    v_readfirstlane_b32 s46, v11
; SI-NEXT:    v_readfirstlane_b32 s47, v10
; SI-NEXT:    v_readfirstlane_b32 s56, v9
; SI-NEXT:    v_readfirstlane_b32 s57, v8
; SI-NEXT:    v_readfirstlane_b32 s58, v7
; SI-NEXT:    v_readfirstlane_b32 s59, v6
; SI-NEXT:    v_readfirstlane_b32 s60, v5
; SI-NEXT:    v_readfirstlane_b32 s61, v4
; SI-NEXT:    s_cmp_lg_u32 s4, 0
; SI-NEXT:    v_readfirstlane_b32 s62, v3
; SI-NEXT:    v_readfirstlane_b32 s63, v2
; SI-NEXT:    v_readfirstlane_b32 s15, v1
; SI-NEXT:    v_readfirstlane_b32 s72, v0
; SI-NEXT:    s_cbranch_scc0 .LBB73_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    s_and_b32 s4, s16, 0xff
; SI-NEXT:    s_lshl_b32 s7, s17, 8
; SI-NEXT:    s_or_b32 s4, s4, s7
; SI-NEXT:    s_and_b32 s7, s18, 0xff
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_lshl_b32 s12, s19, 24
; SI-NEXT:    s_and_b32 s4, s4, 0xffff
; SI-NEXT:    s_or_b32 s7, s12, s7
; SI-NEXT:    s_or_b32 s4, s4, s7
; SI-NEXT:    s_and_b32 s7, s20, 0xff
; SI-NEXT:    s_lshl_b32 s12, s21, 8
; SI-NEXT:    s_or_b32 s7, s7, s12
; SI-NEXT:    s_and_b32 s12, s22, 0xff
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_lshl_b32 s16, s23, 24
; SI-NEXT:    s_and_b32 s7, s7, 0xffff
; SI-NEXT:    s_or_b32 s12, s16, s12
; SI-NEXT:    s_or_b32 s7, s7, s12
; SI-NEXT:    s_and_b32 s12, s24, 0xff
; SI-NEXT:    s_lshl_b32 s16, s25, 8
; SI-NEXT:    s_or_b32 s12, s12, s16
; SI-NEXT:    s_and_b32 s16, s26, 0xff
; SI-NEXT:    s_lshl_b32 s16, s16, 16
; SI-NEXT:    s_lshl_b32 s17, s27, 24
; SI-NEXT:    s_and_b32 s12, s12, 0xffff
; SI-NEXT:    s_or_b32 s16, s17, s16
; SI-NEXT:    s_or_b32 s12, s12, s16
; SI-NEXT:    s_and_b32 s16, s28, 0xff
; SI-NEXT:    s_lshl_b32 s17, s29, 8
; SI-NEXT:    s_or_b32 s16, s16, s17
; SI-NEXT:    s_and_b32 s17, s72, 0xff
; SI-NEXT:    s_lshl_b32 s17, s17, 16
; SI-NEXT:    s_lshl_b32 s15, s15, 24
; SI-NEXT:    s_and_b32 s16, s16, 0xffff
; SI-NEXT:    s_or_b32 s15, s15, s17
; SI-NEXT:    s_or_b32 s15, s16, s15
; SI-NEXT:    s_and_b32 s16, s63, 0xff
; SI-NEXT:    s_lshl_b32 s17, s62, 8
; SI-NEXT:    s_or_b32 s16, s16, s17
; SI-NEXT:    s_and_b32 s17, s61, 0xff
; SI-NEXT:    s_lshl_b32 s17, s17, 16
; SI-NEXT:    s_lshl_b32 s18, s60, 24
; SI-NEXT:    s_and_b32 s16, s16, 0xffff
; SI-NEXT:    s_or_b32 s17, s18, s17
; SI-NEXT:    s_or_b32 s16, s16, s17
; SI-NEXT:    s_and_b32 s17, s59, 0xff
; SI-NEXT:    s_lshl_b32 s18, s58, 8
; SI-NEXT:    s_or_b32 s17, s17, s18
; SI-NEXT:    s_and_b32 s18, s57, 0xff
; SI-NEXT:    s_lshl_b32 s18, s18, 16
; SI-NEXT:    s_lshl_b32 s19, s56, 24
; SI-NEXT:    s_and_b32 s17, s17, 0xffff
; SI-NEXT:    s_or_b32 s18, s19, s18
; SI-NEXT:    s_or_b32 s17, s17, s18
; SI-NEXT:    s_and_b32 s18, s47, 0xff
; SI-NEXT:    s_lshl_b32 s19, s46, 8
; SI-NEXT:    s_or_b32 s18, s18, s19
; SI-NEXT:    s_and_b32 s19, s45, 0xff
; SI-NEXT:    s_lshl_b32 s19, s19, 16
; SI-NEXT:    s_lshl_b32 s20, s44, 24
; SI-NEXT:    s_and_b32 s18, s18, 0xffff
; SI-NEXT:    s_or_b32 s19, s20, s19
; SI-NEXT:    s_or_b32 s18, s18, s19
; SI-NEXT:    s_and_b32 s19, s43, 0xff
; SI-NEXT:    s_lshl_b32 s20, s42, 8
; SI-NEXT:    s_or_b32 s19, s19, s20
; SI-NEXT:    s_and_b32 s20, s41, 0xff
; SI-NEXT:    s_and_b32 s14, s14, 0xff
; SI-NEXT:    s_lshl_b32 s13, s13, 8
; SI-NEXT:    s_and_b32 s11, s11, 0xff
; SI-NEXT:    s_and_b32 s9, s9, 0xff
; SI-NEXT:    s_lshl_b32 s8, s8, 8
; SI-NEXT:    s_and_b32 s6, s6, 0xff
; SI-NEXT:    s_lshl_b32 s20, s20, 16
; SI-NEXT:    s_lshl_b32 s21, s40, 24
; SI-NEXT:    s_or_b32 s13, s14, s13
; SI-NEXT:    s_lshl_b32 s11, s11, 16
; SI-NEXT:    s_lshl_b32 s10, s10, 24
; SI-NEXT:    s_or_b32 s8, s9, s8
; SI-NEXT:    s_lshl_b32 s6, s6, 16
; SI-NEXT:    s_lshl_b32 s5, s5, 24
; SI-NEXT:    s_and_b32 s19, s19, 0xffff
; SI-NEXT:    s_or_b32 s20, s21, s20
; SI-NEXT:    s_and_b32 s13, s13, 0xffff
; SI-NEXT:    s_or_b32 s10, s10, s11
; SI-NEXT:    s_and_b32 s8, s8, 0xffff
; SI-NEXT:    s_or_b32 s5, s5, s6
; SI-NEXT:    s_or_b32 s19, s19, s20
; SI-NEXT:    s_or_b32 s10, s13, s10
; SI-NEXT:    s_or_b32 s5, s8, s5
; SI-NEXT:    s_branch .LBB73_3
; SI-NEXT:  .LBB73_2: ; %cmp.true
; SI-NEXT:    s_add_i32 s16, s16, 3
; SI-NEXT:    s_and_b32 s4, s16, 0xff
; SI-NEXT:    s_lshl_b32 s7, s17, 8
; SI-NEXT:    s_add_i32 s18, s18, 3
; SI-NEXT:    s_or_b32 s4, s7, s4
; SI-NEXT:    s_and_b32 s12, s18, 0xff
; SI-NEXT:    s_addk_i32 s4, 0x300
; SI-NEXT:    s_lshl_b32 s7, s19, 24
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_and_b32 s4, s4, 0xffff
; SI-NEXT:    s_or_b32 s7, s7, s12
; SI-NEXT:    s_add_i32 s20, s20, 3
; SI-NEXT:    s_or_b32 s4, s7, s4
; SI-NEXT:    s_and_b32 s7, s20, 0xff
; SI-NEXT:    s_lshl_b32 s12, s21, 8
; SI-NEXT:    s_add_i32 s22, s22, 3
; SI-NEXT:    s_or_b32 s7, s12, s7
; SI-NEXT:    s_and_b32 s16, s22, 0xff
; SI-NEXT:    s_addk_i32 s7, 0x300
; SI-NEXT:    s_lshl_b32 s12, s23, 24
; SI-NEXT:    s_lshl_b32 s16, s16, 16
; SI-NEXT:    s_and_b32 s7, s7, 0xffff
; SI-NEXT:    s_or_b32 s12, s12, s16
; SI-NEXT:    s_add_i32 s24, s24, 3
; SI-NEXT:    s_or_b32 s7, s12, s7
; SI-NEXT:    s_and_b32 s12, s24, 0xff
; SI-NEXT:    s_lshl_b32 s16, s25, 8
; SI-NEXT:    s_add_i32 s26, s26, 3
; SI-NEXT:    s_or_b32 s12, s16, s12
; SI-NEXT:    s_and_b32 s17, s26, 0xff
; SI-NEXT:    s_addk_i32 s12, 0x300
; SI-NEXT:    s_lshl_b32 s16, s27, 24
; SI-NEXT:    s_lshl_b32 s17, s17, 16
; SI-NEXT:    s_and_b32 s12, s12, 0xffff
; SI-NEXT:    s_or_b32 s16, s16, s17
; SI-NEXT:    s_add_i32 s28, s28, 3
; SI-NEXT:    s_or_b32 s12, s16, s12
; SI-NEXT:    s_and_b32 s16, s28, 0xff
; SI-NEXT:    s_lshl_b32 s17, s29, 8
; SI-NEXT:    s_add_i32 s72, s72, 3
; SI-NEXT:    s_or_b32 s16, s17, s16
; SI-NEXT:    s_and_b32 s17, s72, 0xff
; SI-NEXT:    s_addk_i32 s16, 0x300
; SI-NEXT:    s_lshl_b32 s15, s15, 24
; SI-NEXT:    s_lshl_b32 s17, s17, 16
; SI-NEXT:    s_and_b32 s16, s16, 0xffff
; SI-NEXT:    s_or_b32 s15, s15, s17
; SI-NEXT:    s_add_i32 s63, s63, 3
; SI-NEXT:    s_or_b32 s15, s15, s16
; SI-NEXT:    s_and_b32 s16, s63, 0xff
; SI-NEXT:    s_lshl_b32 s17, s62, 8
; SI-NEXT:    s_add_i32 s61, s61, 3
; SI-NEXT:    s_or_b32 s16, s17, s16
; SI-NEXT:    s_and_b32 s18, s61, 0xff
; SI-NEXT:    s_addk_i32 s16, 0x300
; SI-NEXT:    s_lshl_b32 s17, s60, 24
; SI-NEXT:    s_lshl_b32 s18, s18, 16
; SI-NEXT:    s_and_b32 s16, s16, 0xffff
; SI-NEXT:    s_or_b32 s17, s17, s18
; SI-NEXT:    s_add_i32 s59, s59, 3
; SI-NEXT:    s_or_b32 s16, s17, s16
; SI-NEXT:    s_and_b32 s17, s59, 0xff
; SI-NEXT:    s_lshl_b32 s18, s58, 8
; SI-NEXT:    s_add_i32 s57, s57, 3
; SI-NEXT:    s_or_b32 s17, s18, s17
; SI-NEXT:    s_and_b32 s19, s57, 0xff
; SI-NEXT:    s_addk_i32 s17, 0x300
; SI-NEXT:    s_lshl_b32 s18, s56, 24
; SI-NEXT:    s_lshl_b32 s19, s19, 16
; SI-NEXT:    s_and_b32 s17, s17, 0xffff
; SI-NEXT:    s_or_b32 s18, s18, s19
; SI-NEXT:    s_add_i32 s47, s47, 3
; SI-NEXT:    s_or_b32 s17, s18, s17
; SI-NEXT:    s_and_b32 s18, s47, 0xff
; SI-NEXT:    s_lshl_b32 s19, s46, 8
; SI-NEXT:    s_add_i32 s45, s45, 3
; SI-NEXT:    s_or_b32 s18, s19, s18
; SI-NEXT:    s_and_b32 s20, s45, 0xff
; SI-NEXT:    s_addk_i32 s18, 0x300
; SI-NEXT:    s_lshl_b32 s19, s44, 24
; SI-NEXT:    s_lshl_b32 s20, s20, 16
; SI-NEXT:    s_and_b32 s18, s18, 0xffff
; SI-NEXT:    s_or_b32 s19, s19, s20
; SI-NEXT:    s_add_i32 s43, s43, 3
; SI-NEXT:    s_add_i32 s14, s14, 3
; SI-NEXT:    s_add_i32 s9, s9, 3
; SI-NEXT:    s_or_b32 s18, s19, s18
; SI-NEXT:    s_and_b32 s19, s43, 0xff
; SI-NEXT:    s_lshl_b32 s20, s42, 8
; SI-NEXT:    s_add_i32 s41, s41, 3
; SI-NEXT:    s_and_b32 s14, s14, 0xff
; SI-NEXT:    s_lshl_b32 s13, s13, 8
; SI-NEXT:    s_add_i32 s11, s11, 3
; SI-NEXT:    s_and_b32 s9, s9, 0xff
; SI-NEXT:    s_lshl_b32 s8, s8, 8
; SI-NEXT:    s_add_i32 s6, s6, 3
; SI-NEXT:    s_or_b32 s19, s20, s19
; SI-NEXT:    s_and_b32 s21, s41, 0xff
; SI-NEXT:    s_or_b32 s13, s13, s14
; SI-NEXT:    s_and_b32 s11, s11, 0xff
; SI-NEXT:    s_or_b32 s8, s8, s9
; SI-NEXT:    s_and_b32 s6, s6, 0xff
; SI-NEXT:    s_addk_i32 s19, 0x300
; SI-NEXT:    s_lshl_b32 s20, s40, 24
; SI-NEXT:    s_lshl_b32 s21, s21, 16
; SI-NEXT:    s_addk_i32 s13, 0x300
; SI-NEXT:    s_lshl_b32 s10, s10, 24
; SI-NEXT:    s_lshl_b32 s11, s11, 16
; SI-NEXT:    s_addk_i32 s8, 0x300
; SI-NEXT:    s_lshl_b32 s5, s5, 24
; SI-NEXT:    s_lshl_b32 s6, s6, 16
; SI-NEXT:    s_and_b32 s19, s19, 0xffff
; SI-NEXT:    s_or_b32 s20, s20, s21
; SI-NEXT:    s_and_b32 s13, s13, 0xffff
; SI-NEXT:    s_or_b32 s10, s10, s11
; SI-NEXT:    s_and_b32 s8, s8, 0xffff
; SI-NEXT:    s_or_b32 s5, s5, s6
; SI-NEXT:    s_or_b32 s19, s20, s19
; SI-NEXT:    s_or_b32 s10, s10, s13
; SI-NEXT:    s_or_b32 s5, s5, s8
; SI-NEXT:    s_add_i32 s4, s4, 0x3000000
; SI-NEXT:    s_add_i32 s7, s7, 0x3000000
; SI-NEXT:    s_add_i32 s12, s12, 0x3000000
; SI-NEXT:    s_add_i32 s15, s15, 0x3000000
; SI-NEXT:    s_add_i32 s16, s16, 0x3000000
; SI-NEXT:    s_add_i32 s17, s17, 0x3000000
; SI-NEXT:    s_add_i32 s18, s18, 0x3000000
; SI-NEXT:    s_add_i32 s19, s19, 0x3000000
; SI-NEXT:    s_add_i32 s10, s10, 0x3000000
; SI-NEXT:    s_add_i32 s5, s5, 0x3000000
; SI-NEXT:  .LBB73_3: ; %end
; SI-NEXT:    v_mov_b32_e32 v0, s4
; SI-NEXT:    v_mov_b32_e32 v1, s7
; SI-NEXT:    v_mov_b32_e32 v2, s12
; SI-NEXT:    v_mov_b32_e32 v3, s15
; SI-NEXT:    v_mov_b32_e32 v4, s16
; SI-NEXT:    v_mov_b32_e32 v5, s17
; SI-NEXT:    v_mov_b32_e32 v6, s18
; SI-NEXT:    v_mov_b32_e32 v7, s19
; SI-NEXT:    v_mov_b32_e32 v8, s10
; SI-NEXT:    v_mov_b32_e32 v9, s5
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v40i8_to_v5f64_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_readfirstlane_b32 s61, v26
; VI-NEXT:    v_readfirstlane_b32 s4, v25
; VI-NEXT:    v_readfirstlane_b32 s5, v24
; VI-NEXT:    v_readfirstlane_b32 s6, v23
; VI-NEXT:    v_readfirstlane_b32 s7, v22
; VI-NEXT:    v_readfirstlane_b32 s8, v21
; VI-NEXT:    v_readfirstlane_b32 s9, v20
; VI-NEXT:    v_readfirstlane_b32 s10, v19
; VI-NEXT:    v_readfirstlane_b32 s11, v18
; VI-NEXT:    v_readfirstlane_b32 s12, v17
; VI-NEXT:    v_readfirstlane_b32 s13, v16
; VI-NEXT:    v_readfirstlane_b32 s14, v15
; VI-NEXT:    v_readfirstlane_b32 s15, v14
; VI-NEXT:    v_readfirstlane_b32 s40, v13
; VI-NEXT:    v_readfirstlane_b32 s41, v12
; VI-NEXT:    v_readfirstlane_b32 s42, v11
; VI-NEXT:    v_readfirstlane_b32 s43, v10
; VI-NEXT:    v_readfirstlane_b32 s44, v9
; VI-NEXT:    v_readfirstlane_b32 s45, v8
; VI-NEXT:    v_readfirstlane_b32 s46, v7
; VI-NEXT:    v_readfirstlane_b32 s47, v6
; VI-NEXT:    v_readfirstlane_b32 s56, v5
; VI-NEXT:    v_readfirstlane_b32 s57, v4
; VI-NEXT:    v_readfirstlane_b32 s58, v3
; VI-NEXT:    v_readfirstlane_b32 s59, v2
; VI-NEXT:    v_readfirstlane_b32 s60, v1
; VI-NEXT:    s_cmp_lg_u32 s61, 0
; VI-NEXT:    v_readfirstlane_b32 s61, v0
; VI-NEXT:    s_cbranch_scc0 .LBB73_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    v_mov_b32_e32 v9, 0xc0c0004
; VI-NEXT:    v_mov_b32_e32 v1, s19
; VI-NEXT:    v_mov_b32_e32 v0, s17
; VI-NEXT:    v_perm_b32 v1, s18, v1, v9
; VI-NEXT:    v_perm_b32 v0, s16, v0, v9
; VI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT:    v_mov_b32_e32 v2, s23
; VI-NEXT:    v_or_b32_e32 v0, v0, v1
; VI-NEXT:    v_mov_b32_e32 v1, s21
; VI-NEXT:    v_perm_b32 v2, s22, v2, v9
; VI-NEXT:    v_perm_b32 v1, s20, v1, v9
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_mov_b32_e32 v3, s27
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_mov_b32_e32 v2, s25
; VI-NEXT:    v_perm_b32 v3, s26, v3, v9
; VI-NEXT:    v_perm_b32 v2, s24, v2, v9
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_mov_b32_e32 v4, s60
; VI-NEXT:    v_or_b32_e32 v2, v2, v3
; VI-NEXT:    v_mov_b32_e32 v3, s29
; VI-NEXT:    v_perm_b32 v4, s61, v4, v9
; VI-NEXT:    v_perm_b32 v3, s28, v3, v9
; VI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT:    v_mov_b32_e32 v5, s56
; VI-NEXT:    v_or_b32_e32 v3, v3, v4
; VI-NEXT:    v_mov_b32_e32 v4, s58
; VI-NEXT:    v_perm_b32 v5, s57, v5, v9
; VI-NEXT:    v_perm_b32 v4, s59, v4, v9
; VI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT:    v_mov_b32_e32 v6, s44
; VI-NEXT:    v_or_b32_e32 v4, v4, v5
; VI-NEXT:    v_mov_b32_e32 v5, s46
; VI-NEXT:    v_perm_b32 v6, s45, v6, v9
; VI-NEXT:    v_perm_b32 v5, s47, v5, v9
; VI-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT:    v_mov_b32_e32 v7, s40
; VI-NEXT:    v_or_b32_e32 v5, v5, v6
; VI-NEXT:    v_mov_b32_e32 v6, s42
; VI-NEXT:    v_perm_b32 v7, s41, v7, v9
; VI-NEXT:    v_perm_b32 v6, s43, v6, v9
; VI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT:    v_mov_b32_e32 v8, s12
; VI-NEXT:    v_or_b32_e32 v6, v6, v7
; VI-NEXT:    v_mov_b32_e32 v7, s14
; VI-NEXT:    v_perm_b32 v8, s13, v8, v9
; VI-NEXT:    v_perm_b32 v7, s15, v7, v9
; VI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT:    v_mov_b32_e32 v10, s8
; VI-NEXT:    v_or_b32_e32 v7, v7, v8
; VI-NEXT:    v_mov_b32_e32 v8, s10
; VI-NEXT:    v_perm_b32 v10, s9, v10, v9
; VI-NEXT:    v_perm_b32 v8, s11, v8, v9
; VI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT:    v_or_b32_e32 v8, v8, v10
; VI-NEXT:    v_mov_b32_e32 v10, s6
; VI-NEXT:    v_mov_b32_e32 v11, s4
; VI-NEXT:    v_perm_b32 v10, s7, v10, v9
; VI-NEXT:    v_perm_b32 v9, s5, v11, v9
; VI-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT:    v_or_b32_e32 v9, v10, v9
; VI-NEXT:    s_setpc_b64 s[30:31]
; VI-NEXT:  .LBB73_2: ; %cmp.true
; VI-NEXT:    s_add_i32 s16, s16, 3
; VI-NEXT:    v_mov_b32_e32 v0, s17
; VI-NEXT:    v_mov_b32_e32 v9, 0xc0c0004
; VI-NEXT:    s_add_i32 s18, s18, 3
; VI-NEXT:    v_mov_b32_e32 v1, s19
; VI-NEXT:    v_perm_b32 v0, s16, v0, v9
; VI-NEXT:    v_perm_b32 v1, s18, v1, v9
; VI-NEXT:    v_add_u32_e32 v0, vcc, 0x300, v0
; VI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s20, s20, 3
; VI-NEXT:    v_mov_b32_e32 v1, s21
; VI-NEXT:    s_add_i32 s22, s22, 3
; VI-NEXT:    v_mov_b32_e32 v2, s23
; VI-NEXT:    v_perm_b32 v1, s20, v1, v9
; VI-NEXT:    v_perm_b32 v2, s22, v2, v9
; VI-NEXT:    v_add_u32_e32 v1, vcc, 0x300, v1
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s24, s24, 3
; VI-NEXT:    v_mov_b32_e32 v2, s25
; VI-NEXT:    s_add_i32 s26, s26, 3
; VI-NEXT:    v_mov_b32_e32 v3, s27
; VI-NEXT:    v_perm_b32 v2, s24, v2, v9
; VI-NEXT:    v_perm_b32 v3, s26, v3, v9
; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x300, v2
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s28, s28, 3
; VI-NEXT:    v_mov_b32_e32 v3, s29
; VI-NEXT:    s_add_i32 s61, s61, 3
; VI-NEXT:    v_mov_b32_e32 v4, s60
; VI-NEXT:    v_perm_b32 v3, s28, v3, v9
; VI-NEXT:    v_perm_b32 v4, s61, v4, v9
; VI-NEXT:    v_add_u32_e32 v3, vcc, 0x300, v3
; VI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT:    v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s59, s59, 3
; VI-NEXT:    v_mov_b32_e32 v4, s58
; VI-NEXT:    s_add_i32 s57, s57, 3
; VI-NEXT:    v_mov_b32_e32 v5, s56
; VI-NEXT:    v_perm_b32 v4, s59, v4, v9
; VI-NEXT:    v_perm_b32 v5, s57, v5, v9
; VI-NEXT:    v_add_u32_e32 v4, vcc, 0x300, v4
; VI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT:    v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s47, s47, 3
; VI-NEXT:    v_mov_b32_e32 v5, s46
; VI-NEXT:    s_add_i32 s45, s45, 3
; VI-NEXT:    v_mov_b32_e32 v6, s44
; VI-NEXT:    v_perm_b32 v5, s47, v5, v9
; VI-NEXT:    v_perm_b32 v6, s45, v6, v9
; VI-NEXT:    v_add_u32_e32 v5, vcc, 0x300, v5
; VI-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT:    v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s43, s43, 3
; VI-NEXT:    v_mov_b32_e32 v6, s42
; VI-NEXT:    s_add_i32 s41, s41, 3
; VI-NEXT:    v_mov_b32_e32 v7, s40
; VI-NEXT:    v_perm_b32 v6, s43, v6, v9
; VI-NEXT:    v_perm_b32 v7, s41, v7, v9
; VI-NEXT:    v_add_u32_e32 v6, vcc, 0x300, v6
; VI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT:    v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s15, s15, 3
; VI-NEXT:    v_mov_b32_e32 v7, s14
; VI-NEXT:    s_add_i32 s13, s13, 3
; VI-NEXT:    v_mov_b32_e32 v8, s12
; VI-NEXT:    v_perm_b32 v7, s15, v7, v9
; VI-NEXT:    v_perm_b32 v8, s13, v8, v9
; VI-NEXT:    v_add_u32_e32 v7, vcc, 0x300, v7
; VI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT:    v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s11, s11, 3
; VI-NEXT:    v_mov_b32_e32 v8, s10
; VI-NEXT:    s_add_i32 s9, s9, 3
; VI-NEXT:    v_mov_b32_e32 v10, s8
; VI-NEXT:    v_perm_b32 v8, s11, v8, v9
; VI-NEXT:    v_perm_b32 v10, s9, v10, v9
; VI-NEXT:    v_add_u32_e32 v8, vcc, 0x300, v8
; VI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT:    v_or_b32_sdwa v8, v10, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s7, s7, 3
; VI-NEXT:    v_mov_b32_e32 v10, s6
; VI-NEXT:    s_add_i32 s5, s5, 3
; VI-NEXT:    v_mov_b32_e32 v11, s4
; VI-NEXT:    v_perm_b32 v10, s7, v10, v9
; VI-NEXT:    v_perm_b32 v9, s5, v11, v9
; VI-NEXT:    v_add_u32_e32 v10, vcc, 0x300, v10
; VI-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT:    v_or_b32_sdwa v9, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    v_add_u32_e32 v0, vcc, 0x3000000, v0
; VI-NEXT:    v_add_u32_e32 v1, vcc, 0x3000000, v1
; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x3000000, v2
; VI-NEXT:    v_add_u32_e32 v3, vcc, 0x3000000, v3
; VI-NEXT:    v_add_u32_e32 v4, vcc, 0x3000000, v4
; VI-NEXT:    v_add_u32_e32 v5, vcc, 0x3000000, v5
; VI-NEXT:    v_add_u32_e32 v6, vcc, 0x3000000, v6
; VI-NEXT:    v_add_u32_e32 v7, vcc, 0x3000000, v7
; VI-NEXT:    v_add_u32_e32 v8, vcc, 0x3000000, v8
; VI-NEXT:    v_add_u32_e32 v9, vcc, 0x3000000, v9
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v40i8_to_v5f64_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_readfirstlane_b32 s61, v26
; GFX9-NEXT:    v_readfirstlane_b32 s4, v25
; GFX9-NEXT:    v_readfirstlane_b32 s5, v24
; GFX9-NEXT:    v_readfirstlane_b32 s6, v23
; GFX9-NEXT:    v_readfirstlane_b32 s7, v22
; GFX9-NEXT:    v_readfirstlane_b32 s8, v21
; GFX9-NEXT:    v_readfirstlane_b32 s9, v20
; GFX9-NEXT:    v_readfirstlane_b32 s10, v19
; GFX9-NEXT:    v_readfirstlane_b32 s11, v18
; GFX9-NEXT:    v_readfirstlane_b32 s12, v17
; GFX9-NEXT:    v_readfirstlane_b32 s13, v16
; GFX9-NEXT:    v_readfirstlane_b32 s14, v15
; GFX9-NEXT:    v_readfirstlane_b32 s15, v14
; GFX9-NEXT:    v_readfirstlane_b32 s40, v13
; GFX9-NEXT:    v_readfirstlane_b32 s41, v12
; GFX9-NEXT:    v_readfirstlane_b32 s42, v11
; GFX9-NEXT:    v_readfirstlane_b32 s43, v10
; GFX9-NEXT:    v_readfirstlane_b32 s44, v9
; GFX9-NEXT:    v_readfirstlane_b32 s45, v8
; GFX9-NEXT:    v_readfirstlane_b32 s46, v7
; GFX9-NEXT:    v_readfirstlane_b32 s47, v6
; GFX9-NEXT:    v_readfirstlane_b32 s56, v5
; GFX9-NEXT:    v_readfirstlane_b32 s57, v4
; GFX9-NEXT:    v_readfirstlane_b32 s58, v3
; GFX9-NEXT:    v_readfirstlane_b32 s59, v2
; GFX9-NEXT:    v_readfirstlane_b32 s60, v1
; GFX9-NEXT:    s_cmp_lg_u32 s61, 0
; GFX9-NEXT:    v_readfirstlane_b32 s61, v0
; GFX9-NEXT:    s_cbranch_scc0 .LBB73_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    v_mov_b32_e32 v9, 0xc0c0004
; GFX9-NEXT:    v_mov_b32_e32 v1, s19
; GFX9-NEXT:    v_mov_b32_e32 v0, s17
; GFX9-NEXT:    v_perm_b32 v1, s18, v1, v9
; GFX9-NEXT:    v_perm_b32 v0, s16, v0, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT:    v_mov_b32_e32 v2, s23
; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
; GFX9-NEXT:    v_mov_b32_e32 v1, s21
; GFX9-NEXT:    v_perm_b32 v2, s22, v2, v9
; GFX9-NEXT:    v_perm_b32 v1, s20, v1, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT:    v_mov_b32_e32 v3, s27
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v2
; GFX9-NEXT:    v_mov_b32_e32 v2, s25
; GFX9-NEXT:    v_perm_b32 v3, s26, v3, v9
; GFX9-NEXT:    v_perm_b32 v2, s24, v2, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT:    v_mov_b32_e32 v4, s60
; GFX9-NEXT:    v_or_b32_e32 v2, v2, v3
; GFX9-NEXT:    v_mov_b32_e32 v3, s29
; GFX9-NEXT:    v_perm_b32 v4, s61, v4, v9
; GFX9-NEXT:    v_perm_b32 v3, s28, v3, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; GFX9-NEXT:    v_mov_b32_e32 v5, s56
; GFX9-NEXT:    v_or_b32_e32 v3, v3, v4
; GFX9-NEXT:    v_mov_b32_e32 v4, s58
; GFX9-NEXT:    v_perm_b32 v5, s57, v5, v9
; GFX9-NEXT:    v_perm_b32 v4, s59, v4, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; GFX9-NEXT:    v_mov_b32_e32 v6, s44
; GFX9-NEXT:    v_or_b32_e32 v4, v4, v5
; GFX9-NEXT:    v_mov_b32_e32 v5, s46
; GFX9-NEXT:    v_perm_b32 v6, s45, v6, v9
; GFX9-NEXT:    v_perm_b32 v5, s47, v5, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; GFX9-NEXT:    v_mov_b32_e32 v7, s40
; GFX9-NEXT:    v_or_b32_e32 v5, v5, v6
; GFX9-NEXT:    v_mov_b32_e32 v6, s42
; GFX9-NEXT:    v_perm_b32 v7, s41, v7, v9
; GFX9-NEXT:    v_perm_b32 v6, s43, v6, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; GFX9-NEXT:    v_mov_b32_e32 v8, s12
; GFX9-NEXT:    v_or_b32_e32 v6, v6, v7
; GFX9-NEXT:    v_mov_b32_e32 v7, s14
; GFX9-NEXT:    v_perm_b32 v8, s13, v8, v9
; GFX9-NEXT:    v_perm_b32 v7, s15, v7, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; GFX9-NEXT:    v_mov_b32_e32 v10, s8
; GFX9-NEXT:    v_or_b32_e32 v7, v7, v8
; GFX9-NEXT:    v_mov_b32_e32 v8, s10
; GFX9-NEXT:    v_perm_b32 v10, s9, v10, v9
; GFX9-NEXT:    v_perm_b32 v8, s11, v8, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; GFX9-NEXT:    v_or_b32_e32 v8, v8, v10
; GFX9-NEXT:    v_mov_b32_e32 v10, s6
; GFX9-NEXT:    v_mov_b32_e32 v11, s4
; GFX9-NEXT:    v_perm_b32 v10, s7, v10, v9
; GFX9-NEXT:    v_perm_b32 v9, s5, v11, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; GFX9-NEXT:    v_or_b32_e32 v9, v10, v9
; GFX9-NEXT:    s_setpc_b64 s[30:31]
; GFX9-NEXT:  .LBB73_2: ; %cmp.true
; GFX9-NEXT:    s_add_i32 s16, s16, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s17
; GFX9-NEXT:    v_mov_b32_e32 v9, 0xc0c0004
; GFX9-NEXT:    s_add_i32 s18, s18, 3
; GFX9-NEXT:    v_mov_b32_e32 v1, s19
; GFX9-NEXT:    v_perm_b32 v0, s16, v0, v9
; GFX9-NEXT:    s_movk_i32 s16, 0x300
; GFX9-NEXT:    v_perm_b32 v1, s18, v1, v9
; GFX9-NEXT:    v_add_u32_e32 v0, 0x300, v0
; GFX9-NEXT:    v_add_u32_sdwa v1, v1, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s20, s20, 3
; GFX9-NEXT:    v_mov_b32_e32 v1, s21
; GFX9-NEXT:    s_add_i32 s22, s22, 3
; GFX9-NEXT:    v_mov_b32_e32 v2, s23
; GFX9-NEXT:    v_perm_b32 v1, s20, v1, v9
; GFX9-NEXT:    v_perm_b32 v2, s22, v2, v9
; GFX9-NEXT:    v_add_u32_e32 v1, 0x300, v1
; GFX9-NEXT:    v_add_u32_sdwa v2, v2, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s24, s24, 3
; GFX9-NEXT:    v_mov_b32_e32 v2, s25
; GFX9-NEXT:    s_add_i32 s26, s26, 3
; GFX9-NEXT:    v_mov_b32_e32 v3, s27
; GFX9-NEXT:    v_perm_b32 v2, s24, v2, v9
; GFX9-NEXT:    v_perm_b32 v3, s26, v3, v9
; GFX9-NEXT:    v_add_u32_e32 v2, 0x300, v2
; GFX9-NEXT:    v_add_u32_sdwa v3, v3, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s28, s28, 3
; GFX9-NEXT:    v_mov_b32_e32 v3, s29
; GFX9-NEXT:    s_add_i32 s61, s61, 3
; GFX9-NEXT:    v_mov_b32_e32 v4, s60
; GFX9-NEXT:    v_perm_b32 v3, s28, v3, v9
; GFX9-NEXT:    v_perm_b32 v4, s61, v4, v9
; GFX9-NEXT:    v_add_u32_e32 v3, 0x300, v3
; GFX9-NEXT:    v_add_u32_sdwa v4, v4, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s59, s59, 3
; GFX9-NEXT:    v_mov_b32_e32 v4, s58
; GFX9-NEXT:    s_add_i32 s57, s57, 3
; GFX9-NEXT:    v_mov_b32_e32 v5, s56
; GFX9-NEXT:    v_perm_b32 v4, s59, v4, v9
; GFX9-NEXT:    v_perm_b32 v5, s57, v5, v9
; GFX9-NEXT:    v_add_u32_e32 v4, 0x300, v4
; GFX9-NEXT:    v_add_u32_sdwa v5, v5, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s47, s47, 3
; GFX9-NEXT:    v_mov_b32_e32 v5, s46
; GFX9-NEXT:    s_add_i32 s45, s45, 3
; GFX9-NEXT:    v_mov_b32_e32 v6, s44
; GFX9-NEXT:    v_perm_b32 v5, s47, v5, v9
; GFX9-NEXT:    v_perm_b32 v6, s45, v6, v9
; GFX9-NEXT:    v_add_u32_e32 v5, 0x300, v5
; GFX9-NEXT:    v_add_u32_sdwa v6, v6, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v5, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s43, s43, 3
; GFX9-NEXT:    v_mov_b32_e32 v6, s42
; GFX9-NEXT:    s_add_i32 s41, s41, 3
; GFX9-NEXT:    v_mov_b32_e32 v7, s40
; GFX9-NEXT:    v_perm_b32 v6, s43, v6, v9
; GFX9-NEXT:    v_perm_b32 v7, s41, v7, v9
; GFX9-NEXT:    v_add_u32_e32 v6, 0x300, v6
; GFX9-NEXT:    v_add_u32_sdwa v7, v7, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v6, v6, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s15, s15, 3
; GFX9-NEXT:    v_mov_b32_e32 v7, s14
; GFX9-NEXT:    s_add_i32 s13, s13, 3
; GFX9-NEXT:    v_mov_b32_e32 v8, s12
; GFX9-NEXT:    v_perm_b32 v7, s15, v7, v9
; GFX9-NEXT:    v_perm_b32 v8, s13, v8, v9
; GFX9-NEXT:    v_add_u32_e32 v7, 0x300, v7
; GFX9-NEXT:    v_add_u32_sdwa v8, v8, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s11, s11, 3
; GFX9-NEXT:    v_mov_b32_e32 v8, s10
; GFX9-NEXT:    s_add_i32 s9, s9, 3
; GFX9-NEXT:    v_mov_b32_e32 v10, s8
; GFX9-NEXT:    v_perm_b32 v8, s11, v8, v9
; GFX9-NEXT:    v_perm_b32 v10, s9, v10, v9
; GFX9-NEXT:    v_add_u32_e32 v8, 0x300, v8
; GFX9-NEXT:    v_add_u32_sdwa v10, v10, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v8, v8, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s7, s7, 3
; GFX9-NEXT:    v_mov_b32_e32 v10, s6
; GFX9-NEXT:    s_add_i32 s5, s5, 3
; GFX9-NEXT:    v_mov_b32_e32 v11, s4
; GFX9-NEXT:    v_perm_b32 v10, s7, v10, v9
; GFX9-NEXT:    v_perm_b32 v9, s5, v11, v9
; GFX9-NEXT:    v_add_u32_e32 v10, 0x300, v10
; GFX9-NEXT:    v_add_u32_sdwa v9, v9, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v40i8_to_v5f64_scalar:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s58, v22
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s4, v21
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s5, v20
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s6, v19
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s7, v18
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s9, v17
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s10, v16
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s8, v15
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s11, v14
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s12, v13
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s13, v12
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s14, v11
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s15, v10
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s40, v9
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s41, v8
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s42, v7
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s43, v6
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s44, v5
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s45, v4
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s46, v3
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s47, v2
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s56, v1
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s57, v0
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v5, 0xc0c0004
; GFX11-TRUE16-NEXT:    s_cmp_lg_u32 s58, 0
; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB73_2
; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_perm_b32 v1, s2, s3, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v3, s18, s19, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, s22, s23, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v8, s26, s27, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v10, s57, s56, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v0, s0, s1, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v2, s16, s17, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v4, s20, s21, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, s24, s25, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v9, s28, s29, v5
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v1
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v2, v3
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v4, v6
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, s45, s44, v5
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v7, v8
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v9, v10
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, s41, s40, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v10, s13, s12, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v11, s10, s9, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v13, s5, s4, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v8, s47, s46, v5
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; GFX11-TRUE16-NEXT:    v_perm_b32 v9, s43, s42, v5
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; GFX11-TRUE16-NEXT:    v_perm_b32 v12, s15, s14, v5
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT:    v_perm_b32 v14, s11, s8, v5
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; GFX11-TRUE16-NEXT:    v_perm_b32 v15, s7, s6, v5
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v8, v6
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v9, v7
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v12, v10
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v14, v11
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v15, v13
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT:  .LBB73_2: ; %cmp.true
; GFX11-TRUE16-NEXT:    s_add_i32 s0, s0, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s16, s16, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s18, s18, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s20, s20, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s22, s22, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s24, s24, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s26, s26, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s28, s28, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s57, s57, 3
; GFX11-TRUE16-NEXT:    v_perm_b32 v0, s0, s1, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v1, s2, s3, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v2, s16, s17, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v3, s18, s19, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v4, s20, s21, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, s22, s23, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, s24, s25, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v8, s26, s27, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v9, s28, s29, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v10, s57, s56, v5
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v4, 0x300, v4
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v6, 0x300, v6
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v8, 0x300, v8
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v9, 0x300, v9
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v10, 0x300, v10
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT:    s_add_i32 s47, s47, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s45, s45, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s43, s43, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s41, s41, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s15, s15, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s13, s13, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s11, s11, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s10, s10, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s7, s7, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s5, s5, 3
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v1
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v2, v3
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v4, v6
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v7, v8
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v9, v10
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, s47, s46, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, s45, s44, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v8, s43, s42, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v9, s41, s40, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v10, s15, s14, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v11, s13, s12, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v12, s11, s8, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v13, s10, s9, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v14, s7, s6, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v5, s5, s4, v5
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v6, 0x300, v6
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v8, 0x300, v8
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v9, 0x300, v9
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v10, 0x300, v10
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v11, 0x300, v11
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v13, 0x300, v13
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v14, 0x300, v14
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v5
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v6, v7
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v8, v9
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v10, v11
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v12, v13
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v14, v15
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v40i8_to_v5f64_scalar:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s58, v22
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s5, v21
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s6, v20
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s4, v19
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s7, v18
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s9, v17
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s11, v16
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s8, v15
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s10, v14
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s12, v13
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s13, v12
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s14, v11
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s15, v10
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s40, v9
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s42, v8
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s41, v7
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s43, v6
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s45, v5
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s46, v4
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s44, v3
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s47, v2
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s56, v1
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s57, v0
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, 0xc0c0004
; GFX11-FAKE16-NEXT:    s_cmp_lg_u32 s58, 0
; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB73_2
; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_perm_b32 v1, s2, s3, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v3, s18, s19, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, s22, s23, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, s26, s27, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v10, s57, s56, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v0, s0, s1, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v2, s16, s17, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v4, s20, s21, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, s24, s25, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, s28, s29, v5
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v6
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, s46, s45, v5
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v7, v8
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v9, v10
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, s42, s40, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v10, s13, s12, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v11, s11, s9, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v13, s6, s5, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, s47, s44, v5
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, s43, s41, v5
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; GFX11-FAKE16-NEXT:    v_perm_b32 v12, s15, s14, v5
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; GFX11-FAKE16-NEXT:    v_perm_b32 v14, s10, s8, v5
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; GFX11-FAKE16-NEXT:    v_perm_b32 v15, s7, s4, v5
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v8, v6
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v9, v7
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v12, v10
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v14, v11
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v15, v13
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT:  .LBB73_2: ; %cmp.true
; GFX11-FAKE16-NEXT:    s_add_i32 s0, s0, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s2, s2, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s16, s16, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s18, s18, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s20, s20, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s22, s22, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s24, s24, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s26, s26, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s28, s28, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s57, s57, 3
; GFX11-FAKE16-NEXT:    v_perm_b32 v0, s0, s1, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v1, s2, s3, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v2, s16, s17, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v3, s18, s19, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v4, s20, s21, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, s22, s23, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, s24, s25, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, s26, s27, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, s28, s29, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v10, s57, s56, v5
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, 0x300, v4
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v6, 0x300, v6
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v8, 0x300, v8
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v9, 0x300, v9
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v10, 0x300, v10
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; GFX11-FAKE16-NEXT:    s_add_i32 s47, s47, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s46, s46, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s43, s43, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s42, s42, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s15, s15, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s13, s13, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s10, s10, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s11, s11, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s7, s7, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s6, s6, 3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v6
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v7, v8
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v9, v10
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, s47, s44, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, s46, s45, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, s43, s41, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, s42, s40, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v10, s15, s14, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v11, s13, s12, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v12, s10, s8, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v13, s11, s9, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v14, s7, s4, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v5, s6, s5, v5
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v6, 0x300, v6
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v8, 0x300, v8
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v9, 0x300, v9
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v10, 0x300, v10
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v11, 0x300, v11
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v13, 0x300, v13
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v14, 0x300, v14
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v5
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v6, v7
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v8, v9
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v10, v11
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v12, v13
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v14, v15
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <40 x i8> %a, splat (i8 3)
  %a2 = bitcast <40 x i8> %a1 to <5 x double>
  br label %end

cmp.false:
  %a3 = bitcast <40 x i8> %a to <5 x double>
  br label %end

end:
  %phi = phi <5 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <5 x double> %phi
}

define <40 x i8> @bitcast_v5f64_to_v40i8(<5 x double> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v5f64_to_v40i8:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
; SI-NEXT:    ; implicit-def: $vgpr35
; SI-NEXT:    ; implicit-def: $vgpr33
; SI-NEXT:    ; implicit-def: $vgpr32
; SI-NEXT:    ; implicit-def: $vgpr48
; SI-NEXT:    ; implicit-def: $vgpr39
; SI-NEXT:    ; implicit-def: $vgpr38
; SI-NEXT:    ; implicit-def: $vgpr28
; SI-NEXT:    ; implicit-def: $vgpr27
; SI-NEXT:    ; implicit-def: $vgpr26
; SI-NEXT:    ; implicit-def: $vgpr37
; SI-NEXT:    ; implicit-def: $vgpr36
; SI-NEXT:    ; implicit-def: $vgpr34
; SI-NEXT:    ; implicit-def: $vgpr22
; SI-NEXT:    ; implicit-def: $vgpr21
; SI-NEXT:    ; implicit-def: $vgpr19
; SI-NEXT:    ; implicit-def: $vgpr31
; SI-NEXT:    ; implicit-def: $vgpr30
; SI-NEXT:    ; implicit-def: $vgpr29
; SI-NEXT:    ; implicit-def: $vgpr16
; SI-NEXT:    ; implicit-def: $vgpr15
; SI-NEXT:    ; implicit-def: $vgpr14
; SI-NEXT:    ; implicit-def: $vgpr25
; SI-NEXT:    ; implicit-def: $vgpr24
; SI-NEXT:    ; implicit-def: $vgpr23
; SI-NEXT:    ; implicit-def: $vgpr13
; SI-NEXT:    ; implicit-def: $vgpr12
; SI-NEXT:    ; implicit-def: $vgpr11
; SI-NEXT:    ; implicit-def: $vgpr20
; SI-NEXT:    ; implicit-def: $vgpr18
; SI-NEXT:    ; implicit-def: $vgpr17
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB74_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    v_alignbit_b32 v11, v10, v9, 24
; SI-NEXT:    v_alignbit_b32 v12, v10, v9, 16
; SI-NEXT:    v_alignbit_b32 v13, v10, v9, 8
; SI-NEXT:    v_alignbit_b32 v14, v8, v7, 24
; SI-NEXT:    v_alignbit_b32 v15, v8, v7, 16
; SI-NEXT:    v_alignbit_b32 v16, v8, v7, 8
; SI-NEXT:    v_alignbit_b32 v19, v6, v5, 24
; SI-NEXT:    v_alignbit_b32 v21, v6, v5, 16
; SI-NEXT:    v_alignbit_b32 v22, v6, v5, 8
; SI-NEXT:    v_alignbit_b32 v26, v4, v3, 24
; SI-NEXT:    v_alignbit_b32 v27, v4, v3, 16
; SI-NEXT:    v_alignbit_b32 v28, v4, v3, 8
; SI-NEXT:    v_alignbit_b32 v32, v2, v1, 24
; SI-NEXT:    v_alignbit_b32 v33, v2, v1, 16
; SI-NEXT:    v_alignbit_b32 v35, v2, v1, 8
; SI-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; SI-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; SI-NEXT:    v_lshrrev_b32_e32 v20, 8, v10
; SI-NEXT:    v_lshrrev_b32_e32 v23, 24, v8
; SI-NEXT:    v_lshrrev_b32_e32 v24, 16, v8
; SI-NEXT:    v_lshrrev_b32_e32 v25, 8, v8
; SI-NEXT:    v_lshrrev_b32_e32 v29, 24, v6
; SI-NEXT:    v_lshrrev_b32_e32 v30, 16, v6
; SI-NEXT:    v_lshrrev_b32_e32 v31, 8, v6
; SI-NEXT:    v_lshrrev_b32_e32 v34, 24, v4
; SI-NEXT:    v_lshrrev_b32_e32 v36, 16, v4
; SI-NEXT:    v_lshrrev_b32_e32 v37, 8, v4
; SI-NEXT:    v_lshrrev_b32_e32 v38, 24, v2
; SI-NEXT:    v_lshrrev_b32_e32 v39, 16, v2
; SI-NEXT:    v_lshrrev_b32_e32 v48, 8, v2
; SI-NEXT:  .LBB74_2: ; %Flow
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB74_4
; SI-NEXT:  ; %bb.3: ; %cmp.true
; SI-NEXT:    v_add_f64 v[1:2], v[1:2], 1.0
; SI-NEXT:    v_add_f64 v[3:4], v[3:4], 1.0
; SI-NEXT:    v_add_f64 v[5:6], v[5:6], 1.0
; SI-NEXT:    v_add_f64 v[9:10], v[9:10], 1.0
; SI-NEXT:    v_add_f64 v[7:8], v[7:8], 1.0
; SI-NEXT:    v_alignbit_b32 v11, v10, v9, 24
; SI-NEXT:    v_alignbit_b32 v12, v10, v9, 16
; SI-NEXT:    v_alignbit_b32 v13, v10, v9, 8
; SI-NEXT:    v_alignbit_b32 v14, v8, v7, 24
; SI-NEXT:    v_alignbit_b32 v15, v8, v7, 16
; SI-NEXT:    v_alignbit_b32 v16, v8, v7, 8
; SI-NEXT:    v_alignbit_b32 v19, v6, v5, 24
; SI-NEXT:    v_alignbit_b32 v21, v6, v5, 16
; SI-NEXT:    v_alignbit_b32 v22, v6, v5, 8
; SI-NEXT:    v_alignbit_b32 v26, v4, v3, 24
; SI-NEXT:    v_alignbit_b32 v27, v4, v3, 16
; SI-NEXT:    v_alignbit_b32 v28, v4, v3, 8
; SI-NEXT:    v_alignbit_b32 v32, v2, v1, 24
; SI-NEXT:    v_alignbit_b32 v33, v2, v1, 16
; SI-NEXT:    v_alignbit_b32 v35, v2, v1, 8
; SI-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; SI-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; SI-NEXT:    v_lshrrev_b32_e32 v20, 8, v10
; SI-NEXT:    v_lshrrev_b32_e32 v23, 24, v8
; SI-NEXT:    v_lshrrev_b32_e32 v24, 16, v8
; SI-NEXT:    v_lshrrev_b32_e32 v25, 8, v8
; SI-NEXT:    v_lshrrev_b32_e32 v29, 24, v6
; SI-NEXT:    v_lshrrev_b32_e32 v30, 16, v6
; SI-NEXT:    v_lshrrev_b32_e32 v31, 8, v6
; SI-NEXT:    v_lshrrev_b32_e32 v34, 24, v4
; SI-NEXT:    v_lshrrev_b32_e32 v36, 16, v4
; SI-NEXT:    v_lshrrev_b32_e32 v37, 8, v4
; SI-NEXT:    v_lshrrev_b32_e32 v38, 24, v2
; SI-NEXT:    v_lshrrev_b32_e32 v39, 16, v2
; SI-NEXT:    v_lshrrev_b32_e32 v48, 8, v2
; SI-NEXT:  .LBB74_4: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1
; SI-NEXT:    v_lshlrev_b32_e32 v35, 8, v35
; SI-NEXT:    v_and_b32_e32 v33, 0xff, v33
; SI-NEXT:    v_or_b32_e32 v1, v1, v35
; SI-NEXT:    v_lshlrev_b32_e32 v33, 16, v33
; SI-NEXT:    v_lshlrev_b32_e32 v32, 24, v32
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v32, v32, v33
; SI-NEXT:    v_or_b32_e32 v1, v1, v32
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v2
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v48
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v39
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v32, 24, v38
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v32, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v3
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v28
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v27
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v26
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v4
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v37
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v36
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v34
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v5
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v22
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v21
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v19
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v6
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v31
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v30
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v29
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v7
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v16
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v15
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v14
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v8
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v25
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v24
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v23
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v9
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v13
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v12
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v11
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v10
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v20
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v18
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v17
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v5f64_to_v40i8:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
; VI-NEXT:    ; implicit-def: $vgpr16
; VI-NEXT:    ; implicit-def: $vgpr48
; VI-NEXT:    ; implicit-def: $vgpr15
; VI-NEXT:    ; implicit-def: $vgpr39
; VI-NEXT:    ; implicit-def: $vgpr38
; VI-NEXT:    ; implicit-def: $vgpr37
; VI-NEXT:    ; implicit-def: $vgpr36
; VI-NEXT:    ; implicit-def: $vgpr35
; VI-NEXT:    ; implicit-def: $vgpr14
; VI-NEXT:    ; implicit-def: $vgpr34
; VI-NEXT:    ; implicit-def: $vgpr33
; VI-NEXT:    ; implicit-def: $vgpr32
; VI-NEXT:    ; implicit-def: $vgpr31
; VI-NEXT:    ; implicit-def: $vgpr30
; VI-NEXT:    ; implicit-def: $vgpr13
; VI-NEXT:    ; implicit-def: $vgpr29
; VI-NEXT:    ; implicit-def: $vgpr28
; VI-NEXT:    ; implicit-def: $vgpr27
; VI-NEXT:    ; implicit-def: $vgpr26
; VI-NEXT:    ; implicit-def: $vgpr25
; VI-NEXT:    ; implicit-def: $vgpr12
; VI-NEXT:    ; implicit-def: $vgpr24
; VI-NEXT:    ; implicit-def: $vgpr23
; VI-NEXT:    ; implicit-def: $vgpr22
; VI-NEXT:    ; implicit-def: $vgpr21
; VI-NEXT:    ; implicit-def: $vgpr20
; VI-NEXT:    ; implicit-def: $vgpr19
; VI-NEXT:    ; implicit-def: $vgpr18
; VI-NEXT:    ; implicit-def: $vgpr17
; VI-NEXT:    ; implicit-def: $vgpr11
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB74_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; VI-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; VI-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; VI-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; VI-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; VI-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; VI-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; VI-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; VI-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
; VI-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
; VI-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
; VI-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
; VI-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
; VI-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
; VI-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
; VI-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
; VI-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
; VI-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; VI-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; VI-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; VI-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
; VI-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
; VI-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
; VI-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
; VI-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
; VI-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
; VI-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
; VI-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
; VI-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
; VI-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; VI-NEXT:  .LBB74_2: ; %Flow
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB74_4
; VI-NEXT:  ; %bb.3: ; %cmp.true
; VI-NEXT:    v_add_f64 v[9:10], v[9:10], 1.0
; VI-NEXT:    v_add_f64 v[7:8], v[7:8], 1.0
; VI-NEXT:    v_add_f64 v[5:6], v[5:6], 1.0
; VI-NEXT:    v_add_f64 v[3:4], v[3:4], 1.0
; VI-NEXT:    v_add_f64 v[1:2], v[1:2], 1.0
; VI-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; VI-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; VI-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; VI-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; VI-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; VI-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; VI-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; VI-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; VI-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
; VI-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
; VI-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
; VI-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
; VI-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
; VI-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
; VI-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
; VI-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
; VI-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
; VI-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; VI-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; VI-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; VI-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
; VI-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
; VI-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
; VI-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
; VI-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
; VI-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
; VI-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
; VI-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
; VI-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
; VI-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; VI-NEXT:  .LBB74_4: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_mov_b32 s4, 0xc0c0004
; VI-NEXT:    v_perm_b32 v15, v48, v15, s4
; VI-NEXT:    v_perm_b32 v1, v1, v16, s4
; VI-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT:    v_or_b32_e32 v1, v1, v15
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT:    v_perm_b32 v1, v2, v39, s4
; VI-NEXT:    v_perm_b32 v2, v38, v37, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v35, v14, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
; VI-NEXT:    v_perm_b32 v1, v3, v36, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v33, v32, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; VI-NEXT:    v_perm_b32 v1, v4, v34, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v30, v13, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; VI-NEXT:    v_perm_b32 v1, v5, v31, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v28, v27, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; VI-NEXT:    v_perm_b32 v1, v6, v29, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v25, v12, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; VI-NEXT:    v_perm_b32 v1, v7, v26, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v23, v22, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; VI-NEXT:    v_perm_b32 v1, v8, v24, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v20, v11, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; VI-NEXT:    v_perm_b32 v1, v9, v21, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v18, v17, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; VI-NEXT:    v_perm_b32 v1, v10, v19, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v5f64_to_v40i8:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
; GFX9-NEXT:    ; implicit-def: $vgpr16
; GFX9-NEXT:    ; implicit-def: $vgpr48
; GFX9-NEXT:    ; implicit-def: $vgpr15
; GFX9-NEXT:    ; implicit-def: $vgpr39
; GFX9-NEXT:    ; implicit-def: $vgpr38
; GFX9-NEXT:    ; implicit-def: $vgpr37
; GFX9-NEXT:    ; implicit-def: $vgpr36
; GFX9-NEXT:    ; implicit-def: $vgpr35
; GFX9-NEXT:    ; implicit-def: $vgpr14
; GFX9-NEXT:    ; implicit-def: $vgpr34
; GFX9-NEXT:    ; implicit-def: $vgpr33
; GFX9-NEXT:    ; implicit-def: $vgpr32
; GFX9-NEXT:    ; implicit-def: $vgpr31
; GFX9-NEXT:    ; implicit-def: $vgpr30
; GFX9-NEXT:    ; implicit-def: $vgpr13
; GFX9-NEXT:    ; implicit-def: $vgpr29
; GFX9-NEXT:    ; implicit-def: $vgpr28
; GFX9-NEXT:    ; implicit-def: $vgpr27
; GFX9-NEXT:    ; implicit-def: $vgpr26
; GFX9-NEXT:    ; implicit-def: $vgpr25
; GFX9-NEXT:    ; implicit-def: $vgpr12
; GFX9-NEXT:    ; implicit-def: $vgpr24
; GFX9-NEXT:    ; implicit-def: $vgpr23
; GFX9-NEXT:    ; implicit-def: $vgpr22
; GFX9-NEXT:    ; implicit-def: $vgpr21
; GFX9-NEXT:    ; implicit-def: $vgpr20
; GFX9-NEXT:    ; implicit-def: $vgpr19
; GFX9-NEXT:    ; implicit-def: $vgpr18
; GFX9-NEXT:    ; implicit-def: $vgpr17
; GFX9-NEXT:    ; implicit-def: $vgpr11
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB74_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX9-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX9-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX9-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX9-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX9-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
; GFX9-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
; GFX9-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
; GFX9-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
; GFX9-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; GFX9-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; GFX9-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
; GFX9-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
; GFX9-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
; GFX9-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX9-NEXT:  .LBB74_2: ; %Flow
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB74_4
; GFX9-NEXT:  ; %bb.3: ; %cmp.true
; GFX9-NEXT:    v_add_f64 v[9:10], v[9:10], 1.0
; GFX9-NEXT:    v_add_f64 v[7:8], v[7:8], 1.0
; GFX9-NEXT:    v_add_f64 v[5:6], v[5:6], 1.0
; GFX9-NEXT:    v_add_f64 v[3:4], v[3:4], 1.0
; GFX9-NEXT:    v_add_f64 v[1:2], v[1:2], 1.0
; GFX9-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX9-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX9-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX9-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX9-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX9-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
; GFX9-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
; GFX9-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
; GFX9-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
; GFX9-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; GFX9-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; GFX9-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
; GFX9-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
; GFX9-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
; GFX9-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX9-NEXT:  .LBB74_4: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_mov_b32 s4, 0xc0c0004
; GFX9-NEXT:    v_perm_b32 v15, v48, v15, s4
; GFX9-NEXT:    v_perm_b32 v1, v1, v16, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v15, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen
; GFX9-NEXT:    v_perm_b32 v1, v2, v39, s4
; GFX9-NEXT:    v_perm_b32 v2, v38, v37, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT:    v_perm_b32 v1, v3, v36, s4
; GFX9-NEXT:    v_perm_b32 v2, v35, v14, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT:    v_perm_b32 v1, v4, v34, s4
; GFX9-NEXT:    v_perm_b32 v2, v33, v32, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; GFX9-NEXT:    v_perm_b32 v1, v5, v31, s4
; GFX9-NEXT:    v_perm_b32 v2, v30, v13, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT:    v_perm_b32 v1, v6, v29, s4
; GFX9-NEXT:    v_perm_b32 v2, v28, v27, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; GFX9-NEXT:    v_perm_b32 v1, v7, v26, s4
; GFX9-NEXT:    v_perm_b32 v2, v25, v12, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT:    v_perm_b32 v1, v8, v24, s4
; GFX9-NEXT:    v_perm_b32 v2, v23, v22, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; GFX9-NEXT:    v_perm_b32 v1, v9, v21, s4
; GFX9-NEXT:    v_perm_b32 v2, v20, v11, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT:    v_perm_b32 v1, v10, v19, s4
; GFX9-NEXT:    v_perm_b32 v2, v18, v17, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v5f64_to_v40i8:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v11
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr11_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB74_2
; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v18, 8, v10
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v9
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v20, 24, v8
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v8
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v22, 8, v7
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v6
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v6
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v5
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v4
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v4
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v3
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v28, 24, v2
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v2
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX11-TRUE16-NEXT:  .LBB74_2: ; %Flow
; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB74_4
; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
; GFX11-TRUE16-NEXT:    v_add_f64 v[9:10], v[9:10], 1.0
; GFX11-TRUE16-NEXT:    v_add_f64 v[7:8], v[7:8], 1.0
; GFX11-TRUE16-NEXT:    v_add_f64 v[5:6], v[5:6], 1.0
; GFX11-TRUE16-NEXT:    v_add_f64 v[3:4], v[3:4], 1.0
; GFX11-TRUE16-NEXT:    v_add_f64 v[1:2], v[1:2], 1.0
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v18, 8, v10
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v9
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v20, 24, v8
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v8
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v22, 8, v7
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v6
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v6
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v5
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v4
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v4
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v3
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v28, 24, v2
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v2
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX11-TRUE16-NEXT:  .LBB74_4: ; %end
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v31.l, v1.h
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_perm_b32 v1, v1, v16, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v16, v2, v30, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v29, v3, v29, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v3.h
; GFX11-TRUE16-NEXT:    v_perm_b32 v15, v31, v15, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v31.l, v5.h
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v30.l, v4.h
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
; GFX11-TRUE16-NEXT:    v_perm_b32 v5, v5, v25, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v1, v15, 16, v1
; GFX11-TRUE16-NEXT:    v_perm_b32 v13, v31, v13, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v3, v3, v14, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v4, v4, v27, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v14, v30, v26, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v15.l, v6.h
; GFX11-TRUE16-NEXT:    v_perm_b32 v2, v2, v28, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v5, v13, 16, v5
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v7.h
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v4, v14, 16, v4
; GFX11-TRUE16-NEXT:    v_perm_b32 v14, v15, v23, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v15.l, v8.h
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v2, v2, 16, v16
; GFX11-TRUE16-NEXT:    v_perm_b32 v12, v13, v12, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v9.h
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.l, v10.h
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, v6, v24, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, v7, v22, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v8, v8, v21, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v15, v15, v20, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v9, v9, v19, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v11, v13, v11, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v10, v10, v18, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v13, v16, v17, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v3, v3, 16, v29
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v6, v14, 16, v6
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v7, v12, 16, v7
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v8, v15, 16, v8
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v9, v11, 16, v9
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v10, v13, 16, v10
; GFX11-TRUE16-NEXT:    s_clause 0x2
; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[1:4], off
; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
; GFX11-TRUE16-NEXT:    scratch_store_b64 v0, v[9:10], off offset:32
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v5f64_to_v40i8:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v11
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB74_2
; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX11-FAKE16-NEXT:  .LBB74_2: ; %Flow
; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB74_4
; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
; GFX11-FAKE16-NEXT:    v_add_f64 v[9:10], v[9:10], 1.0
; GFX11-FAKE16-NEXT:    v_add_f64 v[7:8], v[7:8], 1.0
; GFX11-FAKE16-NEXT:    v_add_f64 v[5:6], v[5:6], 1.0
; GFX11-FAKE16-NEXT:    v_add_f64 v[3:4], v[3:4], 1.0
; GFX11-FAKE16-NEXT:    v_add_f64 v[1:2], v[1:2], 1.0
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX11-FAKE16-NEXT:  .LBB74_4: ; %end
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v3, v36, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v35, v14, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v5, v31, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v30, v13, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v1, v16, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v48, v15, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v2, v39, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v16, v38, v37, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v4, v34, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v32, v33, v32, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v3, v14, 16, v3
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v5, v13, 16, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v6, v29, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v28, v27, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v7, v26, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v25, v12, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v8, v24, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v23, v22, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v15, 16, v1
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v9, v21, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v20, v11, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v10, v19, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v18, v17, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, v16, 16, v2
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v4, v32, 16, v4
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v6, v13, 16, v6
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v7, v12, 16, v7
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v8, v14, 16, v8
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v9, v11, 16, v9
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v10, v15, 16, v10
; GFX11-FAKE16-NEXT:    s_clause 0x2
; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[1:4], off
; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
; GFX11-FAKE16-NEXT:    scratch_store_b64 v0, v[9:10], off offset:32
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <5 x double> %a, splat (double 1.000000e+00)
  %a2 = bitcast <5 x double> %a1 to <40 x i8>
  br label %end

cmp.false:
  %a3 = bitcast <5 x double> %a to <40 x i8>
  br label %end

end:
  %phi = phi <40 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <40 x i8> %phi
}

define inreg <40 x i8> @bitcast_v5f64_to_v40i8_scalar(<5 x double> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v5f64_to_v40i8_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc0 .LBB75_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    s_lshr_b64 s[72:73], s[16:17], 8
; SI-NEXT:    v_mov_b32_e32 v28, s72
; SI-NEXT:    s_lshr_b64 s[72:73], s[16:17], 16
; SI-NEXT:    v_mov_b32_e32 v27, s72
; SI-NEXT:    s_lshr_b64 s[72:73], s[16:17], 24
; SI-NEXT:    v_mov_b32_e32 v26, s72
; SI-NEXT:    s_lshr_b64 s[72:73], s[18:19], 8
; SI-NEXT:    v_mov_b32_e32 v25, s72
; SI-NEXT:    s_lshr_b64 s[72:73], s[18:19], 16
; SI-NEXT:    v_mov_b32_e32 v24, s72
; SI-NEXT:    s_lshr_b64 s[72:73], s[18:19], 24
; SI-NEXT:    s_lshr_b64 s[40:41], s[24:25], 24
; SI-NEXT:    s_lshr_b64 s[42:43], s[24:25], 16
; SI-NEXT:    s_lshr_b64 s[44:45], s[24:25], 8
; SI-NEXT:    s_lshr_b64 s[46:47], s[22:23], 24
; SI-NEXT:    s_lshr_b64 s[56:57], s[22:23], 16
; SI-NEXT:    s_lshr_b64 s[58:59], s[22:23], 8
; SI-NEXT:    s_lshr_b64 s[60:61], s[20:21], 24
; SI-NEXT:    s_lshr_b64 s[62:63], s[20:21], 16
; SI-NEXT:    v_mov_b32_e32 v23, s72
; SI-NEXT:    s_lshr_b64 s[72:73], s[20:21], 8
; SI-NEXT:    s_lshr_b32 s4, s25, 24
; SI-NEXT:    s_lshr_b32 s5, s25, 16
; SI-NEXT:    s_lshr_b32 s6, s25, 8
; SI-NEXT:    s_lshr_b32 s7, s23, 24
; SI-NEXT:    s_lshr_b32 s8, s23, 16
; SI-NEXT:    s_lshr_b32 s9, s23, 8
; SI-NEXT:    s_lshr_b32 s10, s21, 24
; SI-NEXT:    s_lshr_b32 s11, s21, 16
; SI-NEXT:    s_lshr_b32 s12, s21, 8
; SI-NEXT:    s_lshr_b32 s13, s19, 24
; SI-NEXT:    s_lshr_b32 s14, s19, 16
; SI-NEXT:    s_lshr_b32 s15, s19, 8
; SI-NEXT:    s_lshr_b32 s26, s17, 24
; SI-NEXT:    s_lshr_b32 s27, s17, 16
; SI-NEXT:    s_lshr_b32 s28, s17, 8
; SI-NEXT:    v_mov_b32_e32 v21, s16
; SI-NEXT:    v_mov_b32_e32 v15, s18
; SI-NEXT:    v_mov_b32_e32 v7, s20
; SI-NEXT:    v_mov_b32_e32 v3, s22
; SI-NEXT:    v_mov_b32_e32 v1, s24
; SI-NEXT:    v_mov_b32_e32 v19, s72
; SI-NEXT:    v_mov_b32_e32 v18, s62
; SI-NEXT:    v_mov_b32_e32 v17, s60
; SI-NEXT:    v_mov_b32_e32 v13, s58
; SI-NEXT:    v_mov_b32_e32 v12, s56
; SI-NEXT:    v_mov_b32_e32 v11, s46
; SI-NEXT:    v_mov_b32_e32 v10, s44
; SI-NEXT:    v_mov_b32_e32 v9, s42
; SI-NEXT:    v_mov_b32_e32 v5, s40
; SI-NEXT:    s_branch .LBB75_3
; SI-NEXT:  .LBB75_2: ; %cmp.true
; SI-NEXT:    v_add_f64 v[15:16], s[18:19], 1.0
; SI-NEXT:    v_add_f64 v[1:2], s[24:25], 1.0
; SI-NEXT:    v_lshr_b64 v[23:24], v[15:16], 24
; SI-NEXT:    v_add_f64 v[3:4], s[22:23], 1.0
; SI-NEXT:    v_add_f64 v[7:8], s[20:21], 1.0
; SI-NEXT:    v_add_f64 v[21:22], s[16:17], 1.0
; SI-NEXT:    v_lshr_b64 v[9:10], v[1:2], 16
; SI-NEXT:    v_lshr_b64 v[24:25], v[15:16], 16
; SI-NEXT:    v_lshr_b64 v[10:11], v[1:2], 8
; SI-NEXT:    v_lshr_b64 v[25:26], v[15:16], 8
; SI-NEXT:    v_lshr_b64 v[11:12], v[3:4], 24
; SI-NEXT:    v_lshr_b64 v[17:18], v[7:8], 24
; SI-NEXT:    v_lshr_b64 v[26:27], v[21:22], 24
; SI-NEXT:    v_readfirstlane_b32 s17, v22
; SI-NEXT:    v_readfirstlane_b32 s19, v16
; SI-NEXT:    v_readfirstlane_b32 s21, v8
; SI-NEXT:    v_readfirstlane_b32 s23, v4
; SI-NEXT:    v_readfirstlane_b32 s25, v2
; SI-NEXT:    v_lshr_b64 v[12:13], v[3:4], 16
; SI-NEXT:    v_lshr_b64 v[18:19], v[7:8], 16
; SI-NEXT:    v_lshr_b64 v[27:28], v[21:22], 16
; SI-NEXT:    s_lshr_b32 s4, s25, 24
; SI-NEXT:    s_lshr_b32 s5, s25, 16
; SI-NEXT:    s_lshr_b32 s6, s25, 8
; SI-NEXT:    s_lshr_b32 s7, s23, 24
; SI-NEXT:    s_lshr_b32 s8, s23, 16
; SI-NEXT:    s_lshr_b32 s9, s23, 8
; SI-NEXT:    s_lshr_b32 s10, s21, 24
; SI-NEXT:    s_lshr_b32 s11, s21, 16
; SI-NEXT:    s_lshr_b32 s12, s21, 8
; SI-NEXT:    s_lshr_b32 s13, s19, 24
; SI-NEXT:    s_lshr_b32 s14, s19, 16
; SI-NEXT:    s_lshr_b32 s15, s19, 8
; SI-NEXT:    s_lshr_b32 s26, s17, 24
; SI-NEXT:    s_lshr_b32 s27, s17, 16
; SI-NEXT:    s_lshr_b32 s28, s17, 8
; SI-NEXT:    v_lshr_b64 v[5:6], v[1:2], 24
; SI-NEXT:    v_lshr_b64 v[13:14], v[3:4], 8
; SI-NEXT:    v_lshr_b64 v[19:20], v[7:8], 8
; SI-NEXT:    v_lshr_b64 v[28:29], v[21:22], 8
; SI-NEXT:  .LBB75_3: ; %end
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v21
; SI-NEXT:    v_lshlrev_b32_e32 v4, 8, v28
; SI-NEXT:    s_and_b32 s16, s17, 0xff
; SI-NEXT:    s_lshl_b32 s17, s28, 8
; SI-NEXT:    v_or_b32_e32 v2, v2, v4
; SI-NEXT:    v_and_b32_e32 v4, 0xff, v27
; SI-NEXT:    s_or_b32 s16, s16, s17
; SI-NEXT:    s_and_b32 s17, s27, 0xff
; SI-NEXT:    v_lshlrev_b32_e32 v6, 24, v26
; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT:    s_lshl_b32 s17, s17, 16
; SI-NEXT:    s_lshl_b32 s18, s26, 24
; SI-NEXT:    v_or_b32_e32 v4, v6, v4
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    s_and_b32 s16, s16, 0xffff
; SI-NEXT:    s_or_b32 s17, s18, s17
; SI-NEXT:    v_or_b32_e32 v2, v2, v4
; SI-NEXT:    s_or_b32 s16, s16, s17
; SI-NEXT:    buffer_store_dword v2, v0, s[0:3], 0 offen
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_mov_b32_e32 v2, s16
; SI-NEXT:    buffer_store_dword v2, v0, s[0:3], 0 offen offset:4
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v15
; SI-NEXT:    v_lshlrev_b32_e32 v4, 8, v25
; SI-NEXT:    v_or_b32_e32 v2, v2, v4
; SI-NEXT:    v_and_b32_e32 v4, 0xff, v24
; SI-NEXT:    s_and_b32 s16, s19, 0xff
; SI-NEXT:    s_lshl_b32 s15, s15, 8
; SI-NEXT:    s_and_b32 s14, s14, 0xff
; SI-NEXT:    v_lshlrev_b32_e32 v6, 24, v23
; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT:    s_or_b32 s15, s16, s15
; SI-NEXT:    s_lshl_b32 s14, s14, 16
; SI-NEXT:    s_lshl_b32 s13, s13, 24
; SI-NEXT:    v_or_b32_e32 v4, v6, v4
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    s_and_b32 s15, s15, 0xffff
; SI-NEXT:    s_or_b32 s13, s13, s14
; SI-NEXT:    v_or_b32_e32 v2, v2, v4
; SI-NEXT:    s_or_b32 s13, s15, s13
; SI-NEXT:    buffer_store_dword v2, v0, s[0:3], 0 offen offset:8
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_mov_b32_e32 v2, s13
; SI-NEXT:    buffer_store_dword v2, v0, s[0:3], 0 offen offset:12
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v7
; SI-NEXT:    v_lshlrev_b32_e32 v4, 8, v19
; SI-NEXT:    v_or_b32_e32 v2, v2, v4
; SI-NEXT:    v_and_b32_e32 v4, 0xff, v18
; SI-NEXT:    s_and_b32 s13, s21, 0xff
; SI-NEXT:    s_lshl_b32 s12, s12, 8
; SI-NEXT:    s_and_b32 s11, s11, 0xff
; SI-NEXT:    v_lshlrev_b32_e32 v6, 24, v17
; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT:    s_or_b32 s12, s13, s12
; SI-NEXT:    s_lshl_b32 s11, s11, 16
; SI-NEXT:    s_lshl_b32 s10, s10, 24
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    v_or_b32_e32 v4, v6, v4
; SI-NEXT:    s_and_b32 s12, s12, 0xffff
; SI-NEXT:    s_or_b32 s10, s10, s11
; SI-NEXT:    v_or_b32_e32 v2, v2, v4
; SI-NEXT:    s_or_b32 s10, s12, s10
; SI-NEXT:    buffer_store_dword v2, v0, s[0:3], 0 offen offset:16
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_mov_b32_e32 v2, s10
; SI-NEXT:    buffer_store_dword v2, v0, s[0:3], 0 offen offset:20
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v3
; SI-NEXT:    v_lshlrev_b32_e32 v3, 8, v13
; SI-NEXT:    v_or_b32_e32 v2, v2, v3
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v12
; SI-NEXT:    s_and_b32 s10, s23, 0xff
; SI-NEXT:    s_lshl_b32 s9, s9, 8
; SI-NEXT:    s_and_b32 s8, s8, 0xff
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_lshlrev_b32_e32 v4, 24, v11
; SI-NEXT:    s_or_b32 s9, s10, s9
; SI-NEXT:    s_lshl_b32 s8, s8, 16
; SI-NEXT:    s_lshl_b32 s7, s7, 24
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    v_or_b32_e32 v3, v4, v3
; SI-NEXT:    s_and_b32 s9, s9, 0xffff
; SI-NEXT:    s_or_b32 s7, s7, s8
; SI-NEXT:    v_or_b32_e32 v2, v2, v3
; SI-NEXT:    s_or_b32 s7, s9, s7
; SI-NEXT:    buffer_store_dword v2, v0, s[0:3], 0 offen offset:24
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_mov_b32_e32 v2, s7
; SI-NEXT:    buffer_store_dword v2, v0, s[0:3], 0 offen offset:28
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v10
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v9
; SI-NEXT:    s_and_b32 s7, s25, 0xff
; SI-NEXT:    s_lshl_b32 s6, s6, 8
; SI-NEXT:    s_and_b32 s5, s5, 0xff
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v5
; SI-NEXT:    s_or_b32 s6, s7, s6
; SI-NEXT:    s_lshl_b32 s5, s5, 16
; SI-NEXT:    s_lshl_b32 s4, s4, 24
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    s_and_b32 s6, s6, 0xffff
; SI-NEXT:    s_or_b32 s4, s4, s5
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    s_or_b32 s4, s6, s4
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_mov_b32_e32 v1, s4
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v5f64_to_v40i8_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc0 .LBB75_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    s_lshr_b32 s14, s25, 24
; VI-NEXT:    s_lshr_b32 s15, s25, 16
; VI-NEXT:    s_lshr_b32 s26, s25, 8
; VI-NEXT:    s_lshr_b32 s27, s24, 16
; VI-NEXT:    s_lshr_b32 s28, s24, 8
; VI-NEXT:    s_lshr_b32 s29, s23, 24
; VI-NEXT:    s_lshr_b32 s40, s23, 16
; VI-NEXT:    s_lshr_b32 s41, s23, 8
; VI-NEXT:    s_lshr_b32 s42, s22, 16
; VI-NEXT:    s_lshr_b32 s43, s22, 8
; VI-NEXT:    s_lshr_b32 s44, s21, 24
; VI-NEXT:    s_lshr_b32 s45, s21, 16
; VI-NEXT:    s_lshr_b32 s46, s21, 8
; VI-NEXT:    s_lshr_b32 s47, s20, 16
; VI-NEXT:    s_lshr_b32 s56, s20, 8
; VI-NEXT:    s_lshr_b32 s57, s19, 24
; VI-NEXT:    s_lshr_b32 s58, s19, 16
; VI-NEXT:    s_lshr_b32 s59, s19, 8
; VI-NEXT:    s_lshr_b32 s60, s18, 16
; VI-NEXT:    s_lshr_b32 s61, s18, 8
; VI-NEXT:    s_lshr_b32 s62, s17, 24
; VI-NEXT:    s_lshr_b32 s63, s17, 16
; VI-NEXT:    s_lshr_b32 s72, s17, 8
; VI-NEXT:    s_lshr_b32 s73, s16, 16
; VI-NEXT:    s_lshr_b32 s74, s16, 8
; VI-NEXT:    s_lshr_b64 s[4:5], s[24:25], 24
; VI-NEXT:    s_lshr_b64 s[6:7], s[22:23], 24
; VI-NEXT:    s_lshr_b64 s[8:9], s[20:21], 24
; VI-NEXT:    s_lshr_b64 s[10:11], s[18:19], 24
; VI-NEXT:    s_lshr_b64 s[12:13], s[16:17], 24
; VI-NEXT:    v_mov_b32_e32 v9, s16
; VI-NEXT:    v_mov_b32_e32 v7, s18
; VI-NEXT:    v_mov_b32_e32 v5, s20
; VI-NEXT:    v_mov_b32_e32 v3, s22
; VI-NEXT:    v_mov_b32_e32 v1, s24
; VI-NEXT:    v_mov_b32_e32 v2, s25
; VI-NEXT:    v_mov_b32_e32 v4, s23
; VI-NEXT:    v_mov_b32_e32 v6, s21
; VI-NEXT:    v_mov_b32_e32 v8, s19
; VI-NEXT:    v_mov_b32_e32 v10, s17
; VI-NEXT:    v_mov_b32_e32 v34, s73
; VI-NEXT:    v_mov_b32_e32 v16, s74
; VI-NEXT:    v_mov_b32_e32 v32, s60
; VI-NEXT:    v_mov_b32_e32 v33, s61
; VI-NEXT:    v_mov_b32_e32 v27, s47
; VI-NEXT:    v_mov_b32_e32 v28, s56
; VI-NEXT:    v_mov_b32_e32 v22, s42
; VI-NEXT:    v_mov_b32_e32 v26, s43
; VI-NEXT:    v_mov_b32_e32 v18, s27
; VI-NEXT:    v_mov_b32_e32 v20, s28
; VI-NEXT:    v_mov_b32_e32 v15, s12
; VI-NEXT:    v_mov_b32_e32 v14, s10
; VI-NEXT:    v_mov_b32_e32 v13, s8
; VI-NEXT:    v_mov_b32_e32 v12, s6
; VI-NEXT:    v_mov_b32_e32 v11, s4
; VI-NEXT:    v_mov_b32_e32 v17, s14
; VI-NEXT:    v_mov_b32_e32 v19, s15
; VI-NEXT:    v_mov_b32_e32 v21, s26
; VI-NEXT:    v_mov_b32_e32 v23, s29
; VI-NEXT:    v_mov_b32_e32 v24, s40
; VI-NEXT:    v_mov_b32_e32 v25, s41
; VI-NEXT:    v_mov_b32_e32 v29, s44
; VI-NEXT:    v_mov_b32_e32 v30, s45
; VI-NEXT:    v_mov_b32_e32 v31, s46
; VI-NEXT:    v_mov_b32_e32 v35, s57
; VI-NEXT:    v_mov_b32_e32 v36, s58
; VI-NEXT:    v_mov_b32_e32 v37, s59
; VI-NEXT:    v_mov_b32_e32 v38, s62
; VI-NEXT:    v_mov_b32_e32 v39, s63
; VI-NEXT:    v_mov_b32_e32 v48, s72
; VI-NEXT:    s_branch .LBB75_3
; VI-NEXT:  .LBB75_2: ; %cmp.true
; VI-NEXT:    v_add_f64 v[1:2], s[24:25], 1.0
; VI-NEXT:    v_add_f64 v[3:4], s[22:23], 1.0
; VI-NEXT:    v_add_f64 v[5:6], s[20:21], 1.0
; VI-NEXT:    v_add_f64 v[7:8], s[18:19], 1.0
; VI-NEXT:    v_add_f64 v[9:10], s[16:17], 1.0
; VI-NEXT:    v_lshrrev_b64 v[11:12], 24, v[1:2]
; VI-NEXT:    v_lshrrev_b64 v[12:13], 24, v[3:4]
; VI-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; VI-NEXT:    v_lshrrev_b64 v[14:15], 24, v[7:8]
; VI-NEXT:    v_lshrrev_b64 v[15:16], 24, v[9:10]
; VI-NEXT:    v_lshrrev_b32_e32 v17, 24, v2
; VI-NEXT:    v_lshrrev_b32_e32 v19, 16, v2
; VI-NEXT:    v_lshrrev_b32_e32 v21, 8, v2
; VI-NEXT:    v_lshrrev_b32_e32 v18, 16, v1
; VI-NEXT:    v_lshrrev_b32_e32 v20, 8, v1
; VI-NEXT:    v_lshrrev_b32_e32 v23, 24, v4
; VI-NEXT:    v_lshrrev_b32_e32 v24, 16, v4
; VI-NEXT:    v_lshrrev_b32_e32 v25, 8, v4
; VI-NEXT:    v_lshrrev_b32_e32 v22, 16, v3
; VI-NEXT:    v_lshrrev_b32_e32 v26, 8, v3
; VI-NEXT:    v_lshrrev_b32_e32 v29, 24, v6
; VI-NEXT:    v_lshrrev_b32_e32 v30, 16, v6
; VI-NEXT:    v_lshrrev_b32_e32 v31, 8, v6
; VI-NEXT:    v_lshrrev_b32_e32 v27, 16, v5
; VI-NEXT:    v_lshrrev_b32_e32 v28, 8, v5
; VI-NEXT:    v_lshrrev_b32_e32 v35, 24, v8
; VI-NEXT:    v_lshrrev_b32_e32 v36, 16, v8
; VI-NEXT:    v_lshrrev_b32_e32 v37, 8, v8
; VI-NEXT:    v_lshrrev_b32_e32 v32, 16, v7
; VI-NEXT:    v_lshrrev_b32_e32 v33, 8, v7
; VI-NEXT:    v_lshrrev_b32_e32 v38, 24, v10
; VI-NEXT:    v_lshrrev_b32_e32 v39, 16, v10
; VI-NEXT:    v_lshrrev_b32_e32 v48, 8, v10
; VI-NEXT:    v_lshrrev_b32_e32 v34, 16, v9
; VI-NEXT:    v_lshrrev_b32_e32 v16, 8, v9
; VI-NEXT:  .LBB75_3: ; %end
; VI-NEXT:    s_mov_b32 s4, 0xc0c0004
; VI-NEXT:    v_perm_b32 v15, v34, v15, s4
; VI-NEXT:    v_perm_b32 v9, v9, v16, s4
; VI-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT:    v_or_b32_e32 v9, v9, v15
; VI-NEXT:    buffer_store_dword v9, v0, s[0:3], 0 offen
; VI-NEXT:    v_perm_b32 v9, v10, v48, s4
; VI-NEXT:    v_perm_b32 v10, v39, v38, s4
; VI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT:    v_or_b32_e32 v9, v9, v10
; VI-NEXT:    buffer_store_dword v9, v0, s[0:3], 0 offen offset:4
; VI-NEXT:    v_perm_b32 v9, v32, v14, s4
; VI-NEXT:    v_perm_b32 v7, v7, v33, s4
; VI-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT:    v_or_b32_e32 v7, v7, v9
; VI-NEXT:    buffer_store_dword v7, v0, s[0:3], 0 offen offset:8
; VI-NEXT:    v_perm_b32 v7, v8, v37, s4
; VI-NEXT:    v_perm_b32 v8, v36, v35, s4
; VI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT:    v_or_b32_e32 v7, v7, v8
; VI-NEXT:    buffer_store_dword v7, v0, s[0:3], 0 offen offset:12
; VI-NEXT:    v_perm_b32 v7, v27, v13, s4
; VI-NEXT:    v_perm_b32 v5, v5, v28, s4
; VI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT:    v_or_b32_e32 v5, v5, v7
; VI-NEXT:    buffer_store_dword v5, v0, s[0:3], 0 offen offset:16
; VI-NEXT:    v_perm_b32 v5, v6, v31, s4
; VI-NEXT:    v_perm_b32 v6, v30, v29, s4
; VI-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT:    v_or_b32_e32 v5, v5, v6
; VI-NEXT:    buffer_store_dword v5, v0, s[0:3], 0 offen offset:20
; VI-NEXT:    v_perm_b32 v5, v22, v12, s4
; VI-NEXT:    v_perm_b32 v3, v3, v26, s4
; VI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT:    v_or_b32_e32 v3, v3, v5
; VI-NEXT:    buffer_store_dword v3, v0, s[0:3], 0 offen offset:24
; VI-NEXT:    v_perm_b32 v3, v4, v25, s4
; VI-NEXT:    v_perm_b32 v4, v24, v23, s4
; VI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT:    v_or_b32_e32 v3, v3, v4
; VI-NEXT:    buffer_store_dword v3, v0, s[0:3], 0 offen offset:28
; VI-NEXT:    v_perm_b32 v3, v18, v11, s4
; VI-NEXT:    v_perm_b32 v1, v1, v20, s4
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_e32 v1, v1, v3
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; VI-NEXT:    v_perm_b32 v1, v2, v21, s4
; VI-NEXT:    v_perm_b32 v2, v19, v17, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v5f64_to_v40i8_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc0 .LBB75_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    s_lshr_b32 s14, s25, 24
; GFX9-NEXT:    s_lshr_b32 s15, s25, 16
; GFX9-NEXT:    s_lshr_b32 s26, s25, 8
; GFX9-NEXT:    s_lshr_b32 s27, s24, 16
; GFX9-NEXT:    s_lshr_b32 s28, s24, 8
; GFX9-NEXT:    s_lshr_b32 s29, s23, 24
; GFX9-NEXT:    s_lshr_b32 s40, s23, 16
; GFX9-NEXT:    s_lshr_b32 s41, s23, 8
; GFX9-NEXT:    s_lshr_b32 s42, s22, 16
; GFX9-NEXT:    s_lshr_b32 s43, s22, 8
; GFX9-NEXT:    s_lshr_b32 s44, s21, 24
; GFX9-NEXT:    s_lshr_b32 s45, s21, 16
; GFX9-NEXT:    s_lshr_b32 s46, s21, 8
; GFX9-NEXT:    s_lshr_b32 s47, s20, 16
; GFX9-NEXT:    s_lshr_b32 s56, s20, 8
; GFX9-NEXT:    s_lshr_b32 s57, s19, 24
; GFX9-NEXT:    s_lshr_b32 s58, s19, 16
; GFX9-NEXT:    s_lshr_b32 s59, s19, 8
; GFX9-NEXT:    s_lshr_b32 s60, s18, 16
; GFX9-NEXT:    s_lshr_b32 s61, s18, 8
; GFX9-NEXT:    s_lshr_b32 s62, s17, 24
; GFX9-NEXT:    s_lshr_b32 s63, s17, 16
; GFX9-NEXT:    s_lshr_b32 s72, s17, 8
; GFX9-NEXT:    s_lshr_b32 s73, s16, 16
; GFX9-NEXT:    s_lshr_b32 s74, s16, 8
; GFX9-NEXT:    s_lshr_b64 s[4:5], s[24:25], 24
; GFX9-NEXT:    s_lshr_b64 s[6:7], s[22:23], 24
; GFX9-NEXT:    s_lshr_b64 s[8:9], s[20:21], 24
; GFX9-NEXT:    s_lshr_b64 s[10:11], s[18:19], 24
; GFX9-NEXT:    s_lshr_b64 s[12:13], s[16:17], 24
; GFX9-NEXT:    v_mov_b32_e32 v9, s16
; GFX9-NEXT:    v_mov_b32_e32 v7, s18
; GFX9-NEXT:    v_mov_b32_e32 v5, s20
; GFX9-NEXT:    v_mov_b32_e32 v3, s22
; GFX9-NEXT:    v_mov_b32_e32 v1, s24
; GFX9-NEXT:    v_mov_b32_e32 v2, s25
; GFX9-NEXT:    v_mov_b32_e32 v4, s23
; GFX9-NEXT:    v_mov_b32_e32 v6, s21
; GFX9-NEXT:    v_mov_b32_e32 v8, s19
; GFX9-NEXT:    v_mov_b32_e32 v10, s17
; GFX9-NEXT:    v_mov_b32_e32 v34, s73
; GFX9-NEXT:    v_mov_b32_e32 v16, s74
; GFX9-NEXT:    v_mov_b32_e32 v32, s60
; GFX9-NEXT:    v_mov_b32_e32 v33, s61
; GFX9-NEXT:    v_mov_b32_e32 v27, s47
; GFX9-NEXT:    v_mov_b32_e32 v28, s56
; GFX9-NEXT:    v_mov_b32_e32 v22, s42
; GFX9-NEXT:    v_mov_b32_e32 v26, s43
; GFX9-NEXT:    v_mov_b32_e32 v18, s27
; GFX9-NEXT:    v_mov_b32_e32 v20, s28
; GFX9-NEXT:    v_mov_b32_e32 v15, s12
; GFX9-NEXT:    v_mov_b32_e32 v14, s10
; GFX9-NEXT:    v_mov_b32_e32 v13, s8
; GFX9-NEXT:    v_mov_b32_e32 v12, s6
; GFX9-NEXT:    v_mov_b32_e32 v11, s4
; GFX9-NEXT:    v_mov_b32_e32 v17, s14
; GFX9-NEXT:    v_mov_b32_e32 v19, s15
; GFX9-NEXT:    v_mov_b32_e32 v21, s26
; GFX9-NEXT:    v_mov_b32_e32 v23, s29
; GFX9-NEXT:    v_mov_b32_e32 v24, s40
; GFX9-NEXT:    v_mov_b32_e32 v25, s41
; GFX9-NEXT:    v_mov_b32_e32 v29, s44
; GFX9-NEXT:    v_mov_b32_e32 v30, s45
; GFX9-NEXT:    v_mov_b32_e32 v31, s46
; GFX9-NEXT:    v_mov_b32_e32 v35, s57
; GFX9-NEXT:    v_mov_b32_e32 v36, s58
; GFX9-NEXT:    v_mov_b32_e32 v37, s59
; GFX9-NEXT:    v_mov_b32_e32 v38, s62
; GFX9-NEXT:    v_mov_b32_e32 v39, s63
; GFX9-NEXT:    v_mov_b32_e32 v48, s72
; GFX9-NEXT:    s_branch .LBB75_3
; GFX9-NEXT:  .LBB75_2: ; %cmp.true
; GFX9-NEXT:    v_add_f64 v[1:2], s[24:25], 1.0
; GFX9-NEXT:    v_add_f64 v[3:4], s[22:23], 1.0
; GFX9-NEXT:    v_add_f64 v[5:6], s[20:21], 1.0
; GFX9-NEXT:    v_add_f64 v[7:8], s[18:19], 1.0
; GFX9-NEXT:    v_add_f64 v[9:10], s[16:17], 1.0
; GFX9-NEXT:    v_lshrrev_b64 v[11:12], 24, v[1:2]
; GFX9-NEXT:    v_lshrrev_b64 v[12:13], 24, v[3:4]
; GFX9-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX9-NEXT:    v_lshrrev_b64 v[14:15], 24, v[7:8]
; GFX9-NEXT:    v_lshrrev_b64 v[15:16], 24, v[9:10]
; GFX9-NEXT:    v_lshrrev_b32_e32 v17, 24, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v19, 16, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v21, 8, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v18, 16, v1
; GFX9-NEXT:    v_lshrrev_b32_e32 v20, 8, v1
; GFX9-NEXT:    v_lshrrev_b32_e32 v23, 24, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v24, 16, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v25, 8, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v22, 16, v3
; GFX9-NEXT:    v_lshrrev_b32_e32 v26, 8, v3
; GFX9-NEXT:    v_lshrrev_b32_e32 v29, 24, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v30, 16, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v31, 8, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v27, 16, v5
; GFX9-NEXT:    v_lshrrev_b32_e32 v28, 8, v5
; GFX9-NEXT:    v_lshrrev_b32_e32 v35, 24, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v36, 16, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v37, 8, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v32, 16, v7
; GFX9-NEXT:    v_lshrrev_b32_e32 v33, 8, v7
; GFX9-NEXT:    v_lshrrev_b32_e32 v38, 24, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v39, 16, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v48, 8, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v34, 16, v9
; GFX9-NEXT:    v_lshrrev_b32_e32 v16, 8, v9
; GFX9-NEXT:  .LBB75_3: ; %end
; GFX9-NEXT:    s_mov_b32 s4, 0xc0c0004
; GFX9-NEXT:    v_perm_b32 v15, v34, v15, s4
; GFX9-NEXT:    v_perm_b32 v9, v9, v16, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
; GFX9-NEXT:    v_or_b32_e32 v9, v9, v15
; GFX9-NEXT:    buffer_store_dword v9, v0, s[0:3], 0 offen
; GFX9-NEXT:    v_perm_b32 v9, v10, v48, s4
; GFX9-NEXT:    v_perm_b32 v10, v39, v38, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; GFX9-NEXT:    v_or_b32_e32 v9, v9, v10
; GFX9-NEXT:    buffer_store_dword v9, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT:    v_perm_b32 v9, v32, v14, s4
; GFX9-NEXT:    v_perm_b32 v7, v7, v33, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; GFX9-NEXT:    v_or_b32_e32 v7, v7, v9
; GFX9-NEXT:    buffer_store_dword v7, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT:    v_perm_b32 v7, v8, v37, s4
; GFX9-NEXT:    v_perm_b32 v8, v36, v35, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; GFX9-NEXT:    v_or_b32_e32 v7, v7, v8
; GFX9-NEXT:    buffer_store_dword v7, v0, s[0:3], 0 offen offset:12
; GFX9-NEXT:    v_perm_b32 v7, v27, v13, s4
; GFX9-NEXT:    v_perm_b32 v5, v5, v28, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; GFX9-NEXT:    v_or_b32_e32 v5, v5, v7
; GFX9-NEXT:    buffer_store_dword v5, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT:    v_perm_b32 v5, v6, v31, s4
; GFX9-NEXT:    v_perm_b32 v6, v30, v29, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; GFX9-NEXT:    v_or_b32_e32 v5, v5, v6
; GFX9-NEXT:    buffer_store_dword v5, v0, s[0:3], 0 offen offset:20
; GFX9-NEXT:    v_perm_b32 v5, v22, v12, s4
; GFX9-NEXT:    v_perm_b32 v3, v3, v26, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; GFX9-NEXT:    v_or_b32_e32 v3, v3, v5
; GFX9-NEXT:    buffer_store_dword v3, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT:    v_perm_b32 v3, v4, v25, s4
; GFX9-NEXT:    v_perm_b32 v4, v24, v23, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; GFX9-NEXT:    v_or_b32_e32 v3, v3, v4
; GFX9-NEXT:    buffer_store_dword v3, v0, s[0:3], 0 offen offset:28
; GFX9-NEXT:    v_perm_b32 v3, v18, v11, s4
; GFX9-NEXT:    v_perm_b32 v1, v1, v20, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT:    v_perm_b32 v1, v2, v21, s4
; GFX9-NEXT:    v_perm_b32 v2, v19, v17, s4
; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v2
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v5f64_to_v40i8_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc0 .LBB75_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-NEXT:    s_lshr_b32 s14, s21, 24
; GFX11-NEXT:    s_lshr_b32 s15, s21, 16
; GFX11-NEXT:    s_lshr_b32 s22, s21, 8
; GFX11-NEXT:    s_lshr_b32 s23, s20, 16
; GFX11-NEXT:    s_lshr_b32 s24, s20, 8
; GFX11-NEXT:    s_lshr_b32 s25, s19, 24
; GFX11-NEXT:    s_lshr_b32 s26, s19, 16
; GFX11-NEXT:    s_lshr_b32 s27, s19, 8
; GFX11-NEXT:    s_lshr_b32 s28, s18, 16
; GFX11-NEXT:    s_lshr_b32 s29, s18, 8
; GFX11-NEXT:    s_lshr_b32 s40, s17, 24
; GFX11-NEXT:    s_lshr_b32 s41, s17, 16
; GFX11-NEXT:    s_lshr_b32 s42, s17, 8
; GFX11-NEXT:    s_lshr_b32 s43, s16, 16
; GFX11-NEXT:    s_lshr_b32 s44, s16, 8
; GFX11-NEXT:    s_lshr_b32 s45, s3, 24
; GFX11-NEXT:    s_lshr_b32 s46, s3, 16
; GFX11-NEXT:    s_lshr_b32 s47, s3, 8
; GFX11-NEXT:    s_lshr_b32 s56, s2, 16
; GFX11-NEXT:    s_lshr_b32 s57, s2, 8
; GFX11-NEXT:    s_lshr_b32 s58, s1, 24
; GFX11-NEXT:    s_lshr_b32 s59, s1, 16
; GFX11-NEXT:    s_lshr_b32 s60, s1, 8
; GFX11-NEXT:    s_lshr_b32 s61, s0, 16
; GFX11-NEXT:    s_lshr_b32 s62, s0, 8
; GFX11-NEXT:    s_lshr_b64 s[4:5], s[20:21], 24
; GFX11-NEXT:    s_lshr_b64 s[6:7], s[18:19], 24
; GFX11-NEXT:    s_lshr_b64 s[8:9], s[16:17], 24
; GFX11-NEXT:    s_lshr_b64 s[10:11], s[2:3], 24
; GFX11-NEXT:    s_lshr_b64 s[12:13], s[0:1], 24
; GFX11-NEXT:    v_dual_mov_b32 v13, s0 :: v_dual_mov_b32 v2, s21
; GFX11-NEXT:    v_dual_mov_b32 v9, s2 :: v_dual_mov_b32 v4, s19
; GFX11-NEXT:    v_dual_mov_b32 v5, s16 :: v_dual_mov_b32 v6, s17
; GFX11-NEXT:    v_dual_mov_b32 v3, s18 :: v_dual_mov_b32 v10, s3
; GFX11-NEXT:    v_dual_mov_b32 v1, s20 :: v_dual_mov_b32 v14, s1
; GFX11-NEXT:    v_dual_mov_b32 v34, s61 :: v_dual_mov_b32 v35, s62
; GFX11-NEXT:    v_dual_mov_b32 v31, s56 :: v_dual_mov_b32 v28, s43
; GFX11-NEXT:    v_dual_mov_b32 v33, s57 :: v_dual_mov_b32 v26, s44
; GFX11-NEXT:    v_dual_mov_b32 v23, s28 :: v_dual_mov_b32 v22, s29
; GFX11-NEXT:    v_dual_mov_b32 v19, s23 :: v_dual_mov_b32 v8, s24
; GFX11-NEXT:    v_dual_mov_b32 v17, s12 :: v_dual_mov_b32 v16, s10
; GFX11-NEXT:    v_dual_mov_b32 v15, s8 :: v_dual_mov_b32 v18, s14
; GFX11-NEXT:    v_dual_mov_b32 v11, s6 :: v_dual_mov_b32 v20, s15
; GFX11-NEXT:    v_dual_mov_b32 v7, s4 :: v_dual_mov_b32 v12, s22
; GFX11-NEXT:    v_dual_mov_b32 v24, s25 :: v_dual_mov_b32 v25, s26
; GFX11-NEXT:    v_dual_mov_b32 v21, s27 :: v_dual_mov_b32 v30, s41
; GFX11-NEXT:    v_dual_mov_b32 v29, s40 :: v_dual_mov_b32 v36, s45
; GFX11-NEXT:    v_dual_mov_b32 v27, s42 :: v_dual_mov_b32 v32, s47
; GFX11-NEXT:    v_dual_mov_b32 v37, s46 :: v_dual_mov_b32 v38, s58
; GFX11-NEXT:    v_dual_mov_b32 v39, s59 :: v_dual_mov_b32 v48, s60
; GFX11-NEXT:    s_branch .LBB75_3
; GFX11-NEXT:  .LBB75_2: ; %cmp.true
; GFX11-NEXT:    v_add_f64 v[5:6], s[16:17], 1.0
; GFX11-NEXT:    v_add_f64 v[9:10], s[2:3], 1.0
; GFX11-NEXT:    v_add_f64 v[1:2], s[20:21], 1.0
; GFX11-NEXT:    v_add_f64 v[3:4], s[18:19], 1.0
; GFX11-NEXT:    v_add_f64 v[13:14], s[0:1], 1.0
; GFX11-NEXT:    v_lshrrev_b64 v[15:16], 24, v[5:6]
; GFX11-NEXT:    v_lshrrev_b64 v[16:17], 24, v[9:10]
; GFX11-NEXT:    v_lshrrev_b64 v[7:8], 24, v[1:2]
; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[3:4]
; GFX11-NEXT:    v_lshrrev_b64 v[17:18], 24, v[13:14]
; GFX11-NEXT:    v_lshrrev_b32_e32 v18, 24, v2
; GFX11-NEXT:    v_lshrrev_b32_e32 v20, 16, v2
; GFX11-NEXT:    v_lshrrev_b32_e32 v12, 8, v2
; GFX11-NEXT:    v_lshrrev_b32_e32 v19, 16, v1
; GFX11-NEXT:    v_lshrrev_b32_e32 v8, 8, v1
; GFX11-NEXT:    v_lshrrev_b32_e32 v24, 24, v4
; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 16, v4
; GFX11-NEXT:    v_lshrrev_b32_e32 v21, 8, v4
; GFX11-NEXT:    v_lshrrev_b32_e32 v23, 16, v3
; GFX11-NEXT:    v_lshrrev_b32_e32 v22, 8, v3
; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 24, v6
; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 16, v6
; GFX11-NEXT:    v_lshrrev_b32_e32 v27, 8, v6
; GFX11-NEXT:    v_lshrrev_b32_e32 v28, 16, v5
; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 8, v5
; GFX11-NEXT:    v_lshrrev_b32_e32 v36, 24, v10
; GFX11-NEXT:    v_lshrrev_b32_e32 v37, 16, v10
; GFX11-NEXT:    v_lshrrev_b32_e32 v32, 8, v10
; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 16, v9
; GFX11-NEXT:    v_lshrrev_b32_e32 v33, 8, v9
; GFX11-NEXT:    v_lshrrev_b32_e32 v38, 24, v14
; GFX11-NEXT:    v_lshrrev_b32_e32 v39, 16, v14
; GFX11-NEXT:    v_lshrrev_b32_e32 v48, 8, v14
; GFX11-NEXT:    v_lshrrev_b32_e32 v34, 16, v13
; GFX11-NEXT:    v_lshrrev_b32_e32 v35, 8, v13
; GFX11-NEXT:  .LBB75_3: ; %end
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT:    v_perm_b32 v17, v34, v17, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v13, v13, v35, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v16, v31, v16, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v31, v37, v36, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v9, v9, v33, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
; GFX11-NEXT:    v_perm_b32 v15, v28, v15, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
; GFX11-NEXT:    v_perm_b32 v10, v10, v32, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v34, v39, v38, 0xc0c0004
; GFX11-NEXT:    v_or_b32_e32 v13, v13, v17
; GFX11-NEXT:    v_lshlrev_b32_e32 v17, 16, v31
; GFX11-NEXT:    v_perm_b32 v5, v5, v26, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v26, 16, v15
; GFX11-NEXT:    v_or_b32_e32 v15, v9, v16
; GFX11-NEXT:    v_perm_b32 v9, v30, v29, 0xc0c0004
; GFX11-NEXT:    v_or_b32_e32 v16, v10, v17
; GFX11-NEXT:    v_perm_b32 v10, v23, v11, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v11, v25, v24, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v7, v19, v7, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v17, v20, v18, 0xc0c0004
; GFX11-NEXT:    v_perm_b32 v14, v14, v48, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v28, 16, v34
; GFX11-NEXT:    v_perm_b32 v6, v6, v27, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; GFX11-NEXT:    v_perm_b32 v3, v3, v22, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; GFX11-NEXT:    v_perm_b32 v4, v4, v21, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; GFX11-NEXT:    v_perm_b32 v1, v1, v8, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v7
; GFX11-NEXT:    v_perm_b32 v2, v2, v12, 0xc0c0004
; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v17
; GFX11-NEXT:    v_or_b32_e32 v14, v14, v28
; GFX11-NEXT:    v_or_b32_e32 v5, v5, v26
; GFX11-NEXT:    v_or_b32_e32 v6, v6, v9
; GFX11-NEXT:    v_or_b32_e32 v7, v3, v10
; GFX11-NEXT:    v_or_b32_e32 v8, v4, v11
; GFX11-NEXT:    v_or_b32_e32 v1, v1, v18
; GFX11-NEXT:    v_or_b32_e32 v2, v2, v12
; GFX11-NEXT:    s_clause 0x2
; GFX11-NEXT:    scratch_store_b128 v0, v[13:16], off
; GFX11-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
; GFX11-NEXT:    scratch_store_b64 v0, v[1:2], off offset:32
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <5 x double> %a, splat (double 1.000000e+00)
  %a2 = bitcast <5 x double> %a1 to <40 x i8>
  br label %end

cmp.false:
  %a3 = bitcast <5 x double> %a to <40 x i8>
  br label %end

end:
  %phi = phi <40 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <40 x i8> %phi
}

define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v40i8_to_v5i64:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    buffer_store_dword v40, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v41, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v42, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v43, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v44, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v45, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v46, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v47, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; SI-NEXT:    buffer_store_dword v56, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; SI-NEXT:    v_mov_b32_e32 v36, v10
; SI-NEXT:    v_mov_b32_e32 v35, v8
; SI-NEXT:    v_mov_b32_e32 v34, v6
; SI-NEXT:    v_mov_b32_e32 v33, v4
; SI-NEXT:    v_mov_b32_e32 v32, v2
; SI-NEXT:    v_mov_b32_e32 v31, v0
; SI-NEXT:    buffer_load_dword v0, off, s[0:3], s32
; SI-NEXT:    buffer_load_dword v2, off, s[0:3], s32 offset:36
; SI-NEXT:    buffer_load_dword v4, off, s[0:3], s32 offset:32
; SI-NEXT:    buffer_load_dword v39, off, s[0:3], s32 offset:28
; SI-NEXT:    buffer_load_dword v6, off, s[0:3], s32 offset:24
; SI-NEXT:    buffer_load_dword v8, off, s[0:3], s32 offset:8
; SI-NEXT:    buffer_load_dword v10, off, s[0:3], s32 offset:16
; SI-NEXT:    buffer_load_dword v48, off, s[0:3], s32 offset:20
; SI-NEXT:    buffer_load_dword v49, off, s[0:3], s32 offset:12
; SI-NEXT:    buffer_load_dword v50, off, s[0:3], s32 offset:4
; SI-NEXT:    v_mov_b32_e32 v38, v14
; SI-NEXT:    v_mov_b32_e32 v37, v12
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_lshlrev_b32_e32 v56, 8, v1
; SI-NEXT:    v_lshlrev_b32_e32 v47, 24, v3
; SI-NEXT:    v_lshlrev_b32_e32 v46, 8, v5
; SI-NEXT:    v_lshlrev_b32_e32 v45, 24, v7
; SI-NEXT:    v_lshlrev_b32_e32 v44, 8, v9
; SI-NEXT:    v_lshlrev_b32_e32 v43, 24, v11
; SI-NEXT:    v_lshlrev_b32_e32 v42, 8, v13
; SI-NEXT:    v_lshlrev_b32_e32 v41, 24, v15
; SI-NEXT:    v_lshlrev_b32_e32 v40, 8, v17
; SI-NEXT:    v_lshlrev_b32_e32 v55, 24, v19
; SI-NEXT:    v_lshlrev_b32_e32 v54, 8, v21
; SI-NEXT:    v_lshlrev_b32_e32 v53, 24, v23
; SI-NEXT:    v_lshlrev_b32_e32 v52, 8, v25
; SI-NEXT:    v_lshlrev_b32_e32 v51, 24, v27
; SI-NEXT:    v_lshlrev_b32_e32 v27, 8, v29
; SI-NEXT:    s_waitcnt vmcnt(9)
; SI-NEXT:    v_lshlrev_b32_e32 v25, 24, v0
; SI-NEXT:    s_waitcnt vmcnt(8)
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
; SI-NEXT:    s_waitcnt vmcnt(7)
; SI-NEXT:    v_lshlrev_b32_e32 v17, 24, v4
; SI-NEXT:    s_waitcnt vmcnt(5)
; SI-NEXT:    v_lshlrev_b32_e32 v19, 8, v6
; SI-NEXT:    s_waitcnt vmcnt(4)
; SI-NEXT:    v_lshlrev_b32_e32 v23, 8, v8
; SI-NEXT:    s_waitcnt vmcnt(3)
; SI-NEXT:    v_lshlrev_b32_e32 v21, 24, v10
; SI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB76_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    v_and_b32_e32 v0, 0xff, v31
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v32
; SI-NEXT:    v_or_b32_e32 v0, v0, v56
; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_or_b32_e32 v1, v47, v1
; SI-NEXT:    v_or_b32_e32 v0, v0, v1
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v33
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v34
; SI-NEXT:    v_or_b32_e32 v1, v1, v46
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v45, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v35
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v36
; SI-NEXT:    v_or_b32_e32 v2, v2, v44
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    v_or_b32_e32 v3, v43, v3
; SI-NEXT:    v_or_b32_e32 v2, v2, v3
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v37
; SI-NEXT:    v_and_b32_e32 v4, 0xff, v38
; SI-NEXT:    v_or_b32_e32 v3, v3, v42
; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT:    v_or_b32_e32 v4, v41, v4
; SI-NEXT:    v_or_b32_e32 v3, v3, v4
; SI-NEXT:    v_and_b32_e32 v4, 0xff, v16
; SI-NEXT:    v_and_b32_e32 v5, 0xff, v18
; SI-NEXT:    v_or_b32_e32 v4, v4, v40
; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT:    v_or_b32_e32 v5, v55, v5
; SI-NEXT:    v_or_b32_e32 v4, v4, v5
; SI-NEXT:    v_and_b32_e32 v5, 0xff, v20
; SI-NEXT:    v_and_b32_e32 v6, 0xff, v22
; SI-NEXT:    v_or_b32_e32 v5, v5, v54
; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT:    v_or_b32_e32 v6, v53, v6
; SI-NEXT:    v_or_b32_e32 v5, v5, v6
; SI-NEXT:    v_and_b32_e32 v6, 0xff, v24
; SI-NEXT:    v_and_b32_e32 v7, 0xff, v26
; SI-NEXT:    v_or_b32_e32 v6, v6, v52
; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT:    v_or_b32_e32 v7, v51, v7
; SI-NEXT:    v_or_b32_e32 v6, v6, v7
; SI-NEXT:    v_and_b32_e32 v7, 0xff, v28
; SI-NEXT:    v_and_b32_e32 v8, 0xff, v30
; SI-NEXT:    v_or_b32_e32 v7, v7, v27
; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT:    v_or_b32_e32 v8, v25, v8
; SI-NEXT:    v_or_b32_e32 v7, v7, v8
; SI-NEXT:    s_waitcnt vmcnt(0)
; SI-NEXT:    v_and_b32_e32 v8, 0xff, v50
; SI-NEXT:    v_and_b32_e32 v9, 0xff, v49
; SI-NEXT:    v_or_b32_e32 v8, v8, v23
; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT:    v_or_b32_e32 v9, v21, v9
; SI-NEXT:    v_or_b32_e32 v8, v8, v9
; SI-NEXT:    v_and_b32_e32 v9, 0xff, v48
; SI-NEXT:    v_and_b32_e32 v10, 0xff, v39
; SI-NEXT:    v_or_b32_e32 v9, v9, v19
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT:    v_or_b32_e32 v10, v17, v10
; SI-NEXT:    v_or_b32_e32 v9, v9, v10
; SI-NEXT:    ; implicit-def: $vgpr31
; SI-NEXT:    ; implicit-def: $vgpr32
; SI-NEXT:    ; implicit-def: $vgpr33
; SI-NEXT:    ; implicit-def: $vgpr34
; SI-NEXT:    ; implicit-def: $vgpr35
; SI-NEXT:    ; implicit-def: $vgpr36
; SI-NEXT:    ; implicit-def: $vgpr37
; SI-NEXT:    ; implicit-def: $vgpr38
; SI-NEXT:    ; implicit-def: $vgpr16
; SI-NEXT:    ; implicit-def: $vgpr18
; SI-NEXT:    ; implicit-def: $vgpr20
; SI-NEXT:    ; implicit-def: $vgpr22
; SI-NEXT:    ; implicit-def: $vgpr24
; SI-NEXT:    ; implicit-def: $vgpr26
; SI-NEXT:    ; implicit-def: $vgpr28
; SI-NEXT:    ; implicit-def: $vgpr30
; SI-NEXT:    ; implicit-def: $vgpr50
; SI-NEXT:    ; implicit-def: $vgpr49
; SI-NEXT:    ; implicit-def: $vgpr48
; SI-NEXT:    ; implicit-def: $vgpr39
; SI-NEXT:    ; implicit-def: $vgpr56
; SI-NEXT:    ; implicit-def: $vgpr47
; SI-NEXT:    ; implicit-def: $vgpr46
; SI-NEXT:    ; implicit-def: $vgpr45
; SI-NEXT:    ; implicit-def: $vgpr44
; SI-NEXT:    ; implicit-def: $vgpr43
; SI-NEXT:    ; implicit-def: $vgpr42
; SI-NEXT:    ; implicit-def: $vgpr41
; SI-NEXT:    ; implicit-def: $vgpr40
; SI-NEXT:    ; implicit-def: $vgpr55
; SI-NEXT:    ; implicit-def: $vgpr54
; SI-NEXT:    ; implicit-def: $vgpr53
; SI-NEXT:    ; implicit-def: $vgpr52
; SI-NEXT:    ; implicit-def: $vgpr51
; SI-NEXT:    ; implicit-def: $vgpr27
; SI-NEXT:    ; implicit-def: $vgpr25
; SI-NEXT:    ; implicit-def: $vgpr23
; SI-NEXT:    ; implicit-def: $vgpr21
; SI-NEXT:    ; implicit-def: $vgpr19
; SI-NEXT:    ; implicit-def: $vgpr17
; SI-NEXT:  .LBB76_2: ; %Flow
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB76_4
; SI-NEXT:  ; %bb.3: ; %cmp.true
; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v31
; SI-NEXT:    v_and_b32_e32 v0, 0xff, v0
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v32
; SI-NEXT:    v_or_b32_e32 v0, v56, v0
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1
; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x300, v0
; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT:    v_or_b32_e32 v1, v47, v1
; SI-NEXT:    v_or_b32_e32 v0, v1, v0
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v33
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1
; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v34
; SI-NEXT:    s_movk_i32 s6, 0x300
; SI-NEXT:    v_or_b32_e32 v1, v46, v1
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v2
; SI-NEXT:    v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v45, v2
; SI-NEXT:    v_or_b32_e32 v1, v2, v1
; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v35
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v2
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v36
; SI-NEXT:    v_or_b32_e32 v2, v44, v2
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v3
; SI-NEXT:    v_add_i32_e32 v2, vcc, s6, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT:    v_or_b32_e32 v3, v43, v3
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v37
; SI-NEXT:    v_and_b32_e32 v3, 0xff, v3
; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v38
; SI-NEXT:    v_or_b32_e32 v3, v42, v3
; SI-NEXT:    v_and_b32_e32 v4, 0xff, v4
; SI-NEXT:    v_add_i32_e32 v3, vcc, s6, v3
; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT:    v_or_b32_e32 v4, v41, v4
; SI-NEXT:    v_or_b32_e32 v3, v4, v3
; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v16
; SI-NEXT:    v_and_b32_e32 v4, 0xff, v4
; SI-NEXT:    v_add_i32_e32 v5, vcc, 3, v18
; SI-NEXT:    v_or_b32_e32 v4, v40, v4
; SI-NEXT:    v_and_b32_e32 v5, 0xff, v5
; SI-NEXT:    v_add_i32_e32 v4, vcc, s6, v4
; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT:    v_or_b32_e32 v5, v55, v5
; SI-NEXT:    v_or_b32_e32 v4, v5, v4
; SI-NEXT:    v_add_i32_e32 v5, vcc, 3, v20
; SI-NEXT:    v_and_b32_e32 v5, 0xff, v5
; SI-NEXT:    v_add_i32_e32 v6, vcc, 3, v22
; SI-NEXT:    v_or_b32_e32 v5, v54, v5
; SI-NEXT:    v_and_b32_e32 v6, 0xff, v6
; SI-NEXT:    v_add_i32_e32 v5, vcc, s6, v5
; SI-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT:    v_or_b32_e32 v6, v53, v6
; SI-NEXT:    v_or_b32_e32 v5, v6, v5
; SI-NEXT:    v_add_i32_e32 v6, vcc, 3, v24
; SI-NEXT:    v_and_b32_e32 v6, 0xff, v6
; SI-NEXT:    v_add_i32_e32 v7, vcc, 3, v26
; SI-NEXT:    v_or_b32_e32 v6, v52, v6
; SI-NEXT:    v_and_b32_e32 v7, 0xff, v7
; SI-NEXT:    v_add_i32_e32 v6, vcc, s6, v6
; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT:    v_or_b32_e32 v7, v51, v7
; SI-NEXT:    v_or_b32_e32 v6, v7, v6
; SI-NEXT:    v_add_i32_e32 v7, vcc, 3, v28
; SI-NEXT:    v_and_b32_e32 v7, 0xff, v7
; SI-NEXT:    v_add_i32_e32 v8, vcc, 3, v30
; SI-NEXT:    v_or_b32_e32 v7, v27, v7
; SI-NEXT:    v_and_b32_e32 v8, 0xff, v8
; SI-NEXT:    v_add_i32_e32 v7, vcc, s6, v7
; SI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT:    v_or_b32_e32 v8, v25, v8
; SI-NEXT:    v_or_b32_e32 v7, v8, v7
; SI-NEXT:    s_waitcnt vmcnt(0)
; SI-NEXT:    v_add_i32_e32 v8, vcc, 3, v50
; SI-NEXT:    v_and_b32_e32 v8, 0xff, v8
; SI-NEXT:    v_add_i32_e32 v9, vcc, 3, v49
; SI-NEXT:    v_or_b32_e32 v8, v23, v8
; SI-NEXT:    v_and_b32_e32 v9, 0xff, v9
; SI-NEXT:    v_add_i32_e32 v8, vcc, s6, v8
; SI-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT:    v_or_b32_e32 v9, v21, v9
; SI-NEXT:    v_or_b32_e32 v8, v9, v8
; SI-NEXT:    v_add_i32_e32 v9, vcc, 3, v48
; SI-NEXT:    v_and_b32_e32 v9, 0xff, v9
; SI-NEXT:    v_add_i32_e32 v10, vcc, 3, v39
; SI-NEXT:    v_or_b32_e32 v9, v19, v9
; SI-NEXT:    v_and_b32_e32 v10, 0xff, v10
; SI-NEXT:    v_add_i32_e32 v9, vcc, s6, v9
; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT:    v_or_b32_e32 v10, v17, v10
; SI-NEXT:    v_or_b32_e32 v9, v10, v9
; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x3000000, v0
; SI-NEXT:    v_add_i32_e32 v1, vcc, 0x3000000, v1
; SI-NEXT:    v_add_i32_e32 v2, vcc, 0x3000000, v2
; SI-NEXT:    v_add_i32_e32 v3, vcc, 0x3000000, v3
; SI-NEXT:    v_add_i32_e32 v4, vcc, 0x3000000, v4
; SI-NEXT:    v_add_i32_e32 v5, vcc, 0x3000000, v5
; SI-NEXT:    v_add_i32_e32 v6, vcc, 0x3000000, v6
; SI-NEXT:    v_add_i32_e32 v7, vcc, 0x3000000, v7
; SI-NEXT:    v_add_i32_e32 v8, vcc, 0x3000000, v8
; SI-NEXT:    v_add_i32_e32 v9, vcc, 0x3000000, v9
; SI-NEXT:  .LBB76_4: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    buffer_load_dword v56, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v47, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v46, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v45, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v44, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v43, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v42, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT:    s_waitcnt vmcnt(0)
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v40i8_to_v5i64:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; VI-NEXT:    buffer_store_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; VI-NEXT:    buffer_store_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; VI-NEXT:    buffer_store_dword v43, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; VI-NEXT:    buffer_store_dword v44, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; VI-NEXT:    buffer_store_dword v45, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; VI-NEXT:    buffer_store_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; VI-NEXT:    buffer_store_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; VI-NEXT:    v_mov_b32_e32 v54, v0
; VI-NEXT:    buffer_load_ushort v45, off, s[0:3], s32
; VI-NEXT:    buffer_load_dword v0, off, s[0:3], s32 offset:36
; VI-NEXT:    buffer_load_ushort v55, off, s[0:3], s32 offset:32
; VI-NEXT:    buffer_load_ushort v40, off, s[0:3], s32 offset:28
; VI-NEXT:    buffer_load_ushort v41, off, s[0:3], s32 offset:24
; VI-NEXT:    buffer_load_ushort v42, off, s[0:3], s32 offset:20
; VI-NEXT:    buffer_load_ushort v43, off, s[0:3], s32 offset:16
; VI-NEXT:    buffer_load_ushort v44, off, s[0:3], s32 offset:12
; VI-NEXT:    buffer_load_ushort v46, off, s[0:3], s32 offset:8
; VI-NEXT:    buffer_load_ushort v47, off, s[0:3], s32 offset:4
; VI-NEXT:    v_mov_b32_e32 v31, v15
; VI-NEXT:    v_mov_b32_e32 v32, v14
; VI-NEXT:    v_mov_b32_e32 v33, v13
; VI-NEXT:    v_mov_b32_e32 v34, v12
; VI-NEXT:    v_mov_b32_e32 v35, v11
; VI-NEXT:    v_mov_b32_e32 v36, v10
; VI-NEXT:    v_mov_b32_e32 v37, v9
; VI-NEXT:    v_mov_b32_e32 v38, v8
; VI-NEXT:    v_mov_b32_e32 v39, v7
; VI-NEXT:    v_mov_b32_e32 v48, v6
; VI-NEXT:    v_mov_b32_e32 v49, v5
; VI-NEXT:    v_mov_b32_e32 v50, v4
; VI-NEXT:    v_mov_b32_e32 v51, v3
; VI-NEXT:    v_mov_b32_e32 v52, v2
; VI-NEXT:    v_mov_b32_e32 v53, v1
; VI-NEXT:    s_waitcnt vmcnt(8)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; VI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB76_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    s_mov_b32 s6, 0xc0c0004
; VI-NEXT:    v_perm_b32 v1, v52, v51, s6
; VI-NEXT:    v_perm_b32 v0, v54, v53, s6
; VI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT:    v_perm_b32 v2, v48, v39, s6
; VI-NEXT:    v_or_b32_e32 v0, v0, v1
; VI-NEXT:    v_perm_b32 v1, v50, v49, s6
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_perm_b32 v3, v36, v35, s6
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v38, v37, s6
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_perm_b32 v4, v32, v31, s6
; VI-NEXT:    v_or_b32_e32 v2, v2, v3
; VI-NEXT:    v_perm_b32 v3, v34, v33, s6
; VI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT:    v_perm_b32 v5, v18, v19, s6
; VI-NEXT:    v_or_b32_e32 v3, v3, v4
; VI-NEXT:    v_perm_b32 v4, v16, v17, s6
; VI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT:    v_perm_b32 v6, v22, v23, s6
; VI-NEXT:    v_or_b32_e32 v4, v4, v5
; VI-NEXT:    v_perm_b32 v5, v20, v21, s6
; VI-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT:    v_perm_b32 v7, v26, v27, s6
; VI-NEXT:    v_or_b32_e32 v5, v5, v6
; VI-NEXT:    v_perm_b32 v6, v24, v25, s6
; VI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT:    v_perm_b32 v8, v30, v45, s6
; VI-NEXT:    v_or_b32_e32 v6, v6, v7
; VI-NEXT:    v_perm_b32 v7, v28, v29, s6
; VI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT:    s_waitcnt vmcnt(2)
; VI-NEXT:    v_perm_b32 v9, v44, v43, s6
; VI-NEXT:    v_or_b32_e32 v7, v7, v8
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    v_perm_b32 v8, v47, v46, s6
; VI-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT:    v_perm_b32 v10, v40, v55, s6
; VI-NEXT:    v_or_b32_e32 v8, v8, v9
; VI-NEXT:    v_perm_b32 v9, v42, v41, s6
; VI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT:    v_or_b32_e32 v9, v9, v10
; VI-NEXT:    ; implicit-def: $vgpr54
; VI-NEXT:    ; implicit-def: $vgpr53
; VI-NEXT:    ; implicit-def: $vgpr52
; VI-NEXT:    ; implicit-def: $vgpr51
; VI-NEXT:    ; implicit-def: $vgpr50
; VI-NEXT:    ; implicit-def: $vgpr49
; VI-NEXT:    ; implicit-def: $vgpr48
; VI-NEXT:    ; implicit-def: $vgpr39
; VI-NEXT:    ; implicit-def: $vgpr38
; VI-NEXT:    ; implicit-def: $vgpr37
; VI-NEXT:    ; implicit-def: $vgpr36
; VI-NEXT:    ; implicit-def: $vgpr35
; VI-NEXT:    ; implicit-def: $vgpr34
; VI-NEXT:    ; implicit-def: $vgpr33
; VI-NEXT:    ; implicit-def: $vgpr32
; VI-NEXT:    ; implicit-def: $vgpr31
; VI-NEXT:    ; implicit-def: $vgpr16
; VI-NEXT:    ; implicit-def: $vgpr17
; VI-NEXT:    ; implicit-def: $vgpr18
; VI-NEXT:    ; implicit-def: $vgpr19
; VI-NEXT:    ; implicit-def: $vgpr20
; VI-NEXT:    ; implicit-def: $vgpr21
; VI-NEXT:    ; implicit-def: $vgpr22
; VI-NEXT:    ; implicit-def: $vgpr23
; VI-NEXT:    ; implicit-def: $vgpr24
; VI-NEXT:    ; implicit-def: $vgpr25
; VI-NEXT:    ; implicit-def: $vgpr26
; VI-NEXT:    ; implicit-def: $vgpr27
; VI-NEXT:    ; implicit-def: $vgpr28
; VI-NEXT:    ; implicit-def: $vgpr29
; VI-NEXT:    ; implicit-def: $vgpr30
; VI-NEXT:    ; implicit-def: $vgpr45
; VI-NEXT:    ; implicit-def: $vgpr47
; VI-NEXT:    ; implicit-def: $vgpr46
; VI-NEXT:    ; implicit-def: $vgpr44
; VI-NEXT:    ; implicit-def: $vgpr43
; VI-NEXT:    ; implicit-def: $vgpr42
; VI-NEXT:    ; implicit-def: $vgpr41
; VI-NEXT:    ; implicit-def: $vgpr40
; VI-NEXT:    ; implicit-def: $vgpr55
; VI-NEXT:  .LBB76_2: ; %Flow
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB76_4
; VI-NEXT:  ; %bb.3: ; %cmp.true
; VI-NEXT:    v_add_u16_e32 v0, 3, v54
; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v53
; VI-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v1, 3, v52
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v51
; VI-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_mov_b32_e32 v9, 0x300
; VI-NEXT:    v_add_u16_e32 v0, 0x300, v0
; VI-NEXT:    v_add_u16_sdwa v1, v1, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v0, v0, v1
; VI-NEXT:    v_add_u16_e32 v1, 3, v50
; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v49
; VI-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v2, 3, v48
; VI-NEXT:    v_lshlrev_b16_e32 v3, 8, v39
; VI-NEXT:    v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v1, 0x300, v1
; VI-NEXT:    v_add_u16_sdwa v2, v2, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_add_u16_e32 v2, 3, v38
; VI-NEXT:    v_lshlrev_b16_e32 v3, 8, v37
; VI-NEXT:    v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v3, 3, v36
; VI-NEXT:    v_lshlrev_b16_e32 v4, 8, v35
; VI-NEXT:    v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v2, 0x300, v2
; VI-NEXT:    v_add_u16_sdwa v3, v3, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v2, v2, v3
; VI-NEXT:    v_add_u16_e32 v3, 3, v34
; VI-NEXT:    v_lshlrev_b16_e32 v4, 8, v33
; VI-NEXT:    v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v4, 3, v32
; VI-NEXT:    v_lshlrev_b16_e32 v5, 8, v31
; VI-NEXT:    v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v3, 0x300, v3
; VI-NEXT:    v_add_u16_sdwa v4, v4, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v3, v3, v4
; VI-NEXT:    v_add_u16_e32 v4, 3, v16
; VI-NEXT:    v_lshlrev_b16_e32 v5, 8, v17
; VI-NEXT:    v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v5, 3, v18
; VI-NEXT:    v_lshlrev_b16_e32 v6, 8, v19
; VI-NEXT:    v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v4, 0x300, v4
; VI-NEXT:    v_add_u16_sdwa v5, v5, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v4, v4, v5
; VI-NEXT:    v_add_u16_e32 v5, 3, v20
; VI-NEXT:    v_lshlrev_b16_e32 v6, 8, v21
; VI-NEXT:    v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v6, 3, v22
; VI-NEXT:    v_lshlrev_b16_e32 v7, 8, v23
; VI-NEXT:    v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v5, 0x300, v5
; VI-NEXT:    v_add_u16_sdwa v6, v6, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v5, v5, v6
; VI-NEXT:    v_add_u16_e32 v6, 3, v24
; VI-NEXT:    v_lshlrev_b16_e32 v7, 8, v25
; VI-NEXT:    v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v7, 3, v26
; VI-NEXT:    v_lshlrev_b16_e32 v8, 8, v27
; VI-NEXT:    v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v6, 0x300, v6
; VI-NEXT:    v_add_u16_sdwa v7, v7, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v6, v6, v7
; VI-NEXT:    v_add_u16_e32 v7, 3, v28
; VI-NEXT:    v_lshlrev_b16_e32 v8, 8, v29
; VI-NEXT:    v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v8, 3, v30
; VI-NEXT:    v_lshlrev_b16_e32 v10, 8, v45
; VI-NEXT:    v_or_b32_sdwa v8, v10, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v7, 0x300, v7
; VI-NEXT:    v_add_u16_sdwa v8, v8, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v7, v7, v8
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    v_add_u16_e32 v8, 3, v47
; VI-NEXT:    v_lshlrev_b16_e32 v10, 8, v46
; VI-NEXT:    v_or_b32_sdwa v8, v10, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v10, 3, v44
; VI-NEXT:    v_lshlrev_b16_e32 v11, 8, v43
; VI-NEXT:    v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v8, 0x300, v8
; VI-NEXT:    v_add_u16_sdwa v10, v10, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v8, v8, v10
; VI-NEXT:    v_add_u16_e32 v10, 3, v42
; VI-NEXT:    v_lshlrev_b16_e32 v11, 8, v41
; VI-NEXT:    v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v11, 3, v40
; VI-NEXT:    v_lshlrev_b16_e32 v12, 8, v55
; VI-NEXT:    v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT:    v_add_u16_e32 v10, 0x300, v10
; VI-NEXT:    v_add_u16_sdwa v9, v11, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT:    v_or_b32_e32 v9, v10, v9
; VI-NEXT:  .LBB76_4: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    buffer_load_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; VI-NEXT:    buffer_load_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; VI-NEXT:    buffer_load_dword v45, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; VI-NEXT:    buffer_load_dword v44, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; VI-NEXT:    buffer_load_dword v43, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; VI-NEXT:    buffer_load_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; VI-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; VI-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v40i8_to_v5i64:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; GFX9-NEXT:    buffer_store_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; GFX9-NEXT:    buffer_store_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT:    buffer_store_dword v43, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT:    buffer_store_dword v44, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; GFX9-NEXT:    buffer_store_dword v45, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; GFX9-NEXT:    buffer_store_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; GFX9-NEXT:    buffer_store_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; GFX9-NEXT:    v_mov_b32_e32 v54, v0
; GFX9-NEXT:    buffer_load_ushort v45, off, s[0:3], s32
; GFX9-NEXT:    buffer_load_dword v0, off, s[0:3], s32 offset:36
; GFX9-NEXT:    buffer_load_ushort v55, off, s[0:3], s32 offset:32
; GFX9-NEXT:    buffer_load_ushort v40, off, s[0:3], s32 offset:28
; GFX9-NEXT:    buffer_load_ushort v41, off, s[0:3], s32 offset:24
; GFX9-NEXT:    buffer_load_ushort v42, off, s[0:3], s32 offset:20
; GFX9-NEXT:    buffer_load_ushort v43, off, s[0:3], s32 offset:16
; GFX9-NEXT:    buffer_load_ushort v44, off, s[0:3], s32 offset:12
; GFX9-NEXT:    buffer_load_ushort v46, off, s[0:3], s32 offset:8
; GFX9-NEXT:    buffer_load_ushort v47, off, s[0:3], s32 offset:4
; GFX9-NEXT:    v_mov_b32_e32 v31, v15
; GFX9-NEXT:    v_mov_b32_e32 v32, v14
; GFX9-NEXT:    v_mov_b32_e32 v33, v13
; GFX9-NEXT:    v_mov_b32_e32 v34, v12
; GFX9-NEXT:    v_mov_b32_e32 v35, v11
; GFX9-NEXT:    v_mov_b32_e32 v36, v10
; GFX9-NEXT:    v_mov_b32_e32 v37, v9
; GFX9-NEXT:    v_mov_b32_e32 v38, v8
; GFX9-NEXT:    v_mov_b32_e32 v39, v7
; GFX9-NEXT:    v_mov_b32_e32 v48, v6
; GFX9-NEXT:    v_mov_b32_e32 v49, v5
; GFX9-NEXT:    v_mov_b32_e32 v50, v4
; GFX9-NEXT:    v_mov_b32_e32 v51, v3
; GFX9-NEXT:    v_mov_b32_e32 v52, v2
; GFX9-NEXT:    v_mov_b32_e32 v53, v1
; GFX9-NEXT:    s_waitcnt vmcnt(8)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB76_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    s_mov_b32 s6, 0xc0c0004
; GFX9-NEXT:    v_perm_b32 v0, v54, v53, s6
; GFX9-NEXT:    v_perm_b32 v1, v52, v51, s6
; GFX9-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT:    v_perm_b32 v1, v50, v49, s6
; GFX9-NEXT:    v_perm_b32 v2, v48, v39, s6
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    v_perm_b32 v2, v38, v37, s6
; GFX9-NEXT:    v_perm_b32 v3, v36, v35, s6
; GFX9-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT:    v_perm_b32 v3, v34, v33, s6
; GFX9-NEXT:    v_perm_b32 v4, v32, v31, s6
; GFX9-NEXT:    v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT:    v_perm_b32 v4, v16, v17, s6
; GFX9-NEXT:    v_perm_b32 v5, v18, v19, s6
; GFX9-NEXT:    v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT:    v_perm_b32 v5, v20, v21, s6
; GFX9-NEXT:    v_perm_b32 v6, v22, v23, s6
; GFX9-NEXT:    v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT:    v_perm_b32 v6, v24, v25, s6
; GFX9-NEXT:    v_perm_b32 v7, v26, v27, s6
; GFX9-NEXT:    v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT:    v_perm_b32 v7, v28, v29, s6
; GFX9-NEXT:    v_perm_b32 v8, v30, v45, s6
; GFX9-NEXT:    v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    v_perm_b32 v8, v47, v46, s6
; GFX9-NEXT:    v_perm_b32 v9, v44, v43, s6
; GFX9-NEXT:    v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT:    v_perm_b32 v9, v42, v41, s6
; GFX9-NEXT:    v_perm_b32 v10, v40, v55, s6
; GFX9-NEXT:    v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT:    ; implicit-def: $vgpr54
; GFX9-NEXT:    ; implicit-def: $vgpr53
; GFX9-NEXT:    ; implicit-def: $vgpr52
; GFX9-NEXT:    ; implicit-def: $vgpr51
; GFX9-NEXT:    ; implicit-def: $vgpr50
; GFX9-NEXT:    ; implicit-def: $vgpr49
; GFX9-NEXT:    ; implicit-def: $vgpr48
; GFX9-NEXT:    ; implicit-def: $vgpr39
; GFX9-NEXT:    ; implicit-def: $vgpr38
; GFX9-NEXT:    ; implicit-def: $vgpr37
; GFX9-NEXT:    ; implicit-def: $vgpr36
; GFX9-NEXT:    ; implicit-def: $vgpr35
; GFX9-NEXT:    ; implicit-def: $vgpr34
; GFX9-NEXT:    ; implicit-def: $vgpr33
; GFX9-NEXT:    ; implicit-def: $vgpr32
; GFX9-NEXT:    ; implicit-def: $vgpr31
; GFX9-NEXT:    ; implicit-def: $vgpr16
; GFX9-NEXT:    ; implicit-def: $vgpr17
; GFX9-NEXT:    ; implicit-def: $vgpr18
; GFX9-NEXT:    ; implicit-def: $vgpr19
; GFX9-NEXT:    ; implicit-def: $vgpr20
; GFX9-NEXT:    ; implicit-def: $vgpr21
; GFX9-NEXT:    ; implicit-def: $vgpr22
; GFX9-NEXT:    ; implicit-def: $vgpr23
; GFX9-NEXT:    ; implicit-def: $vgpr24
; GFX9-NEXT:    ; implicit-def: $vgpr25
; GFX9-NEXT:    ; implicit-def: $vgpr26
; GFX9-NEXT:    ; implicit-def: $vgpr27
; GFX9-NEXT:    ; implicit-def: $vgpr28
; GFX9-NEXT:    ; implicit-def: $vgpr29
; GFX9-NEXT:    ; implicit-def: $vgpr30
; GFX9-NEXT:    ; implicit-def: $vgpr45
; GFX9-NEXT:    ; implicit-def: $vgpr47
; GFX9-NEXT:    ; implicit-def: $vgpr46
; GFX9-NEXT:    ; implicit-def: $vgpr44
; GFX9-NEXT:    ; implicit-def: $vgpr43
; GFX9-NEXT:    ; implicit-def: $vgpr42
; GFX9-NEXT:    ; implicit-def: $vgpr41
; GFX9-NEXT:    ; implicit-def: $vgpr40
; GFX9-NEXT:    ; implicit-def: $vgpr55
; GFX9-NEXT:  .LBB76_2: ; %Flow
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB76_4
; GFX9-NEXT:  ; %bb.3: ; %cmp.true
; GFX9-NEXT:    v_add_u16_e32 v0, 3, v54
; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v53
; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v1, 3, v52
; GFX9-NEXT:    v_lshlrev_b16_e32 v2, 8, v51
; GFX9-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v0, 0x300, v0
; GFX9-NEXT:    v_add_u16_e32 v1, 0x300, v1
; GFX9-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT:    v_add_u16_e32 v1, 3, v50
; GFX9-NEXT:    v_lshlrev_b16_e32 v2, 8, v49
; GFX9-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v2, 3, v48
; GFX9-NEXT:    v_lshlrev_b16_e32 v3, 8, v39
; GFX9-NEXT:    v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v1, 0x300, v1
; GFX9-NEXT:    v_add_u16_e32 v2, 0x300, v2
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    v_add_u16_e32 v2, 3, v38
; GFX9-NEXT:    v_lshlrev_b16_e32 v3, 8, v37
; GFX9-NEXT:    v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v3, 3, v36
; GFX9-NEXT:    v_lshlrev_b16_e32 v4, 8, v35
; GFX9-NEXT:    v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v2, 0x300, v2
; GFX9-NEXT:    v_add_u16_e32 v3, 0x300, v3
; GFX9-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT:    v_add_u16_e32 v3, 3, v34
; GFX9-NEXT:    v_lshlrev_b16_e32 v4, 8, v33
; GFX9-NEXT:    v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v4, 3, v32
; GFX9-NEXT:    v_lshlrev_b16_e32 v5, 8, v31
; GFX9-NEXT:    v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v3, 0x300, v3
; GFX9-NEXT:    v_add_u16_e32 v4, 0x300, v4
; GFX9-NEXT:    v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT:    v_add_u16_e32 v4, 3, v16
; GFX9-NEXT:    v_lshlrev_b16_e32 v5, 8, v17
; GFX9-NEXT:    v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v5, 3, v18
; GFX9-NEXT:    v_lshlrev_b16_e32 v6, 8, v19
; GFX9-NEXT:    v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v4, 0x300, v4
; GFX9-NEXT:    v_add_u16_e32 v5, 0x300, v5
; GFX9-NEXT:    v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT:    v_add_u16_e32 v5, 3, v20
; GFX9-NEXT:    v_lshlrev_b16_e32 v6, 8, v21
; GFX9-NEXT:    v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v6, 3, v22
; GFX9-NEXT:    v_lshlrev_b16_e32 v7, 8, v23
; GFX9-NEXT:    v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v5, 0x300, v5
; GFX9-NEXT:    v_add_u16_e32 v6, 0x300, v6
; GFX9-NEXT:    v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT:    v_add_u16_e32 v6, 3, v24
; GFX9-NEXT:    v_lshlrev_b16_e32 v7, 8, v25
; GFX9-NEXT:    v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v7, 3, v26
; GFX9-NEXT:    v_lshlrev_b16_e32 v8, 8, v27
; GFX9-NEXT:    v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v6, 0x300, v6
; GFX9-NEXT:    v_add_u16_e32 v7, 0x300, v7
; GFX9-NEXT:    v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT:    v_add_u16_e32 v7, 3, v28
; GFX9-NEXT:    v_lshlrev_b16_e32 v8, 8, v29
; GFX9-NEXT:    v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v8, 3, v30
; GFX9-NEXT:    v_lshlrev_b16_e32 v9, 8, v45
; GFX9-NEXT:    v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v7, 0x300, v7
; GFX9-NEXT:    v_add_u16_e32 v8, 0x300, v8
; GFX9-NEXT:    v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    v_add_u16_e32 v8, 3, v47
; GFX9-NEXT:    v_lshlrev_b16_e32 v9, 8, v46
; GFX9-NEXT:    v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v9, 3, v44
; GFX9-NEXT:    v_lshlrev_b16_e32 v10, 8, v43
; GFX9-NEXT:    v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v8, 0x300, v8
; GFX9-NEXT:    v_add_u16_e32 v9, 0x300, v9
; GFX9-NEXT:    v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT:    v_add_u16_e32 v9, 3, v42
; GFX9-NEXT:    v_lshlrev_b16_e32 v10, 8, v41
; GFX9-NEXT:    v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v10, 3, v40
; GFX9-NEXT:    v_lshlrev_b16_e32 v11, 8, v55
; GFX9-NEXT:    v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_add_u16_e32 v9, 0x300, v9
; GFX9-NEXT:    v_add_u16_e32 v10, 0x300, v10
; GFX9-NEXT:    v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT:  .LBB76_4: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    buffer_load_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; GFX9-NEXT:    buffer_load_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; GFX9-NEXT:    buffer_load_dword v45, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; GFX9-NEXT:    buffer_load_dword v44, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; GFX9-NEXT:    buffer_load_dword v43, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; GFX9-NEXT:    buffer_load_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; GFX9-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v40i8_to_v5i64:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    s_clause 0x9
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v31, off, s32 offset:32
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v32, off, s32 offset:28
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v33, off, s32 offset:24
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v34, off, s32 offset:20
; GFX11-TRUE16-NEXT:    scratch_load_b32 v80, off, s32 offset:36
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v35, off, s32 offset:16
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v37, off, s32 offset:12
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v36, off, s32 offset:8
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v38, off, s32 offset:4
; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v39, off, s32
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v48.l, v15.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v49.l, v14.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v50.l, v13.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v51.l, v12.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v52.l, v11.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v53.l, v10.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v54.l, v9.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v8.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v64.l, v7.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v65.l, v6.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v66.l, v5.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v67.l, v4.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v68.l, v3.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v69.l, v2.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v70.l, v1.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v71.l, v0.l
; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(5)
; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v80
; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB76_3
; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB76_4
; GFX11-TRUE16-NEXT:  .LBB76_2: ; %end
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT:  .LBB76_3: ; %cmp.false
; GFX11-TRUE16-NEXT:    v_perm_b32 v0, v71, v70, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v1, v69, v68, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v2, v67, v66, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v3, v65, v64, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v4, v55, v54, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v5, v53, v52, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, v51, v50, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, v49, v48, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v8, v16, v17, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v9, v18, v19, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v1, v3, 16, v2
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v2, v5, 16, v4
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v3, v7, 16, v6
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v4, v9, 16, v8
; GFX11-TRUE16-NEXT:    v_perm_b32 v5, v20, v21, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, v22, v23, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, v24, v25, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v8, v26, v27, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v9, v28, v29, 0xc0c0004
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT:    v_perm_b32 v10, v30, v39, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v11, v38, v36, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v12, v37, v35, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v13, v34, v33, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v14, v32, v31, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v5, v6, 16, v5
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v6, v8, 16, v7
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v7, v10, 16, v9
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v8, v12, 16, v11
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v9, v14, 16, v13
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr71_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr70_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr69_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr68_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr67_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr66_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr65_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_lo16
; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB76_2
; GFX11-TRUE16-NEXT:  .LBB76_4: ; %cmp.true
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v71.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v69.l, 3
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v70.l
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 8, v68.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v67.l, 3
; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, 0xff
; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, v0.h, 0xff
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v65.l, 3
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v66.l
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v64.l
; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v1.h, v0.h
; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, v2.l, 0xff
; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, v3.l, 0xff
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v55.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v53.l, 3
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.l, 8, v50.l
; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v2.h, v1.l
; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v3.h, v1.h
; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, v2.l, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v54.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, v51.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.h, v49.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, v16.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, v18.l, 3
; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.h, v2.l
; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, v3.l, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.l, 8, v52.l
; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, v3.h, 0xff
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, v22.l, 3
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v23.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, v24.l, 3
; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v3.l, v2.h
; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v4.l, v3.h
; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, v4.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.l, 8, v48.l
; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, v5.l, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.l, 8, v17.l
; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, v6.l, 0xff
; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, v7.l, 0xff
; GFX11-TRUE16-NEXT:    v_or_b16 v3.h, v4.l, v3.h
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v25.l
; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v5.l, v4.h
; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, v5.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.l, 8, v19.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, v20.l, 3
; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.h, v6.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, v28.l, 3
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.l, 8, v27.l
; GFX11-TRUE16-NEXT:    v_or_b16 v4.h, v5.l, v4.h
; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, v5.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v21.l
; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, v6.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v29.l
; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.h, v7.l
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(3)
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, v37.l, 3
; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.h, v5.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, v26.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.h, v34.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v10.h, v32.l, 3
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(2)
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.l, 8, v36.l
; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, v9.l, 0xff
; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, v5.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.l, 8, v35.l
; GFX11-TRUE16-NEXT:    v_and_b16 v9.h, v9.h, 0xff
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v33.l
; GFX11-TRUE16-NEXT:    v_and_b16 v10.h, v10.h, 0xff
; GFX11-TRUE16-NEXT:    v_or_b16 v7.h, v8.l, v5.h
; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.h, v6.h
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.h, v30.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, v6.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, v7.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, v7.h, 0x300
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, v38.l, 3
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, v8.l, 0x300
; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, v8.h, 0xff
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v39.l
; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.l, 8, v31.l
; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, v7.h, 0xff
; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v11.l, v9.l
; GFX11-TRUE16-NEXT:    v_or_b16 v9.h, v11.h, v9.h
; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.h, v8.l
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, 0x300
; GFX11-TRUE16-NEXT:    v_or_b16 v8.h, v10.l, v7.h
; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v12.l, v10.h
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v0.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v1.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v1.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v2.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v2.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v3.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, v3.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, v4.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.h, v4.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, v5.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, v8.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, v8.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.h, v9.l, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, v9.h, 0x300
; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.h, v10.l, 0x300
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v40i8_to_v5i64:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v53, v1 :: v_dual_mov_b32 v54, v0
; GFX11-FAKE16-NEXT:    s_clause 0x9
; GFX11-FAKE16-NEXT:    scratch_load_u16 v55, off, s32 offset:32
; GFX11-FAKE16-NEXT:    scratch_load_u16 v64, off, s32 offset:28
; GFX11-FAKE16-NEXT:    scratch_load_u16 v65, off, s32 offset:24
; GFX11-FAKE16-NEXT:    scratch_load_u16 v67, off, s32 offset:20
; GFX11-FAKE16-NEXT:    scratch_load_b32 v0, off, s32 offset:36
; GFX11-FAKE16-NEXT:    scratch_load_u16 v66, off, s32 offset:16
; GFX11-FAKE16-NEXT:    scratch_load_u16 v68, off, s32 offset:12
; GFX11-FAKE16-NEXT:    scratch_load_u16 v69, off, s32 offset:8
; GFX11-FAKE16-NEXT:    scratch_load_u16 v71, off, s32 offset:4
; GFX11-FAKE16-NEXT:    scratch_load_u16 v70, off, s32
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v33, v15 :: v_dual_mov_b32 v34, v12
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v31, v14 :: v_dual_mov_b32 v32, v13
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v35, v11 :: v_dual_mov_b32 v36, v10
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v37, v9 :: v_dual_mov_b32 v38, v8
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v39, v7 :: v_dual_mov_b32 v48, v6
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v49, v5 :: v_dual_mov_b32 v50, v4
; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v51, v3 :: v_dual_mov_b32 v52, v2
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(5)
; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB76_3
; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB76_4
; GFX11-FAKE16-NEXT:  .LBB76_2: ; %end
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT:  .LBB76_3: ; %cmp.false
; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v54, v53, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v52, v51, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v50, v49, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v48, v39, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v38, v37, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v36, v35, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v34, v32, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v31, v33, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v16, v17, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v18, v19, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, v5, 16, v4
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v3, v7, 16, v6
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v4, v9, 16, v8
; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v20, v21, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v22, v23, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v24, v25, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v26, v27, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v28, v29, 0xc0c0004
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v30, v70, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v71, v69, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v68, v66, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v67, v65, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v64, v55, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v5, v6, 16, v5
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v6, v8, 16, v7
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v7, v10, 16, v9
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v8, v12, 16, v11
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v9, v14, 16, v13
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr70
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr71
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr69
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr68
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr66
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr67
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr55
; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB76_2
; GFX11-FAKE16-NEXT:  .LBB76_4: ; %cmp.true
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v54, 3
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v53
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v50, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v38, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v52, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v49
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v48, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v36, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v1, v0
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v37
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v51
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v39
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v5, v4
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v8
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v9
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 8, v35
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v0, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v3, v2
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v4, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v7, v6
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v1, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v8, v5
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v2, 0x300
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v4, 0x300
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v1
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v5, 0x300
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v34, 3
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v2, 16, v0
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v4, 16, v3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v16, 3
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, v5, 16, v6
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v7
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v32
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v31, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v17
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v18, 3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v5, v4
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v6
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v6, 8, v33
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v7, v3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v8
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 8, v19
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v4, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v6, v5
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v20, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v3, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v8, v7
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v5, 0x300
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v9
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 8, v21
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v6, 0x300
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v3, v5, 16, v4
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v24, 3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v22, 3
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v4, v6, 16, v9
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v9, 8, v25
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v7, 0x300
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v8
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v28, 3
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v26, 3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v9, v5
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v23
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v12, 8, v29
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v10
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v5, 0x300
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v10, 8, v27
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v11, v7
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v12, v8
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, v67, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v5
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v71, 3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v10, v9
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v30, 3
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v14, 8, v69
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, v68, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v65
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, v64, 3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v70
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v14, v5
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v15
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v66
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v16, v12
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v17
; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v55
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v8, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v13, v10
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v5, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v15, v14
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, v12, 0x300
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v17, v16
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v7, 0x300
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v9, 0x300
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v10, 0x300
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v5
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, v13, 0x300
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, v14, 0x300
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v5, v7, 16, v6
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v6, v9, 16, v11
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v7, v10, 16, v8
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v8, v13, 16, v15
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v9, v14, 16, v12
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <40 x i8> %a, splat (i8 3)
  %a2 = bitcast <40 x i8> %a1 to <5 x i64>
  br label %end

cmp.false:
  %a3 = bitcast <40 x i8> %a to <5 x i64>
  br label %end

end:
  %phi = phi <5 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <5 x i64> %phi
}

define inreg <5 x i64> @bitcast_v40i8_to_v5i64_scalar(<40 x i8> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v40i8_to_v5i64_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_readfirstlane_b32 s4, v26
; SI-NEXT:    v_readfirstlane_b32 s5, v25
; SI-NEXT:    v_readfirstlane_b32 s6, v24
; SI-NEXT:    v_readfirstlane_b32 s8, v23
; SI-NEXT:    v_readfirstlane_b32 s9, v22
; SI-NEXT:    v_readfirstlane_b32 s10, v21
; SI-NEXT:    v_readfirstlane_b32 s11, v20
; SI-NEXT:    v_readfirstlane_b32 s13, v19
; SI-NEXT:    v_readfirstlane_b32 s14, v18
; SI-NEXT:    v_readfirstlane_b32 s40, v17
; SI-NEXT:    v_readfirstlane_b32 s41, v16
; SI-NEXT:    v_readfirstlane_b32 s42, v15
; SI-NEXT:    v_readfirstlane_b32 s43, v14
; SI-NEXT:    v_readfirstlane_b32 s44, v13
; SI-NEXT:    v_readfirstlane_b32 s45, v12
; SI-NEXT:    v_readfirstlane_b32 s46, v11
; SI-NEXT:    v_readfirstlane_b32 s47, v10
; SI-NEXT:    v_readfirstlane_b32 s56, v9
; SI-NEXT:    v_readfirstlane_b32 s57, v8
; SI-NEXT:    v_readfirstlane_b32 s58, v7
; SI-NEXT:    v_readfirstlane_b32 s59, v6
; SI-NEXT:    v_readfirstlane_b32 s60, v5
; SI-NEXT:    v_readfirstlane_b32 s61, v4
; SI-NEXT:    s_cmp_lg_u32 s4, 0
; SI-NEXT:    v_readfirstlane_b32 s62, v3
; SI-NEXT:    v_readfirstlane_b32 s63, v2
; SI-NEXT:    v_readfirstlane_b32 s15, v1
; SI-NEXT:    v_readfirstlane_b32 s72, v0
; SI-NEXT:    s_cbranch_scc0 .LBB77_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    s_and_b32 s4, s16, 0xff
; SI-NEXT:    s_lshl_b32 s7, s17, 8
; SI-NEXT:    s_or_b32 s4, s4, s7
; SI-NEXT:    s_and_b32 s7, s18, 0xff
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_lshl_b32 s12, s19, 24
; SI-NEXT:    s_and_b32 s4, s4, 0xffff
; SI-NEXT:    s_or_b32 s7, s12, s7
; SI-NEXT:    s_or_b32 s4, s4, s7
; SI-NEXT:    s_and_b32 s7, s20, 0xff
; SI-NEXT:    s_lshl_b32 s12, s21, 8
; SI-NEXT:    s_or_b32 s7, s7, s12
; SI-NEXT:    s_and_b32 s12, s22, 0xff
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_lshl_b32 s16, s23, 24
; SI-NEXT:    s_and_b32 s7, s7, 0xffff
; SI-NEXT:    s_or_b32 s12, s16, s12
; SI-NEXT:    s_or_b32 s7, s7, s12
; SI-NEXT:    s_and_b32 s12, s24, 0xff
; SI-NEXT:    s_lshl_b32 s16, s25, 8
; SI-NEXT:    s_or_b32 s12, s12, s16
; SI-NEXT:    s_and_b32 s16, s26, 0xff
; SI-NEXT:    s_lshl_b32 s16, s16, 16
; SI-NEXT:    s_lshl_b32 s17, s27, 24
; SI-NEXT:    s_and_b32 s12, s12, 0xffff
; SI-NEXT:    s_or_b32 s16, s17, s16
; SI-NEXT:    s_or_b32 s12, s12, s16
; SI-NEXT:    s_and_b32 s16, s28, 0xff
; SI-NEXT:    s_lshl_b32 s17, s29, 8
; SI-NEXT:    s_or_b32 s16, s16, s17
; SI-NEXT:    s_and_b32 s17, s72, 0xff
; SI-NEXT:    s_lshl_b32 s17, s17, 16
; SI-NEXT:    s_lshl_b32 s15, s15, 24
; SI-NEXT:    s_and_b32 s16, s16, 0xffff
; SI-NEXT:    s_or_b32 s15, s15, s17
; SI-NEXT:    s_or_b32 s15, s16, s15
; SI-NEXT:    s_and_b32 s16, s63, 0xff
; SI-NEXT:    s_lshl_b32 s17, s62, 8
; SI-NEXT:    s_or_b32 s16, s16, s17
; SI-NEXT:    s_and_b32 s17, s61, 0xff
; SI-NEXT:    s_lshl_b32 s17, s17, 16
; SI-NEXT:    s_lshl_b32 s18, s60, 24
; SI-NEXT:    s_and_b32 s16, s16, 0xffff
; SI-NEXT:    s_or_b32 s17, s18, s17
; SI-NEXT:    s_or_b32 s16, s16, s17
; SI-NEXT:    s_and_b32 s17, s59, 0xff
; SI-NEXT:    s_lshl_b32 s18, s58, 8
; SI-NEXT:    s_or_b32 s17, s17, s18
; SI-NEXT:    s_and_b32 s18, s57, 0xff
; SI-NEXT:    s_lshl_b32 s18, s18, 16
; SI-NEXT:    s_lshl_b32 s19, s56, 24
; SI-NEXT:    s_and_b32 s17, s17, 0xffff
; SI-NEXT:    s_or_b32 s18, s19, s18
; SI-NEXT:    s_or_b32 s17, s17, s18
; SI-NEXT:    s_and_b32 s18, s47, 0xff
; SI-NEXT:    s_lshl_b32 s19, s46, 8
; SI-NEXT:    s_or_b32 s18, s18, s19
; SI-NEXT:    s_and_b32 s19, s45, 0xff
; SI-NEXT:    s_lshl_b32 s19, s19, 16
; SI-NEXT:    s_lshl_b32 s20, s44, 24
; SI-NEXT:    s_and_b32 s18, s18, 0xffff
; SI-NEXT:    s_or_b32 s19, s20, s19
; SI-NEXT:    s_or_b32 s18, s18, s19
; SI-NEXT:    s_and_b32 s19, s43, 0xff
; SI-NEXT:    s_lshl_b32 s20, s42, 8
; SI-NEXT:    s_or_b32 s19, s19, s20
; SI-NEXT:    s_and_b32 s20, s41, 0xff
; SI-NEXT:    s_and_b32 s14, s14, 0xff
; SI-NEXT:    s_lshl_b32 s13, s13, 8
; SI-NEXT:    s_and_b32 s11, s11, 0xff
; SI-NEXT:    s_and_b32 s9, s9, 0xff
; SI-NEXT:    s_lshl_b32 s8, s8, 8
; SI-NEXT:    s_and_b32 s6, s6, 0xff
; SI-NEXT:    s_lshl_b32 s20, s20, 16
; SI-NEXT:    s_lshl_b32 s21, s40, 24
; SI-NEXT:    s_or_b32 s13, s14, s13
; SI-NEXT:    s_lshl_b32 s11, s11, 16
; SI-NEXT:    s_lshl_b32 s10, s10, 24
; SI-NEXT:    s_or_b32 s8, s9, s8
; SI-NEXT:    s_lshl_b32 s6, s6, 16
; SI-NEXT:    s_lshl_b32 s5, s5, 24
; SI-NEXT:    s_and_b32 s19, s19, 0xffff
; SI-NEXT:    s_or_b32 s20, s21, s20
; SI-NEXT:    s_and_b32 s13, s13, 0xffff
; SI-NEXT:    s_or_b32 s10, s10, s11
; SI-NEXT:    s_and_b32 s8, s8, 0xffff
; SI-NEXT:    s_or_b32 s5, s5, s6
; SI-NEXT:    s_or_b32 s19, s19, s20
; SI-NEXT:    s_or_b32 s10, s13, s10
; SI-NEXT:    s_or_b32 s5, s8, s5
; SI-NEXT:    s_branch .LBB77_3
; SI-NEXT:  .LBB77_2: ; %cmp.true
; SI-NEXT:    s_add_i32 s16, s16, 3
; SI-NEXT:    s_and_b32 s4, s16, 0xff
; SI-NEXT:    s_lshl_b32 s7, s17, 8
; SI-NEXT:    s_add_i32 s18, s18, 3
; SI-NEXT:    s_or_b32 s4, s7, s4
; SI-NEXT:    s_and_b32 s12, s18, 0xff
; SI-NEXT:    s_addk_i32 s4, 0x300
; SI-NEXT:    s_lshl_b32 s7, s19, 24
; SI-NEXT:    s_lshl_b32 s12, s12, 16
; SI-NEXT:    s_and_b32 s4, s4, 0xffff
; SI-NEXT:    s_or_b32 s7, s7, s12
; SI-NEXT:    s_add_i32 s20, s20, 3
; SI-NEXT:    s_or_b32 s4, s7, s4
; SI-NEXT:    s_and_b32 s7, s20, 0xff
; SI-NEXT:    s_lshl_b32 s12, s21, 8
; SI-NEXT:    s_add_i32 s22, s22, 3
; SI-NEXT:    s_or_b32 s7, s12, s7
; SI-NEXT:    s_and_b32 s16, s22, 0xff
; SI-NEXT:    s_addk_i32 s7, 0x300
; SI-NEXT:    s_lshl_b32 s12, s23, 24
; SI-NEXT:    s_lshl_b32 s16, s16, 16
; SI-NEXT:    s_and_b32 s7, s7, 0xffff
; SI-NEXT:    s_or_b32 s12, s12, s16
; SI-NEXT:    s_add_i32 s24, s24, 3
; SI-NEXT:    s_or_b32 s7, s12, s7
; SI-NEXT:    s_and_b32 s12, s24, 0xff
; SI-NEXT:    s_lshl_b32 s16, s25, 8
; SI-NEXT:    s_add_i32 s26, s26, 3
; SI-NEXT:    s_or_b32 s12, s16, s12
; SI-NEXT:    s_and_b32 s17, s26, 0xff
; SI-NEXT:    s_addk_i32 s12, 0x300
; SI-NEXT:    s_lshl_b32 s16, s27, 24
; SI-NEXT:    s_lshl_b32 s17, s17, 16
; SI-NEXT:    s_and_b32 s12, s12, 0xffff
; SI-NEXT:    s_or_b32 s16, s16, s17
; SI-NEXT:    s_add_i32 s28, s28, 3
; SI-NEXT:    s_or_b32 s12, s16, s12
; SI-NEXT:    s_and_b32 s16, s28, 0xff
; SI-NEXT:    s_lshl_b32 s17, s29, 8
; SI-NEXT:    s_add_i32 s72, s72, 3
; SI-NEXT:    s_or_b32 s16, s17, s16
; SI-NEXT:    s_and_b32 s17, s72, 0xff
; SI-NEXT:    s_addk_i32 s16, 0x300
; SI-NEXT:    s_lshl_b32 s15, s15, 24
; SI-NEXT:    s_lshl_b32 s17, s17, 16
; SI-NEXT:    s_and_b32 s16, s16, 0xffff
; SI-NEXT:    s_or_b32 s15, s15, s17
; SI-NEXT:    s_add_i32 s63, s63, 3
; SI-NEXT:    s_or_b32 s15, s15, s16
; SI-NEXT:    s_and_b32 s16, s63, 0xff
; SI-NEXT:    s_lshl_b32 s17, s62, 8
; SI-NEXT:    s_add_i32 s61, s61, 3
; SI-NEXT:    s_or_b32 s16, s17, s16
; SI-NEXT:    s_and_b32 s18, s61, 0xff
; SI-NEXT:    s_addk_i32 s16, 0x300
; SI-NEXT:    s_lshl_b32 s17, s60, 24
; SI-NEXT:    s_lshl_b32 s18, s18, 16
; SI-NEXT:    s_and_b32 s16, s16, 0xffff
; SI-NEXT:    s_or_b32 s17, s17, s18
; SI-NEXT:    s_add_i32 s59, s59, 3
; SI-NEXT:    s_or_b32 s16, s17, s16
; SI-NEXT:    s_and_b32 s17, s59, 0xff
; SI-NEXT:    s_lshl_b32 s18, s58, 8
; SI-NEXT:    s_add_i32 s57, s57, 3
; SI-NEXT:    s_or_b32 s17, s18, s17
; SI-NEXT:    s_and_b32 s19, s57, 0xff
; SI-NEXT:    s_addk_i32 s17, 0x300
; SI-NEXT:    s_lshl_b32 s18, s56, 24
; SI-NEXT:    s_lshl_b32 s19, s19, 16
; SI-NEXT:    s_and_b32 s17, s17, 0xffff
; SI-NEXT:    s_or_b32 s18, s18, s19
; SI-NEXT:    s_add_i32 s47, s47, 3
; SI-NEXT:    s_or_b32 s17, s18, s17
; SI-NEXT:    s_and_b32 s18, s47, 0xff
; SI-NEXT:    s_lshl_b32 s19, s46, 8
; SI-NEXT:    s_add_i32 s45, s45, 3
; SI-NEXT:    s_or_b32 s18, s19, s18
; SI-NEXT:    s_and_b32 s20, s45, 0xff
; SI-NEXT:    s_addk_i32 s18, 0x300
; SI-NEXT:    s_lshl_b32 s19, s44, 24
; SI-NEXT:    s_lshl_b32 s20, s20, 16
; SI-NEXT:    s_and_b32 s18, s18, 0xffff
; SI-NEXT:    s_or_b32 s19, s19, s20
; SI-NEXT:    s_add_i32 s43, s43, 3
; SI-NEXT:    s_add_i32 s14, s14, 3
; SI-NEXT:    s_add_i32 s9, s9, 3
; SI-NEXT:    s_or_b32 s18, s19, s18
; SI-NEXT:    s_and_b32 s19, s43, 0xff
; SI-NEXT:    s_lshl_b32 s20, s42, 8
; SI-NEXT:    s_add_i32 s41, s41, 3
; SI-NEXT:    s_and_b32 s14, s14, 0xff
; SI-NEXT:    s_lshl_b32 s13, s13, 8
; SI-NEXT:    s_add_i32 s11, s11, 3
; SI-NEXT:    s_and_b32 s9, s9, 0xff
; SI-NEXT:    s_lshl_b32 s8, s8, 8
; SI-NEXT:    s_add_i32 s6, s6, 3
; SI-NEXT:    s_or_b32 s19, s20, s19
; SI-NEXT:    s_and_b32 s21, s41, 0xff
; SI-NEXT:    s_or_b32 s13, s13, s14
; SI-NEXT:    s_and_b32 s11, s11, 0xff
; SI-NEXT:    s_or_b32 s8, s8, s9
; SI-NEXT:    s_and_b32 s6, s6, 0xff
; SI-NEXT:    s_addk_i32 s19, 0x300
; SI-NEXT:    s_lshl_b32 s20, s40, 24
; SI-NEXT:    s_lshl_b32 s21, s21, 16
; SI-NEXT:    s_addk_i32 s13, 0x300
; SI-NEXT:    s_lshl_b32 s10, s10, 24
; SI-NEXT:    s_lshl_b32 s11, s11, 16
; SI-NEXT:    s_addk_i32 s8, 0x300
; SI-NEXT:    s_lshl_b32 s5, s5, 24
; SI-NEXT:    s_lshl_b32 s6, s6, 16
; SI-NEXT:    s_and_b32 s19, s19, 0xffff
; SI-NEXT:    s_or_b32 s20, s20, s21
; SI-NEXT:    s_and_b32 s13, s13, 0xffff
; SI-NEXT:    s_or_b32 s10, s10, s11
; SI-NEXT:    s_and_b32 s8, s8, 0xffff
; SI-NEXT:    s_or_b32 s5, s5, s6
; SI-NEXT:    s_or_b32 s19, s20, s19
; SI-NEXT:    s_or_b32 s10, s10, s13
; SI-NEXT:    s_or_b32 s5, s5, s8
; SI-NEXT:    s_add_i32 s4, s4, 0x3000000
; SI-NEXT:    s_add_i32 s7, s7, 0x3000000
; SI-NEXT:    s_add_i32 s12, s12, 0x3000000
; SI-NEXT:    s_add_i32 s15, s15, 0x3000000
; SI-NEXT:    s_add_i32 s16, s16, 0x3000000
; SI-NEXT:    s_add_i32 s17, s17, 0x3000000
; SI-NEXT:    s_add_i32 s18, s18, 0x3000000
; SI-NEXT:    s_add_i32 s19, s19, 0x3000000
; SI-NEXT:    s_add_i32 s10, s10, 0x3000000
; SI-NEXT:    s_add_i32 s5, s5, 0x3000000
; SI-NEXT:  .LBB77_3: ; %end
; SI-NEXT:    v_mov_b32_e32 v0, s4
; SI-NEXT:    v_mov_b32_e32 v1, s7
; SI-NEXT:    v_mov_b32_e32 v2, s12
; SI-NEXT:    v_mov_b32_e32 v3, s15
; SI-NEXT:    v_mov_b32_e32 v4, s16
; SI-NEXT:    v_mov_b32_e32 v5, s17
; SI-NEXT:    v_mov_b32_e32 v6, s18
; SI-NEXT:    v_mov_b32_e32 v7, s19
; SI-NEXT:    v_mov_b32_e32 v8, s10
; SI-NEXT:    v_mov_b32_e32 v9, s5
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v40i8_to_v5i64_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_readfirstlane_b32 s61, v26
; VI-NEXT:    v_readfirstlane_b32 s4, v25
; VI-NEXT:    v_readfirstlane_b32 s5, v24
; VI-NEXT:    v_readfirstlane_b32 s6, v23
; VI-NEXT:    v_readfirstlane_b32 s7, v22
; VI-NEXT:    v_readfirstlane_b32 s8, v21
; VI-NEXT:    v_readfirstlane_b32 s9, v20
; VI-NEXT:    v_readfirstlane_b32 s10, v19
; VI-NEXT:    v_readfirstlane_b32 s11, v18
; VI-NEXT:    v_readfirstlane_b32 s12, v17
; VI-NEXT:    v_readfirstlane_b32 s13, v16
; VI-NEXT:    v_readfirstlane_b32 s14, v15
; VI-NEXT:    v_readfirstlane_b32 s15, v14
; VI-NEXT:    v_readfirstlane_b32 s40, v13
; VI-NEXT:    v_readfirstlane_b32 s41, v12
; VI-NEXT:    v_readfirstlane_b32 s42, v11
; VI-NEXT:    v_readfirstlane_b32 s43, v10
; VI-NEXT:    v_readfirstlane_b32 s44, v9
; VI-NEXT:    v_readfirstlane_b32 s45, v8
; VI-NEXT:    v_readfirstlane_b32 s46, v7
; VI-NEXT:    v_readfirstlane_b32 s47, v6
; VI-NEXT:    v_readfirstlane_b32 s56, v5
; VI-NEXT:    v_readfirstlane_b32 s57, v4
; VI-NEXT:    v_readfirstlane_b32 s58, v3
; VI-NEXT:    v_readfirstlane_b32 s59, v2
; VI-NEXT:    v_readfirstlane_b32 s60, v1
; VI-NEXT:    s_cmp_lg_u32 s61, 0
; VI-NEXT:    v_readfirstlane_b32 s61, v0
; VI-NEXT:    s_cbranch_scc0 .LBB77_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    v_mov_b32_e32 v9, 0xc0c0004
; VI-NEXT:    v_mov_b32_e32 v1, s19
; VI-NEXT:    v_mov_b32_e32 v0, s17
; VI-NEXT:    v_perm_b32 v1, s18, v1, v9
; VI-NEXT:    v_perm_b32 v0, s16, v0, v9
; VI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT:    v_mov_b32_e32 v2, s23
; VI-NEXT:    v_or_b32_e32 v0, v0, v1
; VI-NEXT:    v_mov_b32_e32 v1, s21
; VI-NEXT:    v_perm_b32 v2, s22, v2, v9
; VI-NEXT:    v_perm_b32 v1, s20, v1, v9
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_mov_b32_e32 v3, s27
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_mov_b32_e32 v2, s25
; VI-NEXT:    v_perm_b32 v3, s26, v3, v9
; VI-NEXT:    v_perm_b32 v2, s24, v2, v9
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_mov_b32_e32 v4, s60
; VI-NEXT:    v_or_b32_e32 v2, v2, v3
; VI-NEXT:    v_mov_b32_e32 v3, s29
; VI-NEXT:    v_perm_b32 v4, s61, v4, v9
; VI-NEXT:    v_perm_b32 v3, s28, v3, v9
; VI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT:    v_mov_b32_e32 v5, s56
; VI-NEXT:    v_or_b32_e32 v3, v3, v4
; VI-NEXT:    v_mov_b32_e32 v4, s58
; VI-NEXT:    v_perm_b32 v5, s57, v5, v9
; VI-NEXT:    v_perm_b32 v4, s59, v4, v9
; VI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT:    v_mov_b32_e32 v6, s44
; VI-NEXT:    v_or_b32_e32 v4, v4, v5
; VI-NEXT:    v_mov_b32_e32 v5, s46
; VI-NEXT:    v_perm_b32 v6, s45, v6, v9
; VI-NEXT:    v_perm_b32 v5, s47, v5, v9
; VI-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT:    v_mov_b32_e32 v7, s40
; VI-NEXT:    v_or_b32_e32 v5, v5, v6
; VI-NEXT:    v_mov_b32_e32 v6, s42
; VI-NEXT:    v_perm_b32 v7, s41, v7, v9
; VI-NEXT:    v_perm_b32 v6, s43, v6, v9
; VI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT:    v_mov_b32_e32 v8, s12
; VI-NEXT:    v_or_b32_e32 v6, v6, v7
; VI-NEXT:    v_mov_b32_e32 v7, s14
; VI-NEXT:    v_perm_b32 v8, s13, v8, v9
; VI-NEXT:    v_perm_b32 v7, s15, v7, v9
; VI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT:    v_mov_b32_e32 v10, s8
; VI-NEXT:    v_or_b32_e32 v7, v7, v8
; VI-NEXT:    v_mov_b32_e32 v8, s10
; VI-NEXT:    v_perm_b32 v10, s9, v10, v9
; VI-NEXT:    v_perm_b32 v8, s11, v8, v9
; VI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT:    v_or_b32_e32 v8, v8, v10
; VI-NEXT:    v_mov_b32_e32 v10, s6
; VI-NEXT:    v_mov_b32_e32 v11, s4
; VI-NEXT:    v_perm_b32 v10, s7, v10, v9
; VI-NEXT:    v_perm_b32 v9, s5, v11, v9
; VI-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT:    v_or_b32_e32 v9, v10, v9
; VI-NEXT:    s_setpc_b64 s[30:31]
; VI-NEXT:  .LBB77_2: ; %cmp.true
; VI-NEXT:    s_add_i32 s16, s16, 3
; VI-NEXT:    v_mov_b32_e32 v0, s17
; VI-NEXT:    v_mov_b32_e32 v9, 0xc0c0004
; VI-NEXT:    s_add_i32 s18, s18, 3
; VI-NEXT:    v_mov_b32_e32 v1, s19
; VI-NEXT:    v_perm_b32 v0, s16, v0, v9
; VI-NEXT:    v_perm_b32 v1, s18, v1, v9
; VI-NEXT:    v_add_u32_e32 v0, vcc, 0x300, v0
; VI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s20, s20, 3
; VI-NEXT:    v_mov_b32_e32 v1, s21
; VI-NEXT:    s_add_i32 s22, s22, 3
; VI-NEXT:    v_mov_b32_e32 v2, s23
; VI-NEXT:    v_perm_b32 v1, s20, v1, v9
; VI-NEXT:    v_perm_b32 v2, s22, v2, v9
; VI-NEXT:    v_add_u32_e32 v1, vcc, 0x300, v1
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s24, s24, 3
; VI-NEXT:    v_mov_b32_e32 v2, s25
; VI-NEXT:    s_add_i32 s26, s26, 3
; VI-NEXT:    v_mov_b32_e32 v3, s27
; VI-NEXT:    v_perm_b32 v2, s24, v2, v9
; VI-NEXT:    v_perm_b32 v3, s26, v3, v9
; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x300, v2
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s28, s28, 3
; VI-NEXT:    v_mov_b32_e32 v3, s29
; VI-NEXT:    s_add_i32 s61, s61, 3
; VI-NEXT:    v_mov_b32_e32 v4, s60
; VI-NEXT:    v_perm_b32 v3, s28, v3, v9
; VI-NEXT:    v_perm_b32 v4, s61, v4, v9
; VI-NEXT:    v_add_u32_e32 v3, vcc, 0x300, v3
; VI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT:    v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s59, s59, 3
; VI-NEXT:    v_mov_b32_e32 v4, s58
; VI-NEXT:    s_add_i32 s57, s57, 3
; VI-NEXT:    v_mov_b32_e32 v5, s56
; VI-NEXT:    v_perm_b32 v4, s59, v4, v9
; VI-NEXT:    v_perm_b32 v5, s57, v5, v9
; VI-NEXT:    v_add_u32_e32 v4, vcc, 0x300, v4
; VI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT:    v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s47, s47, 3
; VI-NEXT:    v_mov_b32_e32 v5, s46
; VI-NEXT:    s_add_i32 s45, s45, 3
; VI-NEXT:    v_mov_b32_e32 v6, s44
; VI-NEXT:    v_perm_b32 v5, s47, v5, v9
; VI-NEXT:    v_perm_b32 v6, s45, v6, v9
; VI-NEXT:    v_add_u32_e32 v5, vcc, 0x300, v5
; VI-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT:    v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s43, s43, 3
; VI-NEXT:    v_mov_b32_e32 v6, s42
; VI-NEXT:    s_add_i32 s41, s41, 3
; VI-NEXT:    v_mov_b32_e32 v7, s40
; VI-NEXT:    v_perm_b32 v6, s43, v6, v9
; VI-NEXT:    v_perm_b32 v7, s41, v7, v9
; VI-NEXT:    v_add_u32_e32 v6, vcc, 0x300, v6
; VI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT:    v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s15, s15, 3
; VI-NEXT:    v_mov_b32_e32 v7, s14
; VI-NEXT:    s_add_i32 s13, s13, 3
; VI-NEXT:    v_mov_b32_e32 v8, s12
; VI-NEXT:    v_perm_b32 v7, s15, v7, v9
; VI-NEXT:    v_perm_b32 v8, s13, v8, v9
; VI-NEXT:    v_add_u32_e32 v7, vcc, 0x300, v7
; VI-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT:    v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s11, s11, 3
; VI-NEXT:    v_mov_b32_e32 v8, s10
; VI-NEXT:    s_add_i32 s9, s9, 3
; VI-NEXT:    v_mov_b32_e32 v10, s8
; VI-NEXT:    v_perm_b32 v8, s11, v8, v9
; VI-NEXT:    v_perm_b32 v10, s9, v10, v9
; VI-NEXT:    v_add_u32_e32 v8, vcc, 0x300, v8
; VI-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT:    v_or_b32_sdwa v8, v10, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    s_add_i32 s7, s7, 3
; VI-NEXT:    v_mov_b32_e32 v10, s6
; VI-NEXT:    s_add_i32 s5, s5, 3
; VI-NEXT:    v_mov_b32_e32 v11, s4
; VI-NEXT:    v_perm_b32 v10, s7, v10, v9
; VI-NEXT:    v_perm_b32 v9, s5, v11, v9
; VI-NEXT:    v_add_u32_e32 v10, vcc, 0x300, v10
; VI-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT:    v_or_b32_sdwa v9, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; VI-NEXT:    v_add_u32_e32 v0, vcc, 0x3000000, v0
; VI-NEXT:    v_add_u32_e32 v1, vcc, 0x3000000, v1
; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x3000000, v2
; VI-NEXT:    v_add_u32_e32 v3, vcc, 0x3000000, v3
; VI-NEXT:    v_add_u32_e32 v4, vcc, 0x3000000, v4
; VI-NEXT:    v_add_u32_e32 v5, vcc, 0x3000000, v5
; VI-NEXT:    v_add_u32_e32 v6, vcc, 0x3000000, v6
; VI-NEXT:    v_add_u32_e32 v7, vcc, 0x3000000, v7
; VI-NEXT:    v_add_u32_e32 v8, vcc, 0x3000000, v8
; VI-NEXT:    v_add_u32_e32 v9, vcc, 0x3000000, v9
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v40i8_to_v5i64_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_readfirstlane_b32 s61, v26
; GFX9-NEXT:    v_readfirstlane_b32 s4, v25
; GFX9-NEXT:    v_readfirstlane_b32 s5, v24
; GFX9-NEXT:    v_readfirstlane_b32 s6, v23
; GFX9-NEXT:    v_readfirstlane_b32 s7, v22
; GFX9-NEXT:    v_readfirstlane_b32 s8, v21
; GFX9-NEXT:    v_readfirstlane_b32 s9, v20
; GFX9-NEXT:    v_readfirstlane_b32 s10, v19
; GFX9-NEXT:    v_readfirstlane_b32 s11, v18
; GFX9-NEXT:    v_readfirstlane_b32 s12, v17
; GFX9-NEXT:    v_readfirstlane_b32 s13, v16
; GFX9-NEXT:    v_readfirstlane_b32 s14, v15
; GFX9-NEXT:    v_readfirstlane_b32 s15, v14
; GFX9-NEXT:    v_readfirstlane_b32 s40, v13
; GFX9-NEXT:    v_readfirstlane_b32 s41, v12
; GFX9-NEXT:    v_readfirstlane_b32 s42, v11
; GFX9-NEXT:    v_readfirstlane_b32 s43, v10
; GFX9-NEXT:    v_readfirstlane_b32 s44, v9
; GFX9-NEXT:    v_readfirstlane_b32 s45, v8
; GFX9-NEXT:    v_readfirstlane_b32 s46, v7
; GFX9-NEXT:    v_readfirstlane_b32 s47, v6
; GFX9-NEXT:    v_readfirstlane_b32 s56, v5
; GFX9-NEXT:    v_readfirstlane_b32 s57, v4
; GFX9-NEXT:    v_readfirstlane_b32 s58, v3
; GFX9-NEXT:    v_readfirstlane_b32 s59, v2
; GFX9-NEXT:    v_readfirstlane_b32 s60, v1
; GFX9-NEXT:    s_cmp_lg_u32 s61, 0
; GFX9-NEXT:    v_readfirstlane_b32 s61, v0
; GFX9-NEXT:    s_cbranch_scc0 .LBB77_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    v_mov_b32_e32 v9, 0xc0c0004
; GFX9-NEXT:    v_mov_b32_e32 v1, s19
; GFX9-NEXT:    v_mov_b32_e32 v0, s17
; GFX9-NEXT:    v_perm_b32 v1, s18, v1, v9
; GFX9-NEXT:    v_perm_b32 v0, s16, v0, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT:    v_mov_b32_e32 v2, s23
; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
; GFX9-NEXT:    v_mov_b32_e32 v1, s21
; GFX9-NEXT:    v_perm_b32 v2, s22, v2, v9
; GFX9-NEXT:    v_perm_b32 v1, s20, v1, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT:    v_mov_b32_e32 v3, s27
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v2
; GFX9-NEXT:    v_mov_b32_e32 v2, s25
; GFX9-NEXT:    v_perm_b32 v3, s26, v3, v9
; GFX9-NEXT:    v_perm_b32 v2, s24, v2, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT:    v_mov_b32_e32 v4, s60
; GFX9-NEXT:    v_or_b32_e32 v2, v2, v3
; GFX9-NEXT:    v_mov_b32_e32 v3, s29
; GFX9-NEXT:    v_perm_b32 v4, s61, v4, v9
; GFX9-NEXT:    v_perm_b32 v3, s28, v3, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; GFX9-NEXT:    v_mov_b32_e32 v5, s56
; GFX9-NEXT:    v_or_b32_e32 v3, v3, v4
; GFX9-NEXT:    v_mov_b32_e32 v4, s58
; GFX9-NEXT:    v_perm_b32 v5, s57, v5, v9
; GFX9-NEXT:    v_perm_b32 v4, s59, v4, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
; GFX9-NEXT:    v_mov_b32_e32 v6, s44
; GFX9-NEXT:    v_or_b32_e32 v4, v4, v5
; GFX9-NEXT:    v_mov_b32_e32 v5, s46
; GFX9-NEXT:    v_perm_b32 v6, s45, v6, v9
; GFX9-NEXT:    v_perm_b32 v5, s47, v5, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; GFX9-NEXT:    v_mov_b32_e32 v7, s40
; GFX9-NEXT:    v_or_b32_e32 v5, v5, v6
; GFX9-NEXT:    v_mov_b32_e32 v6, s42
; GFX9-NEXT:    v_perm_b32 v7, s41, v7, v9
; GFX9-NEXT:    v_perm_b32 v6, s43, v6, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; GFX9-NEXT:    v_mov_b32_e32 v8, s12
; GFX9-NEXT:    v_or_b32_e32 v6, v6, v7
; GFX9-NEXT:    v_mov_b32_e32 v7, s14
; GFX9-NEXT:    v_perm_b32 v8, s13, v8, v9
; GFX9-NEXT:    v_perm_b32 v7, s15, v7, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; GFX9-NEXT:    v_mov_b32_e32 v10, s8
; GFX9-NEXT:    v_or_b32_e32 v7, v7, v8
; GFX9-NEXT:    v_mov_b32_e32 v8, s10
; GFX9-NEXT:    v_perm_b32 v10, s9, v10, v9
; GFX9-NEXT:    v_perm_b32 v8, s11, v8, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; GFX9-NEXT:    v_or_b32_e32 v8, v8, v10
; GFX9-NEXT:    v_mov_b32_e32 v10, s6
; GFX9-NEXT:    v_mov_b32_e32 v11, s4
; GFX9-NEXT:    v_perm_b32 v10, s7, v10, v9
; GFX9-NEXT:    v_perm_b32 v9, s5, v11, v9
; GFX9-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; GFX9-NEXT:    v_or_b32_e32 v9, v10, v9
; GFX9-NEXT:    s_setpc_b64 s[30:31]
; GFX9-NEXT:  .LBB77_2: ; %cmp.true
; GFX9-NEXT:    s_add_i32 s16, s16, 3
; GFX9-NEXT:    v_mov_b32_e32 v0, s17
; GFX9-NEXT:    v_mov_b32_e32 v9, 0xc0c0004
; GFX9-NEXT:    s_add_i32 s18, s18, 3
; GFX9-NEXT:    v_mov_b32_e32 v1, s19
; GFX9-NEXT:    v_perm_b32 v0, s16, v0, v9
; GFX9-NEXT:    s_movk_i32 s16, 0x300
; GFX9-NEXT:    v_perm_b32 v1, s18, v1, v9
; GFX9-NEXT:    v_add_u32_e32 v0, 0x300, v0
; GFX9-NEXT:    v_add_u32_sdwa v1, v1, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s20, s20, 3
; GFX9-NEXT:    v_mov_b32_e32 v1, s21
; GFX9-NEXT:    s_add_i32 s22, s22, 3
; GFX9-NEXT:    v_mov_b32_e32 v2, s23
; GFX9-NEXT:    v_perm_b32 v1, s20, v1, v9
; GFX9-NEXT:    v_perm_b32 v2, s22, v2, v9
; GFX9-NEXT:    v_add_u32_e32 v1, 0x300, v1
; GFX9-NEXT:    v_add_u32_sdwa v2, v2, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s24, s24, 3
; GFX9-NEXT:    v_mov_b32_e32 v2, s25
; GFX9-NEXT:    s_add_i32 s26, s26, 3
; GFX9-NEXT:    v_mov_b32_e32 v3, s27
; GFX9-NEXT:    v_perm_b32 v2, s24, v2, v9
; GFX9-NEXT:    v_perm_b32 v3, s26, v3, v9
; GFX9-NEXT:    v_add_u32_e32 v2, 0x300, v2
; GFX9-NEXT:    v_add_u32_sdwa v3, v3, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s28, s28, 3
; GFX9-NEXT:    v_mov_b32_e32 v3, s29
; GFX9-NEXT:    s_add_i32 s61, s61, 3
; GFX9-NEXT:    v_mov_b32_e32 v4, s60
; GFX9-NEXT:    v_perm_b32 v3, s28, v3, v9
; GFX9-NEXT:    v_perm_b32 v4, s61, v4, v9
; GFX9-NEXT:    v_add_u32_e32 v3, 0x300, v3
; GFX9-NEXT:    v_add_u32_sdwa v4, v4, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s59, s59, 3
; GFX9-NEXT:    v_mov_b32_e32 v4, s58
; GFX9-NEXT:    s_add_i32 s57, s57, 3
; GFX9-NEXT:    v_mov_b32_e32 v5, s56
; GFX9-NEXT:    v_perm_b32 v4, s59, v4, v9
; GFX9-NEXT:    v_perm_b32 v5, s57, v5, v9
; GFX9-NEXT:    v_add_u32_e32 v4, 0x300, v4
; GFX9-NEXT:    v_add_u32_sdwa v5, v5, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s47, s47, 3
; GFX9-NEXT:    v_mov_b32_e32 v5, s46
; GFX9-NEXT:    s_add_i32 s45, s45, 3
; GFX9-NEXT:    v_mov_b32_e32 v6, s44
; GFX9-NEXT:    v_perm_b32 v5, s47, v5, v9
; GFX9-NEXT:    v_perm_b32 v6, s45, v6, v9
; GFX9-NEXT:    v_add_u32_e32 v5, 0x300, v5
; GFX9-NEXT:    v_add_u32_sdwa v6, v6, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v5, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s43, s43, 3
; GFX9-NEXT:    v_mov_b32_e32 v6, s42
; GFX9-NEXT:    s_add_i32 s41, s41, 3
; GFX9-NEXT:    v_mov_b32_e32 v7, s40
; GFX9-NEXT:    v_perm_b32 v6, s43, v6, v9
; GFX9-NEXT:    v_perm_b32 v7, s41, v7, v9
; GFX9-NEXT:    v_add_u32_e32 v6, 0x300, v6
; GFX9-NEXT:    v_add_u32_sdwa v7, v7, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v6, v6, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s15, s15, 3
; GFX9-NEXT:    v_mov_b32_e32 v7, s14
; GFX9-NEXT:    s_add_i32 s13, s13, 3
; GFX9-NEXT:    v_mov_b32_e32 v8, s12
; GFX9-NEXT:    v_perm_b32 v7, s15, v7, v9
; GFX9-NEXT:    v_perm_b32 v8, s13, v8, v9
; GFX9-NEXT:    v_add_u32_e32 v7, 0x300, v7
; GFX9-NEXT:    v_add_u32_sdwa v8, v8, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s11, s11, 3
; GFX9-NEXT:    v_mov_b32_e32 v8, s10
; GFX9-NEXT:    s_add_i32 s9, s9, 3
; GFX9-NEXT:    v_mov_b32_e32 v10, s8
; GFX9-NEXT:    v_perm_b32 v8, s11, v8, v9
; GFX9-NEXT:    v_perm_b32 v10, s9, v10, v9
; GFX9-NEXT:    v_add_u32_e32 v8, 0x300, v8
; GFX9-NEXT:    v_add_u32_sdwa v10, v10, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v8, v8, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_add_i32 s7, s7, 3
; GFX9-NEXT:    v_mov_b32_e32 v10, s6
; GFX9-NEXT:    s_add_i32 s5, s5, 3
; GFX9-NEXT:    v_mov_b32_e32 v11, s4
; GFX9-NEXT:    v_perm_b32 v10, s7, v10, v9
; GFX9-NEXT:    v_perm_b32 v9, s5, v11, v9
; GFX9-NEXT:    v_add_u32_e32 v10, 0x300, v10
; GFX9-NEXT:    v_add_u32_sdwa v9, v9, s16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT:    v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v40i8_to_v5i64_scalar:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s58, v22
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s4, v21
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s5, v20
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s6, v19
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s7, v18
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s9, v17
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s10, v16
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s8, v15
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s11, v14
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s12, v13
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s13, v12
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s14, v11
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s15, v10
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s40, v9
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s41, v8
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s42, v7
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s43, v6
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s44, v5
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s45, v4
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s46, v3
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s47, v2
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s56, v1
; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s57, v0
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v5, 0xc0c0004
; GFX11-TRUE16-NEXT:    s_cmp_lg_u32 s58, 0
; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB77_2
; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_perm_b32 v1, s2, s3, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v3, s18, s19, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, s22, s23, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v8, s26, s27, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v10, s57, s56, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v0, s0, s1, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v2, s16, s17, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v4, s20, s21, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, s24, s25, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v9, s28, s29, v5
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v1
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v2, v3
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v4, v6
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, s45, s44, v5
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v7, v8
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v9, v10
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, s41, s40, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v10, s13, s12, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v11, s10, s9, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v13, s5, s4, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v8, s47, s46, v5
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; GFX11-TRUE16-NEXT:    v_perm_b32 v9, s43, s42, v5
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; GFX11-TRUE16-NEXT:    v_perm_b32 v12, s15, s14, v5
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT:    v_perm_b32 v14, s11, s8, v5
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; GFX11-TRUE16-NEXT:    v_perm_b32 v15, s7, s6, v5
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v8, v6
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v9, v7
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v12, v10
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v14, v11
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v15, v13
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT:  .LBB77_2: ; %cmp.true
; GFX11-TRUE16-NEXT:    s_add_i32 s0, s0, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s16, s16, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s18, s18, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s20, s20, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s22, s22, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s24, s24, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s26, s26, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s28, s28, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s57, s57, 3
; GFX11-TRUE16-NEXT:    v_perm_b32 v0, s0, s1, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v1, s2, s3, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v2, s16, s17, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v3, s18, s19, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v4, s20, s21, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, s22, s23, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, s24, s25, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v8, s26, s27, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v9, s28, s29, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v10, s57, s56, v5
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v4, 0x300, v4
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v6, 0x300, v6
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v8, 0x300, v8
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v9, 0x300, v9
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v10, 0x300, v10
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT:    s_add_i32 s47, s47, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s45, s45, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s43, s43, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s41, s41, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s15, s15, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s13, s13, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s11, s11, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s10, s10, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s7, s7, 3
; GFX11-TRUE16-NEXT:    s_add_i32 s5, s5, 3
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v1
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v2, v3
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v4, v6
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v7, v8
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v9, v10
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, s47, s46, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, s45, s44, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v8, s43, s42, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v9, s41, s40, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v10, s15, s14, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v11, s13, s12, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v12, s11, s8, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v13, s10, s9, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v14, s7, s6, v5
; GFX11-TRUE16-NEXT:    v_perm_b32 v5, s5, s4, v5
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v6, 0x300, v6
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v8, 0x300, v8
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v9, 0x300, v9
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v10, 0x300, v10
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v11, 0x300, v11
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v13, 0x300, v13
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v14, 0x300, v14
; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v5
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v6, v7
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v8, v9
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v10, v11
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v12, v13
; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v14, v15
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v40i8_to_v5i64_scalar:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s58, v22
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s5, v21
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s6, v20
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s4, v19
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s7, v18
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s9, v17
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s11, v16
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s8, v15
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s10, v14
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s12, v13
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s13, v12
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s14, v11
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s15, v10
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s40, v9
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s42, v8
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s41, v7
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s43, v6
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s45, v5
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s46, v4
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s44, v3
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s47, v2
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s56, v1
; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s57, v0
; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, 0xc0c0004
; GFX11-FAKE16-NEXT:    s_cmp_lg_u32 s58, 0
; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB77_2
; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_perm_b32 v1, s2, s3, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v3, s18, s19, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, s22, s23, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, s26, s27, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v10, s57, s56, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v0, s0, s1, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v2, s16, s17, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v4, s20, s21, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, s24, s25, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, s28, s29, v5
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v6
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, s46, s45, v5
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v7, v8
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v9, v10
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, s42, s40, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v10, s13, s12, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v11, s11, s9, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v13, s6, s5, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, s47, s44, v5
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, s43, s41, v5
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; GFX11-FAKE16-NEXT:    v_perm_b32 v12, s15, s14, v5
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; GFX11-FAKE16-NEXT:    v_perm_b32 v14, s10, s8, v5
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; GFX11-FAKE16-NEXT:    v_perm_b32 v15, s7, s4, v5
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v8, v6
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v9, v7
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v12, v10
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v14, v11
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v15, v13
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT:  .LBB77_2: ; %cmp.true
; GFX11-FAKE16-NEXT:    s_add_i32 s0, s0, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s2, s2, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s16, s16, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s18, s18, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s20, s20, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s22, s22, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s24, s24, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s26, s26, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s28, s28, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s57, s57, 3
; GFX11-FAKE16-NEXT:    v_perm_b32 v0, s0, s1, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v1, s2, s3, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v2, s16, s17, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v3, s18, s19, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v4, s20, s21, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, s22, s23, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, s24, s25, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, s26, s27, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, s28, s29, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v10, s57, s56, v5
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, 0x300, v4
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v6, 0x300, v6
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v8, 0x300, v8
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v9, 0x300, v9
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v10, 0x300, v10
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
; GFX11-FAKE16-NEXT:    s_add_i32 s47, s47, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s46, s46, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s43, s43, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s42, s42, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s15, s15, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s13, s13, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s10, s10, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s11, s11, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s7, s7, 3
; GFX11-FAKE16-NEXT:    s_add_i32 s6, s6, 3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v6
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v7, v8
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v9, v10
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, s47, s44, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, s46, s45, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, s43, s41, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, s42, s40, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v10, s15, s14, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v11, s13, s12, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v12, s10, s8, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v13, s11, s9, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v14, s7, s4, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v5, s6, s5, v5
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v6, 0x300, v6
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v8, 0x300, v8
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v9, 0x300, v9
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v10, 0x300, v10
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v11, 0x300, v11
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v13, 0x300, v13
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v14, 0x300, v14
; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v5
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v6, v7
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v8, v9
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v10, v11
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v12, v13
; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v14, v15
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <40 x i8> %a, splat (i8 3)
  %a2 = bitcast <40 x i8> %a1 to <5 x i64>
  br label %end

cmp.false:
  %a3 = bitcast <40 x i8> %a to <5 x i64>
  br label %end

end:
  %phi = phi <5 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <5 x i64> %phi
}

define <40 x i8> @bitcast_v5i64_to_v40i8(<5 x i64> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v5i64_to_v40i8:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
; SI-NEXT:    ; implicit-def: $vgpr35
; SI-NEXT:    ; implicit-def: $vgpr33
; SI-NEXT:    ; implicit-def: $vgpr32
; SI-NEXT:    ; implicit-def: $vgpr48
; SI-NEXT:    ; implicit-def: $vgpr39
; SI-NEXT:    ; implicit-def: $vgpr38
; SI-NEXT:    ; implicit-def: $vgpr28
; SI-NEXT:    ; implicit-def: $vgpr27
; SI-NEXT:    ; implicit-def: $vgpr26
; SI-NEXT:    ; implicit-def: $vgpr37
; SI-NEXT:    ; implicit-def: $vgpr36
; SI-NEXT:    ; implicit-def: $vgpr34
; SI-NEXT:    ; implicit-def: $vgpr22
; SI-NEXT:    ; implicit-def: $vgpr21
; SI-NEXT:    ; implicit-def: $vgpr19
; SI-NEXT:    ; implicit-def: $vgpr31
; SI-NEXT:    ; implicit-def: $vgpr30
; SI-NEXT:    ; implicit-def: $vgpr29
; SI-NEXT:    ; implicit-def: $vgpr16
; SI-NEXT:    ; implicit-def: $vgpr15
; SI-NEXT:    ; implicit-def: $vgpr14
; SI-NEXT:    ; implicit-def: $vgpr25
; SI-NEXT:    ; implicit-def: $vgpr24
; SI-NEXT:    ; implicit-def: $vgpr23
; SI-NEXT:    ; implicit-def: $vgpr13
; SI-NEXT:    ; implicit-def: $vgpr12
; SI-NEXT:    ; implicit-def: $vgpr11
; SI-NEXT:    ; implicit-def: $vgpr20
; SI-NEXT:    ; implicit-def: $vgpr18
; SI-NEXT:    ; implicit-def: $vgpr17
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB78_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    v_alignbit_b32 v11, v10, v9, 24
; SI-NEXT:    v_alignbit_b32 v12, v10, v9, 16
; SI-NEXT:    v_alignbit_b32 v13, v10, v9, 8
; SI-NEXT:    v_alignbit_b32 v14, v8, v7, 24
; SI-NEXT:    v_alignbit_b32 v15, v8, v7, 16
; SI-NEXT:    v_alignbit_b32 v16, v8, v7, 8
; SI-NEXT:    v_alignbit_b32 v19, v6, v5, 24
; SI-NEXT:    v_alignbit_b32 v21, v6, v5, 16
; SI-NEXT:    v_alignbit_b32 v22, v6, v5, 8
; SI-NEXT:    v_alignbit_b32 v26, v4, v3, 24
; SI-NEXT:    v_alignbit_b32 v27, v4, v3, 16
; SI-NEXT:    v_alignbit_b32 v28, v4, v3, 8
; SI-NEXT:    v_alignbit_b32 v32, v2, v1, 24
; SI-NEXT:    v_alignbit_b32 v33, v2, v1, 16
; SI-NEXT:    v_alignbit_b32 v35, v2, v1, 8
; SI-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; SI-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; SI-NEXT:    v_lshrrev_b32_e32 v20, 8, v10
; SI-NEXT:    v_lshrrev_b32_e32 v23, 24, v8
; SI-NEXT:    v_lshrrev_b32_e32 v24, 16, v8
; SI-NEXT:    v_lshrrev_b32_e32 v25, 8, v8
; SI-NEXT:    v_lshrrev_b32_e32 v29, 24, v6
; SI-NEXT:    v_lshrrev_b32_e32 v30, 16, v6
; SI-NEXT:    v_lshrrev_b32_e32 v31, 8, v6
; SI-NEXT:    v_lshrrev_b32_e32 v34, 24, v4
; SI-NEXT:    v_lshrrev_b32_e32 v36, 16, v4
; SI-NEXT:    v_lshrrev_b32_e32 v37, 8, v4
; SI-NEXT:    v_lshrrev_b32_e32 v38, 24, v2
; SI-NEXT:    v_lshrrev_b32_e32 v39, 16, v2
; SI-NEXT:    v_lshrrev_b32_e32 v48, 8, v2
; SI-NEXT:  .LBB78_2: ; %Flow
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB78_4
; SI-NEXT:  ; %bb.3: ; %cmp.true
; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v3
; SI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
; SI-NEXT:    v_add_i32_e32 v5, vcc, 3, v5
; SI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v6, vcc
; SI-NEXT:    v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT:    v_addc_u32_e32 v8, vcc, 0, v8, vcc
; SI-NEXT:    v_add_i32_e32 v9, vcc, 3, v9
; SI-NEXT:    v_addc_u32_e32 v10, vcc, 0, v10, vcc
; SI-NEXT:    v_alignbit_b32 v11, v10, v9, 24
; SI-NEXT:    v_alignbit_b32 v12, v10, v9, 16
; SI-NEXT:    v_alignbit_b32 v13, v10, v9, 8
; SI-NEXT:    v_alignbit_b32 v14, v8, v7, 24
; SI-NEXT:    v_alignbit_b32 v15, v8, v7, 16
; SI-NEXT:    v_alignbit_b32 v16, v8, v7, 8
; SI-NEXT:    v_alignbit_b32 v19, v6, v5, 24
; SI-NEXT:    v_alignbit_b32 v21, v6, v5, 16
; SI-NEXT:    v_alignbit_b32 v22, v6, v5, 8
; SI-NEXT:    v_alignbit_b32 v26, v4, v3, 24
; SI-NEXT:    v_alignbit_b32 v27, v4, v3, 16
; SI-NEXT:    v_alignbit_b32 v28, v4, v3, 8
; SI-NEXT:    v_alignbit_b32 v32, v2, v1, 24
; SI-NEXT:    v_alignbit_b32 v33, v2, v1, 16
; SI-NEXT:    v_alignbit_b32 v35, v2, v1, 8
; SI-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; SI-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; SI-NEXT:    v_lshrrev_b32_e32 v20, 8, v10
; SI-NEXT:    v_lshrrev_b32_e32 v23, 24, v8
; SI-NEXT:    v_lshrrev_b32_e32 v24, 16, v8
; SI-NEXT:    v_lshrrev_b32_e32 v25, 8, v8
; SI-NEXT:    v_lshrrev_b32_e32 v29, 24, v6
; SI-NEXT:    v_lshrrev_b32_e32 v30, 16, v6
; SI-NEXT:    v_lshrrev_b32_e32 v31, 8, v6
; SI-NEXT:    v_lshrrev_b32_e32 v34, 24, v4
; SI-NEXT:    v_lshrrev_b32_e32 v36, 16, v4
; SI-NEXT:    v_lshrrev_b32_e32 v37, 8, v4
; SI-NEXT:    v_lshrrev_b32_e32 v38, 24, v2
; SI-NEXT:    v_lshrrev_b32_e32 v39, 16, v2
; SI-NEXT:    v_lshrrev_b32_e32 v48, 8, v2
; SI-NEXT:  .LBB78_4: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v1
; SI-NEXT:    v_lshlrev_b32_e32 v35, 8, v35
; SI-NEXT:    v_and_b32_e32 v33, 0xff, v33
; SI-NEXT:    v_or_b32_e32 v1, v1, v35
; SI-NEXT:    v_lshlrev_b32_e32 v33, 16, v33
; SI-NEXT:    v_lshlrev_b32_e32 v32, 24, v32
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v32, v32, v33
; SI-NEXT:    v_or_b32_e32 v1, v1, v32
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v2
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v48
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v39
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v32, 24, v38
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v32, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v3
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v28
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v27
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v26
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v4
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v37
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v36
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v34
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v5
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v22
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v21
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v19
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v6
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v31
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v30
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v29
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v7
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v16
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v15
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v14
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v8
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v25
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v24
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v23
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v9
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v13
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v12
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v11
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_and_b32_e32 v1, 0xff, v10
; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v20
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    v_and_b32_e32 v2, 0xff, v18
; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v17
; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT:    v_or_b32_e32 v2, v3, v2
; SI-NEXT:    v_or_b32_e32 v1, v1, v2
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v5i64_to_v40i8:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
; VI-NEXT:    ; implicit-def: $vgpr16
; VI-NEXT:    ; implicit-def: $vgpr48
; VI-NEXT:    ; implicit-def: $vgpr15
; VI-NEXT:    ; implicit-def: $vgpr39
; VI-NEXT:    ; implicit-def: $vgpr38
; VI-NEXT:    ; implicit-def: $vgpr37
; VI-NEXT:    ; implicit-def: $vgpr36
; VI-NEXT:    ; implicit-def: $vgpr35
; VI-NEXT:    ; implicit-def: $vgpr14
; VI-NEXT:    ; implicit-def: $vgpr34
; VI-NEXT:    ; implicit-def: $vgpr33
; VI-NEXT:    ; implicit-def: $vgpr32
; VI-NEXT:    ; implicit-def: $vgpr31
; VI-NEXT:    ; implicit-def: $vgpr30
; VI-NEXT:    ; implicit-def: $vgpr13
; VI-NEXT:    ; implicit-def: $vgpr29
; VI-NEXT:    ; implicit-def: $vgpr28
; VI-NEXT:    ; implicit-def: $vgpr27
; VI-NEXT:    ; implicit-def: $vgpr26
; VI-NEXT:    ; implicit-def: $vgpr25
; VI-NEXT:    ; implicit-def: $vgpr12
; VI-NEXT:    ; implicit-def: $vgpr24
; VI-NEXT:    ; implicit-def: $vgpr23
; VI-NEXT:    ; implicit-def: $vgpr22
; VI-NEXT:    ; implicit-def: $vgpr21
; VI-NEXT:    ; implicit-def: $vgpr20
; VI-NEXT:    ; implicit-def: $vgpr19
; VI-NEXT:    ; implicit-def: $vgpr18
; VI-NEXT:    ; implicit-def: $vgpr17
; VI-NEXT:    ; implicit-def: $vgpr11
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB78_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; VI-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; VI-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; VI-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; VI-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; VI-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; VI-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; VI-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; VI-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
; VI-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
; VI-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
; VI-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
; VI-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
; VI-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
; VI-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
; VI-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
; VI-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
; VI-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; VI-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; VI-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; VI-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
; VI-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
; VI-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
; VI-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
; VI-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
; VI-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
; VI-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
; VI-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
; VI-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
; VI-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; VI-NEXT:  .LBB78_2: ; %Flow
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB78_4
; VI-NEXT:  ; %bb.3: ; %cmp.true
; VI-NEXT:    v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
; VI-NEXT:    v_add_u32_e32 v3, vcc, 3, v3
; VI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
; VI-NEXT:    v_add_u32_e32 v5, vcc, 3, v5
; VI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v6, vcc
; VI-NEXT:    v_add_u32_e32 v7, vcc, 3, v7
; VI-NEXT:    v_addc_u32_e32 v8, vcc, 0, v8, vcc
; VI-NEXT:    v_add_u32_e32 v9, vcc, 3, v9
; VI-NEXT:    v_addc_u32_e32 v10, vcc, 0, v10, vcc
; VI-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; VI-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; VI-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; VI-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; VI-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; VI-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; VI-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; VI-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; VI-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
; VI-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
; VI-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
; VI-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
; VI-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
; VI-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
; VI-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
; VI-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
; VI-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
; VI-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; VI-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; VI-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; VI-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
; VI-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
; VI-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
; VI-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
; VI-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
; VI-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
; VI-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
; VI-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
; VI-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
; VI-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; VI-NEXT:  .LBB78_4: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_mov_b32 s4, 0xc0c0004
; VI-NEXT:    v_perm_b32 v15, v48, v15, s4
; VI-NEXT:    v_perm_b32 v1, v1, v16, s4
; VI-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT:    v_or_b32_e32 v1, v1, v15
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT:    v_perm_b32 v1, v2, v39, s4
; VI-NEXT:    v_perm_b32 v2, v38, v37, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v35, v14, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
; VI-NEXT:    v_perm_b32 v1, v3, v36, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v33, v32, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; VI-NEXT:    v_perm_b32 v1, v4, v34, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v30, v13, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; VI-NEXT:    v_perm_b32 v1, v5, v31, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v28, v27, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; VI-NEXT:    v_perm_b32 v1, v6, v29, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v25, v12, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; VI-NEXT:    v_perm_b32 v1, v7, v26, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v23, v22, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; VI-NEXT:    v_perm_b32 v1, v8, v24, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v20, v11, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; VI-NEXT:    v_perm_b32 v1, v9, v21, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    v_perm_b32 v2, v18, v17, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; VI-NEXT:    v_perm_b32 v1, v10, v19, s4
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v5i64_to_v40i8:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
; GFX9-NEXT:    ; implicit-def: $vgpr16
; GFX9-NEXT:    ; implicit-def: $vgpr48
; GFX9-NEXT:    ; implicit-def: $vgpr15
; GFX9-NEXT:    ; implicit-def: $vgpr39
; GFX9-NEXT:    ; implicit-def: $vgpr38
; GFX9-NEXT:    ; implicit-def: $vgpr37
; GFX9-NEXT:    ; implicit-def: $vgpr36
; GFX9-NEXT:    ; implicit-def: $vgpr35
; GFX9-NEXT:    ; implicit-def: $vgpr14
; GFX9-NEXT:    ; implicit-def: $vgpr34
; GFX9-NEXT:    ; implicit-def: $vgpr33
; GFX9-NEXT:    ; implicit-def: $vgpr32
; GFX9-NEXT:    ; implicit-def: $vgpr31
; GFX9-NEXT:    ; implicit-def: $vgpr30
; GFX9-NEXT:    ; implicit-def: $vgpr13
; GFX9-NEXT:    ; implicit-def: $vgpr29
; GFX9-NEXT:    ; implicit-def: $vgpr28
; GFX9-NEXT:    ; implicit-def: $vgpr27
; GFX9-NEXT:    ; implicit-def: $vgpr26
; GFX9-NEXT:    ; implicit-def: $vgpr25
; GFX9-NEXT:    ; implicit-def: $vgpr12
; GFX9-NEXT:    ; implicit-def: $vgpr24
; GFX9-NEXT:    ; implicit-def: $vgpr23
; GFX9-NEXT:    ; implicit-def: $vgpr22
; GFX9-NEXT:    ; implicit-def: $vgpr21
; GFX9-NEXT:    ; implicit-def: $vgpr20
; GFX9-NEXT:    ; implicit-def: $vgpr19
; GFX9-NEXT:    ; implicit-def: $vgpr18
; GFX9-NEXT:    ; implicit-def: $vgpr17
; GFX9-NEXT:    ; implicit-def: $vgpr11
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB78_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX9-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX9-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX9-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX9-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX9-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
; GFX9-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
; GFX9-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
; GFX9-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
; GFX9-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; GFX9-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; GFX9-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
; GFX9-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
; GFX9-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
; GFX9-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX9-NEXT:  .LBB78_2: ; %Flow
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB78_4
; GFX9-NEXT:  ; %bb.3: ; %cmp.true
; GFX9-NEXT:    v_add_co_u32_e32 v1, vcc, 3, v1
; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v2, vcc
; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, 3, v3
; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, 3, v5
; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, 3, v7
; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v8, vcc
; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, 3, v9
; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, 0, v10, vcc
; GFX9-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX9-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX9-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX9-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX9-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX9-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; GFX9-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
; GFX9-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
; GFX9-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
; GFX9-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
; GFX9-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
; GFX9-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; GFX9-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; GFX9-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; GFX9-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
; GFX9-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
; GFX9-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
; GFX9-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
; GFX9-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX9-NEXT:  .LBB78_4: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_mov_b32 s4, 0xc0c0004
; GFX9-NEXT:    v_perm_b32 v15, v48, v15, s4
; GFX9-NEXT:    v_perm_b32 v1, v1, v16, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v15, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen
; GFX9-NEXT:    v_perm_b32 v1, v2, v39, s4
; GFX9-NEXT:    v_perm_b32 v2, v38, v37, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT:    v_perm_b32 v1, v3, v36, s4
; GFX9-NEXT:    v_perm_b32 v2, v35, v14, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT:    v_perm_b32 v1, v4, v34, s4
; GFX9-NEXT:    v_perm_b32 v2, v33, v32, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; GFX9-NEXT:    v_perm_b32 v1, v5, v31, s4
; GFX9-NEXT:    v_perm_b32 v2, v30, v13, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT:    v_perm_b32 v1, v6, v29, s4
; GFX9-NEXT:    v_perm_b32 v2, v28, v27, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; GFX9-NEXT:    v_perm_b32 v1, v7, v26, s4
; GFX9-NEXT:    v_perm_b32 v2, v25, v12, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT:    v_perm_b32 v1, v8, v24, s4
; GFX9-NEXT:    v_perm_b32 v2, v23, v22, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; GFX9-NEXT:    v_perm_b32 v1, v9, v21, s4
; GFX9-NEXT:    v_perm_b32 v2, v20, v11, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT:    v_perm_b32 v1, v10, v19, s4
; GFX9-NEXT:    v_perm_b32 v2, v18, v17, s4
; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v5i64_to_v40i8:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v11
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr11_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB78_2
; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v18, 8, v10
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v9
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v20, 24, v8
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v8
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v22, 8, v7
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v6
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v6
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v5
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v4
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v4
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v3
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v28, 24, v2
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v2
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX11-TRUE16-NEXT:  .LBB78_2: ; %Flow
; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB78_4
; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
; GFX11-TRUE16-NEXT:    v_add_co_u32 v3, vcc_lo, v3, 3
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v4, null, 0, v4, vcc_lo
; GFX11-TRUE16-NEXT:    v_add_co_u32 v5, vcc_lo, v5, 3
; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v6, null, 0, v6, vcc_lo
; GFX11-TRUE16-NEXT:    v_add_co_u32 v7, vcc_lo, v7, 3
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v8, null, 0, v8, vcc_lo
; GFX11-TRUE16-NEXT:    v_add_co_u32 v9, vcc_lo, v9, 3
; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v10, null, 0, v10, vcc_lo
; GFX11-TRUE16-NEXT:    v_add_co_u32 v1, vcc_lo, v1, 3
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v2, null, 0, v2, vcc_lo
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v18, 8, v10
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v9
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v20, 24, v8
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v8
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v22, 8, v7
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v6
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v6
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v5
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v4
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v4
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v3
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v28, 24, v2
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v2
; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX11-TRUE16-NEXT:  .LBB78_4: ; %end
; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v31.l, v1.h
; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT:    v_perm_b32 v1, v1, v16, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v16, v2, v30, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v29, v3, v29, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v3.h
; GFX11-TRUE16-NEXT:    v_perm_b32 v15, v31, v15, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v31.l, v5.h
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v30.l, v4.h
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
; GFX11-TRUE16-NEXT:    v_perm_b32 v5, v5, v25, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v1, v15, 16, v1
; GFX11-TRUE16-NEXT:    v_perm_b32 v13, v31, v13, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v3, v3, v14, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v4, v4, v27, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v14, v30, v26, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v15.l, v6.h
; GFX11-TRUE16-NEXT:    v_perm_b32 v2, v2, v28, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v5, v13, 16, v5
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v7.h
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v4, v14, 16, v4
; GFX11-TRUE16-NEXT:    v_perm_b32 v14, v15, v23, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v15.l, v8.h
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v2, v2, 16, v16
; GFX11-TRUE16-NEXT:    v_perm_b32 v12, v13, v12, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v9.h
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.l, v10.h
; GFX11-TRUE16-NEXT:    v_perm_b32 v6, v6, v24, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v7, v7, v22, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v8, v8, v21, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v15, v15, v20, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v9, v9, v19, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v11, v13, v11, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v10, v10, v18, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_perm_b32 v13, v16, v17, 0xc0c0004
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v3, v3, 16, v29
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v6, v14, 16, v6
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v7, v12, 16, v7
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v8, v15, 16, v8
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v9, v11, 16, v9
; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v10, v13, 16, v10
; GFX11-TRUE16-NEXT:    s_clause 0x2
; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[1:4], off
; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
; GFX11-TRUE16-NEXT:    scratch_store_b64 v0, v[9:10], off offset:32
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v5i64_to_v40i8:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v11
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB78_2
; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX11-FAKE16-NEXT:  .LBB78_2: ; %Flow
; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB78_4
; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
; GFX11-FAKE16-NEXT:    v_add_co_u32 v3, vcc_lo, v3, 3
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v4, null, 0, v4, vcc_lo
; GFX11-FAKE16-NEXT:    v_add_co_u32 v5, vcc_lo, v5, 3
; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v6, null, 0, v6, vcc_lo
; GFX11-FAKE16-NEXT:    v_add_co_u32 v7, vcc_lo, v7, 3
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v8, null, 0, v8, vcc_lo
; GFX11-FAKE16-NEXT:    v_add_co_u32 v9, vcc_lo, v9, 3
; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v10, null, 0, v10, vcc_lo
; GFX11-FAKE16-NEXT:    v_add_co_u32 v1, vcc_lo, v1, 3
; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v2, null, 0, v2, vcc_lo
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
; GFX11-FAKE16-NEXT:  .LBB78_4: ; %end
; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v3, v36, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v35, v14, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v5, v31, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v30, v13, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v1, v16, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v48, v15, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v2, v39, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v16, v38, v37, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v4, v34, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v32, v33, v32, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v3, v14, 16, v3
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v5, v13, 16, v5
; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v6, v29, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v28, v27, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v7, v26, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v25, v12, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v8, v24, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v23, v22, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v15, 16, v1
; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v9, v21, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v20, v11, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v10, v19, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v18, v17, 0xc0c0004
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, v16, 16, v2
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v4, v32, 16, v4
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v6, v13, 16, v6
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v7, v12, 16, v7
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v8, v14, 16, v8
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v9, v11, 16, v9
; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v10, v15, 16, v10
; GFX11-FAKE16-NEXT:    s_clause 0x2
; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[1:4], off
; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
; GFX11-FAKE16-NEXT:    scratch_store_b64 v0, v[9:10], off offset:32
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <5 x i64> %a, splat (i64 3)
  %a2 = bitcast <5 x i64> %a1 to <40 x i8>
  br label %end

cmp.false:
  %a3 = bitcast <5 x i64> %a to <40 x i8>
  br label %end

end:
  %phi = phi <40 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <40 x i8> %phi
}

define inreg <40 x i8> @bitcast_v5i64_to_v40i8_scalar(<5 x i64> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v5i64_to_v40i8_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc1 .LBB79_2
; SI-NEXT:  ; %bb.1: ; %cmp.true
; SI-NEXT:    s_add_u32 s24, s24, 3
; SI-NEXT:    s_addc_u32 s25, s25, 0
; SI-NEXT:    s_add_u32 s22, s22, 3
; SI-NEXT:    s_addc_u32 s23, s23, 0
; SI-NEXT:    s_add_u32 s20, s20, 3
; SI-NEXT:    s_addc_u32 s21, s21, 0
; SI-NEXT:    s_add_u32 s18, s18, 3
; SI-NEXT:    s_addc_u32 s19, s19, 0
; SI-NEXT:    s_add_u32 s16, s16, 3
; SI-NEXT:    s_addc_u32 s17, s17, 0
; SI-NEXT:  .LBB79_2: ; %cmp.false
; SI-NEXT:    s_lshr_b64 s[4:5], s[24:25], 24
; SI-NEXT:    s_lshr_b64 s[6:7], s[24:25], 16
; SI-NEXT:    s_lshr_b64 s[60:61], s[16:17], 8
; SI-NEXT:    s_lshr_b64 s[58:59], s[16:17], 16
; SI-NEXT:    s_lshl_b32 s5, s60, 8
; SI-NEXT:    s_and_b32 s7, s16, 0xff
; SI-NEXT:    s_lshr_b64 s[8:9], s[24:25], 8
; SI-NEXT:    s_lshr_b64 s[56:57], s[16:17], 24
; SI-NEXT:    s_or_b32 s5, s7, s5
; SI-NEXT:    s_and_b32 s7, s58, 0xff
; SI-NEXT:    s_lshl_b32 s9, s56, 24
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_or_b32 s7, s9, s7
; SI-NEXT:    s_and_b32 s5, s5, 0xffff
; SI-NEXT:    s_lshr_b32 s92, s17, 8
; SI-NEXT:    s_or_b32 s5, s5, s7
; SI-NEXT:    s_lshr_b32 s91, s17, 16
; SI-NEXT:    v_mov_b32_e32 v1, s5
; SI-NEXT:    s_and_b32 s5, s17, 0xff
; SI-NEXT:    s_lshl_b32 s7, s92, 8
; SI-NEXT:    s_lshr_b32 s90, s17, 24
; SI-NEXT:    s_or_b32 s5, s5, s7
; SI-NEXT:    s_and_b32 s7, s91, 0xff
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_lshl_b32 s9, s90, 24
; SI-NEXT:    s_or_b32 s7, s9, s7
; SI-NEXT:    s_and_b32 s5, s5, 0xffff
; SI-NEXT:    s_lshr_b64 s[46:47], s[18:19], 8
; SI-NEXT:    s_or_b32 s5, s5, s7
; SI-NEXT:    s_lshr_b64 s[44:45], s[18:19], 16
; SI-NEXT:    v_mov_b32_e32 v2, s5
; SI-NEXT:    s_lshl_b32 s5, s46, 8
; SI-NEXT:    s_and_b32 s7, s18, 0xff
; SI-NEXT:    s_lshr_b64 s[42:43], s[18:19], 24
; SI-NEXT:    s_or_b32 s5, s7, s5
; SI-NEXT:    s_and_b32 s7, s44, 0xff
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_lshl_b32 s9, s42, 24
; SI-NEXT:    s_and_b32 s5, s5, 0xffff
; SI-NEXT:    s_or_b32 s7, s9, s7
; SI-NEXT:    s_lshr_b32 s89, s19, 8
; SI-NEXT:    s_or_b32 s5, s5, s7
; SI-NEXT:    s_lshr_b32 s88, s19, 16
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen
; SI-NEXT:    buffer_store_dword v2, v0, s[0:3], 0 offen offset:4
; SI-NEXT:    s_waitcnt expcnt(1)
; SI-NEXT:    v_mov_b32_e32 v1, s5
; SI-NEXT:    s_and_b32 s5, s19, 0xff
; SI-NEXT:    s_lshl_b32 s7, s89, 8
; SI-NEXT:    s_lshr_b32 s79, s19, 24
; SI-NEXT:    s_or_b32 s5, s5, s7
; SI-NEXT:    s_and_b32 s7, s88, 0xff
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_lshl_b32 s9, s79, 24
; SI-NEXT:    s_and_b32 s5, s5, 0xffff
; SI-NEXT:    s_or_b32 s7, s9, s7
; SI-NEXT:    s_lshr_b64 s[40:41], s[20:21], 8
; SI-NEXT:    s_or_b32 s5, s5, s7
; SI-NEXT:    s_lshr_b64 s[28:29], s[20:21], 16
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_mov_b32_e32 v1, s5
; SI-NEXT:    s_and_b32 s5, s20, 0xff
; SI-NEXT:    s_lshl_b32 s7, s40, 8
; SI-NEXT:    s_lshr_b64 s[26:27], s[20:21], 24
; SI-NEXT:    s_or_b32 s5, s5, s7
; SI-NEXT:    s_and_b32 s7, s28, 0xff
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_lshl_b32 s9, s26, 24
; SI-NEXT:    s_and_b32 s5, s5, 0xffff
; SI-NEXT:    s_or_b32 s7, s9, s7
; SI-NEXT:    s_lshr_b32 s78, s21, 8
; SI-NEXT:    s_or_b32 s5, s5, s7
; SI-NEXT:    s_lshr_b32 s77, s21, 16
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_mov_b32_e32 v1, s5
; SI-NEXT:    s_and_b32 s5, s21, 0xff
; SI-NEXT:    s_lshl_b32 s7, s78, 8
; SI-NEXT:    s_lshr_b32 s76, s21, 24
; SI-NEXT:    s_or_b32 s5, s5, s7
; SI-NEXT:    s_and_b32 s7, s77, 0xff
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_lshl_b32 s9, s76, 24
; SI-NEXT:    s_and_b32 s5, s5, 0xffff
; SI-NEXT:    s_or_b32 s7, s9, s7
; SI-NEXT:    s_lshr_b64 s[14:15], s[22:23], 8
; SI-NEXT:    s_or_b32 s5, s5, s7
; SI-NEXT:    s_lshr_b64 s[12:13], s[22:23], 16
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_mov_b32_e32 v1, s5
; SI-NEXT:    s_and_b32 s5, s22, 0xff
; SI-NEXT:    s_lshl_b32 s7, s14, 8
; SI-NEXT:    s_lshr_b64 s[10:11], s[22:23], 24
; SI-NEXT:    s_or_b32 s5, s5, s7
; SI-NEXT:    s_and_b32 s7, s12, 0xff
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_lshl_b32 s9, s10, 24
; SI-NEXT:    s_and_b32 s5, s5, 0xffff
; SI-NEXT:    s_or_b32 s7, s9, s7
; SI-NEXT:    s_lshr_b32 s75, s23, 8
; SI-NEXT:    s_or_b32 s5, s5, s7
; SI-NEXT:    s_lshr_b32 s74, s23, 16
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_mov_b32_e32 v1, s5
; SI-NEXT:    s_and_b32 s5, s23, 0xff
; SI-NEXT:    s_lshl_b32 s7, s75, 8
; SI-NEXT:    s_lshr_b32 s73, s23, 24
; SI-NEXT:    s_or_b32 s5, s5, s7
; SI-NEXT:    s_and_b32 s7, s74, 0xff
; SI-NEXT:    s_lshl_b32 s7, s7, 16
; SI-NEXT:    s_lshl_b32 s9, s73, 24
; SI-NEXT:    s_and_b32 s5, s5, 0xffff
; SI-NEXT:    s_or_b32 s7, s9, s7
; SI-NEXT:    s_or_b32 s5, s5, s7
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_mov_b32_e32 v1, s5
; SI-NEXT:    s_and_b32 s5, s24, 0xff
; SI-NEXT:    s_lshl_b32 s7, s8, 8
; SI-NEXT:    s_and_b32 s6, s6, 0xff
; SI-NEXT:    s_or_b32 s5, s5, s7
; SI-NEXT:    s_lshl_b32 s6, s6, 16
; SI-NEXT:    s_lshl_b32 s4, s4, 24
; SI-NEXT:    s_and_b32 s5, s5, 0xffff
; SI-NEXT:    s_or_b32 s4, s4, s6
; SI-NEXT:    s_lshr_b32 s72, s25, 8
; SI-NEXT:    s_or_b32 s4, s5, s4
; SI-NEXT:    s_lshr_b32 s63, s25, 16
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_mov_b32_e32 v1, s4
; SI-NEXT:    s_and_b32 s4, s25, 0xff
; SI-NEXT:    s_lshl_b32 s5, s72, 8
; SI-NEXT:    s_lshr_b32 s62, s25, 24
; SI-NEXT:    s_or_b32 s4, s4, s5
; SI-NEXT:    s_and_b32 s5, s63, 0xff
; SI-NEXT:    s_lshl_b32 s5, s5, 16
; SI-NEXT:    s_lshl_b32 s6, s62, 24
; SI-NEXT:    s_and_b32 s4, s4, 0xffff
; SI-NEXT:    s_or_b32 s5, s6, s5
; SI-NEXT:    s_or_b32 s4, s4, s5
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; SI-NEXT:    s_waitcnt expcnt(0)
; SI-NEXT:    v_mov_b32_e32 v1, s4
; SI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v5i64_to_v40i8_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc0 .LBB79_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    s_lshr_b32 s14, s25, 24
; VI-NEXT:    s_lshr_b32 s15, s25, 16
; VI-NEXT:    s_lshr_b32 s26, s25, 8
; VI-NEXT:    s_lshr_b32 s27, s24, 16
; VI-NEXT:    s_lshr_b32 s28, s24, 8
; VI-NEXT:    s_lshr_b32 s29, s23, 24
; VI-NEXT:    s_lshr_b32 s40, s23, 16
; VI-NEXT:    s_lshr_b32 s41, s23, 8
; VI-NEXT:    s_lshr_b32 s42, s22, 16
; VI-NEXT:    s_lshr_b32 s43, s22, 8
; VI-NEXT:    s_lshr_b32 s44, s21, 24
; VI-NEXT:    s_lshr_b32 s45, s21, 16
; VI-NEXT:    s_lshr_b32 s46, s21, 8
; VI-NEXT:    s_lshr_b32 s47, s20, 16
; VI-NEXT:    s_lshr_b32 s56, s20, 8
; VI-NEXT:    s_lshr_b32 s57, s19, 24
; VI-NEXT:    s_lshr_b32 s58, s19, 16
; VI-NEXT:    s_lshr_b32 s59, s19, 8
; VI-NEXT:    s_lshr_b32 s60, s18, 16
; VI-NEXT:    s_lshr_b32 s61, s18, 8
; VI-NEXT:    s_lshr_b32 s62, s17, 24
; VI-NEXT:    s_lshr_b32 s63, s17, 16
; VI-NEXT:    s_lshr_b32 s72, s17, 8
; VI-NEXT:    s_lshr_b32 s73, s16, 16
; VI-NEXT:    s_lshr_b32 s74, s16, 8
; VI-NEXT:    s_lshr_b64 s[4:5], s[24:25], 24
; VI-NEXT:    s_lshr_b64 s[6:7], s[22:23], 24
; VI-NEXT:    s_lshr_b64 s[8:9], s[20:21], 24
; VI-NEXT:    s_lshr_b64 s[10:11], s[18:19], 24
; VI-NEXT:    s_lshr_b64 s[12:13], s[16:17], 24
; VI-NEXT:    s_branch .LBB79_3
; VI-NEXT:  .LBB79_2: ; %cmp.true
; VI-NEXT:    s_add_u32 s16, s16, 3
; VI-NEXT:    s_addc_u32 s17, s17, 0
; VI-NEXT:    s_add_u32 s18, s18, 3
; VI-NEXT:    s_addc_u32 s19, s19, 0
; VI-NEXT:    s_add_u32 s20, s20, 3
; VI-NEXT:    s_addc_u32 s21, s21, 0
; VI-NEXT:    s_add_u32 s22, s22, 3
; VI-NEXT:    s_addc_u32 s23, s23, 0
; VI-NEXT:    s_add_u32 s24, s24, 3
; VI-NEXT:    s_addc_u32 s25, s25, 0
; VI-NEXT:    s_lshr_b64 s[4:5], s[24:25], 24
; VI-NEXT:    s_lshr_b64 s[6:7], s[22:23], 24
; VI-NEXT:    s_lshr_b64 s[8:9], s[20:21], 24
; VI-NEXT:    s_lshr_b64 s[10:11], s[18:19], 24
; VI-NEXT:    s_lshr_b64 s[12:13], s[16:17], 24
; VI-NEXT:    s_lshr_b32 s14, s25, 24
; VI-NEXT:    s_lshr_b32 s15, s25, 16
; VI-NEXT:    s_lshr_b32 s26, s25, 8
; VI-NEXT:    s_lshr_b32 s27, s24, 16
; VI-NEXT:    s_lshr_b32 s28, s24, 8
; VI-NEXT:    s_lshr_b32 s29, s23, 24
; VI-NEXT:    s_lshr_b32 s40, s23, 16
; VI-NEXT:    s_lshr_b32 s41, s23, 8
; VI-NEXT:    s_lshr_b32 s42, s22, 16
; VI-NEXT:    s_lshr_b32 s43, s22, 8
; VI-NEXT:    s_lshr_b32 s44, s21, 24
; VI-NEXT:    s_lshr_b32 s45, s21, 16
; VI-NEXT:    s_lshr_b32 s46, s21, 8
; VI-NEXT:    s_lshr_b32 s47, s20, 16
; VI-NEXT:    s_lshr_b32 s56, s20, 8
; VI-NEXT:    s_lshr_b32 s57, s19, 24
; VI-NEXT:    s_lshr_b32 s58, s19, 16
; VI-NEXT:    s_lshr_b32 s59, s19, 8
; VI-NEXT:    s_lshr_b32 s60, s18, 16
; VI-NEXT:    s_lshr_b32 s61, s18, 8
; VI-NEXT:    s_lshr_b32 s62, s17, 24
; VI-NEXT:    s_lshr_b32 s63, s17, 16
; VI-NEXT:    s_lshr_b32 s72, s17, 8
; VI-NEXT:    s_lshr_b32 s73, s16, 16
; VI-NEXT:    s_lshr_b32 s74, s16, 8
; VI-NEXT:  .LBB79_3: ; %end
; VI-NEXT:    v_mov_b32_e32 v2, 0xc0c0004
; VI-NEXT:    v_mov_b32_e32 v3, s12
; VI-NEXT:    v_mov_b32_e32 v1, s74
; VI-NEXT:    v_perm_b32 v3, s73, v3, v2
; VI-NEXT:    v_perm_b32 v1, s16, v1, v2
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_e32 v1, v1, v3
; VI-NEXT:    v_mov_b32_e32 v3, s62
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT:    v_mov_b32_e32 v1, s72
; VI-NEXT:    v_perm_b32 v3, s63, v3, v2
; VI-NEXT:    v_perm_b32 v1, s17, v1, v2
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_e32 v1, v1, v3
; VI-NEXT:    v_mov_b32_e32 v3, s10
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
; VI-NEXT:    v_mov_b32_e32 v1, s61
; VI-NEXT:    v_perm_b32 v3, s60, v3, v2
; VI-NEXT:    v_perm_b32 v1, s18, v1, v2
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_e32 v1, v1, v3
; VI-NEXT:    v_mov_b32_e32 v3, s57
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; VI-NEXT:    v_mov_b32_e32 v1, s59
; VI-NEXT:    v_perm_b32 v3, s58, v3, v2
; VI-NEXT:    v_perm_b32 v1, s19, v1, v2
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_e32 v1, v1, v3
; VI-NEXT:    v_mov_b32_e32 v3, s8
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; VI-NEXT:    v_mov_b32_e32 v1, s56
; VI-NEXT:    v_perm_b32 v3, s47, v3, v2
; VI-NEXT:    v_perm_b32 v1, s20, v1, v2
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_e32 v1, v1, v3
; VI-NEXT:    v_mov_b32_e32 v3, s44
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; VI-NEXT:    v_mov_b32_e32 v1, s46
; VI-NEXT:    v_perm_b32 v3, s45, v3, v2
; VI-NEXT:    v_perm_b32 v1, s21, v1, v2
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_e32 v1, v1, v3
; VI-NEXT:    v_mov_b32_e32 v3, s6
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; VI-NEXT:    v_mov_b32_e32 v1, s43
; VI-NEXT:    v_perm_b32 v3, s42, v3, v2
; VI-NEXT:    v_perm_b32 v1, s22, v1, v2
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_e32 v1, v1, v3
; VI-NEXT:    v_mov_b32_e32 v3, s29
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; VI-NEXT:    v_mov_b32_e32 v1, s41
; VI-NEXT:    v_perm_b32 v3, s40, v3, v2
; VI-NEXT:    v_perm_b32 v1, s23, v1, v2
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_e32 v1, v1, v3
; VI-NEXT:    v_mov_b32_e32 v3, s4
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; VI-NEXT:    v_mov_b32_e32 v1, s28
; VI-NEXT:    v_perm_b32 v3, s27, v3, v2
; VI-NEXT:    v_perm_b32 v1, s24, v1, v2
; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT:    v_or_b32_e32 v1, v1, v3
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; VI-NEXT:    v_mov_b32_e32 v1, s26
; VI-NEXT:    v_mov_b32_e32 v3, s14
; VI-NEXT:    v_perm_b32 v1, s25, v1, v2
; VI-NEXT:    v_perm_b32 v2, s15, v3, v2
; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v2
; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v5i64_to_v40i8_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc0 .LBB79_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    s_lshr_b32 s14, s25, 24
; GFX9-NEXT:    s_lshr_b32 s15, s25, 16
; GFX9-NEXT:    s_lshr_b32 s26, s25, 8
; GFX9-NEXT:    s_lshr_b32 s27, s24, 16
; GFX9-NEXT:    s_lshr_b32 s28, s24, 8
; GFX9-NEXT:    s_lshr_b32 s29, s23, 24
; GFX9-NEXT:    s_lshr_b32 s40, s23, 16
; GFX9-NEXT:    s_lshr_b32 s41, s23, 8
; GFX9-NEXT:    s_lshr_b32 s42, s22, 16
; GFX9-NEXT:    s_lshr_b32 s43, s22, 8
; GFX9-NEXT:    s_lshr_b32 s44, s21, 24
; GFX9-NEXT:    s_lshr_b32 s45, s21, 16
; GFX9-NEXT:    s_lshr_b32 s46, s21, 8
; GFX9-NEXT:    s_lshr_b32 s47, s20, 16
; GFX9-NEXT:    s_lshr_b32 s56, s20, 8
; GFX9-NEXT:    s_lshr_b32 s57, s19, 24
; GFX9-NEXT:    s_lshr_b32 s58, s19, 16
; GFX9-NEXT:    s_lshr_b32 s59, s19, 8
; GFX9-NEXT:    s_lshr_b32 s60, s18, 16
; GFX9-NEXT:    s_lshr_b32 s61, s18, 8
; GFX9-NEXT:    s_lshr_b32 s62, s17, 24
; GFX9-NEXT:    s_lshr_b32 s63, s17, 16
; GFX9-NEXT:    s_lshr_b32 s72, s17, 8
; GFX9-NEXT:    s_lshr_b32 s73, s16, 16
; GFX9-NEXT:    s_lshr_b32 s74, s16, 8
; GFX9-NEXT:    s_lshr_b64 s[4:5], s[24:25], 24
; GFX9-NEXT:    s_lshr_b64 s[6:7], s[22:23], 24
; GFX9-NEXT:    s_lshr_b64 s[8:9], s[20:21], 24
; GFX9-NEXT:    s_lshr_b64 s[10:11], s[18:19], 24
; GFX9-NEXT:    s_lshr_b64 s[12:13], s[16:17], 24
; GFX9-NEXT:    s_branch .LBB79_3
; GFX9-NEXT:  .LBB79_2: ; %cmp.true
; GFX9-NEXT:    s_add_u32 s16, s16, 3
; GFX9-NEXT:    s_addc_u32 s17, s17, 0
; GFX9-NEXT:    s_add_u32 s18, s18, 3
; GFX9-NEXT:    s_addc_u32 s19, s19, 0
; GFX9-NEXT:    s_add_u32 s20, s20, 3
; GFX9-NEXT:    s_addc_u32 s21, s21, 0
; GFX9-NEXT:    s_add_u32 s22, s22, 3
; GFX9-NEXT:    s_addc_u32 s23, s23, 0
; GFX9-NEXT:    s_add_u32 s24, s24, 3
; GFX9-NEXT:    s_addc_u32 s25, s25, 0
; GFX9-NEXT:    s_lshr_b64 s[4:5], s[24:25], 24
; GFX9-NEXT:    s_lshr_b64 s[6:7], s[22:23], 24
; GFX9-NEXT:    s_lshr_b64 s[8:9], s[20:21], 24
; GFX9-NEXT:    s_lshr_b64 s[10:11], s[18:19], 24
; GFX9-NEXT:    s_lshr_b64 s[12:13], s[16:17], 24
; GFX9-NEXT:    s_lshr_b32 s14, s25, 24
; GFX9-NEXT:    s_lshr_b32 s15, s25, 16
; GFX9-NEXT:    s_lshr_b32 s26, s25, 8
; GFX9-NEXT:    s_lshr_b32 s27, s24, 16
; GFX9-NEXT:    s_lshr_b32 s28, s24, 8
; GFX9-NEXT:    s_lshr_b32 s29, s23, 24
; GFX9-NEXT:    s_lshr_b32 s40, s23, 16
; GFX9-NEXT:    s_lshr_b32 s41, s23, 8
; GFX9-NEXT:    s_lshr_b32 s42, s22, 16
; GFX9-NEXT:    s_lshr_b32 s43, s22, 8
; GFX9-NEXT:    s_lshr_b32 s44, s21, 24
; GFX9-NEXT:    s_lshr_b32 s45, s21, 16
; GFX9-NEXT:    s_lshr_b32 s46, s21, 8
; GFX9-NEXT:    s_lshr_b32 s47, s20, 16
; GFX9-NEXT:    s_lshr_b32 s56, s20, 8
; GFX9-NEXT:    s_lshr_b32 s57, s19, 24
; GFX9-NEXT:    s_lshr_b32 s58, s19, 16
; GFX9-NEXT:    s_lshr_b32 s59, s19, 8
; GFX9-NEXT:    s_lshr_b32 s60, s18, 16
; GFX9-NEXT:    s_lshr_b32 s61, s18, 8
; GFX9-NEXT:    s_lshr_b32 s62, s17, 24
; GFX9-NEXT:    s_lshr_b32 s63, s17, 16
; GFX9-NEXT:    s_lshr_b32 s72, s17, 8
; GFX9-NEXT:    s_lshr_b32 s73, s16, 16
; GFX9-NEXT:    s_lshr_b32 s74, s16, 8
; GFX9-NEXT:  .LBB79_3: ; %end
; GFX9-NEXT:    v_mov_b32_e32 v2, 0xc0c0004
; GFX9-NEXT:    v_mov_b32_e32 v3, s12
; GFX9-NEXT:    v_mov_b32_e32 v1, s74
; GFX9-NEXT:    v_perm_b32 v3, s73, v3, v2
; GFX9-NEXT:    v_perm_b32 v1, s16, v1, v2
; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
; GFX9-NEXT:    v_mov_b32_e32 v3, s62
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen
; GFX9-NEXT:    v_mov_b32_e32 v1, s72
; GFX9-NEXT:    v_perm_b32 v3, s63, v3, v2
; GFX9-NEXT:    v_perm_b32 v1, s17, v1, v2
; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
; GFX9-NEXT:    v_mov_b32_e32 v3, s10
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT:    v_mov_b32_e32 v1, s61
; GFX9-NEXT:    v_perm_b32 v3, s60, v3, v2
; GFX9-NEXT:    v_perm_b32 v1, s18, v1, v2
; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
; GFX9-NEXT:    v_mov_b32_e32 v3, s57
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT:    v_mov_b32_e32 v1, s59
; GFX9-NEXT:    v_perm_b32 v3, s58, v3, v2
; GFX9-NEXT:    v_perm_b32 v1, s19, v1, v2
; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
; GFX9-NEXT:    v_mov_b32_e32 v3, s8
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; GFX9-NEXT:    v_mov_b32_e32 v1, s56
; GFX9-NEXT:    v_perm_b32 v3, s47, v3, v2
; GFX9-NEXT:    v_perm_b32 v1, s20, v1, v2
; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
; GFX9-NEXT:    v_mov_b32_e32 v3, s44
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT:    v_mov_b32_e32 v1, s46
; GFX9-NEXT:    v_perm_b32 v3, s45, v3, v2
; GFX9-NEXT:    v_perm_b32 v1, s21, v1, v2
; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
; GFX9-NEXT:    v_mov_b32_e32 v3, s6
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; GFX9-NEXT:    v_mov_b32_e32 v1, s43
; GFX9-NEXT:    v_perm_b32 v3, s42, v3, v2
; GFX9-NEXT:    v_perm_b32 v1, s22, v1, v2
; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
; GFX9-NEXT:    v_mov_b32_e32 v3, s29
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT:    v_mov_b32_e32 v1, s41
; GFX9-NEXT:    v_perm_b32 v3, s40, v3, v2
; GFX9-NEXT:    v_perm_b32 v1, s23, v1, v2
; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
; GFX9-NEXT:    v_mov_b32_e32 v3, s4
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; GFX9-NEXT:    v_mov_b32_e32 v1, s28
; GFX9-NEXT:    v_perm_b32 v3, s27, v3, v2
; GFX9-NEXT:    v_perm_b32 v1, s24, v1, v2
; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT:    v_mov_b32_e32 v1, s26
; GFX9-NEXT:    v_mov_b32_e32 v3, s14
; GFX9-NEXT:    v_perm_b32 v1, s25, v1, v2
; GFX9-NEXT:    v_perm_b32 v2, s15, v3, v2
; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v2
; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v5i64_to_v40i8_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc0 .LBB79_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-NEXT:    s_lshr_b32 s14, s21, 24
; GFX11-NEXT:    s_lshr_b32 s22, s21, 16
; GFX11-NEXT:    s_lshr_b32 s15, s21, 8
; GFX11-NEXT:    s_lshr_b32 s24, s20, 16
; GFX11-NEXT:    s_lshr_b32 s23, s20, 8
; GFX11-NEXT:    s_lshr_b32 s26, s19, 24
; GFX11-NEXT:    s_lshr_b32 s27, s19, 16
; GFX11-NEXT:    s_lshr_b32 s25, s19, 8
; GFX11-NEXT:    s_lshr_b32 s28, s18, 16
; GFX11-NEXT:    s_lshr_b32 s29, s18, 8
; GFX11-NEXT:    s_lshr_b32 s40, s17, 24
; GFX11-NEXT:    s_lshr_b32 s42, s17, 16
; GFX11-NEXT:    s_lshr_b32 s41, s17, 8
; GFX11-NEXT:    s_lshr_b32 s43, s16, 16
; GFX11-NEXT:    s_lshr_b32 s44, s16, 8
; GFX11-NEXT:    s_lshr_b32 s45, s3, 24
; GFX11-NEXT:    s_lshr_b32 s46, s3, 16
; GFX11-NEXT:    s_lshr_b32 s47, s3, 8
; GFX11-NEXT:    s_lshr_b32 s56, s2, 16
; GFX11-NEXT:    s_lshr_b32 s57, s2, 8
; GFX11-NEXT:    s_lshr_b32 s58, s1, 24
; GFX11-NEXT:    s_lshr_b32 s59, s1, 16
; GFX11-NEXT:    s_lshr_b32 s60, s1, 8
; GFX11-NEXT:    s_lshr_b32 s61, s0, 16
; GFX11-NEXT:    s_lshr_b32 s62, s0, 8
; GFX11-NEXT:    s_lshr_b64 s[4:5], s[20:21], 24
; GFX11-NEXT:    s_lshr_b64 s[6:7], s[18:19], 24
; GFX11-NEXT:    s_lshr_b64 s[8:9], s[16:17], 24
; GFX11-NEXT:    s_lshr_b64 s[10:11], s[2:3], 24
; GFX11-NEXT:    s_lshr_b64 s[12:13], s[0:1], 24
; GFX11-NEXT:    s_branch .LBB79_3
; GFX11-NEXT:  .LBB79_2: ; %cmp.true
; GFX11-NEXT:    s_add_u32 s0, s0, 3
; GFX11-NEXT:    s_addc_u32 s1, s1, 0
; GFX11-NEXT:    s_add_u32 s2, s2, 3
; GFX11-NEXT:    s_addc_u32 s3, s3, 0
; GFX11-NEXT:    s_add_u32 s16, s16, 3
; GFX11-NEXT:    s_addc_u32 s17, s17, 0
; GFX11-NEXT:    s_add_u32 s18, s18, 3
; GFX11-NEXT:    s_addc_u32 s19, s19, 0
; GFX11-NEXT:    s_add_u32 s20, s20, 3
; GFX11-NEXT:    s_addc_u32 s21, s21, 0
; GFX11-NEXT:    s_lshr_b64 s[6:7], s[18:19], 24
; GFX11-NEXT:    s_lshr_b64 s[4:5], s[20:21], 24
; GFX11-NEXT:    s_lshr_b64 s[8:9], s[16:17], 24
; GFX11-NEXT:    s_lshr_b64 s[10:11], s[2:3], 24
; GFX11-NEXT:    s_lshr_b64 s[12:13], s[0:1], 24
; GFX11-NEXT:    s_lshr_b32 s14, s21, 24
; GFX11-NEXT:    s_lshr_b32 s22, s21, 16
; GFX11-NEXT:    s_lshr_b32 s15, s21, 8
; GFX11-NEXT:    s_lshr_b32 s24, s20, 16
; GFX11-NEXT:    s_lshr_b32 s23, s20, 8
; GFX11-NEXT:    s_lshr_b32 s26, s19, 24
; GFX11-NEXT:    s_lshr_b32 s27, s19, 16
; GFX11-NEXT:    s_lshr_b32 s25, s19, 8
; GFX11-NEXT:    s_lshr_b32 s28, s18, 16
; GFX11-NEXT:    s_lshr_b32 s29, s18, 8
; GFX11-NEXT:    s_lshr_b32 s40, s17, 24
; GFX11-NEXT:    s_lshr_b32 s42, s17, 16
; GFX11-NEXT:    s_lshr_b32 s41, s17, 8
; GFX11-NEXT:    s_lshr_b32 s43, s16, 16
; GFX11-NEXT:    s_lshr_b32 s44, s16, 8
; GFX11-NEXT:    s_lshr_b32 s45, s3, 24
; GFX11-NEXT:    s_lshr_b32 s46, s3, 16
; GFX11-NEXT:    s_lshr_b32 s47, s3, 8
; GFX11-NEXT:    s_lshr_b32 s56, s2, 16
; GFX11-NEXT:    s_lshr_b32 s57, s2, 8
; GFX11-NEXT:    s_lshr_b32 s58, s1, 24
; GFX11-NEXT:    s_lshr_b32 s59, s1, 16
; GFX11-NEXT:    s_lshr_b32 s60, s1, 8
; GFX11-NEXT:    s_lshr_b32 s61, s0, 16
; GFX11-NEXT:    s_lshr_b32 s62, s0, 8
; GFX11-NEXT:  .LBB79_3: ; %end
; GFX11-NEXT:    v_mov_b32_e32 v6, 0xc0c0004
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_perm_b32 v7, s56, s10, v6
; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; GFX11-NEXT:    v_perm_b32 v2, s61, s12, v6
; GFX11-NEXT:    v_perm_b32 v4, s59, s58, v6
; GFX11-NEXT:    v_perm_b32 v9, s46, s45, v6
; GFX11-NEXT:    v_perm_b32 v11, s43, s8, v6
; GFX11-NEXT:    v_perm_b32 v1, s0, s62, v6
; GFX11-NEXT:    v_perm_b32 v3, s1, s60, v6
; GFX11-NEXT:    v_perm_b32 v5, s2, s57, v6
; GFX11-NEXT:    v_perm_b32 v8, s3, s47, v6
; GFX11-NEXT:    v_perm_b32 v10, s16, s44, v6
; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; GFX11-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; GFX11-NEXT:    v_perm_b32 v12, s24, s4, v6
; GFX11-NEXT:    v_or_b32_e32 v1, v1, v2
; GFX11-NEXT:    v_or_b32_e32 v2, v3, v4
; GFX11-NEXT:    v_or_b32_e32 v3, v5, v7
; GFX11-NEXT:    v_perm_b32 v7, s42, s40, v6
; GFX11-NEXT:    v_or_b32_e32 v4, v8, v9
; GFX11-NEXT:    v_or_b32_e32 v5, v10, v11
; GFX11-NEXT:    v_perm_b32 v8, s28, s6, v6
; GFX11-NEXT:    v_perm_b32 v11, s27, s26, v6
; GFX11-NEXT:    v_perm_b32 v14, s22, s14, v6
; GFX11-NEXT:    v_perm_b32 v9, s17, s41, v6
; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; GFX11-NEXT:    v_perm_b32 v10, s18, s29, v6
; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
; GFX11-NEXT:    v_perm_b32 v13, s19, s25, v6
; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
; GFX11-NEXT:    v_perm_b32 v15, s20, s23, v6
; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
; GFX11-NEXT:    v_perm_b32 v16, s21, s15, v6
; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
; GFX11-NEXT:    v_or_b32_e32 v6, v9, v7
; GFX11-NEXT:    v_or_b32_e32 v7, v10, v8
; GFX11-NEXT:    v_or_b32_e32 v8, v13, v11
; GFX11-NEXT:    v_or_b32_e32 v9, v15, v12
; GFX11-NEXT:    v_or_b32_e32 v10, v16, v14
; GFX11-NEXT:    s_clause 0x2
; GFX11-NEXT:    scratch_store_b128 v0, v[1:4], off
; GFX11-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
; GFX11-NEXT:    scratch_store_b64 v0, v[9:10], off offset:32
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <5 x i64> %a, splat (i64 3)
  %a2 = bitcast <5 x i64> %a1 to <40 x i8>
  br label %end

cmp.false:
  %a3 = bitcast <5 x i64> %a to <40 x i8>
  br label %end

end:
  %phi = phi <40 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <40 x i8> %phi
}

define <5 x i64> @bitcast_v5f64_to_v5i64(<5 x double> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v5f64_to_v5i64:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB80_2
; SI-NEXT:  ; %bb.1: ; %cmp.true
; SI-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
; SI-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
; SI-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
; SI-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
; SI-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
; SI-NEXT:  .LBB80_2: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v5f64_to_v5i64:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB80_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
; VI-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
; VI-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
; VI-NEXT:  .LBB80_2: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v5f64_to_v5i64:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB80_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
; GFX9-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
; GFX9-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
; GFX9-NEXT:  .LBB80_2: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v5f64_to_v5i64:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB80_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
; GFX11-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
; GFX11-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
; GFX11-NEXT:  .LBB80_2: ; %end
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <5 x double> %a, splat (double 1.000000e+00)
  %a2 = bitcast <5 x double> %a1 to <5 x i64>
  br label %end

cmp.false:
  %a3 = bitcast <5 x double> %a to <5 x i64>
  br label %end

end:
  %phi = phi <5 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <5 x i64> %phi
}

define inreg <5 x i64> @bitcast_v5f64_to_v5i64_scalar(<5 x double> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v5f64_to_v5i64_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc0 .LBB81_2
; SI-NEXT:  ; %bb.1: ; %cmp.false
; SI-NEXT:    v_mov_b32_e32 v0, s16
; SI-NEXT:    v_mov_b32_e32 v1, s17
; SI-NEXT:    v_mov_b32_e32 v2, s18
; SI-NEXT:    v_mov_b32_e32 v3, s19
; SI-NEXT:    v_mov_b32_e32 v4, s20
; SI-NEXT:    v_mov_b32_e32 v5, s21
; SI-NEXT:    v_mov_b32_e32 v6, s22
; SI-NEXT:    v_mov_b32_e32 v7, s23
; SI-NEXT:    v_mov_b32_e32 v8, s24
; SI-NEXT:    v_mov_b32_e32 v9, s25
; SI-NEXT:    v_mov_b32_e32 v10, s26
; SI-NEXT:    v_mov_b32_e32 v11, s27
; SI-NEXT:    v_mov_b32_e32 v12, s28
; SI-NEXT:    v_mov_b32_e32 v13, s29
; SI-NEXT:    v_mov_b32_e32 v14, s30
; SI-NEXT:    v_mov_b32_e32 v15, s31
; SI-NEXT:    s_setpc_b64 s[30:31]
; SI-NEXT:  .LBB81_2: ; %cmp.true
; SI-NEXT:    v_add_f64 v[0:1], s[16:17], 1.0
; SI-NEXT:    v_add_f64 v[2:3], s[18:19], 1.0
; SI-NEXT:    v_add_f64 v[4:5], s[20:21], 1.0
; SI-NEXT:    v_add_f64 v[6:7], s[22:23], 1.0
; SI-NEXT:    v_add_f64 v[8:9], s[24:25], 1.0
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v5f64_to_v5i64_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc0 .LBB81_2
; VI-NEXT:  ; %bb.1: ; %cmp.false
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s17
; VI-NEXT:    v_mov_b32_e32 v2, s18
; VI-NEXT:    v_mov_b32_e32 v3, s19
; VI-NEXT:    v_mov_b32_e32 v4, s20
; VI-NEXT:    v_mov_b32_e32 v5, s21
; VI-NEXT:    v_mov_b32_e32 v6, s22
; VI-NEXT:    v_mov_b32_e32 v7, s23
; VI-NEXT:    v_mov_b32_e32 v8, s24
; VI-NEXT:    v_mov_b32_e32 v9, s25
; VI-NEXT:    v_mov_b32_e32 v10, s26
; VI-NEXT:    v_mov_b32_e32 v11, s27
; VI-NEXT:    v_mov_b32_e32 v12, s28
; VI-NEXT:    v_mov_b32_e32 v13, s29
; VI-NEXT:    v_mov_b32_e32 v14, s30
; VI-NEXT:    v_mov_b32_e32 v15, s31
; VI-NEXT:    s_setpc_b64 s[30:31]
; VI-NEXT:  .LBB81_2: ; %cmp.true
; VI-NEXT:    v_add_f64 v[0:1], s[16:17], 1.0
; VI-NEXT:    v_add_f64 v[2:3], s[18:19], 1.0
; VI-NEXT:    v_add_f64 v[4:5], s[20:21], 1.0
; VI-NEXT:    v_add_f64 v[6:7], s[22:23], 1.0
; VI-NEXT:    v_add_f64 v[8:9], s[24:25], 1.0
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v5f64_to_v5i64_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc0 .LBB81_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.false
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s17
; GFX9-NEXT:    v_mov_b32_e32 v2, s18
; GFX9-NEXT:    v_mov_b32_e32 v3, s19
; GFX9-NEXT:    v_mov_b32_e32 v4, s20
; GFX9-NEXT:    v_mov_b32_e32 v5, s21
; GFX9-NEXT:    v_mov_b32_e32 v6, s22
; GFX9-NEXT:    v_mov_b32_e32 v7, s23
; GFX9-NEXT:    v_mov_b32_e32 v8, s24
; GFX9-NEXT:    v_mov_b32_e32 v9, s25
; GFX9-NEXT:    v_mov_b32_e32 v10, s26
; GFX9-NEXT:    v_mov_b32_e32 v11, s27
; GFX9-NEXT:    v_mov_b32_e32 v12, s28
; GFX9-NEXT:    v_mov_b32_e32 v13, s29
; GFX9-NEXT:    v_mov_b32_e32 v14, s30
; GFX9-NEXT:    v_mov_b32_e32 v15, s31
; GFX9-NEXT:    s_setpc_b64 s[30:31]
; GFX9-NEXT:  .LBB81_2: ; %cmp.true
; GFX9-NEXT:    v_add_f64 v[0:1], s[16:17], 1.0
; GFX9-NEXT:    v_add_f64 v[2:3], s[18:19], 1.0
; GFX9-NEXT:    v_add_f64 v[4:5], s[20:21], 1.0
; GFX9-NEXT:    v_add_f64 v[6:7], s[22:23], 1.0
; GFX9-NEXT:    v_add_f64 v[8:9], s[24:25], 1.0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v5f64_to_v5i64_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s15, s3
; GFX11-NEXT:    s_mov_b32 s14, s2
; GFX11-NEXT:    s_mov_b32 s13, s1
; GFX11-NEXT:    s_mov_b32 s12, s0
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc0 .LBB81_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.false
; GFX11-NEXT:    v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
; GFX11-NEXT:    v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT:    v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
; GFX11-NEXT:    v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
; GFX11-NEXT:    v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
; GFX11-NEXT:    s_setpc_b64 s[30:31]
; GFX11-NEXT:  .LBB81_2: ; %cmp.true
; GFX11-NEXT:    v_add_f64 v[0:1], s[12:13], 1.0
; GFX11-NEXT:    v_add_f64 v[2:3], s[14:15], 1.0
; GFX11-NEXT:    v_add_f64 v[4:5], s[16:17], 1.0
; GFX11-NEXT:    v_add_f64 v[6:7], s[18:19], 1.0
; GFX11-NEXT:    v_add_f64 v[8:9], s[20:21], 1.0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = fadd <5 x double> %a, splat (double 1.000000e+00)
  %a2 = bitcast <5 x double> %a1 to <5 x i64>
  br label %end

cmp.false:
  %a3 = bitcast <5 x double> %a to <5 x i64>
  br label %end

end:
  %phi = phi <5 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <5 x i64> %phi
}

define <5 x double> @bitcast_v5i64_to_v5f64(<5 x i64> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v5i64_to_v5f64:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT:    s_cbranch_execz .LBB82_2
; SI-NEXT:  ; %bb.1: ; %cmp.true
; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
; SI-NEXT:    v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
; SI-NEXT:    v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
; SI-NEXT:  .LBB82_2: ; %end
; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v5i64_to_v5f64:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB82_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT:    v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT:    v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT:    v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
; VI-NEXT:    v_add_u32_e32 v8, vcc, 3, v8
; VI-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
; VI-NEXT:  .LBB82_2: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v5i64_to_v5f64:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB82_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, 3, v2
; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, 3, v4
; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, 3, v6
; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, 3, v8
; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v9, vcc
; GFX9-NEXT:  .LBB82_2: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v5i64_to_v5f64:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB82_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX11-NEXT:    v_add_co_u32 v2, vcc_lo, v2, 3
; GFX11-NEXT:    v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-NEXT:    v_add_co_u32 v4, vcc_lo, v4, 3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
; GFX11-NEXT:    v_add_co_u32 v6, vcc_lo, v6, 3
; GFX11-NEXT:    v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo
; GFX11-NEXT:    v_add_co_u32 v8, vcc_lo, v8, 3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo
; GFX11-NEXT:  .LBB82_2: ; %end
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <5 x i64> %a, splat (i64 3)
  %a2 = bitcast <5 x i64> %a1 to <5 x double>
  br label %end

cmp.false:
  %a3 = bitcast <5 x i64> %a to <5 x double>
  br label %end

end:
  %phi = phi <5 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <5 x double> %phi
}

define inreg <5 x double> @bitcast_v5i64_to_v5f64_scalar(<5 x i64> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v5i64_to_v5f64_scalar:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_cmp_lg_u32 s26, 0
; SI-NEXT:    s_cbranch_scc1 .LBB83_2
; SI-NEXT:  ; %bb.1: ; %cmp.true
; SI-NEXT:    s_add_u32 s16, s16, 3
; SI-NEXT:    s_addc_u32 s17, s17, 0
; SI-NEXT:    s_add_u32 s18, s18, 3
; SI-NEXT:    s_addc_u32 s19, s19, 0
; SI-NEXT:    s_add_u32 s20, s20, 3
; SI-NEXT:    s_addc_u32 s21, s21, 0
; SI-NEXT:    s_add_u32 s22, s22, 3
; SI-NEXT:    s_addc_u32 s23, s23, 0
; SI-NEXT:    s_add_u32 s24, s24, 3
; SI-NEXT:    s_addc_u32 s25, s25, 0
; SI-NEXT:  .LBB83_2: ; %end
; SI-NEXT:    v_mov_b32_e32 v0, s16
; SI-NEXT:    v_mov_b32_e32 v1, s17
; SI-NEXT:    v_mov_b32_e32 v2, s18
; SI-NEXT:    v_mov_b32_e32 v3, s19
; SI-NEXT:    v_mov_b32_e32 v4, s20
; SI-NEXT:    v_mov_b32_e32 v5, s21
; SI-NEXT:    v_mov_b32_e32 v6, s22
; SI-NEXT:    v_mov_b32_e32 v7, s23
; SI-NEXT:    v_mov_b32_e32 v8, s24
; SI-NEXT:    v_mov_b32_e32 v9, s25
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v5i64_to_v5f64_scalar:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_cmp_lg_u32 s26, 0
; VI-NEXT:    s_cbranch_scc1 .LBB83_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    s_add_u32 s16, s16, 3
; VI-NEXT:    s_addc_u32 s17, s17, 0
; VI-NEXT:    s_add_u32 s18, s18, 3
; VI-NEXT:    s_addc_u32 s19, s19, 0
; VI-NEXT:    s_add_u32 s20, s20, 3
; VI-NEXT:    s_addc_u32 s21, s21, 0
; VI-NEXT:    s_add_u32 s22, s22, 3
; VI-NEXT:    s_addc_u32 s23, s23, 0
; VI-NEXT:    s_add_u32 s24, s24, 3
; VI-NEXT:    s_addc_u32 s25, s25, 0
; VI-NEXT:  .LBB83_2: ; %end
; VI-NEXT:    v_mov_b32_e32 v0, s16
; VI-NEXT:    v_mov_b32_e32 v1, s17
; VI-NEXT:    v_mov_b32_e32 v2, s18
; VI-NEXT:    v_mov_b32_e32 v3, s19
; VI-NEXT:    v_mov_b32_e32 v4, s20
; VI-NEXT:    v_mov_b32_e32 v5, s21
; VI-NEXT:    v_mov_b32_e32 v6, s22
; VI-NEXT:    v_mov_b32_e32 v7, s23
; VI-NEXT:    v_mov_b32_e32 v8, s24
; VI-NEXT:    v_mov_b32_e32 v9, s25
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v5i64_to_v5f64_scalar:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_cmp_lg_u32 s26, 0
; GFX9-NEXT:    s_cbranch_scc1 .LBB83_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    s_add_u32 s16, s16, 3
; GFX9-NEXT:    s_addc_u32 s17, s17, 0
; GFX9-NEXT:    s_add_u32 s18, s18, 3
; GFX9-NEXT:    s_addc_u32 s19, s19, 0
; GFX9-NEXT:    s_add_u32 s20, s20, 3
; GFX9-NEXT:    s_addc_u32 s21, s21, 0
; GFX9-NEXT:    s_add_u32 s22, s22, 3
; GFX9-NEXT:    s_addc_u32 s23, s23, 0
; GFX9-NEXT:    s_add_u32 s24, s24, 3
; GFX9-NEXT:    s_addc_u32 s25, s25, 0
; GFX9-NEXT:  .LBB83_2: ; %end
; GFX9-NEXT:    v_mov_b32_e32 v0, s16
; GFX9-NEXT:    v_mov_b32_e32 v1, s17
; GFX9-NEXT:    v_mov_b32_e32 v2, s18
; GFX9-NEXT:    v_mov_b32_e32 v3, s19
; GFX9-NEXT:    v_mov_b32_e32 v4, s20
; GFX9-NEXT:    v_mov_b32_e32 v5, s21
; GFX9-NEXT:    v_mov_b32_e32 v6, s22
; GFX9-NEXT:    v_mov_b32_e32 v7, s23
; GFX9-NEXT:    v_mov_b32_e32 v8, s24
; GFX9-NEXT:    v_mov_b32_e32 v9, s25
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v5i64_to_v5f64_scalar:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_cmp_lg_u32 s22, 0
; GFX11-NEXT:    s_cbranch_scc1 .LBB83_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    s_add_u32 s0, s0, 3
; GFX11-NEXT:    s_addc_u32 s1, s1, 0
; GFX11-NEXT:    s_add_u32 s2, s2, 3
; GFX11-NEXT:    s_addc_u32 s3, s3, 0
; GFX11-NEXT:    s_add_u32 s16, s16, 3
; GFX11-NEXT:    s_addc_u32 s17, s17, 0
; GFX11-NEXT:    s_add_u32 s18, s18, 3
; GFX11-NEXT:    s_addc_u32 s19, s19, 0
; GFX11-NEXT:    s_add_u32 s20, s20, 3
; GFX11-NEXT:    s_addc_u32 s21, s21, 0
; GFX11-NEXT:  .LBB83_2: ; %end
; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT:    v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT:    v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT:    v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <5 x i64> %a, splat (i64 3)
  %a2 = bitcast <5 x i64> %a1 to <5 x double>
  br label %end

cmp.false:
  %a3 = bitcast <5 x i64> %a to <5 x double>
  br label %end

end:
  %phi = phi <5 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <5 x double> %phi
}

attributes #0 = { nounwind }