| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py | |
| ; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SD | |
| ; RUN: llc < %s -mtriple=aarch64 -mattr=+neon -global-isel -global-isel-abort=2 | FileCheck %s --check-prefixes=CHECK,CHECK-GI | |
| define <1 x i64> @llrint_v1i64_v1f16(<1 x half> %x) nounwind { | |
| ; CHECK-LABEL: llrint_v1i64_v1f16: | |
| ; CHECK: // %bb.0: | |
| ; CHECK-NEXT: fcvt s0, h0 | |
| ; CHECK-NEXT: frintx s0, s0 | |
| ; CHECK-NEXT: fcvtzs x8, s0 | |
| ; CHECK-NEXT: fmov d0, x8 | |
| ; CHECK-NEXT: ret | |
| %a = call <1 x i64> @llvm.llrint.v1i64.v1f16(<1 x half> %x) | |
| ret <1 x i64> %a | |
| } | |
| declare <1 x i64> @llvm.llrint.v1i64.v1f16(<1 x half>) | |
| define <2 x i64> @llrint_v1i64_v2f16(<2 x half> %x) nounwind { | |
| ; CHECK-SD-LABEL: llrint_v1i64_v2f16: | |
| ; CHECK-SD: // %bb.0: | |
| ; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 | |
| ; CHECK-SD-NEXT: mov h1, v0.h[1] | |
| ; CHECK-SD-NEXT: fcvt s0, h0 | |
| ; CHECK-SD-NEXT: fcvt s1, h1 | |
| ; CHECK-SD-NEXT: frintx s0, s0 | |
| ; CHECK-SD-NEXT: frintx s1, s1 | |
| ; CHECK-SD-NEXT: fcvtzs x8, s0 | |
| ; CHECK-SD-NEXT: fcvtzs x9, s1 | |
| ; CHECK-SD-NEXT: fmov d0, x8 | |
| ; CHECK-SD-NEXT: mov v0.d[1], x9 | |
| ; CHECK-SD-NEXT: ret | |
| ; | |
| ; CHECK-GI-LABEL: llrint_v1i64_v2f16: | |
| ; CHECK-GI: // %bb.0: | |
| ; CHECK-GI-NEXT: fcvtl v0.4s, v0.4h | |
| ; CHECK-GI-NEXT: frintx v0.2s, v0.2s | |
| ; CHECK-GI-NEXT: fcvtn v0.4h, v0.4s | |
| ; CHECK-GI-NEXT: fcvtl v0.4s, v0.4h | |
| ; CHECK-GI-NEXT: fcvtl v0.2d, v0.2s | |
| ; CHECK-GI-NEXT: fcvtzs v0.2d, v0.2d | |
| ; CHECK-GI-NEXT: ret | |
| %a = call <2 x i64> @llvm.llrint.v2i64.v2f16(<2 x half> %x) | |
| ret <2 x i64> %a | |
| } | |
| declare <2 x i64> @llvm.llrint.v2i64.v2f16(<2 x half>) | |
| define <4 x i64> @llrint_v4i64_v4f16(<4 x half> %x) nounwind { | |
| ; CHECK-SD-LABEL: llrint_v4i64_v4f16: | |
| ; CHECK-SD: // %bb.0: | |
| ; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 | |
| ; CHECK-SD-NEXT: mov h1, v0.h[2] | |
| ; CHECK-SD-NEXT: mov h2, v0.h[1] | |
| ; CHECK-SD-NEXT: mov h3, v0.h[3] | |
| ; CHECK-SD-NEXT: fcvt s0, h0 | |
| ; CHECK-SD-NEXT: fcvt s1, h1 | |
| ; CHECK-SD-NEXT: fcvt s2, h2 | |
| ; CHECK-SD-NEXT: fcvt s3, h3 | |
| ; CHECK-SD-NEXT: frintx s0, s0 | |
| ; CHECK-SD-NEXT: frintx s1, s1 | |
| ; CHECK-SD-NEXT: frintx s2, s2 | |
| ; CHECK-SD-NEXT: frintx s3, s3 | |
| ; CHECK-SD-NEXT: fcvtzs x8, s0 | |
| ; CHECK-SD-NEXT: fcvtzs x9, s1 | |
| ; CHECK-SD-NEXT: fcvtzs x10, s2 | |
| ; CHECK-SD-NEXT: fcvtzs x11, s3 | |
| ; CHECK-SD-NEXT: fmov d0, x8 | |
| ; CHECK-SD-NEXT: fmov d1, x9 | |
| ; CHECK-SD-NEXT: mov v0.d[1], x10 | |
| ; CHECK-SD-NEXT: mov v1.d[1], x11 | |
| ; CHECK-SD-NEXT: ret | |
| ; | |
| ; CHECK-GI-LABEL: llrint_v4i64_v4f16: | |
| ; CHECK-GI: // %bb.0: | |
| ; CHECK-GI-NEXT: fcvtl v0.4s, v0.4h | |
| ; CHECK-GI-NEXT: frintx v0.4s, v0.4s | |
| ; CHECK-GI-NEXT: fcvtn v0.4h, v0.4s | |
| ; CHECK-GI-NEXT: fcvtl v0.4s, v0.4h | |
| ; CHECK-GI-NEXT: fcvtl v1.2d, v0.2s | |
| ; CHECK-GI-NEXT: fcvtl2 v2.2d, v0.4s | |
| ; CHECK-GI-NEXT: fcvtzs v0.2d, v1.2d | |
| ; CHECK-GI-NEXT: fcvtzs v1.2d, v2.2d | |
| ; CHECK-GI-NEXT: ret | |
| %a = call <4 x i64> @llvm.llrint.v4i64.v4f16(<4 x half> %x) | |
| ret <4 x i64> %a | |
| } | |
| declare <4 x i64> @llvm.llrint.v4i64.v4f16(<4 x half>) | |
| define <8 x i64> @llrint_v8i64_v8f16(<8 x half> %x) nounwind { | |
| ; CHECK-SD-LABEL: llrint_v8i64_v8f16: | |
| ; CHECK-SD: // %bb.0: | |
| ; CHECK-SD-NEXT: mov d1, v0.d[1] | |
| ; CHECK-SD-NEXT: mov h4, v0.h[2] | |
| ; CHECK-SD-NEXT: mov h3, v0.h[1] | |
| ; CHECK-SD-NEXT: mov h7, v0.h[3] | |
| ; CHECK-SD-NEXT: fcvt s0, h0 | |
| ; CHECK-SD-NEXT: mov h2, v1.h[2] | |
| ; CHECK-SD-NEXT: mov h5, v1.h[1] | |
| ; CHECK-SD-NEXT: mov h6, v1.h[3] | |
| ; CHECK-SD-NEXT: fcvt s1, h1 | |
| ; CHECK-SD-NEXT: fcvt s4, h4 | |
| ; CHECK-SD-NEXT: fcvt s3, h3 | |
| ; CHECK-SD-NEXT: fcvt s7, h7 | |
| ; CHECK-SD-NEXT: frintx s0, s0 | |
| ; CHECK-SD-NEXT: fcvt s2, h2 | |
| ; CHECK-SD-NEXT: fcvt s5, h5 | |
| ; CHECK-SD-NEXT: fcvt s6, h6 | |
| ; CHECK-SD-NEXT: frintx s1, s1 | |
| ; CHECK-SD-NEXT: frintx s4, s4 | |
| ; CHECK-SD-NEXT: frintx s3, s3 | |
| ; CHECK-SD-NEXT: frintx s7, s7 | |
| ; CHECK-SD-NEXT: fcvtzs x9, s0 | |
| ; CHECK-SD-NEXT: frintx s2, s2 | |
| ; CHECK-SD-NEXT: frintx s5, s5 | |
| ; CHECK-SD-NEXT: frintx s6, s6 | |
| ; CHECK-SD-NEXT: fcvtzs x8, s1 | |
| ; CHECK-SD-NEXT: fcvtzs x12, s4 | |
| ; CHECK-SD-NEXT: fcvtzs x11, s3 | |
| ; CHECK-SD-NEXT: fcvtzs x15, s7 | |
| ; CHECK-SD-NEXT: fmov d0, x9 | |
| ; CHECK-SD-NEXT: fcvtzs x10, s2 | |
| ; CHECK-SD-NEXT: fcvtzs x13, s5 | |
| ; CHECK-SD-NEXT: fcvtzs x14, s6 | |
| ; CHECK-SD-NEXT: fmov d2, x8 | |
| ; CHECK-SD-NEXT: fmov d1, x12 | |
| ; CHECK-SD-NEXT: mov v0.d[1], x11 | |
| ; CHECK-SD-NEXT: fmov d3, x10 | |
| ; CHECK-SD-NEXT: mov v2.d[1], x13 | |
| ; CHECK-SD-NEXT: mov v1.d[1], x15 | |
| ; CHECK-SD-NEXT: mov v3.d[1], x14 | |
| ; CHECK-SD-NEXT: ret | |
| ; | |
| ; CHECK-GI-LABEL: llrint_v8i64_v8f16: | |
| ; CHECK-GI: // %bb.0: | |
| ; CHECK-GI-NEXT: fcvtl v1.4s, v0.4h | |
| ; CHECK-GI-NEXT: fcvtl2 v0.4s, v0.8h | |
| ; CHECK-GI-NEXT: frintx v1.4s, v1.4s | |
| ; CHECK-GI-NEXT: frintx v0.4s, v0.4s | |
| ; CHECK-GI-NEXT: fcvtn v1.4h, v1.4s | |
| ; CHECK-GI-NEXT: fcvtn v0.4h, v0.4s | |
| ; CHECK-GI-NEXT: fcvtl v1.4s, v1.4h | |
| ; CHECK-GI-NEXT: fcvtl v0.4s, v0.4h | |
| ; CHECK-GI-NEXT: fcvtl v2.2d, v1.2s | |
| ; CHECK-GI-NEXT: fcvtl2 v1.2d, v1.4s | |
| ; CHECK-GI-NEXT: fcvtl v3.2d, v0.2s | |
| ; CHECK-GI-NEXT: fcvtl2 v4.2d, v0.4s | |
| ; CHECK-GI-NEXT: fcvtzs v0.2d, v2.2d | |
| ; CHECK-GI-NEXT: fcvtzs v1.2d, v1.2d | |
| ; CHECK-GI-NEXT: fcvtzs v2.2d, v3.2d | |
| ; CHECK-GI-NEXT: fcvtzs v3.2d, v4.2d | |
| ; CHECK-GI-NEXT: ret | |
| %a = call <8 x i64> @llvm.llrint.v8i64.v8f16(<8 x half> %x) | |
| ret <8 x i64> %a | |
| } | |
| declare <8 x i64> @llvm.llrint.v8i64.v8f16(<8 x half>) | |
| define <16 x i64> @llrint_v16i64_v16f16(<16 x half> %x) nounwind { | |
| ; CHECK-SD-LABEL: llrint_v16i64_v16f16: | |
| ; CHECK-SD: // %bb.0: | |
| ; CHECK-SD-NEXT: mov d2, v0.d[1] | |
| ; CHECK-SD-NEXT: mov d3, v1.d[1] | |
| ; CHECK-SD-NEXT: mov h17, v0.h[1] | |
| ; CHECK-SD-NEXT: mov h19, v0.h[2] | |
| ; CHECK-SD-NEXT: fcvt s18, h0 | |
| ; CHECK-SD-NEXT: mov h0, v0.h[3] | |
| ; CHECK-SD-NEXT: mov h4, v2.h[1] | |
| ; CHECK-SD-NEXT: mov h5, v2.h[2] | |
| ; CHECK-SD-NEXT: fcvt s7, h3 | |
| ; CHECK-SD-NEXT: fcvt s6, h2 | |
| ; CHECK-SD-NEXT: mov h16, v3.h[2] | |
| ; CHECK-SD-NEXT: mov h2, v2.h[3] | |
| ; CHECK-SD-NEXT: fcvt s17, h17 | |
| ; CHECK-SD-NEXT: fcvt s19, h19 | |
| ; CHECK-SD-NEXT: frintx s18, s18 | |
| ; CHECK-SD-NEXT: fcvt s0, h0 | |
| ; CHECK-SD-NEXT: fcvt s4, h4 | |
| ; CHECK-SD-NEXT: fcvt s5, h5 | |
| ; CHECK-SD-NEXT: frintx s7, s7 | |
| ; CHECK-SD-NEXT: frintx s6, s6 | |
| ; CHECK-SD-NEXT: fcvt s16, h16 | |
| ; CHECK-SD-NEXT: fcvt s2, h2 | |
| ; CHECK-SD-NEXT: frintx s17, s17 | |
| ; CHECK-SD-NEXT: frintx s19, s19 | |
| ; CHECK-SD-NEXT: fcvtzs x13, s18 | |
| ; CHECK-SD-NEXT: frintx s0, s0 | |
| ; CHECK-SD-NEXT: frintx s4, s4 | |
| ; CHECK-SD-NEXT: frintx s5, s5 | |
| ; CHECK-SD-NEXT: fcvtzs x9, s7 | |
| ; CHECK-SD-NEXT: mov h7, v1.h[2] | |
| ; CHECK-SD-NEXT: fcvtzs x8, s6 | |
| ; CHECK-SD-NEXT: mov h6, v1.h[1] | |
| ; CHECK-SD-NEXT: frintx s16, s16 | |
| ; CHECK-SD-NEXT: fcvtzs x14, s17 | |
| ; CHECK-SD-NEXT: fcvtzs x15, s19 | |
| ; CHECK-SD-NEXT: fcvtzs x10, s4 | |
| ; CHECK-SD-NEXT: mov h4, v3.h[1] | |
| ; CHECK-SD-NEXT: fcvtzs x11, s5 | |
| ; CHECK-SD-NEXT: mov h5, v1.h[3] | |
| ; CHECK-SD-NEXT: mov h3, v3.h[3] | |
| ; CHECK-SD-NEXT: fcvt s1, h1 | |
| ; CHECK-SD-NEXT: fcvt s7, h7 | |
| ; CHECK-SD-NEXT: fcvt s6, h6 | |
| ; CHECK-SD-NEXT: fcvtzs x12, s16 | |
| ; CHECK-SD-NEXT: frintx s16, s2 | |
| ; CHECK-SD-NEXT: fmov d2, x8 | |
| ; CHECK-SD-NEXT: fcvt s4, h4 | |
| ; CHECK-SD-NEXT: fcvt s3, h3 | |
| ; CHECK-SD-NEXT: fcvt s5, h5 | |
| ; CHECK-SD-NEXT: frintx s1, s1 | |
| ; CHECK-SD-NEXT: frintx s7, s7 | |
| ; CHECK-SD-NEXT: frintx s17, s6 | |
| ; CHECK-SD-NEXT: fmov d6, x9 | |
| ; CHECK-SD-NEXT: mov v2.d[1], x10 | |
| ; CHECK-SD-NEXT: frintx s4, s4 | |
| ; CHECK-SD-NEXT: frintx s18, s3 | |
| ; CHECK-SD-NEXT: frintx s5, s5 | |
| ; CHECK-SD-NEXT: fcvtzs x8, s1 | |
| ; CHECK-SD-NEXT: fcvtzs x9, s7 | |
| ; CHECK-SD-NEXT: fmov d3, x11 | |
| ; CHECK-SD-NEXT: fcvtzs x11, s0 | |
| ; CHECK-SD-NEXT: fmov d7, x12 | |
| ; CHECK-SD-NEXT: fcvtzs x12, s16 | |
| ; CHECK-SD-NEXT: fcvtzs x16, s17 | |
| ; CHECK-SD-NEXT: fcvtzs x17, s4 | |
| ; CHECK-SD-NEXT: fmov d0, x13 | |
| ; CHECK-SD-NEXT: fmov d1, x15 | |
| ; CHECK-SD-NEXT: fcvtzs x18, s18 | |
| ; CHECK-SD-NEXT: fcvtzs x0, s5 | |
| ; CHECK-SD-NEXT: fmov d4, x8 | |
| ; CHECK-SD-NEXT: fmov d5, x9 | |
| ; CHECK-SD-NEXT: mov v0.d[1], x14 | |
| ; CHECK-SD-NEXT: mov v1.d[1], x11 | |
| ; CHECK-SD-NEXT: mov v3.d[1], x12 | |
| ; CHECK-SD-NEXT: mov v4.d[1], x16 | |
| ; CHECK-SD-NEXT: mov v6.d[1], x17 | |
| ; CHECK-SD-NEXT: mov v7.d[1], x18 | |
| ; CHECK-SD-NEXT: mov v5.d[1], x0 | |
| ; CHECK-SD-NEXT: ret | |
| ; | |
| ; CHECK-GI-LABEL: llrint_v16i64_v16f16: | |
| ; CHECK-GI: // %bb.0: | |
| ; CHECK-GI-NEXT: fcvtl v2.4s, v0.4h | |
| ; CHECK-GI-NEXT: fcvtl2 v0.4s, v0.8h | |
| ; CHECK-GI-NEXT: fcvtl v3.4s, v1.4h | |
| ; CHECK-GI-NEXT: fcvtl2 v1.4s, v1.8h | |
| ; CHECK-GI-NEXT: frintx v2.4s, v2.4s | |
| ; CHECK-GI-NEXT: frintx v0.4s, v0.4s | |
| ; CHECK-GI-NEXT: frintx v3.4s, v3.4s | |
| ; CHECK-GI-NEXT: frintx v1.4s, v1.4s | |
| ; CHECK-GI-NEXT: fcvtn v2.4h, v2.4s | |
| ; CHECK-GI-NEXT: fcvtn v0.4h, v0.4s | |
| ; CHECK-GI-NEXT: fcvtn v3.4h, v3.4s | |
| ; CHECK-GI-NEXT: fcvtn v1.4h, v1.4s | |
| ; CHECK-GI-NEXT: fcvtl v2.4s, v2.4h | |
| ; CHECK-GI-NEXT: fcvtl v0.4s, v0.4h | |
| ; CHECK-GI-NEXT: fcvtl v3.4s, v3.4h | |
| ; CHECK-GI-NEXT: fcvtl v1.4s, v1.4h | |
| ; CHECK-GI-NEXT: fcvtl v4.2d, v2.2s | |
| ; CHECK-GI-NEXT: fcvtl2 v2.2d, v2.4s | |
| ; CHECK-GI-NEXT: fcvtl v5.2d, v0.2s | |
| ; CHECK-GI-NEXT: fcvtl2 v6.2d, v0.4s | |
| ; CHECK-GI-NEXT: fcvtl v7.2d, v3.2s | |
| ; CHECK-GI-NEXT: fcvtl2 v16.2d, v3.4s | |
| ; CHECK-GI-NEXT: fcvtl v17.2d, v1.2s | |
| ; CHECK-GI-NEXT: fcvtl2 v18.2d, v1.4s | |
| ; CHECK-GI-NEXT: fcvtzs v0.2d, v4.2d | |
| ; CHECK-GI-NEXT: fcvtzs v1.2d, v2.2d | |
| ; CHECK-GI-NEXT: fcvtzs v2.2d, v5.2d | |
| ; CHECK-GI-NEXT: fcvtzs v3.2d, v6.2d | |
| ; CHECK-GI-NEXT: fcvtzs v4.2d, v7.2d | |
| ; CHECK-GI-NEXT: fcvtzs v5.2d, v16.2d | |
| ; CHECK-GI-NEXT: fcvtzs v6.2d, v17.2d | |
| ; CHECK-GI-NEXT: fcvtzs v7.2d, v18.2d | |
| ; CHECK-GI-NEXT: ret | |
| %a = call <16 x i64> @llvm.llrint.v16i64.v16f16(<16 x half> %x) | |
| ret <16 x i64> %a | |
| } | |
| declare <16 x i64> @llvm.llrint.v16i64.v16f16(<16 x half>) | |
| define <32 x i64> @llrint_v32i64_v32f16(<32 x half> %x) nounwind { | |
| ; CHECK-SD-LABEL: llrint_v32i64_v32f16: | |
| ; CHECK-SD: // %bb.0: | |
| ; CHECK-SD-NEXT: mov d4, v1.d[1] | |
| ; CHECK-SD-NEXT: mov d5, v2.d[1] | |
| ; CHECK-SD-NEXT: mov d6, v3.d[1] | |
| ; CHECK-SD-NEXT: mov d7, v0.d[1] | |
| ; CHECK-SD-NEXT: mov h19, v0.h[1] | |
| ; CHECK-SD-NEXT: fcvt s21, h0 | |
| ; CHECK-SD-NEXT: mov h23, v1.h[2] | |
| ; CHECK-SD-NEXT: fcvt s22, h1 | |
| ; CHECK-SD-NEXT: fcvt s26, h2 | |
| ; CHECK-SD-NEXT: mov h27, v2.h[1] | |
| ; CHECK-SD-NEXT: mov h28, v2.h[2] | |
| ; CHECK-SD-NEXT: mov h16, v4.h[2] | |
| ; CHECK-SD-NEXT: fcvt s17, h5 | |
| ; CHECK-SD-NEXT: mov h18, v5.h[2] | |
| ; CHECK-SD-NEXT: mov h20, v6.h[2] | |
| ; CHECK-SD-NEXT: fcvt s24, h7 | |
| ; CHECK-SD-NEXT: fcvt s25, h6 | |
| ; CHECK-SD-NEXT: fcvt s19, h19 | |
| ; CHECK-SD-NEXT: frintx s22, s22 | |
| ; CHECK-SD-NEXT: fcvt s16, h16 | |
| ; CHECK-SD-NEXT: frintx s17, s17 | |
| ; CHECK-SD-NEXT: fcvt s18, h18 | |
| ; CHECK-SD-NEXT: fcvt s20, h20 | |
| ; CHECK-SD-NEXT: frintx s16, s16 | |
| ; CHECK-SD-NEXT: fcvtzs x12, s17 | |
| ; CHECK-SD-NEXT: frintx s17, s18 | |
| ; CHECK-SD-NEXT: frintx s18, s21 | |
| ; CHECK-SD-NEXT: fcvt s21, h23 | |
| ; CHECK-SD-NEXT: frintx s23, s24 | |
| ; CHECK-SD-NEXT: frintx s24, s25 | |
| ; CHECK-SD-NEXT: frintx s25, s19 | |
| ; CHECK-SD-NEXT: mov h19, v7.h[1] | |
| ; CHECK-SD-NEXT: fcvtzs x13, s16 | |
| ; CHECK-SD-NEXT: frintx s16, s20 | |
| ; CHECK-SD-NEXT: frintx s20, s26 | |
| ; CHECK-SD-NEXT: fcvtzs x9, s23 | |
| ; CHECK-SD-NEXT: mov h23, v3.h[2] | |
| ; CHECK-SD-NEXT: fcvt s26, h27 | |
| ; CHECK-SD-NEXT: fcvtzs x15, s24 | |
| ; CHECK-SD-NEXT: fcvtzs x10, s25 | |
| ; CHECK-SD-NEXT: fcvt s24, h28 | |
| ; CHECK-SD-NEXT: mov h25, v3.h[3] | |
| ; CHECK-SD-NEXT: fcvtzs x14, s17 | |
| ; CHECK-SD-NEXT: frintx s21, s21 | |
| ; CHECK-SD-NEXT: fmov d17, x12 | |
| ; CHECK-SD-NEXT: fcvtzs x12, s16 | |
| ; CHECK-SD-NEXT: fmov d16, x13 | |
| ; CHECK-SD-NEXT: fcvtzs x13, s22 | |
| ; CHECK-SD-NEXT: fcvt s22, h3 | |
| ; CHECK-SD-NEXT: mov h3, v3.h[1] | |
| ; CHECK-SD-NEXT: mov h27, v0.h[2] | |
| ; CHECK-SD-NEXT: mov h28, v2.h[3] | |
| ; CHECK-SD-NEXT: fcvt s23, h23 | |
| ; CHECK-SD-NEXT: frintx s26, s26 | |
| ; CHECK-SD-NEXT: fcvtzs x16, s20 | |
| ; CHECK-SD-NEXT: frintx s20, s24 | |
| ; CHECK-SD-NEXT: fcvt s24, h25 | |
| ; CHECK-SD-NEXT: fcvtzs x11, s18 | |
| ; CHECK-SD-NEXT: fmov d18, x14 | |
| ; CHECK-SD-NEXT: fcvtzs x14, s21 | |
| ; CHECK-SD-NEXT: frintx s22, s22 | |
| ; CHECK-SD-NEXT: fcvt s3, h3 | |
| ; CHECK-SD-NEXT: fcvt s25, h27 | |
| ; CHECK-SD-NEXT: fcvt s27, h28 | |
| ; CHECK-SD-NEXT: frintx s23, s23 | |
| ; CHECK-SD-NEXT: mov h21, v1.h[3] | |
| ; CHECK-SD-NEXT: fmov d2, x15 | |
| ; CHECK-SD-NEXT: fcvtzs x15, s26 | |
| ; CHECK-SD-NEXT: fmov d26, x13 | |
| ; CHECK-SD-NEXT: mov h1, v1.h[1] | |
| ; CHECK-SD-NEXT: fcvtzs x13, s20 | |
| ; CHECK-SD-NEXT: frintx s20, s24 | |
| ; CHECK-SD-NEXT: fmov d24, x14 | |
| ; CHECK-SD-NEXT: fcvtzs x14, s22 | |
| ; CHECK-SD-NEXT: frintx s3, s3 | |
| ; CHECK-SD-NEXT: fmov d22, x16 | |
| ; CHECK-SD-NEXT: frintx s27, s27 | |
| ; CHECK-SD-NEXT: fcvtzs x16, s23 | |
| ; CHECK-SD-NEXT: fcvt s21, h21 | |
| ; CHECK-SD-NEXT: frintx s25, s25 | |
| ; CHECK-SD-NEXT: fcvt s1, h1 | |
| ; CHECK-SD-NEXT: mov h0, v0.h[3] | |
| ; CHECK-SD-NEXT: mov h23, v7.h[2] | |
| ; CHECK-SD-NEXT: mov v22.d[1], x15 | |
| ; CHECK-SD-NEXT: fcvtzs x15, s20 | |
| ; CHECK-SD-NEXT: fmov d20, x13 | |
| ; CHECK-SD-NEXT: fcvtzs x13, s3 | |
| ; CHECK-SD-NEXT: fmov d3, x14 | |
| ; CHECK-SD-NEXT: fcvtzs x14, s27 | |
| ; CHECK-SD-NEXT: fmov d27, x16 | |
| ; CHECK-SD-NEXT: frintx s21, s21 | |
| ; CHECK-SD-NEXT: mov h7, v7.h[3] | |
| ; CHECK-SD-NEXT: frintx s1, s1 | |
| ; CHECK-SD-NEXT: fcvt s0, h0 | |
| ; CHECK-SD-NEXT: fcvt s23, h23 | |
| ; CHECK-SD-NEXT: fcvt s19, h19 | |
| ; CHECK-SD-NEXT: mov v27.d[1], x15 | |
| ; CHECK-SD-NEXT: fcvtzs x15, s25 | |
| ; CHECK-SD-NEXT: mov h25, v6.h[3] | |
| ; CHECK-SD-NEXT: mov h6, v6.h[1] | |
| ; CHECK-SD-NEXT: mov v3.d[1], x13 | |
| ; CHECK-SD-NEXT: fcvtzs x13, s21 | |
| ; CHECK-SD-NEXT: mov h21, v5.h[1] | |
| ; CHECK-SD-NEXT: mov h5, v5.h[3] | |
| ; CHECK-SD-NEXT: mov v20.d[1], x14 | |
| ; CHECK-SD-NEXT: fcvtzs x14, s1 | |
| ; CHECK-SD-NEXT: mov h1, v4.h[1] | |
| ; CHECK-SD-NEXT: frintx s0, s0 | |
| ; CHECK-SD-NEXT: fcvt s25, h25 | |
| ; CHECK-SD-NEXT: fcvt s7, h7 | |
| ; CHECK-SD-NEXT: stp q3, q27, [x8, #192] | |
| ; CHECK-SD-NEXT: fcvt s6, h6 | |
| ; CHECK-SD-NEXT: mov h3, v4.h[3] | |
| ; CHECK-SD-NEXT: stp q22, q20, [x8, #128] | |
| ; CHECK-SD-NEXT: fcvt s21, h21 | |
| ; CHECK-SD-NEXT: fcvt s5, h5 | |
| ; CHECK-SD-NEXT: mov v24.d[1], x13 | |
| ; CHECK-SD-NEXT: mov v26.d[1], x14 | |
| ; CHECK-SD-NEXT: fcvt s4, h4 | |
| ; CHECK-SD-NEXT: frintx s22, s25 | |
| ; CHECK-SD-NEXT: fmov d20, x12 | |
| ; CHECK-SD-NEXT: fcvt s1, h1 | |
| ; CHECK-SD-NEXT: frintx s6, s6 | |
| ; CHECK-SD-NEXT: fcvt s3, h3 | |
| ; CHECK-SD-NEXT: fcvtzs x12, s0 | |
| ; CHECK-SD-NEXT: frintx s5, s5 | |
| ; CHECK-SD-NEXT: frintx s21, s21 | |
| ; CHECK-SD-NEXT: fmov d0, x11 | |
| ; CHECK-SD-NEXT: stp q26, q24, [x8, #64] | |
| ; CHECK-SD-NEXT: fmov d24, x15 | |
| ; CHECK-SD-NEXT: frintx s4, s4 | |
| ; CHECK-SD-NEXT: fcvtzs x11, s22 | |
| ; CHECK-SD-NEXT: frintx s22, s23 | |
| ; CHECK-SD-NEXT: frintx s1, s1 | |
| ; CHECK-SD-NEXT: fcvtzs x13, s6 | |
| ; CHECK-SD-NEXT: frintx s3, s3 | |
| ; CHECK-SD-NEXT: frintx s6, s7 | |
| ; CHECK-SD-NEXT: fcvtzs x14, s5 | |
| ; CHECK-SD-NEXT: mov v24.d[1], x12 | |
| ; CHECK-SD-NEXT: frintx s5, s19 | |
| ; CHECK-SD-NEXT: fcvtzs x12, s21 | |
| ; CHECK-SD-NEXT: mov v0.d[1], x10 | |
| ; CHECK-SD-NEXT: fcvtzs x10, s4 | |
| ; CHECK-SD-NEXT: mov v20.d[1], x11 | |
| ; CHECK-SD-NEXT: fcvtzs x11, s22 | |
| ; CHECK-SD-NEXT: mov v2.d[1], x13 | |
| ; CHECK-SD-NEXT: fcvtzs x15, s3 | |
| ; CHECK-SD-NEXT: fcvtzs x13, s1 | |
| ; CHECK-SD-NEXT: mov v18.d[1], x14 | |
| ; CHECK-SD-NEXT: fcvtzs x14, s6 | |
| ; CHECK-SD-NEXT: stp q0, q24, [x8] | |
| ; CHECK-SD-NEXT: mov v17.d[1], x12 | |
| ; CHECK-SD-NEXT: fcvtzs x12, s5 | |
| ; CHECK-SD-NEXT: fmov d0, x10 | |
| ; CHECK-SD-NEXT: fmov d1, x11 | |
| ; CHECK-SD-NEXT: stp q2, q20, [x8, #224] | |
| ; CHECK-SD-NEXT: fmov d2, x9 | |
| ; CHECK-SD-NEXT: mov v16.d[1], x15 | |
| ; CHECK-SD-NEXT: stp q17, q18, [x8, #160] | |
| ; CHECK-SD-NEXT: mov v0.d[1], x13 | |
| ; CHECK-SD-NEXT: mov v1.d[1], x14 | |
| ; CHECK-SD-NEXT: mov v2.d[1], x12 | |
| ; CHECK-SD-NEXT: stp q0, q16, [x8, #96] | |
| ; CHECK-SD-NEXT: stp q2, q1, [x8, #32] | |
| ; CHECK-SD-NEXT: ret | |
| ; | |
| ; CHECK-GI-LABEL: llrint_v32i64_v32f16: | |
| ; CHECK-GI: // %bb.0: | |
| ; CHECK-GI-NEXT: fcvtl v4.4s, v0.4h | |
| ; CHECK-GI-NEXT: fcvtl2 v0.4s, v0.8h | |
| ; CHECK-GI-NEXT: fcvtl v5.4s, v1.4h | |
| ; CHECK-GI-NEXT: fcvtl2 v1.4s, v1.8h | |
| ; CHECK-GI-NEXT: fcvtl v6.4s, v2.4h | |
| ; CHECK-GI-NEXT: fcvtl2 v2.4s, v2.8h | |
| ; CHECK-GI-NEXT: fcvtl v7.4s, v3.4h | |
| ; CHECK-GI-NEXT: fcvtl2 v3.4s, v3.8h | |
| ; CHECK-GI-NEXT: frintx v4.4s, v4.4s | |
| ; CHECK-GI-NEXT: frintx v0.4s, v0.4s | |
| ; CHECK-GI-NEXT: frintx v5.4s, v5.4s | |
| ; CHECK-GI-NEXT: frintx v1.4s, v1.4s | |
| ; CHECK-GI-NEXT: frintx v6.4s, v6.4s | |
| ; CHECK-GI-NEXT: frintx v2.4s, v2.4s | |
| ; CHECK-GI-NEXT: frintx v7.4s, v7.4s | |
| ; CHECK-GI-NEXT: frintx v3.4s, v3.4s | |
| ; CHECK-GI-NEXT: fcvtn v4.4h, v4.4s | |
| ; CHECK-GI-NEXT: fcvtn v0.4h, v0.4s | |
| ; CHECK-GI-NEXT: fcvtn v5.4h, v5.4s | |
| ; CHECK-GI-NEXT: fcvtn v1.4h, v1.4s | |
| ; CHECK-GI-NEXT: fcvtn v6.4h, v6.4s | |
| ; CHECK-GI-NEXT: fcvtn v2.4h, v2.4s | |
| ; CHECK-GI-NEXT: fcvtn v7.4h, v7.4s | |
| ; CHECK-GI-NEXT: fcvtn v3.4h, v3.4s | |
| ; CHECK-GI-NEXT: fcvtl v4.4s, v4.4h | |
| ; CHECK-GI-NEXT: fcvtl v0.4s, v0.4h | |
| ; CHECK-GI-NEXT: fcvtl v5.4s, v5.4h | |
| ; CHECK-GI-NEXT: fcvtl v1.4s, v1.4h | |
| ; CHECK-GI-NEXT: fcvtl v6.4s, v6.4h | |
| ; CHECK-GI-NEXT: fcvtl v2.4s, v2.4h | |
| ; CHECK-GI-NEXT: fcvtl v7.4s, v7.4h | |
| ; CHECK-GI-NEXT: fcvtl v3.4s, v3.4h | |
| ; CHECK-GI-NEXT: fcvtl v16.2d, v4.2s | |
| ; CHECK-GI-NEXT: fcvtl2 v4.2d, v4.4s | |
| ; CHECK-GI-NEXT: fcvtl v17.2d, v0.2s | |
| ; CHECK-GI-NEXT: fcvtl2 v0.2d, v0.4s | |
| ; CHECK-GI-NEXT: fcvtl v18.2d, v5.2s | |
| ; CHECK-GI-NEXT: fcvtl2 v5.2d, v5.4s | |
| ; CHECK-GI-NEXT: fcvtl v19.2d, v1.2s | |
| ; CHECK-GI-NEXT: fcvtl2 v1.2d, v1.4s | |
| ; CHECK-GI-NEXT: fcvtl v20.2d, v6.2s | |
| ; CHECK-GI-NEXT: fcvtl2 v6.2d, v6.4s | |
| ; CHECK-GI-NEXT: fcvtzs v16.2d, v16.2d | |
| ; CHECK-GI-NEXT: fcvtzs v4.2d, v4.2d | |
| ; CHECK-GI-NEXT: fcvtzs v17.2d, v17.2d | |
| ; CHECK-GI-NEXT: fcvtzs v0.2d, v0.2d | |
| ; CHECK-GI-NEXT: fcvtzs v18.2d, v18.2d | |
| ; CHECK-GI-NEXT: fcvtzs v5.2d, v5.2d | |
| ; CHECK-GI-NEXT: fcvtzs v1.2d, v1.2d | |
| ; CHECK-GI-NEXT: fcvtzs v6.2d, v6.2d | |
| ; CHECK-GI-NEXT: stp q16, q4, [x8] | |
| ; CHECK-GI-NEXT: fcvtzs v16.2d, v19.2d | |
| ; CHECK-GI-NEXT: fcvtl v4.2d, v2.2s | |
| ; CHECK-GI-NEXT: stp q17, q0, [x8, #32] | |
| ; CHECK-GI-NEXT: fcvtl2 v2.2d, v2.4s | |
| ; CHECK-GI-NEXT: fcvtl v0.2d, v7.2s | |
| ; CHECK-GI-NEXT: stp q18, q5, [x8, #64] | |
| ; CHECK-GI-NEXT: fcvtl2 v5.2d, v7.4s | |
| ; CHECK-GI-NEXT: fcvtl v7.2d, v3.2s | |
| ; CHECK-GI-NEXT: fcvtzs v17.2d, v20.2d | |
| ; CHECK-GI-NEXT: stp q16, q1, [x8, #96] | |
| ; CHECK-GI-NEXT: fcvtl2 v1.2d, v3.4s | |
| ; CHECK-GI-NEXT: fcvtzs v4.2d, v4.2d | |
| ; CHECK-GI-NEXT: fcvtzs v2.2d, v2.2d | |
| ; CHECK-GI-NEXT: fcvtzs v0.2d, v0.2d | |
| ; CHECK-GI-NEXT: fcvtzs v3.2d, v5.2d | |
| ; CHECK-GI-NEXT: fcvtzs v5.2d, v7.2d | |
| ; CHECK-GI-NEXT: stp q17, q6, [x8, #128] | |
| ; CHECK-GI-NEXT: fcvtzs v1.2d, v1.2d | |
| ; CHECK-GI-NEXT: stp q4, q2, [x8, #160] | |
| ; CHECK-GI-NEXT: stp q0, q3, [x8, #192] | |
| ; CHECK-GI-NEXT: stp q5, q1, [x8, #224] | |
| ; CHECK-GI-NEXT: ret | |
| %a = call <32 x i64> @llvm.llrint.v32i64.v32f16(<32 x half> %x) | |
| ret <32 x i64> %a | |
| } | |
| declare <32 x i64> @llvm.llrint.v32i64.v32f16(<32 x half>) | |
| define <1 x i64> @llrint_v1i64_v1f32(<1 x float> %x) nounwind { | |
| ; CHECK-SD-LABEL: llrint_v1i64_v1f32: | |
| ; CHECK-SD: // %bb.0: | |
| ; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 | |
| ; CHECK-SD-NEXT: frintx s0, s0 | |
| ; CHECK-SD-NEXT: fcvtzs x8, s0 | |
| ; CHECK-SD-NEXT: fmov d0, x8 | |
| ; CHECK-SD-NEXT: ret | |
| ; | |
| ; CHECK-GI-LABEL: llrint_v1i64_v1f32: | |
| ; CHECK-GI: // %bb.0: | |
| ; CHECK-GI-NEXT: frintx s0, s0 | |
| ; CHECK-GI-NEXT: fcvtzs x8, s0 | |
| ; CHECK-GI-NEXT: fmov d0, x8 | |
| ; CHECK-GI-NEXT: ret | |
| %a = call <1 x i64> @llvm.llrint.v1i64.v1f32(<1 x float> %x) | |
| ret <1 x i64> %a | |
| } | |
| declare <1 x i64> @llvm.llrint.v1i64.v1f32(<1 x float>) | |
| define <2 x i64> @llrint_v2i64_v2f32(<2 x float> %x) nounwind { | |
| ; CHECK-LABEL: llrint_v2i64_v2f32: | |
| ; CHECK: // %bb.0: | |
| ; CHECK-NEXT: frintx v0.2s, v0.2s | |
| ; CHECK-NEXT: fcvtl v0.2d, v0.2s | |
| ; CHECK-NEXT: fcvtzs v0.2d, v0.2d | |
| ; CHECK-NEXT: ret | |
| %a = call <2 x i64> @llvm.llrint.v2i64.v2f32(<2 x float> %x) | |
| ret <2 x i64> %a | |
| } | |
| declare <2 x i64> @llvm.llrint.v2i64.v2f32(<2 x float>) | |
| define <4 x i64> @llrint_v4i64_v4f32(<4 x float> %x) nounwind { | |
| ; CHECK-SD-LABEL: llrint_v4i64_v4f32: | |
| ; CHECK-SD: // %bb.0: | |
| ; CHECK-SD-NEXT: mov d1, v0.d[1] | |
| ; CHECK-SD-NEXT: frintx v0.2s, v0.2s | |
| ; CHECK-SD-NEXT: frintx v1.2s, v1.2s | |
| ; CHECK-SD-NEXT: fcvtl v0.2d, v0.2s | |
| ; CHECK-SD-NEXT: fcvtl v1.2d, v1.2s | |
| ; CHECK-SD-NEXT: fcvtzs v0.2d, v0.2d | |
| ; CHECK-SD-NEXT: fcvtzs v1.2d, v1.2d | |
| ; CHECK-SD-NEXT: ret | |
| ; | |
| ; CHECK-GI-LABEL: llrint_v4i64_v4f32: | |
| ; CHECK-GI: // %bb.0: | |
| ; CHECK-GI-NEXT: frintx v0.4s, v0.4s | |
| ; CHECK-GI-NEXT: fcvtl v1.2d, v0.2s | |
| ; CHECK-GI-NEXT: fcvtl2 v2.2d, v0.4s | |
| ; CHECK-GI-NEXT: fcvtzs v0.2d, v1.2d | |
| ; CHECK-GI-NEXT: fcvtzs v1.2d, v2.2d | |
| ; CHECK-GI-NEXT: ret | |
| %a = call <4 x i64> @llvm.llrint.v4i64.v4f32(<4 x float> %x) | |
| ret <4 x i64> %a | |
| } | |
| declare <4 x i64> @llvm.llrint.v4i64.v4f32(<4 x float>) | |
| define <8 x i64> @llrint_v8i64_v8f32(<8 x float> %x) nounwind { | |
| ; CHECK-SD-LABEL: llrint_v8i64_v8f32: | |
| ; CHECK-SD: // %bb.0: | |
| ; CHECK-SD-NEXT: mov d2, v0.d[1] | |
| ; CHECK-SD-NEXT: mov d3, v1.d[1] | |
| ; CHECK-SD-NEXT: frintx v0.2s, v0.2s | |
| ; CHECK-SD-NEXT: frintx v1.2s, v1.2s | |
| ; CHECK-SD-NEXT: frintx v2.2s, v2.2s | |
| ; CHECK-SD-NEXT: frintx v3.2s, v3.2s | |
| ; CHECK-SD-NEXT: fcvtl v0.2d, v0.2s | |
| ; CHECK-SD-NEXT: fcvtl v4.2d, v1.2s | |
| ; CHECK-SD-NEXT: fcvtl v2.2d, v2.2s | |
| ; CHECK-SD-NEXT: fcvtl v3.2d, v3.2s | |
| ; CHECK-SD-NEXT: fcvtzs v0.2d, v0.2d | |
| ; CHECK-SD-NEXT: fcvtzs v1.2d, v2.2d | |
| ; CHECK-SD-NEXT: fcvtzs v2.2d, v4.2d | |
| ; CHECK-SD-NEXT: fcvtzs v3.2d, v3.2d | |
| ; CHECK-SD-NEXT: ret | |
| ; | |
| ; CHECK-GI-LABEL: llrint_v8i64_v8f32: | |
| ; CHECK-GI: // %bb.0: | |
| ; CHECK-GI-NEXT: frintx v0.4s, v0.4s | |
| ; CHECK-GI-NEXT: frintx v1.4s, v1.4s | |
| ; CHECK-GI-NEXT: fcvtl v2.2d, v0.2s | |
| ; CHECK-GI-NEXT: fcvtl2 v3.2d, v0.4s | |
| ; CHECK-GI-NEXT: fcvtl v4.2d, v1.2s | |
| ; CHECK-GI-NEXT: fcvtl2 v5.2d, v1.4s | |
| ; CHECK-GI-NEXT: fcvtzs v0.2d, v2.2d | |
| ; CHECK-GI-NEXT: fcvtzs v1.2d, v3.2d | |
| ; CHECK-GI-NEXT: fcvtzs v2.2d, v4.2d | |
| ; CHECK-GI-NEXT: fcvtzs v3.2d, v5.2d | |
| ; CHECK-GI-NEXT: ret | |
| %a = call <8 x i64> @llvm.llrint.v8i64.v8f32(<8 x float> %x) | |
| ret <8 x i64> %a | |
| } | |
| declare <8 x i64> @llvm.llrint.v8i64.v8f32(<8 x float>) | |
| define <16 x i64> @llrint_v16i64_v16f32(<16 x float> %x) nounwind { | |
| ; CHECK-SD-LABEL: llrint_v16i64_v16f32: | |
| ; CHECK-SD: // %bb.0: | |
| ; CHECK-SD-NEXT: mov d4, v1.d[1] | |
| ; CHECK-SD-NEXT: mov d5, v0.d[1] | |
| ; CHECK-SD-NEXT: mov d6, v2.d[1] | |
| ; CHECK-SD-NEXT: mov d7, v3.d[1] | |
| ; CHECK-SD-NEXT: frintx v0.2s, v0.2s | |
| ; CHECK-SD-NEXT: frintx v1.2s, v1.2s | |
| ; CHECK-SD-NEXT: frintx v2.2s, v2.2s | |
| ; CHECK-SD-NEXT: frintx v3.2s, v3.2s | |
| ; CHECK-SD-NEXT: frintx v5.2s, v5.2s | |
| ; CHECK-SD-NEXT: frintx v4.2s, v4.2s | |
| ; CHECK-SD-NEXT: frintx v6.2s, v6.2s | |
| ; CHECK-SD-NEXT: frintx v7.2s, v7.2s | |
| ; CHECK-SD-NEXT: fcvtl v0.2d, v0.2s | |
| ; CHECK-SD-NEXT: fcvtl v1.2d, v1.2s | |
| ; CHECK-SD-NEXT: fcvtl v16.2d, v2.2s | |
| ; CHECK-SD-NEXT: fcvtl v18.2d, v3.2s | |
| ; CHECK-SD-NEXT: fcvtl v5.2d, v5.2s | |
| ; CHECK-SD-NEXT: fcvtl v17.2d, v4.2s | |
| ; CHECK-SD-NEXT: fcvtl v19.2d, v6.2s | |
| ; CHECK-SD-NEXT: fcvtl v7.2d, v7.2s | |
| ; CHECK-SD-NEXT: fcvtzs v0.2d, v0.2d | |
| ; CHECK-SD-NEXT: fcvtzs v2.2d, v1.2d | |
| ; CHECK-SD-NEXT: fcvtzs v4.2d, v16.2d | |
| ; CHECK-SD-NEXT: fcvtzs v6.2d, v18.2d | |
| ; CHECK-SD-NEXT: fcvtzs v1.2d, v5.2d | |
| ; CHECK-SD-NEXT: fcvtzs v3.2d, v17.2d | |
| ; CHECK-SD-NEXT: fcvtzs v5.2d, v19.2d | |
| ; CHECK-SD-NEXT: fcvtzs v7.2d, v7.2d | |
| ; CHECK-SD-NEXT: ret | |
| ; | |
| ; CHECK-GI-LABEL: llrint_v16i64_v16f32: | |
| ; CHECK-GI: // %bb.0: | |
| ; CHECK-GI-NEXT: frintx v0.4s, v0.4s | |
| ; CHECK-GI-NEXT: frintx v1.4s, v1.4s | |
| ; CHECK-GI-NEXT: frintx v2.4s, v2.4s | |
| ; CHECK-GI-NEXT: frintx v3.4s, v3.4s | |
| ; CHECK-GI-NEXT: fcvtl v4.2d, v0.2s | |
| ; CHECK-GI-NEXT: fcvtl2 v5.2d, v0.4s | |
| ; CHECK-GI-NEXT: fcvtl v6.2d, v1.2s | |
| ; CHECK-GI-NEXT: fcvtl2 v7.2d, v1.4s | |
| ; CHECK-GI-NEXT: fcvtl v16.2d, v2.2s | |
| ; CHECK-GI-NEXT: fcvtl2 v17.2d, v2.4s | |
| ; CHECK-GI-NEXT: fcvtl v18.2d, v3.2s | |
| ; CHECK-GI-NEXT: fcvtl2 v19.2d, v3.4s | |
| ; CHECK-GI-NEXT: fcvtzs v0.2d, v4.2d | |
| ; CHECK-GI-NEXT: fcvtzs v1.2d, v5.2d | |
| ; CHECK-GI-NEXT: fcvtzs v2.2d, v6.2d | |
| ; CHECK-GI-NEXT: fcvtzs v3.2d, v7.2d | |
| ; CHECK-GI-NEXT: fcvtzs v4.2d, v16.2d | |
| ; CHECK-GI-NEXT: fcvtzs v5.2d, v17.2d | |
| ; CHECK-GI-NEXT: fcvtzs v6.2d, v18.2d | |
| ; CHECK-GI-NEXT: fcvtzs v7.2d, v19.2d | |
| ; CHECK-GI-NEXT: ret | |
| %a = call <16 x i64> @llvm.llrint.v16i64.v16f32(<16 x float> %x) | |
| ret <16 x i64> %a | |
| } | |
| declare <16 x i64> @llvm.llrint.v16i64.v16f32(<16 x float>) | |
| define <32 x i64> @llrint_v32i64_v32f32(<32 x float> %x) nounwind { | |
| ; CHECK-SD-LABEL: llrint_v32i64_v32f32: | |
| ; CHECK-SD: // %bb.0: | |
| ; CHECK-SD-NEXT: mov d16, v7.d[1] | |
| ; CHECK-SD-NEXT: mov d17, v6.d[1] | |
| ; CHECK-SD-NEXT: frintx v7.2s, v7.2s | |
| ; CHECK-SD-NEXT: mov d18, v5.d[1] | |
| ; CHECK-SD-NEXT: frintx v6.2s, v6.2s | |
| ; CHECK-SD-NEXT: mov d19, v4.d[1] | |
| ; CHECK-SD-NEXT: mov d22, v3.d[1] | |
| ; CHECK-SD-NEXT: frintx v5.2s, v5.2s | |
| ; CHECK-SD-NEXT: mov d20, v0.d[1] | |
| ; CHECK-SD-NEXT: frintx v21.2s, v1.2s | |
| ; CHECK-SD-NEXT: mov d1, v1.d[1] | |
| ; CHECK-SD-NEXT: mov d23, v2.d[1] | |
| ; CHECK-SD-NEXT: frintx v16.2s, v16.2s | |
| ; CHECK-SD-NEXT: frintx v17.2s, v17.2s | |
| ; CHECK-SD-NEXT: fcvtl v7.2d, v7.2s | |
| ; CHECK-SD-NEXT: frintx v18.2s, v18.2s | |
| ; CHECK-SD-NEXT: fcvtl v6.2d, v6.2s | |
| ; CHECK-SD-NEXT: frintx v19.2s, v19.2s | |
| ; CHECK-SD-NEXT: frintx v4.2s, v4.2s | |
| ; CHECK-SD-NEXT: frintx v22.2s, v22.2s | |
| ; CHECK-SD-NEXT: frintx v3.2s, v3.2s | |
| ; CHECK-SD-NEXT: fcvtl v5.2d, v5.2s | |
| ; CHECK-SD-NEXT: frintx v2.2s, v2.2s | |
| ; CHECK-SD-NEXT: frintx v23.2s, v23.2s | |
| ; CHECK-SD-NEXT: fcvtl v16.2d, v16.2s | |
| ; CHECK-SD-NEXT: fcvtl v17.2d, v17.2s | |
| ; CHECK-SD-NEXT: fcvtzs v7.2d, v7.2d | |
| ; CHECK-SD-NEXT: fcvtl v18.2d, v18.2s | |
| ; CHECK-SD-NEXT: fcvtzs v6.2d, v6.2d | |
| ; CHECK-SD-NEXT: fcvtl v19.2d, v19.2s | |
| ; CHECK-SD-NEXT: frintx v1.2s, v1.2s | |
| ; CHECK-SD-NEXT: fcvtl v4.2d, v4.2s | |
| ; CHECK-SD-NEXT: fcvtl v3.2d, v3.2s | |
| ; CHECK-SD-NEXT: fcvtzs v5.2d, v5.2d | |
| ; CHECK-SD-NEXT: frintx v0.2s, v0.2s | |
| ; CHECK-SD-NEXT: fcvtl v2.2d, v2.2s | |
| ; CHECK-SD-NEXT: fcvtzs v16.2d, v16.2d | |
| ; CHECK-SD-NEXT: fcvtzs v17.2d, v17.2d | |
| ; CHECK-SD-NEXT: fcvtzs v4.2d, v4.2d | |
| ; CHECK-SD-NEXT: fcvtl v1.2d, v1.2s | |
| ; CHECK-SD-NEXT: fcvtzs v3.2d, v3.2d | |
| ; CHECK-SD-NEXT: fcvtl v0.2d, v0.2s | |
| ; CHECK-SD-NEXT: fcvtzs v2.2d, v2.2d | |
| ; CHECK-SD-NEXT: stp q6, q17, [x8, #192] | |
| ; CHECK-SD-NEXT: frintx v6.2s, v20.2s | |
| ; CHECK-SD-NEXT: fcvtl v17.2d, v23.2s | |
| ; CHECK-SD-NEXT: stp q7, q16, [x8, #224] | |
| ; CHECK-SD-NEXT: fcvtl v7.2d, v22.2s | |
| ; CHECK-SD-NEXT: fcvtzs v16.2d, v18.2d | |
| ; CHECK-SD-NEXT: fcvtzs v18.2d, v19.2d | |
| ; CHECK-SD-NEXT: fcvtzs v1.2d, v1.2d | |
| ; CHECK-SD-NEXT: fcvtzs v0.2d, v0.2d | |
| ; CHECK-SD-NEXT: fcvtl v6.2d, v6.2s | |
| ; CHECK-SD-NEXT: stp q5, q16, [x8, #160] | |
| ; CHECK-SD-NEXT: fcvtzs v7.2d, v7.2d | |
| ; CHECK-SD-NEXT: fcvtl v5.2d, v21.2s | |
| ; CHECK-SD-NEXT: stp q4, q18, [x8, #128] | |
| ; CHECK-SD-NEXT: fcvtzs v16.2d, v17.2d | |
| ; CHECK-SD-NEXT: fcvtzs v4.2d, v6.2d | |
| ; CHECK-SD-NEXT: stp q3, q7, [x8, #96] | |
| ; CHECK-SD-NEXT: fcvtzs v3.2d, v5.2d | |
| ; CHECK-SD-NEXT: stp q2, q16, [x8, #64] | |
| ; CHECK-SD-NEXT: stp q0, q4, [x8] | |
| ; CHECK-SD-NEXT: stp q3, q1, [x8, #32] | |
| ; CHECK-SD-NEXT: ret | |
| ; | |
| ; CHECK-GI-LABEL: llrint_v32i64_v32f32: | |
| ; CHECK-GI: // %bb.0: | |
| ; CHECK-GI-NEXT: frintx v0.4s, v0.4s | |
| ; CHECK-GI-NEXT: frintx v1.4s, v1.4s | |
| ; CHECK-GI-NEXT: frintx v2.4s, v2.4s | |
| ; CHECK-GI-NEXT: frintx v3.4s, v3.4s | |
| ; CHECK-GI-NEXT: frintx v4.4s, v4.4s | |
| ; CHECK-GI-NEXT: frintx v5.4s, v5.4s | |
| ; CHECK-GI-NEXT: frintx v6.4s, v6.4s | |
| ; CHECK-GI-NEXT: frintx v7.4s, v7.4s | |
| ; CHECK-GI-NEXT: fcvtl v16.2d, v0.2s | |
| ; CHECK-GI-NEXT: fcvtl2 v0.2d, v0.4s | |
| ; CHECK-GI-NEXT: fcvtl v17.2d, v1.2s | |
| ; CHECK-GI-NEXT: fcvtl2 v1.2d, v1.4s | |
| ; CHECK-GI-NEXT: fcvtl v18.2d, v2.2s | |
| ; CHECK-GI-NEXT: fcvtl2 v2.2d, v2.4s | |
| ; CHECK-GI-NEXT: fcvtl v19.2d, v3.2s | |
| ; CHECK-GI-NEXT: fcvtl2 v3.2d, v3.4s | |
| ; CHECK-GI-NEXT: fcvtl v20.2d, v4.2s | |
| ; CHECK-GI-NEXT: fcvtl2 v4.2d, v4.4s | |
| ; CHECK-GI-NEXT: fcvtzs v16.2d, v16.2d | |
| ; CHECK-GI-NEXT: fcvtzs v0.2d, v0.2d | |
| ; CHECK-GI-NEXT: fcvtzs v17.2d, v17.2d | |
| ; CHECK-GI-NEXT: fcvtzs v1.2d, v1.2d | |
| ; CHECK-GI-NEXT: fcvtzs v18.2d, v18.2d | |
| ; CHECK-GI-NEXT: fcvtzs v2.2d, v2.2d | |
| ; CHECK-GI-NEXT: fcvtzs v3.2d, v3.2d | |
| ; CHECK-GI-NEXT: fcvtzs v4.2d, v4.2d | |
| ; CHECK-GI-NEXT: stp q16, q0, [x8] | |
| ; CHECK-GI-NEXT: fcvtl v0.2d, v5.2s | |
| ; CHECK-GI-NEXT: fcvtzs v16.2d, v19.2d | |
| ; CHECK-GI-NEXT: stp q17, q1, [x8, #32] | |
| ; CHECK-GI-NEXT: fcvtl2 v5.2d, v5.4s | |
| ; CHECK-GI-NEXT: fcvtl v1.2d, v6.2s | |
| ; CHECK-GI-NEXT: stp q18, q2, [x8, #64] | |
| ; CHECK-GI-NEXT: fcvtzs v17.2d, v20.2d | |
| ; CHECK-GI-NEXT: fcvtl2 v2.2d, v6.4s | |
| ; CHECK-GI-NEXT: fcvtl v6.2d, v7.2s | |
| ; CHECK-GI-NEXT: fcvtzs v0.2d, v0.2d | |
| ; CHECK-GI-NEXT: stp q16, q3, [x8, #96] | |
| ; CHECK-GI-NEXT: fcvtl2 v3.2d, v7.4s | |
| ; CHECK-GI-NEXT: fcvtzs v5.2d, v5.2d | |
| ; CHECK-GI-NEXT: fcvtzs v1.2d, v1.2d | |
| ; CHECK-GI-NEXT: stp q17, q4, [x8, #128] | |
| ; CHECK-GI-NEXT: fcvtzs v2.2d, v2.2d | |
| ; CHECK-GI-NEXT: fcvtzs v4.2d, v6.2d | |
| ; CHECK-GI-NEXT: stp q0, q5, [x8, #160] | |
| ; CHECK-GI-NEXT: fcvtzs v0.2d, v3.2d | |
| ; CHECK-GI-NEXT: stp q1, q2, [x8, #192] | |
| ; CHECK-GI-NEXT: stp q4, q0, [x8, #224] | |
| ; CHECK-GI-NEXT: ret | |
| %a = call <32 x i64> @llvm.llrint.v32i64.v32f32(<32 x float> %x) | |
| ret <32 x i64> %a | |
| } | |
| declare <32 x i64> @llvm.llrint.v32i64.v32f32(<32 x float>) | |
| define <1 x i64> @llrint_v1i64_v1f64(<1 x double> %x) nounwind { | |
| ; CHECK-LABEL: llrint_v1i64_v1f64: | |
| ; CHECK: // %bb.0: | |
| ; CHECK-NEXT: frintx d0, d0 | |
| ; CHECK-NEXT: fcvtzs d0, d0 | |
| ; CHECK-NEXT: ret | |
| %a = call <1 x i64> @llvm.llrint.v1i64.v1f64(<1 x double> %x) | |
| ret <1 x i64> %a | |
| } | |
| declare <1 x i64> @llvm.llrint.v1i64.v1f64(<1 x double>) | |
| define <2 x i64> @llrint_v2i64_v2f64(<2 x double> %x) nounwind { | |
| ; CHECK-LABEL: llrint_v2i64_v2f64: | |
| ; CHECK: // %bb.0: | |
| ; CHECK-NEXT: frintx v0.2d, v0.2d | |
| ; CHECK-NEXT: fcvtzs v0.2d, v0.2d | |
| ; CHECK-NEXT: ret | |
| %a = call <2 x i64> @llvm.llrint.v2i64.v2f64(<2 x double> %x) | |
| ret <2 x i64> %a | |
| } | |
| declare <2 x i64> @llvm.llrint.v2i64.v2f64(<2 x double>) | |
| define <4 x i64> @llrint_v4i64_v4f64(<4 x double> %x) nounwind { | |
| ; CHECK-LABEL: llrint_v4i64_v4f64: | |
| ; CHECK: // %bb.0: | |
| ; CHECK-NEXT: frintx v0.2d, v0.2d | |
| ; CHECK-NEXT: frintx v1.2d, v1.2d | |
| ; CHECK-NEXT: fcvtzs v0.2d, v0.2d | |
| ; CHECK-NEXT: fcvtzs v1.2d, v1.2d | |
| ; CHECK-NEXT: ret | |
| %a = call <4 x i64> @llvm.llrint.v4i64.v4f64(<4 x double> %x) | |
| ret <4 x i64> %a | |
| } | |
| declare <4 x i64> @llvm.llrint.v4i64.v4f64(<4 x double>) | |
| define <8 x i64> @llrint_v8i64_v8f64(<8 x double> %x) nounwind { | |
| ; CHECK-LABEL: llrint_v8i64_v8f64: | |
| ; CHECK: // %bb.0: | |
| ; CHECK-NEXT: frintx v0.2d, v0.2d | |
| ; CHECK-NEXT: frintx v1.2d, v1.2d | |
| ; CHECK-NEXT: frintx v2.2d, v2.2d | |
| ; CHECK-NEXT: frintx v3.2d, v3.2d | |
| ; CHECK-NEXT: fcvtzs v0.2d, v0.2d | |
| ; CHECK-NEXT: fcvtzs v1.2d, v1.2d | |
| ; CHECK-NEXT: fcvtzs v2.2d, v2.2d | |
| ; CHECK-NEXT: fcvtzs v3.2d, v3.2d | |
| ; CHECK-NEXT: ret | |
| %a = call <8 x i64> @llvm.llrint.v8i64.v8f64(<8 x double> %x) | |
| ret <8 x i64> %a | |
| } | |
| declare <8 x i64> @llvm.llrint.v8i64.v8f64(<8 x double>) | |
| define <16 x i64> @llrint_v16f64(<16 x double> %x) nounwind { | |
| ; CHECK-LABEL: llrint_v16f64: | |
| ; CHECK: // %bb.0: | |
| ; CHECK-NEXT: frintx v0.2d, v0.2d | |
| ; CHECK-NEXT: frintx v1.2d, v1.2d | |
| ; CHECK-NEXT: frintx v2.2d, v2.2d | |
| ; CHECK-NEXT: frintx v3.2d, v3.2d | |
| ; CHECK-NEXT: frintx v4.2d, v4.2d | |
| ; CHECK-NEXT: frintx v5.2d, v5.2d | |
| ; CHECK-NEXT: frintx v6.2d, v6.2d | |
| ; CHECK-NEXT: frintx v7.2d, v7.2d | |
| ; CHECK-NEXT: fcvtzs v0.2d, v0.2d | |
| ; CHECK-NEXT: fcvtzs v1.2d, v1.2d | |
| ; CHECK-NEXT: fcvtzs v2.2d, v2.2d | |
| ; CHECK-NEXT: fcvtzs v3.2d, v3.2d | |
| ; CHECK-NEXT: fcvtzs v4.2d, v4.2d | |
| ; CHECK-NEXT: fcvtzs v5.2d, v5.2d | |
| ; CHECK-NEXT: fcvtzs v6.2d, v6.2d | |
| ; CHECK-NEXT: fcvtzs v7.2d, v7.2d | |
| ; CHECK-NEXT: ret | |
| %a = call <16 x i64> @llvm.llrint.v16i64.v16f64(<16 x double> %x) | |
| ret <16 x i64> %a | |
| } | |
| declare <16 x i64> @llvm.llrint.v16i64.v16f64(<16 x double>) | |
| define <32 x i64> @llrint_v32f64(<32 x double> %x) nounwind { | |
| ; CHECK-SD-LABEL: llrint_v32f64: | |
| ; CHECK-SD: // %bb.0: | |
| ; CHECK-SD-NEXT: ldp q17, q16, [sp, #96] | |
| ; CHECK-SD-NEXT: frintx v7.2d, v7.2d | |
| ; CHECK-SD-NEXT: ldp q19, q18, [sp, #64] | |
| ; CHECK-SD-NEXT: frintx v6.2d, v6.2d | |
| ; CHECK-SD-NEXT: ldp q21, q20, [sp, #32] | |
| ; CHECK-SD-NEXT: frintx v5.2d, v5.2d | |
| ; CHECK-SD-NEXT: frintx v16.2d, v16.2d | |
| ; CHECK-SD-NEXT: frintx v17.2d, v17.2d | |
| ; CHECK-SD-NEXT: frintx v4.2d, v4.2d | |
| ; CHECK-SD-NEXT: frintx v18.2d, v18.2d | |
| ; CHECK-SD-NEXT: frintx v19.2d, v19.2d | |
| ; CHECK-SD-NEXT: frintx v3.2d, v3.2d | |
| ; CHECK-SD-NEXT: ldp q23, q22, [sp] | |
| ; CHECK-SD-NEXT: frintx v20.2d, v20.2d | |
| ; CHECK-SD-NEXT: frintx v21.2d, v21.2d | |
| ; CHECK-SD-NEXT: frintx v2.2d, v2.2d | |
| ; CHECK-SD-NEXT: frintx v1.2d, v1.2d | |
| ; CHECK-SD-NEXT: fcvtzs v16.2d, v16.2d | |
| ; CHECK-SD-NEXT: fcvtzs v17.2d, v17.2d | |
| ; CHECK-SD-NEXT: frintx v0.2d, v0.2d | |
| ; CHECK-SD-NEXT: frintx v22.2d, v22.2d | |
| ; CHECK-SD-NEXT: fcvtzs v18.2d, v18.2d | |
| ; CHECK-SD-NEXT: frintx v23.2d, v23.2d | |
| ; CHECK-SD-NEXT: fcvtzs v19.2d, v19.2d | |
| ; CHECK-SD-NEXT: fcvtzs v20.2d, v20.2d | |
| ; CHECK-SD-NEXT: fcvtzs v7.2d, v7.2d | |
| ; CHECK-SD-NEXT: fcvtzs v6.2d, v6.2d | |
| ; CHECK-SD-NEXT: fcvtzs v5.2d, v5.2d | |
| ; CHECK-SD-NEXT: fcvtzs v4.2d, v4.2d | |
| ; CHECK-SD-NEXT: stp q17, q16, [x8, #224] | |
| ; CHECK-SD-NEXT: fcvtzs v16.2d, v21.2d | |
| ; CHECK-SD-NEXT: fcvtzs v3.2d, v3.2d | |
| ; CHECK-SD-NEXT: fcvtzs v17.2d, v22.2d | |
| ; CHECK-SD-NEXT: fcvtzs v2.2d, v2.2d | |
| ; CHECK-SD-NEXT: fcvtzs v1.2d, v1.2d | |
| ; CHECK-SD-NEXT: stp q19, q18, [x8, #192] | |
| ; CHECK-SD-NEXT: fcvtzs v18.2d, v23.2d | |
| ; CHECK-SD-NEXT: fcvtzs v0.2d, v0.2d | |
| ; CHECK-SD-NEXT: stp q4, q5, [x8, #64] | |
| ; CHECK-SD-NEXT: stp q6, q7, [x8, #96] | |
| ; CHECK-SD-NEXT: stp q2, q3, [x8, #32] | |
| ; CHECK-SD-NEXT: stp q0, q1, [x8] | |
| ; CHECK-SD-NEXT: stp q18, q17, [x8, #128] | |
| ; CHECK-SD-NEXT: stp q16, q20, [x8, #160] | |
| ; CHECK-SD-NEXT: ret | |
| ; | |
| ; CHECK-GI-LABEL: llrint_v32f64: | |
| ; CHECK-GI: // %bb.0: | |
| ; CHECK-GI-NEXT: frintx v0.2d, v0.2d | |
| ; CHECK-GI-NEXT: frintx v1.2d, v1.2d | |
| ; CHECK-GI-NEXT: frintx v2.2d, v2.2d | |
| ; CHECK-GI-NEXT: frintx v3.2d, v3.2d | |
| ; CHECK-GI-NEXT: ldp q16, q17, [sp] | |
| ; CHECK-GI-NEXT: frintx v4.2d, v4.2d | |
| ; CHECK-GI-NEXT: frintx v5.2d, v5.2d | |
| ; CHECK-GI-NEXT: frintx v6.2d, v6.2d | |
| ; CHECK-GI-NEXT: frintx v7.2d, v7.2d | |
| ; CHECK-GI-NEXT: ldp q18, q19, [sp, #32] | |
| ; CHECK-GI-NEXT: fcvtzs v0.2d, v0.2d | |
| ; CHECK-GI-NEXT: fcvtzs v1.2d, v1.2d | |
| ; CHECK-GI-NEXT: fcvtzs v2.2d, v2.2d | |
| ; CHECK-GI-NEXT: fcvtzs v3.2d, v3.2d | |
| ; CHECK-GI-NEXT: ldp q20, q21, [sp, #64] | |
| ; CHECK-GI-NEXT: frintx v16.2d, v16.2d | |
| ; CHECK-GI-NEXT: fcvtzs v4.2d, v4.2d | |
| ; CHECK-GI-NEXT: fcvtzs v5.2d, v5.2d | |
| ; CHECK-GI-NEXT: fcvtzs v6.2d, v6.2d | |
| ; CHECK-GI-NEXT: ldp q22, q23, [sp, #96] | |
| ; CHECK-GI-NEXT: stp q0, q1, [x8] | |
| ; CHECK-GI-NEXT: frintx v0.2d, v17.2d | |
| ; CHECK-GI-NEXT: frintx v1.2d, v18.2d | |
| ; CHECK-GI-NEXT: stp q2, q3, [x8, #32] | |
| ; CHECK-GI-NEXT: frintx v2.2d, v19.2d | |
| ; CHECK-GI-NEXT: fcvtzs v7.2d, v7.2d | |
| ; CHECK-GI-NEXT: frintx v3.2d, v20.2d | |
| ; CHECK-GI-NEXT: fcvtzs v16.2d, v16.2d | |
| ; CHECK-GI-NEXT: stp q4, q5, [x8, #64] | |
| ; CHECK-GI-NEXT: frintx v4.2d, v21.2d | |
| ; CHECK-GI-NEXT: frintx v5.2d, v22.2d | |
| ; CHECK-GI-NEXT: fcvtzs v0.2d, v0.2d | |
| ; CHECK-GI-NEXT: fcvtzs v1.2d, v1.2d | |
| ; CHECK-GI-NEXT: stp q6, q7, [x8, #96] | |
| ; CHECK-GI-NEXT: frintx v6.2d, v23.2d | |
| ; CHECK-GI-NEXT: fcvtzs v2.2d, v2.2d | |
| ; CHECK-GI-NEXT: fcvtzs v3.2d, v3.2d | |
| ; CHECK-GI-NEXT: fcvtzs v4.2d, v4.2d | |
| ; CHECK-GI-NEXT: stp q16, q0, [x8, #128] | |
| ; CHECK-GI-NEXT: fcvtzs v0.2d, v5.2d | |
| ; CHECK-GI-NEXT: stp q1, q2, [x8, #160] | |
| ; CHECK-GI-NEXT: fcvtzs v1.2d, v6.2d | |
| ; CHECK-GI-NEXT: stp q3, q4, [x8, #192] | |
| ; CHECK-GI-NEXT: stp q0, q1, [x8, #224] | |
| ; CHECK-GI-NEXT: ret | |
| %a = call <32 x i64> @llvm.llrint.v32i64.v16f64(<32 x double> %x) | |
| ret <32 x i64> %a | |
| } | |
| declare <32 x i64> @llvm.llrint.v32i64.v32f64(<32 x double>) | |
| define <1 x i64> @llrint_v1i64_v1f128(<1 x fp128> %x) nounwind { | |
| ; CHECK-LABEL: llrint_v1i64_v1f128: | |
| ; CHECK: // %bb.0: | |
| ; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill | |
| ; CHECK-NEXT: bl llrintl | |
| ; CHECK-NEXT: fmov d0, x0 | |
| ; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload | |
| ; CHECK-NEXT: ret | |
| %a = call <1 x i64> @llvm.llrint.v1i64.v1f128(<1 x fp128> %x) | |
| ret <1 x i64> %a | |
| } | |
| declare <1 x i64> @llvm.llrint.v1i64.v1f128(<1 x fp128>) | |
| define <2 x i64> @llrint_v2i64_v2f128(<2 x fp128> %x) nounwind { | |
| ; CHECK-SD-LABEL: llrint_v2i64_v2f128: | |
| ; CHECK-SD: // %bb.0: | |
| ; CHECK-SD-NEXT: sub sp, sp, #48 | |
| ; CHECK-SD-NEXT: str q0, [sp] // 16-byte Spill | |
| ; CHECK-SD-NEXT: mov v0.16b, v1.16b | |
| ; CHECK-SD-NEXT: str x30, [sp, #32] // 8-byte Spill | |
| ; CHECK-SD-NEXT: bl llrintl | |
| ; CHECK-SD-NEXT: fmov d0, x0 | |
| ; CHECK-SD-NEXT: str q0, [sp, #16] // 16-byte Spill | |
| ; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Reload | |
| ; CHECK-SD-NEXT: bl llrintl | |
| ; CHECK-SD-NEXT: fmov d0, x0 | |
| ; CHECK-SD-NEXT: ldr q1, [sp, #16] // 16-byte Reload | |
| ; CHECK-SD-NEXT: ldr x30, [sp, #32] // 8-byte Reload | |
| ; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] | |
| ; CHECK-SD-NEXT: add sp, sp, #48 | |
| ; CHECK-SD-NEXT: ret | |
| ; | |
| ; CHECK-GI-LABEL: llrint_v2i64_v2f128: | |
| ; CHECK-GI: // %bb.0: | |
| ; CHECK-GI-NEXT: sub sp, sp, #48 | |
| ; CHECK-GI-NEXT: stp x30, x19, [sp, #32] // 16-byte Folded Spill | |
| ; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill | |
| ; CHECK-GI-NEXT: bl rintl | |
| ; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload | |
| ; CHECK-GI-NEXT: bl rintl | |
| ; CHECK-GI-NEXT: str q0, [sp, #16] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload | |
| ; CHECK-GI-NEXT: bl __fixtfdi | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload | |
| ; CHECK-GI-NEXT: mov x19, x0 | |
| ; CHECK-GI-NEXT: bl __fixtfdi | |
| ; CHECK-GI-NEXT: fmov d0, x19 | |
| ; CHECK-GI-NEXT: ldp x30, x19, [sp, #32] // 16-byte Folded Reload | |
| ; CHECK-GI-NEXT: mov v0.d[1], x0 | |
| ; CHECK-GI-NEXT: add sp, sp, #48 | |
| ; CHECK-GI-NEXT: ret | |
| %a = call <2 x i64> @llvm.llrint.v2i64.v2f128(<2 x fp128> %x) | |
| ret <2 x i64> %a | |
| } | |
| declare <2 x i64> @llvm.llrint.v2i64.v2f128(<2 x fp128>) | |
| define <4 x i64> @llrint_v4i64_v4f128(<4 x fp128> %x) nounwind { | |
| ; CHECK-SD-LABEL: llrint_v4i64_v4f128: | |
| ; CHECK-SD: // %bb.0: | |
| ; CHECK-SD-NEXT: sub sp, sp, #80 | |
| ; CHECK-SD-NEXT: str q0, [sp] // 16-byte Spill | |
| ; CHECK-SD-NEXT: mov v0.16b, v1.16b | |
| ; CHECK-SD-NEXT: str x30, [sp, #64] // 8-byte Spill | |
| ; CHECK-SD-NEXT: stp q3, q2, [sp, #32] // 32-byte Folded Spill | |
| ; CHECK-SD-NEXT: bl llrintl | |
| ; CHECK-SD-NEXT: fmov d0, x0 | |
| ; CHECK-SD-NEXT: str q0, [sp, #16] // 16-byte Spill | |
| ; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Reload | |
| ; CHECK-SD-NEXT: bl llrintl | |
| ; CHECK-SD-NEXT: fmov d0, x0 | |
| ; CHECK-SD-NEXT: ldr q1, [sp, #16] // 16-byte Reload | |
| ; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] | |
| ; CHECK-SD-NEXT: str q0, [sp, #16] // 16-byte Spill | |
| ; CHECK-SD-NEXT: ldr q0, [sp, #32] // 16-byte Reload | |
| ; CHECK-SD-NEXT: bl llrintl | |
| ; CHECK-SD-NEXT: fmov d0, x0 | |
| ; CHECK-SD-NEXT: str q0, [sp, #32] // 16-byte Spill | |
| ; CHECK-SD-NEXT: ldr q0, [sp, #48] // 16-byte Reload | |
| ; CHECK-SD-NEXT: bl llrintl | |
| ; CHECK-SD-NEXT: fmov d1, x0 | |
| ; CHECK-SD-NEXT: ldp q0, q4, [sp, #16] // 32-byte Folded Reload | |
| ; CHECK-SD-NEXT: ldr x30, [sp, #64] // 8-byte Reload | |
| ; CHECK-SD-NEXT: mov v1.d[1], v4.d[0] | |
| ; CHECK-SD-NEXT: add sp, sp, #80 | |
| ; CHECK-SD-NEXT: ret | |
| ; | |
| ; CHECK-GI-LABEL: llrint_v4i64_v4f128: | |
| ; CHECK-GI: // %bb.0: | |
| ; CHECK-GI-NEXT: sub sp, sp, #96 | |
| ; CHECK-GI-NEXT: stp x30, x21, [sp, #64] // 16-byte Folded Spill | |
| ; CHECK-GI-NEXT: stp x20, x19, [sp, #80] // 16-byte Folded Spill | |
| ; CHECK-GI-NEXT: stp q2, q1, [sp] // 32-byte Folded Spill | |
| ; CHECK-GI-NEXT: str q3, [sp, #48] // 16-byte Spill | |
| ; CHECK-GI-NEXT: bl rintl | |
| ; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload | |
| ; CHECK-GI-NEXT: bl rintl | |
| ; CHECK-GI-NEXT: str q0, [sp, #16] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload | |
| ; CHECK-GI-NEXT: bl rintl | |
| ; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload | |
| ; CHECK-GI-NEXT: bl rintl | |
| ; CHECK-GI-NEXT: str q0, [sp, #48] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload | |
| ; CHECK-GI-NEXT: bl __fixtfdi | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload | |
| ; CHECK-GI-NEXT: mov x19, x0 | |
| ; CHECK-GI-NEXT: bl __fixtfdi | |
| ; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload | |
| ; CHECK-GI-NEXT: mov x20, x0 | |
| ; CHECK-GI-NEXT: bl __fixtfdi | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload | |
| ; CHECK-GI-NEXT: mov x21, x0 | |
| ; CHECK-GI-NEXT: bl __fixtfdi | |
| ; CHECK-GI-NEXT: fmov d0, x19 | |
| ; CHECK-GI-NEXT: fmov d1, x21 | |
| ; CHECK-GI-NEXT: ldp x30, x21, [sp, #64] // 16-byte Folded Reload | |
| ; CHECK-GI-NEXT: mov v0.d[1], x20 | |
| ; CHECK-GI-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload | |
| ; CHECK-GI-NEXT: mov v1.d[1], x0 | |
| ; CHECK-GI-NEXT: add sp, sp, #96 | |
| ; CHECK-GI-NEXT: ret | |
| %a = call <4 x i64> @llvm.llrint.v4i64.v4f128(<4 x fp128> %x) | |
| ret <4 x i64> %a | |
| } | |
| declare <4 x i64> @llvm.llrint.v4i64.v4f128(<4 x fp128>) | |
| define <8 x i64> @llrint_v8i64_v8f128(<8 x fp128> %x) nounwind { | |
| ; CHECK-SD-LABEL: llrint_v8i64_v8f128: | |
| ; CHECK-SD: // %bb.0: | |
| ; CHECK-SD-NEXT: sub sp, sp, #144 | |
| ; CHECK-SD-NEXT: str q0, [sp] // 16-byte Spill | |
| ; CHECK-SD-NEXT: mov v0.16b, v1.16b | |
| ; CHECK-SD-NEXT: str x30, [sp, #128] // 8-byte Spill | |
| ; CHECK-SD-NEXT: stp q3, q2, [sp, #16] // 32-byte Folded Spill | |
| ; CHECK-SD-NEXT: stp q5, q4, [sp, #48] // 32-byte Folded Spill | |
| ; CHECK-SD-NEXT: stp q7, q6, [sp, #96] // 32-byte Folded Spill | |
| ; CHECK-SD-NEXT: bl llrintl | |
| ; CHECK-SD-NEXT: fmov d0, x0 | |
| ; CHECK-SD-NEXT: str q0, [sp, #80] // 16-byte Spill | |
| ; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Reload | |
| ; CHECK-SD-NEXT: bl llrintl | |
| ; CHECK-SD-NEXT: fmov d0, x0 | |
| ; CHECK-SD-NEXT: ldr q1, [sp, #80] // 16-byte Reload | |
| ; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] | |
| ; CHECK-SD-NEXT: str q0, [sp, #80] // 16-byte Spill | |
| ; CHECK-SD-NEXT: ldr q0, [sp, #16] // 16-byte Reload | |
| ; CHECK-SD-NEXT: bl llrintl | |
| ; CHECK-SD-NEXT: fmov d0, x0 | |
| ; CHECK-SD-NEXT: str q0, [sp, #16] // 16-byte Spill | |
| ; CHECK-SD-NEXT: ldr q0, [sp, #32] // 16-byte Reload | |
| ; CHECK-SD-NEXT: bl llrintl | |
| ; CHECK-SD-NEXT: fmov d0, x0 | |
| ; CHECK-SD-NEXT: ldr q1, [sp, #16] // 16-byte Reload | |
| ; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] | |
| ; CHECK-SD-NEXT: str q0, [sp, #32] // 16-byte Spill | |
| ; CHECK-SD-NEXT: ldr q0, [sp, #48] // 16-byte Reload | |
| ; CHECK-SD-NEXT: bl llrintl | |
| ; CHECK-SD-NEXT: fmov d0, x0 | |
| ; CHECK-SD-NEXT: str q0, [sp, #48] // 16-byte Spill | |
| ; CHECK-SD-NEXT: ldr q0, [sp, #64] // 16-byte Reload | |
| ; CHECK-SD-NEXT: bl llrintl | |
| ; CHECK-SD-NEXT: fmov d0, x0 | |
| ; CHECK-SD-NEXT: ldr q1, [sp, #48] // 16-byte Reload | |
| ; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] | |
| ; CHECK-SD-NEXT: str q0, [sp, #64] // 16-byte Spill | |
| ; CHECK-SD-NEXT: ldr q0, [sp, #96] // 16-byte Reload | |
| ; CHECK-SD-NEXT: bl llrintl | |
| ; CHECK-SD-NEXT: fmov d0, x0 | |
| ; CHECK-SD-NEXT: str q0, [sp, #96] // 16-byte Spill | |
| ; CHECK-SD-NEXT: ldr q0, [sp, #112] // 16-byte Reload | |
| ; CHECK-SD-NEXT: bl llrintl | |
| ; CHECK-SD-NEXT: fmov d3, x0 | |
| ; CHECK-SD-NEXT: ldp q0, q1, [sp, #80] // 32-byte Folded Reload | |
| ; CHECK-SD-NEXT: ldr q2, [sp, #64] // 16-byte Reload | |
| ; CHECK-SD-NEXT: ldr x30, [sp, #128] // 8-byte Reload | |
| ; CHECK-SD-NEXT: mov v3.d[1], v1.d[0] | |
| ; CHECK-SD-NEXT: ldr q1, [sp, #32] // 16-byte Reload | |
| ; CHECK-SD-NEXT: add sp, sp, #144 | |
| ; CHECK-SD-NEXT: ret | |
| ; | |
| ; CHECK-GI-LABEL: llrint_v8i64_v8f128: | |
| ; CHECK-GI: // %bb.0: | |
| ; CHECK-GI-NEXT: sub sp, sp, #192 | |
| ; CHECK-GI-NEXT: stp x30, x25, [sp, #128] // 16-byte Folded Spill | |
| ; CHECK-GI-NEXT: stp x24, x23, [sp, #144] // 16-byte Folded Spill | |
| ; CHECK-GI-NEXT: stp x22, x21, [sp, #160] // 16-byte Folded Spill | |
| ; CHECK-GI-NEXT: stp x20, x19, [sp, #176] // 16-byte Folded Spill | |
| ; CHECK-GI-NEXT: stp q6, q5, [sp] // 32-byte Folded Spill | |
| ; CHECK-GI-NEXT: stp q4, q3, [sp, #32] // 32-byte Folded Spill | |
| ; CHECK-GI-NEXT: stp q2, q1, [sp, #64] // 32-byte Folded Spill | |
| ; CHECK-GI-NEXT: str q7, [sp, #112] // 16-byte Spill | |
| ; CHECK-GI-NEXT: bl rintl | |
| ; CHECK-GI-NEXT: str q0, [sp, #96] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload | |
| ; CHECK-GI-NEXT: bl rintl | |
| ; CHECK-GI-NEXT: str q0, [sp, #80] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload | |
| ; CHECK-GI-NEXT: bl rintl | |
| ; CHECK-GI-NEXT: str q0, [sp, #64] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload | |
| ; CHECK-GI-NEXT: bl rintl | |
| ; CHECK-GI-NEXT: str q0, [sp, #48] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload | |
| ; CHECK-GI-NEXT: bl rintl | |
| ; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload | |
| ; CHECK-GI-NEXT: bl rintl | |
| ; CHECK-GI-NEXT: str q0, [sp, #16] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload | |
| ; CHECK-GI-NEXT: bl rintl | |
| ; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #112] // 16-byte Reload | |
| ; CHECK-GI-NEXT: bl rintl | |
| ; CHECK-GI-NEXT: str q0, [sp, #112] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #96] // 16-byte Reload | |
| ; CHECK-GI-NEXT: bl __fixtfdi | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload | |
| ; CHECK-GI-NEXT: mov x19, x0 | |
| ; CHECK-GI-NEXT: bl __fixtfdi | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload | |
| ; CHECK-GI-NEXT: mov x20, x0 | |
| ; CHECK-GI-NEXT: bl __fixtfdi | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload | |
| ; CHECK-GI-NEXT: mov x21, x0 | |
| ; CHECK-GI-NEXT: bl __fixtfdi | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload | |
| ; CHECK-GI-NEXT: mov x22, x0 | |
| ; CHECK-GI-NEXT: bl __fixtfdi | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload | |
| ; CHECK-GI-NEXT: mov x23, x0 | |
| ; CHECK-GI-NEXT: bl __fixtfdi | |
| ; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload | |
| ; CHECK-GI-NEXT: mov x24, x0 | |
| ; CHECK-GI-NEXT: bl __fixtfdi | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #112] // 16-byte Reload | |
| ; CHECK-GI-NEXT: mov x25, x0 | |
| ; CHECK-GI-NEXT: bl __fixtfdi | |
| ; CHECK-GI-NEXT: fmov d0, x19 | |
| ; CHECK-GI-NEXT: fmov d1, x21 | |
| ; CHECK-GI-NEXT: fmov d2, x23 | |
| ; CHECK-GI-NEXT: fmov d3, x25 | |
| ; CHECK-GI-NEXT: ldp x30, x25, [sp, #128] // 16-byte Folded Reload | |
| ; CHECK-GI-NEXT: mov v0.d[1], x20 | |
| ; CHECK-GI-NEXT: mov v1.d[1], x22 | |
| ; CHECK-GI-NEXT: mov v2.d[1], x24 | |
| ; CHECK-GI-NEXT: ldp x20, x19, [sp, #176] // 16-byte Folded Reload | |
| ; CHECK-GI-NEXT: mov v3.d[1], x0 | |
| ; CHECK-GI-NEXT: ldp x22, x21, [sp, #160] // 16-byte Folded Reload | |
| ; CHECK-GI-NEXT: ldp x24, x23, [sp, #144] // 16-byte Folded Reload | |
| ; CHECK-GI-NEXT: add sp, sp, #192 | |
| ; CHECK-GI-NEXT: ret | |
| %a = call <8 x i64> @llvm.llrint.v8i64.v8f128(<8 x fp128> %x) | |
| ret <8 x i64> %a | |
| } | |
| declare <8 x i64> @llvm.llrint.v8i64.v8f128(<8 x fp128>) | |
| define <16 x i64> @llrint_v16f128(<16 x fp128> %x) nounwind { | |
| ; CHECK-SD-LABEL: llrint_v16f128: | |
| ; CHECK-SD: // %bb.0: | |
| ; CHECK-SD-NEXT: sub sp, sp, #272 | |
| ; CHECK-SD-NEXT: str q2, [sp, #160] // 16-byte Spill | |
| ; CHECK-SD-NEXT: ldr q2, [sp, #368] | |
| ; CHECK-SD-NEXT: stp q0, q3, [sp] // 32-byte Folded Spill | |
| ; CHECK-SD-NEXT: mov v0.16b, v1.16b | |
| ; CHECK-SD-NEXT: str q2, [sp, #240] // 16-byte Spill | |
| ; CHECK-SD-NEXT: ldr q2, [sp, #384] | |
| ; CHECK-SD-NEXT: stp x29, x30, [sp, #256] // 16-byte Folded Spill | |
| ; CHECK-SD-NEXT: str q2, [sp, #224] // 16-byte Spill | |
| ; CHECK-SD-NEXT: ldr q2, [sp, #336] | |
| ; CHECK-SD-NEXT: stp q5, q7, [sp, #32] // 32-byte Folded Spill | |
| ; CHECK-SD-NEXT: str q2, [sp, #192] // 16-byte Spill | |
| ; CHECK-SD-NEXT: ldr q2, [sp, #352] | |
| ; CHECK-SD-NEXT: str q2, [sp, #176] // 16-byte Spill | |
| ; CHECK-SD-NEXT: ldr q2, [sp, #304] | |
| ; CHECK-SD-NEXT: str q2, [sp, #144] // 16-byte Spill | |
| ; CHECK-SD-NEXT: ldr q2, [sp, #320] | |
| ; CHECK-SD-NEXT: stp q4, q2, [sp, #112] // 32-byte Folded Spill | |
| ; CHECK-SD-NEXT: ldr q2, [sp, #272] | |
| ; CHECK-SD-NEXT: stp q6, q2, [sp, #80] // 32-byte Folded Spill | |
| ; CHECK-SD-NEXT: ldr q2, [sp, #288] | |
| ; CHECK-SD-NEXT: str q2, [sp, #64] // 16-byte Spill | |
| ; CHECK-SD-NEXT: bl llrintl | |
| ; CHECK-SD-NEXT: fmov d0, x0 | |
| ; CHECK-SD-NEXT: str q0, [sp, #208] // 16-byte Spill | |
| ; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Reload | |
| ; CHECK-SD-NEXT: bl llrintl | |
| ; CHECK-SD-NEXT: fmov d0, x0 | |
| ; CHECK-SD-NEXT: ldr q1, [sp, #208] // 16-byte Reload | |
| ; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] | |
| ; CHECK-SD-NEXT: str q0, [sp, #208] // 16-byte Spill | |
| ; CHECK-SD-NEXT: ldr q0, [sp, #16] // 16-byte Reload | |
| ; CHECK-SD-NEXT: bl llrintl | |
| ; CHECK-SD-NEXT: fmov d0, x0 | |
| ; CHECK-SD-NEXT: str q0, [sp, #16] // 16-byte Spill | |
| ; CHECK-SD-NEXT: ldr q0, [sp, #160] // 16-byte Reload | |
| ; CHECK-SD-NEXT: bl llrintl | |
| ; CHECK-SD-NEXT: fmov d0, x0 | |
| ; CHECK-SD-NEXT: ldr q1, [sp, #16] // 16-byte Reload | |
| ; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] | |
| ; CHECK-SD-NEXT: str q0, [sp, #160] // 16-byte Spill | |
| ; CHECK-SD-NEXT: ldr q0, [sp, #32] // 16-byte Reload | |
| ; CHECK-SD-NEXT: bl llrintl | |
| ; CHECK-SD-NEXT: fmov d0, x0 | |
| ; CHECK-SD-NEXT: str q0, [sp, #32] // 16-byte Spill | |
| ; CHECK-SD-NEXT: ldr q0, [sp, #112] // 16-byte Reload | |
| ; CHECK-SD-NEXT: bl llrintl | |
| ; CHECK-SD-NEXT: fmov d0, x0 | |
| ; CHECK-SD-NEXT: ldr q1, [sp, #32] // 16-byte Reload | |
| ; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] | |
| ; CHECK-SD-NEXT: str q0, [sp, #112] // 16-byte Spill | |
| ; CHECK-SD-NEXT: ldr q0, [sp, #48] // 16-byte Reload | |
| ; CHECK-SD-NEXT: bl llrintl | |
| ; CHECK-SD-NEXT: fmov d0, x0 | |
| ; CHECK-SD-NEXT: str q0, [sp, #48] // 16-byte Spill | |
| ; CHECK-SD-NEXT: ldr q0, [sp, #80] // 16-byte Reload | |
| ; CHECK-SD-NEXT: bl llrintl | |
| ; CHECK-SD-NEXT: fmov d0, x0 | |
| ; CHECK-SD-NEXT: ldr q1, [sp, #48] // 16-byte Reload | |
| ; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] | |
| ; CHECK-SD-NEXT: str q0, [sp, #80] // 16-byte Spill | |
| ; CHECK-SD-NEXT: ldr q0, [sp, #64] // 16-byte Reload | |
| ; CHECK-SD-NEXT: bl llrintl | |
| ; CHECK-SD-NEXT: fmov d0, x0 | |
| ; CHECK-SD-NEXT: str q0, [sp, #64] // 16-byte Spill | |
| ; CHECK-SD-NEXT: ldr q0, [sp, #96] // 16-byte Reload | |
| ; CHECK-SD-NEXT: bl llrintl | |
| ; CHECK-SD-NEXT: fmov d0, x0 | |
| ; CHECK-SD-NEXT: ldr q1, [sp, #64] // 16-byte Reload | |
| ; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] | |
| ; CHECK-SD-NEXT: str q0, [sp, #96] // 16-byte Spill | |
| ; CHECK-SD-NEXT: ldr q0, [sp, #128] // 16-byte Reload | |
| ; CHECK-SD-NEXT: bl llrintl | |
| ; CHECK-SD-NEXT: fmov d0, x0 | |
| ; CHECK-SD-NEXT: str q0, [sp, #128] // 16-byte Spill | |
| ; CHECK-SD-NEXT: ldr q0, [sp, #144] // 16-byte Reload | |
| ; CHECK-SD-NEXT: bl llrintl | |
| ; CHECK-SD-NEXT: fmov d0, x0 | |
| ; CHECK-SD-NEXT: ldr q1, [sp, #128] // 16-byte Reload | |
| ; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] | |
| ; CHECK-SD-NEXT: str q0, [sp, #144] // 16-byte Spill | |
| ; CHECK-SD-NEXT: ldr q0, [sp, #176] // 16-byte Reload | |
| ; CHECK-SD-NEXT: bl llrintl | |
| ; CHECK-SD-NEXT: fmov d0, x0 | |
| ; CHECK-SD-NEXT: str q0, [sp, #176] // 16-byte Spill | |
| ; CHECK-SD-NEXT: ldr q0, [sp, #192] // 16-byte Reload | |
| ; CHECK-SD-NEXT: bl llrintl | |
| ; CHECK-SD-NEXT: fmov d0, x0 | |
| ; CHECK-SD-NEXT: ldr q1, [sp, #176] // 16-byte Reload | |
| ; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] | |
| ; CHECK-SD-NEXT: str q0, [sp, #192] // 16-byte Spill | |
| ; CHECK-SD-NEXT: ldr q0, [sp, #224] // 16-byte Reload | |
| ; CHECK-SD-NEXT: bl llrintl | |
| ; CHECK-SD-NEXT: fmov d0, x0 | |
| ; CHECK-SD-NEXT: str q0, [sp, #224] // 16-byte Spill | |
| ; CHECK-SD-NEXT: ldr q0, [sp, #240] // 16-byte Reload | |
| ; CHECK-SD-NEXT: bl llrintl | |
| ; CHECK-SD-NEXT: fmov d7, x0 | |
| ; CHECK-SD-NEXT: ldp q0, q1, [sp, #208] // 32-byte Folded Reload | |
| ; CHECK-SD-NEXT: ldp q4, q2, [sp, #96] // 32-byte Folded Reload | |
| ; CHECK-SD-NEXT: ldr q3, [sp, #80] // 16-byte Reload | |
| ; CHECK-SD-NEXT: ldp x29, x30, [sp, #256] // 16-byte Folded Reload | |
| ; CHECK-SD-NEXT: ldr q6, [sp, #192] // 16-byte Reload | |
| ; CHECK-SD-NEXT: mov v7.d[1], v1.d[0] | |
| ; CHECK-SD-NEXT: ldp q5, q1, [sp, #144] // 32-byte Folded Reload | |
| ; CHECK-SD-NEXT: add sp, sp, #272 | |
| ; CHECK-SD-NEXT: ret | |
| ; | |
| ; CHECK-GI-LABEL: llrint_v16f128: | |
| ; CHECK-GI: // %bb.0: | |
| ; CHECK-GI-NEXT: sub sp, sp, #384 | |
| ; CHECK-GI-NEXT: stp q6, q5, [sp, #160] // 32-byte Folded Spill | |
| ; CHECK-GI-NEXT: stp q4, q3, [sp, #192] // 32-byte Folded Spill | |
| ; CHECK-GI-NEXT: stp q2, q1, [sp, #224] // 32-byte Folded Spill | |
| ; CHECK-GI-NEXT: ldr q1, [sp, #384] | |
| ; CHECK-GI-NEXT: stp x29, x30, [sp, #288] // 16-byte Folded Spill | |
| ; CHECK-GI-NEXT: stp q1, q7, [sp, #128] // 32-byte Folded Spill | |
| ; CHECK-GI-NEXT: ldr q1, [sp, #400] | |
| ; CHECK-GI-NEXT: stp x28, x27, [sp, #304] // 16-byte Folded Spill | |
| ; CHECK-GI-NEXT: str q1, [sp, #112] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q1, [sp, #416] | |
| ; CHECK-GI-NEXT: stp x26, x25, [sp, #320] // 16-byte Folded Spill | |
| ; CHECK-GI-NEXT: str q1, [sp, #96] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q1, [sp, #432] | |
| ; CHECK-GI-NEXT: stp x24, x23, [sp, #336] // 16-byte Folded Spill | |
| ; CHECK-GI-NEXT: str q1, [sp, #80] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q1, [sp, #448] | |
| ; CHECK-GI-NEXT: stp x22, x21, [sp, #352] // 16-byte Folded Spill | |
| ; CHECK-GI-NEXT: str q1, [sp, #64] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q1, [sp, #464] | |
| ; CHECK-GI-NEXT: stp x20, x19, [sp, #368] // 16-byte Folded Spill | |
| ; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q1, [sp, #480] | |
| ; CHECK-GI-NEXT: str q1, [sp, #32] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q1, [sp, #496] | |
| ; CHECK-GI-NEXT: str q1, [sp, #272] // 16-byte Spill | |
| ; CHECK-GI-NEXT: bl rintl | |
| ; CHECK-GI-NEXT: str q0, [sp, #256] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #240] // 16-byte Reload | |
| ; CHECK-GI-NEXT: bl rintl | |
| ; CHECK-GI-NEXT: str q0, [sp, #240] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #224] // 16-byte Reload | |
| ; CHECK-GI-NEXT: bl rintl | |
| ; CHECK-GI-NEXT: str q0, [sp, #224] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #208] // 16-byte Reload | |
| ; CHECK-GI-NEXT: bl rintl | |
| ; CHECK-GI-NEXT: str q0, [sp, #208] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #192] // 16-byte Reload | |
| ; CHECK-GI-NEXT: bl rintl | |
| ; CHECK-GI-NEXT: str q0, [sp, #192] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #176] // 16-byte Reload | |
| ; CHECK-GI-NEXT: bl rintl | |
| ; CHECK-GI-NEXT: str q0, [sp, #176] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #160] // 16-byte Reload | |
| ; CHECK-GI-NEXT: bl rintl | |
| ; CHECK-GI-NEXT: str q0, [sp, #160] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #144] // 16-byte Reload | |
| ; CHECK-GI-NEXT: bl rintl | |
| ; CHECK-GI-NEXT: str q0, [sp, #144] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #128] // 16-byte Reload | |
| ; CHECK-GI-NEXT: bl rintl | |
| ; CHECK-GI-NEXT: str q0, [sp, #128] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #112] // 16-byte Reload | |
| ; CHECK-GI-NEXT: bl rintl | |
| ; CHECK-GI-NEXT: str q0, [sp, #112] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #96] // 16-byte Reload | |
| ; CHECK-GI-NEXT: bl rintl | |
| ; CHECK-GI-NEXT: str q0, [sp, #96] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload | |
| ; CHECK-GI-NEXT: bl rintl | |
| ; CHECK-GI-NEXT: str q0, [sp, #80] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload | |
| ; CHECK-GI-NEXT: bl rintl | |
| ; CHECK-GI-NEXT: str q0, [sp, #64] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload | |
| ; CHECK-GI-NEXT: bl rintl | |
| ; CHECK-GI-NEXT: str q0, [sp, #48] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload | |
| ; CHECK-GI-NEXT: bl rintl | |
| ; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #272] // 16-byte Reload | |
| ; CHECK-GI-NEXT: bl rintl | |
| ; CHECK-GI-NEXT: str q0, [sp, #16] // 16-byte Spill | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #256] // 16-byte Reload | |
| ; CHECK-GI-NEXT: bl __fixtfdi | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #240] // 16-byte Reload | |
| ; CHECK-GI-NEXT: str x0, [sp, #256] // 8-byte Spill | |
| ; CHECK-GI-NEXT: bl __fixtfdi | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #224] // 16-byte Reload | |
| ; CHECK-GI-NEXT: str x0, [sp, #272] // 8-byte Spill | |
| ; CHECK-GI-NEXT: bl __fixtfdi | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #208] // 16-byte Reload | |
| ; CHECK-GI-NEXT: str x0, [sp, #240] // 8-byte Spill | |
| ; CHECK-GI-NEXT: bl __fixtfdi | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #192] // 16-byte Reload | |
| ; CHECK-GI-NEXT: str x0, [sp, #224] // 8-byte Spill | |
| ; CHECK-GI-NEXT: bl __fixtfdi | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #176] // 16-byte Reload | |
| ; CHECK-GI-NEXT: mov x24, x0 | |
| ; CHECK-GI-NEXT: bl __fixtfdi | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #160] // 16-byte Reload | |
| ; CHECK-GI-NEXT: mov x23, x0 | |
| ; CHECK-GI-NEXT: bl __fixtfdi | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #144] // 16-byte Reload | |
| ; CHECK-GI-NEXT: mov x25, x0 | |
| ; CHECK-GI-NEXT: bl __fixtfdi | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #128] // 16-byte Reload | |
| ; CHECK-GI-NEXT: mov x26, x0 | |
| ; CHECK-GI-NEXT: bl __fixtfdi | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #112] // 16-byte Reload | |
| ; CHECK-GI-NEXT: mov x27, x0 | |
| ; CHECK-GI-NEXT: bl __fixtfdi | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #96] // 16-byte Reload | |
| ; CHECK-GI-NEXT: mov x28, x0 | |
| ; CHECK-GI-NEXT: bl __fixtfdi | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload | |
| ; CHECK-GI-NEXT: mov x29, x0 | |
| ; CHECK-GI-NEXT: bl __fixtfdi | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload | |
| ; CHECK-GI-NEXT: mov x19, x0 | |
| ; CHECK-GI-NEXT: bl __fixtfdi | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload | |
| ; CHECK-GI-NEXT: mov x20, x0 | |
| ; CHECK-GI-NEXT: bl __fixtfdi | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload | |
| ; CHECK-GI-NEXT: mov x21, x0 | |
| ; CHECK-GI-NEXT: bl __fixtfdi | |
| ; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload | |
| ; CHECK-GI-NEXT: mov x22, x0 | |
| ; CHECK-GI-NEXT: bl __fixtfdi | |
| ; CHECK-GI-NEXT: fmov d2, x24 | |
| ; CHECK-GI-NEXT: fmov d3, x25 | |
| ; CHECK-GI-NEXT: ldr d0, [sp, #256] // 8-byte Reload | |
| ; CHECK-GI-NEXT: fmov d4, x27 | |
| ; CHECK-GI-NEXT: fmov d5, x29 | |
| ; CHECK-GI-NEXT: ldr x8, [sp, #272] // 8-byte Reload | |
| ; CHECK-GI-NEXT: fmov d6, x20 | |
| ; CHECK-GI-NEXT: fmov d7, x22 | |
| ; CHECK-GI-NEXT: ldr d1, [sp, #240] // 8-byte Reload | |
| ; CHECK-GI-NEXT: mov v0.d[1], x8 | |
| ; CHECK-GI-NEXT: ldr x8, [sp, #224] // 8-byte Reload | |
| ; CHECK-GI-NEXT: mov v2.d[1], x23 | |
| ; CHECK-GI-NEXT: mov v3.d[1], x26 | |
| ; CHECK-GI-NEXT: mov v4.d[1], x28 | |
| ; CHECK-GI-NEXT: mov v5.d[1], x19 | |
| ; CHECK-GI-NEXT: mov v6.d[1], x21 | |
| ; CHECK-GI-NEXT: ldp x20, x19, [sp, #368] // 16-byte Folded Reload | |
| ; CHECK-GI-NEXT: ldp x22, x21, [sp, #352] // 16-byte Folded Reload | |
| ; CHECK-GI-NEXT: mov v1.d[1], x8 | |
| ; CHECK-GI-NEXT: ldp x24, x23, [sp, #336] // 16-byte Folded Reload | |
| ; CHECK-GI-NEXT: mov v7.d[1], x0 | |
| ; CHECK-GI-NEXT: ldp x26, x25, [sp, #320] // 16-byte Folded Reload | |
| ; CHECK-GI-NEXT: ldp x28, x27, [sp, #304] // 16-byte Folded Reload | |
| ; CHECK-GI-NEXT: ldp x29, x30, [sp, #288] // 16-byte Folded Reload | |
| ; CHECK-GI-NEXT: add sp, sp, #384 | |
| ; CHECK-GI-NEXT: ret | |
| %a = call <16 x i64> @llvm.llrint.v16i64.v16f128(<16 x fp128> %x) | |
| ret <16 x i64> %a | |
| } | |
| declare <16 x i64> @llvm.llrint.v16i64.v16f128(<16 x fp128>) |